if_pcn.c revision 1.41
1 /* $NetBSD: if_pcn.c,v 1.41 2007/10/19 12:00:47 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.41 2007/10/19 12:00:47 ad Exp $"); 69 70 #include "bpfilter.h" 71 #include "rnd.h" 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/callout.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/ioctl.h> 81 #include <sys/errno.h> 82 #include <sys/device.h> 83 #include <sys/queue.h> 84 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #include <sys/bus.h> 101 #include <sys/intr.h> 102 #include <machine/endian.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/ic/am79900reg.h> 108 #include <dev/ic/lancereg.h> 109 110 #include <dev/pci/pcireg.h> 111 #include <dev/pci/pcivar.h> 112 #include <dev/pci/pcidevs.h> 113 114 #include <dev/pci/if_pcnreg.h> 115 116 /* 117 * Transmit descriptor list size. This is arbitrary, but allocate 118 * enough descriptors for 128 pending transmissions, and 4 segments 119 * per packet. This MUST work out to a power of 2. 120 * 121 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 122 * 123 * So we play a little trick here. We give each packet up to 16 124 * DMA segments, but only allocate the max of 512 descriptors. The 125 * transmit logic can deal with this, we just are hoping to sneak by. 126 */ 127 #define PCN_NTXSEGS 16 128 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 129 130 #define PCN_TXQUEUELEN 128 131 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 132 #define PCN_NTXDESC 512 133 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 134 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 135 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 136 137 /* Tx interrupt every N + 1 packets. */ 138 #define PCN_TXINTR_MASK 7 139 140 /* 141 * Receive descriptor list size. We have one Rx buffer per incoming 142 * packet, so this logic is a little simpler. 143 */ 144 #define PCN_NRXDESC 128 145 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 146 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 147 148 /* 149 * Control structures are DMA'd to the PCnet chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct pcn_control_data { 154 /* The transmit descriptors. */ 155 struct letmd pcd_txdescs[PCN_NTXDESC]; 156 157 /* The receive descriptors. */ 158 struct lermd pcd_rxdescs[PCN_NRXDESC]; 159 160 /* The init block. */ 161 struct leinit pcd_initblock; 162 }; 163 164 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 165 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 166 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 167 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct pcn_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 }; 178 179 /* 180 * Software state for receive jobs. 181 */ 182 struct pcn_rxsoft { 183 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t rxs_dmamap; /* our DMA map */ 185 }; 186 187 /* 188 * Description of Rx FIFO watermarks for various revisions. 189 */ 190 static const char * const pcn_79c970_rcvfw[] = { 191 "16 bytes", 192 "64 bytes", 193 "128 bytes", 194 NULL, 195 }; 196 197 static const char * const pcn_79c971_rcvfw[] = { 198 "16 bytes", 199 "64 bytes", 200 "112 bytes", 201 NULL, 202 }; 203 204 /* 205 * Description of Tx start points for various revisions. 206 */ 207 static const char * const pcn_79c970_xmtsp[] = { 208 "8 bytes", 209 "64 bytes", 210 "128 bytes", 211 "248 bytes", 212 }; 213 214 static const char * const pcn_79c971_xmtsp[] = { 215 "20 bytes", 216 "64 bytes", 217 "128 bytes", 218 "248 bytes", 219 }; 220 221 static const char * const pcn_79c971_xmtsp_sram[] = { 222 "44 bytes", 223 "64 bytes", 224 "128 bytes", 225 "store-and-forward", 226 }; 227 228 /* 229 * Description of Tx FIFO watermarks for various revisions. 230 */ 231 static const char * const pcn_79c970_xmtfw[] = { 232 "16 bytes", 233 "64 bytes", 234 "128 bytes", 235 NULL, 236 }; 237 238 static const char * const pcn_79c971_xmtfw[] = { 239 "16 bytes", 240 "64 bytes", 241 "108 bytes", 242 NULL, 243 }; 244 245 /* 246 * Software state per device. 247 */ 248 struct pcn_softc { 249 struct device sc_dev; /* generic device information */ 250 bus_space_tag_t sc_st; /* bus space tag */ 251 bus_space_handle_t sc_sh; /* bus space handle */ 252 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 253 struct ethercom sc_ethercom; /* Ethernet common data */ 254 void *sc_sdhook; /* shutdown hook */ 255 256 /* Points to our media routines, etc. */ 257 const struct pcn_variant *sc_variant; 258 259 void *sc_ih; /* interrupt cookie */ 260 261 struct mii_data sc_mii; /* MII/media information */ 262 263 callout_t sc_tick_ch; /* tick callout */ 264 265 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 266 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 267 268 /* Software state for transmit and receive descriptors. */ 269 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 270 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 271 272 /* Control data structures */ 273 struct pcn_control_data *sc_control_data; 274 #define sc_txdescs sc_control_data->pcd_txdescs 275 #define sc_rxdescs sc_control_data->pcd_rxdescs 276 #define sc_initblock sc_control_data->pcd_initblock 277 278 #ifdef PCN_EVENT_COUNTERS 279 /* Event counters. */ 280 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 281 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 282 struct evcnt sc_ev_txintr; /* Tx interrupts */ 283 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 284 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 285 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 286 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 287 288 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 289 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 290 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 291 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 292 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 293 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 294 struct evcnt sc_ev_txcopy; /* Tx copies required */ 295 #endif /* PCN_EVENT_COUNTERS */ 296 297 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 298 int sc_rcvfw; 299 300 const char * const *sc_xmtsp_desc; /* Tx start point info */ 301 int sc_xmtsp; 302 303 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 304 int sc_xmtfw; 305 306 int sc_flags; /* misc. flags; see below */ 307 int sc_swstyle; /* the software style in use */ 308 309 int sc_txfree; /* number of free Tx descriptors */ 310 int sc_txnext; /* next ready Tx descriptor */ 311 312 int sc_txsfree; /* number of free Tx jobs */ 313 int sc_txsnext; /* next free Tx job */ 314 int sc_txsdirty; /* dirty Tx jobs */ 315 316 int sc_rxptr; /* next ready Rx descriptor/job */ 317 318 uint32_t sc_csr5; /* prototype CSR5 register */ 319 uint32_t sc_mode; /* prototype MODE register */ 320 321 #if NRND > 0 322 rndsource_element_t rnd_source; /* random source */ 323 #endif 324 }; 325 326 /* sc_flags */ 327 #define PCN_F_HAS_MII 0x0001 /* has MII */ 328 329 #ifdef PCN_EVENT_COUNTERS 330 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 331 #else 332 #define PCN_EVCNT_INCR(ev) /* nothing */ 333 #endif 334 335 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 336 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 337 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 338 339 #define PCN_CDTXSYNC(sc, x, n, ops) \ 340 do { \ 341 int __x, __n; \ 342 \ 343 __x = (x); \ 344 __n = (n); \ 345 \ 346 /* If it will wrap around, sync to the end of the ring. */ \ 347 if ((__x + __n) > PCN_NTXDESC) { \ 348 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 349 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 350 (PCN_NTXDESC - __x), (ops)); \ 351 __n -= (PCN_NTXDESC - __x); \ 352 __x = 0; \ 353 } \ 354 \ 355 /* Now sync whatever is left. */ \ 356 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 357 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 358 } while (/*CONSTCOND*/0) 359 360 #define PCN_CDRXSYNC(sc, x, ops) \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 363 364 #define PCN_CDINITSYNC(sc, ops) \ 365 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 366 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 367 368 #define PCN_INIT_RXDESC(sc, x) \ 369 do { \ 370 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 371 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 372 struct mbuf *__m = __rxs->rxs_mbuf; \ 373 \ 374 /* \ 375 * Note: We scoot the packet forward 2 bytes in the buffer \ 376 * so that the payload after the Ethernet header is aligned \ 377 * to a 4-byte boundary. \ 378 */ \ 379 __m->m_data = __m->m_ext.ext_buf + 2; \ 380 \ 381 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 382 __rmd->rmd2 = \ 383 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 384 __rmd->rmd0 = 0; \ 385 } else { \ 386 __rmd->rmd2 = 0; \ 387 __rmd->rmd0 = \ 388 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 389 } \ 390 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 391 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 392 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 393 } while(/*CONSTCOND*/0) 394 395 static void pcn_start(struct ifnet *); 396 static void pcn_watchdog(struct ifnet *); 397 static int pcn_ioctl(struct ifnet *, u_long, void *); 398 static int pcn_init(struct ifnet *); 399 static void pcn_stop(struct ifnet *, int); 400 401 static void pcn_shutdown(void *); 402 403 static void pcn_reset(struct pcn_softc *); 404 static void pcn_rxdrain(struct pcn_softc *); 405 static int pcn_add_rxbuf(struct pcn_softc *, int); 406 static void pcn_tick(void *); 407 408 static void pcn_spnd(struct pcn_softc *); 409 410 static void pcn_set_filter(struct pcn_softc *); 411 412 static int pcn_intr(void *); 413 static void pcn_txintr(struct pcn_softc *); 414 static int pcn_rxintr(struct pcn_softc *); 415 416 static int pcn_mii_readreg(struct device *, int, int); 417 static void pcn_mii_writereg(struct device *, int, int, int); 418 static void pcn_mii_statchg(struct device *); 419 420 static void pcn_79c970_mediainit(struct pcn_softc *); 421 static int pcn_79c970_mediachange(struct ifnet *); 422 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 423 424 static void pcn_79c971_mediainit(struct pcn_softc *); 425 static int pcn_79c971_mediachange(struct ifnet *); 426 static void pcn_79c971_mediastatus(struct ifnet *, struct ifmediareq *); 427 428 /* 429 * Description of a PCnet-PCI variant. Used to select media access 430 * method, mostly, and to print a nice description of the chip. 431 */ 432 static const struct pcn_variant { 433 const char *pcv_desc; 434 void (*pcv_mediainit)(struct pcn_softc *); 435 uint16_t pcv_chipid; 436 } pcn_variants[] = { 437 { "Am79c970 PCnet-PCI", 438 pcn_79c970_mediainit, 439 PARTID_Am79c970 }, 440 441 { "Am79c970A PCnet-PCI II", 442 pcn_79c970_mediainit, 443 PARTID_Am79c970A }, 444 445 { "Am79c971 PCnet-FAST", 446 pcn_79c971_mediainit, 447 PARTID_Am79c971 }, 448 449 { "Am79c972 PCnet-FAST+", 450 pcn_79c971_mediainit, 451 PARTID_Am79c972 }, 452 453 { "Am79c973 PCnet-FAST III", 454 pcn_79c971_mediainit, 455 PARTID_Am79c973 }, 456 457 { "Am79c975 PCnet-FAST III", 458 pcn_79c971_mediainit, 459 PARTID_Am79c975 }, 460 461 { "Unknown PCnet-PCI variant", 462 pcn_79c971_mediainit, 463 0 }, 464 }; 465 466 int pcn_copy_small = 0; 467 468 static int pcn_match(struct device *, struct cfdata *, void *); 469 static void pcn_attach(struct device *, struct device *, void *); 470 471 CFATTACH_DECL(pcn, sizeof(struct pcn_softc), 472 pcn_match, pcn_attach, NULL, NULL); 473 474 /* 475 * Routines to read and write the PCnet-PCI CSR/BCR space. 476 */ 477 478 static inline uint32_t 479 pcn_csr_read(struct pcn_softc *sc, int reg) 480 { 481 482 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 483 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 484 } 485 486 static inline void 487 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 488 { 489 490 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 491 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 492 } 493 494 static inline uint32_t 495 pcn_bcr_read(struct pcn_softc *sc, int reg) 496 { 497 498 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 499 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 500 } 501 502 static inline void 503 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 504 { 505 506 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 507 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 508 } 509 510 static bool 511 pcn_is_vmware(const char *enaddr) 512 { 513 514 /* 515 * VMware uses the OUI 00:0c:29 for auto-generated MAC 516 * addresses. 517 */ 518 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 519 return (TRUE); 520 521 /* 522 * VMware uses the OUI 00:50:56 for manually-set MAC 523 * addresses (and some auto-generated ones). 524 */ 525 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 526 return (TRUE); 527 528 return (FALSE); 529 } 530 531 static const struct pcn_variant * 532 pcn_lookup_variant(uint16_t chipid) 533 { 534 const struct pcn_variant *pcv; 535 536 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 537 if (chipid == pcv->pcv_chipid) 538 return (pcv); 539 } 540 541 /* 542 * This covers unknown chips, which we simply treat like 543 * a generic PCnet-FAST. 544 */ 545 return (pcv); 546 } 547 548 static int 549 pcn_match(struct device *parent, struct cfdata *cf, void *aux) 550 { 551 struct pci_attach_args *pa = aux; 552 553 /* 554 * IBM Makes a PCI variant of this card which shows up as a 555 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 556 * this card is truly a pcn card, so we have a special case match for 557 * it 558 */ 559 560 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 561 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 562 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 563 return(1); 564 565 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 566 return (0); 567 568 switch (PCI_PRODUCT(pa->pa_id)) { 569 case PCI_PRODUCT_AMD_PCNET_PCI: 570 /* Beat if_le_pci.c */ 571 return (10); 572 } 573 574 return (0); 575 } 576 577 static void 578 pcn_attach(struct device *parent, struct device *self, void *aux) 579 { 580 struct pcn_softc *sc = (struct pcn_softc *) self; 581 struct pci_attach_args *pa = aux; 582 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 583 pci_chipset_tag_t pc = pa->pa_pc; 584 pci_intr_handle_t ih; 585 const char *intrstr = NULL; 586 bus_space_tag_t iot, memt; 587 bus_space_handle_t ioh, memh; 588 bus_dma_segment_t seg; 589 int ioh_valid, memh_valid; 590 int ntxsegs, i, rseg, error; 591 uint32_t chipid, reg; 592 uint8_t enaddr[ETHER_ADDR_LEN]; 593 prop_object_t obj; 594 bool is_vmware; 595 596 callout_init(&sc->sc_tick_ch, 0); 597 598 printf(": AMD PCnet-PCI Ethernet\n"); 599 600 /* 601 * Map the device. 602 */ 603 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 604 &iot, &ioh, NULL, NULL) == 0); 605 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 606 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 607 &memt, &memh, NULL, NULL) == 0); 608 609 if (memh_valid) { 610 sc->sc_st = memt; 611 sc->sc_sh = memh; 612 } else if (ioh_valid) { 613 sc->sc_st = iot; 614 sc->sc_sh = ioh; 615 } else { 616 printf("%s: unable to map device registers\n", 617 sc->sc_dev.dv_xname); 618 return; 619 } 620 621 sc->sc_dmat = pa->pa_dmat; 622 623 /* Make sure bus mastering is enabled. */ 624 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 625 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 626 PCI_COMMAND_MASTER_ENABLE); 627 628 /* power up chip */ 629 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 630 NULL)) && error != EOPNOTSUPP) { 631 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 632 error); 633 return; 634 } 635 636 /* 637 * Reset the chip to a known state. This also puts the 638 * chip into 32-bit mode. 639 */ 640 pcn_reset(sc); 641 642 /* 643 * On some systems with the chip is an on-board device, the 644 * EEPROM is not used. Handle this by reading the MAC address 645 * from the CSRs (assuming that boot firmware has written 646 * it there). 647 */ 648 obj = prop_dictionary_get(device_properties(&sc->sc_dev), 649 "am79c970-no-eeprom"); 650 if (prop_bool_true(obj)) { 651 for (i = 0; i < 3; i++) { 652 uint32_t val; 653 val = pcn_csr_read(sc, LE_CSR12 + i); 654 enaddr[2*i] = val & 0x0ff; 655 enaddr[2*i+1] = (val >> 8) & 0x0ff; 656 } 657 } else { 658 for (i = 0; i < ETHER_ADDR_LEN; i++) { 659 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 660 PCN32_APROM + i); 661 } 662 } 663 664 /* Check to see if this is a VMware emulated network interface. */ 665 is_vmware = pcn_is_vmware(enaddr); 666 667 /* 668 * Now that the device is mapped, attempt to figure out what 669 * kind of chip we have. Note that IDL has all 32 bits of 670 * the chip ID when we're in 32-bit mode. 671 */ 672 chipid = pcn_csr_read(sc, LE_CSR88); 673 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 674 675 printf("%s: %s rev %d, Ethernet address %s\n", 676 sc->sc_dev.dv_xname, sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 677 ether_sprintf(enaddr)); 678 679 /* 680 * VMware has a bug in its network interface emulation; we must 681 * limit the number of Tx segments. 682 */ 683 if (is_vmware) { 684 ntxsegs = PCN_NTXSEGS_VMWARE; 685 prop_dictionary_set_bool(device_properties(&sc->sc_dev), 686 "am79c970-vmware-tx-bug", TRUE); 687 aprint_verbose("%s: VMware Tx segment count bug detected\n", 688 sc->sc_dev.dv_xname); 689 } else { 690 ntxsegs = PCN_NTXSEGS; 691 } 692 693 /* 694 * Map and establish our interrupt. 695 */ 696 if (pci_intr_map(pa, &ih)) { 697 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 698 return; 699 } 700 intrstr = pci_intr_string(pc, ih); 701 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 702 if (sc->sc_ih == NULL) { 703 printf("%s: unable to establish interrupt", 704 sc->sc_dev.dv_xname); 705 if (intrstr != NULL) 706 printf(" at %s", intrstr); 707 printf("\n"); 708 return; 709 } 710 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 711 712 /* 713 * Allocate the control data structures, and create and load the 714 * DMA map for it. 715 */ 716 if ((error = bus_dmamem_alloc(sc->sc_dmat, 717 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 718 0)) != 0) { 719 printf("%s: unable to allocate control data, error = %d\n", 720 sc->sc_dev.dv_xname, error); 721 goto fail_0; 722 } 723 724 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 725 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 726 BUS_DMA_COHERENT)) != 0) { 727 printf("%s: unable to map control data, error = %d\n", 728 sc->sc_dev.dv_xname, error); 729 goto fail_1; 730 } 731 732 if ((error = bus_dmamap_create(sc->sc_dmat, 733 sizeof(struct pcn_control_data), 1, 734 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 735 printf("%s: unable to create control data DMA map, " 736 "error = %d\n", sc->sc_dev.dv_xname, error); 737 goto fail_2; 738 } 739 740 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 741 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 742 0)) != 0) { 743 printf("%s: unable to load control data DMA map, error = %d\n", 744 sc->sc_dev.dv_xname, error); 745 goto fail_3; 746 } 747 748 /* Create the transmit buffer DMA maps. */ 749 for (i = 0; i < PCN_TXQUEUELEN; i++) { 750 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 751 ntxsegs, MCLBYTES, 0, 0, 752 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 753 printf("%s: unable to create tx DMA map %d, " 754 "error = %d\n", sc->sc_dev.dv_xname, i, error); 755 goto fail_4; 756 } 757 } 758 759 /* Create the receive buffer DMA maps. */ 760 for (i = 0; i < PCN_NRXDESC; i++) { 761 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 762 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 763 printf("%s: unable to create rx DMA map %d, " 764 "error = %d\n", sc->sc_dev.dv_xname, i, error); 765 goto fail_5; 766 } 767 sc->sc_rxsoft[i].rxs_mbuf = NULL; 768 } 769 770 /* Initialize our media structures. */ 771 (*sc->sc_variant->pcv_mediainit)(sc); 772 773 /* 774 * Initialize FIFO watermark info. 775 */ 776 switch (sc->sc_variant->pcv_chipid) { 777 case PARTID_Am79c970: 778 case PARTID_Am79c970A: 779 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 780 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 781 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 782 break; 783 784 default: 785 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 786 /* 787 * Read BCR25 to determine how much SRAM is 788 * on the board. If > 0, then we the chip 789 * uses different Start Point thresholds. 790 * 791 * Note BCR25 and BCR26 are loaded from the 792 * EEPROM on RST, and unaffected by S_RESET, 793 * so we don't really have to worry about 794 * them except for this. 795 */ 796 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 797 if (reg != 0) 798 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 799 else 800 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 801 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 802 break; 803 } 804 805 /* 806 * Set up defaults -- see the tables above for what these 807 * values mean. 808 * 809 * XXX How should we tune RCVFW and XMTFW? 810 */ 811 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 812 sc->sc_xmtsp = 1; 813 sc->sc_xmtfw = 0; 814 815 ifp = &sc->sc_ethercom.ec_if; 816 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 817 ifp->if_softc = sc; 818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 819 ifp->if_ioctl = pcn_ioctl; 820 ifp->if_start = pcn_start; 821 ifp->if_watchdog = pcn_watchdog; 822 ifp->if_init = pcn_init; 823 ifp->if_stop = pcn_stop; 824 IFQ_SET_READY(&ifp->if_snd); 825 826 /* Attach the interface. */ 827 if_attach(ifp); 828 ether_ifattach(ifp, enaddr); 829 #if NRND > 0 830 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 831 RND_TYPE_NET, 0); 832 #endif 833 834 #ifdef PCN_EVENT_COUNTERS 835 /* Attach event counters. */ 836 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 837 NULL, sc->sc_dev.dv_xname, "txsstall"); 838 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 839 NULL, sc->sc_dev.dv_xname, "txdstall"); 840 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 841 NULL, sc->sc_dev.dv_xname, "txintr"); 842 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 843 NULL, sc->sc_dev.dv_xname, "rxintr"); 844 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 845 NULL, sc->sc_dev.dv_xname, "babl"); 846 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 847 NULL, sc->sc_dev.dv_xname, "miss"); 848 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 849 NULL, sc->sc_dev.dv_xname, "merr"); 850 851 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 852 NULL, sc->sc_dev.dv_xname, "txseg1"); 853 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 854 NULL, sc->sc_dev.dv_xname, "txseg2"); 855 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 856 NULL, sc->sc_dev.dv_xname, "txseg3"); 857 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 858 NULL, sc->sc_dev.dv_xname, "txseg4"); 859 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 860 NULL, sc->sc_dev.dv_xname, "txseg5"); 861 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 862 NULL, sc->sc_dev.dv_xname, "txsegmore"); 863 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 864 NULL, sc->sc_dev.dv_xname, "txcopy"); 865 #endif /* PCN_EVENT_COUNTERS */ 866 867 /* Make sure the interface is shutdown during reboot. */ 868 sc->sc_sdhook = shutdownhook_establish(pcn_shutdown, sc); 869 if (sc->sc_sdhook == NULL) 870 printf("%s: WARNING: unable to establish shutdown hook\n", 871 sc->sc_dev.dv_xname); 872 return; 873 874 /* 875 * Free any resources we've allocated during the failed attach 876 * attempt. Do this in reverse order and fall through. 877 */ 878 fail_5: 879 for (i = 0; i < PCN_NRXDESC; i++) { 880 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 881 bus_dmamap_destroy(sc->sc_dmat, 882 sc->sc_rxsoft[i].rxs_dmamap); 883 } 884 fail_4: 885 for (i = 0; i < PCN_TXQUEUELEN; i++) { 886 if (sc->sc_txsoft[i].txs_dmamap != NULL) 887 bus_dmamap_destroy(sc->sc_dmat, 888 sc->sc_txsoft[i].txs_dmamap); 889 } 890 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 891 fail_3: 892 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 893 fail_2: 894 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 895 sizeof(struct pcn_control_data)); 896 fail_1: 897 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 898 fail_0: 899 return; 900 } 901 902 /* 903 * pcn_shutdown: 904 * 905 * Make sure the interface is stopped at reboot time. 906 */ 907 static void 908 pcn_shutdown(void *arg) 909 { 910 struct pcn_softc *sc = arg; 911 912 pcn_stop(&sc->sc_ethercom.ec_if, 1); 913 /* explicitly reset the chip for some onboard one with lazy firmware */ 914 pcn_reset(sc); 915 } 916 917 /* 918 * pcn_start: [ifnet interface function] 919 * 920 * Start packet transmission on the interface. 921 */ 922 static void 923 pcn_start(struct ifnet *ifp) 924 { 925 struct pcn_softc *sc = ifp->if_softc; 926 struct mbuf *m0, *m; 927 struct pcn_txsoft *txs; 928 bus_dmamap_t dmamap; 929 int error, nexttx, lasttx = -1, ofree, seg; 930 931 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 932 return; 933 934 /* 935 * Remember the previous number of free descriptors and 936 * the first descriptor we'll use. 937 */ 938 ofree = sc->sc_txfree; 939 940 /* 941 * Loop through the send queue, setting up transmit descriptors 942 * until we drain the queue, or use up all available transmit 943 * descriptors. 944 */ 945 for (;;) { 946 /* Grab a packet off the queue. */ 947 IFQ_POLL(&ifp->if_snd, m0); 948 if (m0 == NULL) 949 break; 950 m = NULL; 951 952 /* Get a work queue entry. */ 953 if (sc->sc_txsfree == 0) { 954 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 955 break; 956 } 957 958 txs = &sc->sc_txsoft[sc->sc_txsnext]; 959 dmamap = txs->txs_dmamap; 960 961 /* 962 * Load the DMA map. If this fails, the packet either 963 * didn't fit in the alloted number of segments, or we 964 * were short on resources. In this case, we'll copy 965 * and try again. 966 */ 967 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 968 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 969 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 970 MGETHDR(m, M_DONTWAIT, MT_DATA); 971 if (m == NULL) { 972 printf("%s: unable to allocate Tx mbuf\n", 973 sc->sc_dev.dv_xname); 974 break; 975 } 976 if (m0->m_pkthdr.len > MHLEN) { 977 MCLGET(m, M_DONTWAIT); 978 if ((m->m_flags & M_EXT) == 0) { 979 printf("%s: unable to allocate Tx " 980 "cluster\n", sc->sc_dev.dv_xname); 981 m_freem(m); 982 break; 983 } 984 } 985 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 986 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 987 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 988 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 989 if (error) { 990 printf("%s: unable to load Tx buffer, " 991 "error = %d\n", sc->sc_dev.dv_xname, error); 992 break; 993 } 994 } 995 996 /* 997 * Ensure we have enough descriptors free to describe 998 * the packet. Note, we always reserve one descriptor 999 * at the end of the ring as a termination point, to 1000 * prevent wrap-around. 1001 */ 1002 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1003 /* 1004 * Not enough free descriptors to transmit this 1005 * packet. We haven't committed anything yet, 1006 * so just unload the DMA map, put the packet 1007 * back on the queue, and punt. Notify the upper 1008 * layer that there are not more slots left. 1009 * 1010 * XXX We could allocate an mbuf and copy, but 1011 * XXX is it worth it? 1012 */ 1013 ifp->if_flags |= IFF_OACTIVE; 1014 bus_dmamap_unload(sc->sc_dmat, dmamap); 1015 if (m != NULL) 1016 m_freem(m); 1017 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1018 break; 1019 } 1020 1021 IFQ_DEQUEUE(&ifp->if_snd, m0); 1022 if (m != NULL) { 1023 m_freem(m0); 1024 m0 = m; 1025 } 1026 1027 /* 1028 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1029 */ 1030 1031 /* Sync the DMA map. */ 1032 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1033 BUS_DMASYNC_PREWRITE); 1034 1035 #ifdef PCN_EVENT_COUNTERS 1036 switch (dmamap->dm_nsegs) { 1037 case 1: 1038 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1039 break; 1040 case 2: 1041 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1042 break; 1043 case 3: 1044 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1045 break; 1046 case 4: 1047 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1048 break; 1049 case 5: 1050 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1051 break; 1052 default: 1053 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1054 break; 1055 } 1056 #endif /* PCN_EVENT_COUNTERS */ 1057 1058 /* 1059 * Initialize the transmit descriptors. 1060 */ 1061 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1062 for (nexttx = sc->sc_txnext, seg = 0; 1063 seg < dmamap->dm_nsegs; 1064 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1065 /* 1066 * If this is the first descriptor we're 1067 * enqueueing, don't set the OWN bit just 1068 * yet. That could cause a race condition. 1069 * We'll do it below. 1070 */ 1071 sc->sc_txdescs[nexttx].tmd0 = 0; 1072 sc->sc_txdescs[nexttx].tmd2 = 1073 htole32(dmamap->dm_segs[seg].ds_addr); 1074 sc->sc_txdescs[nexttx].tmd1 = 1075 htole32(LE_T1_ONES | 1076 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1077 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1078 LE_T1_BCNT_MASK)); 1079 lasttx = nexttx; 1080 } 1081 } else { 1082 for (nexttx = sc->sc_txnext, seg = 0; 1083 seg < dmamap->dm_nsegs; 1084 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1085 /* 1086 * If this is the first descriptor we're 1087 * enqueueing, don't set the OWN bit just 1088 * yet. That could cause a race condition. 1089 * We'll do it below. 1090 */ 1091 sc->sc_txdescs[nexttx].tmd0 = 1092 htole32(dmamap->dm_segs[seg].ds_addr); 1093 sc->sc_txdescs[nexttx].tmd2 = 0; 1094 sc->sc_txdescs[nexttx].tmd1 = 1095 htole32(LE_T1_ONES | 1096 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1097 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1098 LE_T1_BCNT_MASK)); 1099 lasttx = nexttx; 1100 } 1101 } 1102 1103 KASSERT(lasttx != -1); 1104 /* Interrupt on the packet, if appropriate. */ 1105 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1106 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1107 1108 /* Set `start of packet' and `end of packet' appropriately. */ 1109 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1110 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1111 htole32(LE_T1_OWN|LE_T1_STP); 1112 1113 /* Sync the descriptors we're using. */ 1114 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1116 1117 /* Kick the transmitter. */ 1118 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1119 1120 /* 1121 * Store a pointer to the packet so we can free it later, 1122 * and remember what txdirty will be once the packet is 1123 * done. 1124 */ 1125 txs->txs_mbuf = m0; 1126 txs->txs_firstdesc = sc->sc_txnext; 1127 txs->txs_lastdesc = lasttx; 1128 1129 /* Advance the tx pointer. */ 1130 sc->sc_txfree -= dmamap->dm_nsegs; 1131 sc->sc_txnext = nexttx; 1132 1133 sc->sc_txsfree--; 1134 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1135 1136 #if NBPFILTER > 0 1137 /* Pass the packet to any BPF listeners. */ 1138 if (ifp->if_bpf) 1139 bpf_mtap(ifp->if_bpf, m0); 1140 #endif /* NBPFILTER > 0 */ 1141 } 1142 1143 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1144 /* No more slots left; notify upper layer. */ 1145 ifp->if_flags |= IFF_OACTIVE; 1146 } 1147 1148 if (sc->sc_txfree != ofree) { 1149 /* Set a watchdog timer in case the chip flakes out. */ 1150 ifp->if_timer = 5; 1151 } 1152 } 1153 1154 /* 1155 * pcn_watchdog: [ifnet interface function] 1156 * 1157 * Watchdog timer handler. 1158 */ 1159 static void 1160 pcn_watchdog(struct ifnet *ifp) 1161 { 1162 struct pcn_softc *sc = ifp->if_softc; 1163 1164 /* 1165 * Since we're not interrupting every packet, sweep 1166 * up before we report an error. 1167 */ 1168 pcn_txintr(sc); 1169 1170 if (sc->sc_txfree != PCN_NTXDESC) { 1171 printf("%s: device timeout (txfree %d txsfree %d)\n", 1172 sc->sc_dev.dv_xname, sc->sc_txfree, sc->sc_txsfree); 1173 ifp->if_oerrors++; 1174 1175 /* Reset the interface. */ 1176 (void) pcn_init(ifp); 1177 } 1178 1179 /* Try to get more packets going. */ 1180 pcn_start(ifp); 1181 } 1182 1183 /* 1184 * pcn_ioctl: [ifnet interface function] 1185 * 1186 * Handle control requests from the operator. 1187 */ 1188 static int 1189 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1190 { 1191 struct pcn_softc *sc = ifp->if_softc; 1192 struct ifreq *ifr = (struct ifreq *) data; 1193 int s, error; 1194 1195 s = splnet(); 1196 1197 switch (cmd) { 1198 case SIOCSIFMEDIA: 1199 case SIOCGIFMEDIA: 1200 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1201 break; 1202 1203 default: 1204 error = ether_ioctl(ifp, cmd, data); 1205 if (error == ENETRESET) { 1206 /* 1207 * Multicast list has changed; set the hardware filter 1208 * accordingly. 1209 */ 1210 if (ifp->if_flags & IFF_RUNNING) 1211 error = pcn_init(ifp); 1212 else 1213 error = 0; 1214 } 1215 break; 1216 } 1217 1218 /* Try to get more packets going. */ 1219 pcn_start(ifp); 1220 1221 splx(s); 1222 return (error); 1223 } 1224 1225 /* 1226 * pcn_intr: 1227 * 1228 * Interrupt service routine. 1229 */ 1230 static int 1231 pcn_intr(void *arg) 1232 { 1233 struct pcn_softc *sc = arg; 1234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1235 uint32_t csr0; 1236 int wantinit, handled = 0; 1237 1238 for (wantinit = 0; wantinit == 0;) { 1239 csr0 = pcn_csr_read(sc, LE_CSR0); 1240 if ((csr0 & LE_C0_INTR) == 0) 1241 break; 1242 1243 #if NRND > 0 1244 if (RND_ENABLED(&sc->rnd_source)) 1245 rnd_add_uint32(&sc->rnd_source, csr0); 1246 #endif 1247 1248 /* ACK the bits and re-enable interrupts. */ 1249 pcn_csr_write(sc, LE_CSR0, csr0 & 1250 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1251 LE_C0_TINT|LE_C0_IDON)); 1252 1253 handled = 1; 1254 1255 if (csr0 & LE_C0_RINT) { 1256 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1257 wantinit = pcn_rxintr(sc); 1258 } 1259 1260 if (csr0 & LE_C0_TINT) { 1261 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1262 pcn_txintr(sc); 1263 } 1264 1265 if (csr0 & LE_C0_ERR) { 1266 if (csr0 & LE_C0_BABL) { 1267 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1268 ifp->if_oerrors++; 1269 } 1270 if (csr0 & LE_C0_MISS) { 1271 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1272 ifp->if_ierrors++; 1273 } 1274 if (csr0 & LE_C0_MERR) { 1275 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1276 printf("%s: memory error\n", 1277 sc->sc_dev.dv_xname); 1278 wantinit = 1; 1279 break; 1280 } 1281 } 1282 1283 if ((csr0 & LE_C0_RXON) == 0) { 1284 printf("%s: receiver disabled\n", 1285 sc->sc_dev.dv_xname); 1286 ifp->if_ierrors++; 1287 wantinit = 1; 1288 } 1289 1290 if ((csr0 & LE_C0_TXON) == 0) { 1291 printf("%s: transmitter disabled\n", 1292 sc->sc_dev.dv_xname); 1293 ifp->if_oerrors++; 1294 wantinit = 1; 1295 } 1296 } 1297 1298 if (handled) { 1299 if (wantinit) 1300 pcn_init(ifp); 1301 1302 /* Try to get more packets going. */ 1303 pcn_start(ifp); 1304 } 1305 1306 return (handled); 1307 } 1308 1309 /* 1310 * pcn_spnd: 1311 * 1312 * Suspend the chip. 1313 */ 1314 static void 1315 pcn_spnd(struct pcn_softc *sc) 1316 { 1317 int i; 1318 1319 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1320 1321 for (i = 0; i < 10000; i++) { 1322 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1323 return; 1324 delay(5); 1325 } 1326 1327 printf("%s: WARNING: chip failed to enter suspended state\n", 1328 sc->sc_dev.dv_xname); 1329 } 1330 1331 /* 1332 * pcn_txintr: 1333 * 1334 * Helper; handle transmit interrupts. 1335 */ 1336 static void 1337 pcn_txintr(struct pcn_softc *sc) 1338 { 1339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1340 struct pcn_txsoft *txs; 1341 uint32_t tmd1, tmd2, tmd; 1342 int i, j; 1343 1344 ifp->if_flags &= ~IFF_OACTIVE; 1345 1346 /* 1347 * Go through our Tx list and free mbufs for those 1348 * frames which have been transmitted. 1349 */ 1350 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1351 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1352 txs = &sc->sc_txsoft[i]; 1353 1354 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1355 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1356 1357 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1358 if (tmd1 & LE_T1_OWN) 1359 break; 1360 1361 /* 1362 * Slightly annoying -- we have to loop through the 1363 * descriptors we've used looking for ERR, since it 1364 * can appear on any descriptor in the chain. 1365 */ 1366 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1367 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1368 if (tmd & LE_T1_ERR) { 1369 ifp->if_oerrors++; 1370 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1371 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1372 else 1373 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1374 if (tmd2 & LE_T2_UFLO) { 1375 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1376 sc->sc_xmtsp++; 1377 printf("%s: transmit " 1378 "underrun; new threshold: " 1379 "%s\n", 1380 sc->sc_dev.dv_xname, 1381 sc->sc_xmtsp_desc[ 1382 sc->sc_xmtsp]); 1383 pcn_spnd(sc); 1384 pcn_csr_write(sc, LE_CSR80, 1385 LE_C80_RCVFW(sc->sc_rcvfw) | 1386 LE_C80_XMTSP(sc->sc_xmtsp) | 1387 LE_C80_XMTFW(sc->sc_xmtfw)); 1388 pcn_csr_write(sc, LE_CSR5, 1389 sc->sc_csr5); 1390 } else { 1391 printf("%s: transmit " 1392 "underrun\n", 1393 sc->sc_dev.dv_xname); 1394 } 1395 } else if (tmd2 & LE_T2_BUFF) { 1396 printf("%s: transmit buffer error\n", 1397 sc->sc_dev.dv_xname); 1398 } 1399 if (tmd2 & LE_T2_LCOL) 1400 ifp->if_collisions++; 1401 if (tmd2 & LE_T2_RTRY) 1402 ifp->if_collisions += 16; 1403 goto next_packet; 1404 } 1405 if (j == txs->txs_lastdesc) 1406 break; 1407 } 1408 if (tmd1 & LE_T1_ONE) 1409 ifp->if_collisions++; 1410 else if (tmd & LE_T1_MORE) { 1411 /* Real number is unknown. */ 1412 ifp->if_collisions += 2; 1413 } 1414 ifp->if_opackets++; 1415 next_packet: 1416 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1417 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1418 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1419 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1420 m_freem(txs->txs_mbuf); 1421 txs->txs_mbuf = NULL; 1422 } 1423 1424 /* Update the dirty transmit buffer pointer. */ 1425 sc->sc_txsdirty = i; 1426 1427 /* 1428 * If there are no more pending transmissions, cancel the watchdog 1429 * timer. 1430 */ 1431 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1432 ifp->if_timer = 0; 1433 } 1434 1435 /* 1436 * pcn_rxintr: 1437 * 1438 * Helper; handle receive interrupts. 1439 */ 1440 static int 1441 pcn_rxintr(struct pcn_softc *sc) 1442 { 1443 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1444 struct pcn_rxsoft *rxs; 1445 struct mbuf *m; 1446 uint32_t rmd1; 1447 int i, len; 1448 1449 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1450 rxs = &sc->sc_rxsoft[i]; 1451 1452 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1453 1454 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1455 1456 if (rmd1 & LE_R1_OWN) 1457 break; 1458 1459 /* 1460 * Check for errors and make sure the packet fit into 1461 * a single buffer. We have structured this block of 1462 * code the way it is in order to compress it into 1463 * one test in the common case (no error). 1464 */ 1465 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1466 (LE_R1_STP|LE_R1_ENP))) { 1467 /* Make sure the packet is in a single buffer. */ 1468 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1469 (LE_R1_STP|LE_R1_ENP)) { 1470 printf("%s: packet spilled into next buffer\n", 1471 sc->sc_dev.dv_xname); 1472 return (1); /* pcn_intr() will re-init */ 1473 } 1474 1475 /* 1476 * If the packet had an error, simple recycle the 1477 * buffer. 1478 */ 1479 if (rmd1 & LE_R1_ERR) { 1480 ifp->if_ierrors++; 1481 /* 1482 * If we got an overflow error, chances 1483 * are there will be a CRC error. In 1484 * this case, just print the overflow 1485 * error, and skip the others. 1486 */ 1487 if (rmd1 & LE_R1_OFLO) 1488 printf("%s: overflow error\n", 1489 sc->sc_dev.dv_xname); 1490 else { 1491 #define PRINTIT(x, str) \ 1492 if (rmd1 & (x)) \ 1493 printf("%s: %s\n", \ 1494 sc->sc_dev.dv_xname, str); 1495 PRINTIT(LE_R1_FRAM, "framing error"); 1496 PRINTIT(LE_R1_CRC, "CRC error"); 1497 PRINTIT(LE_R1_BUFF, "buffer error"); 1498 } 1499 #undef PRINTIT 1500 PCN_INIT_RXDESC(sc, i); 1501 continue; 1502 } 1503 } 1504 1505 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1506 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1507 1508 /* 1509 * No errors; receive the packet. 1510 */ 1511 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1512 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1513 else 1514 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1515 1516 /* 1517 * The LANCE family includes the CRC with every packet; 1518 * trim it off here. 1519 */ 1520 len -= ETHER_CRC_LEN; 1521 1522 /* 1523 * If the packet is small enough to fit in a 1524 * single header mbuf, allocate one and copy 1525 * the data into it. This greatly reduces 1526 * memory consumption when we receive lots 1527 * of small packets. 1528 * 1529 * Otherwise, we add a new buffer to the receive 1530 * chain. If this fails, we drop the packet and 1531 * recycle the old buffer. 1532 */ 1533 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1534 MGETHDR(m, M_DONTWAIT, MT_DATA); 1535 if (m == NULL) 1536 goto dropit; 1537 m->m_data += 2; 1538 memcpy(mtod(m, void *), 1539 mtod(rxs->rxs_mbuf, void *), len); 1540 PCN_INIT_RXDESC(sc, i); 1541 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1542 rxs->rxs_dmamap->dm_mapsize, 1543 BUS_DMASYNC_PREREAD); 1544 } else { 1545 m = rxs->rxs_mbuf; 1546 if (pcn_add_rxbuf(sc, i) != 0) { 1547 dropit: 1548 ifp->if_ierrors++; 1549 PCN_INIT_RXDESC(sc, i); 1550 bus_dmamap_sync(sc->sc_dmat, 1551 rxs->rxs_dmamap, 0, 1552 rxs->rxs_dmamap->dm_mapsize, 1553 BUS_DMASYNC_PREREAD); 1554 continue; 1555 } 1556 } 1557 1558 m->m_pkthdr.rcvif = ifp; 1559 m->m_pkthdr.len = m->m_len = len; 1560 1561 #if NBPFILTER > 0 1562 /* Pass this up to any BPF listeners. */ 1563 if (ifp->if_bpf) 1564 bpf_mtap(ifp->if_bpf, m); 1565 #endif /* NBPFILTER > 0 */ 1566 1567 /* Pass it on. */ 1568 (*ifp->if_input)(ifp, m); 1569 ifp->if_ipackets++; 1570 } 1571 1572 /* Update the receive pointer. */ 1573 sc->sc_rxptr = i; 1574 return (0); 1575 } 1576 1577 /* 1578 * pcn_tick: 1579 * 1580 * One second timer, used to tick the MII. 1581 */ 1582 static void 1583 pcn_tick(void *arg) 1584 { 1585 struct pcn_softc *sc = arg; 1586 int s; 1587 1588 s = splnet(); 1589 mii_tick(&sc->sc_mii); 1590 splx(s); 1591 1592 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1593 } 1594 1595 /* 1596 * pcn_reset: 1597 * 1598 * Perform a soft reset on the PCnet-PCI. 1599 */ 1600 static void 1601 pcn_reset(struct pcn_softc *sc) 1602 { 1603 1604 /* 1605 * The PCnet-PCI chip is reset by reading from the 1606 * RESET register. Note that while the NE2100 LANCE 1607 * boards require a write after the read, the PCnet-PCI 1608 * chips do not require this. 1609 * 1610 * Since we don't know if we're in 16-bit or 32-bit 1611 * mode right now, issue both (it's safe) in the 1612 * hopes that one will succeed. 1613 */ 1614 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1615 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1616 1617 /* Wait 1ms for it to finish. */ 1618 delay(1000); 1619 1620 /* 1621 * Select 32-bit I/O mode by issuing a 32-bit write to the 1622 * RDP. Since the RAP is 0 after a reset, writing a 0 1623 * to RDP is safe (since it simply clears CSR0). 1624 */ 1625 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1626 } 1627 1628 /* 1629 * pcn_init: [ifnet interface function] 1630 * 1631 * Initialize the interface. Must be called at splnet(). 1632 */ 1633 static int 1634 pcn_init(struct ifnet *ifp) 1635 { 1636 struct pcn_softc *sc = ifp->if_softc; 1637 struct pcn_rxsoft *rxs; 1638 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1639 int i, error = 0; 1640 uint32_t reg; 1641 1642 /* Cancel any pending I/O. */ 1643 pcn_stop(ifp, 0); 1644 1645 /* Reset the chip to a known state. */ 1646 pcn_reset(sc); 1647 1648 /* 1649 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1650 * else. 1651 * 1652 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1653 * because the structure layout is compatible with ILACC, 1654 * but the burst mode is only available in SSTYLE 3, and 1655 * burst mode should provide some performance enhancement. 1656 */ 1657 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1658 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1659 else 1660 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1661 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1662 1663 /* Initialize the transmit descriptor ring. */ 1664 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1665 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1667 sc->sc_txfree = PCN_NTXDESC; 1668 sc->sc_txnext = 0; 1669 1670 /* Initialize the transmit job descriptors. */ 1671 for (i = 0; i < PCN_TXQUEUELEN; i++) 1672 sc->sc_txsoft[i].txs_mbuf = NULL; 1673 sc->sc_txsfree = PCN_TXQUEUELEN; 1674 sc->sc_txsnext = 0; 1675 sc->sc_txsdirty = 0; 1676 1677 /* 1678 * Initialize the receive descriptor and receive job 1679 * descriptor rings. 1680 */ 1681 for (i = 0; i < PCN_NRXDESC; i++) { 1682 rxs = &sc->sc_rxsoft[i]; 1683 if (rxs->rxs_mbuf == NULL) { 1684 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1685 printf("%s: unable to allocate or map rx " 1686 "buffer %d, error = %d\n", 1687 sc->sc_dev.dv_xname, i, error); 1688 /* 1689 * XXX Should attempt to run with fewer receive 1690 * XXX buffers instead of just failing. 1691 */ 1692 pcn_rxdrain(sc); 1693 goto out; 1694 } 1695 } else 1696 PCN_INIT_RXDESC(sc, i); 1697 } 1698 sc->sc_rxptr = 0; 1699 1700 /* Initialize MODE for the initialization block. */ 1701 sc->sc_mode = 0; 1702 if (ifp->if_flags & IFF_PROMISC) 1703 sc->sc_mode |= LE_C15_PROM; 1704 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1705 sc->sc_mode |= LE_C15_DRCVBC; 1706 1707 /* 1708 * If we have MII, simply select MII in the MODE register, 1709 * and clear ASEL. Otherwise, let ASEL stand (for now), 1710 * and leave PORTSEL alone (it is ignored with ASEL is set). 1711 */ 1712 if (sc->sc_flags & PCN_F_HAS_MII) { 1713 pcn_bcr_write(sc, LE_BCR2, 1714 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1715 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1716 1717 /* 1718 * Disable MII auto-negotiation. We handle that in 1719 * our own MII layer. 1720 */ 1721 pcn_bcr_write(sc, LE_BCR32, 1722 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1723 } 1724 1725 /* 1726 * Set the Tx and Rx descriptor ring addresses in the init 1727 * block, the TLEN and RLEN other fields of the init block 1728 * MODE register. 1729 */ 1730 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1731 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1732 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1733 ((ffs(PCN_NTXDESC) - 1) << 28) | 1734 ((ffs(PCN_NRXDESC) - 1) << 20)); 1735 1736 /* Set the station address in the init block. */ 1737 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1738 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1739 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1740 (enaddr[5] << 8)); 1741 1742 /* Set the multicast filter in the init block. */ 1743 pcn_set_filter(sc); 1744 1745 /* Initialize CSR3. */ 1746 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1747 1748 /* Initialize CSR4. */ 1749 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1750 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1751 1752 /* Initialize CSR5. */ 1753 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1754 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1755 1756 /* 1757 * If we have an Am79c971 or greater, initialize CSR7. 1758 * 1759 * XXX Might be nice to use the MII auto-poll interrupt someday. 1760 */ 1761 switch (sc->sc_variant->pcv_chipid) { 1762 case PARTID_Am79c970: 1763 case PARTID_Am79c970A: 1764 /* Not available on these chips. */ 1765 break; 1766 1767 default: 1768 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1769 break; 1770 } 1771 1772 /* 1773 * On the Am79c970A and greater, initialize BCR18 to 1774 * enable burst mode. 1775 * 1776 * Also enable the "no underflow" option on the Am79c971 and 1777 * higher, which prevents the chip from generating transmit 1778 * underflows, yet sill provides decent performance. Note if 1779 * chip is not connected to external SRAM, then we still have 1780 * to handle underflow errors (the NOUFLO bit is ignored in 1781 * that case). 1782 */ 1783 reg = pcn_bcr_read(sc, LE_BCR18); 1784 switch (sc->sc_variant->pcv_chipid) { 1785 case PARTID_Am79c970: 1786 break; 1787 1788 case PARTID_Am79c970A: 1789 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1790 break; 1791 1792 default: 1793 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1794 break; 1795 } 1796 pcn_bcr_write(sc, LE_BCR18, reg); 1797 1798 /* 1799 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1800 */ 1801 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1802 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1803 1804 /* 1805 * Send the init block to the chip, and wait for it 1806 * to be processed. 1807 */ 1808 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1809 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1810 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1811 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1812 delay(100); 1813 for (i = 0; i < 10000; i++) { 1814 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1815 break; 1816 delay(10); 1817 } 1818 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1819 if (i == 10000) { 1820 printf("%s: timeout processing init block\n", 1821 sc->sc_dev.dv_xname); 1822 error = EIO; 1823 goto out; 1824 } 1825 1826 /* Set the media. */ 1827 (void) (*sc->sc_mii.mii_media.ifm_change)(ifp); 1828 1829 /* Enable interrupts and external activity (and ACK IDON). */ 1830 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1831 1832 if (sc->sc_flags & PCN_F_HAS_MII) { 1833 /* Start the one second MII clock. */ 1834 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1835 } 1836 1837 /* ...all done! */ 1838 ifp->if_flags |= IFF_RUNNING; 1839 ifp->if_flags &= ~IFF_OACTIVE; 1840 1841 out: 1842 if (error) 1843 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1844 return (error); 1845 } 1846 1847 /* 1848 * pcn_rxdrain: 1849 * 1850 * Drain the receive queue. 1851 */ 1852 static void 1853 pcn_rxdrain(struct pcn_softc *sc) 1854 { 1855 struct pcn_rxsoft *rxs; 1856 int i; 1857 1858 for (i = 0; i < PCN_NRXDESC; i++) { 1859 rxs = &sc->sc_rxsoft[i]; 1860 if (rxs->rxs_mbuf != NULL) { 1861 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1862 m_freem(rxs->rxs_mbuf); 1863 rxs->rxs_mbuf = NULL; 1864 } 1865 } 1866 } 1867 1868 /* 1869 * pcn_stop: [ifnet interface function] 1870 * 1871 * Stop transmission on the interface. 1872 */ 1873 static void 1874 pcn_stop(struct ifnet *ifp, int disable) 1875 { 1876 struct pcn_softc *sc = ifp->if_softc; 1877 struct pcn_txsoft *txs; 1878 int i; 1879 1880 if (sc->sc_flags & PCN_F_HAS_MII) { 1881 /* Stop the one second clock. */ 1882 callout_stop(&sc->sc_tick_ch); 1883 1884 /* Down the MII. */ 1885 mii_down(&sc->sc_mii); 1886 } 1887 1888 /* Stop the chip. */ 1889 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1890 1891 /* Release any queued transmit buffers. */ 1892 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1893 txs = &sc->sc_txsoft[i]; 1894 if (txs->txs_mbuf != NULL) { 1895 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1896 m_freem(txs->txs_mbuf); 1897 txs->txs_mbuf = NULL; 1898 } 1899 } 1900 1901 if (disable) 1902 pcn_rxdrain(sc); 1903 1904 /* Mark the interface as down and cancel the watchdog timer. */ 1905 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1906 ifp->if_timer = 0; 1907 } 1908 1909 /* 1910 * pcn_add_rxbuf: 1911 * 1912 * Add a receive buffer to the indicated descriptor. 1913 */ 1914 static int 1915 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1916 { 1917 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1918 struct mbuf *m; 1919 int error; 1920 1921 MGETHDR(m, M_DONTWAIT, MT_DATA); 1922 if (m == NULL) 1923 return (ENOBUFS); 1924 1925 MCLGET(m, M_DONTWAIT); 1926 if ((m->m_flags & M_EXT) == 0) { 1927 m_freem(m); 1928 return (ENOBUFS); 1929 } 1930 1931 if (rxs->rxs_mbuf != NULL) 1932 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1933 1934 rxs->rxs_mbuf = m; 1935 1936 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1937 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1938 BUS_DMA_READ|BUS_DMA_NOWAIT); 1939 if (error) { 1940 printf("%s: can't load rx DMA map %d, error = %d\n", 1941 sc->sc_dev.dv_xname, idx, error); 1942 panic("pcn_add_rxbuf"); 1943 } 1944 1945 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1946 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1947 1948 PCN_INIT_RXDESC(sc, idx); 1949 1950 return (0); 1951 } 1952 1953 /* 1954 * pcn_set_filter: 1955 * 1956 * Set up the receive filter. 1957 */ 1958 static void 1959 pcn_set_filter(struct pcn_softc *sc) 1960 { 1961 struct ethercom *ec = &sc->sc_ethercom; 1962 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1963 struct ether_multi *enm; 1964 struct ether_multistep step; 1965 uint32_t crc; 1966 1967 /* 1968 * Set up the multicast address filter by passing all multicast 1969 * addresses through a CRC generator, and then using the high 1970 * order 6 bits as an index into the 64-bit logical address 1971 * filter. The high order bits select the word, while the rest 1972 * of the bits select the bit within the word. 1973 */ 1974 1975 if (ifp->if_flags & IFF_PROMISC) 1976 goto allmulti; 1977 1978 sc->sc_initblock.init_ladrf[0] = 1979 sc->sc_initblock.init_ladrf[1] = 1980 sc->sc_initblock.init_ladrf[2] = 1981 sc->sc_initblock.init_ladrf[3] = 0; 1982 1983 ETHER_FIRST_MULTI(step, ec, enm); 1984 while (enm != NULL) { 1985 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1986 /* 1987 * We must listen to a range of multicast addresses. 1988 * For now, just accept all multicasts, rather than 1989 * trying to set only those filter bits needed to match 1990 * the range. (At this time, the only use of address 1991 * ranges is for IP multicast routing, for which the 1992 * range is big enough to require all bits set.) 1993 */ 1994 goto allmulti; 1995 } 1996 1997 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1998 1999 /* Just want the 6 most significant bits. */ 2000 crc >>= 26; 2001 2002 /* Set the corresponding bit in the filter. */ 2003 sc->sc_initblock.init_ladrf[crc >> 4] |= 2004 htole16(1 << (crc & 0xf)); 2005 2006 ETHER_NEXT_MULTI(step, enm); 2007 } 2008 2009 ifp->if_flags &= ~IFF_ALLMULTI; 2010 return; 2011 2012 allmulti: 2013 ifp->if_flags |= IFF_ALLMULTI; 2014 sc->sc_initblock.init_ladrf[0] = 2015 sc->sc_initblock.init_ladrf[1] = 2016 sc->sc_initblock.init_ladrf[2] = 2017 sc->sc_initblock.init_ladrf[3] = 0xffff; 2018 } 2019 2020 /* 2021 * pcn_79c970_mediainit: 2022 * 2023 * Initialize media for the Am79c970. 2024 */ 2025 static void 2026 pcn_79c970_mediainit(struct pcn_softc *sc) 2027 { 2028 const char *sep = ""; 2029 2030 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2031 pcn_79c970_mediastatus); 2032 2033 #define ADD(str, m, d) \ 2034 do { \ 2035 printf("%s%s", sep, str); \ 2036 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2037 sep = ", "; \ 2038 } while (/*CONSTCOND*/0) 2039 2040 printf("%s: ", sc->sc_dev.dv_xname); 2041 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2042 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2043 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2044 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2045 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2046 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2047 ADD("auto", IFM_AUTO, 0); 2048 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2049 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2050 printf("\n"); 2051 2052 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2053 } 2054 2055 /* 2056 * pcn_79c970_mediastatus: [ifmedia interface function] 2057 * 2058 * Get the current interface media status (Am79c970 version). 2059 */ 2060 static void 2061 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2062 { 2063 struct pcn_softc *sc = ifp->if_softc; 2064 2065 /* 2066 * The currently selected media is always the active media. 2067 * Note: We have no way to determine what media the AUTO 2068 * process picked. 2069 */ 2070 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2071 } 2072 2073 /* 2074 * pcn_79c970_mediachange: [ifmedia interface function] 2075 * 2076 * Set hardware to newly-selected media (Am79c970 version). 2077 */ 2078 static int 2079 pcn_79c970_mediachange(struct ifnet *ifp) 2080 { 2081 struct pcn_softc *sc = ifp->if_softc; 2082 uint32_t reg; 2083 2084 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2085 /* 2086 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2087 */ 2088 reg = pcn_bcr_read(sc, LE_BCR2); 2089 reg |= LE_B2_ASEL; 2090 pcn_bcr_write(sc, LE_BCR2, reg); 2091 } else { 2092 /* 2093 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2094 */ 2095 reg = pcn_bcr_read(sc, LE_BCR2); 2096 reg &= ~LE_B2_ASEL; 2097 pcn_bcr_write(sc, LE_BCR2, reg); 2098 2099 reg = pcn_csr_read(sc, LE_CSR15); 2100 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2101 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2102 pcn_csr_write(sc, LE_CSR15, reg); 2103 } 2104 2105 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2106 reg = LE_B9_FDEN; 2107 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2108 reg |= LE_B9_AUIFD; 2109 pcn_bcr_write(sc, LE_BCR9, reg); 2110 } else 2111 pcn_bcr_write(sc, LE_BCR9, 0); 2112 2113 return (0); 2114 } 2115 2116 /* 2117 * pcn_79c971_mediainit: 2118 * 2119 * Initialize media for the Am79c971. 2120 */ 2121 static void 2122 pcn_79c971_mediainit(struct pcn_softc *sc) 2123 { 2124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2125 2126 /* We have MII. */ 2127 sc->sc_flags |= PCN_F_HAS_MII; 2128 2129 /* 2130 * The built-in 10BASE-T interface is mapped to the MII 2131 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2132 * word that tells us which PHY to use. 2133 * This driver used to ignore all but the first PHY to 2134 * answer, but this code was removed to support multiple 2135 * external PHYs. As the default instance will be the first 2136 * one to answer, no harm is done by letting the possibly 2137 * non-connected internal PHY show up. 2138 */ 2139 2140 /* Initialize our media structures and probe the MII. */ 2141 sc->sc_mii.mii_ifp = ifp; 2142 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2143 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2144 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2145 ifmedia_init(&sc->sc_mii.mii_media, 0, pcn_79c971_mediachange, 2146 pcn_79c971_mediastatus); 2147 2148 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2149 MII_OFFSET_ANY, 0); 2150 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2151 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2152 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2153 } else 2154 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2155 } 2156 2157 /* 2158 * pcn_79c971_mediastatus: [ifmedia interface function] 2159 * 2160 * Get the current interface media status (Am79c971 version). 2161 */ 2162 static void 2163 pcn_79c971_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2164 { 2165 struct pcn_softc *sc = ifp->if_softc; 2166 2167 mii_pollstat(&sc->sc_mii); 2168 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2169 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2170 } 2171 2172 /* 2173 * pcn_79c971_mediachange: [ifmedia interface function] 2174 * 2175 * Set hardware to newly-selected media (Am79c971 version). 2176 */ 2177 static int 2178 pcn_79c971_mediachange(struct ifnet *ifp) 2179 { 2180 struct pcn_softc *sc = ifp->if_softc; 2181 2182 if (ifp->if_flags & IFF_UP) 2183 mii_mediachg(&sc->sc_mii); 2184 return (0); 2185 } 2186 2187 /* 2188 * pcn_mii_readreg: [mii interface function] 2189 * 2190 * Read a PHY register on the MII. 2191 */ 2192 static int 2193 pcn_mii_readreg(struct device *self, int phy, int reg) 2194 { 2195 struct pcn_softc *sc = (void *) self; 2196 uint32_t rv; 2197 2198 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2199 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2200 if (rv == 0xffff) 2201 return (0); 2202 2203 return (rv); 2204 } 2205 2206 /* 2207 * pcn_mii_writereg: [mii interface function] 2208 * 2209 * Write a PHY register on the MII. 2210 */ 2211 static void 2212 pcn_mii_writereg(struct device *self, int phy, int reg, int val) 2213 { 2214 struct pcn_softc *sc = (void *) self; 2215 2216 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2217 pcn_bcr_write(sc, LE_BCR34, val); 2218 } 2219 2220 /* 2221 * pcn_mii_statchg: [mii interface function] 2222 * 2223 * Callback from MII layer when media changes. 2224 */ 2225 static void 2226 pcn_mii_statchg(struct device *self) 2227 { 2228 struct pcn_softc *sc = (void *) self; 2229 2230 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2231 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2232 else 2233 pcn_bcr_write(sc, LE_BCR9, 0); 2234 } 2235
Indexes created Fri Sep 26 20:09:58 GMT 2025