if_pcn.c revision 1.62
1 /* $NetBSD: if_pcn.c,v 1.62 2016/06/10 13:27:14 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.62 2016/06/10 13:27:14 ozaki-r Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rndsource.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txintr; /* Tx interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 275 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 276 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 277 278 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 279 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 280 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 281 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 282 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 283 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 284 struct evcnt sc_ev_txcopy; /* Tx copies required */ 285 #endif /* PCN_EVENT_COUNTERS */ 286 287 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 288 int sc_rcvfw; 289 290 const char * const *sc_xmtsp_desc; /* Tx start point info */ 291 int sc_xmtsp; 292 293 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 294 int sc_xmtfw; 295 296 int sc_flags; /* misc. flags; see below */ 297 int sc_swstyle; /* the software style in use */ 298 299 int sc_txfree; /* number of free Tx descriptors */ 300 int sc_txnext; /* next ready Tx descriptor */ 301 302 int sc_txsfree; /* number of free Tx jobs */ 303 int sc_txsnext; /* next free Tx job */ 304 int sc_txsdirty; /* dirty Tx jobs */ 305 306 int sc_rxptr; /* next ready Rx descriptor/job */ 307 308 uint32_t sc_csr5; /* prototype CSR5 register */ 309 uint32_t sc_mode; /* prototype MODE register */ 310 311 krndsource_t rnd_source; /* random source */ 312 }; 313 314 /* sc_flags */ 315 #define PCN_F_HAS_MII 0x0001 /* has MII */ 316 317 #ifdef PCN_EVENT_COUNTERS 318 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 319 #else 320 #define PCN_EVCNT_INCR(ev) /* nothing */ 321 #endif 322 323 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 324 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 325 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 326 327 #define PCN_CDTXSYNC(sc, x, n, ops) \ 328 do { \ 329 int __x, __n; \ 330 \ 331 __x = (x); \ 332 __n = (n); \ 333 \ 334 /* If it will wrap around, sync to the end of the ring. */ \ 335 if ((__x + __n) > PCN_NTXDESC) { \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 338 (PCN_NTXDESC - __x), (ops)); \ 339 __n -= (PCN_NTXDESC - __x); \ 340 __x = 0; \ 341 } \ 342 \ 343 /* Now sync whatever is left. */ \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 346 } while (/*CONSTCOND*/0) 347 348 #define PCN_CDRXSYNC(sc, x, ops) \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 351 352 #define PCN_CDINITSYNC(sc, ops) \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 355 356 #define PCN_INIT_RXDESC(sc, x) \ 357 do { \ 358 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 359 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 360 struct mbuf *__m = __rxs->rxs_mbuf; \ 361 \ 362 /* \ 363 * Note: We scoot the packet forward 2 bytes in the buffer \ 364 * so that the payload after the Ethernet header is aligned \ 365 * to a 4-byte boundary. \ 366 */ \ 367 __m->m_data = __m->m_ext.ext_buf + 2; \ 368 \ 369 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 370 __rmd->rmd2 = \ 371 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 372 __rmd->rmd0 = 0; \ 373 } else { \ 374 __rmd->rmd2 = 0; \ 375 __rmd->rmd0 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 } \ 378 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 379 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 380 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 381 } while(/*CONSTCOND*/0) 382 383 static void pcn_start(struct ifnet *); 384 static void pcn_watchdog(struct ifnet *); 385 static int pcn_ioctl(struct ifnet *, u_long, void *); 386 static int pcn_init(struct ifnet *); 387 static void pcn_stop(struct ifnet *, int); 388 389 static bool pcn_shutdown(device_t, int); 390 391 static void pcn_reset(struct pcn_softc *); 392 static void pcn_rxdrain(struct pcn_softc *); 393 static int pcn_add_rxbuf(struct pcn_softc *, int); 394 static void pcn_tick(void *); 395 396 static void pcn_spnd(struct pcn_softc *); 397 398 static void pcn_set_filter(struct pcn_softc *); 399 400 static int pcn_intr(void *); 401 static void pcn_txintr(struct pcn_softc *); 402 static int pcn_rxintr(struct pcn_softc *); 403 404 static int pcn_mii_readreg(device_t, int, int); 405 static void pcn_mii_writereg(device_t, int, int, int); 406 static void pcn_mii_statchg(struct ifnet *); 407 408 static void pcn_79c970_mediainit(struct pcn_softc *); 409 static int pcn_79c970_mediachange(struct ifnet *); 410 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 411 412 static void pcn_79c971_mediainit(struct pcn_softc *); 413 414 /* 415 * Description of a PCnet-PCI variant. Used to select media access 416 * method, mostly, and to print a nice description of the chip. 417 */ 418 static const struct pcn_variant { 419 const char *pcv_desc; 420 void (*pcv_mediainit)(struct pcn_softc *); 421 uint16_t pcv_chipid; 422 } pcn_variants[] = { 423 { "Am79c970 PCnet-PCI", 424 pcn_79c970_mediainit, 425 PARTID_Am79c970 }, 426 427 { "Am79c970A PCnet-PCI II", 428 pcn_79c970_mediainit, 429 PARTID_Am79c970A }, 430 431 { "Am79c971 PCnet-FAST", 432 pcn_79c971_mediainit, 433 PARTID_Am79c971 }, 434 435 { "Am79c972 PCnet-FAST+", 436 pcn_79c971_mediainit, 437 PARTID_Am79c972 }, 438 439 { "Am79c973 PCnet-FAST III", 440 pcn_79c971_mediainit, 441 PARTID_Am79c973 }, 442 443 { "Am79c975 PCnet-FAST III", 444 pcn_79c971_mediainit, 445 PARTID_Am79c975 }, 446 447 { "Unknown PCnet-PCI variant", 448 pcn_79c971_mediainit, 449 0 }, 450 }; 451 452 int pcn_copy_small = 0; 453 454 static int pcn_match(device_t, cfdata_t, void *); 455 static void pcn_attach(device_t, device_t, void *); 456 457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 458 pcn_match, pcn_attach, NULL, NULL); 459 460 /* 461 * Routines to read and write the PCnet-PCI CSR/BCR space. 462 */ 463 464 static inline uint32_t 465 pcn_csr_read(struct pcn_softc *sc, int reg) 466 { 467 468 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 469 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 470 } 471 472 static inline void 473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 478 } 479 480 static inline uint32_t 481 pcn_bcr_read(struct pcn_softc *sc, int reg) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 486 } 487 488 static inline void 489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 494 } 495 496 static bool 497 pcn_is_vmware(const char *enaddr) 498 { 499 500 /* 501 * VMware uses the OUI 00:0c:29 for auto-generated MAC 502 * addresses. 503 */ 504 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 505 return (TRUE); 506 507 /* 508 * VMware uses the OUI 00:50:56 for manually-set MAC 509 * addresses (and some auto-generated ones). 510 */ 511 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 512 return (TRUE); 513 514 return (FALSE); 515 } 516 517 static const struct pcn_variant * 518 pcn_lookup_variant(uint16_t chipid) 519 { 520 const struct pcn_variant *pcv; 521 522 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 523 if (chipid == pcv->pcv_chipid) 524 return (pcv); 525 } 526 527 /* 528 * This covers unknown chips, which we simply treat like 529 * a generic PCnet-FAST. 530 */ 531 return (pcv); 532 } 533 534 static int 535 pcn_match(device_t parent, cfdata_t cf, void *aux) 536 { 537 struct pci_attach_args *pa = aux; 538 539 /* 540 * IBM Makes a PCI variant of this card which shows up as a 541 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 542 * this card is truly a pcn card, so we have a special case match for 543 * it 544 */ 545 546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 548 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 549 return(1); 550 551 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 552 return (0); 553 554 switch (PCI_PRODUCT(pa->pa_id)) { 555 case PCI_PRODUCT_AMD_PCNET_PCI: 556 /* Beat if_le_pci.c */ 557 return (10); 558 } 559 560 return (0); 561 } 562 563 static void 564 pcn_attach(device_t parent, device_t self, void *aux) 565 { 566 struct pcn_softc *sc = device_private(self); 567 struct pci_attach_args *pa = aux; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 pci_intr_handle_t ih; 571 const char *intrstr = NULL; 572 bus_space_tag_t iot, memt; 573 bus_space_handle_t ioh, memh; 574 bus_dma_segment_t seg; 575 int ioh_valid, memh_valid; 576 int ntxsegs, i, rseg, error; 577 uint32_t chipid, reg; 578 uint8_t enaddr[ETHER_ADDR_LEN]; 579 prop_object_t obj; 580 bool is_vmware; 581 char intrbuf[PCI_INTRSTR_LEN]; 582 583 sc->sc_dev = self; 584 callout_init(&sc->sc_tick_ch, 0); 585 586 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 587 588 /* 589 * Map the device. 590 */ 591 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 592 &iot, &ioh, NULL, NULL) == 0); 593 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 594 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 595 &memt, &memh, NULL, NULL) == 0); 596 597 if (memh_valid) { 598 sc->sc_st = memt; 599 sc->sc_sh = memh; 600 } else if (ioh_valid) { 601 sc->sc_st = iot; 602 sc->sc_sh = ioh; 603 } else { 604 aprint_error_dev(self, "unable to map device registers\n"); 605 return; 606 } 607 608 sc->sc_dmat = pa->pa_dmat; 609 610 /* Make sure bus mastering is enabled. */ 611 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 612 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 613 PCI_COMMAND_MASTER_ENABLE); 614 615 /* power up chip */ 616 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 617 NULL)) && error != EOPNOTSUPP) { 618 aprint_error_dev(self, "cannot activate %d\n", error); 619 return; 620 } 621 622 /* 623 * Reset the chip to a known state. This also puts the 624 * chip into 32-bit mode. 625 */ 626 pcn_reset(sc); 627 628 /* 629 * On some systems with the chip is an on-board device, the 630 * EEPROM is not used. Handle this by reading the MAC address 631 * from the CSRs (assuming that boot firmware has written 632 * it there). 633 */ 634 obj = prop_dictionary_get(device_properties(sc->sc_dev), 635 "am79c970-no-eeprom"); 636 if (prop_bool_true(obj)) { 637 for (i = 0; i < 3; i++) { 638 uint32_t val; 639 val = pcn_csr_read(sc, LE_CSR12 + i); 640 enaddr[2 * i] = val & 0xff; 641 enaddr[2 * i + 1] = (val >> 8) & 0xff; 642 } 643 } else { 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 646 PCN32_APROM + i); 647 } 648 } 649 650 /* Check to see if this is a VMware emulated network interface. */ 651 is_vmware = pcn_is_vmware(enaddr); 652 653 /* 654 * Now that the device is mapped, attempt to figure out what 655 * kind of chip we have. Note that IDL has all 32 bits of 656 * the chip ID when we're in 32-bit mode. 657 */ 658 chipid = pcn_csr_read(sc, LE_CSR88); 659 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 660 661 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 662 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 663 ether_sprintf(enaddr)); 664 665 /* 666 * VMware has a bug in its network interface emulation; we must 667 * limit the number of Tx segments. 668 */ 669 if (is_vmware) { 670 ntxsegs = PCN_NTXSEGS_VMWARE; 671 prop_dictionary_set_bool(device_properties(sc->sc_dev), 672 "am79c970-vmware-tx-bug", TRUE); 673 aprint_verbose_dev(self, 674 "VMware Tx segment count bug detected\n"); 675 } else { 676 ntxsegs = PCN_NTXSEGS; 677 } 678 679 /* 680 * Map and establish our interrupt. 681 */ 682 if (pci_intr_map(pa, &ih)) { 683 aprint_error_dev(self, "unable to map interrupt\n"); 684 return; 685 } 686 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 687 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 688 if (sc->sc_ih == NULL) { 689 aprint_error_dev(self, "unable to establish interrupt"); 690 if (intrstr != NULL) 691 aprint_error(" at %s", intrstr); 692 aprint_error("\n"); 693 return; 694 } 695 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 696 697 /* 698 * Allocate the control data structures, and create and load the 699 * DMA map for it. 700 */ 701 if ((error = bus_dmamem_alloc(sc->sc_dmat, 702 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 703 0)) != 0) { 704 aprint_error_dev(self, "unable to allocate control data, " 705 "error = %d\n", error); 706 goto fail_0; 707 } 708 709 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 710 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 711 BUS_DMA_COHERENT)) != 0) { 712 aprint_error_dev(self, "unable to map control data, " 713 "error = %d\n", error); 714 goto fail_1; 715 } 716 717 if ((error = bus_dmamap_create(sc->sc_dmat, 718 sizeof(struct pcn_control_data), 1, 719 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 720 aprint_error_dev(self, "unable to create control data DMA map, " 721 "error = %d\n", error); 722 goto fail_2; 723 } 724 725 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 726 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 727 0)) != 0) { 728 aprint_error_dev(self, 729 "unable to load control data DMA map, error = %d\n", error); 730 goto fail_3; 731 } 732 733 /* Create the transmit buffer DMA maps. */ 734 for (i = 0; i < PCN_TXQUEUELEN; i++) { 735 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 736 ntxsegs, MCLBYTES, 0, 0, 737 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 738 aprint_error_dev(self, 739 "unable to create tx DMA map %d, error = %d\n", 740 i, error); 741 goto fail_4; 742 } 743 } 744 745 /* Create the receive buffer DMA maps. */ 746 for (i = 0; i < PCN_NRXDESC; i++) { 747 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 748 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 749 aprint_error_dev(self, 750 "unable to create rx DMA map %d, error = %d\n", 751 i, error); 752 goto fail_5; 753 } 754 sc->sc_rxsoft[i].rxs_mbuf = NULL; 755 } 756 757 /* Initialize our media structures. */ 758 (*sc->sc_variant->pcv_mediainit)(sc); 759 760 /* 761 * Initialize FIFO watermark info. 762 */ 763 switch (sc->sc_variant->pcv_chipid) { 764 case PARTID_Am79c970: 765 case PARTID_Am79c970A: 766 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 767 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 768 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 769 break; 770 771 default: 772 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 773 /* 774 * Read BCR25 to determine how much SRAM is 775 * on the board. If > 0, then we the chip 776 * uses different Start Point thresholds. 777 * 778 * Note BCR25 and BCR26 are loaded from the 779 * EEPROM on RST, and unaffected by S_RESET, 780 * so we don't really have to worry about 781 * them except for this. 782 */ 783 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 784 if (reg != 0) 785 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 786 else 787 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 788 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 789 break; 790 } 791 792 /* 793 * Set up defaults -- see the tables above for what these 794 * values mean. 795 * 796 * XXX How should we tune RCVFW and XMTFW? 797 */ 798 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 799 sc->sc_xmtsp = 1; 800 sc->sc_xmtfw = 0; 801 802 ifp = &sc->sc_ethercom.ec_if; 803 strcpy(ifp->if_xname, device_xname(self)); 804 ifp->if_softc = sc; 805 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 806 ifp->if_ioctl = pcn_ioctl; 807 ifp->if_start = pcn_start; 808 ifp->if_watchdog = pcn_watchdog; 809 ifp->if_init = pcn_init; 810 ifp->if_stop = pcn_stop; 811 IFQ_SET_READY(&ifp->if_snd); 812 813 /* Attach the interface. */ 814 if_attach(ifp); 815 ether_ifattach(ifp, enaddr); 816 rnd_attach_source(&sc->rnd_source, device_xname(self), 817 RND_TYPE_NET, RND_FLAG_DEFAULT); 818 819 #ifdef PCN_EVENT_COUNTERS 820 /* Attach event counters. */ 821 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 822 NULL, device_xname(self), "txsstall"); 823 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 824 NULL, device_xname(self), "txdstall"); 825 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 826 NULL, device_xname(self), "txintr"); 827 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 828 NULL, device_xname(self), "rxintr"); 829 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 830 NULL, device_xname(self), "babl"); 831 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 832 NULL, device_xname(self), "miss"); 833 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 834 NULL, device_xname(self), "merr"); 835 836 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 837 NULL, device_xname(self), "txseg1"); 838 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 839 NULL, device_xname(self), "txseg2"); 840 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 841 NULL, device_xname(self), "txseg3"); 842 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 843 NULL, device_xname(self), "txseg4"); 844 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 845 NULL, device_xname(self), "txseg5"); 846 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 847 NULL, device_xname(self), "txsegmore"); 848 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 849 NULL, device_xname(self), "txcopy"); 850 #endif /* PCN_EVENT_COUNTERS */ 851 852 /* 853 * Establish power handler with shutdown hook, to make sure 854 * the interface is shutdown during reboot. 855 */ 856 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 857 pmf_class_network_register(self, ifp); 858 else 859 aprint_error_dev(self, "couldn't establish power handler\n"); 860 861 return; 862 863 /* 864 * Free any resources we've allocated during the failed attach 865 * attempt. Do this in reverse order and fall through. 866 */ 867 fail_5: 868 for (i = 0; i < PCN_NRXDESC; i++) { 869 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 870 bus_dmamap_destroy(sc->sc_dmat, 871 sc->sc_rxsoft[i].rxs_dmamap); 872 } 873 fail_4: 874 for (i = 0; i < PCN_TXQUEUELEN; i++) { 875 if (sc->sc_txsoft[i].txs_dmamap != NULL) 876 bus_dmamap_destroy(sc->sc_dmat, 877 sc->sc_txsoft[i].txs_dmamap); 878 } 879 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 880 fail_3: 881 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 882 fail_2: 883 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 884 sizeof(struct pcn_control_data)); 885 fail_1: 886 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 887 fail_0: 888 return; 889 } 890 891 /* 892 * pcn_shutdown: 893 * 894 * Make sure the interface is stopped at reboot time. 895 */ 896 static bool 897 pcn_shutdown(device_t self, int howto) 898 { 899 struct pcn_softc *sc = device_private(self); 900 901 pcn_stop(&sc->sc_ethercom.ec_if, 1); 902 /* explicitly reset the chip for some onboard one with lazy firmware */ 903 pcn_reset(sc); 904 905 return true; 906 } 907 908 /* 909 * pcn_start: [ifnet interface function] 910 * 911 * Start packet transmission on the interface. 912 */ 913 static void 914 pcn_start(struct ifnet *ifp) 915 { 916 struct pcn_softc *sc = ifp->if_softc; 917 struct mbuf *m0, *m; 918 struct pcn_txsoft *txs; 919 bus_dmamap_t dmamap; 920 int error, nexttx, lasttx = -1, ofree, seg; 921 922 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 923 return; 924 925 /* 926 * Remember the previous number of free descriptors and 927 * the first descriptor we'll use. 928 */ 929 ofree = sc->sc_txfree; 930 931 /* 932 * Loop through the send queue, setting up transmit descriptors 933 * until we drain the queue, or use up all available transmit 934 * descriptors. 935 */ 936 for (;;) { 937 /* Grab a packet off the queue. */ 938 IFQ_POLL(&ifp->if_snd, m0); 939 if (m0 == NULL) 940 break; 941 m = NULL; 942 943 /* Get a work queue entry. */ 944 if (sc->sc_txsfree == 0) { 945 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 946 break; 947 } 948 949 txs = &sc->sc_txsoft[sc->sc_txsnext]; 950 dmamap = txs->txs_dmamap; 951 952 /* 953 * Load the DMA map. If this fails, the packet either 954 * didn't fit in the alloted number of segments, or we 955 * were short on resources. In this case, we'll copy 956 * and try again. 957 */ 958 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 959 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 960 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 961 MGETHDR(m, M_DONTWAIT, MT_DATA); 962 if (m == NULL) { 963 printf("%s: unable to allocate Tx mbuf\n", 964 device_xname(sc->sc_dev)); 965 break; 966 } 967 if (m0->m_pkthdr.len > MHLEN) { 968 MCLGET(m, M_DONTWAIT); 969 if ((m->m_flags & M_EXT) == 0) { 970 printf("%s: unable to allocate Tx " 971 "cluster\n", 972 device_xname(sc->sc_dev)); 973 m_freem(m); 974 break; 975 } 976 } 977 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 978 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 979 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 980 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 981 if (error) { 982 printf("%s: unable to load Tx buffer, " 983 "error = %d\n", device_xname(sc->sc_dev), 984 error); 985 m_freem(m); 986 break; 987 } 988 } 989 990 /* 991 * Ensure we have enough descriptors free to describe 992 * the packet. Note, we always reserve one descriptor 993 * at the end of the ring as a termination point, to 994 * prevent wrap-around. 995 */ 996 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 997 /* 998 * Not enough free descriptors to transmit this 999 * packet. We haven't committed anything yet, 1000 * so just unload the DMA map, put the packet 1001 * back on the queue, and punt. Notify the upper 1002 * layer that there are not more slots left. 1003 * 1004 * XXX We could allocate an mbuf and copy, but 1005 * XXX is it worth it? 1006 */ 1007 ifp->if_flags |= IFF_OACTIVE; 1008 bus_dmamap_unload(sc->sc_dmat, dmamap); 1009 if (m != NULL) 1010 m_freem(m); 1011 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1012 break; 1013 } 1014 1015 IFQ_DEQUEUE(&ifp->if_snd, m0); 1016 if (m != NULL) { 1017 m_freem(m0); 1018 m0 = m; 1019 } 1020 1021 /* 1022 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1023 */ 1024 1025 /* Sync the DMA map. */ 1026 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1027 BUS_DMASYNC_PREWRITE); 1028 1029 #ifdef PCN_EVENT_COUNTERS 1030 switch (dmamap->dm_nsegs) { 1031 case 1: 1032 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1033 break; 1034 case 2: 1035 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1036 break; 1037 case 3: 1038 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1039 break; 1040 case 4: 1041 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1042 break; 1043 case 5: 1044 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1045 break; 1046 default: 1047 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1048 break; 1049 } 1050 #endif /* PCN_EVENT_COUNTERS */ 1051 1052 /* 1053 * Initialize the transmit descriptors. 1054 */ 1055 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1056 for (nexttx = sc->sc_txnext, seg = 0; 1057 seg < dmamap->dm_nsegs; 1058 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1059 /* 1060 * If this is the first descriptor we're 1061 * enqueueing, don't set the OWN bit just 1062 * yet. That could cause a race condition. 1063 * We'll do it below. 1064 */ 1065 sc->sc_txdescs[nexttx].tmd0 = 0; 1066 sc->sc_txdescs[nexttx].tmd2 = 1067 htole32(dmamap->dm_segs[seg].ds_addr); 1068 sc->sc_txdescs[nexttx].tmd1 = 1069 htole32(LE_T1_ONES | 1070 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1071 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1072 LE_T1_BCNT_MASK)); 1073 lasttx = nexttx; 1074 } 1075 } else { 1076 for (nexttx = sc->sc_txnext, seg = 0; 1077 seg < dmamap->dm_nsegs; 1078 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1079 /* 1080 * If this is the first descriptor we're 1081 * enqueueing, don't set the OWN bit just 1082 * yet. That could cause a race condition. 1083 * We'll do it below. 1084 */ 1085 sc->sc_txdescs[nexttx].tmd0 = 1086 htole32(dmamap->dm_segs[seg].ds_addr); 1087 sc->sc_txdescs[nexttx].tmd2 = 0; 1088 sc->sc_txdescs[nexttx].tmd1 = 1089 htole32(LE_T1_ONES | 1090 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1091 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1092 LE_T1_BCNT_MASK)); 1093 lasttx = nexttx; 1094 } 1095 } 1096 1097 KASSERT(lasttx != -1); 1098 /* Interrupt on the packet, if appropriate. */ 1099 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1100 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1101 1102 /* Set `start of packet' and `end of packet' appropriately. */ 1103 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1104 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1105 htole32(LE_T1_OWN|LE_T1_STP); 1106 1107 /* Sync the descriptors we're using. */ 1108 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1109 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1110 1111 /* Kick the transmitter. */ 1112 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1113 1114 /* 1115 * Store a pointer to the packet so we can free it later, 1116 * and remember what txdirty will be once the packet is 1117 * done. 1118 */ 1119 txs->txs_mbuf = m0; 1120 txs->txs_firstdesc = sc->sc_txnext; 1121 txs->txs_lastdesc = lasttx; 1122 1123 /* Advance the tx pointer. */ 1124 sc->sc_txfree -= dmamap->dm_nsegs; 1125 sc->sc_txnext = nexttx; 1126 1127 sc->sc_txsfree--; 1128 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1129 1130 /* Pass the packet to any BPF listeners. */ 1131 bpf_mtap(ifp, m0); 1132 } 1133 1134 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1135 /* No more slots left; notify upper layer. */ 1136 ifp->if_flags |= IFF_OACTIVE; 1137 } 1138 1139 if (sc->sc_txfree != ofree) { 1140 /* Set a watchdog timer in case the chip flakes out. */ 1141 ifp->if_timer = 5; 1142 } 1143 } 1144 1145 /* 1146 * pcn_watchdog: [ifnet interface function] 1147 * 1148 * Watchdog timer handler. 1149 */ 1150 static void 1151 pcn_watchdog(struct ifnet *ifp) 1152 { 1153 struct pcn_softc *sc = ifp->if_softc; 1154 1155 /* 1156 * Since we're not interrupting every packet, sweep 1157 * up before we report an error. 1158 */ 1159 pcn_txintr(sc); 1160 1161 if (sc->sc_txfree != PCN_NTXDESC) { 1162 printf("%s: device timeout (txfree %d txsfree %d)\n", 1163 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1164 ifp->if_oerrors++; 1165 1166 /* Reset the interface. */ 1167 (void) pcn_init(ifp); 1168 } 1169 1170 /* Try to get more packets going. */ 1171 pcn_start(ifp); 1172 } 1173 1174 /* 1175 * pcn_ioctl: [ifnet interface function] 1176 * 1177 * Handle control requests from the operator. 1178 */ 1179 static int 1180 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1181 { 1182 struct pcn_softc *sc = ifp->if_softc; 1183 struct ifreq *ifr = (struct ifreq *) data; 1184 int s, error; 1185 1186 s = splnet(); 1187 1188 switch (cmd) { 1189 case SIOCSIFMEDIA: 1190 case SIOCGIFMEDIA: 1191 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1192 break; 1193 1194 default: 1195 error = ether_ioctl(ifp, cmd, data); 1196 if (error == ENETRESET) { 1197 /* 1198 * Multicast list has changed; set the hardware filter 1199 * accordingly. 1200 */ 1201 if (ifp->if_flags & IFF_RUNNING) 1202 error = pcn_init(ifp); 1203 else 1204 error = 0; 1205 } 1206 break; 1207 } 1208 1209 /* Try to get more packets going. */ 1210 pcn_start(ifp); 1211 1212 splx(s); 1213 return (error); 1214 } 1215 1216 /* 1217 * pcn_intr: 1218 * 1219 * Interrupt service routine. 1220 */ 1221 static int 1222 pcn_intr(void *arg) 1223 { 1224 struct pcn_softc *sc = arg; 1225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1226 uint32_t csr0; 1227 int wantinit, handled = 0; 1228 1229 for (wantinit = 0; wantinit == 0;) { 1230 csr0 = pcn_csr_read(sc, LE_CSR0); 1231 if ((csr0 & LE_C0_INTR) == 0) 1232 break; 1233 1234 rnd_add_uint32(&sc->rnd_source, csr0); 1235 1236 /* ACK the bits and re-enable interrupts. */ 1237 pcn_csr_write(sc, LE_CSR0, csr0 & 1238 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1239 LE_C0_TINT|LE_C0_IDON)); 1240 1241 handled = 1; 1242 1243 if (csr0 & LE_C0_RINT) { 1244 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1245 wantinit = pcn_rxintr(sc); 1246 } 1247 1248 if (csr0 & LE_C0_TINT) { 1249 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1250 pcn_txintr(sc); 1251 } 1252 1253 if (csr0 & LE_C0_ERR) { 1254 if (csr0 & LE_C0_BABL) { 1255 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1256 ifp->if_oerrors++; 1257 } 1258 if (csr0 & LE_C0_MISS) { 1259 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1260 ifp->if_ierrors++; 1261 } 1262 if (csr0 & LE_C0_MERR) { 1263 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1264 printf("%s: memory error\n", 1265 device_xname(sc->sc_dev)); 1266 wantinit = 1; 1267 break; 1268 } 1269 } 1270 1271 if ((csr0 & LE_C0_RXON) == 0) { 1272 printf("%s: receiver disabled\n", 1273 device_xname(sc->sc_dev)); 1274 ifp->if_ierrors++; 1275 wantinit = 1; 1276 } 1277 1278 if ((csr0 & LE_C0_TXON) == 0) { 1279 printf("%s: transmitter disabled\n", 1280 device_xname(sc->sc_dev)); 1281 ifp->if_oerrors++; 1282 wantinit = 1; 1283 } 1284 } 1285 1286 if (handled) { 1287 if (wantinit) 1288 pcn_init(ifp); 1289 1290 /* Try to get more packets going. */ 1291 pcn_start(ifp); 1292 } 1293 1294 return (handled); 1295 } 1296 1297 /* 1298 * pcn_spnd: 1299 * 1300 * Suspend the chip. 1301 */ 1302 static void 1303 pcn_spnd(struct pcn_softc *sc) 1304 { 1305 int i; 1306 1307 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1308 1309 for (i = 0; i < 10000; i++) { 1310 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1311 return; 1312 delay(5); 1313 } 1314 1315 printf("%s: WARNING: chip failed to enter suspended state\n", 1316 device_xname(sc->sc_dev)); 1317 } 1318 1319 /* 1320 * pcn_txintr: 1321 * 1322 * Helper; handle transmit interrupts. 1323 */ 1324 static void 1325 pcn_txintr(struct pcn_softc *sc) 1326 { 1327 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1328 struct pcn_txsoft *txs; 1329 uint32_t tmd1, tmd2, tmd; 1330 int i, j; 1331 1332 ifp->if_flags &= ~IFF_OACTIVE; 1333 1334 /* 1335 * Go through our Tx list and free mbufs for those 1336 * frames which have been transmitted. 1337 */ 1338 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1339 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1340 txs = &sc->sc_txsoft[i]; 1341 1342 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1343 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1344 1345 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1346 if (tmd1 & LE_T1_OWN) 1347 break; 1348 1349 /* 1350 * Slightly annoying -- we have to loop through the 1351 * descriptors we've used looking for ERR, since it 1352 * can appear on any descriptor in the chain. 1353 */ 1354 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1355 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1356 if (tmd & LE_T1_ERR) { 1357 ifp->if_oerrors++; 1358 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1359 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1360 else 1361 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1362 if (tmd2 & LE_T2_UFLO) { 1363 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1364 sc->sc_xmtsp++; 1365 printf("%s: transmit " 1366 "underrun; new threshold: " 1367 "%s\n", 1368 device_xname(sc->sc_dev), 1369 sc->sc_xmtsp_desc[ 1370 sc->sc_xmtsp]); 1371 pcn_spnd(sc); 1372 pcn_csr_write(sc, LE_CSR80, 1373 LE_C80_RCVFW(sc->sc_rcvfw) | 1374 LE_C80_XMTSP(sc->sc_xmtsp) | 1375 LE_C80_XMTFW(sc->sc_xmtfw)); 1376 pcn_csr_write(sc, LE_CSR5, 1377 sc->sc_csr5); 1378 } else { 1379 printf("%s: transmit " 1380 "underrun\n", 1381 device_xname(sc->sc_dev)); 1382 } 1383 } else if (tmd2 & LE_T2_BUFF) { 1384 printf("%s: transmit buffer error\n", 1385 device_xname(sc->sc_dev)); 1386 } 1387 if (tmd2 & LE_T2_LCOL) 1388 ifp->if_collisions++; 1389 if (tmd2 & LE_T2_RTRY) 1390 ifp->if_collisions += 16; 1391 goto next_packet; 1392 } 1393 if (j == txs->txs_lastdesc) 1394 break; 1395 } 1396 if (tmd1 & LE_T1_ONE) 1397 ifp->if_collisions++; 1398 else if (tmd & LE_T1_MORE) { 1399 /* Real number is unknown. */ 1400 ifp->if_collisions += 2; 1401 } 1402 ifp->if_opackets++; 1403 next_packet: 1404 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1405 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1406 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1407 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1408 m_freem(txs->txs_mbuf); 1409 txs->txs_mbuf = NULL; 1410 } 1411 1412 /* Update the dirty transmit buffer pointer. */ 1413 sc->sc_txsdirty = i; 1414 1415 /* 1416 * If there are no more pending transmissions, cancel the watchdog 1417 * timer. 1418 */ 1419 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1420 ifp->if_timer = 0; 1421 } 1422 1423 /* 1424 * pcn_rxintr: 1425 * 1426 * Helper; handle receive interrupts. 1427 */ 1428 static int 1429 pcn_rxintr(struct pcn_softc *sc) 1430 { 1431 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1432 struct pcn_rxsoft *rxs; 1433 struct mbuf *m; 1434 uint32_t rmd1; 1435 int i, len; 1436 1437 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1438 rxs = &sc->sc_rxsoft[i]; 1439 1440 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1441 1442 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1443 1444 if (rmd1 & LE_R1_OWN) 1445 break; 1446 1447 /* 1448 * Check for errors and make sure the packet fit into 1449 * a single buffer. We have structured this block of 1450 * code the way it is in order to compress it into 1451 * one test in the common case (no error). 1452 */ 1453 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1454 (LE_R1_STP|LE_R1_ENP))) { 1455 /* Make sure the packet is in a single buffer. */ 1456 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1457 (LE_R1_STP|LE_R1_ENP)) { 1458 printf("%s: packet spilled into next buffer\n", 1459 device_xname(sc->sc_dev)); 1460 return (1); /* pcn_intr() will re-init */ 1461 } 1462 1463 /* 1464 * If the packet had an error, simple recycle the 1465 * buffer. 1466 */ 1467 if (rmd1 & LE_R1_ERR) { 1468 ifp->if_ierrors++; 1469 /* 1470 * If we got an overflow error, chances 1471 * are there will be a CRC error. In 1472 * this case, just print the overflow 1473 * error, and skip the others. 1474 */ 1475 if (rmd1 & LE_R1_OFLO) 1476 printf("%s: overflow error\n", 1477 device_xname(sc->sc_dev)); 1478 else { 1479 #define PRINTIT(x, str) \ 1480 if (rmd1 & (x)) \ 1481 printf("%s: %s\n", \ 1482 device_xname(sc->sc_dev), \ 1483 str); 1484 PRINTIT(LE_R1_FRAM, "framing error"); 1485 PRINTIT(LE_R1_CRC, "CRC error"); 1486 PRINTIT(LE_R1_BUFF, "buffer error"); 1487 } 1488 #undef PRINTIT 1489 PCN_INIT_RXDESC(sc, i); 1490 continue; 1491 } 1492 } 1493 1494 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1495 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1496 1497 /* 1498 * No errors; receive the packet. 1499 */ 1500 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1501 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1502 else 1503 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1504 1505 /* 1506 * The LANCE family includes the CRC with every packet; 1507 * trim it off here. 1508 */ 1509 len -= ETHER_CRC_LEN; 1510 1511 /* 1512 * If the packet is small enough to fit in a 1513 * single header mbuf, allocate one and copy 1514 * the data into it. This greatly reduces 1515 * memory consumption when we receive lots 1516 * of small packets. 1517 * 1518 * Otherwise, we add a new buffer to the receive 1519 * chain. If this fails, we drop the packet and 1520 * recycle the old buffer. 1521 */ 1522 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1523 MGETHDR(m, M_DONTWAIT, MT_DATA); 1524 if (m == NULL) 1525 goto dropit; 1526 m->m_data += 2; 1527 memcpy(mtod(m, void *), 1528 mtod(rxs->rxs_mbuf, void *), len); 1529 PCN_INIT_RXDESC(sc, i); 1530 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1531 rxs->rxs_dmamap->dm_mapsize, 1532 BUS_DMASYNC_PREREAD); 1533 } else { 1534 m = rxs->rxs_mbuf; 1535 if (pcn_add_rxbuf(sc, i) != 0) { 1536 dropit: 1537 ifp->if_ierrors++; 1538 PCN_INIT_RXDESC(sc, i); 1539 bus_dmamap_sync(sc->sc_dmat, 1540 rxs->rxs_dmamap, 0, 1541 rxs->rxs_dmamap->dm_mapsize, 1542 BUS_DMASYNC_PREREAD); 1543 continue; 1544 } 1545 } 1546 1547 m_set_rcvif(m, ifp); 1548 m->m_pkthdr.len = m->m_len = len; 1549 1550 /* Pass this up to any BPF listeners. */ 1551 bpf_mtap(ifp, m); 1552 1553 /* Pass it on. */ 1554 if_percpuq_enqueue(ifp->if_percpuq, m); 1555 ifp->if_ipackets++; 1556 } 1557 1558 /* Update the receive pointer. */ 1559 sc->sc_rxptr = i; 1560 return (0); 1561 } 1562 1563 /* 1564 * pcn_tick: 1565 * 1566 * One second timer, used to tick the MII. 1567 */ 1568 static void 1569 pcn_tick(void *arg) 1570 { 1571 struct pcn_softc *sc = arg; 1572 int s; 1573 1574 s = splnet(); 1575 mii_tick(&sc->sc_mii); 1576 splx(s); 1577 1578 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1579 } 1580 1581 /* 1582 * pcn_reset: 1583 * 1584 * Perform a soft reset on the PCnet-PCI. 1585 */ 1586 static void 1587 pcn_reset(struct pcn_softc *sc) 1588 { 1589 1590 /* 1591 * The PCnet-PCI chip is reset by reading from the 1592 * RESET register. Note that while the NE2100 LANCE 1593 * boards require a write after the read, the PCnet-PCI 1594 * chips do not require this. 1595 * 1596 * Since we don't know if we're in 16-bit or 32-bit 1597 * mode right now, issue both (it's safe) in the 1598 * hopes that one will succeed. 1599 */ 1600 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1601 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1602 1603 /* Wait 1ms for it to finish. */ 1604 delay(1000); 1605 1606 /* 1607 * Select 32-bit I/O mode by issuing a 32-bit write to the 1608 * RDP. Since the RAP is 0 after a reset, writing a 0 1609 * to RDP is safe (since it simply clears CSR0). 1610 */ 1611 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1612 } 1613 1614 /* 1615 * pcn_init: [ifnet interface function] 1616 * 1617 * Initialize the interface. Must be called at splnet(). 1618 */ 1619 static int 1620 pcn_init(struct ifnet *ifp) 1621 { 1622 struct pcn_softc *sc = ifp->if_softc; 1623 struct pcn_rxsoft *rxs; 1624 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1625 int i, error = 0; 1626 uint32_t reg; 1627 1628 /* Cancel any pending I/O. */ 1629 pcn_stop(ifp, 0); 1630 1631 /* Reset the chip to a known state. */ 1632 pcn_reset(sc); 1633 1634 /* 1635 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1636 * else. 1637 * 1638 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1639 * because the structure layout is compatible with ILACC, 1640 * but the burst mode is only available in SSTYLE 3, and 1641 * burst mode should provide some performance enhancement. 1642 */ 1643 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1644 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1645 else 1646 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1647 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1648 1649 /* Initialize the transmit descriptor ring. */ 1650 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1651 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1652 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1653 sc->sc_txfree = PCN_NTXDESC; 1654 sc->sc_txnext = 0; 1655 1656 /* Initialize the transmit job descriptors. */ 1657 for (i = 0; i < PCN_TXQUEUELEN; i++) 1658 sc->sc_txsoft[i].txs_mbuf = NULL; 1659 sc->sc_txsfree = PCN_TXQUEUELEN; 1660 sc->sc_txsnext = 0; 1661 sc->sc_txsdirty = 0; 1662 1663 /* 1664 * Initialize the receive descriptor and receive job 1665 * descriptor rings. 1666 */ 1667 for (i = 0; i < PCN_NRXDESC; i++) { 1668 rxs = &sc->sc_rxsoft[i]; 1669 if (rxs->rxs_mbuf == NULL) { 1670 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1671 printf("%s: unable to allocate or map rx " 1672 "buffer %d, error = %d\n", 1673 device_xname(sc->sc_dev), i, error); 1674 /* 1675 * XXX Should attempt to run with fewer receive 1676 * XXX buffers instead of just failing. 1677 */ 1678 pcn_rxdrain(sc); 1679 goto out; 1680 } 1681 } else 1682 PCN_INIT_RXDESC(sc, i); 1683 } 1684 sc->sc_rxptr = 0; 1685 1686 /* Initialize MODE for the initialization block. */ 1687 sc->sc_mode = 0; 1688 if (ifp->if_flags & IFF_PROMISC) 1689 sc->sc_mode |= LE_C15_PROM; 1690 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1691 sc->sc_mode |= LE_C15_DRCVBC; 1692 1693 /* 1694 * If we have MII, simply select MII in the MODE register, 1695 * and clear ASEL. Otherwise, let ASEL stand (for now), 1696 * and leave PORTSEL alone (it is ignored with ASEL is set). 1697 */ 1698 if (sc->sc_flags & PCN_F_HAS_MII) { 1699 pcn_bcr_write(sc, LE_BCR2, 1700 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1701 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1702 1703 /* 1704 * Disable MII auto-negotiation. We handle that in 1705 * our own MII layer. 1706 */ 1707 pcn_bcr_write(sc, LE_BCR32, 1708 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1709 } 1710 1711 /* 1712 * Set the Tx and Rx descriptor ring addresses in the init 1713 * block, the TLEN and RLEN other fields of the init block 1714 * MODE register. 1715 */ 1716 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1717 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1718 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1719 ((ffs(PCN_NTXDESC) - 1) << 28) | 1720 ((ffs(PCN_NRXDESC) - 1) << 20)); 1721 1722 /* Set the station address in the init block. */ 1723 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1724 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1725 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1726 (enaddr[5] << 8)); 1727 1728 /* Set the multicast filter in the init block. */ 1729 pcn_set_filter(sc); 1730 1731 /* Initialize CSR3. */ 1732 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1733 1734 /* Initialize CSR4. */ 1735 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1736 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1737 1738 /* Initialize CSR5. */ 1739 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1740 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1741 1742 /* 1743 * If we have an Am79c971 or greater, initialize CSR7. 1744 * 1745 * XXX Might be nice to use the MII auto-poll interrupt someday. 1746 */ 1747 switch (sc->sc_variant->pcv_chipid) { 1748 case PARTID_Am79c970: 1749 case PARTID_Am79c970A: 1750 /* Not available on these chips. */ 1751 break; 1752 1753 default: 1754 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1755 break; 1756 } 1757 1758 /* 1759 * On the Am79c970A and greater, initialize BCR18 to 1760 * enable burst mode. 1761 * 1762 * Also enable the "no underflow" option on the Am79c971 and 1763 * higher, which prevents the chip from generating transmit 1764 * underflows, yet sill provides decent performance. Note if 1765 * chip is not connected to external SRAM, then we still have 1766 * to handle underflow errors (the NOUFLO bit is ignored in 1767 * that case). 1768 */ 1769 reg = pcn_bcr_read(sc, LE_BCR18); 1770 switch (sc->sc_variant->pcv_chipid) { 1771 case PARTID_Am79c970: 1772 break; 1773 1774 case PARTID_Am79c970A: 1775 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1776 break; 1777 1778 default: 1779 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1780 break; 1781 } 1782 pcn_bcr_write(sc, LE_BCR18, reg); 1783 1784 /* 1785 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1786 */ 1787 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1788 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1789 1790 /* 1791 * Send the init block to the chip, and wait for it 1792 * to be processed. 1793 */ 1794 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1795 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1796 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1797 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1798 delay(100); 1799 for (i = 0; i < 10000; i++) { 1800 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1801 break; 1802 delay(10); 1803 } 1804 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1805 if (i == 10000) { 1806 printf("%s: timeout processing init block\n", 1807 device_xname(sc->sc_dev)); 1808 error = EIO; 1809 goto out; 1810 } 1811 1812 /* Set the media. */ 1813 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1814 goto out; 1815 1816 /* Enable interrupts and external activity (and ACK IDON). */ 1817 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1818 1819 if (sc->sc_flags & PCN_F_HAS_MII) { 1820 /* Start the one second MII clock. */ 1821 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1822 } 1823 1824 /* ...all done! */ 1825 ifp->if_flags |= IFF_RUNNING; 1826 ifp->if_flags &= ~IFF_OACTIVE; 1827 1828 out: 1829 if (error) 1830 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1831 return (error); 1832 } 1833 1834 /* 1835 * pcn_rxdrain: 1836 * 1837 * Drain the receive queue. 1838 */ 1839 static void 1840 pcn_rxdrain(struct pcn_softc *sc) 1841 { 1842 struct pcn_rxsoft *rxs; 1843 int i; 1844 1845 for (i = 0; i < PCN_NRXDESC; i++) { 1846 rxs = &sc->sc_rxsoft[i]; 1847 if (rxs->rxs_mbuf != NULL) { 1848 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1849 m_freem(rxs->rxs_mbuf); 1850 rxs->rxs_mbuf = NULL; 1851 } 1852 } 1853 } 1854 1855 /* 1856 * pcn_stop: [ifnet interface function] 1857 * 1858 * Stop transmission on the interface. 1859 */ 1860 static void 1861 pcn_stop(struct ifnet *ifp, int disable) 1862 { 1863 struct pcn_softc *sc = ifp->if_softc; 1864 struct pcn_txsoft *txs; 1865 int i; 1866 1867 if (sc->sc_flags & PCN_F_HAS_MII) { 1868 /* Stop the one second clock. */ 1869 callout_stop(&sc->sc_tick_ch); 1870 1871 /* Down the MII. */ 1872 mii_down(&sc->sc_mii); 1873 } 1874 1875 /* Stop the chip. */ 1876 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1877 1878 /* Release any queued transmit buffers. */ 1879 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1880 txs = &sc->sc_txsoft[i]; 1881 if (txs->txs_mbuf != NULL) { 1882 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1883 m_freem(txs->txs_mbuf); 1884 txs->txs_mbuf = NULL; 1885 } 1886 } 1887 1888 /* Mark the interface as down and cancel the watchdog timer. */ 1889 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1890 ifp->if_timer = 0; 1891 1892 if (disable) 1893 pcn_rxdrain(sc); 1894 } 1895 1896 /* 1897 * pcn_add_rxbuf: 1898 * 1899 * Add a receive buffer to the indicated descriptor. 1900 */ 1901 static int 1902 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1903 { 1904 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1905 struct mbuf *m; 1906 int error; 1907 1908 MGETHDR(m, M_DONTWAIT, MT_DATA); 1909 if (m == NULL) 1910 return (ENOBUFS); 1911 1912 MCLGET(m, M_DONTWAIT); 1913 if ((m->m_flags & M_EXT) == 0) { 1914 m_freem(m); 1915 return (ENOBUFS); 1916 } 1917 1918 if (rxs->rxs_mbuf != NULL) 1919 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1920 1921 rxs->rxs_mbuf = m; 1922 1923 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1924 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1925 BUS_DMA_READ|BUS_DMA_NOWAIT); 1926 if (error) { 1927 printf("%s: can't load rx DMA map %d, error = %d\n", 1928 device_xname(sc->sc_dev), idx, error); 1929 panic("pcn_add_rxbuf"); 1930 } 1931 1932 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1933 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1934 1935 PCN_INIT_RXDESC(sc, idx); 1936 1937 return (0); 1938 } 1939 1940 /* 1941 * pcn_set_filter: 1942 * 1943 * Set up the receive filter. 1944 */ 1945 static void 1946 pcn_set_filter(struct pcn_softc *sc) 1947 { 1948 struct ethercom *ec = &sc->sc_ethercom; 1949 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1950 struct ether_multi *enm; 1951 struct ether_multistep step; 1952 uint32_t crc; 1953 1954 /* 1955 * Set up the multicast address filter by passing all multicast 1956 * addresses through a CRC generator, and then using the high 1957 * order 6 bits as an index into the 64-bit logical address 1958 * filter. The high order bits select the word, while the rest 1959 * of the bits select the bit within the word. 1960 */ 1961 1962 if (ifp->if_flags & IFF_PROMISC) 1963 goto allmulti; 1964 1965 sc->sc_initblock.init_ladrf[0] = 1966 sc->sc_initblock.init_ladrf[1] = 1967 sc->sc_initblock.init_ladrf[2] = 1968 sc->sc_initblock.init_ladrf[3] = 0; 1969 1970 ETHER_FIRST_MULTI(step, ec, enm); 1971 while (enm != NULL) { 1972 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1973 /* 1974 * We must listen to a range of multicast addresses. 1975 * For now, just accept all multicasts, rather than 1976 * trying to set only those filter bits needed to match 1977 * the range. (At this time, the only use of address 1978 * ranges is for IP multicast routing, for which the 1979 * range is big enough to require all bits set.) 1980 */ 1981 goto allmulti; 1982 } 1983 1984 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1985 1986 /* Just want the 6 most significant bits. */ 1987 crc >>= 26; 1988 1989 /* Set the corresponding bit in the filter. */ 1990 sc->sc_initblock.init_ladrf[crc >> 4] |= 1991 htole16(1 << (crc & 0xf)); 1992 1993 ETHER_NEXT_MULTI(step, enm); 1994 } 1995 1996 ifp->if_flags &= ~IFF_ALLMULTI; 1997 return; 1998 1999 allmulti: 2000 ifp->if_flags |= IFF_ALLMULTI; 2001 sc->sc_initblock.init_ladrf[0] = 2002 sc->sc_initblock.init_ladrf[1] = 2003 sc->sc_initblock.init_ladrf[2] = 2004 sc->sc_initblock.init_ladrf[3] = 0xffff; 2005 } 2006 2007 /* 2008 * pcn_79c970_mediainit: 2009 * 2010 * Initialize media for the Am79c970. 2011 */ 2012 static void 2013 pcn_79c970_mediainit(struct pcn_softc *sc) 2014 { 2015 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2016 const char *sep = ""; 2017 2018 sc->sc_mii.mii_ifp = ifp; 2019 2020 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2021 pcn_79c970_mediastatus); 2022 2023 #define ADD(str, m, d) \ 2024 do { \ 2025 aprint_normal("%s%s", sep, str); \ 2026 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2027 sep = ", "; \ 2028 } while (/*CONSTCOND*/0) 2029 2030 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2031 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2032 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2033 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2034 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2035 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2036 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2037 ADD("auto", IFM_AUTO, 0); 2038 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2039 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2040 aprint_normal("\n"); 2041 2042 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2043 } 2044 2045 /* 2046 * pcn_79c970_mediastatus: [ifmedia interface function] 2047 * 2048 * Get the current interface media status (Am79c970 version). 2049 */ 2050 static void 2051 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2052 { 2053 struct pcn_softc *sc = ifp->if_softc; 2054 2055 /* 2056 * The currently selected media is always the active media. 2057 * Note: We have no way to determine what media the AUTO 2058 * process picked. 2059 */ 2060 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2061 } 2062 2063 /* 2064 * pcn_79c970_mediachange: [ifmedia interface function] 2065 * 2066 * Set hardware to newly-selected media (Am79c970 version). 2067 */ 2068 static int 2069 pcn_79c970_mediachange(struct ifnet *ifp) 2070 { 2071 struct pcn_softc *sc = ifp->if_softc; 2072 uint32_t reg; 2073 2074 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2075 /* 2076 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2077 */ 2078 reg = pcn_bcr_read(sc, LE_BCR2); 2079 reg |= LE_B2_ASEL; 2080 pcn_bcr_write(sc, LE_BCR2, reg); 2081 } else { 2082 /* 2083 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2084 */ 2085 reg = pcn_bcr_read(sc, LE_BCR2); 2086 reg &= ~LE_B2_ASEL; 2087 pcn_bcr_write(sc, LE_BCR2, reg); 2088 2089 reg = pcn_csr_read(sc, LE_CSR15); 2090 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2091 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2092 pcn_csr_write(sc, LE_CSR15, reg); 2093 } 2094 2095 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2096 reg = LE_B9_FDEN; 2097 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2098 reg |= LE_B9_AUIFD; 2099 pcn_bcr_write(sc, LE_BCR9, reg); 2100 } else 2101 pcn_bcr_write(sc, LE_BCR9, 0); 2102 2103 return (0); 2104 } 2105 2106 /* 2107 * pcn_79c971_mediainit: 2108 * 2109 * Initialize media for the Am79c971. 2110 */ 2111 static void 2112 pcn_79c971_mediainit(struct pcn_softc *sc) 2113 { 2114 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2115 2116 /* We have MII. */ 2117 sc->sc_flags |= PCN_F_HAS_MII; 2118 2119 /* 2120 * The built-in 10BASE-T interface is mapped to the MII 2121 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2122 * word that tells us which PHY to use. 2123 * This driver used to ignore all but the first PHY to 2124 * answer, but this code was removed to support multiple 2125 * external PHYs. As the default instance will be the first 2126 * one to answer, no harm is done by letting the possibly 2127 * non-connected internal PHY show up. 2128 */ 2129 2130 /* Initialize our media structures and probe the MII. */ 2131 sc->sc_mii.mii_ifp = ifp; 2132 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2133 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2134 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2135 2136 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2137 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2138 ether_mediastatus); 2139 2140 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2141 MII_OFFSET_ANY, 0); 2142 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2143 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2144 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2145 } else 2146 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2147 } 2148 2149 /* 2150 * pcn_mii_readreg: [mii interface function] 2151 * 2152 * Read a PHY register on the MII. 2153 */ 2154 static int 2155 pcn_mii_readreg(device_t self, int phy, int reg) 2156 { 2157 struct pcn_softc *sc = device_private(self); 2158 uint32_t rv; 2159 2160 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2161 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2162 if (rv == 0xffff) 2163 return (0); 2164 2165 return (rv); 2166 } 2167 2168 /* 2169 * pcn_mii_writereg: [mii interface function] 2170 * 2171 * Write a PHY register on the MII. 2172 */ 2173 static void 2174 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2175 { 2176 struct pcn_softc *sc = device_private(self); 2177 2178 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2179 pcn_bcr_write(sc, LE_BCR34, val); 2180 } 2181 2182 /* 2183 * pcn_mii_statchg: [mii interface function] 2184 * 2185 * Callback from MII layer when media changes. 2186 */ 2187 static void 2188 pcn_mii_statchg(struct ifnet *ifp) 2189 { 2190 struct pcn_softc *sc = ifp->if_softc; 2191 2192 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2193 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2194 else 2195 pcn_bcr_write(sc, LE_BCR9, 0); 2196 } 2197
Indexes created Fri Sep 26 20:09:58 GMT 2025