if_pcn.c revision 1.63
1 /* $NetBSD: if_pcn.c,v 1.63 2016/12/08 01:12:01 ozaki-r Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.63 2016/12/08 01:12:01 ozaki-r Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rndsource.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txintr; /* Tx interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 275 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 276 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 277 278 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 279 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 280 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 281 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 282 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 283 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 284 struct evcnt sc_ev_txcopy; /* Tx copies required */ 285 #endif /* PCN_EVENT_COUNTERS */ 286 287 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 288 int sc_rcvfw; 289 290 const char * const *sc_xmtsp_desc; /* Tx start point info */ 291 int sc_xmtsp; 292 293 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 294 int sc_xmtfw; 295 296 int sc_flags; /* misc. flags; see below */ 297 int sc_swstyle; /* the software style in use */ 298 299 int sc_txfree; /* number of free Tx descriptors */ 300 int sc_txnext; /* next ready Tx descriptor */ 301 302 int sc_txsfree; /* number of free Tx jobs */ 303 int sc_txsnext; /* next free Tx job */ 304 int sc_txsdirty; /* dirty Tx jobs */ 305 306 int sc_rxptr; /* next ready Rx descriptor/job */ 307 308 uint32_t sc_csr5; /* prototype CSR5 register */ 309 uint32_t sc_mode; /* prototype MODE register */ 310 311 krndsource_t rnd_source; /* random source */ 312 }; 313 314 /* sc_flags */ 315 #define PCN_F_HAS_MII 0x0001 /* has MII */ 316 317 #ifdef PCN_EVENT_COUNTERS 318 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 319 #else 320 #define PCN_EVCNT_INCR(ev) /* nothing */ 321 #endif 322 323 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 324 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 325 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 326 327 #define PCN_CDTXSYNC(sc, x, n, ops) \ 328 do { \ 329 int __x, __n; \ 330 \ 331 __x = (x); \ 332 __n = (n); \ 333 \ 334 /* If it will wrap around, sync to the end of the ring. */ \ 335 if ((__x + __n) > PCN_NTXDESC) { \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 338 (PCN_NTXDESC - __x), (ops)); \ 339 __n -= (PCN_NTXDESC - __x); \ 340 __x = 0; \ 341 } \ 342 \ 343 /* Now sync whatever is left. */ \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 346 } while (/*CONSTCOND*/0) 347 348 #define PCN_CDRXSYNC(sc, x, ops) \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 351 352 #define PCN_CDINITSYNC(sc, ops) \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 355 356 #define PCN_INIT_RXDESC(sc, x) \ 357 do { \ 358 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 359 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 360 struct mbuf *__m = __rxs->rxs_mbuf; \ 361 \ 362 /* \ 363 * Note: We scoot the packet forward 2 bytes in the buffer \ 364 * so that the payload after the Ethernet header is aligned \ 365 * to a 4-byte boundary. \ 366 */ \ 367 __m->m_data = __m->m_ext.ext_buf + 2; \ 368 \ 369 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 370 __rmd->rmd2 = \ 371 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 372 __rmd->rmd0 = 0; \ 373 } else { \ 374 __rmd->rmd2 = 0; \ 375 __rmd->rmd0 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 } \ 378 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 379 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 380 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 381 } while(/*CONSTCOND*/0) 382 383 static void pcn_start(struct ifnet *); 384 static void pcn_watchdog(struct ifnet *); 385 static int pcn_ioctl(struct ifnet *, u_long, void *); 386 static int pcn_init(struct ifnet *); 387 static void pcn_stop(struct ifnet *, int); 388 389 static bool pcn_shutdown(device_t, int); 390 391 static void pcn_reset(struct pcn_softc *); 392 static void pcn_rxdrain(struct pcn_softc *); 393 static int pcn_add_rxbuf(struct pcn_softc *, int); 394 static void pcn_tick(void *); 395 396 static void pcn_spnd(struct pcn_softc *); 397 398 static void pcn_set_filter(struct pcn_softc *); 399 400 static int pcn_intr(void *); 401 static void pcn_txintr(struct pcn_softc *); 402 static int pcn_rxintr(struct pcn_softc *); 403 404 static int pcn_mii_readreg(device_t, int, int); 405 static void pcn_mii_writereg(device_t, int, int, int); 406 static void pcn_mii_statchg(struct ifnet *); 407 408 static void pcn_79c970_mediainit(struct pcn_softc *); 409 static int pcn_79c970_mediachange(struct ifnet *); 410 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 411 412 static void pcn_79c971_mediainit(struct pcn_softc *); 413 414 /* 415 * Description of a PCnet-PCI variant. Used to select media access 416 * method, mostly, and to print a nice description of the chip. 417 */ 418 static const struct pcn_variant { 419 const char *pcv_desc; 420 void (*pcv_mediainit)(struct pcn_softc *); 421 uint16_t pcv_chipid; 422 } pcn_variants[] = { 423 { "Am79c970 PCnet-PCI", 424 pcn_79c970_mediainit, 425 PARTID_Am79c970 }, 426 427 { "Am79c970A PCnet-PCI II", 428 pcn_79c970_mediainit, 429 PARTID_Am79c970A }, 430 431 { "Am79c971 PCnet-FAST", 432 pcn_79c971_mediainit, 433 PARTID_Am79c971 }, 434 435 { "Am79c972 PCnet-FAST+", 436 pcn_79c971_mediainit, 437 PARTID_Am79c972 }, 438 439 { "Am79c973 PCnet-FAST III", 440 pcn_79c971_mediainit, 441 PARTID_Am79c973 }, 442 443 { "Am79c975 PCnet-FAST III", 444 pcn_79c971_mediainit, 445 PARTID_Am79c975 }, 446 447 { "Unknown PCnet-PCI variant", 448 pcn_79c971_mediainit, 449 0 }, 450 }; 451 452 int pcn_copy_small = 0; 453 454 static int pcn_match(device_t, cfdata_t, void *); 455 static void pcn_attach(device_t, device_t, void *); 456 457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 458 pcn_match, pcn_attach, NULL, NULL); 459 460 /* 461 * Routines to read and write the PCnet-PCI CSR/BCR space. 462 */ 463 464 static inline uint32_t 465 pcn_csr_read(struct pcn_softc *sc, int reg) 466 { 467 468 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 469 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 470 } 471 472 static inline void 473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 478 } 479 480 static inline uint32_t 481 pcn_bcr_read(struct pcn_softc *sc, int reg) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 486 } 487 488 static inline void 489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 494 } 495 496 static bool 497 pcn_is_vmware(const char *enaddr) 498 { 499 500 /* 501 * VMware uses the OUI 00:0c:29 for auto-generated MAC 502 * addresses. 503 */ 504 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 505 return (TRUE); 506 507 /* 508 * VMware uses the OUI 00:50:56 for manually-set MAC 509 * addresses (and some auto-generated ones). 510 */ 511 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 512 return (TRUE); 513 514 return (FALSE); 515 } 516 517 static const struct pcn_variant * 518 pcn_lookup_variant(uint16_t chipid) 519 { 520 const struct pcn_variant *pcv; 521 522 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 523 if (chipid == pcv->pcv_chipid) 524 return (pcv); 525 } 526 527 /* 528 * This covers unknown chips, which we simply treat like 529 * a generic PCnet-FAST. 530 */ 531 return (pcv); 532 } 533 534 static int 535 pcn_match(device_t parent, cfdata_t cf, void *aux) 536 { 537 struct pci_attach_args *pa = aux; 538 539 /* 540 * IBM Makes a PCI variant of this card which shows up as a 541 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 542 * this card is truly a pcn card, so we have a special case match for 543 * it 544 */ 545 546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 548 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 549 return(1); 550 551 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 552 return (0); 553 554 switch (PCI_PRODUCT(pa->pa_id)) { 555 case PCI_PRODUCT_AMD_PCNET_PCI: 556 /* Beat if_le_pci.c */ 557 return (10); 558 } 559 560 return (0); 561 } 562 563 static void 564 pcn_attach(device_t parent, device_t self, void *aux) 565 { 566 struct pcn_softc *sc = device_private(self); 567 struct pci_attach_args *pa = aux; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 pci_intr_handle_t ih; 571 const char *intrstr = NULL; 572 bus_space_tag_t iot, memt; 573 bus_space_handle_t ioh, memh; 574 bus_dma_segment_t seg; 575 int ioh_valid, memh_valid; 576 int ntxsegs, i, rseg, error; 577 uint32_t chipid, reg; 578 uint8_t enaddr[ETHER_ADDR_LEN]; 579 prop_object_t obj; 580 bool is_vmware; 581 char intrbuf[PCI_INTRSTR_LEN]; 582 583 sc->sc_dev = self; 584 callout_init(&sc->sc_tick_ch, 0); 585 586 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 587 588 /* 589 * Map the device. 590 */ 591 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 592 &iot, &ioh, NULL, NULL) == 0); 593 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 594 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 595 &memt, &memh, NULL, NULL) == 0); 596 597 if (memh_valid) { 598 sc->sc_st = memt; 599 sc->sc_sh = memh; 600 } else if (ioh_valid) { 601 sc->sc_st = iot; 602 sc->sc_sh = ioh; 603 } else { 604 aprint_error_dev(self, "unable to map device registers\n"); 605 return; 606 } 607 608 sc->sc_dmat = pa->pa_dmat; 609 610 /* Make sure bus mastering is enabled. */ 611 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 612 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 613 PCI_COMMAND_MASTER_ENABLE); 614 615 /* power up chip */ 616 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 617 NULL)) && error != EOPNOTSUPP) { 618 aprint_error_dev(self, "cannot activate %d\n", error); 619 return; 620 } 621 622 /* 623 * Reset the chip to a known state. This also puts the 624 * chip into 32-bit mode. 625 */ 626 pcn_reset(sc); 627 628 /* 629 * On some systems with the chip is an on-board device, the 630 * EEPROM is not used. Handle this by reading the MAC address 631 * from the CSRs (assuming that boot firmware has written 632 * it there). 633 */ 634 obj = prop_dictionary_get(device_properties(sc->sc_dev), 635 "am79c970-no-eeprom"); 636 if (prop_bool_true(obj)) { 637 for (i = 0; i < 3; i++) { 638 uint32_t val; 639 val = pcn_csr_read(sc, LE_CSR12 + i); 640 enaddr[2 * i] = val & 0xff; 641 enaddr[2 * i + 1] = (val >> 8) & 0xff; 642 } 643 } else { 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 646 PCN32_APROM + i); 647 } 648 } 649 650 /* Check to see if this is a VMware emulated network interface. */ 651 is_vmware = pcn_is_vmware(enaddr); 652 653 /* 654 * Now that the device is mapped, attempt to figure out what 655 * kind of chip we have. Note that IDL has all 32 bits of 656 * the chip ID when we're in 32-bit mode. 657 */ 658 chipid = pcn_csr_read(sc, LE_CSR88); 659 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 660 661 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 662 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 663 ether_sprintf(enaddr)); 664 665 /* 666 * VMware has a bug in its network interface emulation; we must 667 * limit the number of Tx segments. 668 */ 669 if (is_vmware) { 670 ntxsegs = PCN_NTXSEGS_VMWARE; 671 prop_dictionary_set_bool(device_properties(sc->sc_dev), 672 "am79c970-vmware-tx-bug", TRUE); 673 aprint_verbose_dev(self, 674 "VMware Tx segment count bug detected\n"); 675 } else { 676 ntxsegs = PCN_NTXSEGS; 677 } 678 679 /* 680 * Map and establish our interrupt. 681 */ 682 if (pci_intr_map(pa, &ih)) { 683 aprint_error_dev(self, "unable to map interrupt\n"); 684 return; 685 } 686 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 687 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, pcn_intr, sc); 688 if (sc->sc_ih == NULL) { 689 aprint_error_dev(self, "unable to establish interrupt"); 690 if (intrstr != NULL) 691 aprint_error(" at %s", intrstr); 692 aprint_error("\n"); 693 return; 694 } 695 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 696 697 /* 698 * Allocate the control data structures, and create and load the 699 * DMA map for it. 700 */ 701 if ((error = bus_dmamem_alloc(sc->sc_dmat, 702 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 703 0)) != 0) { 704 aprint_error_dev(self, "unable to allocate control data, " 705 "error = %d\n", error); 706 goto fail_0; 707 } 708 709 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 710 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 711 BUS_DMA_COHERENT)) != 0) { 712 aprint_error_dev(self, "unable to map control data, " 713 "error = %d\n", error); 714 goto fail_1; 715 } 716 717 if ((error = bus_dmamap_create(sc->sc_dmat, 718 sizeof(struct pcn_control_data), 1, 719 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 720 aprint_error_dev(self, "unable to create control data DMA map, " 721 "error = %d\n", error); 722 goto fail_2; 723 } 724 725 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 726 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 727 0)) != 0) { 728 aprint_error_dev(self, 729 "unable to load control data DMA map, error = %d\n", error); 730 goto fail_3; 731 } 732 733 /* Create the transmit buffer DMA maps. */ 734 for (i = 0; i < PCN_TXQUEUELEN; i++) { 735 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 736 ntxsegs, MCLBYTES, 0, 0, 737 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 738 aprint_error_dev(self, 739 "unable to create tx DMA map %d, error = %d\n", 740 i, error); 741 goto fail_4; 742 } 743 } 744 745 /* Create the receive buffer DMA maps. */ 746 for (i = 0; i < PCN_NRXDESC; i++) { 747 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 748 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 749 aprint_error_dev(self, 750 "unable to create rx DMA map %d, error = %d\n", 751 i, error); 752 goto fail_5; 753 } 754 sc->sc_rxsoft[i].rxs_mbuf = NULL; 755 } 756 757 /* Initialize our media structures. */ 758 (*sc->sc_variant->pcv_mediainit)(sc); 759 760 /* 761 * Initialize FIFO watermark info. 762 */ 763 switch (sc->sc_variant->pcv_chipid) { 764 case PARTID_Am79c970: 765 case PARTID_Am79c970A: 766 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 767 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 768 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 769 break; 770 771 default: 772 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 773 /* 774 * Read BCR25 to determine how much SRAM is 775 * on the board. If > 0, then we the chip 776 * uses different Start Point thresholds. 777 * 778 * Note BCR25 and BCR26 are loaded from the 779 * EEPROM on RST, and unaffected by S_RESET, 780 * so we don't really have to worry about 781 * them except for this. 782 */ 783 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 784 if (reg != 0) 785 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 786 else 787 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 788 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 789 break; 790 } 791 792 /* 793 * Set up defaults -- see the tables above for what these 794 * values mean. 795 * 796 * XXX How should we tune RCVFW and XMTFW? 797 */ 798 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 799 sc->sc_xmtsp = 1; 800 sc->sc_xmtfw = 0; 801 802 ifp = &sc->sc_ethercom.ec_if; 803 strcpy(ifp->if_xname, device_xname(self)); 804 ifp->if_softc = sc; 805 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 806 ifp->if_ioctl = pcn_ioctl; 807 ifp->if_start = pcn_start; 808 ifp->if_watchdog = pcn_watchdog; 809 ifp->if_init = pcn_init; 810 ifp->if_stop = pcn_stop; 811 IFQ_SET_READY(&ifp->if_snd); 812 813 /* Attach the interface. */ 814 if_attach(ifp); 815 if_deferred_start_init(ifp, NULL); 816 ether_ifattach(ifp, enaddr); 817 rnd_attach_source(&sc->rnd_source, device_xname(self), 818 RND_TYPE_NET, RND_FLAG_DEFAULT); 819 820 #ifdef PCN_EVENT_COUNTERS 821 /* Attach event counters. */ 822 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 823 NULL, device_xname(self), "txsstall"); 824 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 825 NULL, device_xname(self), "txdstall"); 826 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 827 NULL, device_xname(self), "txintr"); 828 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 829 NULL, device_xname(self), "rxintr"); 830 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 831 NULL, device_xname(self), "babl"); 832 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 833 NULL, device_xname(self), "miss"); 834 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 835 NULL, device_xname(self), "merr"); 836 837 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 838 NULL, device_xname(self), "txseg1"); 839 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 840 NULL, device_xname(self), "txseg2"); 841 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 842 NULL, device_xname(self), "txseg3"); 843 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txseg4"); 845 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txseg5"); 847 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txsegmore"); 849 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 850 NULL, device_xname(self), "txcopy"); 851 #endif /* PCN_EVENT_COUNTERS */ 852 853 /* 854 * Establish power handler with shutdown hook, to make sure 855 * the interface is shutdown during reboot. 856 */ 857 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 858 pmf_class_network_register(self, ifp); 859 else 860 aprint_error_dev(self, "couldn't establish power handler\n"); 861 862 return; 863 864 /* 865 * Free any resources we've allocated during the failed attach 866 * attempt. Do this in reverse order and fall through. 867 */ 868 fail_5: 869 for (i = 0; i < PCN_NRXDESC; i++) { 870 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 871 bus_dmamap_destroy(sc->sc_dmat, 872 sc->sc_rxsoft[i].rxs_dmamap); 873 } 874 fail_4: 875 for (i = 0; i < PCN_TXQUEUELEN; i++) { 876 if (sc->sc_txsoft[i].txs_dmamap != NULL) 877 bus_dmamap_destroy(sc->sc_dmat, 878 sc->sc_txsoft[i].txs_dmamap); 879 } 880 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 881 fail_3: 882 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 883 fail_2: 884 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 885 sizeof(struct pcn_control_data)); 886 fail_1: 887 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 888 fail_0: 889 return; 890 } 891 892 /* 893 * pcn_shutdown: 894 * 895 * Make sure the interface is stopped at reboot time. 896 */ 897 static bool 898 pcn_shutdown(device_t self, int howto) 899 { 900 struct pcn_softc *sc = device_private(self); 901 902 pcn_stop(&sc->sc_ethercom.ec_if, 1); 903 /* explicitly reset the chip for some onboard one with lazy firmware */ 904 pcn_reset(sc); 905 906 return true; 907 } 908 909 /* 910 * pcn_start: [ifnet interface function] 911 * 912 * Start packet transmission on the interface. 913 */ 914 static void 915 pcn_start(struct ifnet *ifp) 916 { 917 struct pcn_softc *sc = ifp->if_softc; 918 struct mbuf *m0, *m; 919 struct pcn_txsoft *txs; 920 bus_dmamap_t dmamap; 921 int error, nexttx, lasttx = -1, ofree, seg; 922 923 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 924 return; 925 926 /* 927 * Remember the previous number of free descriptors and 928 * the first descriptor we'll use. 929 */ 930 ofree = sc->sc_txfree; 931 932 /* 933 * Loop through the send queue, setting up transmit descriptors 934 * until we drain the queue, or use up all available transmit 935 * descriptors. 936 */ 937 for (;;) { 938 /* Grab a packet off the queue. */ 939 IFQ_POLL(&ifp->if_snd, m0); 940 if (m0 == NULL) 941 break; 942 m = NULL; 943 944 /* Get a work queue entry. */ 945 if (sc->sc_txsfree == 0) { 946 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 947 break; 948 } 949 950 txs = &sc->sc_txsoft[sc->sc_txsnext]; 951 dmamap = txs->txs_dmamap; 952 953 /* 954 * Load the DMA map. If this fails, the packet either 955 * didn't fit in the alloted number of segments, or we 956 * were short on resources. In this case, we'll copy 957 * and try again. 958 */ 959 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 960 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 961 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 962 MGETHDR(m, M_DONTWAIT, MT_DATA); 963 if (m == NULL) { 964 printf("%s: unable to allocate Tx mbuf\n", 965 device_xname(sc->sc_dev)); 966 break; 967 } 968 if (m0->m_pkthdr.len > MHLEN) { 969 MCLGET(m, M_DONTWAIT); 970 if ((m->m_flags & M_EXT) == 0) { 971 printf("%s: unable to allocate Tx " 972 "cluster\n", 973 device_xname(sc->sc_dev)); 974 m_freem(m); 975 break; 976 } 977 } 978 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 979 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 980 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 981 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 982 if (error) { 983 printf("%s: unable to load Tx buffer, " 984 "error = %d\n", device_xname(sc->sc_dev), 985 error); 986 m_freem(m); 987 break; 988 } 989 } 990 991 /* 992 * Ensure we have enough descriptors free to describe 993 * the packet. Note, we always reserve one descriptor 994 * at the end of the ring as a termination point, to 995 * prevent wrap-around. 996 */ 997 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 998 /* 999 * Not enough free descriptors to transmit this 1000 * packet. We haven't committed anything yet, 1001 * so just unload the DMA map, put the packet 1002 * back on the queue, and punt. Notify the upper 1003 * layer that there are not more slots left. 1004 * 1005 * XXX We could allocate an mbuf and copy, but 1006 * XXX is it worth it? 1007 */ 1008 ifp->if_flags |= IFF_OACTIVE; 1009 bus_dmamap_unload(sc->sc_dmat, dmamap); 1010 if (m != NULL) 1011 m_freem(m); 1012 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1013 break; 1014 } 1015 1016 IFQ_DEQUEUE(&ifp->if_snd, m0); 1017 if (m != NULL) { 1018 m_freem(m0); 1019 m0 = m; 1020 } 1021 1022 /* 1023 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1024 */ 1025 1026 /* Sync the DMA map. */ 1027 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1028 BUS_DMASYNC_PREWRITE); 1029 1030 #ifdef PCN_EVENT_COUNTERS 1031 switch (dmamap->dm_nsegs) { 1032 case 1: 1033 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1034 break; 1035 case 2: 1036 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1037 break; 1038 case 3: 1039 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1040 break; 1041 case 4: 1042 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1043 break; 1044 case 5: 1045 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1046 break; 1047 default: 1048 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1049 break; 1050 } 1051 #endif /* PCN_EVENT_COUNTERS */ 1052 1053 /* 1054 * Initialize the transmit descriptors. 1055 */ 1056 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1057 for (nexttx = sc->sc_txnext, seg = 0; 1058 seg < dmamap->dm_nsegs; 1059 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1060 /* 1061 * If this is the first descriptor we're 1062 * enqueueing, don't set the OWN bit just 1063 * yet. That could cause a race condition. 1064 * We'll do it below. 1065 */ 1066 sc->sc_txdescs[nexttx].tmd0 = 0; 1067 sc->sc_txdescs[nexttx].tmd2 = 1068 htole32(dmamap->dm_segs[seg].ds_addr); 1069 sc->sc_txdescs[nexttx].tmd1 = 1070 htole32(LE_T1_ONES | 1071 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1072 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1073 LE_T1_BCNT_MASK)); 1074 lasttx = nexttx; 1075 } 1076 } else { 1077 for (nexttx = sc->sc_txnext, seg = 0; 1078 seg < dmamap->dm_nsegs; 1079 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1080 /* 1081 * If this is the first descriptor we're 1082 * enqueueing, don't set the OWN bit just 1083 * yet. That could cause a race condition. 1084 * We'll do it below. 1085 */ 1086 sc->sc_txdescs[nexttx].tmd0 = 1087 htole32(dmamap->dm_segs[seg].ds_addr); 1088 sc->sc_txdescs[nexttx].tmd2 = 0; 1089 sc->sc_txdescs[nexttx].tmd1 = 1090 htole32(LE_T1_ONES | 1091 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1092 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1093 LE_T1_BCNT_MASK)); 1094 lasttx = nexttx; 1095 } 1096 } 1097 1098 KASSERT(lasttx != -1); 1099 /* Interrupt on the packet, if appropriate. */ 1100 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1101 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1102 1103 /* Set `start of packet' and `end of packet' appropriately. */ 1104 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1105 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1106 htole32(LE_T1_OWN|LE_T1_STP); 1107 1108 /* Sync the descriptors we're using. */ 1109 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1110 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1111 1112 /* Kick the transmitter. */ 1113 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1114 1115 /* 1116 * Store a pointer to the packet so we can free it later, 1117 * and remember what txdirty will be once the packet is 1118 * done. 1119 */ 1120 txs->txs_mbuf = m0; 1121 txs->txs_firstdesc = sc->sc_txnext; 1122 txs->txs_lastdesc = lasttx; 1123 1124 /* Advance the tx pointer. */ 1125 sc->sc_txfree -= dmamap->dm_nsegs; 1126 sc->sc_txnext = nexttx; 1127 1128 sc->sc_txsfree--; 1129 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1130 1131 /* Pass the packet to any BPF listeners. */ 1132 bpf_mtap(ifp, m0); 1133 } 1134 1135 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1136 /* No more slots left; notify upper layer. */ 1137 ifp->if_flags |= IFF_OACTIVE; 1138 } 1139 1140 if (sc->sc_txfree != ofree) { 1141 /* Set a watchdog timer in case the chip flakes out. */ 1142 ifp->if_timer = 5; 1143 } 1144 } 1145 1146 /* 1147 * pcn_watchdog: [ifnet interface function] 1148 * 1149 * Watchdog timer handler. 1150 */ 1151 static void 1152 pcn_watchdog(struct ifnet *ifp) 1153 { 1154 struct pcn_softc *sc = ifp->if_softc; 1155 1156 /* 1157 * Since we're not interrupting every packet, sweep 1158 * up before we report an error. 1159 */ 1160 pcn_txintr(sc); 1161 1162 if (sc->sc_txfree != PCN_NTXDESC) { 1163 printf("%s: device timeout (txfree %d txsfree %d)\n", 1164 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1165 ifp->if_oerrors++; 1166 1167 /* Reset the interface. */ 1168 (void) pcn_init(ifp); 1169 } 1170 1171 /* Try to get more packets going. */ 1172 pcn_start(ifp); 1173 } 1174 1175 /* 1176 * pcn_ioctl: [ifnet interface function] 1177 * 1178 * Handle control requests from the operator. 1179 */ 1180 static int 1181 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1182 { 1183 struct pcn_softc *sc = ifp->if_softc; 1184 struct ifreq *ifr = (struct ifreq *) data; 1185 int s, error; 1186 1187 s = splnet(); 1188 1189 switch (cmd) { 1190 case SIOCSIFMEDIA: 1191 case SIOCGIFMEDIA: 1192 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1193 break; 1194 1195 default: 1196 error = ether_ioctl(ifp, cmd, data); 1197 if (error == ENETRESET) { 1198 /* 1199 * Multicast list has changed; set the hardware filter 1200 * accordingly. 1201 */ 1202 if (ifp->if_flags & IFF_RUNNING) 1203 error = pcn_init(ifp); 1204 else 1205 error = 0; 1206 } 1207 break; 1208 } 1209 1210 /* Try to get more packets going. */ 1211 pcn_start(ifp); 1212 1213 splx(s); 1214 return (error); 1215 } 1216 1217 /* 1218 * pcn_intr: 1219 * 1220 * Interrupt service routine. 1221 */ 1222 static int 1223 pcn_intr(void *arg) 1224 { 1225 struct pcn_softc *sc = arg; 1226 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1227 uint32_t csr0; 1228 int wantinit, handled = 0; 1229 1230 for (wantinit = 0; wantinit == 0;) { 1231 csr0 = pcn_csr_read(sc, LE_CSR0); 1232 if ((csr0 & LE_C0_INTR) == 0) 1233 break; 1234 1235 rnd_add_uint32(&sc->rnd_source, csr0); 1236 1237 /* ACK the bits and re-enable interrupts. */ 1238 pcn_csr_write(sc, LE_CSR0, csr0 & 1239 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1240 LE_C0_TINT|LE_C0_IDON)); 1241 1242 handled = 1; 1243 1244 if (csr0 & LE_C0_RINT) { 1245 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1246 wantinit = pcn_rxintr(sc); 1247 } 1248 1249 if (csr0 & LE_C0_TINT) { 1250 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1251 pcn_txintr(sc); 1252 } 1253 1254 if (csr0 & LE_C0_ERR) { 1255 if (csr0 & LE_C0_BABL) { 1256 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1257 ifp->if_oerrors++; 1258 } 1259 if (csr0 & LE_C0_MISS) { 1260 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1261 ifp->if_ierrors++; 1262 } 1263 if (csr0 & LE_C0_MERR) { 1264 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1265 printf("%s: memory error\n", 1266 device_xname(sc->sc_dev)); 1267 wantinit = 1; 1268 break; 1269 } 1270 } 1271 1272 if ((csr0 & LE_C0_RXON) == 0) { 1273 printf("%s: receiver disabled\n", 1274 device_xname(sc->sc_dev)); 1275 ifp->if_ierrors++; 1276 wantinit = 1; 1277 } 1278 1279 if ((csr0 & LE_C0_TXON) == 0) { 1280 printf("%s: transmitter disabled\n", 1281 device_xname(sc->sc_dev)); 1282 ifp->if_oerrors++; 1283 wantinit = 1; 1284 } 1285 } 1286 1287 if (handled) { 1288 if (wantinit) 1289 pcn_init(ifp); 1290 1291 /* Try to get more packets going. */ 1292 if_schedule_deferred_start(ifp); 1293 } 1294 1295 return (handled); 1296 } 1297 1298 /* 1299 * pcn_spnd: 1300 * 1301 * Suspend the chip. 1302 */ 1303 static void 1304 pcn_spnd(struct pcn_softc *sc) 1305 { 1306 int i; 1307 1308 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1309 1310 for (i = 0; i < 10000; i++) { 1311 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1312 return; 1313 delay(5); 1314 } 1315 1316 printf("%s: WARNING: chip failed to enter suspended state\n", 1317 device_xname(sc->sc_dev)); 1318 } 1319 1320 /* 1321 * pcn_txintr: 1322 * 1323 * Helper; handle transmit interrupts. 1324 */ 1325 static void 1326 pcn_txintr(struct pcn_softc *sc) 1327 { 1328 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1329 struct pcn_txsoft *txs; 1330 uint32_t tmd1, tmd2, tmd; 1331 int i, j; 1332 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 1335 /* 1336 * Go through our Tx list and free mbufs for those 1337 * frames which have been transmitted. 1338 */ 1339 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1340 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1341 txs = &sc->sc_txsoft[i]; 1342 1343 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1344 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1345 1346 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1347 if (tmd1 & LE_T1_OWN) 1348 break; 1349 1350 /* 1351 * Slightly annoying -- we have to loop through the 1352 * descriptors we've used looking for ERR, since it 1353 * can appear on any descriptor in the chain. 1354 */ 1355 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1356 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1357 if (tmd & LE_T1_ERR) { 1358 ifp->if_oerrors++; 1359 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1360 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1361 else 1362 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1363 if (tmd2 & LE_T2_UFLO) { 1364 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1365 sc->sc_xmtsp++; 1366 printf("%s: transmit " 1367 "underrun; new threshold: " 1368 "%s\n", 1369 device_xname(sc->sc_dev), 1370 sc->sc_xmtsp_desc[ 1371 sc->sc_xmtsp]); 1372 pcn_spnd(sc); 1373 pcn_csr_write(sc, LE_CSR80, 1374 LE_C80_RCVFW(sc->sc_rcvfw) | 1375 LE_C80_XMTSP(sc->sc_xmtsp) | 1376 LE_C80_XMTFW(sc->sc_xmtfw)); 1377 pcn_csr_write(sc, LE_CSR5, 1378 sc->sc_csr5); 1379 } else { 1380 printf("%s: transmit " 1381 "underrun\n", 1382 device_xname(sc->sc_dev)); 1383 } 1384 } else if (tmd2 & LE_T2_BUFF) { 1385 printf("%s: transmit buffer error\n", 1386 device_xname(sc->sc_dev)); 1387 } 1388 if (tmd2 & LE_T2_LCOL) 1389 ifp->if_collisions++; 1390 if (tmd2 & LE_T2_RTRY) 1391 ifp->if_collisions += 16; 1392 goto next_packet; 1393 } 1394 if (j == txs->txs_lastdesc) 1395 break; 1396 } 1397 if (tmd1 & LE_T1_ONE) 1398 ifp->if_collisions++; 1399 else if (tmd & LE_T1_MORE) { 1400 /* Real number is unknown. */ 1401 ifp->if_collisions += 2; 1402 } 1403 ifp->if_opackets++; 1404 next_packet: 1405 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1406 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1407 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1408 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1409 m_freem(txs->txs_mbuf); 1410 txs->txs_mbuf = NULL; 1411 } 1412 1413 /* Update the dirty transmit buffer pointer. */ 1414 sc->sc_txsdirty = i; 1415 1416 /* 1417 * If there are no more pending transmissions, cancel the watchdog 1418 * timer. 1419 */ 1420 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1421 ifp->if_timer = 0; 1422 } 1423 1424 /* 1425 * pcn_rxintr: 1426 * 1427 * Helper; handle receive interrupts. 1428 */ 1429 static int 1430 pcn_rxintr(struct pcn_softc *sc) 1431 { 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 struct pcn_rxsoft *rxs; 1434 struct mbuf *m; 1435 uint32_t rmd1; 1436 int i, len; 1437 1438 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1439 rxs = &sc->sc_rxsoft[i]; 1440 1441 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1442 1443 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1444 1445 if (rmd1 & LE_R1_OWN) 1446 break; 1447 1448 /* 1449 * Check for errors and make sure the packet fit into 1450 * a single buffer. We have structured this block of 1451 * code the way it is in order to compress it into 1452 * one test in the common case (no error). 1453 */ 1454 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1455 (LE_R1_STP|LE_R1_ENP))) { 1456 /* Make sure the packet is in a single buffer. */ 1457 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1458 (LE_R1_STP|LE_R1_ENP)) { 1459 printf("%s: packet spilled into next buffer\n", 1460 device_xname(sc->sc_dev)); 1461 return (1); /* pcn_intr() will re-init */ 1462 } 1463 1464 /* 1465 * If the packet had an error, simple recycle the 1466 * buffer. 1467 */ 1468 if (rmd1 & LE_R1_ERR) { 1469 ifp->if_ierrors++; 1470 /* 1471 * If we got an overflow error, chances 1472 * are there will be a CRC error. In 1473 * this case, just print the overflow 1474 * error, and skip the others. 1475 */ 1476 if (rmd1 & LE_R1_OFLO) 1477 printf("%s: overflow error\n", 1478 device_xname(sc->sc_dev)); 1479 else { 1480 #define PRINTIT(x, str) \ 1481 if (rmd1 & (x)) \ 1482 printf("%s: %s\n", \ 1483 device_xname(sc->sc_dev), \ 1484 str); 1485 PRINTIT(LE_R1_FRAM, "framing error"); 1486 PRINTIT(LE_R1_CRC, "CRC error"); 1487 PRINTIT(LE_R1_BUFF, "buffer error"); 1488 } 1489 #undef PRINTIT 1490 PCN_INIT_RXDESC(sc, i); 1491 continue; 1492 } 1493 } 1494 1495 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1496 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1497 1498 /* 1499 * No errors; receive the packet. 1500 */ 1501 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1502 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1503 else 1504 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1505 1506 /* 1507 * The LANCE family includes the CRC with every packet; 1508 * trim it off here. 1509 */ 1510 len -= ETHER_CRC_LEN; 1511 1512 /* 1513 * If the packet is small enough to fit in a 1514 * single header mbuf, allocate one and copy 1515 * the data into it. This greatly reduces 1516 * memory consumption when we receive lots 1517 * of small packets. 1518 * 1519 * Otherwise, we add a new buffer to the receive 1520 * chain. If this fails, we drop the packet and 1521 * recycle the old buffer. 1522 */ 1523 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1524 MGETHDR(m, M_DONTWAIT, MT_DATA); 1525 if (m == NULL) 1526 goto dropit; 1527 m->m_data += 2; 1528 memcpy(mtod(m, void *), 1529 mtod(rxs->rxs_mbuf, void *), len); 1530 PCN_INIT_RXDESC(sc, i); 1531 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1532 rxs->rxs_dmamap->dm_mapsize, 1533 BUS_DMASYNC_PREREAD); 1534 } else { 1535 m = rxs->rxs_mbuf; 1536 if (pcn_add_rxbuf(sc, i) != 0) { 1537 dropit: 1538 ifp->if_ierrors++; 1539 PCN_INIT_RXDESC(sc, i); 1540 bus_dmamap_sync(sc->sc_dmat, 1541 rxs->rxs_dmamap, 0, 1542 rxs->rxs_dmamap->dm_mapsize, 1543 BUS_DMASYNC_PREREAD); 1544 continue; 1545 } 1546 } 1547 1548 m_set_rcvif(m, ifp); 1549 m->m_pkthdr.len = m->m_len = len; 1550 1551 /* Pass this up to any BPF listeners. */ 1552 bpf_mtap(ifp, m); 1553 1554 /* Pass it on. */ 1555 if_percpuq_enqueue(ifp->if_percpuq, m); 1556 ifp->if_ipackets++; 1557 } 1558 1559 /* Update the receive pointer. */ 1560 sc->sc_rxptr = i; 1561 return (0); 1562 } 1563 1564 /* 1565 * pcn_tick: 1566 * 1567 * One second timer, used to tick the MII. 1568 */ 1569 static void 1570 pcn_tick(void *arg) 1571 { 1572 struct pcn_softc *sc = arg; 1573 int s; 1574 1575 s = splnet(); 1576 mii_tick(&sc->sc_mii); 1577 splx(s); 1578 1579 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1580 } 1581 1582 /* 1583 * pcn_reset: 1584 * 1585 * Perform a soft reset on the PCnet-PCI. 1586 */ 1587 static void 1588 pcn_reset(struct pcn_softc *sc) 1589 { 1590 1591 /* 1592 * The PCnet-PCI chip is reset by reading from the 1593 * RESET register. Note that while the NE2100 LANCE 1594 * boards require a write after the read, the PCnet-PCI 1595 * chips do not require this. 1596 * 1597 * Since we don't know if we're in 16-bit or 32-bit 1598 * mode right now, issue both (it's safe) in the 1599 * hopes that one will succeed. 1600 */ 1601 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1602 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1603 1604 /* Wait 1ms for it to finish. */ 1605 delay(1000); 1606 1607 /* 1608 * Select 32-bit I/O mode by issuing a 32-bit write to the 1609 * RDP. Since the RAP is 0 after a reset, writing a 0 1610 * to RDP is safe (since it simply clears CSR0). 1611 */ 1612 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1613 } 1614 1615 /* 1616 * pcn_init: [ifnet interface function] 1617 * 1618 * Initialize the interface. Must be called at splnet(). 1619 */ 1620 static int 1621 pcn_init(struct ifnet *ifp) 1622 { 1623 struct pcn_softc *sc = ifp->if_softc; 1624 struct pcn_rxsoft *rxs; 1625 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1626 int i, error = 0; 1627 uint32_t reg; 1628 1629 /* Cancel any pending I/O. */ 1630 pcn_stop(ifp, 0); 1631 1632 /* Reset the chip to a known state. */ 1633 pcn_reset(sc); 1634 1635 /* 1636 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1637 * else. 1638 * 1639 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1640 * because the structure layout is compatible with ILACC, 1641 * but the burst mode is only available in SSTYLE 3, and 1642 * burst mode should provide some performance enhancement. 1643 */ 1644 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1645 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1646 else 1647 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1648 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1649 1650 /* Initialize the transmit descriptor ring. */ 1651 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1652 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1653 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1654 sc->sc_txfree = PCN_NTXDESC; 1655 sc->sc_txnext = 0; 1656 1657 /* Initialize the transmit job descriptors. */ 1658 for (i = 0; i < PCN_TXQUEUELEN; i++) 1659 sc->sc_txsoft[i].txs_mbuf = NULL; 1660 sc->sc_txsfree = PCN_TXQUEUELEN; 1661 sc->sc_txsnext = 0; 1662 sc->sc_txsdirty = 0; 1663 1664 /* 1665 * Initialize the receive descriptor and receive job 1666 * descriptor rings. 1667 */ 1668 for (i = 0; i < PCN_NRXDESC; i++) { 1669 rxs = &sc->sc_rxsoft[i]; 1670 if (rxs->rxs_mbuf == NULL) { 1671 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1672 printf("%s: unable to allocate or map rx " 1673 "buffer %d, error = %d\n", 1674 device_xname(sc->sc_dev), i, error); 1675 /* 1676 * XXX Should attempt to run with fewer receive 1677 * XXX buffers instead of just failing. 1678 */ 1679 pcn_rxdrain(sc); 1680 goto out; 1681 } 1682 } else 1683 PCN_INIT_RXDESC(sc, i); 1684 } 1685 sc->sc_rxptr = 0; 1686 1687 /* Initialize MODE for the initialization block. */ 1688 sc->sc_mode = 0; 1689 if (ifp->if_flags & IFF_PROMISC) 1690 sc->sc_mode |= LE_C15_PROM; 1691 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1692 sc->sc_mode |= LE_C15_DRCVBC; 1693 1694 /* 1695 * If we have MII, simply select MII in the MODE register, 1696 * and clear ASEL. Otherwise, let ASEL stand (for now), 1697 * and leave PORTSEL alone (it is ignored with ASEL is set). 1698 */ 1699 if (sc->sc_flags & PCN_F_HAS_MII) { 1700 pcn_bcr_write(sc, LE_BCR2, 1701 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1702 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1703 1704 /* 1705 * Disable MII auto-negotiation. We handle that in 1706 * our own MII layer. 1707 */ 1708 pcn_bcr_write(sc, LE_BCR32, 1709 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1710 } 1711 1712 /* 1713 * Set the Tx and Rx descriptor ring addresses in the init 1714 * block, the TLEN and RLEN other fields of the init block 1715 * MODE register. 1716 */ 1717 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1718 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1719 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1720 ((ffs(PCN_NTXDESC) - 1) << 28) | 1721 ((ffs(PCN_NRXDESC) - 1) << 20)); 1722 1723 /* Set the station address in the init block. */ 1724 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1725 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1726 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1727 (enaddr[5] << 8)); 1728 1729 /* Set the multicast filter in the init block. */ 1730 pcn_set_filter(sc); 1731 1732 /* Initialize CSR3. */ 1733 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1734 1735 /* Initialize CSR4. */ 1736 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1737 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1738 1739 /* Initialize CSR5. */ 1740 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1741 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1742 1743 /* 1744 * If we have an Am79c971 or greater, initialize CSR7. 1745 * 1746 * XXX Might be nice to use the MII auto-poll interrupt someday. 1747 */ 1748 switch (sc->sc_variant->pcv_chipid) { 1749 case PARTID_Am79c970: 1750 case PARTID_Am79c970A: 1751 /* Not available on these chips. */ 1752 break; 1753 1754 default: 1755 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1756 break; 1757 } 1758 1759 /* 1760 * On the Am79c970A and greater, initialize BCR18 to 1761 * enable burst mode. 1762 * 1763 * Also enable the "no underflow" option on the Am79c971 and 1764 * higher, which prevents the chip from generating transmit 1765 * underflows, yet sill provides decent performance. Note if 1766 * chip is not connected to external SRAM, then we still have 1767 * to handle underflow errors (the NOUFLO bit is ignored in 1768 * that case). 1769 */ 1770 reg = pcn_bcr_read(sc, LE_BCR18); 1771 switch (sc->sc_variant->pcv_chipid) { 1772 case PARTID_Am79c970: 1773 break; 1774 1775 case PARTID_Am79c970A: 1776 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1777 break; 1778 1779 default: 1780 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1781 break; 1782 } 1783 pcn_bcr_write(sc, LE_BCR18, reg); 1784 1785 /* 1786 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1787 */ 1788 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1789 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1790 1791 /* 1792 * Send the init block to the chip, and wait for it 1793 * to be processed. 1794 */ 1795 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1796 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1797 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1798 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1799 delay(100); 1800 for (i = 0; i < 10000; i++) { 1801 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1802 break; 1803 delay(10); 1804 } 1805 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1806 if (i == 10000) { 1807 printf("%s: timeout processing init block\n", 1808 device_xname(sc->sc_dev)); 1809 error = EIO; 1810 goto out; 1811 } 1812 1813 /* Set the media. */ 1814 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1815 goto out; 1816 1817 /* Enable interrupts and external activity (and ACK IDON). */ 1818 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1819 1820 if (sc->sc_flags & PCN_F_HAS_MII) { 1821 /* Start the one second MII clock. */ 1822 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1823 } 1824 1825 /* ...all done! */ 1826 ifp->if_flags |= IFF_RUNNING; 1827 ifp->if_flags &= ~IFF_OACTIVE; 1828 1829 out: 1830 if (error) 1831 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1832 return (error); 1833 } 1834 1835 /* 1836 * pcn_rxdrain: 1837 * 1838 * Drain the receive queue. 1839 */ 1840 static void 1841 pcn_rxdrain(struct pcn_softc *sc) 1842 { 1843 struct pcn_rxsoft *rxs; 1844 int i; 1845 1846 for (i = 0; i < PCN_NRXDESC; i++) { 1847 rxs = &sc->sc_rxsoft[i]; 1848 if (rxs->rxs_mbuf != NULL) { 1849 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1850 m_freem(rxs->rxs_mbuf); 1851 rxs->rxs_mbuf = NULL; 1852 } 1853 } 1854 } 1855 1856 /* 1857 * pcn_stop: [ifnet interface function] 1858 * 1859 * Stop transmission on the interface. 1860 */ 1861 static void 1862 pcn_stop(struct ifnet *ifp, int disable) 1863 { 1864 struct pcn_softc *sc = ifp->if_softc; 1865 struct pcn_txsoft *txs; 1866 int i; 1867 1868 if (sc->sc_flags & PCN_F_HAS_MII) { 1869 /* Stop the one second clock. */ 1870 callout_stop(&sc->sc_tick_ch); 1871 1872 /* Down the MII. */ 1873 mii_down(&sc->sc_mii); 1874 } 1875 1876 /* Stop the chip. */ 1877 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1878 1879 /* Release any queued transmit buffers. */ 1880 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1881 txs = &sc->sc_txsoft[i]; 1882 if (txs->txs_mbuf != NULL) { 1883 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1884 m_freem(txs->txs_mbuf); 1885 txs->txs_mbuf = NULL; 1886 } 1887 } 1888 1889 /* Mark the interface as down and cancel the watchdog timer. */ 1890 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1891 ifp->if_timer = 0; 1892 1893 if (disable) 1894 pcn_rxdrain(sc); 1895 } 1896 1897 /* 1898 * pcn_add_rxbuf: 1899 * 1900 * Add a receive buffer to the indicated descriptor. 1901 */ 1902 static int 1903 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1904 { 1905 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1906 struct mbuf *m; 1907 int error; 1908 1909 MGETHDR(m, M_DONTWAIT, MT_DATA); 1910 if (m == NULL) 1911 return (ENOBUFS); 1912 1913 MCLGET(m, M_DONTWAIT); 1914 if ((m->m_flags & M_EXT) == 0) { 1915 m_freem(m); 1916 return (ENOBUFS); 1917 } 1918 1919 if (rxs->rxs_mbuf != NULL) 1920 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1921 1922 rxs->rxs_mbuf = m; 1923 1924 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1925 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1926 BUS_DMA_READ|BUS_DMA_NOWAIT); 1927 if (error) { 1928 printf("%s: can't load rx DMA map %d, error = %d\n", 1929 device_xname(sc->sc_dev), idx, error); 1930 panic("pcn_add_rxbuf"); 1931 } 1932 1933 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1934 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1935 1936 PCN_INIT_RXDESC(sc, idx); 1937 1938 return (0); 1939 } 1940 1941 /* 1942 * pcn_set_filter: 1943 * 1944 * Set up the receive filter. 1945 */ 1946 static void 1947 pcn_set_filter(struct pcn_softc *sc) 1948 { 1949 struct ethercom *ec = &sc->sc_ethercom; 1950 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1951 struct ether_multi *enm; 1952 struct ether_multistep step; 1953 uint32_t crc; 1954 1955 /* 1956 * Set up the multicast address filter by passing all multicast 1957 * addresses through a CRC generator, and then using the high 1958 * order 6 bits as an index into the 64-bit logical address 1959 * filter. The high order bits select the word, while the rest 1960 * of the bits select the bit within the word. 1961 */ 1962 1963 if (ifp->if_flags & IFF_PROMISC) 1964 goto allmulti; 1965 1966 sc->sc_initblock.init_ladrf[0] = 1967 sc->sc_initblock.init_ladrf[1] = 1968 sc->sc_initblock.init_ladrf[2] = 1969 sc->sc_initblock.init_ladrf[3] = 0; 1970 1971 ETHER_FIRST_MULTI(step, ec, enm); 1972 while (enm != NULL) { 1973 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1974 /* 1975 * We must listen to a range of multicast addresses. 1976 * For now, just accept all multicasts, rather than 1977 * trying to set only those filter bits needed to match 1978 * the range. (At this time, the only use of address 1979 * ranges is for IP multicast routing, for which the 1980 * range is big enough to require all bits set.) 1981 */ 1982 goto allmulti; 1983 } 1984 1985 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1986 1987 /* Just want the 6 most significant bits. */ 1988 crc >>= 26; 1989 1990 /* Set the corresponding bit in the filter. */ 1991 sc->sc_initblock.init_ladrf[crc >> 4] |= 1992 htole16(1 << (crc & 0xf)); 1993 1994 ETHER_NEXT_MULTI(step, enm); 1995 } 1996 1997 ifp->if_flags &= ~IFF_ALLMULTI; 1998 return; 1999 2000 allmulti: 2001 ifp->if_flags |= IFF_ALLMULTI; 2002 sc->sc_initblock.init_ladrf[0] = 2003 sc->sc_initblock.init_ladrf[1] = 2004 sc->sc_initblock.init_ladrf[2] = 2005 sc->sc_initblock.init_ladrf[3] = 0xffff; 2006 } 2007 2008 /* 2009 * pcn_79c970_mediainit: 2010 * 2011 * Initialize media for the Am79c970. 2012 */ 2013 static void 2014 pcn_79c970_mediainit(struct pcn_softc *sc) 2015 { 2016 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2017 const char *sep = ""; 2018 2019 sc->sc_mii.mii_ifp = ifp; 2020 2021 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2022 pcn_79c970_mediastatus); 2023 2024 #define ADD(str, m, d) \ 2025 do { \ 2026 aprint_normal("%s%s", sep, str); \ 2027 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2028 sep = ", "; \ 2029 } while (/*CONSTCOND*/0) 2030 2031 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2032 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2033 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2034 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2035 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2036 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2037 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2038 ADD("auto", IFM_AUTO, 0); 2039 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2040 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2041 aprint_normal("\n"); 2042 2043 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2044 } 2045 2046 /* 2047 * pcn_79c970_mediastatus: [ifmedia interface function] 2048 * 2049 * Get the current interface media status (Am79c970 version). 2050 */ 2051 static void 2052 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2053 { 2054 struct pcn_softc *sc = ifp->if_softc; 2055 2056 /* 2057 * The currently selected media is always the active media. 2058 * Note: We have no way to determine what media the AUTO 2059 * process picked. 2060 */ 2061 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2062 } 2063 2064 /* 2065 * pcn_79c970_mediachange: [ifmedia interface function] 2066 * 2067 * Set hardware to newly-selected media (Am79c970 version). 2068 */ 2069 static int 2070 pcn_79c970_mediachange(struct ifnet *ifp) 2071 { 2072 struct pcn_softc *sc = ifp->if_softc; 2073 uint32_t reg; 2074 2075 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2076 /* 2077 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2078 */ 2079 reg = pcn_bcr_read(sc, LE_BCR2); 2080 reg |= LE_B2_ASEL; 2081 pcn_bcr_write(sc, LE_BCR2, reg); 2082 } else { 2083 /* 2084 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2085 */ 2086 reg = pcn_bcr_read(sc, LE_BCR2); 2087 reg &= ~LE_B2_ASEL; 2088 pcn_bcr_write(sc, LE_BCR2, reg); 2089 2090 reg = pcn_csr_read(sc, LE_CSR15); 2091 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2092 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2093 pcn_csr_write(sc, LE_CSR15, reg); 2094 } 2095 2096 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2097 reg = LE_B9_FDEN; 2098 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2099 reg |= LE_B9_AUIFD; 2100 pcn_bcr_write(sc, LE_BCR9, reg); 2101 } else 2102 pcn_bcr_write(sc, LE_BCR9, 0); 2103 2104 return (0); 2105 } 2106 2107 /* 2108 * pcn_79c971_mediainit: 2109 * 2110 * Initialize media for the Am79c971. 2111 */ 2112 static void 2113 pcn_79c971_mediainit(struct pcn_softc *sc) 2114 { 2115 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2116 2117 /* We have MII. */ 2118 sc->sc_flags |= PCN_F_HAS_MII; 2119 2120 /* 2121 * The built-in 10BASE-T interface is mapped to the MII 2122 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2123 * word that tells us which PHY to use. 2124 * This driver used to ignore all but the first PHY to 2125 * answer, but this code was removed to support multiple 2126 * external PHYs. As the default instance will be the first 2127 * one to answer, no harm is done by letting the possibly 2128 * non-connected internal PHY show up. 2129 */ 2130 2131 /* Initialize our media structures and probe the MII. */ 2132 sc->sc_mii.mii_ifp = ifp; 2133 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2134 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2135 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2136 2137 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2138 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2139 ether_mediastatus); 2140 2141 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2142 MII_OFFSET_ANY, 0); 2143 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2144 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2145 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2146 } else 2147 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2148 } 2149 2150 /* 2151 * pcn_mii_readreg: [mii interface function] 2152 * 2153 * Read a PHY register on the MII. 2154 */ 2155 static int 2156 pcn_mii_readreg(device_t self, int phy, int reg) 2157 { 2158 struct pcn_softc *sc = device_private(self); 2159 uint32_t rv; 2160 2161 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2162 rv = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2163 if (rv == 0xffff) 2164 return (0); 2165 2166 return (rv); 2167 } 2168 2169 /* 2170 * pcn_mii_writereg: [mii interface function] 2171 * 2172 * Write a PHY register on the MII. 2173 */ 2174 static void 2175 pcn_mii_writereg(device_t self, int phy, int reg, int val) 2176 { 2177 struct pcn_softc *sc = device_private(self); 2178 2179 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2180 pcn_bcr_write(sc, LE_BCR34, val); 2181 } 2182 2183 /* 2184 * pcn_mii_statchg: [mii interface function] 2185 * 2186 * Callback from MII layer when media changes. 2187 */ 2188 static void 2189 pcn_mii_statchg(struct ifnet *ifp) 2190 { 2191 struct pcn_softc *sc = ifp->if_softc; 2192 2193 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2194 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2195 else 2196 pcn_bcr_write(sc, LE_BCR9, 0); 2197 } 2198
Indexes created Fri Sep 26 20:09:58 GMT 2025