if_pcn.c revision 1.67
1 /* $NetBSD: if_pcn.c,v 1.67 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.67 2019/01/22 03:42:27 msaitoh Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rndsource.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txintr; /* Tx interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 275 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 276 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 277 278 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 279 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 280 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 281 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 282 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 283 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 284 struct evcnt sc_ev_txcopy; /* Tx copies required */ 285 #endif /* PCN_EVENT_COUNTERS */ 286 287 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 288 int sc_rcvfw; 289 290 const char * const *sc_xmtsp_desc; /* Tx start point info */ 291 int sc_xmtsp; 292 293 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 294 int sc_xmtfw; 295 296 int sc_flags; /* misc. flags; see below */ 297 int sc_swstyle; /* the software style in use */ 298 299 int sc_txfree; /* number of free Tx descriptors */ 300 int sc_txnext; /* next ready Tx descriptor */ 301 302 int sc_txsfree; /* number of free Tx jobs */ 303 int sc_txsnext; /* next free Tx job */ 304 int sc_txsdirty; /* dirty Tx jobs */ 305 306 int sc_rxptr; /* next ready Rx descriptor/job */ 307 308 uint32_t sc_csr5; /* prototype CSR5 register */ 309 uint32_t sc_mode; /* prototype MODE register */ 310 311 krndsource_t rnd_source; /* random source */ 312 }; 313 314 /* sc_flags */ 315 #define PCN_F_HAS_MII 0x0001 /* has MII */ 316 317 #ifdef PCN_EVENT_COUNTERS 318 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 319 #else 320 #define PCN_EVCNT_INCR(ev) /* nothing */ 321 #endif 322 323 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 324 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 325 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 326 327 #define PCN_CDTXSYNC(sc, x, n, ops) \ 328 do { \ 329 int __x, __n; \ 330 \ 331 __x = (x); \ 332 __n = (n); \ 333 \ 334 /* If it will wrap around, sync to the end of the ring. */ \ 335 if ((__x + __n) > PCN_NTXDESC) { \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 338 (PCN_NTXDESC - __x), (ops)); \ 339 __n -= (PCN_NTXDESC - __x); \ 340 __x = 0; \ 341 } \ 342 \ 343 /* Now sync whatever is left. */ \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 346 } while (/*CONSTCOND*/0) 347 348 #define PCN_CDRXSYNC(sc, x, ops) \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 351 352 #define PCN_CDINITSYNC(sc, ops) \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 355 356 #define PCN_INIT_RXDESC(sc, x) \ 357 do { \ 358 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 359 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 360 struct mbuf *__m = __rxs->rxs_mbuf; \ 361 \ 362 /* \ 363 * Note: We scoot the packet forward 2 bytes in the buffer \ 364 * so that the payload after the Ethernet header is aligned \ 365 * to a 4-byte boundary. \ 366 */ \ 367 __m->m_data = __m->m_ext.ext_buf + 2; \ 368 \ 369 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 370 __rmd->rmd2 = \ 371 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 372 __rmd->rmd0 = 0; \ 373 } else { \ 374 __rmd->rmd2 = 0; \ 375 __rmd->rmd0 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 } \ 378 __rmd->rmd1 = htole32(LE_R1_OWN|LE_R1_ONES| \ 379 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 380 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);\ 381 } while(/*CONSTCOND*/0) 382 383 static void pcn_start(struct ifnet *); 384 static void pcn_watchdog(struct ifnet *); 385 static int pcn_ioctl(struct ifnet *, u_long, void *); 386 static int pcn_init(struct ifnet *); 387 static void pcn_stop(struct ifnet *, int); 388 389 static bool pcn_shutdown(device_t, int); 390 391 static void pcn_reset(struct pcn_softc *); 392 static void pcn_rxdrain(struct pcn_softc *); 393 static int pcn_add_rxbuf(struct pcn_softc *, int); 394 static void pcn_tick(void *); 395 396 static void pcn_spnd(struct pcn_softc *); 397 398 static void pcn_set_filter(struct pcn_softc *); 399 400 static int pcn_intr(void *); 401 static void pcn_txintr(struct pcn_softc *); 402 static int pcn_rxintr(struct pcn_softc *); 403 404 static int pcn_mii_readreg(device_t, int, int, uint16_t *); 405 static int pcn_mii_writereg(device_t, int, int, uint16_t); 406 static void pcn_mii_statchg(struct ifnet *); 407 408 static void pcn_79c970_mediainit(struct pcn_softc *); 409 static int pcn_79c970_mediachange(struct ifnet *); 410 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 411 412 static void pcn_79c971_mediainit(struct pcn_softc *); 413 414 /* 415 * Description of a PCnet-PCI variant. Used to select media access 416 * method, mostly, and to print a nice description of the chip. 417 */ 418 static const struct pcn_variant { 419 const char *pcv_desc; 420 void (*pcv_mediainit)(struct pcn_softc *); 421 uint16_t pcv_chipid; 422 } pcn_variants[] = { 423 { "Am79c970 PCnet-PCI", 424 pcn_79c970_mediainit, 425 PARTID_Am79c970 }, 426 427 { "Am79c970A PCnet-PCI II", 428 pcn_79c970_mediainit, 429 PARTID_Am79c970A }, 430 431 { "Am79c971 PCnet-FAST", 432 pcn_79c971_mediainit, 433 PARTID_Am79c971 }, 434 435 { "Am79c972 PCnet-FAST+", 436 pcn_79c971_mediainit, 437 PARTID_Am79c972 }, 438 439 { "Am79c973 PCnet-FAST III", 440 pcn_79c971_mediainit, 441 PARTID_Am79c973 }, 442 443 { "Am79c975 PCnet-FAST III", 444 pcn_79c971_mediainit, 445 PARTID_Am79c975 }, 446 447 { "Unknown PCnet-PCI variant", 448 pcn_79c971_mediainit, 449 0 }, 450 }; 451 452 int pcn_copy_small = 0; 453 454 static int pcn_match(device_t, cfdata_t, void *); 455 static void pcn_attach(device_t, device_t, void *); 456 457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 458 pcn_match, pcn_attach, NULL, NULL); 459 460 /* 461 * Routines to read and write the PCnet-PCI CSR/BCR space. 462 */ 463 464 static inline uint32_t 465 pcn_csr_read(struct pcn_softc *sc, int reg) 466 { 467 468 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 469 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP)); 470 } 471 472 static inline void 473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 478 } 479 480 static inline uint32_t 481 pcn_bcr_read(struct pcn_softc *sc, int reg) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 return (bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP)); 486 } 487 488 static inline void 489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 494 } 495 496 static bool 497 pcn_is_vmware(const char *enaddr) 498 { 499 500 /* 501 * VMware uses the OUI 00:0c:29 for auto-generated MAC 502 * addresses. 503 */ 504 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 505 return (TRUE); 506 507 /* 508 * VMware uses the OUI 00:50:56 for manually-set MAC 509 * addresses (and some auto-generated ones). 510 */ 511 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 512 return (TRUE); 513 514 return (FALSE); 515 } 516 517 static const struct pcn_variant * 518 pcn_lookup_variant(uint16_t chipid) 519 { 520 const struct pcn_variant *pcv; 521 522 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 523 if (chipid == pcv->pcv_chipid) 524 return (pcv); 525 } 526 527 /* 528 * This covers unknown chips, which we simply treat like 529 * a generic PCnet-FAST. 530 */ 531 return (pcv); 532 } 533 534 static int 535 pcn_match(device_t parent, cfdata_t cf, void *aux) 536 { 537 struct pci_attach_args *pa = aux; 538 539 /* 540 * IBM Makes a PCI variant of this card which shows up as a 541 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 542 * this card is truly a pcn card, so we have a special case match for 543 * it 544 */ 545 546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 548 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 549 return(1); 550 551 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 552 return (0); 553 554 switch (PCI_PRODUCT(pa->pa_id)) { 555 case PCI_PRODUCT_AMD_PCNET_PCI: 556 /* Beat if_le_pci.c */ 557 return (10); 558 } 559 560 return (0); 561 } 562 563 static void 564 pcn_attach(device_t parent, device_t self, void *aux) 565 { 566 struct pcn_softc *sc = device_private(self); 567 struct pci_attach_args *pa = aux; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 pci_intr_handle_t ih; 571 const char *intrstr = NULL; 572 bus_space_tag_t iot, memt; 573 bus_space_handle_t ioh, memh; 574 bus_dma_segment_t seg; 575 int ioh_valid, memh_valid; 576 int ntxsegs, i, rseg, error; 577 uint32_t chipid, reg; 578 uint8_t enaddr[ETHER_ADDR_LEN]; 579 prop_object_t obj; 580 bool is_vmware; 581 char intrbuf[PCI_INTRSTR_LEN]; 582 583 sc->sc_dev = self; 584 callout_init(&sc->sc_tick_ch, 0); 585 586 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 587 588 /* 589 * Map the device. 590 */ 591 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 592 &iot, &ioh, NULL, NULL) == 0); 593 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 594 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 595 &memt, &memh, NULL, NULL) == 0); 596 597 if (memh_valid) { 598 sc->sc_st = memt; 599 sc->sc_sh = memh; 600 } else if (ioh_valid) { 601 sc->sc_st = iot; 602 sc->sc_sh = ioh; 603 } else { 604 aprint_error_dev(self, "unable to map device registers\n"); 605 return; 606 } 607 608 sc->sc_dmat = pa->pa_dmat; 609 610 /* Make sure bus mastering is enabled. */ 611 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 612 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 613 PCI_COMMAND_MASTER_ENABLE); 614 615 /* power up chip */ 616 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 617 NULL)) && error != EOPNOTSUPP) { 618 aprint_error_dev(self, "cannot activate %d\n", error); 619 return; 620 } 621 622 /* 623 * Reset the chip to a known state. This also puts the 624 * chip into 32-bit mode. 625 */ 626 pcn_reset(sc); 627 628 /* 629 * On some systems with the chip is an on-board device, the 630 * EEPROM is not used. Handle this by reading the MAC address 631 * from the CSRs (assuming that boot firmware has written 632 * it there). 633 */ 634 obj = prop_dictionary_get(device_properties(sc->sc_dev), 635 "am79c970-no-eeprom"); 636 if (prop_bool_true(obj)) { 637 for (i = 0; i < 3; i++) { 638 uint32_t val; 639 val = pcn_csr_read(sc, LE_CSR12 + i); 640 enaddr[2 * i] = val & 0xff; 641 enaddr[2 * i + 1] = (val >> 8) & 0xff; 642 } 643 } else { 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 646 PCN32_APROM + i); 647 } 648 } 649 650 /* Check to see if this is a VMware emulated network interface. */ 651 is_vmware = pcn_is_vmware(enaddr); 652 653 /* 654 * Now that the device is mapped, attempt to figure out what 655 * kind of chip we have. Note that IDL has all 32 bits of 656 * the chip ID when we're in 32-bit mode. 657 */ 658 chipid = pcn_csr_read(sc, LE_CSR88); 659 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 660 661 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 662 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 663 ether_sprintf(enaddr)); 664 665 /* 666 * VMware has a bug in its network interface emulation; we must 667 * limit the number of Tx segments. 668 */ 669 if (is_vmware) { 670 ntxsegs = PCN_NTXSEGS_VMWARE; 671 prop_dictionary_set_bool(device_properties(sc->sc_dev), 672 "am79c970-vmware-tx-bug", TRUE); 673 aprint_verbose_dev(self, 674 "VMware Tx segment count bug detected\n"); 675 } else { 676 ntxsegs = PCN_NTXSEGS; 677 } 678 679 /* 680 * Map and establish our interrupt. 681 */ 682 if (pci_intr_map(pa, &ih)) { 683 aprint_error_dev(self, "unable to map interrupt\n"); 684 return; 685 } 686 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 687 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, pcn_intr, sc, 688 device_xname(self)); 689 if (sc->sc_ih == NULL) { 690 aprint_error_dev(self, "unable to establish interrupt"); 691 if (intrstr != NULL) 692 aprint_error(" at %s", intrstr); 693 aprint_error("\n"); 694 return; 695 } 696 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 697 698 /* 699 * Allocate the control data structures, and create and load the 700 * DMA map for it. 701 */ 702 if ((error = bus_dmamem_alloc(sc->sc_dmat, 703 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 704 0)) != 0) { 705 aprint_error_dev(self, "unable to allocate control data, " 706 "error = %d\n", error); 707 goto fail_0; 708 } 709 710 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 711 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 712 BUS_DMA_COHERENT)) != 0) { 713 aprint_error_dev(self, "unable to map control data, " 714 "error = %d\n", error); 715 goto fail_1; 716 } 717 718 if ((error = bus_dmamap_create(sc->sc_dmat, 719 sizeof(struct pcn_control_data), 1, 720 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 721 aprint_error_dev(self, "unable to create control data DMA map, " 722 "error = %d\n", error); 723 goto fail_2; 724 } 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 727 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 728 0)) != 0) { 729 aprint_error_dev(self, 730 "unable to load control data DMA map, error = %d\n", error); 731 goto fail_3; 732 } 733 734 /* Create the transmit buffer DMA maps. */ 735 for (i = 0; i < PCN_TXQUEUELEN; i++) { 736 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 737 ntxsegs, MCLBYTES, 0, 0, 738 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 739 aprint_error_dev(self, 740 "unable to create tx DMA map %d, error = %d\n", 741 i, error); 742 goto fail_4; 743 } 744 } 745 746 /* Create the receive buffer DMA maps. */ 747 for (i = 0; i < PCN_NRXDESC; i++) { 748 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 749 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 750 aprint_error_dev(self, 751 "unable to create rx DMA map %d, error = %d\n", 752 i, error); 753 goto fail_5; 754 } 755 sc->sc_rxsoft[i].rxs_mbuf = NULL; 756 } 757 758 /* Initialize our media structures. */ 759 (*sc->sc_variant->pcv_mediainit)(sc); 760 761 /* 762 * Initialize FIFO watermark info. 763 */ 764 switch (sc->sc_variant->pcv_chipid) { 765 case PARTID_Am79c970: 766 case PARTID_Am79c970A: 767 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 768 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 769 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 770 break; 771 772 default: 773 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 774 /* 775 * Read BCR25 to determine how much SRAM is 776 * on the board. If > 0, then we the chip 777 * uses different Start Point thresholds. 778 * 779 * Note BCR25 and BCR26 are loaded from the 780 * EEPROM on RST, and unaffected by S_RESET, 781 * so we don't really have to worry about 782 * them except for this. 783 */ 784 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 785 if (reg != 0) 786 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 787 else 788 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 789 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 790 break; 791 } 792 793 /* 794 * Set up defaults -- see the tables above for what these 795 * values mean. 796 * 797 * XXX How should we tune RCVFW and XMTFW? 798 */ 799 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 800 sc->sc_xmtsp = 1; 801 sc->sc_xmtfw = 0; 802 803 ifp = &sc->sc_ethercom.ec_if; 804 strcpy(ifp->if_xname, device_xname(self)); 805 ifp->if_softc = sc; 806 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 807 ifp->if_ioctl = pcn_ioctl; 808 ifp->if_start = pcn_start; 809 ifp->if_watchdog = pcn_watchdog; 810 ifp->if_init = pcn_init; 811 ifp->if_stop = pcn_stop; 812 IFQ_SET_READY(&ifp->if_snd); 813 814 /* Attach the interface. */ 815 if_attach(ifp); 816 if_deferred_start_init(ifp, NULL); 817 ether_ifattach(ifp, enaddr); 818 rnd_attach_source(&sc->rnd_source, device_xname(self), 819 RND_TYPE_NET, RND_FLAG_DEFAULT); 820 821 #ifdef PCN_EVENT_COUNTERS 822 /* Attach event counters. */ 823 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 824 NULL, device_xname(self), "txsstall"); 825 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 826 NULL, device_xname(self), "txdstall"); 827 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 828 NULL, device_xname(self), "txintr"); 829 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 830 NULL, device_xname(self), "rxintr"); 831 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 832 NULL, device_xname(self), "babl"); 833 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 834 NULL, device_xname(self), "miss"); 835 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 836 NULL, device_xname(self), "merr"); 837 838 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 839 NULL, device_xname(self), "txseg1"); 840 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 841 NULL, device_xname(self), "txseg2"); 842 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 843 NULL, device_xname(self), "txseg3"); 844 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 845 NULL, device_xname(self), "txseg4"); 846 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 847 NULL, device_xname(self), "txseg5"); 848 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 849 NULL, device_xname(self), "txsegmore"); 850 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 851 NULL, device_xname(self), "txcopy"); 852 #endif /* PCN_EVENT_COUNTERS */ 853 854 /* 855 * Establish power handler with shutdown hook, to make sure 856 * the interface is shutdown during reboot. 857 */ 858 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 859 pmf_class_network_register(self, ifp); 860 else 861 aprint_error_dev(self, "couldn't establish power handler\n"); 862 863 return; 864 865 /* 866 * Free any resources we've allocated during the failed attach 867 * attempt. Do this in reverse order and fall through. 868 */ 869 fail_5: 870 for (i = 0; i < PCN_NRXDESC; i++) { 871 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 872 bus_dmamap_destroy(sc->sc_dmat, 873 sc->sc_rxsoft[i].rxs_dmamap); 874 } 875 fail_4: 876 for (i = 0; i < PCN_TXQUEUELEN; i++) { 877 if (sc->sc_txsoft[i].txs_dmamap != NULL) 878 bus_dmamap_destroy(sc->sc_dmat, 879 sc->sc_txsoft[i].txs_dmamap); 880 } 881 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 882 fail_3: 883 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 884 fail_2: 885 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 886 sizeof(struct pcn_control_data)); 887 fail_1: 888 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 889 fail_0: 890 return; 891 } 892 893 /* 894 * pcn_shutdown: 895 * 896 * Make sure the interface is stopped at reboot time. 897 */ 898 static bool 899 pcn_shutdown(device_t self, int howto) 900 { 901 struct pcn_softc *sc = device_private(self); 902 903 pcn_stop(&sc->sc_ethercom.ec_if, 1); 904 /* explicitly reset the chip for some onboard one with lazy firmware */ 905 pcn_reset(sc); 906 907 return true; 908 } 909 910 /* 911 * pcn_start: [ifnet interface function] 912 * 913 * Start packet transmission on the interface. 914 */ 915 static void 916 pcn_start(struct ifnet *ifp) 917 { 918 struct pcn_softc *sc = ifp->if_softc; 919 struct mbuf *m0, *m; 920 struct pcn_txsoft *txs; 921 bus_dmamap_t dmamap; 922 int error, nexttx, lasttx = -1, ofree, seg; 923 924 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 925 return; 926 927 /* 928 * Remember the previous number of free descriptors and 929 * the first descriptor we'll use. 930 */ 931 ofree = sc->sc_txfree; 932 933 /* 934 * Loop through the send queue, setting up transmit descriptors 935 * until we drain the queue, or use up all available transmit 936 * descriptors. 937 */ 938 for (;;) { 939 /* Grab a packet off the queue. */ 940 IFQ_POLL(&ifp->if_snd, m0); 941 if (m0 == NULL) 942 break; 943 m = NULL; 944 945 /* Get a work queue entry. */ 946 if (sc->sc_txsfree == 0) { 947 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 948 break; 949 } 950 951 txs = &sc->sc_txsoft[sc->sc_txsnext]; 952 dmamap = txs->txs_dmamap; 953 954 /* 955 * Load the DMA map. If this fails, the packet either 956 * didn't fit in the alloted number of segments, or we 957 * were short on resources. In this case, we'll copy 958 * and try again. 959 */ 960 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 961 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 962 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 963 MGETHDR(m, M_DONTWAIT, MT_DATA); 964 if (m == NULL) { 965 printf("%s: unable to allocate Tx mbuf\n", 966 device_xname(sc->sc_dev)); 967 break; 968 } 969 if (m0->m_pkthdr.len > MHLEN) { 970 MCLGET(m, M_DONTWAIT); 971 if ((m->m_flags & M_EXT) == 0) { 972 printf("%s: unable to allocate Tx " 973 "cluster\n", 974 device_xname(sc->sc_dev)); 975 m_freem(m); 976 break; 977 } 978 } 979 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 980 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 981 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 982 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 983 if (error) { 984 printf("%s: unable to load Tx buffer, " 985 "error = %d\n", device_xname(sc->sc_dev), 986 error); 987 m_freem(m); 988 break; 989 } 990 } 991 992 /* 993 * Ensure we have enough descriptors free to describe 994 * the packet. Note, we always reserve one descriptor 995 * at the end of the ring as a termination point, to 996 * prevent wrap-around. 997 */ 998 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 999 /* 1000 * Not enough free descriptors to transmit this 1001 * packet. We haven't committed anything yet, 1002 * so just unload the DMA map, put the packet 1003 * back on the queue, and punt. Notify the upper 1004 * layer that there are not more slots left. 1005 * 1006 * XXX We could allocate an mbuf and copy, but 1007 * XXX is it worth it? 1008 */ 1009 ifp->if_flags |= IFF_OACTIVE; 1010 bus_dmamap_unload(sc->sc_dmat, dmamap); 1011 if (m != NULL) 1012 m_freem(m); 1013 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1014 break; 1015 } 1016 1017 IFQ_DEQUEUE(&ifp->if_snd, m0); 1018 if (m != NULL) { 1019 m_freem(m0); 1020 m0 = m; 1021 } 1022 1023 /* 1024 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1025 */ 1026 1027 /* Sync the DMA map. */ 1028 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1029 BUS_DMASYNC_PREWRITE); 1030 1031 #ifdef PCN_EVENT_COUNTERS 1032 switch (dmamap->dm_nsegs) { 1033 case 1: 1034 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1035 break; 1036 case 2: 1037 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1038 break; 1039 case 3: 1040 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1041 break; 1042 case 4: 1043 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1044 break; 1045 case 5: 1046 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1047 break; 1048 default: 1049 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1050 break; 1051 } 1052 #endif /* PCN_EVENT_COUNTERS */ 1053 1054 /* 1055 * Initialize the transmit descriptors. 1056 */ 1057 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1058 for (nexttx = sc->sc_txnext, seg = 0; 1059 seg < dmamap->dm_nsegs; 1060 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1061 /* 1062 * If this is the first descriptor we're 1063 * enqueueing, don't set the OWN bit just 1064 * yet. That could cause a race condition. 1065 * We'll do it below. 1066 */ 1067 sc->sc_txdescs[nexttx].tmd0 = 0; 1068 sc->sc_txdescs[nexttx].tmd2 = 1069 htole32(dmamap->dm_segs[seg].ds_addr); 1070 sc->sc_txdescs[nexttx].tmd1 = 1071 htole32(LE_T1_ONES | 1072 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1073 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1074 LE_T1_BCNT_MASK)); 1075 lasttx = nexttx; 1076 } 1077 } else { 1078 for (nexttx = sc->sc_txnext, seg = 0; 1079 seg < dmamap->dm_nsegs; 1080 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1081 /* 1082 * If this is the first descriptor we're 1083 * enqueueing, don't set the OWN bit just 1084 * yet. That could cause a race condition. 1085 * We'll do it below. 1086 */ 1087 sc->sc_txdescs[nexttx].tmd0 = 1088 htole32(dmamap->dm_segs[seg].ds_addr); 1089 sc->sc_txdescs[nexttx].tmd2 = 0; 1090 sc->sc_txdescs[nexttx].tmd1 = 1091 htole32(LE_T1_ONES | 1092 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1093 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1094 LE_T1_BCNT_MASK)); 1095 lasttx = nexttx; 1096 } 1097 } 1098 1099 KASSERT(lasttx != -1); 1100 /* Interrupt on the packet, if appropriate. */ 1101 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1102 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1103 1104 /* Set `start of packet' and `end of packet' appropriately. */ 1105 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1106 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1107 htole32(LE_T1_OWN|LE_T1_STP); 1108 1109 /* Sync the descriptors we're using. */ 1110 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1111 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1112 1113 /* Kick the transmitter. */ 1114 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_TDMD); 1115 1116 /* 1117 * Store a pointer to the packet so we can free it later, 1118 * and remember what txdirty will be once the packet is 1119 * done. 1120 */ 1121 txs->txs_mbuf = m0; 1122 txs->txs_firstdesc = sc->sc_txnext; 1123 txs->txs_lastdesc = lasttx; 1124 1125 /* Advance the tx pointer. */ 1126 sc->sc_txfree -= dmamap->dm_nsegs; 1127 sc->sc_txnext = nexttx; 1128 1129 sc->sc_txsfree--; 1130 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1131 1132 /* Pass the packet to any BPF listeners. */ 1133 bpf_mtap(ifp, m0, BPF_D_OUT); 1134 } 1135 1136 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1137 /* No more slots left; notify upper layer. */ 1138 ifp->if_flags |= IFF_OACTIVE; 1139 } 1140 1141 if (sc->sc_txfree != ofree) { 1142 /* Set a watchdog timer in case the chip flakes out. */ 1143 ifp->if_timer = 5; 1144 } 1145 } 1146 1147 /* 1148 * pcn_watchdog: [ifnet interface function] 1149 * 1150 * Watchdog timer handler. 1151 */ 1152 static void 1153 pcn_watchdog(struct ifnet *ifp) 1154 { 1155 struct pcn_softc *sc = ifp->if_softc; 1156 1157 /* 1158 * Since we're not interrupting every packet, sweep 1159 * up before we report an error. 1160 */ 1161 pcn_txintr(sc); 1162 1163 if (sc->sc_txfree != PCN_NTXDESC) { 1164 printf("%s: device timeout (txfree %d txsfree %d)\n", 1165 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1166 ifp->if_oerrors++; 1167 1168 /* Reset the interface. */ 1169 (void) pcn_init(ifp); 1170 } 1171 1172 /* Try to get more packets going. */ 1173 pcn_start(ifp); 1174 } 1175 1176 /* 1177 * pcn_ioctl: [ifnet interface function] 1178 * 1179 * Handle control requests from the operator. 1180 */ 1181 static int 1182 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1183 { 1184 struct pcn_softc *sc = ifp->if_softc; 1185 struct ifreq *ifr = (struct ifreq *) data; 1186 int s, error; 1187 1188 s = splnet(); 1189 1190 switch (cmd) { 1191 case SIOCSIFMEDIA: 1192 case SIOCGIFMEDIA: 1193 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1194 break; 1195 1196 default: 1197 error = ether_ioctl(ifp, cmd, data); 1198 if (error == ENETRESET) { 1199 /* 1200 * Multicast list has changed; set the hardware filter 1201 * accordingly. 1202 */ 1203 if (ifp->if_flags & IFF_RUNNING) 1204 error = pcn_init(ifp); 1205 else 1206 error = 0; 1207 } 1208 break; 1209 } 1210 1211 /* Try to get more packets going. */ 1212 pcn_start(ifp); 1213 1214 splx(s); 1215 return (error); 1216 } 1217 1218 /* 1219 * pcn_intr: 1220 * 1221 * Interrupt service routine. 1222 */ 1223 static int 1224 pcn_intr(void *arg) 1225 { 1226 struct pcn_softc *sc = arg; 1227 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1228 uint32_t csr0; 1229 int wantinit, handled = 0; 1230 1231 for (wantinit = 0; wantinit == 0;) { 1232 csr0 = pcn_csr_read(sc, LE_CSR0); 1233 if ((csr0 & LE_C0_INTR) == 0) 1234 break; 1235 1236 rnd_add_uint32(&sc->rnd_source, csr0); 1237 1238 /* ACK the bits and re-enable interrupts. */ 1239 pcn_csr_write(sc, LE_CSR0, csr0 & 1240 (LE_C0_INEA|LE_C0_BABL|LE_C0_MISS|LE_C0_MERR|LE_C0_RINT| 1241 LE_C0_TINT|LE_C0_IDON)); 1242 1243 handled = 1; 1244 1245 if (csr0 & LE_C0_RINT) { 1246 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1247 wantinit = pcn_rxintr(sc); 1248 } 1249 1250 if (csr0 & LE_C0_TINT) { 1251 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1252 pcn_txintr(sc); 1253 } 1254 1255 if (csr0 & LE_C0_ERR) { 1256 if (csr0 & LE_C0_BABL) { 1257 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1258 ifp->if_oerrors++; 1259 } 1260 if (csr0 & LE_C0_MISS) { 1261 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1262 ifp->if_ierrors++; 1263 } 1264 if (csr0 & LE_C0_MERR) { 1265 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1266 printf("%s: memory error\n", 1267 device_xname(sc->sc_dev)); 1268 wantinit = 1; 1269 break; 1270 } 1271 } 1272 1273 if ((csr0 & LE_C0_RXON) == 0) { 1274 printf("%s: receiver disabled\n", 1275 device_xname(sc->sc_dev)); 1276 ifp->if_ierrors++; 1277 wantinit = 1; 1278 } 1279 1280 if ((csr0 & LE_C0_TXON) == 0) { 1281 printf("%s: transmitter disabled\n", 1282 device_xname(sc->sc_dev)); 1283 ifp->if_oerrors++; 1284 wantinit = 1; 1285 } 1286 } 1287 1288 if (handled) { 1289 if (wantinit) 1290 pcn_init(ifp); 1291 1292 /* Try to get more packets going. */ 1293 if_schedule_deferred_start(ifp); 1294 } 1295 1296 return (handled); 1297 } 1298 1299 /* 1300 * pcn_spnd: 1301 * 1302 * Suspend the chip. 1303 */ 1304 static void 1305 pcn_spnd(struct pcn_softc *sc) 1306 { 1307 int i; 1308 1309 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1310 1311 for (i = 0; i < 10000; i++) { 1312 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1313 return; 1314 delay(5); 1315 } 1316 1317 printf("%s: WARNING: chip failed to enter suspended state\n", 1318 device_xname(sc->sc_dev)); 1319 } 1320 1321 /* 1322 * pcn_txintr: 1323 * 1324 * Helper; handle transmit interrupts. 1325 */ 1326 static void 1327 pcn_txintr(struct pcn_softc *sc) 1328 { 1329 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1330 struct pcn_txsoft *txs; 1331 uint32_t tmd1, tmd2, tmd; 1332 int i, j; 1333 1334 ifp->if_flags &= ~IFF_OACTIVE; 1335 1336 /* 1337 * Go through our Tx list and free mbufs for those 1338 * frames which have been transmitted. 1339 */ 1340 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1341 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1342 txs = &sc->sc_txsoft[i]; 1343 1344 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1345 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1346 1347 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1348 if (tmd1 & LE_T1_OWN) 1349 break; 1350 1351 /* 1352 * Slightly annoying -- we have to loop through the 1353 * descriptors we've used looking for ERR, since it 1354 * can appear on any descriptor in the chain. 1355 */ 1356 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1357 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1358 if (tmd & LE_T1_ERR) { 1359 ifp->if_oerrors++; 1360 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1361 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1362 else 1363 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1364 if (tmd2 & LE_T2_UFLO) { 1365 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1366 sc->sc_xmtsp++; 1367 printf("%s: transmit " 1368 "underrun; new threshold: " 1369 "%s\n", 1370 device_xname(sc->sc_dev), 1371 sc->sc_xmtsp_desc[ 1372 sc->sc_xmtsp]); 1373 pcn_spnd(sc); 1374 pcn_csr_write(sc, LE_CSR80, 1375 LE_C80_RCVFW(sc->sc_rcvfw) | 1376 LE_C80_XMTSP(sc->sc_xmtsp) | 1377 LE_C80_XMTFW(sc->sc_xmtfw)); 1378 pcn_csr_write(sc, LE_CSR5, 1379 sc->sc_csr5); 1380 } else { 1381 printf("%s: transmit " 1382 "underrun\n", 1383 device_xname(sc->sc_dev)); 1384 } 1385 } else if (tmd2 & LE_T2_BUFF) { 1386 printf("%s: transmit buffer error\n", 1387 device_xname(sc->sc_dev)); 1388 } 1389 if (tmd2 & LE_T2_LCOL) 1390 ifp->if_collisions++; 1391 if (tmd2 & LE_T2_RTRY) 1392 ifp->if_collisions += 16; 1393 goto next_packet; 1394 } 1395 if (j == txs->txs_lastdesc) 1396 break; 1397 } 1398 if (tmd1 & LE_T1_ONE) 1399 ifp->if_collisions++; 1400 else if (tmd & LE_T1_MORE) { 1401 /* Real number is unknown. */ 1402 ifp->if_collisions += 2; 1403 } 1404 ifp->if_opackets++; 1405 next_packet: 1406 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1407 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1408 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1409 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1410 m_freem(txs->txs_mbuf); 1411 txs->txs_mbuf = NULL; 1412 } 1413 1414 /* Update the dirty transmit buffer pointer. */ 1415 sc->sc_txsdirty = i; 1416 1417 /* 1418 * If there are no more pending transmissions, cancel the watchdog 1419 * timer. 1420 */ 1421 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1422 ifp->if_timer = 0; 1423 } 1424 1425 /* 1426 * pcn_rxintr: 1427 * 1428 * Helper; handle receive interrupts. 1429 */ 1430 static int 1431 pcn_rxintr(struct pcn_softc *sc) 1432 { 1433 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1434 struct pcn_rxsoft *rxs; 1435 struct mbuf *m; 1436 uint32_t rmd1; 1437 int i, len; 1438 1439 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1440 rxs = &sc->sc_rxsoft[i]; 1441 1442 PCN_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1443 1444 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1445 1446 if (rmd1 & LE_R1_OWN) 1447 break; 1448 1449 /* 1450 * Check for errors and make sure the packet fit into 1451 * a single buffer. We have structured this block of 1452 * code the way it is in order to compress it into 1453 * one test in the common case (no error). 1454 */ 1455 if (__predict_false((rmd1 & (LE_R1_STP|LE_R1_ENP|LE_R1_ERR)) != 1456 (LE_R1_STP|LE_R1_ENP))) { 1457 /* Make sure the packet is in a single buffer. */ 1458 if ((rmd1 & (LE_R1_STP|LE_R1_ENP)) != 1459 (LE_R1_STP|LE_R1_ENP)) { 1460 printf("%s: packet spilled into next buffer\n", 1461 device_xname(sc->sc_dev)); 1462 return (1); /* pcn_intr() will re-init */ 1463 } 1464 1465 /* 1466 * If the packet had an error, simple recycle the 1467 * buffer. 1468 */ 1469 if (rmd1 & LE_R1_ERR) { 1470 ifp->if_ierrors++; 1471 /* 1472 * If we got an overflow error, chances 1473 * are there will be a CRC error. In 1474 * this case, just print the overflow 1475 * error, and skip the others. 1476 */ 1477 if (rmd1 & LE_R1_OFLO) 1478 printf("%s: overflow error\n", 1479 device_xname(sc->sc_dev)); 1480 else { 1481 #define PRINTIT(x, str) \ 1482 if (rmd1 & (x)) \ 1483 printf("%s: %s\n", \ 1484 device_xname(sc->sc_dev), \ 1485 str); 1486 PRINTIT(LE_R1_FRAM, "framing error"); 1487 PRINTIT(LE_R1_CRC, "CRC error"); 1488 PRINTIT(LE_R1_BUFF, "buffer error"); 1489 } 1490 #undef PRINTIT 1491 PCN_INIT_RXDESC(sc, i); 1492 continue; 1493 } 1494 } 1495 1496 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1497 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1498 1499 /* 1500 * No errors; receive the packet. 1501 */ 1502 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1503 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1504 else 1505 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1506 1507 /* 1508 * The LANCE family includes the CRC with every packet; 1509 * trim it off here. 1510 */ 1511 len -= ETHER_CRC_LEN; 1512 1513 /* 1514 * If the packet is small enough to fit in a 1515 * single header mbuf, allocate one and copy 1516 * the data into it. This greatly reduces 1517 * memory consumption when we receive lots 1518 * of small packets. 1519 * 1520 * Otherwise, we add a new buffer to the receive 1521 * chain. If this fails, we drop the packet and 1522 * recycle the old buffer. 1523 */ 1524 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1525 MGETHDR(m, M_DONTWAIT, MT_DATA); 1526 if (m == NULL) 1527 goto dropit; 1528 m->m_data += 2; 1529 memcpy(mtod(m, void *), 1530 mtod(rxs->rxs_mbuf, void *), len); 1531 PCN_INIT_RXDESC(sc, i); 1532 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1533 rxs->rxs_dmamap->dm_mapsize, 1534 BUS_DMASYNC_PREREAD); 1535 } else { 1536 m = rxs->rxs_mbuf; 1537 if (pcn_add_rxbuf(sc, i) != 0) { 1538 dropit: 1539 ifp->if_ierrors++; 1540 PCN_INIT_RXDESC(sc, i); 1541 bus_dmamap_sync(sc->sc_dmat, 1542 rxs->rxs_dmamap, 0, 1543 rxs->rxs_dmamap->dm_mapsize, 1544 BUS_DMASYNC_PREREAD); 1545 continue; 1546 } 1547 } 1548 1549 m_set_rcvif(m, ifp); 1550 m->m_pkthdr.len = m->m_len = len; 1551 1552 /* Pass it on. */ 1553 if_percpuq_enqueue(ifp->if_percpuq, m); 1554 } 1555 1556 /* Update the receive pointer. */ 1557 sc->sc_rxptr = i; 1558 return (0); 1559 } 1560 1561 /* 1562 * pcn_tick: 1563 * 1564 * One second timer, used to tick the MII. 1565 */ 1566 static void 1567 pcn_tick(void *arg) 1568 { 1569 struct pcn_softc *sc = arg; 1570 int s; 1571 1572 s = splnet(); 1573 mii_tick(&sc->sc_mii); 1574 splx(s); 1575 1576 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1577 } 1578 1579 /* 1580 * pcn_reset: 1581 * 1582 * Perform a soft reset on the PCnet-PCI. 1583 */ 1584 static void 1585 pcn_reset(struct pcn_softc *sc) 1586 { 1587 1588 /* 1589 * The PCnet-PCI chip is reset by reading from the 1590 * RESET register. Note that while the NE2100 LANCE 1591 * boards require a write after the read, the PCnet-PCI 1592 * chips do not require this. 1593 * 1594 * Since we don't know if we're in 16-bit or 32-bit 1595 * mode right now, issue both (it's safe) in the 1596 * hopes that one will succeed. 1597 */ 1598 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1599 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1600 1601 /* Wait 1ms for it to finish. */ 1602 delay(1000); 1603 1604 /* 1605 * Select 32-bit I/O mode by issuing a 32-bit write to the 1606 * RDP. Since the RAP is 0 after a reset, writing a 0 1607 * to RDP is safe (since it simply clears CSR0). 1608 */ 1609 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1610 } 1611 1612 /* 1613 * pcn_init: [ifnet interface function] 1614 * 1615 * Initialize the interface. Must be called at splnet(). 1616 */ 1617 static int 1618 pcn_init(struct ifnet *ifp) 1619 { 1620 struct pcn_softc *sc = ifp->if_softc; 1621 struct pcn_rxsoft *rxs; 1622 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1623 int i, error = 0; 1624 uint32_t reg; 1625 1626 /* Cancel any pending I/O. */ 1627 pcn_stop(ifp, 0); 1628 1629 /* Reset the chip to a known state. */ 1630 pcn_reset(sc); 1631 1632 /* 1633 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1634 * else. 1635 * 1636 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1637 * because the structure layout is compatible with ILACC, 1638 * but the burst mode is only available in SSTYLE 3, and 1639 * burst mode should provide some performance enhancement. 1640 */ 1641 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1642 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1643 else 1644 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1645 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1646 1647 /* Initialize the transmit descriptor ring. */ 1648 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1649 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1650 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1651 sc->sc_txfree = PCN_NTXDESC; 1652 sc->sc_txnext = 0; 1653 1654 /* Initialize the transmit job descriptors. */ 1655 for (i = 0; i < PCN_TXQUEUELEN; i++) 1656 sc->sc_txsoft[i].txs_mbuf = NULL; 1657 sc->sc_txsfree = PCN_TXQUEUELEN; 1658 sc->sc_txsnext = 0; 1659 sc->sc_txsdirty = 0; 1660 1661 /* 1662 * Initialize the receive descriptor and receive job 1663 * descriptor rings. 1664 */ 1665 for (i = 0; i < PCN_NRXDESC; i++) { 1666 rxs = &sc->sc_rxsoft[i]; 1667 if (rxs->rxs_mbuf == NULL) { 1668 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1669 printf("%s: unable to allocate or map rx " 1670 "buffer %d, error = %d\n", 1671 device_xname(sc->sc_dev), i, error); 1672 /* 1673 * XXX Should attempt to run with fewer receive 1674 * XXX buffers instead of just failing. 1675 */ 1676 pcn_rxdrain(sc); 1677 goto out; 1678 } 1679 } else 1680 PCN_INIT_RXDESC(sc, i); 1681 } 1682 sc->sc_rxptr = 0; 1683 1684 /* Initialize MODE for the initialization block. */ 1685 sc->sc_mode = 0; 1686 if (ifp->if_flags & IFF_PROMISC) 1687 sc->sc_mode |= LE_C15_PROM; 1688 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1689 sc->sc_mode |= LE_C15_DRCVBC; 1690 1691 /* 1692 * If we have MII, simply select MII in the MODE register, 1693 * and clear ASEL. Otherwise, let ASEL stand (for now), 1694 * and leave PORTSEL alone (it is ignored with ASEL is set). 1695 */ 1696 if (sc->sc_flags & PCN_F_HAS_MII) { 1697 pcn_bcr_write(sc, LE_BCR2, 1698 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1699 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1700 1701 /* 1702 * Disable MII auto-negotiation. We handle that in 1703 * our own MII layer. 1704 */ 1705 pcn_bcr_write(sc, LE_BCR32, 1706 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1707 } 1708 1709 /* 1710 * Set the Tx and Rx descriptor ring addresses in the init 1711 * block, the TLEN and RLEN other fields of the init block 1712 * MODE register. 1713 */ 1714 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1715 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1716 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1717 ((ffs(PCN_NTXDESC) - 1) << 28) | 1718 ((ffs(PCN_NRXDESC) - 1) << 20)); 1719 1720 /* Set the station address in the init block. */ 1721 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1722 (enaddr[1] << 8) | (enaddr[2] << 16) | (enaddr[3] << 24)); 1723 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1724 (enaddr[5] << 8)); 1725 1726 /* Set the multicast filter in the init block. */ 1727 pcn_set_filter(sc); 1728 1729 /* Initialize CSR3. */ 1730 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM|LE_C3_IDONM|LE_C3_DXSUFLO); 1731 1732 /* Initialize CSR4. */ 1733 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS|LE_C4_APAD_XMT| 1734 LE_C4_MFCOM|LE_C4_RCVCCOM|LE_C4_TXSTRTM); 1735 1736 /* Initialize CSR5. */ 1737 sc->sc_csr5 = LE_C5_LTINTEN|LE_C5_SINTE; 1738 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1739 1740 /* 1741 * If we have an Am79c971 or greater, initialize CSR7. 1742 * 1743 * XXX Might be nice to use the MII auto-poll interrupt someday. 1744 */ 1745 switch (sc->sc_variant->pcv_chipid) { 1746 case PARTID_Am79c970: 1747 case PARTID_Am79c970A: 1748 /* Not available on these chips. */ 1749 break; 1750 1751 default: 1752 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1753 break; 1754 } 1755 1756 /* 1757 * On the Am79c970A and greater, initialize BCR18 to 1758 * enable burst mode. 1759 * 1760 * Also enable the "no underflow" option on the Am79c971 and 1761 * higher, which prevents the chip from generating transmit 1762 * underflows, yet sill provides decent performance. Note if 1763 * chip is not connected to external SRAM, then we still have 1764 * to handle underflow errors (the NOUFLO bit is ignored in 1765 * that case). 1766 */ 1767 reg = pcn_bcr_read(sc, LE_BCR18); 1768 switch (sc->sc_variant->pcv_chipid) { 1769 case PARTID_Am79c970: 1770 break; 1771 1772 case PARTID_Am79c970A: 1773 reg |= LE_B18_BREADE|LE_B18_BWRITE; 1774 break; 1775 1776 default: 1777 reg |= LE_B18_BREADE|LE_B18_BWRITE|LE_B18_NOUFLO; 1778 break; 1779 } 1780 pcn_bcr_write(sc, LE_BCR18, reg); 1781 1782 /* 1783 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1784 */ 1785 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1786 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1787 1788 /* 1789 * Send the init block to the chip, and wait for it 1790 * to be processed. 1791 */ 1792 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1793 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1794 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1795 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1796 delay(100); 1797 for (i = 0; i < 10000; i++) { 1798 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1799 break; 1800 delay(10); 1801 } 1802 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1803 if (i == 10000) { 1804 printf("%s: timeout processing init block\n", 1805 device_xname(sc->sc_dev)); 1806 error = EIO; 1807 goto out; 1808 } 1809 1810 /* Set the media. */ 1811 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1812 goto out; 1813 1814 /* Enable interrupts and external activity (and ACK IDON). */ 1815 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA|LE_C0_STRT|LE_C0_IDON); 1816 1817 if (sc->sc_flags & PCN_F_HAS_MII) { 1818 /* Start the one second MII clock. */ 1819 callout_reset(&sc->sc_tick_ch, hz, pcn_tick, sc); 1820 } 1821 1822 /* ...all done! */ 1823 ifp->if_flags |= IFF_RUNNING; 1824 ifp->if_flags &= ~IFF_OACTIVE; 1825 1826 out: 1827 if (error) 1828 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1829 return (error); 1830 } 1831 1832 /* 1833 * pcn_rxdrain: 1834 * 1835 * Drain the receive queue. 1836 */ 1837 static void 1838 pcn_rxdrain(struct pcn_softc *sc) 1839 { 1840 struct pcn_rxsoft *rxs; 1841 int i; 1842 1843 for (i = 0; i < PCN_NRXDESC; i++) { 1844 rxs = &sc->sc_rxsoft[i]; 1845 if (rxs->rxs_mbuf != NULL) { 1846 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1847 m_freem(rxs->rxs_mbuf); 1848 rxs->rxs_mbuf = NULL; 1849 } 1850 } 1851 } 1852 1853 /* 1854 * pcn_stop: [ifnet interface function] 1855 * 1856 * Stop transmission on the interface. 1857 */ 1858 static void 1859 pcn_stop(struct ifnet *ifp, int disable) 1860 { 1861 struct pcn_softc *sc = ifp->if_softc; 1862 struct pcn_txsoft *txs; 1863 int i; 1864 1865 if (sc->sc_flags & PCN_F_HAS_MII) { 1866 /* Stop the one second clock. */ 1867 callout_stop(&sc->sc_tick_ch); 1868 1869 /* Down the MII. */ 1870 mii_down(&sc->sc_mii); 1871 } 1872 1873 /* Stop the chip. */ 1874 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1875 1876 /* Release any queued transmit buffers. */ 1877 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1878 txs = &sc->sc_txsoft[i]; 1879 if (txs->txs_mbuf != NULL) { 1880 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1881 m_freem(txs->txs_mbuf); 1882 txs->txs_mbuf = NULL; 1883 } 1884 } 1885 1886 /* Mark the interface as down and cancel the watchdog timer. */ 1887 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1888 ifp->if_timer = 0; 1889 1890 if (disable) 1891 pcn_rxdrain(sc); 1892 } 1893 1894 /* 1895 * pcn_add_rxbuf: 1896 * 1897 * Add a receive buffer to the indicated descriptor. 1898 */ 1899 static int 1900 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1901 { 1902 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1903 struct mbuf *m; 1904 int error; 1905 1906 MGETHDR(m, M_DONTWAIT, MT_DATA); 1907 if (m == NULL) 1908 return (ENOBUFS); 1909 1910 MCLGET(m, M_DONTWAIT); 1911 if ((m->m_flags & M_EXT) == 0) { 1912 m_freem(m); 1913 return (ENOBUFS); 1914 } 1915 1916 if (rxs->rxs_mbuf != NULL) 1917 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1918 1919 rxs->rxs_mbuf = m; 1920 1921 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1922 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1923 BUS_DMA_READ|BUS_DMA_NOWAIT); 1924 if (error) { 1925 printf("%s: can't load rx DMA map %d, error = %d\n", 1926 device_xname(sc->sc_dev), idx, error); 1927 panic("pcn_add_rxbuf"); 1928 } 1929 1930 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1931 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1932 1933 PCN_INIT_RXDESC(sc, idx); 1934 1935 return (0); 1936 } 1937 1938 /* 1939 * pcn_set_filter: 1940 * 1941 * Set up the receive filter. 1942 */ 1943 static void 1944 pcn_set_filter(struct pcn_softc *sc) 1945 { 1946 struct ethercom *ec = &sc->sc_ethercom; 1947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1948 struct ether_multi *enm; 1949 struct ether_multistep step; 1950 uint32_t crc; 1951 1952 /* 1953 * Set up the multicast address filter by passing all multicast 1954 * addresses through a CRC generator, and then using the high 1955 * order 6 bits as an index into the 64-bit logical address 1956 * filter. The high order bits select the word, while the rest 1957 * of the bits select the bit within the word. 1958 */ 1959 1960 if (ifp->if_flags & IFF_PROMISC) 1961 goto allmulti; 1962 1963 sc->sc_initblock.init_ladrf[0] = 1964 sc->sc_initblock.init_ladrf[1] = 1965 sc->sc_initblock.init_ladrf[2] = 1966 sc->sc_initblock.init_ladrf[3] = 0; 1967 1968 ETHER_FIRST_MULTI(step, ec, enm); 1969 while (enm != NULL) { 1970 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1971 /* 1972 * We must listen to a range of multicast addresses. 1973 * For now, just accept all multicasts, rather than 1974 * trying to set only those filter bits needed to match 1975 * the range. (At this time, the only use of address 1976 * ranges is for IP multicast routing, for which the 1977 * range is big enough to require all bits set.) 1978 */ 1979 goto allmulti; 1980 } 1981 1982 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1983 1984 /* Just want the 6 most significant bits. */ 1985 crc >>= 26; 1986 1987 /* Set the corresponding bit in the filter. */ 1988 sc->sc_initblock.init_ladrf[crc >> 4] |= 1989 htole16(1 << (crc & 0xf)); 1990 1991 ETHER_NEXT_MULTI(step, enm); 1992 } 1993 1994 ifp->if_flags &= ~IFF_ALLMULTI; 1995 return; 1996 1997 allmulti: 1998 ifp->if_flags |= IFF_ALLMULTI; 1999 sc->sc_initblock.init_ladrf[0] = 2000 sc->sc_initblock.init_ladrf[1] = 2001 sc->sc_initblock.init_ladrf[2] = 2002 sc->sc_initblock.init_ladrf[3] = 0xffff; 2003 } 2004 2005 /* 2006 * pcn_79c970_mediainit: 2007 * 2008 * Initialize media for the Am79c970. 2009 */ 2010 static void 2011 pcn_79c970_mediainit(struct pcn_softc *sc) 2012 { 2013 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2014 const char *sep = ""; 2015 2016 sc->sc_mii.mii_ifp = ifp; 2017 2018 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, pcn_79c970_mediachange, 2019 pcn_79c970_mediastatus); 2020 2021 #define ADD(str, m, d) \ 2022 do { \ 2023 aprint_normal("%s%s", sep, str); \ 2024 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(m), (d), NULL); \ 2025 sep = ", "; \ 2026 } while (/*CONSTCOND*/0) 2027 2028 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2029 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2030 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2031 ADD("10base5-FDX", IFM_10_5|IFM_FDX, PORTSEL_AUI); 2032 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2033 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2034 ADD("10baseT-FDX", IFM_10_T|IFM_FDX, PORTSEL_10T); 2035 ADD("auto", IFM_AUTO, 0); 2036 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2037 ADD("auto-FDX", IFM_AUTO|IFM_FDX, 0); 2038 aprint_normal("\n"); 2039 2040 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2041 } 2042 2043 /* 2044 * pcn_79c970_mediastatus: [ifmedia interface function] 2045 * 2046 * Get the current interface media status (Am79c970 version). 2047 */ 2048 static void 2049 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2050 { 2051 struct pcn_softc *sc = ifp->if_softc; 2052 2053 /* 2054 * The currently selected media is always the active media. 2055 * Note: We have no way to determine what media the AUTO 2056 * process picked. 2057 */ 2058 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2059 } 2060 2061 /* 2062 * pcn_79c970_mediachange: [ifmedia interface function] 2063 * 2064 * Set hardware to newly-selected media (Am79c970 version). 2065 */ 2066 static int 2067 pcn_79c970_mediachange(struct ifnet *ifp) 2068 { 2069 struct pcn_softc *sc = ifp->if_softc; 2070 uint32_t reg; 2071 2072 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2073 /* 2074 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2075 */ 2076 reg = pcn_bcr_read(sc, LE_BCR2); 2077 reg |= LE_B2_ASEL; 2078 pcn_bcr_write(sc, LE_BCR2, reg); 2079 } else { 2080 /* 2081 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2082 */ 2083 reg = pcn_bcr_read(sc, LE_BCR2); 2084 reg &= ~LE_B2_ASEL; 2085 pcn_bcr_write(sc, LE_BCR2, reg); 2086 2087 reg = pcn_csr_read(sc, LE_CSR15); 2088 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2089 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2090 pcn_csr_write(sc, LE_CSR15, reg); 2091 } 2092 2093 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2094 reg = LE_B9_FDEN; 2095 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2096 reg |= LE_B9_AUIFD; 2097 pcn_bcr_write(sc, LE_BCR9, reg); 2098 } else 2099 pcn_bcr_write(sc, LE_BCR9, 0); 2100 2101 return (0); 2102 } 2103 2104 /* 2105 * pcn_79c971_mediainit: 2106 * 2107 * Initialize media for the Am79c971. 2108 */ 2109 static void 2110 pcn_79c971_mediainit(struct pcn_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2113 2114 /* We have MII. */ 2115 sc->sc_flags |= PCN_F_HAS_MII; 2116 2117 /* 2118 * The built-in 10BASE-T interface is mapped to the MII 2119 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2120 * word that tells us which PHY to use. 2121 * This driver used to ignore all but the first PHY to 2122 * answer, but this code was removed to support multiple 2123 * external PHYs. As the default instance will be the first 2124 * one to answer, no harm is done by letting the possibly 2125 * non-connected internal PHY show up. 2126 */ 2127 2128 /* Initialize our media structures and probe the MII. */ 2129 sc->sc_mii.mii_ifp = ifp; 2130 sc->sc_mii.mii_readreg = pcn_mii_readreg; 2131 sc->sc_mii.mii_writereg = pcn_mii_writereg; 2132 sc->sc_mii.mii_statchg = pcn_mii_statchg; 2133 2134 sc->sc_ethercom.ec_mii = &sc->sc_mii; 2135 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 2136 ether_mediastatus); 2137 2138 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 2139 MII_OFFSET_ANY, 0); 2140 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 2141 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 2142 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 2143 } else 2144 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 2145 } 2146 2147 /* 2148 * pcn_mii_readreg: [mii interface function] 2149 * 2150 * Read a PHY register on the MII. 2151 */ 2152 static int 2153 pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2154 { 2155 struct pcn_softc *sc = device_private(self); 2156 2157 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2158 *val = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2159 if (*val == 0xffff) 2160 return -1; 2161 2162 return 0; 2163 } 2164 2165 /* 2166 * pcn_mii_writereg: [mii interface function] 2167 * 2168 * Write a PHY register on the MII. 2169 */ 2170 static int 2171 pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2172 { 2173 struct pcn_softc *sc = device_private(self); 2174 2175 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2176 pcn_bcr_write(sc, LE_BCR34, val); 2177 2178 return 0; 2179 } 2180 2181 /* 2182 * pcn_mii_statchg: [mii interface function] 2183 * 2184 * Callback from MII layer when media changes. 2185 */ 2186 static void 2187 pcn_mii_statchg(struct ifnet *ifp) 2188 { 2189 struct pcn_softc *sc = ifp->if_softc; 2190 2191 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2192 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2193 else 2194 pcn_bcr_write(sc, LE_BCR9, 0); 2195 } 2196
Indexes created Fri Sep 26 20:09:58 GMT 2025