if_pcn.c revision 1.74
1 /* $NetBSD: if_pcn.c,v 1.74 2020/02/07 00:04:28 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for the AMD PCnet-PCI series of Ethernet 40 * chips: 41 * 42 * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI 43 * Local Bus 44 * 45 * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller 46 * for PCI Local Bus 47 * 48 * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps 49 * Ethernet Controller for PCI Local Bus 50 * 51 * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller 52 * with OnNow Support 53 * 54 * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI 55 * Ethernet Controller with Integrated PHY 56 * 57 * This also supports the virtual PCnet-PCI Ethernet interface found 58 * in VMware. 59 * 60 * TODO: 61 * 62 * * Split this into bus-specific and bus-independent portions. 63 * The core could also be used for the ILACC (Am79900) 32-bit 64 * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE). 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: if_pcn.c,v 1.74 2020/02/07 00:04:28 thorpej Exp $"); 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/callout.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/ioctl.h> 78 #include <sys/errno.h> 79 #include <sys/device.h> 80 #include <sys/queue.h> 81 82 #include <sys/rndsource.h> 83 84 #include <net/if.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #include <net/bpf.h> 90 91 #include <sys/bus.h> 92 #include <sys/intr.h> 93 #include <machine/endian.h> 94 95 #include <dev/mii/mii.h> 96 #include <dev/mii/miivar.h> 97 98 #include <dev/ic/am79900reg.h> 99 #include <dev/ic/lancereg.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 105 #include <dev/pci/if_pcnreg.h> 106 107 /* 108 * Transmit descriptor list size. This is arbitrary, but allocate 109 * enough descriptors for 128 pending transmissions, and 4 segments 110 * per packet. This MUST work out to a power of 2. 111 * 112 * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL! 113 * 114 * So we play a little trick here. We give each packet up to 16 115 * DMA segments, but only allocate the max of 512 descriptors. The 116 * transmit logic can deal with this, we just are hoping to sneak by. 117 */ 118 #define PCN_NTXSEGS 16 119 #define PCN_NTXSEGS_VMWARE 8 /* bug in VMware's emulation */ 120 121 #define PCN_TXQUEUELEN 128 122 #define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1) 123 #define PCN_NTXDESC 512 124 #define PCN_NTXDESC_MASK (PCN_NTXDESC - 1) 125 #define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK) 126 #define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK) 127 128 /* Tx interrupt every N + 1 packets. */ 129 #define PCN_TXINTR_MASK 7 130 131 /* 132 * Receive descriptor list size. We have one Rx buffer per incoming 133 * packet, so this logic is a little simpler. 134 */ 135 #define PCN_NRXDESC 128 136 #define PCN_NRXDESC_MASK (PCN_NRXDESC - 1) 137 #define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK) 138 139 /* 140 * Control structures are DMA'd to the PCnet chip. We allocate them in 141 * a single clump that maps to a single DMA segment to make several things 142 * easier. 143 */ 144 struct pcn_control_data { 145 /* The transmit descriptors. */ 146 struct letmd pcd_txdescs[PCN_NTXDESC]; 147 148 /* The receive descriptors. */ 149 struct lermd pcd_rxdescs[PCN_NRXDESC]; 150 151 /* The init block. */ 152 struct leinit pcd_initblock; 153 }; 154 155 #define PCN_CDOFF(x) offsetof(struct pcn_control_data, x) 156 #define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)]) 157 #define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)]) 158 #define PCN_CDINITOFF PCN_CDOFF(pcd_initblock) 159 160 /* 161 * Software state for transmit jobs. 162 */ 163 struct pcn_txsoft { 164 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 165 bus_dmamap_t txs_dmamap; /* our DMA map */ 166 int txs_firstdesc; /* first descriptor in packet */ 167 int txs_lastdesc; /* last descriptor in packet */ 168 }; 169 170 /* 171 * Software state for receive jobs. 172 */ 173 struct pcn_rxsoft { 174 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 175 bus_dmamap_t rxs_dmamap; /* our DMA map */ 176 }; 177 178 /* 179 * Description of Rx FIFO watermarks for various revisions. 180 */ 181 static const char * const pcn_79c970_rcvfw[] = { 182 "16 bytes", 183 "64 bytes", 184 "128 bytes", 185 NULL, 186 }; 187 188 static const char * const pcn_79c971_rcvfw[] = { 189 "16 bytes", 190 "64 bytes", 191 "112 bytes", 192 NULL, 193 }; 194 195 /* 196 * Description of Tx start points for various revisions. 197 */ 198 static const char * const pcn_79c970_xmtsp[] = { 199 "8 bytes", 200 "64 bytes", 201 "128 bytes", 202 "248 bytes", 203 }; 204 205 static const char * const pcn_79c971_xmtsp[] = { 206 "20 bytes", 207 "64 bytes", 208 "128 bytes", 209 "248 bytes", 210 }; 211 212 static const char * const pcn_79c971_xmtsp_sram[] = { 213 "44 bytes", 214 "64 bytes", 215 "128 bytes", 216 "store-and-forward", 217 }; 218 219 /* 220 * Description of Tx FIFO watermarks for various revisions. 221 */ 222 static const char * const pcn_79c970_xmtfw[] = { 223 "16 bytes", 224 "64 bytes", 225 "128 bytes", 226 NULL, 227 }; 228 229 static const char * const pcn_79c971_xmtfw[] = { 230 "16 bytes", 231 "64 bytes", 232 "108 bytes", 233 NULL, 234 }; 235 236 /* 237 * Software state per device. 238 */ 239 struct pcn_softc { 240 device_t sc_dev; /* generic device information */ 241 bus_space_tag_t sc_st; /* bus space tag */ 242 bus_space_handle_t sc_sh; /* bus space handle */ 243 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 244 struct ethercom sc_ethercom; /* Ethernet common data */ 245 246 /* Points to our media routines, etc. */ 247 const struct pcn_variant *sc_variant; 248 249 void *sc_ih; /* interrupt cookie */ 250 251 struct mii_data sc_mii; /* MII/media information */ 252 253 callout_t sc_tick_ch; /* tick callout */ 254 255 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 256 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 257 258 /* Software state for transmit and receive descriptors. */ 259 struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN]; 260 struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC]; 261 262 /* Control data structures */ 263 struct pcn_control_data *sc_control_data; 264 #define sc_txdescs sc_control_data->pcd_txdescs 265 #define sc_rxdescs sc_control_data->pcd_rxdescs 266 #define sc_initblock sc_control_data->pcd_initblock 267 268 #ifdef PCN_EVENT_COUNTERS 269 /* Event counters. */ 270 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 271 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 272 struct evcnt sc_ev_txintr; /* Tx interrupts */ 273 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 274 struct evcnt sc_ev_babl; /* BABL in pcn_intr() */ 275 struct evcnt sc_ev_miss; /* MISS in pcn_intr() */ 276 struct evcnt sc_ev_merr; /* MERR in pcn_intr() */ 277 278 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */ 279 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */ 280 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */ 281 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */ 282 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */ 283 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */ 284 struct evcnt sc_ev_txcopy; /* Tx copies required */ 285 #endif /* PCN_EVENT_COUNTERS */ 286 287 const char * const *sc_rcvfw_desc; /* Rx FIFO watermark info */ 288 int sc_rcvfw; 289 290 const char * const *sc_xmtsp_desc; /* Tx start point info */ 291 int sc_xmtsp; 292 293 const char * const *sc_xmtfw_desc; /* Tx FIFO watermark info */ 294 int sc_xmtfw; 295 296 int sc_flags; /* misc. flags; see below */ 297 int sc_swstyle; /* the software style in use */ 298 299 int sc_txfree; /* number of free Tx descriptors */ 300 int sc_txnext; /* next ready Tx descriptor */ 301 302 int sc_txsfree; /* number of free Tx jobs */ 303 int sc_txsnext; /* next free Tx job */ 304 int sc_txsdirty; /* dirty Tx jobs */ 305 306 int sc_rxptr; /* next ready Rx descriptor/job */ 307 308 uint32_t sc_csr5; /* prototype CSR5 register */ 309 uint32_t sc_mode; /* prototype MODE register */ 310 311 krndsource_t rnd_source; /* random source */ 312 }; 313 314 /* sc_flags */ 315 #define PCN_F_HAS_MII 0x0001 /* has MII */ 316 317 #ifdef PCN_EVENT_COUNTERS 318 #define PCN_EVCNT_INCR(ev) (ev)->ev_count++ 319 #else 320 #define PCN_EVCNT_INCR(ev) /* nothing */ 321 #endif 322 323 #define PCN_CDTXADDR(sc, x) ((sc)->sc_cddma + PCN_CDTXOFF((x))) 324 #define PCN_CDRXADDR(sc, x) ((sc)->sc_cddma + PCN_CDRXOFF((x))) 325 #define PCN_CDINITADDR(sc) ((sc)->sc_cddma + PCN_CDINITOFF) 326 327 #define PCN_CDTXSYNC(sc, x, n, ops) \ 328 do { \ 329 int __x, __n; \ 330 \ 331 __x = (x); \ 332 __n = (n); \ 333 \ 334 /* If it will wrap around, sync to the end of the ring. */ \ 335 if ((__x + __n) > PCN_NTXDESC) { \ 336 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 337 PCN_CDTXOFF(__x), sizeof(struct letmd) * \ 338 (PCN_NTXDESC - __x), (ops)); \ 339 __n -= (PCN_NTXDESC - __x); \ 340 __x = 0; \ 341 } \ 342 \ 343 /* Now sync whatever is left. */ \ 344 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 345 PCN_CDTXOFF(__x), sizeof(struct letmd) * __n, (ops)); \ 346 } while (/*CONSTCOND*/0) 347 348 #define PCN_CDRXSYNC(sc, x, ops) \ 349 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 350 PCN_CDRXOFF((x)), sizeof(struct lermd), (ops)) 351 352 #define PCN_CDINITSYNC(sc, ops) \ 353 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 354 PCN_CDINITOFF, sizeof(struct leinit), (ops)) 355 356 #define PCN_INIT_RXDESC(sc, x) \ 357 do { \ 358 struct pcn_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 359 struct lermd *__rmd = &(sc)->sc_rxdescs[(x)]; \ 360 struct mbuf *__m = __rxs->rxs_mbuf; \ 361 \ 362 /* \ 363 * Note: We scoot the packet forward 2 bytes in the buffer \ 364 * so that the payload after the Ethernet header is aligned \ 365 * to a 4-byte boundary. \ 366 */ \ 367 __m->m_data = __m->m_ext.ext_buf + 2; \ 368 \ 369 if ((sc)->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { \ 370 __rmd->rmd2 = \ 371 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 372 __rmd->rmd0 = 0; \ 373 } else { \ 374 __rmd->rmd2 = 0; \ 375 __rmd->rmd0 = \ 376 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr + 2); \ 377 } \ 378 __rmd->rmd1 = htole32(LE_R1_OWN | LE_R1_ONES | \ 379 (LE_BCNT(MCLBYTES - 2) & LE_R1_BCNT_MASK)); \ 380 PCN_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);\ 381 } while(/*CONSTCOND*/0) 382 383 static void pcn_start(struct ifnet *); 384 static void pcn_watchdog(struct ifnet *); 385 static int pcn_ioctl(struct ifnet *, u_long, void *); 386 static int pcn_init(struct ifnet *); 387 static void pcn_stop(struct ifnet *, int); 388 389 static bool pcn_shutdown(device_t, int); 390 391 static void pcn_reset(struct pcn_softc *); 392 static void pcn_rxdrain(struct pcn_softc *); 393 static int pcn_add_rxbuf(struct pcn_softc *, int); 394 static void pcn_tick(void *); 395 396 static void pcn_spnd(struct pcn_softc *); 397 398 static void pcn_set_filter(struct pcn_softc *); 399 400 static int pcn_intr(void *); 401 static void pcn_txintr(struct pcn_softc *); 402 static int pcn_rxintr(struct pcn_softc *); 403 404 static int pcn_mii_readreg(device_t, int, int, uint16_t *); 405 static int pcn_mii_writereg(device_t, int, int, uint16_t); 406 static void pcn_mii_statchg(struct ifnet *); 407 408 static void pcn_79c970_mediainit(struct pcn_softc *); 409 static int pcn_79c970_mediachange(struct ifnet *); 410 static void pcn_79c970_mediastatus(struct ifnet *, struct ifmediareq *); 411 412 static void pcn_79c971_mediainit(struct pcn_softc *); 413 414 /* 415 * Description of a PCnet-PCI variant. Used to select media access 416 * method, mostly, and to print a nice description of the chip. 417 */ 418 static const struct pcn_variant { 419 const char *pcv_desc; 420 void (*pcv_mediainit)(struct pcn_softc *); 421 uint16_t pcv_chipid; 422 } pcn_variants[] = { 423 { "Am79c970 PCnet-PCI", 424 pcn_79c970_mediainit, 425 PARTID_Am79c970 }, 426 427 { "Am79c970A PCnet-PCI II", 428 pcn_79c970_mediainit, 429 PARTID_Am79c970A }, 430 431 { "Am79c971 PCnet-FAST", 432 pcn_79c971_mediainit, 433 PARTID_Am79c971 }, 434 435 { "Am79c972 PCnet-FAST+", 436 pcn_79c971_mediainit, 437 PARTID_Am79c972 }, 438 439 { "Am79c973 PCnet-FAST III", 440 pcn_79c971_mediainit, 441 PARTID_Am79c973 }, 442 443 { "Am79c975 PCnet-FAST III", 444 pcn_79c971_mediainit, 445 PARTID_Am79c975 }, 446 447 { "Unknown PCnet-PCI variant", 448 pcn_79c971_mediainit, 449 0 }, 450 }; 451 452 int pcn_copy_small = 0; 453 454 static int pcn_match(device_t, cfdata_t, void *); 455 static void pcn_attach(device_t, device_t, void *); 456 457 CFATTACH_DECL_NEW(pcn, sizeof(struct pcn_softc), 458 pcn_match, pcn_attach, NULL, NULL); 459 460 /* 461 * Routines to read and write the PCnet-PCI CSR/BCR space. 462 */ 463 464 static inline uint32_t 465 pcn_csr_read(struct pcn_softc *sc, int reg) 466 { 467 468 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 469 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RDP); 470 } 471 472 static inline void 473 pcn_csr_write(struct pcn_softc *sc, int reg, uint32_t val) 474 { 475 476 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 477 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, val); 478 } 479 480 static inline uint32_t 481 pcn_bcr_read(struct pcn_softc *sc, int reg) 482 { 483 484 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 485 return bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_BDP); 486 } 487 488 static inline void 489 pcn_bcr_write(struct pcn_softc *sc, int reg, uint32_t val) 490 { 491 492 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RAP, reg); 493 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_BDP, val); 494 } 495 496 static bool 497 pcn_is_vmware(const char *enaddr) 498 { 499 500 /* 501 * VMware uses the OUI 00:0c:29 for auto-generated MAC 502 * addresses. 503 */ 504 if (enaddr[0] == 0x00 && enaddr[1] == 0x0c && enaddr[2] == 0x29) 505 return TRUE; 506 507 /* 508 * VMware uses the OUI 00:50:56 for manually-set MAC 509 * addresses (and some auto-generated ones). 510 */ 511 if (enaddr[0] == 0x00 && enaddr[1] == 0x50 && enaddr[2] == 0x56) 512 return TRUE; 513 514 return FALSE; 515 } 516 517 static const struct pcn_variant * 518 pcn_lookup_variant(uint16_t chipid) 519 { 520 const struct pcn_variant *pcv; 521 522 for (pcv = pcn_variants; pcv->pcv_chipid != 0; pcv++) { 523 if (chipid == pcv->pcv_chipid) 524 return pcv; 525 } 526 527 /* 528 * This covers unknown chips, which we simply treat like 529 * a generic PCnet-FAST. 530 */ 531 return pcv; 532 } 533 534 static int 535 pcn_match(device_t parent, cfdata_t cf, void *aux) 536 { 537 struct pci_attach_args *pa = aux; 538 539 /* 540 * IBM Makes a PCI variant of this card which shows up as a 541 * Trident Microsystems 4DWAVE DX (ethernet network, revision 0x25) 542 * this card is truly a pcn card, so we have a special case match for 543 * it 544 */ 545 546 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIDENT && 547 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_TRIDENT_4DWAVE_DX && 548 PCI_CLASS(pa->pa_class) == PCI_CLASS_NETWORK) 549 return 1; 550 551 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD) 552 return 0; 553 554 switch (PCI_PRODUCT(pa->pa_id)) { 555 case PCI_PRODUCT_AMD_PCNET_PCI: 556 /* Beat if_le_pci.c */ 557 return 10; 558 } 559 560 return 0; 561 } 562 563 static void 564 pcn_attach(device_t parent, device_t self, void *aux) 565 { 566 struct pcn_softc *sc = device_private(self); 567 struct pci_attach_args *pa = aux; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 pci_chipset_tag_t pc = pa->pa_pc; 570 pci_intr_handle_t ih; 571 const char *intrstr = NULL; 572 bus_space_tag_t iot, memt; 573 bus_space_handle_t ioh, memh; 574 bus_dma_segment_t seg; 575 int ioh_valid, memh_valid; 576 int ntxsegs, i, rseg, error; 577 uint32_t chipid, reg; 578 uint8_t enaddr[ETHER_ADDR_LEN]; 579 prop_object_t obj; 580 bool is_vmware; 581 char intrbuf[PCI_INTRSTR_LEN]; 582 583 sc->sc_dev = self; 584 callout_init(&sc->sc_tick_ch, 0); 585 callout_setfunc(&sc->sc_tick_ch, pcn_tick, sc); 586 587 aprint_normal(": AMD PCnet-PCI Ethernet\n"); 588 589 /* 590 * Map the device. 591 */ 592 ioh_valid = (pci_mapreg_map(pa, PCN_PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 593 &iot, &ioh, NULL, NULL) == 0); 594 memh_valid = (pci_mapreg_map(pa, PCN_PCI_CBMEM, 595 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 596 &memt, &memh, NULL, NULL) == 0); 597 598 if (memh_valid) { 599 sc->sc_st = memt; 600 sc->sc_sh = memh; 601 } else if (ioh_valid) { 602 sc->sc_st = iot; 603 sc->sc_sh = ioh; 604 } else { 605 aprint_error_dev(self, "unable to map device registers\n"); 606 return; 607 } 608 609 sc->sc_dmat = pa->pa_dmat; 610 611 /* Make sure bus mastering is enabled. */ 612 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 613 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 614 PCI_COMMAND_MASTER_ENABLE); 615 616 /* power up chip */ 617 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 618 NULL)) && error != EOPNOTSUPP) { 619 aprint_error_dev(self, "cannot activate %d\n", error); 620 return; 621 } 622 623 /* 624 * Reset the chip to a known state. This also puts the 625 * chip into 32-bit mode. 626 */ 627 pcn_reset(sc); 628 629 /* 630 * On some systems with the chip is an on-board device, the 631 * EEPROM is not used. Handle this by reading the MAC address 632 * from the CSRs (assuming that boot firmware has written 633 * it there). 634 */ 635 obj = prop_dictionary_get(device_properties(sc->sc_dev), 636 "am79c970-no-eeprom"); 637 if (prop_bool_true(obj)) { 638 for (i = 0; i < 3; i++) { 639 uint32_t val; 640 val = pcn_csr_read(sc, LE_CSR12 + i); 641 enaddr[2 * i] = val & 0xff; 642 enaddr[2 * i + 1] = (val >> 8) & 0xff; 643 } 644 } else { 645 for (i = 0; i < ETHER_ADDR_LEN; i++) { 646 enaddr[i] = bus_space_read_1(sc->sc_st, sc->sc_sh, 647 PCN32_APROM + i); 648 } 649 } 650 651 /* Check to see if this is a VMware emulated network interface. */ 652 is_vmware = pcn_is_vmware(enaddr); 653 654 /* 655 * Now that the device is mapped, attempt to figure out what 656 * kind of chip we have. Note that IDL has all 32 bits of 657 * the chip ID when we're in 32-bit mode. 658 */ 659 chipid = pcn_csr_read(sc, LE_CSR88); 660 sc->sc_variant = pcn_lookup_variant(CHIPID_PARTID(chipid)); 661 662 aprint_normal_dev(self, "%s rev %d, Ethernet address %s\n", 663 sc->sc_variant->pcv_desc, CHIPID_VER(chipid), 664 ether_sprintf(enaddr)); 665 666 /* 667 * VMware has a bug in its network interface emulation; we must 668 * limit the number of Tx segments. 669 */ 670 if (is_vmware) { 671 ntxsegs = PCN_NTXSEGS_VMWARE; 672 prop_dictionary_set_bool(device_properties(sc->sc_dev), 673 "am79c970-vmware-tx-bug", TRUE); 674 aprint_verbose_dev(self, 675 "VMware Tx segment count bug detected\n"); 676 } else { 677 ntxsegs = PCN_NTXSEGS; 678 } 679 680 /* 681 * Map and establish our interrupt. 682 */ 683 if (pci_intr_map(pa, &ih)) { 684 aprint_error_dev(self, "unable to map interrupt\n"); 685 return; 686 } 687 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 688 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, pcn_intr, sc, 689 device_xname(self)); 690 if (sc->sc_ih == NULL) { 691 aprint_error_dev(self, "unable to establish interrupt"); 692 if (intrstr != NULL) 693 aprint_error(" at %s", intrstr); 694 aprint_error("\n"); 695 return; 696 } 697 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 698 699 /* 700 * Allocate the control data structures, and create and load the 701 * DMA map for it. 702 */ 703 if ((error = bus_dmamem_alloc(sc->sc_dmat, 704 sizeof(struct pcn_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 705 0)) != 0) { 706 aprint_error_dev(self, "unable to allocate control data, " 707 "error = %d\n", error); 708 goto fail_0; 709 } 710 711 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 712 sizeof(struct pcn_control_data), (void **)&sc->sc_control_data, 713 BUS_DMA_COHERENT)) != 0) { 714 aprint_error_dev(self, "unable to map control data, " 715 "error = %d\n", error); 716 goto fail_1; 717 } 718 719 if ((error = bus_dmamap_create(sc->sc_dmat, 720 sizeof(struct pcn_control_data), 1, 721 sizeof(struct pcn_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 722 aprint_error_dev(self, "unable to create control data DMA map, " 723 "error = %d\n", error); 724 goto fail_2; 725 } 726 727 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 728 sc->sc_control_data, sizeof(struct pcn_control_data), NULL, 729 0)) != 0) { 730 aprint_error_dev(self, 731 "unable to load control data DMA map, error = %d\n", error); 732 goto fail_3; 733 } 734 735 /* Create the transmit buffer DMA maps. */ 736 for (i = 0; i < PCN_TXQUEUELEN; i++) { 737 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 738 ntxsegs, MCLBYTES, 0, 0, 739 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 740 aprint_error_dev(self, 741 "unable to create tx DMA map %d, error = %d\n", 742 i, error); 743 goto fail_4; 744 } 745 } 746 747 /* Create the receive buffer DMA maps. */ 748 for (i = 0; i < PCN_NRXDESC; i++) { 749 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 750 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 751 aprint_error_dev(self, 752 "unable to create rx DMA map %d, error = %d\n", 753 i, error); 754 goto fail_5; 755 } 756 sc->sc_rxsoft[i].rxs_mbuf = NULL; 757 } 758 759 /* Initialize our media structures. */ 760 (*sc->sc_variant->pcv_mediainit)(sc); 761 762 /* 763 * Initialize FIFO watermark info. 764 */ 765 switch (sc->sc_variant->pcv_chipid) { 766 case PARTID_Am79c970: 767 case PARTID_Am79c970A: 768 sc->sc_rcvfw_desc = pcn_79c970_rcvfw; 769 sc->sc_xmtsp_desc = pcn_79c970_xmtsp; 770 sc->sc_xmtfw_desc = pcn_79c970_xmtfw; 771 break; 772 773 default: 774 sc->sc_rcvfw_desc = pcn_79c971_rcvfw; 775 /* 776 * Read BCR25 to determine how much SRAM is 777 * on the board. If > 0, then we the chip 778 * uses different Start Point thresholds. 779 * 780 * Note BCR25 and BCR26 are loaded from the 781 * EEPROM on RST, and unaffected by S_RESET, 782 * so we don't really have to worry about 783 * them except for this. 784 */ 785 reg = pcn_bcr_read(sc, LE_BCR25) & 0x00ff; 786 if (reg != 0) 787 sc->sc_xmtsp_desc = pcn_79c971_xmtsp_sram; 788 else 789 sc->sc_xmtsp_desc = pcn_79c971_xmtsp; 790 sc->sc_xmtfw_desc = pcn_79c971_xmtfw; 791 break; 792 } 793 794 /* 795 * Set up defaults -- see the tables above for what these 796 * values mean. 797 * 798 * XXX How should we tune RCVFW and XMTFW? 799 */ 800 sc->sc_rcvfw = 1; /* minimum for full-duplex */ 801 sc->sc_xmtsp = 1; 802 sc->sc_xmtfw = 0; 803 804 ifp = &sc->sc_ethercom.ec_if; 805 strcpy(ifp->if_xname, device_xname(self)); 806 ifp->if_softc = sc; 807 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 808 ifp->if_ioctl = pcn_ioctl; 809 ifp->if_start = pcn_start; 810 ifp->if_watchdog = pcn_watchdog; 811 ifp->if_init = pcn_init; 812 ifp->if_stop = pcn_stop; 813 IFQ_SET_READY(&ifp->if_snd); 814 815 /* Attach the interface. */ 816 if_attach(ifp); 817 if_deferred_start_init(ifp, NULL); 818 ether_ifattach(ifp, enaddr); 819 rnd_attach_source(&sc->rnd_source, device_xname(self), 820 RND_TYPE_NET, RND_FLAG_DEFAULT); 821 822 #ifdef PCN_EVENT_COUNTERS 823 /* Attach event counters. */ 824 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 825 NULL, device_xname(self), "txsstall"); 826 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 827 NULL, device_xname(self), "txdstall"); 828 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_INTR, 829 NULL, device_xname(self), "txintr"); 830 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 831 NULL, device_xname(self), "rxintr"); 832 evcnt_attach_dynamic(&sc->sc_ev_babl, EVCNT_TYPE_MISC, 833 NULL, device_xname(self), "babl"); 834 evcnt_attach_dynamic(&sc->sc_ev_miss, EVCNT_TYPE_MISC, 835 NULL, device_xname(self), "miss"); 836 evcnt_attach_dynamic(&sc->sc_ev_merr, EVCNT_TYPE_MISC, 837 NULL, device_xname(self), "merr"); 838 839 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC, 840 NULL, device_xname(self), "txseg1"); 841 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC, 842 NULL, device_xname(self), "txseg2"); 843 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC, 844 NULL, device_xname(self), "txseg3"); 845 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC, 846 NULL, device_xname(self), "txseg4"); 847 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC, 848 NULL, device_xname(self), "txseg5"); 849 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC, 850 NULL, device_xname(self), "txsegmore"); 851 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC, 852 NULL, device_xname(self), "txcopy"); 853 #endif /* PCN_EVENT_COUNTERS */ 854 855 /* 856 * Establish power handler with shutdown hook, to make sure 857 * the interface is shutdown during reboot. 858 */ 859 if (pmf_device_register1(self, NULL, NULL, pcn_shutdown)) 860 pmf_class_network_register(self, ifp); 861 else 862 aprint_error_dev(self, "couldn't establish power handler\n"); 863 864 return; 865 866 /* 867 * Free any resources we've allocated during the failed attach 868 * attempt. Do this in reverse order and fall through. 869 */ 870 fail_5: 871 for (i = 0; i < PCN_NRXDESC; i++) { 872 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 873 bus_dmamap_destroy(sc->sc_dmat, 874 sc->sc_rxsoft[i].rxs_dmamap); 875 } 876 fail_4: 877 for (i = 0; i < PCN_TXQUEUELEN; i++) { 878 if (sc->sc_txsoft[i].txs_dmamap != NULL) 879 bus_dmamap_destroy(sc->sc_dmat, 880 sc->sc_txsoft[i].txs_dmamap); 881 } 882 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 883 fail_3: 884 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 885 fail_2: 886 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 887 sizeof(struct pcn_control_data)); 888 fail_1: 889 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 890 fail_0: 891 return; 892 } 893 894 /* 895 * pcn_shutdown: 896 * 897 * Make sure the interface is stopped at reboot time. 898 */ 899 static bool 900 pcn_shutdown(device_t self, int howto) 901 { 902 struct pcn_softc *sc = device_private(self); 903 904 pcn_stop(&sc->sc_ethercom.ec_if, 1); 905 /* explicitly reset the chip for some onboard one with lazy firmware */ 906 pcn_reset(sc); 907 908 return true; 909 } 910 911 /* 912 * pcn_start: [ifnet interface function] 913 * 914 * Start packet transmission on the interface. 915 */ 916 static void 917 pcn_start(struct ifnet *ifp) 918 { 919 struct pcn_softc *sc = ifp->if_softc; 920 struct mbuf *m0, *m; 921 struct pcn_txsoft *txs; 922 bus_dmamap_t dmamap; 923 int error, nexttx, lasttx = -1, ofree, seg; 924 925 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 926 return; 927 928 /* 929 * Remember the previous number of free descriptors and 930 * the first descriptor we'll use. 931 */ 932 ofree = sc->sc_txfree; 933 934 /* 935 * Loop through the send queue, setting up transmit descriptors 936 * until we drain the queue, or use up all available transmit 937 * descriptors. 938 */ 939 for (;;) { 940 /* Grab a packet off the queue. */ 941 IFQ_POLL(&ifp->if_snd, m0); 942 if (m0 == NULL) 943 break; 944 m = NULL; 945 946 /* Get a work queue entry. */ 947 if (sc->sc_txsfree == 0) { 948 PCN_EVCNT_INCR(&sc->sc_ev_txsstall); 949 break; 950 } 951 952 txs = &sc->sc_txsoft[sc->sc_txsnext]; 953 dmamap = txs->txs_dmamap; 954 955 /* 956 * Load the DMA map. If this fails, the packet either 957 * didn't fit in the alloted number of segments, or we 958 * were short on resources. In this case, we'll copy 959 * and try again. 960 */ 961 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 962 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 963 PCN_EVCNT_INCR(&sc->sc_ev_txcopy); 964 MGETHDR(m, M_DONTWAIT, MT_DATA); 965 if (m == NULL) { 966 printf("%s: unable to allocate Tx mbuf\n", 967 device_xname(sc->sc_dev)); 968 break; 969 } 970 if (m0->m_pkthdr.len > MHLEN) { 971 MCLGET(m, M_DONTWAIT); 972 if ((m->m_flags & M_EXT) == 0) { 973 printf("%s: unable to allocate Tx " 974 "cluster\n", 975 device_xname(sc->sc_dev)); 976 m_freem(m); 977 break; 978 } 979 } 980 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 981 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 982 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 983 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 984 if (error) { 985 printf("%s: unable to load Tx buffer, " 986 "error = %d\n", device_xname(sc->sc_dev), 987 error); 988 m_freem(m); 989 break; 990 } 991 } 992 993 /* 994 * Ensure we have enough descriptors free to describe 995 * the packet. Note, we always reserve one descriptor 996 * at the end of the ring as a termination point, to 997 * prevent wrap-around. 998 */ 999 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1000 /* 1001 * Not enough free descriptors to transmit this 1002 * packet. We haven't committed anything yet, 1003 * so just unload the DMA map, put the packet 1004 * back on the queue, and punt. Notify the upper 1005 * layer that there are not more slots left. 1006 * 1007 * XXX We could allocate an mbuf and copy, but 1008 * XXX is it worth it? 1009 */ 1010 ifp->if_flags |= IFF_OACTIVE; 1011 bus_dmamap_unload(sc->sc_dmat, dmamap); 1012 if (m != NULL) 1013 m_freem(m); 1014 PCN_EVCNT_INCR(&sc->sc_ev_txdstall); 1015 break; 1016 } 1017 1018 IFQ_DEQUEUE(&ifp->if_snd, m0); 1019 if (m != NULL) { 1020 m_freem(m0); 1021 m0 = m; 1022 } 1023 1024 /* 1025 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1026 */ 1027 1028 /* Sync the DMA map. */ 1029 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1030 BUS_DMASYNC_PREWRITE); 1031 1032 #ifdef PCN_EVENT_COUNTERS 1033 switch (dmamap->dm_nsegs) { 1034 case 1: 1035 PCN_EVCNT_INCR(&sc->sc_ev_txseg1); 1036 break; 1037 case 2: 1038 PCN_EVCNT_INCR(&sc->sc_ev_txseg2); 1039 break; 1040 case 3: 1041 PCN_EVCNT_INCR(&sc->sc_ev_txseg3); 1042 break; 1043 case 4: 1044 PCN_EVCNT_INCR(&sc->sc_ev_txseg4); 1045 break; 1046 case 5: 1047 PCN_EVCNT_INCR(&sc->sc_ev_txseg5); 1048 break; 1049 default: 1050 PCN_EVCNT_INCR(&sc->sc_ev_txsegmore); 1051 break; 1052 } 1053 #endif /* PCN_EVENT_COUNTERS */ 1054 1055 /* 1056 * Initialize the transmit descriptors. 1057 */ 1058 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) { 1059 for (nexttx = sc->sc_txnext, seg = 0; 1060 seg < dmamap->dm_nsegs; 1061 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1062 /* 1063 * If this is the first descriptor we're 1064 * enqueueing, don't set the OWN bit just 1065 * yet. That could cause a race condition. 1066 * We'll do it below. 1067 */ 1068 sc->sc_txdescs[nexttx].tmd0 = 0; 1069 sc->sc_txdescs[nexttx].tmd2 = 1070 htole32(dmamap->dm_segs[seg].ds_addr); 1071 sc->sc_txdescs[nexttx].tmd1 = 1072 htole32(LE_T1_ONES | 1073 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1074 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1075 LE_T1_BCNT_MASK)); 1076 lasttx = nexttx; 1077 } 1078 } else { 1079 for (nexttx = sc->sc_txnext, seg = 0; 1080 seg < dmamap->dm_nsegs; 1081 seg++, nexttx = PCN_NEXTTX(nexttx)) { 1082 /* 1083 * If this is the first descriptor we're 1084 * enqueueing, don't set the OWN bit just 1085 * yet. That could cause a race condition. 1086 * We'll do it below. 1087 */ 1088 sc->sc_txdescs[nexttx].tmd0 = 1089 htole32(dmamap->dm_segs[seg].ds_addr); 1090 sc->sc_txdescs[nexttx].tmd2 = 0; 1091 sc->sc_txdescs[nexttx].tmd1 = 1092 htole32(LE_T1_ONES | 1093 (nexttx == sc->sc_txnext ? 0 : LE_T1_OWN) | 1094 (LE_BCNT(dmamap->dm_segs[seg].ds_len) & 1095 LE_T1_BCNT_MASK)); 1096 lasttx = nexttx; 1097 } 1098 } 1099 1100 KASSERT(lasttx != -1); 1101 /* Interrupt on the packet, if appropriate. */ 1102 if ((sc->sc_txsnext & PCN_TXINTR_MASK) == 0) 1103 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); 1104 1105 /* Set `start of packet' and `end of packet' appropriately. */ 1106 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); 1107 sc->sc_txdescs[sc->sc_txnext].tmd1 |= 1108 htole32(LE_T1_OWN | LE_T1_STP); 1109 1110 /* Sync the descriptors we're using. */ 1111 PCN_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1113 1114 /* Kick the transmitter. */ 1115 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_TDMD); 1116 1117 /* 1118 * Store a pointer to the packet so we can free it later, 1119 * and remember what txdirty will be once the packet is 1120 * done. 1121 */ 1122 txs->txs_mbuf = m0; 1123 txs->txs_firstdesc = sc->sc_txnext; 1124 txs->txs_lastdesc = lasttx; 1125 1126 /* Advance the tx pointer. */ 1127 sc->sc_txfree -= dmamap->dm_nsegs; 1128 sc->sc_txnext = nexttx; 1129 1130 sc->sc_txsfree--; 1131 sc->sc_txsnext = PCN_NEXTTXS(sc->sc_txsnext); 1132 1133 /* Pass the packet to any BPF listeners. */ 1134 bpf_mtap(ifp, m0, BPF_D_OUT); 1135 } 1136 1137 if (sc->sc_txsfree == 0 || sc->sc_txfree == 0) { 1138 /* No more slots left; notify upper layer. */ 1139 ifp->if_flags |= IFF_OACTIVE; 1140 } 1141 1142 if (sc->sc_txfree != ofree) { 1143 /* Set a watchdog timer in case the chip flakes out. */ 1144 ifp->if_timer = 5; 1145 } 1146 } 1147 1148 /* 1149 * pcn_watchdog: [ifnet interface function] 1150 * 1151 * Watchdog timer handler. 1152 */ 1153 static void 1154 pcn_watchdog(struct ifnet *ifp) 1155 { 1156 struct pcn_softc *sc = ifp->if_softc; 1157 1158 /* 1159 * Since we're not interrupting every packet, sweep 1160 * up before we report an error. 1161 */ 1162 pcn_txintr(sc); 1163 1164 if (sc->sc_txfree != PCN_NTXDESC) { 1165 printf("%s: device timeout (txfree %d txsfree %d)\n", 1166 device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree); 1167 if_statinc(ifp, if_oerrors); 1168 1169 /* Reset the interface. */ 1170 (void) pcn_init(ifp); 1171 } 1172 1173 /* Try to get more packets going. */ 1174 pcn_start(ifp); 1175 } 1176 1177 /* 1178 * pcn_ioctl: [ifnet interface function] 1179 * 1180 * Handle control requests from the operator. 1181 */ 1182 static int 1183 pcn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1184 { 1185 int s, error; 1186 1187 s = splnet(); 1188 1189 switch (cmd) { 1190 default: 1191 error = ether_ioctl(ifp, cmd, data); 1192 if (error == ENETRESET) { 1193 /* 1194 * Multicast list has changed; set the hardware filter 1195 * accordingly. 1196 */ 1197 if (ifp->if_flags & IFF_RUNNING) 1198 error = pcn_init(ifp); 1199 else 1200 error = 0; 1201 } 1202 break; 1203 } 1204 1205 /* Try to get more packets going. */ 1206 pcn_start(ifp); 1207 1208 splx(s); 1209 return error; 1210 } 1211 1212 /* 1213 * pcn_intr: 1214 * 1215 * Interrupt service routine. 1216 */ 1217 static int 1218 pcn_intr(void *arg) 1219 { 1220 struct pcn_softc *sc = arg; 1221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1222 uint32_t csr0; 1223 int wantinit, handled = 0; 1224 1225 for (wantinit = 0; wantinit == 0;) { 1226 csr0 = pcn_csr_read(sc, LE_CSR0); 1227 if ((csr0 & LE_C0_INTR) == 0) 1228 break; 1229 1230 rnd_add_uint32(&sc->rnd_source, csr0); 1231 1232 /* ACK the bits and re-enable interrupts. */ 1233 pcn_csr_write(sc, LE_CSR0, csr0 & 1234 (LE_C0_INEA | LE_C0_BABL | LE_C0_MISS | LE_C0_MERR | 1235 LE_C0_RINT | LE_C0_TINT | LE_C0_IDON)); 1236 1237 handled = 1; 1238 1239 if (csr0 & LE_C0_RINT) { 1240 PCN_EVCNT_INCR(&sc->sc_ev_rxintr); 1241 wantinit = pcn_rxintr(sc); 1242 } 1243 1244 if (csr0 & LE_C0_TINT) { 1245 PCN_EVCNT_INCR(&sc->sc_ev_txintr); 1246 pcn_txintr(sc); 1247 } 1248 1249 if (csr0 & LE_C0_ERR) { 1250 if (csr0 & LE_C0_BABL) { 1251 PCN_EVCNT_INCR(&sc->sc_ev_babl); 1252 if_statinc(ifp, if_oerrors); 1253 } 1254 if (csr0 & LE_C0_MISS) { 1255 PCN_EVCNT_INCR(&sc->sc_ev_miss); 1256 if_statinc(ifp, if_ierrors); 1257 } 1258 if (csr0 & LE_C0_MERR) { 1259 PCN_EVCNT_INCR(&sc->sc_ev_merr); 1260 printf("%s: memory error\n", 1261 device_xname(sc->sc_dev)); 1262 wantinit = 1; 1263 break; 1264 } 1265 } 1266 1267 if ((csr0 & LE_C0_RXON) == 0) { 1268 printf("%s: receiver disabled\n", 1269 device_xname(sc->sc_dev)); 1270 if_statinc(ifp, if_ierrors); 1271 wantinit = 1; 1272 } 1273 1274 if ((csr0 & LE_C0_TXON) == 0) { 1275 printf("%s: transmitter disabled\n", 1276 device_xname(sc->sc_dev)); 1277 if_statinc(ifp, if_oerrors); 1278 wantinit = 1; 1279 } 1280 } 1281 1282 if (handled) { 1283 if (wantinit) 1284 pcn_init(ifp); 1285 1286 /* Try to get more packets going. */ 1287 if_schedule_deferred_start(ifp); 1288 } 1289 1290 return handled; 1291 } 1292 1293 /* 1294 * pcn_spnd: 1295 * 1296 * Suspend the chip. 1297 */ 1298 static void 1299 pcn_spnd(struct pcn_softc *sc) 1300 { 1301 int i; 1302 1303 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5 | LE_C5_SPND); 1304 1305 for (i = 0; i < 10000; i++) { 1306 if (pcn_csr_read(sc, LE_CSR5) & LE_C5_SPND) 1307 return; 1308 delay(5); 1309 } 1310 1311 printf("%s: WARNING: chip failed to enter suspended state\n", 1312 device_xname(sc->sc_dev)); 1313 } 1314 1315 /* 1316 * pcn_txintr: 1317 * 1318 * Helper; handle transmit interrupts. 1319 */ 1320 static void 1321 pcn_txintr(struct pcn_softc *sc) 1322 { 1323 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1324 struct pcn_txsoft *txs; 1325 uint32_t tmd1, tmd2, tmd; 1326 int i, j; 1327 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 1330 /* 1331 * Go through our Tx list and free mbufs for those 1332 * frames which have been transmitted. 1333 */ 1334 for (i = sc->sc_txsdirty; sc->sc_txsfree != PCN_TXQUEUELEN; 1335 i = PCN_NEXTTXS(i), sc->sc_txsfree++) { 1336 txs = &sc->sc_txsoft[i]; 1337 1338 PCN_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1340 1341 tmd1 = le32toh(sc->sc_txdescs[txs->txs_lastdesc].tmd1); 1342 if (tmd1 & LE_T1_OWN) 1343 break; 1344 1345 /* 1346 * Slightly annoying -- we have to loop through the 1347 * descriptors we've used looking for ERR, since it 1348 * can appear on any descriptor in the chain. 1349 */ 1350 for (j = txs->txs_firstdesc;; j = PCN_NEXTTX(j)) { 1351 tmd = le32toh(sc->sc_txdescs[j].tmd1); 1352 if (tmd & LE_T1_ERR) { 1353 if_statinc(ifp, if_oerrors); 1354 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1355 tmd2 = le32toh(sc->sc_txdescs[j].tmd0); 1356 else 1357 tmd2 = le32toh(sc->sc_txdescs[j].tmd2); 1358 if (tmd2 & LE_T2_UFLO) { 1359 if (sc->sc_xmtsp < LE_C80_XMTSP_MAX) { 1360 sc->sc_xmtsp++; 1361 printf("%s: transmit " 1362 "underrun; new threshold: " 1363 "%s\n", 1364 device_xname(sc->sc_dev), 1365 sc->sc_xmtsp_desc[ 1366 sc->sc_xmtsp]); 1367 pcn_spnd(sc); 1368 pcn_csr_write(sc, LE_CSR80, 1369 LE_C80_RCVFW(sc->sc_rcvfw) | 1370 LE_C80_XMTSP(sc->sc_xmtsp) | 1371 LE_C80_XMTFW(sc->sc_xmtfw)); 1372 pcn_csr_write(sc, LE_CSR5, 1373 sc->sc_csr5); 1374 } else { 1375 printf("%s: transmit " 1376 "underrun\n", 1377 device_xname(sc->sc_dev)); 1378 } 1379 } else if (tmd2 & LE_T2_BUFF) { 1380 printf("%s: transmit buffer error\n", 1381 device_xname(sc->sc_dev)); 1382 } 1383 if (tmd2 & LE_T2_LCOL) 1384 if_statinc(ifp, if_collisions); 1385 if (tmd2 & LE_T2_RTRY) 1386 if_statadd(ifp, if_collisions, 16); 1387 goto next_packet; 1388 } 1389 if (j == txs->txs_lastdesc) 1390 break; 1391 } 1392 if (tmd1 & LE_T1_ONE) 1393 if_statinc(ifp, if_collisions); 1394 else if (tmd & LE_T1_MORE) { 1395 /* Real number is unknown. */ 1396 if_statadd(ifp, if_collisions, 2); 1397 } 1398 if_statinc(ifp, if_opackets); 1399 next_packet: 1400 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1401 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1402 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1403 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1404 m_freem(txs->txs_mbuf); 1405 txs->txs_mbuf = NULL; 1406 } 1407 1408 /* Update the dirty transmit buffer pointer. */ 1409 sc->sc_txsdirty = i; 1410 1411 /* 1412 * If there are no more pending transmissions, cancel the watchdog 1413 * timer. 1414 */ 1415 if (sc->sc_txsfree == PCN_TXQUEUELEN) 1416 ifp->if_timer = 0; 1417 } 1418 1419 /* 1420 * pcn_rxintr: 1421 * 1422 * Helper; handle receive interrupts. 1423 */ 1424 static int 1425 pcn_rxintr(struct pcn_softc *sc) 1426 { 1427 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1428 struct pcn_rxsoft *rxs; 1429 struct mbuf *m; 1430 uint32_t rmd1; 1431 int i, len; 1432 1433 for (i = sc->sc_rxptr;; i = PCN_NEXTRX(i)) { 1434 rxs = &sc->sc_rxsoft[i]; 1435 1436 PCN_CDRXSYNC(sc, i, 1437 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1438 1439 rmd1 = le32toh(sc->sc_rxdescs[i].rmd1); 1440 1441 if (rmd1 & LE_R1_OWN) 1442 break; 1443 1444 /* 1445 * Check for errors and make sure the packet fit into 1446 * a single buffer. We have structured this block of 1447 * code the way it is in order to compress it into 1448 * one test in the common case (no error). 1449 */ 1450 if (__predict_false((rmd1 & (LE_R1_STP | LE_R1_ENP |LE_R1_ERR)) 1451 != (LE_R1_STP | LE_R1_ENP))) { 1452 /* Make sure the packet is in a single buffer. */ 1453 if ((rmd1 & (LE_R1_STP | LE_R1_ENP)) != 1454 (LE_R1_STP | LE_R1_ENP)) { 1455 printf("%s: packet spilled into next buffer\n", 1456 device_xname(sc->sc_dev)); 1457 return 1; /* pcn_intr() will re-init */ 1458 } 1459 1460 /* 1461 * If the packet had an error, simple recycle the 1462 * buffer. 1463 */ 1464 if (rmd1 & LE_R1_ERR) { 1465 if_statinc(ifp, if_ierrors); 1466 /* 1467 * If we got an overflow error, chances 1468 * are there will be a CRC error. In 1469 * this case, just print the overflow 1470 * error, and skip the others. 1471 */ 1472 if (rmd1 & LE_R1_OFLO) 1473 printf("%s: overflow error\n", 1474 device_xname(sc->sc_dev)); 1475 else { 1476 #define PRINTIT(x, str) \ 1477 if (rmd1 & (x)) \ 1478 printf("%s: %s\n", \ 1479 device_xname(sc->sc_dev), \ 1480 str); 1481 PRINTIT(LE_R1_FRAM, "framing error"); 1482 PRINTIT(LE_R1_CRC, "CRC error"); 1483 PRINTIT(LE_R1_BUFF, "buffer error"); 1484 } 1485 #undef PRINTIT 1486 PCN_INIT_RXDESC(sc, i); 1487 continue; 1488 } 1489 } 1490 1491 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1492 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1493 1494 /* 1495 * No errors; receive the packet. 1496 */ 1497 if (sc->sc_swstyle == LE_B20_SSTYLE_PCNETPCI3) 1498 len = le32toh(sc->sc_rxdescs[i].rmd0) & LE_R1_BCNT_MASK; 1499 else 1500 len = le32toh(sc->sc_rxdescs[i].rmd2) & LE_R1_BCNT_MASK; 1501 1502 /* 1503 * The LANCE family includes the CRC with every packet; 1504 * trim it off here. 1505 */ 1506 len -= ETHER_CRC_LEN; 1507 1508 /* 1509 * If the packet is small enough to fit in a 1510 * single header mbuf, allocate one and copy 1511 * the data into it. This greatly reduces 1512 * memory consumption when we receive lots 1513 * of small packets. 1514 * 1515 * Otherwise, we add a new buffer to the receive 1516 * chain. If this fails, we drop the packet and 1517 * recycle the old buffer. 1518 */ 1519 if (pcn_copy_small != 0 && len <= (MHLEN - 2)) { 1520 MGETHDR(m, M_DONTWAIT, MT_DATA); 1521 if (m == NULL) 1522 goto dropit; 1523 m->m_data += 2; 1524 memcpy(mtod(m, void *), 1525 mtod(rxs->rxs_mbuf, void *), len); 1526 PCN_INIT_RXDESC(sc, i); 1527 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1528 rxs->rxs_dmamap->dm_mapsize, 1529 BUS_DMASYNC_PREREAD); 1530 } else { 1531 m = rxs->rxs_mbuf; 1532 if (pcn_add_rxbuf(sc, i) != 0) { 1533 dropit: 1534 if_statinc(ifp, if_ierrors); 1535 PCN_INIT_RXDESC(sc, i); 1536 bus_dmamap_sync(sc->sc_dmat, 1537 rxs->rxs_dmamap, 0, 1538 rxs->rxs_dmamap->dm_mapsize, 1539 BUS_DMASYNC_PREREAD); 1540 continue; 1541 } 1542 } 1543 1544 m_set_rcvif(m, ifp); 1545 m->m_pkthdr.len = m->m_len = len; 1546 1547 /* Pass it on. */ 1548 if_percpuq_enqueue(ifp->if_percpuq, m); 1549 } 1550 1551 /* Update the receive pointer. */ 1552 sc->sc_rxptr = i; 1553 return 0; 1554 } 1555 1556 /* 1557 * pcn_tick: 1558 * 1559 * One second timer, used to tick the MII. 1560 */ 1561 static void 1562 pcn_tick(void *arg) 1563 { 1564 struct pcn_softc *sc = arg; 1565 int s; 1566 1567 s = splnet(); 1568 mii_tick(&sc->sc_mii); 1569 splx(s); 1570 1571 callout_schedule(&sc->sc_tick_ch, hz); 1572 } 1573 1574 /* 1575 * pcn_reset: 1576 * 1577 * Perform a soft reset on the PCnet-PCI. 1578 */ 1579 static void 1580 pcn_reset(struct pcn_softc *sc) 1581 { 1582 1583 /* 1584 * The PCnet-PCI chip is reset by reading from the 1585 * RESET register. Note that while the NE2100 LANCE 1586 * boards require a write after the read, the PCnet-PCI 1587 * chips do not require this. 1588 * 1589 * Since we don't know if we're in 16-bit or 32-bit 1590 * mode right now, issue both (it's safe) in the 1591 * hopes that one will succeed. 1592 */ 1593 (void) bus_space_read_2(sc->sc_st, sc->sc_sh, PCN16_RESET); 1594 (void) bus_space_read_4(sc->sc_st, sc->sc_sh, PCN32_RESET); 1595 1596 /* Wait 1ms for it to finish. */ 1597 delay(1000); 1598 1599 /* 1600 * Select 32-bit I/O mode by issuing a 32-bit write to the 1601 * RDP. Since the RAP is 0 after a reset, writing a 0 1602 * to RDP is safe (since it simply clears CSR0). 1603 */ 1604 bus_space_write_4(sc->sc_st, sc->sc_sh, PCN32_RDP, 0); 1605 } 1606 1607 /* 1608 * pcn_init: [ifnet interface function] 1609 * 1610 * Initialize the interface. Must be called at splnet(). 1611 */ 1612 static int 1613 pcn_init(struct ifnet *ifp) 1614 { 1615 struct pcn_softc *sc = ifp->if_softc; 1616 struct pcn_rxsoft *rxs; 1617 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 1618 int i, error = 0; 1619 uint32_t reg; 1620 1621 /* Cancel any pending I/O. */ 1622 pcn_stop(ifp, 0); 1623 1624 /* Reset the chip to a known state. */ 1625 pcn_reset(sc); 1626 1627 /* 1628 * On the Am79c970, select SSTYLE 2, and SSTYLE 3 on everything 1629 * else. 1630 * 1631 * XXX It'd be really nice to use SSTYLE 2 on all the chips, 1632 * because the structure layout is compatible with ILACC, 1633 * but the burst mode is only available in SSTYLE 3, and 1634 * burst mode should provide some performance enhancement. 1635 */ 1636 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970) 1637 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI2; 1638 else 1639 sc->sc_swstyle = LE_B20_SSTYLE_PCNETPCI3; 1640 pcn_bcr_write(sc, LE_BCR20, sc->sc_swstyle); 1641 1642 /* Initialize the transmit descriptor ring. */ 1643 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1644 PCN_CDTXSYNC(sc, 0, PCN_NTXDESC, 1645 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1646 sc->sc_txfree = PCN_NTXDESC; 1647 sc->sc_txnext = 0; 1648 1649 /* Initialize the transmit job descriptors. */ 1650 for (i = 0; i < PCN_TXQUEUELEN; i++) 1651 sc->sc_txsoft[i].txs_mbuf = NULL; 1652 sc->sc_txsfree = PCN_TXQUEUELEN; 1653 sc->sc_txsnext = 0; 1654 sc->sc_txsdirty = 0; 1655 1656 /* 1657 * Initialize the receive descriptor and receive job 1658 * descriptor rings. 1659 */ 1660 for (i = 0; i < PCN_NRXDESC; i++) { 1661 rxs = &sc->sc_rxsoft[i]; 1662 if (rxs->rxs_mbuf == NULL) { 1663 if ((error = pcn_add_rxbuf(sc, i)) != 0) { 1664 printf("%s: unable to allocate or map rx " 1665 "buffer %d, error = %d\n", 1666 device_xname(sc->sc_dev), i, error); 1667 /* 1668 * XXX Should attempt to run with fewer receive 1669 * XXX buffers instead of just failing. 1670 */ 1671 pcn_rxdrain(sc); 1672 goto out; 1673 } 1674 } else 1675 PCN_INIT_RXDESC(sc, i); 1676 } 1677 sc->sc_rxptr = 0; 1678 1679 /* Initialize MODE for the initialization block. */ 1680 sc->sc_mode = 0; 1681 if (ifp->if_flags & IFF_PROMISC) 1682 sc->sc_mode |= LE_C15_PROM; 1683 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1684 sc->sc_mode |= LE_C15_DRCVBC; 1685 1686 /* 1687 * If we have MII, simply select MII in the MODE register, 1688 * and clear ASEL. Otherwise, let ASEL stand (for now), 1689 * and leave PORTSEL alone (it is ignored with ASEL is set). 1690 */ 1691 if (sc->sc_flags & PCN_F_HAS_MII) { 1692 pcn_bcr_write(sc, LE_BCR2, 1693 pcn_bcr_read(sc, LE_BCR2) & ~LE_B2_ASEL); 1694 sc->sc_mode |= LE_C15_PORTSEL(PORTSEL_MII); 1695 1696 /* 1697 * Disable MII auto-negotiation. We handle that in 1698 * our own MII layer. 1699 */ 1700 pcn_bcr_write(sc, LE_BCR32, 1701 pcn_bcr_read(sc, LE_BCR32) | LE_B32_DANAS); 1702 } 1703 1704 /* 1705 * Set the Tx and Rx descriptor ring addresses in the init 1706 * block, the TLEN and RLEN other fields of the init block 1707 * MODE register. 1708 */ 1709 sc->sc_initblock.init_rdra = htole32(PCN_CDRXADDR(sc, 0)); 1710 sc->sc_initblock.init_tdra = htole32(PCN_CDTXADDR(sc, 0)); 1711 sc->sc_initblock.init_mode = htole32(sc->sc_mode | 1712 (((uint32_t)ffs(PCN_NTXDESC) - 1) << 28) | 1713 ((ffs(PCN_NRXDESC) - 1) << 20)); 1714 1715 /* Set the station address in the init block. */ 1716 sc->sc_initblock.init_padr[0] = htole32(enaddr[0] | 1717 (enaddr[1] << 8) | (enaddr[2] << 16) | 1718 ((uint32_t)enaddr[3] << 24)); 1719 sc->sc_initblock.init_padr[1] = htole32(enaddr[4] | 1720 (enaddr[5] << 8)); 1721 1722 /* Set the multicast filter in the init block. */ 1723 pcn_set_filter(sc); 1724 1725 /* Initialize CSR3. */ 1726 pcn_csr_write(sc, LE_CSR3, LE_C3_MISSM | LE_C3_IDONM | LE_C3_DXSUFLO); 1727 1728 /* Initialize CSR4. */ 1729 pcn_csr_write(sc, LE_CSR4, LE_C4_DMAPLUS | LE_C4_APAD_XMT | 1730 LE_C4_MFCOM | LE_C4_RCVCCOM | LE_C4_TXSTRTM); 1731 1732 /* Initialize CSR5. */ 1733 sc->sc_csr5 = LE_C5_LTINTEN | LE_C5_SINTE; 1734 pcn_csr_write(sc, LE_CSR5, sc->sc_csr5); 1735 1736 /* 1737 * If we have an Am79c971 or greater, initialize CSR7. 1738 * 1739 * XXX Might be nice to use the MII auto-poll interrupt someday. 1740 */ 1741 switch (sc->sc_variant->pcv_chipid) { 1742 case PARTID_Am79c970: 1743 case PARTID_Am79c970A: 1744 /* Not available on these chips. */ 1745 break; 1746 1747 default: 1748 pcn_csr_write(sc, LE_CSR7, LE_C7_FASTSPNDE); 1749 break; 1750 } 1751 1752 /* 1753 * On the Am79c970A and greater, initialize BCR18 to 1754 * enable burst mode. 1755 * 1756 * Also enable the "no underflow" option on the Am79c971 and 1757 * higher, which prevents the chip from generating transmit 1758 * underflows, yet sill provides decent performance. Note if 1759 * chip is not connected to external SRAM, then we still have 1760 * to handle underflow errors (the NOUFLO bit is ignored in 1761 * that case). 1762 */ 1763 reg = pcn_bcr_read(sc, LE_BCR18); 1764 switch (sc->sc_variant->pcv_chipid) { 1765 case PARTID_Am79c970: 1766 break; 1767 1768 case PARTID_Am79c970A: 1769 reg |= LE_B18_BREADE | LE_B18_BWRITE; 1770 break; 1771 1772 default: 1773 reg |= LE_B18_BREADE | LE_B18_BWRITE | LE_B18_NOUFLO; 1774 break; 1775 } 1776 pcn_bcr_write(sc, LE_BCR18, reg); 1777 1778 /* 1779 * Initialize CSR80 (FIFO thresholds for Tx and Rx). 1780 */ 1781 pcn_csr_write(sc, LE_CSR80, LE_C80_RCVFW(sc->sc_rcvfw) | 1782 LE_C80_XMTSP(sc->sc_xmtsp) | LE_C80_XMTFW(sc->sc_xmtfw)); 1783 1784 /* 1785 * Send the init block to the chip, and wait for it 1786 * to be processed. 1787 */ 1788 PCN_CDINITSYNC(sc, BUS_DMASYNC_PREWRITE); 1789 pcn_csr_write(sc, LE_CSR1, PCN_CDINITADDR(sc) & 0xffff); 1790 pcn_csr_write(sc, LE_CSR2, (PCN_CDINITADDR(sc) >> 16) & 0xffff); 1791 pcn_csr_write(sc, LE_CSR0, LE_C0_INIT); 1792 delay(100); 1793 for (i = 0; i < 10000; i++) { 1794 if (pcn_csr_read(sc, LE_CSR0) & LE_C0_IDON) 1795 break; 1796 delay(10); 1797 } 1798 PCN_CDINITSYNC(sc, BUS_DMASYNC_POSTWRITE); 1799 if (i == 10000) { 1800 printf("%s: timeout processing init block\n", 1801 device_xname(sc->sc_dev)); 1802 error = EIO; 1803 goto out; 1804 } 1805 1806 /* Set the media. */ 1807 if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0) 1808 goto out; 1809 1810 /* Enable interrupts and external activity (and ACK IDON). */ 1811 pcn_csr_write(sc, LE_CSR0, LE_C0_INEA | LE_C0_STRT | LE_C0_IDON); 1812 1813 if (sc->sc_flags & PCN_F_HAS_MII) { 1814 /* Start the one second MII clock. */ 1815 callout_schedule(&sc->sc_tick_ch, hz); 1816 } 1817 1818 /* ...all done! */ 1819 ifp->if_flags |= IFF_RUNNING; 1820 ifp->if_flags &= ~IFF_OACTIVE; 1821 1822 out: 1823 if (error) 1824 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1825 return error; 1826 } 1827 1828 /* 1829 * pcn_rxdrain: 1830 * 1831 * Drain the receive queue. 1832 */ 1833 static void 1834 pcn_rxdrain(struct pcn_softc *sc) 1835 { 1836 struct pcn_rxsoft *rxs; 1837 int i; 1838 1839 for (i = 0; i < PCN_NRXDESC; i++) { 1840 rxs = &sc->sc_rxsoft[i]; 1841 if (rxs->rxs_mbuf != NULL) { 1842 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1843 m_freem(rxs->rxs_mbuf); 1844 rxs->rxs_mbuf = NULL; 1845 } 1846 } 1847 } 1848 1849 /* 1850 * pcn_stop: [ifnet interface function] 1851 * 1852 * Stop transmission on the interface. 1853 */ 1854 static void 1855 pcn_stop(struct ifnet *ifp, int disable) 1856 { 1857 struct pcn_softc *sc = ifp->if_softc; 1858 struct pcn_txsoft *txs; 1859 int i; 1860 1861 if (sc->sc_flags & PCN_F_HAS_MII) { 1862 /* Stop the one second clock. */ 1863 callout_stop(&sc->sc_tick_ch); 1864 1865 /* Down the MII. */ 1866 mii_down(&sc->sc_mii); 1867 } 1868 1869 /* Stop the chip. */ 1870 pcn_csr_write(sc, LE_CSR0, LE_C0_STOP); 1871 1872 /* Release any queued transmit buffers. */ 1873 for (i = 0; i < PCN_TXQUEUELEN; i++) { 1874 txs = &sc->sc_txsoft[i]; 1875 if (txs->txs_mbuf != NULL) { 1876 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1877 m_freem(txs->txs_mbuf); 1878 txs->txs_mbuf = NULL; 1879 } 1880 } 1881 1882 /* Mark the interface as down and cancel the watchdog timer. */ 1883 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1884 ifp->if_timer = 0; 1885 1886 if (disable) 1887 pcn_rxdrain(sc); 1888 } 1889 1890 /* 1891 * pcn_add_rxbuf: 1892 * 1893 * Add a receive buffer to the indicated descriptor. 1894 */ 1895 static int 1896 pcn_add_rxbuf(struct pcn_softc *sc, int idx) 1897 { 1898 struct pcn_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1899 struct mbuf *m; 1900 int error; 1901 1902 MGETHDR(m, M_DONTWAIT, MT_DATA); 1903 if (m == NULL) 1904 return ENOBUFS; 1905 1906 MCLGET(m, M_DONTWAIT); 1907 if ((m->m_flags & M_EXT) == 0) { 1908 m_freem(m); 1909 return ENOBUFS; 1910 } 1911 1912 if (rxs->rxs_mbuf != NULL) 1913 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1914 1915 rxs->rxs_mbuf = m; 1916 1917 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1918 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1919 BUS_DMA_READ | BUS_DMA_NOWAIT); 1920 if (error) { 1921 printf("%s: can't load rx DMA map %d, error = %d\n", 1922 device_xname(sc->sc_dev), idx, error); 1923 panic("pcn_add_rxbuf"); 1924 } 1925 1926 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1927 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1928 1929 PCN_INIT_RXDESC(sc, idx); 1930 1931 return 0; 1932 } 1933 1934 /* 1935 * pcn_set_filter: 1936 * 1937 * Set up the receive filter. 1938 */ 1939 static void 1940 pcn_set_filter(struct pcn_softc *sc) 1941 { 1942 struct ethercom *ec = &sc->sc_ethercom; 1943 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1944 struct ether_multi *enm; 1945 struct ether_multistep step; 1946 uint32_t crc; 1947 1948 /* 1949 * Set up the multicast address filter by passing all multicast 1950 * addresses through a CRC generator, and then using the high 1951 * order 6 bits as an index into the 64-bit logical address 1952 * filter. The high order bits select the word, while the rest 1953 * of the bits select the bit within the word. 1954 */ 1955 1956 if (ifp->if_flags & IFF_PROMISC) 1957 goto allmulti; 1958 1959 sc->sc_initblock.init_ladrf[0] = 1960 sc->sc_initblock.init_ladrf[1] = 1961 sc->sc_initblock.init_ladrf[2] = 1962 sc->sc_initblock.init_ladrf[3] = 0; 1963 1964 ETHER_LOCK(ec); 1965 ETHER_FIRST_MULTI(step, ec, enm); 1966 while (enm != NULL) { 1967 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1968 /* 1969 * We must listen to a range of multicast addresses. 1970 * For now, just accept all multicasts, rather than 1971 * trying to set only those filter bits needed to match 1972 * the range. (At this time, the only use of address 1973 * ranges is for IP multicast routing, for which the 1974 * range is big enough to require all bits set.) 1975 */ 1976 ETHER_UNLOCK(ec); 1977 goto allmulti; 1978 } 1979 1980 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1981 1982 /* Just want the 6 most significant bits. */ 1983 crc >>= 26; 1984 1985 /* Set the corresponding bit in the filter. */ 1986 sc->sc_initblock.init_ladrf[crc >> 4] |= 1987 htole16(1 << (crc & 0xf)); 1988 1989 ETHER_NEXT_MULTI(step, enm); 1990 } 1991 ETHER_UNLOCK(ec); 1992 1993 ifp->if_flags &= ~IFF_ALLMULTI; 1994 return; 1995 1996 allmulti: 1997 ifp->if_flags |= IFF_ALLMULTI; 1998 sc->sc_initblock.init_ladrf[0] = 1999 sc->sc_initblock.init_ladrf[1] = 2000 sc->sc_initblock.init_ladrf[2] = 2001 sc->sc_initblock.init_ladrf[3] = 0xffff; 2002 } 2003 2004 /* 2005 * pcn_79c970_mediainit: 2006 * 2007 * Initialize media for the Am79c970. 2008 */ 2009 static void 2010 pcn_79c970_mediainit(struct pcn_softc *sc) 2011 { 2012 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2013 struct mii_data * const mii = &sc->sc_mii; 2014 const char *sep = ""; 2015 2016 mii->mii_ifp = ifp; 2017 2018 ifmedia_init(&mii->mii_media, IFM_IMASK, pcn_79c970_mediachange, 2019 pcn_79c970_mediastatus); 2020 2021 #define ADD(str, m, d) \ 2022 do { \ 2023 aprint_normal("%s%s", sep, str); \ 2024 ifmedia_add(&mii->mii_media, IFM_ETHER | (m), (d), NULL); \ 2025 sep = ", "; \ 2026 } while (/*CONSTCOND*/0) 2027 2028 aprint_normal("%s: ", device_xname(sc->sc_dev)); 2029 ADD("10base5", IFM_10_5, PORTSEL_AUI); 2030 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2031 ADD("10base5-FDX", IFM_10_5 | IFM_FDX, PORTSEL_AUI); 2032 ADD("10baseT", IFM_10_T, PORTSEL_10T); 2033 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2034 ADD("10baseT-FDX", IFM_10_T | IFM_FDX, PORTSEL_10T); 2035 ADD("auto", IFM_AUTO, 0); 2036 if (sc->sc_variant->pcv_chipid == PARTID_Am79c970A) 2037 ADD("auto-FDX", IFM_AUTO | IFM_FDX, 0); 2038 aprint_normal("\n"); 2039 2040 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2041 } 2042 2043 /* 2044 * pcn_79c970_mediastatus: [ifmedia interface function] 2045 * 2046 * Get the current interface media status (Am79c970 version). 2047 */ 2048 static void 2049 pcn_79c970_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2050 { 2051 struct pcn_softc *sc = ifp->if_softc; 2052 2053 /* 2054 * The currently selected media is always the active media. 2055 * Note: We have no way to determine what media the AUTO 2056 * process picked. 2057 */ 2058 ifmr->ifm_active = sc->sc_mii.mii_media.ifm_media; 2059 } 2060 2061 /* 2062 * pcn_79c970_mediachange: [ifmedia interface function] 2063 * 2064 * Set hardware to newly-selected media (Am79c970 version). 2065 */ 2066 static int 2067 pcn_79c970_mediachange(struct ifnet *ifp) 2068 { 2069 struct pcn_softc *sc = ifp->if_softc; 2070 uint32_t reg; 2071 2072 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_AUTO) { 2073 /* 2074 * CSR15:PORTSEL doesn't matter. Just set BCR2:ASEL. 2075 */ 2076 reg = pcn_bcr_read(sc, LE_BCR2); 2077 reg |= LE_B2_ASEL; 2078 pcn_bcr_write(sc, LE_BCR2, reg); 2079 } else { 2080 /* 2081 * Clear BCR2:ASEL and set the new CSR15:PORTSEL value. 2082 */ 2083 reg = pcn_bcr_read(sc, LE_BCR2); 2084 reg &= ~LE_B2_ASEL; 2085 pcn_bcr_write(sc, LE_BCR2, reg); 2086 2087 reg = pcn_csr_read(sc, LE_CSR15); 2088 reg = (reg & ~LE_C15_PORTSEL(PORTSEL_MASK)) | 2089 LE_C15_PORTSEL(sc->sc_mii.mii_media.ifm_cur->ifm_data); 2090 pcn_csr_write(sc, LE_CSR15, reg); 2091 } 2092 2093 if ((sc->sc_mii.mii_media.ifm_media & IFM_FDX) != 0) { 2094 reg = LE_B9_FDEN; 2095 if (IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media) == IFM_10_5) 2096 reg |= LE_B9_AUIFD; 2097 pcn_bcr_write(sc, LE_BCR9, reg); 2098 } else 2099 pcn_bcr_write(sc, LE_BCR9, 0); 2100 2101 return 0; 2102 } 2103 2104 /* 2105 * pcn_79c971_mediainit: 2106 * 2107 * Initialize media for the Am79c971. 2108 */ 2109 static void 2110 pcn_79c971_mediainit(struct pcn_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2113 struct mii_data * const mii = &sc->sc_mii; 2114 2115 /* We have MII. */ 2116 sc->sc_flags |= PCN_F_HAS_MII; 2117 2118 /* 2119 * The built-in 10BASE-T interface is mapped to the MII 2120 * on the PCNet-FAST. Unfortunately, there's no EEPROM 2121 * word that tells us which PHY to use. 2122 * This driver used to ignore all but the first PHY to 2123 * answer, but this code was removed to support multiple 2124 * external PHYs. As the default instance will be the first 2125 * one to answer, no harm is done by letting the possibly 2126 * non-connected internal PHY show up. 2127 */ 2128 2129 /* Initialize our media structures and probe the MII. */ 2130 mii->mii_ifp = ifp; 2131 mii->mii_readreg = pcn_mii_readreg; 2132 mii->mii_writereg = pcn_mii_writereg; 2133 mii->mii_statchg = pcn_mii_statchg; 2134 2135 sc->sc_ethercom.ec_mii = mii; 2136 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 2137 2138 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 2139 MII_OFFSET_ANY, 0); 2140 if (LIST_FIRST(&mii->mii_phys) == NULL) { 2141 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 2142 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 2143 } else 2144 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 2145 } 2146 2147 /* 2148 * pcn_mii_readreg: [mii interface function] 2149 * 2150 * Read a PHY register on the MII. 2151 */ 2152 static int 2153 pcn_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2154 { 2155 struct pcn_softc *sc = device_private(self); 2156 2157 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2158 *val = pcn_bcr_read(sc, LE_BCR34) & LE_B34_MIIMD; 2159 if (*val == 0xffff) 2160 return -1; 2161 2162 return 0; 2163 } 2164 2165 /* 2166 * pcn_mii_writereg: [mii interface function] 2167 * 2168 * Write a PHY register on the MII. 2169 */ 2170 static int 2171 pcn_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2172 { 2173 struct pcn_softc *sc = device_private(self); 2174 2175 pcn_bcr_write(sc, LE_BCR33, reg | (phy << PHYAD_SHIFT)); 2176 pcn_bcr_write(sc, LE_BCR34, val); 2177 2178 return 0; 2179 } 2180 2181 /* 2182 * pcn_mii_statchg: [mii interface function] 2183 * 2184 * Callback from MII layer when media changes. 2185 */ 2186 static void 2187 pcn_mii_statchg(struct ifnet *ifp) 2188 { 2189 struct pcn_softc *sc = ifp->if_softc; 2190 2191 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 2192 pcn_bcr_write(sc, LE_BCR9, LE_B9_FDEN); 2193 else 2194 pcn_bcr_write(sc, LE_BCR9, 0); 2195 } 2196
Indexes created Fri Sep 26 20:09:58 GMT 2025