if_re_pci.c revision 1.13.6.2
1 /* $NetBSD: if_re_pci.c,v 1.13.6.2 2006/12/10 07:17:44 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul (at) windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 36 37 /* 38 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 39 * 40 * Written by Bill Paul <wpaul (at) windriver.com> 41 * Senior Networking Software Engineer 42 * Wind River Systems 43 * 44 * NetBSD bus-specific frontends for written by 45 * Jonathan Stone <jonathan (at) netbsd.org> 46 */ 47 48 #include "bpfilter.h" 49 #include "vlan.h" 50 51 #include <sys/types.h> 52 53 #include <sys/param.h> 54 #include <sys/endian.h> 55 #include <sys/systm.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/device.h> 62 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_ether.h> 67 #include <net/if_media.h> 68 #include <net/if_vlanvar.h> 69 70 #include <machine/bus.h> 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 /* 80 * Default to using PIO access for this driver. 81 */ 82 #define RE_USEIOSPACE 83 84 #include <dev/ic/rtl81x9reg.h> 85 #include <dev/ic/rtl81x9var.h> 86 #include <dev/ic/rtl8169var.h> 87 88 struct re_pci_softc { 89 struct rtk_softc sc_rtk; 90 91 void *sc_ih; 92 pci_chipset_tag_t sc_pc; 93 pcitag_t sc_pcitag; 94 }; 95 96 static int re_pci_match(struct device *, struct cfdata *, void *); 97 static void re_pci_attach(struct device *, struct device *, void *); 98 99 /* 100 * Various supported device vendors/types and their names. 101 */ 102 static const struct rtk_type re_devs[] = { 103 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, 104 RTK_HWREV_8139CPLUS, 105 "RealTek 8139C+ 10/100BaseTX" }, 106 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 107 RTK_HWREV_8100E, 108 "RealTek 8100E PCIe 10/100BaseTX" }, 109 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, 110 RTK_HWREV_8101E, 111 "RealTek 8101E PCIe 10/100BaseTX" }, 112 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 113 RTK_HWREV_8168_SPIN1, 114 "RealTek 8168B/8111B PCIe Gigabit Ethernet" }, 115 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, 116 RTK_HWREV_8168_SPIN2, 117 "RealTek 8168B/8111B PCIe Gigabit Ethernet" }, 118 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 119 RTK_HWREV_8169, 120 "RealTek 8169 Gigabit Ethernet" }, 121 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 122 RTK_HWREV_8169S, 123 "RealTek 8169S Single-chip Gigabit Ethernet" }, 124 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 125 RTK_HWREV_8110S, 126 "RealTek 8110S Single-chip Gigabit Ethernet" }, 127 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, 128 RTK_HWREV_8169_8110SB, 129 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 130 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, 131 RTK_HWREV_8169_8110SC, 132 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 133 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_LAPCIGT, 134 RTK_HWREV_8169S, 135 "Corega CG-LAPCIGT Gigabit Ethernet" }, 136 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, 137 RTK_HWREV_8169S, 138 "D-Link DGE-528T Gigabit Ethernet" }, 139 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_USR997902, 140 RTK_HWREV_8169S, 141 "US Robotics (3Com) USR997902 Gigabit Ethernet" }, 142 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, 143 RTK_HWREV_8169S, 144 "Linksys EG1032 rev. 3 Gigabit Ethernet" }, 145 { 0, 0, 0, NULL } 146 }; 147 148 static const struct rtk_hwrev re_hwrevs[] = { 149 { RTK_HWREV_8139, RTK_8139, "" }, 150 { RTK_HWREV_8139A, RTK_8139, "A" }, 151 { RTK_HWREV_8139AG, RTK_8139, "A-G" }, 152 { RTK_HWREV_8139B, RTK_8139, "B" }, 153 { RTK_HWREV_8130, RTK_8139, "8130" }, 154 { RTK_HWREV_8139C, RTK_8139, "C" }, 155 { RTK_HWREV_8139D, RTK_8139, "8139D/8100B/8100C" }, 156 { RTK_HWREV_8139CPLUS, RTK_8139CPLUS, "C+"}, 157 { RTK_HWREV_8168_SPIN1, RTK_8169, "8168B/8111B"}, 158 { RTK_HWREV_8168_SPIN2, RTK_8169, "8168B/8111B"}, 159 { RTK_HWREV_8169, RTK_8169, "8169"}, 160 { RTK_HWREV_8169S, RTK_8169, "8169S"}, 161 { RTK_HWREV_8110S, RTK_8169, "8110S"}, 162 { RTK_HWREV_8169_8110SB, RTK_8169, "8169SB"}, 163 { RTK_HWREV_8169_8110SC, RTK_8169, "8169SC"}, 164 { RTK_HWREV_8100E, RTK_8169, "8100E"}, 165 { RTK_HWREV_8101E, RTK_8169, "8101E"}, 166 { RTK_HWREV_8100, RTK_8139, "8100"}, 167 { RTK_HWREV_8101, RTK_8139, "8101"}, 168 { 0, 0, NULL } 169 }; 170 171 #define RE_LINKSYS_EG1032_SUBID 0x00241737 172 173 CFATTACH_DECL(re_pci, sizeof(struct re_pci_softc), re_pci_match, re_pci_attach, 174 NULL, NULL); 175 176 /* 177 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 178 * IDs against our list and return a device name if we find a match. 179 */ 180 static int 181 re_pci_match(struct device *parent, struct cfdata *match, void *aux) 182 { 183 const struct rtk_type *t; 184 struct pci_attach_args *pa = aux; 185 bus_space_tag_t rtk_btag; 186 bus_space_handle_t rtk_bhandle; 187 bus_size_t bsize; 188 u_int32_t hwrev; 189 pcireg_t subid; 190 191 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 192 193 /* special-case Linksys EG1032, since rev 2 uses sk(4) */ 194 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 195 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 196 subid == RE_LINKSYS_EG1032_SUBID) 197 return 1; 198 199 t = re_devs; 200 201 while (t->rtk_name != NULL) { 202 if ((PCI_VENDOR(pa->pa_id) == t->rtk_vid) && 203 (PCI_PRODUCT(pa->pa_id) == t->rtk_did)) { 204 205 /* 206 * Temporarily map the I/O space 207 * so we can read the chip ID register. 208 */ 209 #ifdef RE_USEIOSPACE 210 if (pci_mapreg_map(pa, RTK_PCI_LOIO, 211 PCI_MAPREG_TYPE_IO, 0, &rtk_btag, 212 &rtk_bhandle, NULL, &bsize)) { 213 aprint_error("can't map i/o space\n"); 214 return 0; 215 } 216 #else 217 if (pci_mapreg_map(pa, RTK_PCI_LOMEM, 218 PCI_MAPREG_TYPE_MEM, 0, &rtk_btag, 219 &rtk_bhandle, NULL, &bsize)) { 220 aprint_error("can't map mem space\n"); 221 return 0; 222 } 223 #endif 224 hwrev = bus_space_read_4(rtk_btag, rtk_bhandle, 225 RTK_TXCFG) & RTK_TXCFG_HWREV; 226 bus_space_unmap(rtk_btag, rtk_bhandle, bsize); 227 if (t->rtk_basetype == hwrev) 228 return 2; /* defeat rtk(4) */ 229 } 230 t++; 231 } 232 233 return 0; 234 } 235 236 static void 237 re_pci_attach(struct device *parent, struct device *self, void *aux) 238 { 239 struct re_pci_softc *psc = (void *)self; 240 struct rtk_softc *sc = &psc->sc_rtk; 241 struct pci_attach_args *pa = aux; 242 pci_chipset_tag_t pc = pa->pa_pc; 243 pci_intr_handle_t ih; 244 const char *intrstr = NULL; 245 const struct rtk_type *t; 246 const struct rtk_hwrev *hw_rev; 247 int hwrev; 248 int error = 0; 249 int pmreg; 250 pcireg_t command; 251 bus_size_t bsize; 252 253 254 /* 255 * Handle power management nonsense. 256 */ 257 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 258 command = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR); 259 if (command & PCI_PMCSR_STATE_MASK) { 260 u_int32_t iobase, membase, irq; 261 262 /* Save important PCI config data. */ 263 iobase = pci_conf_read(pc, pa->pa_tag, RTK_PCI_LOIO); 264 membase = pci_conf_read(pc, pa->pa_tag, RTK_PCI_LOMEM); 265 irq = pci_conf_read(pc, pa->pa_tag, PCI_INTERRUPT_REG); 266 267 /* Reset the power state. */ 268 aprint_normal("%s: chip is is in D%d power mode " 269 "-- setting to D0\n", sc->sc_dev.dv_xname, 270 command & PCI_PMCSR_STATE_MASK); 271 272 command &= ~PCI_PMCSR_STATE_MASK; 273 pci_conf_write(pc, pa->pa_tag, 274 pmreg + PCI_PMCSR, command); 275 276 /* Restore PCI config data. */ 277 pci_conf_write(pc, pa->pa_tag, RTK_PCI_LOIO, iobase); 278 pci_conf_write(pc, pa->pa_tag, RTK_PCI_LOMEM, membase); 279 pci_conf_write(pc, pa->pa_tag, PCI_INTERRUPT_REG, irq); 280 } 281 } 282 283 /* 284 * Map control/status registers. 285 */ 286 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 287 command |= PCI_COMMAND_MASTER_ENABLE; 288 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 289 290 #ifdef RE_USEIOSPACE 291 if (pci_mapreg_map(pa, RTK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 292 &sc->rtk_btag, &sc->rtk_bhandle, NULL, &bsize)) { 293 aprint_error("%s: can't map i/o space\n", sc->sc_dev.dv_xname); 294 return; 295 } 296 #else 297 if (pci_mapreg_map(pa, RTK_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 298 &sc->rtk_btag, &sc->rtk_bhandle, NULL, &bsize)) { 299 aprint_error("%s: can't map mem space\n", sc->sc_dev.dv_xname); 300 return; 301 } 302 #endif 303 t = re_devs; 304 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 305 306 while (t->rtk_name != NULL) { 307 if ((PCI_VENDOR(pa->pa_id) == t->rtk_vid) && 308 (PCI_PRODUCT(pa->pa_id) == t->rtk_did)) { 309 310 if (t->rtk_basetype == hwrev) 311 break; 312 } 313 t++; 314 } 315 aprint_normal(": %s\n", t->rtk_name); 316 317 hw_rev = re_hwrevs; 318 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 319 while (hw_rev->rtk_desc != NULL) { 320 if (hw_rev->rtk_rev == hwrev) { 321 sc->rtk_type = hw_rev->rtk_type; 322 break; 323 } 324 hw_rev++; 325 } 326 327 sc->sc_dmat = pa->pa_dmat; 328 329 /* 330 * No power/enable/disable machinery for PCI attac; 331 * mark the card enabled now. 332 */ 333 sc->sc_flags |= RTK_ENABLED; 334 335 /* Hook interrupt last to avoid having to lock softc */ 336 /* Allocate interrupt */ 337 if (pci_intr_map(pa, &ih)) { 338 aprint_error("%s: couldn't map interrupt\n", 339 sc->sc_dev.dv_xname); 340 return; 341 } 342 intrstr = pci_intr_string(pc, ih); 343 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, re_intr, sc); 344 if (psc->sc_ih == NULL) { 345 aprint_error("%s: couldn't establish interrupt", 346 sc->sc_dev.dv_xname); 347 if (intrstr != NULL) 348 aprint_error(" at %s", intrstr); 349 aprint_error("\n"); 350 return; 351 } 352 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 353 354 re_attach(sc); 355 356 /* 357 * Perform hardware diagnostic on the original RTL8169. 358 * Some 32-bit cards were incorrectly wired and would 359 * malfunction if plugged into a 64-bit slot. 360 */ 361 if (hwrev == RTK_HWREV_8169) { 362 error = re_diag(sc); 363 if (error) { 364 aprint_error( 365 "%s: attach aborted due to hardware diag failure\n", 366 sc->sc_dev.dv_xname); 367 368 re_detach(sc); 369 370 if (psc->sc_ih != NULL) { 371 pci_intr_disestablish(pc, psc->sc_ih); 372 psc->sc_ih = NULL; 373 } 374 375 if (bsize) 376 bus_space_unmap(sc->rtk_btag, sc->rtk_bhandle, 377 bsize); 378 } 379 } 380 } 381
Indexes created Tue Oct 28 12:10:06 GMT 2025