if_rtw_pci.c revision 1.1.2.2
1 /* $NetBSD: if_rtw_pci.c,v 1.1.2.2 2004/10/19 15:56:59 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center; Charles M. Hannum; and David Young. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Realtek RTL8180 802.11 MAC/BBP chip. 42 * 43 * Derived from the ADMtek ADM8211 PCI bus front-end. 44 * 45 * Derived from the ``Tulip'' PCI bus front-end. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_rtw_pci.c,v 1.1.2.2 2004/10/19 15:56:59 skrll Exp $"); 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/device.h> 60 61 #include <machine/endian.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #include <net80211/ieee80211_compat.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_var.h> 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/ic/rtwreg.h> 76 #include <dev/ic/sa2400reg.h> 77 #include <dev/ic/rtwvar.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcidevs.h> 82 83 /* 84 * PCI configuration space registers used by the ADM8211. 85 */ 86 #define RTW_PCI_IOBA 0x10 /* i/o mapped base */ 87 #define RTW_PCI_MMBA 0x14 /* memory mapped base */ 88 89 struct rtw_pci_softc { 90 struct rtw_softc psc_rtw; /* real ADM8211 softc */ 91 92 pci_intr_handle_t psc_ih; /* interrupt handle */ 93 void *psc_intrcookie; 94 95 pci_chipset_tag_t psc_pc; /* our PCI chipset */ 96 pcitag_t psc_pcitag; /* our PCI tag */ 97 }; 98 99 static int rtw_pci_match(struct device *, struct cfdata *, void *); 100 static void rtw_pci_attach(struct device *, struct device *, void *); 101 102 CFATTACH_DECL(rtw_pci, sizeof(struct rtw_pci_softc), 103 rtw_pci_match, rtw_pci_attach, NULL, NULL); 104 105 static const struct rtw_pci_product { 106 u_int32_t app_vendor; /* PCI vendor ID */ 107 u_int32_t app_product; /* PCI product ID */ 108 const char *app_product_name; 109 } rtw_pci_products[] = { 110 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180, 111 "Realtek RTL8180 802.11 MAC/BBP" }, 112 113 { 0, 0, NULL }, 114 }; 115 116 static const struct rtw_pci_product * 117 rtw_pci_lookup(const struct pci_attach_args *pa) 118 { 119 const struct rtw_pci_product *app; 120 121 for (app = rtw_pci_products; 122 app->app_product_name != NULL; 123 app++) { 124 if (PCI_VENDOR(pa->pa_id) == app->app_vendor && 125 PCI_PRODUCT(pa->pa_id) == app->app_product) 126 return (app); 127 } 128 return (NULL); 129 } 130 131 static int 132 rtw_pci_match(struct device *parent, struct cfdata *match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (rtw_pci_lookup(pa) != NULL) 137 return (1); 138 139 return (0); 140 } 141 142 static int 143 rtw_pci_enable(struct rtw_softc *sc) 144 { 145 struct rtw_pci_softc *psc = (void *)sc; 146 147 /* Establish the interrupt. */ 148 psc->psc_intrcookie = pci_intr_establish(psc->psc_pc, psc->psc_ih, 149 IPL_NET, rtw_intr, sc); 150 if (psc->psc_intrcookie == NULL) { 151 printf("%s: unable to establish interrupt\n", 152 sc->sc_dev.dv_xname); 153 return (1); 154 } 155 156 return (0); 157 } 158 159 static void 160 rtw_pci_disable(struct rtw_softc *sc) 161 { 162 struct rtw_pci_softc *psc = (void *)sc; 163 164 /* Unhook the interrupt handler. */ 165 pci_intr_disestablish(psc->psc_pc, psc->psc_intrcookie); 166 psc->psc_intrcookie = NULL; 167 } 168 169 static void 170 rtw_pci_attach(struct device *parent, struct device *self, void *aux) 171 { 172 struct rtw_pci_softc *psc = (void *) self; 173 struct rtw_softc *sc = &psc->psc_rtw; 174 struct rtw_regs *regs = &sc->sc_regs; 175 struct pci_attach_args *pa = aux; 176 pci_chipset_tag_t pc = pa->pa_pc; 177 const char *intrstr = NULL; 178 bus_space_tag_t iot, memt; 179 bus_space_handle_t ioh, memh; 180 int ioh_valid, memh_valid; 181 const struct rtw_pci_product *app; 182 pcireg_t reg; 183 int pmreg; 184 185 psc->psc_pc = pa->pa_pc; 186 psc->psc_pcitag = pa->pa_tag; 187 188 app = rtw_pci_lookup(pa); 189 if (app == NULL) { 190 printf("\n"); 191 panic("rtw_pci_attach: impossible"); 192 } 193 194 /* 195 * No power management hooks. 196 * XXX Maybe we should add some! 197 */ 198 sc->sc_flags |= RTW_F_ENABLED; 199 200 /* 201 * Get revision info, and set some chip-specific variables. 202 */ 203 sc->sc_rev = PCI_REVISION(pa->pa_class); 204 printf(": %s, revision %d.%d\n", app->app_product_name, 205 (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf); 206 207 /* 208 * Check to see if the device is in power-save mode, and 209 * being it out if necessary. 210 * 211 * XXX This code comes almost verbatim from if_tlp_pci.c. I do 212 * not understand it. Tulip clears the "sleep mode" bit in the 213 * CFDA register, first. There is an equivalent (?) register at the 214 * same place in the ADM8211, but the docs do not assign its bits 215 * any meanings. -dcy 216 */ 217 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 218 reg = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR); 219 switch (reg & PCI_PMCSR_STATE_MASK) { 220 case PCI_PMCSR_STATE_D1: 221 case PCI_PMCSR_STATE_D2: 222 printf(": waking up from power state D%d\n%s", 223 reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname); 224 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 225 (reg & ~PCI_PMCSR_STATE_MASK) | 226 PCI_PMCSR_STATE_D0); 227 break; 228 case PCI_PMCSR_STATE_D3: 229 /* 230 * The card has lost all configuration data in 231 * this state, so punt. 232 */ 233 printf(": unable to wake up from power state D3, " 234 "reboot required.\n"); 235 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 236 (reg & ~PCI_PMCSR_STATE_MASK) | 237 PCI_PMCSR_STATE_D0); 238 return; 239 } 240 } 241 242 /* 243 * Map the device. 244 */ 245 ioh_valid = (pci_mapreg_map(pa, RTW_PCI_IOBA, 246 PCI_MAPREG_TYPE_IO, 0, 247 &iot, &ioh, NULL, NULL) == 0); 248 memh_valid = (pci_mapreg_map(pa, RTW_PCI_MMBA, 249 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 250 &memt, &memh, NULL, NULL) == 0); 251 252 if (memh_valid) { 253 regs->r_bt = memt; 254 regs->r_bh = memh; 255 } else if (ioh_valid) { 256 regs->r_bt = iot; 257 regs->r_bh = ioh; 258 } else { 259 printf(": unable to map device registers\n"); 260 return; 261 } 262 263 sc->sc_dmat = pa->pa_dmat; 264 265 /* 266 * Make sure bus mastering is enabled. 267 */ 268 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 269 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 270 PCI_COMMAND_MASTER_ENABLE); 271 272 /* 273 * Map and establish our interrupt. 274 */ 275 if (pci_intr_map(pa, &psc->psc_ih)) { 276 printf("%s: unable to map interrupt\n", 277 sc->sc_dev.dv_xname); 278 return; 279 } 280 intrstr = pci_intr_string(pc, psc->psc_ih); 281 psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET, 282 rtw_intr, sc); 283 if (psc->psc_intrcookie == NULL) { 284 printf("%s: unable to establish interrupt", 285 sc->sc_dev.dv_xname); 286 if (intrstr != NULL) 287 printf(" at %s", intrstr); 288 printf("\n"); 289 return; 290 } 291 292 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 293 294 sc->sc_enable = rtw_pci_enable; 295 sc->sc_disable = rtw_pci_disable; 296 297 /* 298 * Finish off the attach. 299 */ 300 rtw_attach(sc); 301 } 302
Indexes created Wed Oct 01 19:09:53 GMT 2025