if_rtwn.c revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: if_rtwn.c,v 1.1.2.2 2015/09/22 12:05:59 skrll Exp $ */ 2 1.1.2.2 skrll /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 1.1.2.2 skrll #define IEEE80211_NO_HT 4 1.1.2.2 skrll /*- 5 1.1.2.2 skrll * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.1.2.2 skrll * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 1.1.2.2 skrll * 8 1.1.2.2 skrll * Permission to use, copy, modify, and distribute this software for any 9 1.1.2.2 skrll * purpose with or without fee is hereby granted, provided that the above 10 1.1.2.2 skrll * copyright notice and this permission notice appear in all copies. 11 1.1.2.2 skrll * 12 1.1.2.2 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.1.2.2 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.1.2.2 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.1.2.2 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.1.2.2 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.1.2.2 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.1.2.2 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.1.2.2 skrll */ 20 1.1.2.2 skrll 21 1.1.2.2 skrll /* 22 1.1.2.2 skrll * Driver for Realtek RTL8188CE 23 1.1.2.2 skrll */ 24 1.1.2.2 skrll 25 1.1.2.2 skrll #include <sys/cdefs.h> 26 1.1.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.1.2.2 2015/09/22 12:05:59 skrll Exp $"); 27 1.1.2.2 skrll 28 1.1.2.2 skrll #include <sys/param.h> 29 1.1.2.2 skrll #include <sys/sockio.h> 30 1.1.2.2 skrll #include <sys/mbuf.h> 31 1.1.2.2 skrll #include <sys/kernel.h> 32 1.1.2.2 skrll #include <sys/socket.h> 33 1.1.2.2 skrll #include <sys/systm.h> 34 1.1.2.2 skrll #include <sys/callout.h> 35 1.1.2.2 skrll #include <sys/conf.h> 36 1.1.2.2 skrll #include <sys/device.h> 37 1.1.2.2 skrll #include <sys/endian.h> 38 1.1.2.2 skrll #include <sys/mutex.h> 39 1.1.2.2 skrll 40 1.1.2.2 skrll #include <sys/bus.h> 41 1.1.2.2 skrll #include <sys/intr.h> 42 1.1.2.2 skrll 43 1.1.2.2 skrll #include <net/bpf.h> 44 1.1.2.2 skrll #include <net/if.h> 45 1.1.2.2 skrll #include <net/if_arp.h> 46 1.1.2.2 skrll #include <net/if_dl.h> 47 1.1.2.2 skrll #include <net/if_ether.h> 48 1.1.2.2 skrll #include <net/if_media.h> 49 1.1.2.2 skrll #include <net/if_types.h> 50 1.1.2.2 skrll 51 1.1.2.2 skrll #include <netinet/in.h> 52 1.1.2.2 skrll 53 1.1.2.2 skrll #include <net80211/ieee80211_var.h> 54 1.1.2.2 skrll #include <net80211/ieee80211_radiotap.h> 55 1.1.2.2 skrll 56 1.1.2.2 skrll #include <dev/firmload.h> 57 1.1.2.2 skrll 58 1.1.2.2 skrll #include <dev/pci/pcireg.h> 59 1.1.2.2 skrll #include <dev/pci/pcivar.h> 60 1.1.2.2 skrll #include <dev/pci/pcidevs.h> 61 1.1.2.2 skrll 62 1.1.2.2 skrll #include <dev/pci/if_rtwnreg.h> 63 1.1.2.2 skrll 64 1.1.2.2 skrll #ifdef RTWN_DEBUG 65 1.1.2.2 skrll #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 1.1.2.2 skrll #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 1.1.2.2 skrll int rtwn_debug = 0; 68 1.1.2.2 skrll #else 69 1.1.2.2 skrll #define DPRINTF(x) 70 1.1.2.2 skrll #define DPRINTFN(n, x) 71 1.1.2.2 skrll #endif 72 1.1.2.2 skrll 73 1.1.2.2 skrll /* 74 1.1.2.2 skrll * PCI configuration space registers. 75 1.1.2.2 skrll */ 76 1.1.2.2 skrll #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 1.1.2.2 skrll #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 1.1.2.2 skrll 79 1.1.2.2 skrll #define RTWN_INT_ENABLE_TX \ 80 1.1.2.2 skrll (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 1.1.2.2 skrll R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 1.1.2.2 skrll R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 1.1.2.2 skrll #define RTWN_INT_ENABLE_RX \ 84 1.1.2.2 skrll (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 1.1.2.2 skrll #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 1.1.2.2 skrll 87 1.1.2.2 skrll static const struct rtwn_device { 88 1.1.2.2 skrll pci_vendor_id_t rd_vendor; 89 1.1.2.2 skrll pci_product_id_t rd_product; 90 1.1.2.2 skrll } rtwn_devices[] = { 91 1.1.2.2 skrll { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 1.1.2.2 skrll { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 1.1.2.2 skrll }; 94 1.1.2.2 skrll 95 1.1.2.2 skrll static int rtwn_match(device_t, cfdata_t, void *); 96 1.1.2.2 skrll static void rtwn_attach(device_t, device_t, void *); 97 1.1.2.2 skrll static int rtwn_detach(device_t, int); 98 1.1.2.2 skrll static int rtwn_activate(device_t, enum devact); 99 1.1.2.2 skrll 100 1.1.2.2 skrll CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 1.1.2.2 skrll rtwn_attach, rtwn_detach, rtwn_activate); 102 1.1.2.2 skrll 103 1.1.2.2 skrll static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 1.1.2.2 skrll static void rtwn_reset_rx_list(struct rtwn_softc *); 105 1.1.2.2 skrll static void rtwn_free_rx_list(struct rtwn_softc *); 106 1.1.2.2 skrll static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 1.1.2.2 skrll bus_addr_t, size_t, int); 108 1.1.2.2 skrll static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 1.1.2.2 skrll static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 1.1.2.2 skrll static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 1.1.2.2 skrll static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 1.1.2.2 skrll static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 1.1.2.2 skrll static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 1.1.2.2 skrll static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 1.1.2.2 skrll static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 1.1.2.2 skrll static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 1.1.2.2 skrll static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 1.1.2.2 skrll static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 1.1.2.2 skrll static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 1.1.2.2 skrll static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 1.1.2.2 skrll static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 1.1.2.2 skrll static void rtwn_efuse_read(struct rtwn_softc *); 123 1.1.2.2 skrll static int rtwn_read_chipid(struct rtwn_softc *); 124 1.1.2.2 skrll static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 1.1.2.2 skrll static void rtwn_read_rom(struct rtwn_softc *); 126 1.1.2.2 skrll static int rtwn_media_change(struct ifnet *); 127 1.1.2.2 skrll static int rtwn_ra_init(struct rtwn_softc *); 128 1.1.2.2 skrll static int rtwn_get_nettype(struct rtwn_softc *); 129 1.1.2.2 skrll static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 1.1.2.2 skrll static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 1.1.2.2 skrll static void rtwn_set_led(struct rtwn_softc *, int, int); 132 1.1.2.2 skrll static void rtwn_calib_to(void *); 133 1.1.2.2 skrll static void rtwn_next_scan(void *); 134 1.1.2.2 skrll static void rtwn_newassoc(struct ieee80211_node *, int); 135 1.1.2.2 skrll static int rtwn_reset(struct ifnet *); 136 1.1.2.2 skrll static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 1.1.2.2 skrll int); 138 1.1.2.2 skrll static int rtwn_wme_update(struct ieee80211com *); 139 1.1.2.2 skrll static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 1.1.2.2 skrll static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 1.1.2.2 skrll static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 1.1.2.2 skrll struct rtwn_rx_data *, int); 143 1.1.2.2 skrll static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 1.1.2.2 skrll struct ieee80211_node *); 145 1.1.2.2 skrll static void rtwn_tx_done(struct rtwn_softc *, int); 146 1.1.2.2 skrll static void rtwn_start(struct ifnet *); 147 1.1.2.2 skrll static void rtwn_watchdog(struct ifnet *); 148 1.1.2.2 skrll static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 1.1.2.2 skrll static int rtwn_power_on(struct rtwn_softc *); 150 1.1.2.2 skrll static int rtwn_llt_init(struct rtwn_softc *); 151 1.1.2.2 skrll static void rtwn_fw_reset(struct rtwn_softc *); 152 1.1.2.2 skrll static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 1.1.2.2 skrll static int rtwn_load_firmware(struct rtwn_softc *); 154 1.1.2.2 skrll static int rtwn_dma_init(struct rtwn_softc *); 155 1.1.2.2 skrll static void rtwn_mac_init(struct rtwn_softc *); 156 1.1.2.2 skrll static void rtwn_bb_init(struct rtwn_softc *); 157 1.1.2.2 skrll static void rtwn_rf_init(struct rtwn_softc *); 158 1.1.2.2 skrll static void rtwn_cam_init(struct rtwn_softc *); 159 1.1.2.2 skrll static void rtwn_pa_bias_init(struct rtwn_softc *); 160 1.1.2.2 skrll static void rtwn_rxfilter_init(struct rtwn_softc *); 161 1.1.2.2 skrll static void rtwn_edca_init(struct rtwn_softc *); 162 1.1.2.2 skrll static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 1.1.2.2 skrll static void rtwn_get_txpower(struct rtwn_softc *, int, 164 1.1.2.2 skrll struct ieee80211_channel *, struct ieee80211_channel *, 165 1.1.2.2 skrll uint16_t[]); 166 1.1.2.2 skrll static void rtwn_set_txpower(struct rtwn_softc *, 167 1.1.2.2 skrll struct ieee80211_channel *, struct ieee80211_channel *); 168 1.1.2.2 skrll static void rtwn_set_chan(struct rtwn_softc *, 169 1.1.2.2 skrll struct ieee80211_channel *, struct ieee80211_channel *); 170 1.1.2.2 skrll static void rtwn_iq_calib(struct rtwn_softc *); 171 1.1.2.2 skrll static void rtwn_lc_calib(struct rtwn_softc *); 172 1.1.2.2 skrll static void rtwn_temp_calib(struct rtwn_softc *); 173 1.1.2.2 skrll static int rtwn_init(struct ifnet *); 174 1.1.2.2 skrll static void rtwn_init_task(void *); 175 1.1.2.2 skrll static void rtwn_stop(struct ifnet *, int); 176 1.1.2.2 skrll static int rtwn_intr(void *); 177 1.1.2.2 skrll 178 1.1.2.2 skrll /* Aliases. */ 179 1.1.2.2 skrll #define rtwn_bb_write rtwn_write_4 180 1.1.2.2 skrll #define rtwn_bb_read rtwn_read_4 181 1.1.2.2 skrll 182 1.1.2.2 skrll static const struct rtwn_device * 183 1.1.2.2 skrll rtwn_lookup(const struct pci_attach_args *pa) 184 1.1.2.2 skrll { 185 1.1.2.2 skrll const struct rtwn_device *rd; 186 1.1.2.2 skrll int i; 187 1.1.2.2 skrll 188 1.1.2.2 skrll for (i = 0; i < __arraycount(rtwn_devices); i++) { 189 1.1.2.2 skrll rd = &rtwn_devices[i]; 190 1.1.2.2 skrll if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 191 1.1.2.2 skrll PCI_PRODUCT(pa->pa_id) == rd->rd_product) 192 1.1.2.2 skrll return rd; 193 1.1.2.2 skrll } 194 1.1.2.2 skrll return NULL; 195 1.1.2.2 skrll } 196 1.1.2.2 skrll 197 1.1.2.2 skrll static int 198 1.1.2.2 skrll rtwn_match(device_t parent, cfdata_t match, void *aux) 199 1.1.2.2 skrll { 200 1.1.2.2 skrll struct pci_attach_args *pa = aux; 201 1.1.2.2 skrll 202 1.1.2.2 skrll if (rtwn_lookup(pa) != NULL) 203 1.1.2.2 skrll return 1; 204 1.1.2.2 skrll return 0; 205 1.1.2.2 skrll } 206 1.1.2.2 skrll 207 1.1.2.2 skrll static void 208 1.1.2.2 skrll rtwn_attach(device_t parent, device_t self, void *aux) 209 1.1.2.2 skrll { 210 1.1.2.2 skrll struct rtwn_softc *sc = device_private(self); 211 1.1.2.2 skrll struct pci_attach_args *pa = aux; 212 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 213 1.1.2.2 skrll struct ifnet *ifp = GET_IFP(sc); 214 1.1.2.2 skrll int i, error; 215 1.1.2.2 skrll pcireg_t memtype; 216 1.1.2.2 skrll #ifndef __HAVE_PCI_MSI_MSIX 217 1.1.2.2 skrll pci_intr_handle_t ih; 218 1.1.2.2 skrll #endif 219 1.1.2.2 skrll const char *intrstr; 220 1.1.2.2 skrll char intrbuf[PCI_INTRSTR_LEN]; 221 1.1.2.2 skrll 222 1.1.2.2 skrll sc->sc_dev = self; 223 1.1.2.2 skrll sc->sc_dmat = pa->pa_dmat; 224 1.1.2.2 skrll sc->sc_pc = pa->pa_pc; 225 1.1.2.2 skrll sc->sc_tag = pa->pa_tag; 226 1.1.2.2 skrll 227 1.1.2.2 skrll pci_aprint_devinfo(pa, NULL); 228 1.1.2.2 skrll 229 1.1.2.2 skrll callout_init(&sc->scan_to, 0); 230 1.1.2.2 skrll callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 231 1.1.2.2 skrll callout_init(&sc->calib_to, 0); 232 1.1.2.2 skrll callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 233 1.1.2.2 skrll 234 1.1.2.2 skrll sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 235 1.1.2.2 skrll 236 1.1.2.2 skrll /* Power up the device */ 237 1.1.2.2 skrll pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 238 1.1.2.2 skrll 239 1.1.2.2 skrll /* Map control/status registers. */ 240 1.1.2.2 skrll memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 241 1.1.2.2 skrll error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 242 1.1.2.2 skrll &sc->sc_sh, NULL, &sc->sc_mapsize); 243 1.1.2.2 skrll if (error != 0) { 244 1.1.2.2 skrll aprint_error_dev(self, "can't map mem space\n"); 245 1.1.2.2 skrll return; 246 1.1.2.2 skrll } 247 1.1.2.2 skrll 248 1.1.2.2 skrll /* Install interrupt handler. */ 249 1.1.2.2 skrll #ifdef __HAVE_PCI_MSI_MSIX 250 1.1.2.2 skrll if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 251 1.1.2.2 skrll aprint_error_dev(self, "can't map interrupt\n"); 252 1.1.2.2 skrll return; 253 1.1.2.2 skrll } 254 1.1.2.2 skrll intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 255 1.1.2.2 skrll sizeof(intrbuf)); 256 1.1.2.2 skrll sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 257 1.1.2.2 skrll rtwn_intr, sc); 258 1.1.2.2 skrll #else /* !__HAVE_PCI_MSI_MSIX */ 259 1.1.2.2 skrll if (pci_intr_map(pa, &ih)) { 260 1.1.2.2 skrll aprint_error_dev(self, "can't map interrupt\n"); 261 1.1.2.2 skrll return; 262 1.1.2.2 skrll } 263 1.1.2.2 skrll intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf)); 264 1.1.2.2 skrll sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, rtwn_intr, sc); 265 1.1.2.2 skrll #endif /* __HAVE_PCI_MSI_MSIX */ 266 1.1.2.2 skrll if (sc->sc_ih == NULL) { 267 1.1.2.2 skrll aprint_error_dev(self, "can't establish interrupt"); 268 1.1.2.2 skrll if (intrstr != NULL) 269 1.1.2.2 skrll aprint_error(" at %s", intrstr); 270 1.1.2.2 skrll aprint_error("\n"); 271 1.1.2.2 skrll return; 272 1.1.2.2 skrll } 273 1.1.2.2 skrll aprint_normal_dev(self, "interrupting at %s\n", intrstr); 274 1.1.2.2 skrll 275 1.1.2.2 skrll error = rtwn_read_chipid(sc); 276 1.1.2.2 skrll if (error != 0) { 277 1.1.2.2 skrll aprint_error_dev(self, "unsupported test or unknown chip\n"); 278 1.1.2.2 skrll return; 279 1.1.2.2 skrll } 280 1.1.2.2 skrll 281 1.1.2.2 skrll /* Disable PCIe Active State Power Management (ASPM). */ 282 1.1.2.2 skrll if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 283 1.1.2.2 skrll &sc->sc_cap_off, NULL)) { 284 1.1.2.2 skrll uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 285 1.1.2.2 skrll sc->sc_cap_off + PCIE_LCSR); 286 1.1.2.2 skrll lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 287 1.1.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, 288 1.1.2.2 skrll sc->sc_cap_off + PCIE_LCSR, lcsr); 289 1.1.2.2 skrll } 290 1.1.2.2 skrll 291 1.1.2.2 skrll /* Allocate Tx/Rx buffers. */ 292 1.1.2.2 skrll error = rtwn_alloc_rx_list(sc); 293 1.1.2.2 skrll if (error != 0) { 294 1.1.2.2 skrll aprint_error_dev(self, "could not allocate Rx buffers\n"); 295 1.1.2.2 skrll return; 296 1.1.2.2 skrll } 297 1.1.2.2 skrll for (i = 0; i < RTWN_NTXQUEUES; i++) { 298 1.1.2.2 skrll error = rtwn_alloc_tx_list(sc, i); 299 1.1.2.2 skrll if (error != 0) { 300 1.1.2.2 skrll aprint_error_dev(self, 301 1.1.2.2 skrll "could not allocate Tx buffers\n"); 302 1.1.2.2 skrll return; 303 1.1.2.2 skrll } 304 1.1.2.2 skrll } 305 1.1.2.2 skrll 306 1.1.2.2 skrll /* Determine number of Tx/Rx chains. */ 307 1.1.2.2 skrll if (sc->chip & RTWN_CHIP_92C) { 308 1.1.2.2 skrll sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 309 1.1.2.2 skrll sc->nrxchains = 2; 310 1.1.2.2 skrll } else { 311 1.1.2.2 skrll sc->ntxchains = 1; 312 1.1.2.2 skrll sc->nrxchains = 1; 313 1.1.2.2 skrll } 314 1.1.2.2 skrll rtwn_read_rom(sc); 315 1.1.2.2 skrll 316 1.1.2.2 skrll aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 317 1.1.2.2 skrll (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 318 1.1.2.2 skrll sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 319 1.1.2.2 skrll 320 1.1.2.2 skrll /* 321 1.1.2.2 skrll * Setup the 802.11 device. 322 1.1.2.2 skrll */ 323 1.1.2.2 skrll ic->ic_ifp = ifp; 324 1.1.2.2 skrll ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 325 1.1.2.2 skrll ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 326 1.1.2.2 skrll ic->ic_state = IEEE80211_S_INIT; 327 1.1.2.2 skrll 328 1.1.2.2 skrll /* Set device capabilities. */ 329 1.1.2.2 skrll ic->ic_caps = 330 1.1.2.2 skrll IEEE80211_C_MONITOR | /* Monitor mode supported. */ 331 1.1.2.2 skrll IEEE80211_C_IBSS | /* IBSS mode supported */ 332 1.1.2.2 skrll IEEE80211_C_HOSTAP | /* HostAp mode supported */ 333 1.1.2.2 skrll IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 334 1.1.2.2 skrll IEEE80211_C_SHSLOT | /* Short slot time supported. */ 335 1.1.2.2 skrll IEEE80211_C_WME | /* 802.11e */ 336 1.1.2.2 skrll IEEE80211_C_WPA; /* WPA/RSN. */ 337 1.1.2.2 skrll 338 1.1.2.2 skrll #ifndef IEEE80211_NO_HT 339 1.1.2.2 skrll /* Set HT capabilities. */ 340 1.1.2.2 skrll ic->ic_htcaps = 341 1.1.2.2 skrll IEEE80211_HTCAP_CBW20_40 | 342 1.1.2.2 skrll IEEE80211_HTCAP_DSSSCCK40; 343 1.1.2.2 skrll /* Set supported HT rates. */ 344 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) 345 1.1.2.2 skrll ic->ic_sup_mcs[i] = 0xff; 346 1.1.2.2 skrll #endif 347 1.1.2.2 skrll 348 1.1.2.2 skrll /* Set supported .11b and .11g rates. */ 349 1.1.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 350 1.1.2.2 skrll ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 351 1.1.2.2 skrll 352 1.1.2.2 skrll /* Set supported .11b and .11g channels (1 through 14). */ 353 1.1.2.2 skrll for (i = 1; i <= 14; i++) { 354 1.1.2.2 skrll ic->ic_channels[i].ic_freq = 355 1.1.2.2 skrll ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 356 1.1.2.2 skrll ic->ic_channels[i].ic_flags = 357 1.1.2.2 skrll IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 358 1.1.2.2 skrll IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 359 1.1.2.2 skrll } 360 1.1.2.2 skrll 361 1.1.2.2 skrll ifp->if_softc = sc; 362 1.1.2.2 skrll ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 363 1.1.2.2 skrll ifp->if_init = rtwn_init; 364 1.1.2.2 skrll ifp->if_ioctl = rtwn_ioctl; 365 1.1.2.2 skrll ifp->if_start = rtwn_start; 366 1.1.2.2 skrll ifp->if_watchdog = rtwn_watchdog; 367 1.1.2.2 skrll IFQ_SET_READY(&ifp->if_snd); 368 1.1.2.2 skrll memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 369 1.1.2.2 skrll 370 1.1.2.2 skrll if_initialize(ifp); 371 1.1.2.2 skrll ieee80211_ifattach(ic); 372 1.1.2.2 skrll if_register(ifp); 373 1.1.2.2 skrll 374 1.1.2.2 skrll /* override default methods */ 375 1.1.2.2 skrll ic->ic_newassoc = rtwn_newassoc; 376 1.1.2.2 skrll ic->ic_reset = rtwn_reset; 377 1.1.2.2 skrll ic->ic_wme.wme_update = rtwn_wme_update; 378 1.1.2.2 skrll 379 1.1.2.2 skrll /* Override state transition machine. */ 380 1.1.2.2 skrll sc->sc_newstate = ic->ic_newstate; 381 1.1.2.2 skrll ic->ic_newstate = rtwn_newstate; 382 1.1.2.2 skrll ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 383 1.1.2.2 skrll 384 1.1.2.2 skrll bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 385 1.1.2.2 skrll sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 386 1.1.2.2 skrll &sc->sc_drvbpf); 387 1.1.2.2 skrll 388 1.1.2.2 skrll sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 389 1.1.2.2 skrll sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 390 1.1.2.2 skrll sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 391 1.1.2.2 skrll 392 1.1.2.2 skrll sc->sc_txtap_len = sizeof(sc->sc_txtapu); 393 1.1.2.2 skrll sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 394 1.1.2.2 skrll sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 395 1.1.2.2 skrll 396 1.1.2.2 skrll ieee80211_announce(ic); 397 1.1.2.2 skrll 398 1.1.2.2 skrll if (!pmf_device_register(self, NULL, NULL)) 399 1.1.2.2 skrll aprint_error_dev(self, "couldn't establish power handler\n"); 400 1.1.2.2 skrll } 401 1.1.2.2 skrll 402 1.1.2.2 skrll static int 403 1.1.2.2 skrll rtwn_detach(device_t self, int flags) 404 1.1.2.2 skrll { 405 1.1.2.2 skrll struct rtwn_softc *sc = device_private(self); 406 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 407 1.1.2.2 skrll struct ifnet *ifp = GET_IFP(sc); 408 1.1.2.2 skrll int s, i; 409 1.1.2.2 skrll 410 1.1.2.2 skrll callout_stop(&sc->scan_to); 411 1.1.2.2 skrll callout_stop(&sc->calib_to); 412 1.1.2.2 skrll 413 1.1.2.2 skrll s = splnet(); 414 1.1.2.2 skrll 415 1.1.2.2 skrll if (ifp->if_softc != NULL) { 416 1.1.2.2 skrll rtwn_stop(ifp, 0); 417 1.1.2.2 skrll 418 1.1.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 419 1.1.2.2 skrll bpf_detach(ifp); 420 1.1.2.2 skrll ieee80211_ifdetach(ic); 421 1.1.2.2 skrll if_detach(ifp); 422 1.1.2.2 skrll } 423 1.1.2.2 skrll 424 1.1.2.2 skrll /* Free Tx/Rx buffers. */ 425 1.1.2.2 skrll for (i = 0; i < RTWN_NTXQUEUES; i++) 426 1.1.2.2 skrll rtwn_free_tx_list(sc, i); 427 1.1.2.2 skrll rtwn_free_rx_list(sc); 428 1.1.2.2 skrll 429 1.1.2.2 skrll splx(s); 430 1.1.2.2 skrll 431 1.1.2.2 skrll callout_destroy(&sc->scan_to); 432 1.1.2.2 skrll callout_destroy(&sc->calib_to); 433 1.1.2.2 skrll 434 1.1.2.2 skrll if (sc->init_task != NULL) 435 1.1.2.2 skrll softint_disestablish(sc->init_task); 436 1.1.2.2 skrll 437 1.1.2.2 skrll if (sc->sc_ih != NULL) { 438 1.1.2.2 skrll pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 439 1.1.2.2 skrll #ifdef __HAVE_PCI_MSI_MSIX 440 1.1.2.2 skrll pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 441 1.1.2.2 skrll #endif 442 1.1.2.2 skrll } 443 1.1.2.2 skrll 444 1.1.2.2 skrll pmf_device_deregister(self); 445 1.1.2.2 skrll 446 1.1.2.2 skrll return 0; 447 1.1.2.2 skrll } 448 1.1.2.2 skrll 449 1.1.2.2 skrll static int 450 1.1.2.2 skrll rtwn_activate(device_t self, enum devact act) 451 1.1.2.2 skrll { 452 1.1.2.2 skrll struct rtwn_softc *sc = device_private(self); 453 1.1.2.2 skrll struct ifnet *ifp = GET_IFP(sc); 454 1.1.2.2 skrll 455 1.1.2.2 skrll switch (act) { 456 1.1.2.2 skrll case DVACT_DEACTIVATE: 457 1.1.2.2 skrll if (ifp->if_flags & IFF_RUNNING) 458 1.1.2.2 skrll rtwn_stop(ifp, 0); 459 1.1.2.2 skrll return 0; 460 1.1.2.2 skrll default: 461 1.1.2.2 skrll return EOPNOTSUPP; 462 1.1.2.2 skrll } 463 1.1.2.2 skrll } 464 1.1.2.2 skrll 465 1.1.2.2 skrll static void 466 1.1.2.2 skrll rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 467 1.1.2.2 skrll bus_addr_t addr, size_t len, int idx) 468 1.1.2.2 skrll { 469 1.1.2.2 skrll 470 1.1.2.2 skrll memset(desc, 0, sizeof(*desc)); 471 1.1.2.2 skrll desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 472 1.1.2.2 skrll ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 473 1.1.2.2 skrll desc->rxbufaddr = htole32(addr); 474 1.1.2.2 skrll bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 475 1.1.2.2 skrll BUS_SPACE_BARRIER_WRITE); 476 1.1.2.2 skrll desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 477 1.1.2.2 skrll } 478 1.1.2.2 skrll 479 1.1.2.2 skrll static int 480 1.1.2.2 skrll rtwn_alloc_rx_list(struct rtwn_softc *sc) 481 1.1.2.2 skrll { 482 1.1.2.2 skrll struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 483 1.1.2.2 skrll struct rtwn_rx_data *rx_data; 484 1.1.2.2 skrll const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 485 1.1.2.2 skrll int i, error = 0; 486 1.1.2.2 skrll 487 1.1.2.2 skrll /* Allocate Rx descriptors. */ 488 1.1.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 489 1.1.2.2 skrll &rx_ring->map); 490 1.1.2.2 skrll if (error != 0) { 491 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 492 1.1.2.2 skrll "could not create rx desc DMA map\n"); 493 1.1.2.2 skrll rx_ring->map = NULL; 494 1.1.2.2 skrll goto fail; 495 1.1.2.2 skrll } 496 1.1.2.2 skrll 497 1.1.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 498 1.1.2.2 skrll &rx_ring->nsegs, BUS_DMA_NOWAIT); 499 1.1.2.2 skrll if (error != 0) { 500 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 501 1.1.2.2 skrll goto fail; 502 1.1.2.2 skrll } 503 1.1.2.2 skrll 504 1.1.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 505 1.1.2.2 skrll size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 506 1.1.2.2 skrll if (error != 0) { 507 1.1.2.2 skrll bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 508 1.1.2.2 skrll rx_ring->desc = NULL; 509 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 510 1.1.2.2 skrll goto fail; 511 1.1.2.2 skrll } 512 1.1.2.2 skrll memset(rx_ring->desc, 0, size); 513 1.1.2.2 skrll 514 1.1.2.2 skrll error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 515 1.1.2.2 skrll 1, size, BUS_DMA_NOWAIT); 516 1.1.2.2 skrll if (error != 0) { 517 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 518 1.1.2.2 skrll goto fail; 519 1.1.2.2 skrll } 520 1.1.2.2 skrll 521 1.1.2.2 skrll /* Allocate Rx buffers. */ 522 1.1.2.2 skrll for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 523 1.1.2.2 skrll rx_data = &rx_ring->rx_data[i]; 524 1.1.2.2 skrll 525 1.1.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 526 1.1.2.2 skrll 0, BUS_DMA_NOWAIT, &rx_data->map); 527 1.1.2.2 skrll if (error != 0) { 528 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 529 1.1.2.2 skrll "could not create rx buf DMA map\n"); 530 1.1.2.2 skrll goto fail; 531 1.1.2.2 skrll } 532 1.1.2.2 skrll 533 1.1.2.2 skrll MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 534 1.1.2.2 skrll if (__predict_false(rx_data->m == NULL)) { 535 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 536 1.1.2.2 skrll "couldn't allocate rx mbuf\n"); 537 1.1.2.2 skrll error = ENOMEM; 538 1.1.2.2 skrll goto fail; 539 1.1.2.2 skrll } 540 1.1.2.2 skrll MCLGET(rx_data->m, M_DONTWAIT); 541 1.1.2.2 skrll if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 542 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 543 1.1.2.2 skrll "couldn't allocate rx mbuf cluster\n"); 544 1.1.2.2 skrll m_free(rx_data->m); 545 1.1.2.2 skrll rx_data->m = NULL; 546 1.1.2.2 skrll error = ENOMEM; 547 1.1.2.2 skrll goto fail; 548 1.1.2.2 skrll } 549 1.1.2.2 skrll 550 1.1.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 551 1.1.2.2 skrll mtod(rx_data->m, void *), MCLBYTES, NULL, 552 1.1.2.2 skrll BUS_DMA_NOWAIT | BUS_DMA_READ); 553 1.1.2.2 skrll if (error != 0) { 554 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 555 1.1.2.2 skrll "could not load rx buf DMA map\n"); 556 1.1.2.2 skrll goto fail; 557 1.1.2.2 skrll } 558 1.1.2.2 skrll 559 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 560 1.1.2.2 skrll BUS_DMASYNC_PREREAD); 561 1.1.2.2 skrll 562 1.1.2.2 skrll rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 563 1.1.2.2 skrll rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 564 1.1.2.2 skrll } 565 1.1.2.2 skrll fail: if (error != 0) 566 1.1.2.2 skrll rtwn_free_rx_list(sc); 567 1.1.2.2 skrll return error; 568 1.1.2.2 skrll } 569 1.1.2.2 skrll 570 1.1.2.2 skrll static void 571 1.1.2.2 skrll rtwn_reset_rx_list(struct rtwn_softc *sc) 572 1.1.2.2 skrll { 573 1.1.2.2 skrll struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 574 1.1.2.2 skrll struct rtwn_rx_data *rx_data; 575 1.1.2.2 skrll int i; 576 1.1.2.2 skrll 577 1.1.2.2 skrll for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 578 1.1.2.2 skrll rx_data = &rx_ring->rx_data[i]; 579 1.1.2.2 skrll rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 580 1.1.2.2 skrll rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 581 1.1.2.2 skrll } 582 1.1.2.2 skrll } 583 1.1.2.2 skrll 584 1.1.2.2 skrll static void 585 1.1.2.2 skrll rtwn_free_rx_list(struct rtwn_softc *sc) 586 1.1.2.2 skrll { 587 1.1.2.2 skrll struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 588 1.1.2.2 skrll struct rtwn_rx_data *rx_data; 589 1.1.2.2 skrll int i, s; 590 1.1.2.2 skrll 591 1.1.2.2 skrll s = splnet(); 592 1.1.2.2 skrll 593 1.1.2.2 skrll if (rx_ring->map) { 594 1.1.2.2 skrll if (rx_ring->desc) { 595 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 596 1.1.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 597 1.1.2.2 skrll sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 598 1.1.2.2 skrll bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 599 1.1.2.2 skrll rx_ring->nsegs); 600 1.1.2.2 skrll rx_ring->desc = NULL; 601 1.1.2.2 skrll } 602 1.1.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 603 1.1.2.2 skrll rx_ring->map = NULL; 604 1.1.2.2 skrll } 605 1.1.2.2 skrll 606 1.1.2.2 skrll for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 607 1.1.2.2 skrll rx_data = &rx_ring->rx_data[i]; 608 1.1.2.2 skrll 609 1.1.2.2 skrll if (rx_data->m != NULL) { 610 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rx_data->map); 611 1.1.2.2 skrll m_freem(rx_data->m); 612 1.1.2.2 skrll rx_data->m = NULL; 613 1.1.2.2 skrll } 614 1.1.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 615 1.1.2.2 skrll rx_data->map = NULL; 616 1.1.2.2 skrll } 617 1.1.2.2 skrll 618 1.1.2.2 skrll splx(s); 619 1.1.2.2 skrll } 620 1.1.2.2 skrll 621 1.1.2.2 skrll static int 622 1.1.2.2 skrll rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 623 1.1.2.2 skrll { 624 1.1.2.2 skrll struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 625 1.1.2.2 skrll struct rtwn_tx_data *tx_data; 626 1.1.2.2 skrll const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 627 1.1.2.2 skrll int i = 0, error = 0; 628 1.1.2.2 skrll 629 1.1.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 630 1.1.2.2 skrll &tx_ring->map); 631 1.1.2.2 skrll if (error != 0) { 632 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 633 1.1.2.2 skrll "could not create tx ring DMA map\n"); 634 1.1.2.2 skrll goto fail; 635 1.1.2.2 skrll } 636 1.1.2.2 skrll 637 1.1.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 638 1.1.2.2 skrll &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 639 1.1.2.2 skrll if (error != 0) { 640 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 641 1.1.2.2 skrll "could not allocate tx ring DMA memory\n"); 642 1.1.2.2 skrll goto fail; 643 1.1.2.2 skrll } 644 1.1.2.2 skrll 645 1.1.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 646 1.1.2.2 skrll size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 647 1.1.2.2 skrll if (error != 0) { 648 1.1.2.2 skrll bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 649 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 650 1.1.2.2 skrll goto fail; 651 1.1.2.2 skrll } 652 1.1.2.2 skrll memset(tx_ring->desc, 0, size); 653 1.1.2.2 skrll 654 1.1.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 655 1.1.2.2 skrll size, NULL, BUS_DMA_NOWAIT); 656 1.1.2.2 skrll if (error != 0) { 657 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 658 1.1.2.2 skrll "could not load tx ring DMA map\n"); 659 1.1.2.2 skrll goto fail; 660 1.1.2.2 skrll } 661 1.1.2.2 skrll 662 1.1.2.2 skrll for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 663 1.1.2.2 skrll struct r92c_tx_desc *desc = &tx_ring->desc[i]; 664 1.1.2.2 skrll 665 1.1.2.2 skrll /* setup tx desc */ 666 1.1.2.2 skrll desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 667 1.1.2.2 skrll + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 668 1.1.2.2 skrll 669 1.1.2.2 skrll tx_data = &tx_ring->tx_data[i]; 670 1.1.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 671 1.1.2.2 skrll 0, BUS_DMA_NOWAIT, &tx_data->map); 672 1.1.2.2 skrll if (error != 0) { 673 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 674 1.1.2.2 skrll "could not create tx buf DMA map\n"); 675 1.1.2.2 skrll goto fail; 676 1.1.2.2 skrll } 677 1.1.2.2 skrll tx_data->m = NULL; 678 1.1.2.2 skrll tx_data->ni = NULL; 679 1.1.2.2 skrll } 680 1.1.2.2 skrll 681 1.1.2.2 skrll fail: 682 1.1.2.2 skrll if (error != 0) 683 1.1.2.2 skrll rtwn_free_tx_list(sc, qid); 684 1.1.2.2 skrll return error; 685 1.1.2.2 skrll } 686 1.1.2.2 skrll 687 1.1.2.2 skrll static void 688 1.1.2.2 skrll rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 689 1.1.2.2 skrll { 690 1.1.2.2 skrll struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 691 1.1.2.2 skrll int i; 692 1.1.2.2 skrll 693 1.1.2.2 skrll for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 694 1.1.2.2 skrll struct r92c_tx_desc *desc = &tx_ring->desc[i]; 695 1.1.2.2 skrll struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 696 1.1.2.2 skrll 697 1.1.2.2 skrll memset(desc, 0, sizeof(*desc) - 698 1.1.2.2 skrll (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 699 1.1.2.2 skrll sizeof(desc->nextdescaddr))); 700 1.1.2.2 skrll 701 1.1.2.2 skrll if (tx_data->m != NULL) { 702 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, tx_data->map); 703 1.1.2.2 skrll m_freem(tx_data->m); 704 1.1.2.2 skrll tx_data->m = NULL; 705 1.1.2.2 skrll ieee80211_free_node(tx_data->ni); 706 1.1.2.2 skrll tx_data->ni = NULL; 707 1.1.2.2 skrll } 708 1.1.2.2 skrll } 709 1.1.2.2 skrll 710 1.1.2.2 skrll sc->qfullmsk &= ~(1 << qid); 711 1.1.2.2 skrll tx_ring->queued = 0; 712 1.1.2.2 skrll tx_ring->cur = 0; 713 1.1.2.2 skrll } 714 1.1.2.2 skrll 715 1.1.2.2 skrll static void 716 1.1.2.2 skrll rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 717 1.1.2.2 skrll { 718 1.1.2.2 skrll struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 719 1.1.2.2 skrll struct rtwn_tx_data *tx_data; 720 1.1.2.2 skrll int i; 721 1.1.2.2 skrll 722 1.1.2.2 skrll if (tx_ring->map != NULL) { 723 1.1.2.2 skrll if (tx_ring->desc != NULL) { 724 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 725 1.1.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 726 1.1.2.2 skrll sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 727 1.1.2.2 skrll bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 728 1.1.2.2 skrll tx_ring->nsegs); 729 1.1.2.2 skrll } 730 1.1.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 731 1.1.2.2 skrll } 732 1.1.2.2 skrll 733 1.1.2.2 skrll for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 734 1.1.2.2 skrll tx_data = &tx_ring->tx_data[i]; 735 1.1.2.2 skrll 736 1.1.2.2 skrll if (tx_data->m != NULL) { 737 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, tx_data->map); 738 1.1.2.2 skrll m_freem(tx_data->m); 739 1.1.2.2 skrll tx_data->m = NULL; 740 1.1.2.2 skrll } 741 1.1.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 742 1.1.2.2 skrll } 743 1.1.2.2 skrll 744 1.1.2.2 skrll sc->qfullmsk &= ~(1 << qid); 745 1.1.2.2 skrll tx_ring->queued = 0; 746 1.1.2.2 skrll tx_ring->cur = 0; 747 1.1.2.2 skrll } 748 1.1.2.2 skrll 749 1.1.2.2 skrll static void 750 1.1.2.2 skrll rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 751 1.1.2.2 skrll { 752 1.1.2.2 skrll bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 753 1.1.2.2 skrll } 754 1.1.2.2 skrll 755 1.1.2.2 skrll static void 756 1.1.2.2 skrll rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 757 1.1.2.2 skrll { 758 1.1.2.2 skrll bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 759 1.1.2.2 skrll } 760 1.1.2.2 skrll 761 1.1.2.2 skrll static void 762 1.1.2.2 skrll rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 763 1.1.2.2 skrll { 764 1.1.2.2 skrll bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 765 1.1.2.2 skrll } 766 1.1.2.2 skrll 767 1.1.2.2 skrll static uint8_t 768 1.1.2.2 skrll rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 769 1.1.2.2 skrll { 770 1.1.2.2 skrll return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 771 1.1.2.2 skrll } 772 1.1.2.2 skrll 773 1.1.2.2 skrll static uint16_t 774 1.1.2.2 skrll rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 775 1.1.2.2 skrll { 776 1.1.2.2 skrll return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 777 1.1.2.2 skrll } 778 1.1.2.2 skrll 779 1.1.2.2 skrll static uint32_t 780 1.1.2.2 skrll rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 781 1.1.2.2 skrll { 782 1.1.2.2 skrll return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 783 1.1.2.2 skrll } 784 1.1.2.2 skrll 785 1.1.2.2 skrll static int 786 1.1.2.2 skrll rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 787 1.1.2.2 skrll { 788 1.1.2.2 skrll struct r92c_fw_cmd cmd; 789 1.1.2.2 skrll uint8_t *cp; 790 1.1.2.2 skrll int fwcur; 791 1.1.2.2 skrll int ntries; 792 1.1.2.2 skrll 793 1.1.2.2 skrll DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 794 1.1.2.2 skrll device_xname(sc->sc_dev), __func__, id, buf, len)); 795 1.1.2.2 skrll 796 1.1.2.2 skrll fwcur = sc->fwcur; 797 1.1.2.2 skrll sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 798 1.1.2.2 skrll 799 1.1.2.2 skrll /* Wait for current FW box to be empty. */ 800 1.1.2.2 skrll for (ntries = 0; ntries < 100; ntries++) { 801 1.1.2.2 skrll if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 802 1.1.2.2 skrll break; 803 1.1.2.2 skrll DELAY(1); 804 1.1.2.2 skrll } 805 1.1.2.2 skrll if (ntries == 100) { 806 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 807 1.1.2.2 skrll "could not send firmware command %d\n", id); 808 1.1.2.2 skrll return ETIMEDOUT; 809 1.1.2.2 skrll } 810 1.1.2.2 skrll 811 1.1.2.2 skrll memset(&cmd, 0, sizeof(cmd)); 812 1.1.2.2 skrll KASSERT(len <= sizeof(cmd.msg)); 813 1.1.2.2 skrll memcpy(cmd.msg, buf, len); 814 1.1.2.2 skrll 815 1.1.2.2 skrll /* Write the first word last since that will trigger the FW. */ 816 1.1.2.2 skrll cp = (uint8_t *)&cmd; 817 1.1.2.2 skrll if (len >= 4) { 818 1.1.2.2 skrll cmd.id = id | R92C_CMD_FLAG_EXT; 819 1.1.2.2 skrll rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 820 1.1.2.2 skrll rtwn_write_4(sc, R92C_HMEBOX(fwcur), 821 1.1.2.2 skrll cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 822 1.1.2.2 skrll } else { 823 1.1.2.2 skrll cmd.id = id; 824 1.1.2.2 skrll rtwn_write_4(sc, R92C_HMEBOX(fwcur), 825 1.1.2.2 skrll cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 826 1.1.2.2 skrll } 827 1.1.2.2 skrll 828 1.1.2.2 skrll /* Give firmware some time for processing. */ 829 1.1.2.2 skrll DELAY(2000); 830 1.1.2.2 skrll 831 1.1.2.2 skrll return 0; 832 1.1.2.2 skrll } 833 1.1.2.2 skrll 834 1.1.2.2 skrll static void 835 1.1.2.2 skrll rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 836 1.1.2.2 skrll { 837 1.1.2.2 skrll 838 1.1.2.2 skrll rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 839 1.1.2.2 skrll SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 840 1.1.2.2 skrll } 841 1.1.2.2 skrll 842 1.1.2.2 skrll static uint32_t 843 1.1.2.2 skrll rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 844 1.1.2.2 skrll { 845 1.1.2.2 skrll uint32_t reg[R92C_MAX_CHAINS], val; 846 1.1.2.2 skrll 847 1.1.2.2 skrll reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 848 1.1.2.2 skrll if (chain != 0) 849 1.1.2.2 skrll reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 850 1.1.2.2 skrll 851 1.1.2.2 skrll rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 852 1.1.2.2 skrll reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 853 1.1.2.2 skrll DELAY(1000); 854 1.1.2.2 skrll 855 1.1.2.2 skrll rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 856 1.1.2.2 skrll RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 857 1.1.2.2 skrll R92C_HSSI_PARAM2_READ_EDGE); 858 1.1.2.2 skrll DELAY(1000); 859 1.1.2.2 skrll 860 1.1.2.2 skrll rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 861 1.1.2.2 skrll reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 862 1.1.2.2 skrll DELAY(1000); 863 1.1.2.2 skrll 864 1.1.2.2 skrll if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 865 1.1.2.2 skrll val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 866 1.1.2.2 skrll else 867 1.1.2.2 skrll val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 868 1.1.2.2 skrll return MS(val, R92C_LSSI_READBACK_DATA); 869 1.1.2.2 skrll } 870 1.1.2.2 skrll 871 1.1.2.2 skrll static int 872 1.1.2.2 skrll rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 873 1.1.2.2 skrll { 874 1.1.2.2 skrll int ntries; 875 1.1.2.2 skrll 876 1.1.2.2 skrll rtwn_write_4(sc, R92C_LLT_INIT, 877 1.1.2.2 skrll SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 878 1.1.2.2 skrll SM(R92C_LLT_INIT_ADDR, addr) | 879 1.1.2.2 skrll SM(R92C_LLT_INIT_DATA, data)); 880 1.1.2.2 skrll /* Wait for write operation to complete. */ 881 1.1.2.2 skrll for (ntries = 0; ntries < 20; ntries++) { 882 1.1.2.2 skrll if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 883 1.1.2.2 skrll R92C_LLT_INIT_OP_NO_ACTIVE) 884 1.1.2.2 skrll return 0; 885 1.1.2.2 skrll DELAY(5); 886 1.1.2.2 skrll } 887 1.1.2.2 skrll return ETIMEDOUT; 888 1.1.2.2 skrll } 889 1.1.2.2 skrll 890 1.1.2.2 skrll static uint8_t 891 1.1.2.2 skrll rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 892 1.1.2.2 skrll { 893 1.1.2.2 skrll uint32_t reg; 894 1.1.2.2 skrll int ntries; 895 1.1.2.2 skrll 896 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 897 1.1.2.2 skrll reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 898 1.1.2.2 skrll reg &= ~R92C_EFUSE_CTRL_VALID; 899 1.1.2.2 skrll rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 900 1.1.2.2 skrll /* Wait for read operation to complete. */ 901 1.1.2.2 skrll for (ntries = 0; ntries < 100; ntries++) { 902 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 903 1.1.2.2 skrll if (reg & R92C_EFUSE_CTRL_VALID) 904 1.1.2.2 skrll return MS(reg, R92C_EFUSE_CTRL_DATA); 905 1.1.2.2 skrll DELAY(5); 906 1.1.2.2 skrll } 907 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 908 1.1.2.2 skrll "could not read efuse byte at address 0x%x\n", addr); 909 1.1.2.2 skrll return 0xff; 910 1.1.2.2 skrll } 911 1.1.2.2 skrll 912 1.1.2.2 skrll static void 913 1.1.2.2 skrll rtwn_efuse_read(struct rtwn_softc *sc) 914 1.1.2.2 skrll { 915 1.1.2.2 skrll uint8_t *rom = (uint8_t *)&sc->rom; 916 1.1.2.2 skrll uint32_t reg; 917 1.1.2.2 skrll uint16_t addr = 0; 918 1.1.2.2 skrll uint8_t off, msk; 919 1.1.2.2 skrll int i; 920 1.1.2.2 skrll 921 1.1.2.2 skrll rtwn_efuse_switch_power(sc); 922 1.1.2.2 skrll 923 1.1.2.2 skrll memset(&sc->rom, 0xff, sizeof(sc->rom)); 924 1.1.2.2 skrll while (addr < 512) { 925 1.1.2.2 skrll reg = rtwn_efuse_read_1(sc, addr); 926 1.1.2.2 skrll if (reg == 0xff) 927 1.1.2.2 skrll break; 928 1.1.2.2 skrll addr++; 929 1.1.2.2 skrll off = reg >> 4; 930 1.1.2.2 skrll msk = reg & 0xf; 931 1.1.2.2 skrll for (i = 0; i < 4; i++) { 932 1.1.2.2 skrll if (msk & (1 << i)) 933 1.1.2.2 skrll continue; 934 1.1.2.2 skrll rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 935 1.1.2.2 skrll addr++; 936 1.1.2.2 skrll rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 937 1.1.2.2 skrll addr++; 938 1.1.2.2 skrll } 939 1.1.2.2 skrll } 940 1.1.2.2 skrll #ifdef RTWN_DEBUG 941 1.1.2.2 skrll if (rtwn_debug >= 2) { 942 1.1.2.2 skrll /* Dump ROM content. */ 943 1.1.2.2 skrll printf("\n"); 944 1.1.2.2 skrll for (i = 0; i < sizeof(sc->rom); i++) 945 1.1.2.2 skrll printf("%02x:", rom[i]); 946 1.1.2.2 skrll printf("\n"); 947 1.1.2.2 skrll } 948 1.1.2.2 skrll #endif 949 1.1.2.2 skrll } 950 1.1.2.2 skrll 951 1.1.2.2 skrll static void 952 1.1.2.2 skrll rtwn_efuse_switch_power(struct rtwn_softc *sc) 953 1.1.2.2 skrll { 954 1.1.2.2 skrll uint32_t reg; 955 1.1.2.2 skrll 956 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 957 1.1.2.2 skrll if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 958 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 959 1.1.2.2 skrll reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 960 1.1.2.2 skrll } 961 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 962 1.1.2.2 skrll if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 963 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_FUNC_EN, 964 1.1.2.2 skrll reg | R92C_SYS_FUNC_EN_ELDR); 965 1.1.2.2 skrll } 966 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_SYS_CLKR); 967 1.1.2.2 skrll if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 968 1.1.2.2 skrll (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 969 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_CLKR, 970 1.1.2.2 skrll reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 971 1.1.2.2 skrll } 972 1.1.2.2 skrll } 973 1.1.2.2 skrll 974 1.1.2.2 skrll /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 975 1.1.2.2 skrll static int 976 1.1.2.2 skrll rtwn_read_chipid(struct rtwn_softc *sc) 977 1.1.2.2 skrll { 978 1.1.2.2 skrll uint32_t reg; 979 1.1.2.2 skrll 980 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 981 1.1.2.2 skrll 982 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_SYS_CFG); 983 1.1.2.2 skrll DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 984 1.1.2.2 skrll if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 985 1.1.2.2 skrll /* Unsupported test chip. */ 986 1.1.2.2 skrll return EIO; 987 1.1.2.2 skrll 988 1.1.2.2 skrll if (reg & R92C_SYS_CFG_TYPE_92C) { 989 1.1.2.2 skrll sc->chip |= RTWN_CHIP_92C; 990 1.1.2.2 skrll /* Check if it is a castrated 8192C. */ 991 1.1.2.2 skrll if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 992 1.1.2.2 skrll R92C_HPON_FSM_CHIP_BONDING_ID) == 993 1.1.2.2 skrll R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 994 1.1.2.2 skrll sc->chip |= RTWN_CHIP_92C_1T2R; 995 1.1.2.2 skrll } 996 1.1.2.2 skrll if (reg & R92C_SYS_CFG_VENDOR_UMC) { 997 1.1.2.2 skrll sc->chip |= RTWN_CHIP_UMC; 998 1.1.2.2 skrll if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 999 1.1.2.2 skrll sc->chip |= RTWN_CHIP_UMC_A_CUT; 1000 1.1.2.2 skrll } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 1001 1.1.2.2 skrll if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 1002 1.1.2.2 skrll sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 1003 1.1.2.2 skrll else 1004 1.1.2.2 skrll /* Unsupported unknown chip. */ 1005 1.1.2.2 skrll return EIO; 1006 1.1.2.2 skrll } 1007 1.1.2.2 skrll return 0; 1008 1.1.2.2 skrll } 1009 1.1.2.2 skrll 1010 1.1.2.2 skrll static void 1011 1.1.2.2 skrll rtwn_read_rom(struct rtwn_softc *sc) 1012 1.1.2.2 skrll { 1013 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1014 1.1.2.2 skrll struct r92c_rom *rom = &sc->rom; 1015 1.1.2.2 skrll 1016 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1017 1.1.2.2 skrll 1018 1.1.2.2 skrll /* Read full ROM image. */ 1019 1.1.2.2 skrll rtwn_efuse_read(sc); 1020 1.1.2.2 skrll 1021 1.1.2.2 skrll if (rom->id != 0x8129) { 1022 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1023 1.1.2.2 skrll rom->id); 1024 1.1.2.2 skrll } 1025 1.1.2.2 skrll 1026 1.1.2.2 skrll /* XXX Weird but this is what the vendor driver does. */ 1027 1.1.2.2 skrll sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1028 1.1.2.2 skrll sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1029 1.1.2.2 skrll sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1030 1.1.2.2 skrll 1031 1.1.2.2 skrll DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1032 1.1.2.2 skrll sc->pa_setting, sc->board_type, sc->regulatory)); 1033 1.1.2.2 skrll 1034 1.1.2.2 skrll IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1035 1.1.2.2 skrll } 1036 1.1.2.2 skrll 1037 1.1.2.2 skrll static int 1038 1.1.2.2 skrll rtwn_media_change(struct ifnet *ifp) 1039 1.1.2.2 skrll { 1040 1.1.2.2 skrll int error; 1041 1.1.2.2 skrll 1042 1.1.2.2 skrll error = ieee80211_media_change(ifp); 1043 1.1.2.2 skrll if (error != ENETRESET) 1044 1.1.2.2 skrll return error; 1045 1.1.2.2 skrll 1046 1.1.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1047 1.1.2.2 skrll (IFF_UP | IFF_RUNNING)) { 1048 1.1.2.2 skrll rtwn_stop(ifp, 0); 1049 1.1.2.2 skrll error = rtwn_init(ifp); 1050 1.1.2.2 skrll } 1051 1.1.2.2 skrll return error; 1052 1.1.2.2 skrll } 1053 1.1.2.2 skrll 1054 1.1.2.2 skrll /* 1055 1.1.2.2 skrll * Initialize rate adaptation in firmware. 1056 1.1.2.2 skrll */ 1057 1.1.2.2 skrll static int 1058 1.1.2.2 skrll rtwn_ra_init(struct rtwn_softc *sc) 1059 1.1.2.2 skrll { 1060 1.1.2.2 skrll static const uint8_t map[] = { 1061 1.1.2.2 skrll 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1062 1.1.2.2 skrll }; 1063 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1064 1.1.2.2 skrll struct ieee80211_node *ni = ic->ic_bss; 1065 1.1.2.2 skrll struct ieee80211_rateset *rs = &ni->ni_rates; 1066 1.1.2.2 skrll struct r92c_fw_cmd_macid_cfg cmd; 1067 1.1.2.2 skrll uint32_t rates, basicrates; 1068 1.1.2.2 skrll uint8_t mode; 1069 1.1.2.2 skrll int maxrate, maxbasicrate, error, i, j; 1070 1.1.2.2 skrll 1071 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1072 1.1.2.2 skrll 1073 1.1.2.2 skrll /* Get normal and basic rates mask. */ 1074 1.1.2.2 skrll rates = basicrates = 0; 1075 1.1.2.2 skrll maxrate = maxbasicrate = 0; 1076 1.1.2.2 skrll for (i = 0; i < rs->rs_nrates; i++) { 1077 1.1.2.2 skrll /* Convert 802.11 rate to HW rate index. */ 1078 1.1.2.2 skrll for (j = 0; j < __arraycount(map); j++) 1079 1.1.2.2 skrll if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1080 1.1.2.2 skrll break; 1081 1.1.2.2 skrll if (j == __arraycount(map)) /* Unknown rate, skip. */ 1082 1.1.2.2 skrll continue; 1083 1.1.2.2 skrll rates |= 1 << j; 1084 1.1.2.2 skrll if (j > maxrate) 1085 1.1.2.2 skrll maxrate = j; 1086 1.1.2.2 skrll if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1087 1.1.2.2 skrll basicrates |= 1 << j; 1088 1.1.2.2 skrll if (j > maxbasicrate) 1089 1.1.2.2 skrll maxbasicrate = j; 1090 1.1.2.2 skrll } 1091 1.1.2.2 skrll } 1092 1.1.2.2 skrll if (ic->ic_curmode == IEEE80211_MODE_11B) 1093 1.1.2.2 skrll mode = R92C_RAID_11B; 1094 1.1.2.2 skrll else 1095 1.1.2.2 skrll mode = R92C_RAID_11BG; 1096 1.1.2.2 skrll DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1097 1.1.2.2 skrll device_xname(sc->sc_dev), mode, rates, basicrates)); 1098 1.1.2.2 skrll if (basicrates == 0) 1099 1.1.2.2 skrll basicrates |= 1; /* add 1Mbps */ 1100 1.1.2.2 skrll 1101 1.1.2.2 skrll /* Set rates mask for group addressed frames. */ 1102 1.1.2.2 skrll cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1103 1.1.2.2 skrll cmd.mask = htole32((mode << 28) | basicrates); 1104 1.1.2.2 skrll error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1105 1.1.2.2 skrll if (error != 0) { 1106 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 1107 1.1.2.2 skrll "could not add broadcast station\n"); 1108 1.1.2.2 skrll return error; 1109 1.1.2.2 skrll } 1110 1.1.2.2 skrll /* Set initial MRR rate. */ 1111 1.1.2.2 skrll DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1112 1.1.2.2 skrll maxbasicrate)); 1113 1.1.2.2 skrll rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1114 1.1.2.2 skrll 1115 1.1.2.2 skrll /* Set rates mask for unicast frames. */ 1116 1.1.2.2 skrll cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1117 1.1.2.2 skrll cmd.mask = htole32((mode << 28) | rates); 1118 1.1.2.2 skrll error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1119 1.1.2.2 skrll if (error != 0) { 1120 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1121 1.1.2.2 skrll return error; 1122 1.1.2.2 skrll } 1123 1.1.2.2 skrll /* Set initial MRR rate. */ 1124 1.1.2.2 skrll DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1125 1.1.2.2 skrll rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1126 1.1.2.2 skrll 1127 1.1.2.2 skrll /* Configure Automatic Rate Fallback Register. */ 1128 1.1.2.2 skrll if (ic->ic_curmode == IEEE80211_MODE_11B) { 1129 1.1.2.2 skrll if (rates & 0x0c) 1130 1.1.2.2 skrll rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1131 1.1.2.2 skrll else 1132 1.1.2.2 skrll rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1133 1.1.2.2 skrll } else 1134 1.1.2.2 skrll rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1135 1.1.2.2 skrll 1136 1.1.2.2 skrll /* Indicate highest supported rate. */ 1137 1.1.2.2 skrll ni->ni_txrate = rs->rs_nrates - 1; 1138 1.1.2.2 skrll return 0; 1139 1.1.2.2 skrll } 1140 1.1.2.2 skrll 1141 1.1.2.2 skrll static int 1142 1.1.2.2 skrll rtwn_get_nettype(struct rtwn_softc *sc) 1143 1.1.2.2 skrll { 1144 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1145 1.1.2.2 skrll int type; 1146 1.1.2.2 skrll 1147 1.1.2.2 skrll switch (ic->ic_opmode) { 1148 1.1.2.2 skrll case IEEE80211_M_STA: 1149 1.1.2.2 skrll type = R92C_CR_NETTYPE_INFRA; 1150 1.1.2.2 skrll break; 1151 1.1.2.2 skrll 1152 1.1.2.2 skrll case IEEE80211_M_HOSTAP: 1153 1.1.2.2 skrll type = R92C_CR_NETTYPE_AP; 1154 1.1.2.2 skrll break; 1155 1.1.2.2 skrll 1156 1.1.2.2 skrll case IEEE80211_M_IBSS: 1157 1.1.2.2 skrll type = R92C_CR_NETTYPE_ADHOC; 1158 1.1.2.2 skrll break; 1159 1.1.2.2 skrll 1160 1.1.2.2 skrll default: 1161 1.1.2.2 skrll type = R92C_CR_NETTYPE_NOLINK; 1162 1.1.2.2 skrll break; 1163 1.1.2.2 skrll } 1164 1.1.2.2 skrll 1165 1.1.2.2 skrll return type; 1166 1.1.2.2 skrll } 1167 1.1.2.2 skrll 1168 1.1.2.2 skrll static void 1169 1.1.2.2 skrll rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1170 1.1.2.2 skrll { 1171 1.1.2.2 skrll uint32_t reg; 1172 1.1.2.2 skrll 1173 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_CR); 1174 1.1.2.2 skrll reg = RW(reg, R92C_CR_NETTYPE, type); 1175 1.1.2.2 skrll rtwn_write_4(sc, R92C_CR, reg); 1176 1.1.2.2 skrll } 1177 1.1.2.2 skrll 1178 1.1.2.2 skrll static void 1179 1.1.2.2 skrll rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1180 1.1.2.2 skrll { 1181 1.1.2.2 skrll struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1182 1.1.2.2 skrll uint64_t tsf; 1183 1.1.2.2 skrll 1184 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1185 1.1.2.2 skrll 1186 1.1.2.2 skrll /* Enable TSF synchronization. */ 1187 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, 1188 1.1.2.2 skrll rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1189 1.1.2.2 skrll 1190 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, 1191 1.1.2.2 skrll rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1192 1.1.2.2 skrll 1193 1.1.2.2 skrll /* Set initial TSF. */ 1194 1.1.2.2 skrll tsf = ni->ni_tstamp.tsf; 1195 1.1.2.2 skrll tsf = le64toh(tsf); 1196 1.1.2.2 skrll tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1197 1.1.2.2 skrll tsf -= IEEE80211_DUR_TU; 1198 1.1.2.2 skrll rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1199 1.1.2.2 skrll rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1200 1.1.2.2 skrll 1201 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, 1202 1.1.2.2 skrll rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1203 1.1.2.2 skrll } 1204 1.1.2.2 skrll 1205 1.1.2.2 skrll static void 1206 1.1.2.2 skrll rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1207 1.1.2.2 skrll { 1208 1.1.2.2 skrll uint8_t reg; 1209 1.1.2.2 skrll 1210 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1211 1.1.2.2 skrll 1212 1.1.2.2 skrll if (led == RTWN_LED_LINK) { 1213 1.1.2.2 skrll reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1214 1.1.2.2 skrll if (!on) 1215 1.1.2.2 skrll reg |= R92C_LEDCFG2_DIS; 1216 1.1.2.2 skrll else 1217 1.1.2.2 skrll reg |= R92C_LEDCFG2_EN; 1218 1.1.2.2 skrll rtwn_write_1(sc, R92C_LEDCFG2, reg); 1219 1.1.2.2 skrll sc->ledlink = on; /* Save LED state. */ 1220 1.1.2.2 skrll } 1221 1.1.2.2 skrll } 1222 1.1.2.2 skrll 1223 1.1.2.2 skrll static void 1224 1.1.2.2 skrll rtwn_calib_to(void *arg) 1225 1.1.2.2 skrll { 1226 1.1.2.2 skrll struct rtwn_softc *sc = arg; 1227 1.1.2.2 skrll struct r92c_fw_cmd_rssi cmd; 1228 1.1.2.2 skrll 1229 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1230 1.1.2.2 skrll 1231 1.1.2.2 skrll if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1232 1.1.2.2 skrll goto restart_timer; 1233 1.1.2.2 skrll 1234 1.1.2.2 skrll if (sc->avg_pwdb != -1) { 1235 1.1.2.2 skrll /* Indicate Rx signal strength to FW for rate adaptation. */ 1236 1.1.2.2 skrll memset(&cmd, 0, sizeof(cmd)); 1237 1.1.2.2 skrll cmd.macid = 0; /* BSS. */ 1238 1.1.2.2 skrll cmd.pwdb = sc->avg_pwdb; 1239 1.1.2.2 skrll DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1240 1.1.2.2 skrll rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1241 1.1.2.2 skrll } 1242 1.1.2.2 skrll 1243 1.1.2.2 skrll /* Do temperature compensation. */ 1244 1.1.2.2 skrll rtwn_temp_calib(sc); 1245 1.1.2.2 skrll 1246 1.1.2.2 skrll restart_timer: 1247 1.1.2.2 skrll callout_schedule(&sc->calib_to, mstohz(2000)); 1248 1.1.2.2 skrll } 1249 1.1.2.2 skrll 1250 1.1.2.2 skrll static void 1251 1.1.2.2 skrll rtwn_next_scan(void *arg) 1252 1.1.2.2 skrll { 1253 1.1.2.2 skrll struct rtwn_softc *sc = arg; 1254 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1255 1.1.2.2 skrll int s; 1256 1.1.2.2 skrll 1257 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1258 1.1.2.2 skrll 1259 1.1.2.2 skrll s = splnet(); 1260 1.1.2.2 skrll if (ic->ic_state == IEEE80211_S_SCAN) 1261 1.1.2.2 skrll ieee80211_next_scan(ic); 1262 1.1.2.2 skrll splx(s); 1263 1.1.2.2 skrll } 1264 1.1.2.2 skrll 1265 1.1.2.2 skrll static void 1266 1.1.2.2 skrll rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1267 1.1.2.2 skrll { 1268 1.1.2.2 skrll 1269 1.1.2.2 skrll DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1270 1.1.2.2 skrll 1271 1.1.2.2 skrll /* start with lowest Tx rate */ 1272 1.1.2.2 skrll ni->ni_txrate = 0; 1273 1.1.2.2 skrll } 1274 1.1.2.2 skrll 1275 1.1.2.2 skrll static int 1276 1.1.2.2 skrll rtwn_reset(struct ifnet *ifp) 1277 1.1.2.2 skrll { 1278 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 1279 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1280 1.1.2.2 skrll 1281 1.1.2.2 skrll if (ic->ic_opmode != IEEE80211_M_MONITOR) 1282 1.1.2.2 skrll return ENETRESET; 1283 1.1.2.2 skrll 1284 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1285 1.1.2.2 skrll 1286 1.1.2.2 skrll return 0; 1287 1.1.2.2 skrll } 1288 1.1.2.2 skrll 1289 1.1.2.2 skrll static int 1290 1.1.2.2 skrll rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1291 1.1.2.2 skrll { 1292 1.1.2.2 skrll struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1293 1.1.2.2 skrll struct ieee80211_node *ni; 1294 1.1.2.2 skrll enum ieee80211_state ostate = ic->ic_state; 1295 1.1.2.2 skrll uint32_t reg; 1296 1.1.2.2 skrll int s; 1297 1.1.2.2 skrll 1298 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1299 1.1.2.2 skrll 1300 1.1.2.2 skrll s = splnet(); 1301 1.1.2.2 skrll 1302 1.1.2.2 skrll callout_stop(&sc->scan_to); 1303 1.1.2.2 skrll callout_stop(&sc->calib_to); 1304 1.1.2.2 skrll 1305 1.1.2.2 skrll if (ostate != nstate) { 1306 1.1.2.2 skrll DPRINTF(("%s: %s -> %s\n", __func__, 1307 1.1.2.2 skrll ieee80211_state_name[ostate], 1308 1.1.2.2 skrll ieee80211_state_name[nstate])); 1309 1.1.2.2 skrll } 1310 1.1.2.2 skrll 1311 1.1.2.2 skrll switch (ostate) { 1312 1.1.2.2 skrll case IEEE80211_S_INIT: 1313 1.1.2.2 skrll break; 1314 1.1.2.2 skrll 1315 1.1.2.2 skrll case IEEE80211_S_SCAN: 1316 1.1.2.2 skrll if (nstate != IEEE80211_S_SCAN) { 1317 1.1.2.2 skrll /* 1318 1.1.2.2 skrll * End of scanning 1319 1.1.2.2 skrll */ 1320 1.1.2.2 skrll /* flush 4-AC Queue after site_survey */ 1321 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1322 1.1.2.2 skrll 1323 1.1.2.2 skrll /* Allow Rx from our BSSID only. */ 1324 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1325 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) | 1326 1.1.2.2 skrll R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1327 1.1.2.2 skrll } 1328 1.1.2.2 skrll break; 1329 1.1.2.2 skrll 1330 1.1.2.2 skrll case IEEE80211_S_AUTH: 1331 1.1.2.2 skrll case IEEE80211_S_ASSOC: 1332 1.1.2.2 skrll break; 1333 1.1.2.2 skrll 1334 1.1.2.2 skrll case IEEE80211_S_RUN: 1335 1.1.2.2 skrll /* Turn link LED off. */ 1336 1.1.2.2 skrll rtwn_set_led(sc, RTWN_LED_LINK, 0); 1337 1.1.2.2 skrll 1338 1.1.2.2 skrll /* Set media status to 'No Link'. */ 1339 1.1.2.2 skrll rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1340 1.1.2.2 skrll 1341 1.1.2.2 skrll /* Stop Rx of data frames. */ 1342 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1343 1.1.2.2 skrll 1344 1.1.2.2 skrll /* Rest TSF. */ 1345 1.1.2.2 skrll rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1346 1.1.2.2 skrll 1347 1.1.2.2 skrll /* Disable TSF synchronization. */ 1348 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, 1349 1.1.2.2 skrll rtwn_read_1(sc, R92C_BCN_CTRL) | 1350 1.1.2.2 skrll R92C_BCN_CTRL_DIS_TSF_UDT0); 1351 1.1.2.2 skrll 1352 1.1.2.2 skrll /* Back to 20MHz mode */ 1353 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1354 1.1.2.2 skrll 1355 1.1.2.2 skrll /* Reset EDCA parameters. */ 1356 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1357 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1358 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1359 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1360 1.1.2.2 skrll 1361 1.1.2.2 skrll /* flush all cam entries */ 1362 1.1.2.2 skrll rtwn_cam_init(sc); 1363 1.1.2.2 skrll break; 1364 1.1.2.2 skrll } 1365 1.1.2.2 skrll 1366 1.1.2.2 skrll switch (nstate) { 1367 1.1.2.2 skrll case IEEE80211_S_INIT: 1368 1.1.2.2 skrll /* Turn link LED off. */ 1369 1.1.2.2 skrll rtwn_set_led(sc, RTWN_LED_LINK, 0); 1370 1.1.2.2 skrll break; 1371 1.1.2.2 skrll 1372 1.1.2.2 skrll case IEEE80211_S_SCAN: 1373 1.1.2.2 skrll if (ostate != IEEE80211_S_SCAN) { 1374 1.1.2.2 skrll /* 1375 1.1.2.2 skrll * Begin of scanning 1376 1.1.2.2 skrll */ 1377 1.1.2.2 skrll 1378 1.1.2.2 skrll /* Set gain for scanning. */ 1379 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1380 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1381 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1382 1.1.2.2 skrll 1383 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1384 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1385 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1386 1.1.2.2 skrll 1387 1.1.2.2 skrll /* Allow Rx from any BSSID. */ 1388 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1389 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) & 1390 1.1.2.2 skrll ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1391 1.1.2.2 skrll 1392 1.1.2.2 skrll /* Stop Rx of data frames. */ 1393 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1394 1.1.2.2 skrll 1395 1.1.2.2 skrll /* Disable update TSF */ 1396 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, 1397 1.1.2.2 skrll rtwn_read_1(sc, R92C_BCN_CTRL) | 1398 1.1.2.2 skrll R92C_BCN_CTRL_DIS_TSF_UDT0); 1399 1.1.2.2 skrll } 1400 1.1.2.2 skrll 1401 1.1.2.2 skrll /* Make link LED blink during scan. */ 1402 1.1.2.2 skrll rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1403 1.1.2.2 skrll 1404 1.1.2.2 skrll /* Pause AC Tx queues. */ 1405 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 1406 1.1.2.2 skrll rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1407 1.1.2.2 skrll 1408 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1409 1.1.2.2 skrll 1410 1.1.2.2 skrll /* Start periodic scan. */ 1411 1.1.2.2 skrll callout_schedule(&sc->scan_to, mstohz(200)); 1412 1.1.2.2 skrll break; 1413 1.1.2.2 skrll 1414 1.1.2.2 skrll case IEEE80211_S_AUTH: 1415 1.1.2.2 skrll /* Set initial gain under link. */ 1416 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1417 1.1.2.2 skrll #ifdef doaslinux 1418 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1419 1.1.2.2 skrll #else 1420 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1421 1.1.2.2 skrll #endif 1422 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1423 1.1.2.2 skrll 1424 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1425 1.1.2.2 skrll #ifdef doaslinux 1426 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1427 1.1.2.2 skrll #else 1428 1.1.2.2 skrll reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1429 1.1.2.2 skrll #endif 1430 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1431 1.1.2.2 skrll 1432 1.1.2.2 skrll /* Set media status to 'No Link'. */ 1433 1.1.2.2 skrll rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1434 1.1.2.2 skrll 1435 1.1.2.2 skrll /* Allow Rx from any BSSID. */ 1436 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1437 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) & 1438 1.1.2.2 skrll ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1439 1.1.2.2 skrll 1440 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1441 1.1.2.2 skrll break; 1442 1.1.2.2 skrll 1443 1.1.2.2 skrll case IEEE80211_S_ASSOC: 1444 1.1.2.2 skrll break; 1445 1.1.2.2 skrll 1446 1.1.2.2 skrll case IEEE80211_S_RUN: 1447 1.1.2.2 skrll ni = ic->ic_bss; 1448 1.1.2.2 skrll 1449 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1450 1.1.2.2 skrll 1451 1.1.2.2 skrll if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1452 1.1.2.2 skrll /* Back to 20Mhz mode */ 1453 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 1454 1.1.2.2 skrll 1455 1.1.2.2 skrll /* Set media status to 'No Link'. */ 1456 1.1.2.2 skrll rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1457 1.1.2.2 skrll 1458 1.1.2.2 skrll /* Enable Rx of data frames. */ 1459 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1460 1.1.2.2 skrll 1461 1.1.2.2 skrll /* Allow Rx from any BSSID. */ 1462 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1463 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) & 1464 1.1.2.2 skrll ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1465 1.1.2.2 skrll 1466 1.1.2.2 skrll /* Accept Rx data/control/management frames */ 1467 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1468 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) | 1469 1.1.2.2 skrll R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1470 1.1.2.2 skrll 1471 1.1.2.2 skrll /* Turn link LED on. */ 1472 1.1.2.2 skrll rtwn_set_led(sc, RTWN_LED_LINK, 1); 1473 1.1.2.2 skrll break; 1474 1.1.2.2 skrll } 1475 1.1.2.2 skrll 1476 1.1.2.2 skrll /* Set media status to 'Associated'. */ 1477 1.1.2.2 skrll rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1478 1.1.2.2 skrll 1479 1.1.2.2 skrll /* Set BSSID. */ 1480 1.1.2.2 skrll rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1481 1.1.2.2 skrll rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1482 1.1.2.2 skrll 1483 1.1.2.2 skrll if (ic->ic_curmode == IEEE80211_MODE_11B) 1484 1.1.2.2 skrll rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1485 1.1.2.2 skrll else /* 802.11b/g */ 1486 1.1.2.2 skrll rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1487 1.1.2.2 skrll 1488 1.1.2.2 skrll /* Enable Rx of data frames. */ 1489 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1490 1.1.2.2 skrll 1491 1.1.2.2 skrll /* Flush all AC queues. */ 1492 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 0); 1493 1.1.2.2 skrll 1494 1.1.2.2 skrll /* Set beacon interval. */ 1495 1.1.2.2 skrll rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1496 1.1.2.2 skrll 1497 1.1.2.2 skrll switch (ic->ic_opmode) { 1498 1.1.2.2 skrll case IEEE80211_M_STA: 1499 1.1.2.2 skrll /* Allow Rx from our BSSID only. */ 1500 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1501 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) | 1502 1.1.2.2 skrll R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1503 1.1.2.2 skrll 1504 1.1.2.2 skrll /* Enable TSF synchronization. */ 1505 1.1.2.2 skrll rtwn_tsf_sync_enable(sc); 1506 1.1.2.2 skrll break; 1507 1.1.2.2 skrll 1508 1.1.2.2 skrll case IEEE80211_M_HOSTAP: 1509 1.1.2.2 skrll rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1510 1.1.2.2 skrll 1511 1.1.2.2 skrll /* Allow Rx from any BSSID. */ 1512 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 1513 1.1.2.2 skrll rtwn_read_4(sc, R92C_RCR) & 1514 1.1.2.2 skrll ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1515 1.1.2.2 skrll 1516 1.1.2.2 skrll /* Reset TSF timer to zero. */ 1517 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_TCR); 1518 1.1.2.2 skrll reg &= ~0x01; 1519 1.1.2.2 skrll rtwn_write_4(sc, R92C_TCR, reg); 1520 1.1.2.2 skrll reg |= 0x01; 1521 1.1.2.2 skrll rtwn_write_4(sc, R92C_TCR, reg); 1522 1.1.2.2 skrll break; 1523 1.1.2.2 skrll 1524 1.1.2.2 skrll case IEEE80211_M_MONITOR: 1525 1.1.2.2 skrll default: 1526 1.1.2.2 skrll break; 1527 1.1.2.2 skrll } 1528 1.1.2.2 skrll 1529 1.1.2.2 skrll rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1530 1.1.2.2 skrll rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1531 1.1.2.2 skrll rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1532 1.1.2.2 skrll rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1533 1.1.2.2 skrll rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1534 1.1.2.2 skrll rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1535 1.1.2.2 skrll 1536 1.1.2.2 skrll /* Intialize rate adaptation. */ 1537 1.1.2.2 skrll rtwn_ra_init(sc); 1538 1.1.2.2 skrll 1539 1.1.2.2 skrll /* Turn link LED on. */ 1540 1.1.2.2 skrll rtwn_set_led(sc, RTWN_LED_LINK, 1); 1541 1.1.2.2 skrll 1542 1.1.2.2 skrll /* Reset average RSSI. */ 1543 1.1.2.2 skrll sc->avg_pwdb = -1; 1544 1.1.2.2 skrll 1545 1.1.2.2 skrll /* Reset temperature calibration state machine. */ 1546 1.1.2.2 skrll sc->thcal_state = 0; 1547 1.1.2.2 skrll sc->thcal_lctemp = 0; 1548 1.1.2.2 skrll 1549 1.1.2.2 skrll /* Start periodic calibration. */ 1550 1.1.2.2 skrll callout_schedule(&sc->calib_to, mstohz(2000)); 1551 1.1.2.2 skrll break; 1552 1.1.2.2 skrll } 1553 1.1.2.2 skrll 1554 1.1.2.2 skrll (void)sc->sc_newstate(ic, nstate, arg); 1555 1.1.2.2 skrll 1556 1.1.2.2 skrll splx(s); 1557 1.1.2.2 skrll 1558 1.1.2.2 skrll return 0; 1559 1.1.2.2 skrll } 1560 1.1.2.2 skrll 1561 1.1.2.2 skrll static int 1562 1.1.2.2 skrll rtwn_wme_update(struct ieee80211com *ic) 1563 1.1.2.2 skrll { 1564 1.1.2.2 skrll static const uint16_t aci2reg[WME_NUM_AC] = { 1565 1.1.2.2 skrll R92C_EDCA_BE_PARAM, 1566 1.1.2.2 skrll R92C_EDCA_BK_PARAM, 1567 1.1.2.2 skrll R92C_EDCA_VI_PARAM, 1568 1.1.2.2 skrll R92C_EDCA_VO_PARAM 1569 1.1.2.2 skrll }; 1570 1.1.2.2 skrll struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1571 1.1.2.2 skrll const struct wmeParams *wmep; 1572 1.1.2.2 skrll int s, aci, aifs, slottime; 1573 1.1.2.2 skrll 1574 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1575 1.1.2.2 skrll 1576 1.1.2.2 skrll s = splnet(); 1577 1.1.2.2 skrll slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1578 1.1.2.2 skrll for (aci = 0; aci < WME_NUM_AC; aci++) { 1579 1.1.2.2 skrll wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1580 1.1.2.2 skrll /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1581 1.1.2.2 skrll aifs = wmep->wmep_aifsn * slottime + 10; 1582 1.1.2.2 skrll rtwn_write_4(sc, aci2reg[aci], 1583 1.1.2.2 skrll SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1584 1.1.2.2 skrll SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1585 1.1.2.2 skrll SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1586 1.1.2.2 skrll SM(R92C_EDCA_PARAM_AIFS, aifs)); 1587 1.1.2.2 skrll } 1588 1.1.2.2 skrll splx(s); 1589 1.1.2.2 skrll 1590 1.1.2.2 skrll return 0; 1591 1.1.2.2 skrll } 1592 1.1.2.2 skrll 1593 1.1.2.2 skrll static void 1594 1.1.2.2 skrll rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1595 1.1.2.2 skrll { 1596 1.1.2.2 skrll int pwdb; 1597 1.1.2.2 skrll 1598 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1599 1.1.2.2 skrll 1600 1.1.2.2 skrll /* Convert antenna signal to percentage. */ 1601 1.1.2.2 skrll if (rssi <= -100 || rssi >= 20) 1602 1.1.2.2 skrll pwdb = 0; 1603 1.1.2.2 skrll else if (rssi >= 0) 1604 1.1.2.2 skrll pwdb = 100; 1605 1.1.2.2 skrll else 1606 1.1.2.2 skrll pwdb = 100 + rssi; 1607 1.1.2.2 skrll if (rate <= 3) { 1608 1.1.2.2 skrll /* CCK gain is smaller than OFDM/MCS gain. */ 1609 1.1.2.2 skrll pwdb += 6; 1610 1.1.2.2 skrll if (pwdb > 100) 1611 1.1.2.2 skrll pwdb = 100; 1612 1.1.2.2 skrll if (pwdb <= 14) 1613 1.1.2.2 skrll pwdb -= 4; 1614 1.1.2.2 skrll else if (pwdb <= 26) 1615 1.1.2.2 skrll pwdb -= 8; 1616 1.1.2.2 skrll else if (pwdb <= 34) 1617 1.1.2.2 skrll pwdb -= 6; 1618 1.1.2.2 skrll else if (pwdb <= 42) 1619 1.1.2.2 skrll pwdb -= 2; 1620 1.1.2.2 skrll } 1621 1.1.2.2 skrll if (sc->avg_pwdb == -1) /* Init. */ 1622 1.1.2.2 skrll sc->avg_pwdb = pwdb; 1623 1.1.2.2 skrll else if (sc->avg_pwdb < pwdb) 1624 1.1.2.2 skrll sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1625 1.1.2.2 skrll else 1626 1.1.2.2 skrll sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1627 1.1.2.2 skrll DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1628 1.1.2.2 skrll } 1629 1.1.2.2 skrll 1630 1.1.2.2 skrll static int8_t 1631 1.1.2.2 skrll rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1632 1.1.2.2 skrll { 1633 1.1.2.2 skrll static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1634 1.1.2.2 skrll struct r92c_rx_phystat *phy; 1635 1.1.2.2 skrll struct r92c_rx_cck *cck; 1636 1.1.2.2 skrll uint8_t rpt; 1637 1.1.2.2 skrll int8_t rssi; 1638 1.1.2.2 skrll 1639 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1640 1.1.2.2 skrll 1641 1.1.2.2 skrll if (rate <= 3) { 1642 1.1.2.2 skrll cck = (struct r92c_rx_cck *)physt; 1643 1.1.2.2 skrll if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1644 1.1.2.2 skrll rpt = (cck->agc_rpt >> 5) & 0x3; 1645 1.1.2.2 skrll rssi = (cck->agc_rpt & 0x1f) << 1; 1646 1.1.2.2 skrll } else { 1647 1.1.2.2 skrll rpt = (cck->agc_rpt >> 6) & 0x3; 1648 1.1.2.2 skrll rssi = cck->agc_rpt & 0x3e; 1649 1.1.2.2 skrll } 1650 1.1.2.2 skrll rssi = cckoff[rpt] - rssi; 1651 1.1.2.2 skrll } else { /* OFDM/HT. */ 1652 1.1.2.2 skrll phy = (struct r92c_rx_phystat *)physt; 1653 1.1.2.2 skrll rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1654 1.1.2.2 skrll } 1655 1.1.2.2 skrll return rssi; 1656 1.1.2.2 skrll } 1657 1.1.2.2 skrll 1658 1.1.2.2 skrll static void 1659 1.1.2.2 skrll rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1660 1.1.2.2 skrll struct rtwn_rx_data *rx_data, int desc_idx) 1661 1.1.2.2 skrll { 1662 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1663 1.1.2.2 skrll struct ifnet *ifp = IC2IFP(ic); 1664 1.1.2.2 skrll struct ieee80211_frame *wh; 1665 1.1.2.2 skrll struct ieee80211_node *ni; 1666 1.1.2.2 skrll struct r92c_rx_phystat *phy = NULL; 1667 1.1.2.2 skrll uint32_t rxdw0, rxdw3; 1668 1.1.2.2 skrll struct mbuf *m, *m1; 1669 1.1.2.2 skrll uint8_t rate; 1670 1.1.2.2 skrll int8_t rssi = 0; 1671 1.1.2.2 skrll int infosz, pktlen, shift, totlen, error; 1672 1.1.2.2 skrll 1673 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1674 1.1.2.2 skrll 1675 1.1.2.2 skrll rxdw0 = le32toh(rx_desc->rxdw0); 1676 1.1.2.2 skrll rxdw3 = le32toh(rx_desc->rxdw3); 1677 1.1.2.2 skrll 1678 1.1.2.2 skrll if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1679 1.1.2.2 skrll /* 1680 1.1.2.2 skrll * This should not happen since we setup our Rx filter 1681 1.1.2.2 skrll * to not receive these frames. 1682 1.1.2.2 skrll */ 1683 1.1.2.2 skrll ifp->if_ierrors++; 1684 1.1.2.2 skrll return; 1685 1.1.2.2 skrll } 1686 1.1.2.2 skrll 1687 1.1.2.2 skrll pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1688 1.1.2.2 skrll /* 1689 1.1.2.2 skrll * XXX: This will drop most control packets. Do we really 1690 1.1.2.2 skrll * want this in IEEE80211_M_MONITOR mode? 1691 1.1.2.2 skrll */ 1692 1.1.2.2 skrll if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1693 1.1.2.2 skrll ic->ic_stats.is_rx_tooshort++; 1694 1.1.2.2 skrll ifp->if_ierrors++; 1695 1.1.2.2 skrll return; 1696 1.1.2.2 skrll } 1697 1.1.2.2 skrll if (__predict_false(pktlen > MCLBYTES)) { 1698 1.1.2.2 skrll ifp->if_ierrors++; 1699 1.1.2.2 skrll return; 1700 1.1.2.2 skrll } 1701 1.1.2.2 skrll 1702 1.1.2.2 skrll rate = MS(rxdw3, R92C_RXDW3_RATE); 1703 1.1.2.2 skrll infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1704 1.1.2.2 skrll if (infosz > sizeof(struct r92c_rx_phystat)) 1705 1.1.2.2 skrll infosz = sizeof(struct r92c_rx_phystat); 1706 1.1.2.2 skrll shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1707 1.1.2.2 skrll totlen = pktlen + infosz + shift; 1708 1.1.2.2 skrll 1709 1.1.2.2 skrll /* Get RSSI from PHY status descriptor if present. */ 1710 1.1.2.2 skrll if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1711 1.1.2.2 skrll phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1712 1.1.2.2 skrll rssi = rtwn_get_rssi(sc, rate, phy); 1713 1.1.2.2 skrll /* Update our average RSSI. */ 1714 1.1.2.2 skrll rtwn_update_avgrssi(sc, rate, rssi); 1715 1.1.2.2 skrll } 1716 1.1.2.2 skrll 1717 1.1.2.2 skrll DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1718 1.1.2.2 skrll pktlen, rate, infosz, shift, rssi)); 1719 1.1.2.2 skrll 1720 1.1.2.2 skrll MGETHDR(m1, M_DONTWAIT, MT_DATA); 1721 1.1.2.2 skrll if (__predict_false(m1 == NULL)) { 1722 1.1.2.2 skrll ic->ic_stats.is_rx_nobuf++; 1723 1.1.2.2 skrll ifp->if_ierrors++; 1724 1.1.2.2 skrll return; 1725 1.1.2.2 skrll } 1726 1.1.2.2 skrll MCLGET(m1, M_DONTWAIT); 1727 1.1.2.2 skrll if (__predict_false(!(m1->m_flags & M_EXT))) { 1728 1.1.2.2 skrll m_freem(m1); 1729 1.1.2.2 skrll ic->ic_stats.is_rx_nobuf++; 1730 1.1.2.2 skrll ifp->if_ierrors++; 1731 1.1.2.2 skrll return; 1732 1.1.2.2 skrll } 1733 1.1.2.2 skrll 1734 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1735 1.1.2.2 skrll BUS_DMASYNC_POSTREAD); 1736 1.1.2.2 skrll 1737 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1738 1.1.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1739 1.1.2.2 skrll MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1740 1.1.2.2 skrll if (error != 0) { 1741 1.1.2.2 skrll m_freem(m1); 1742 1.1.2.2 skrll 1743 1.1.2.2 skrll if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1744 1.1.2.2 skrll rx_data->m, BUS_DMA_NOWAIT)) 1745 1.1.2.2 skrll panic("%s: could not load old RX mbuf", 1746 1.1.2.2 skrll device_xname(sc->sc_dev)); 1747 1.1.2.2 skrll 1748 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1749 1.1.2.2 skrll BUS_DMASYNC_PREREAD); 1750 1.1.2.2 skrll 1751 1.1.2.2 skrll /* Physical address may have changed. */ 1752 1.1.2.2 skrll rtwn_setup_rx_desc(sc, rx_desc, 1753 1.1.2.2 skrll rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1754 1.1.2.2 skrll 1755 1.1.2.2 skrll ifp->if_ierrors++; 1756 1.1.2.2 skrll return; 1757 1.1.2.2 skrll } 1758 1.1.2.2 skrll 1759 1.1.2.2 skrll /* Finalize mbuf. */ 1760 1.1.2.2 skrll m = rx_data->m; 1761 1.1.2.2 skrll rx_data->m = m1; 1762 1.1.2.2 skrll m->m_pkthdr.len = m->m_len = totlen; 1763 1.1.2.2 skrll m->m_pkthdr.rcvif = ifp; 1764 1.1.2.2 skrll 1765 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1766 1.1.2.2 skrll BUS_DMASYNC_PREREAD); 1767 1.1.2.2 skrll 1768 1.1.2.2 skrll /* Update RX descriptor. */ 1769 1.1.2.2 skrll rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1770 1.1.2.2 skrll MCLBYTES, desc_idx); 1771 1.1.2.2 skrll 1772 1.1.2.2 skrll /* Get ieee80211 frame header. */ 1773 1.1.2.2 skrll if (rxdw0 & R92C_RXDW0_PHYST) 1774 1.1.2.2 skrll m_adj(m, infosz + shift); 1775 1.1.2.2 skrll else 1776 1.1.2.2 skrll m_adj(m, shift); 1777 1.1.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1778 1.1.2.2 skrll 1779 1.1.2.2 skrll if (__predict_false(sc->sc_drvbpf != NULL)) { 1780 1.1.2.2 skrll struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1781 1.1.2.2 skrll 1782 1.1.2.2 skrll tap->wr_flags = 0; 1783 1.1.2.2 skrll /* Map HW rate index to 802.11 rate. */ 1784 1.1.2.2 skrll tap->wr_flags = 2; 1785 1.1.2.2 skrll if (!(rxdw3 & R92C_RXDW3_HT)) { 1786 1.1.2.2 skrll switch (rate) { 1787 1.1.2.2 skrll /* CCK. */ 1788 1.1.2.2 skrll case 0: tap->wr_rate = 2; break; 1789 1.1.2.2 skrll case 1: tap->wr_rate = 4; break; 1790 1.1.2.2 skrll case 2: tap->wr_rate = 11; break; 1791 1.1.2.2 skrll case 3: tap->wr_rate = 22; break; 1792 1.1.2.2 skrll /* OFDM. */ 1793 1.1.2.2 skrll case 4: tap->wr_rate = 12; break; 1794 1.1.2.2 skrll case 5: tap->wr_rate = 18; break; 1795 1.1.2.2 skrll case 6: tap->wr_rate = 24; break; 1796 1.1.2.2 skrll case 7: tap->wr_rate = 36; break; 1797 1.1.2.2 skrll case 8: tap->wr_rate = 48; break; 1798 1.1.2.2 skrll case 9: tap->wr_rate = 72; break; 1799 1.1.2.2 skrll case 10: tap->wr_rate = 96; break; 1800 1.1.2.2 skrll case 11: tap->wr_rate = 108; break; 1801 1.1.2.2 skrll } 1802 1.1.2.2 skrll } else if (rate >= 12) { /* MCS0~15. */ 1803 1.1.2.2 skrll /* Bit 7 set means HT MCS instead of rate. */ 1804 1.1.2.2 skrll tap->wr_rate = 0x80 | (rate - 12); 1805 1.1.2.2 skrll } 1806 1.1.2.2 skrll tap->wr_dbm_antsignal = rssi; 1807 1.1.2.2 skrll tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1808 1.1.2.2 skrll tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1809 1.1.2.2 skrll 1810 1.1.2.2 skrll bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1811 1.1.2.2 skrll } 1812 1.1.2.2 skrll 1813 1.1.2.2 skrll ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1814 1.1.2.2 skrll 1815 1.1.2.2 skrll /* push the frame up to the 802.11 stack */ 1816 1.1.2.2 skrll ieee80211_input(ic, m, ni, rssi, 0); 1817 1.1.2.2 skrll 1818 1.1.2.2 skrll /* Node is no longer needed. */ 1819 1.1.2.2 skrll ieee80211_free_node(ni); 1820 1.1.2.2 skrll } 1821 1.1.2.2 skrll 1822 1.1.2.2 skrll static int 1823 1.1.2.2 skrll rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1824 1.1.2.2 skrll { 1825 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 1826 1.1.2.2 skrll struct ieee80211_frame *wh; 1827 1.1.2.2 skrll struct ieee80211_key *k = NULL; 1828 1.1.2.2 skrll struct rtwn_tx_ring *tx_ring; 1829 1.1.2.2 skrll struct rtwn_tx_data *data; 1830 1.1.2.2 skrll struct r92c_tx_desc *txd; 1831 1.1.2.2 skrll uint16_t qos, seq; 1832 1.1.2.2 skrll uint8_t raid, type, tid, qid; 1833 1.1.2.2 skrll int hasqos, error; 1834 1.1.2.2 skrll 1835 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1836 1.1.2.2 skrll 1837 1.1.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1838 1.1.2.2 skrll type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1839 1.1.2.2 skrll 1840 1.1.2.2 skrll if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1841 1.1.2.2 skrll k = ieee80211_crypto_encap(ic, ni, m); 1842 1.1.2.2 skrll if (k == NULL) 1843 1.1.2.2 skrll return ENOBUFS; 1844 1.1.2.2 skrll 1845 1.1.2.2 skrll wh = mtod(m, struct ieee80211_frame *); 1846 1.1.2.2 skrll } 1847 1.1.2.2 skrll 1848 1.1.2.2 skrll if ((hasqos = ieee80211_has_qos(wh))) { 1849 1.1.2.2 skrll /* data frames in 11n mode */ 1850 1.1.2.2 skrll qos = ieee80211_get_qos(wh); 1851 1.1.2.2 skrll tid = qos & IEEE80211_QOS_TID; 1852 1.1.2.2 skrll qid = TID_TO_WME_AC(tid); 1853 1.1.2.2 skrll } else if (type != IEEE80211_FC0_TYPE_DATA) { 1854 1.1.2.2 skrll /* Use AC_VO for management frames. */ 1855 1.1.2.2 skrll tid = 0; /* compiler happy */ 1856 1.1.2.2 skrll qid = RTWN_VO_QUEUE; 1857 1.1.2.2 skrll } else { 1858 1.1.2.2 skrll /* non-qos data frames */ 1859 1.1.2.2 skrll tid = R92C_TXDW1_QSEL_BE; 1860 1.1.2.2 skrll qid = RTWN_BE_QUEUE; 1861 1.1.2.2 skrll } 1862 1.1.2.2 skrll 1863 1.1.2.2 skrll /* Grab a Tx buffer from the ring. */ 1864 1.1.2.2 skrll tx_ring = &sc->tx_ring[qid]; 1865 1.1.2.2 skrll data = &tx_ring->tx_data[tx_ring->cur]; 1866 1.1.2.2 skrll if (data->m != NULL) { 1867 1.1.2.2 skrll m_freem(m); 1868 1.1.2.2 skrll return ENOBUFS; 1869 1.1.2.2 skrll } 1870 1.1.2.2 skrll 1871 1.1.2.2 skrll /* Fill Tx descriptor. */ 1872 1.1.2.2 skrll txd = &tx_ring->desc[tx_ring->cur]; 1873 1.1.2.2 skrll if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1874 1.1.2.2 skrll m_freem(m); 1875 1.1.2.2 skrll return ENOBUFS; 1876 1.1.2.2 skrll } 1877 1.1.2.2 skrll 1878 1.1.2.2 skrll txd->txdw0 = htole32( 1879 1.1.2.2 skrll SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1880 1.1.2.2 skrll SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1881 1.1.2.2 skrll R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1882 1.1.2.2 skrll if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1883 1.1.2.2 skrll txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1884 1.1.2.2 skrll 1885 1.1.2.2 skrll txd->txdw1 = 0; 1886 1.1.2.2 skrll txd->txdw4 = 0; 1887 1.1.2.2 skrll txd->txdw5 = 0; 1888 1.1.2.2 skrll if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1889 1.1.2.2 skrll type == IEEE80211_FC0_TYPE_DATA) { 1890 1.1.2.2 skrll if (ic->ic_curmode == IEEE80211_MODE_11B) 1891 1.1.2.2 skrll raid = R92C_RAID_11B; 1892 1.1.2.2 skrll else 1893 1.1.2.2 skrll raid = R92C_RAID_11BG; 1894 1.1.2.2 skrll 1895 1.1.2.2 skrll txd->txdw1 |= htole32( 1896 1.1.2.2 skrll SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1897 1.1.2.2 skrll SM(R92C_TXDW1_QSEL, tid) | 1898 1.1.2.2 skrll SM(R92C_TXDW1_RAID, raid) | 1899 1.1.2.2 skrll R92C_TXDW1_AGGBK); 1900 1.1.2.2 skrll 1901 1.1.2.2 skrll if (ic->ic_flags & IEEE80211_F_USEPROT) { 1902 1.1.2.2 skrll /* for 11g */ 1903 1.1.2.2 skrll if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1904 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1905 1.1.2.2 skrll R92C_TXDW4_HWRTSEN); 1906 1.1.2.2 skrll } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1907 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1908 1.1.2.2 skrll R92C_TXDW4_HWRTSEN); 1909 1.1.2.2 skrll } 1910 1.1.2.2 skrll } 1911 1.1.2.2 skrll /* Send RTS at OFDM24. */ 1912 1.1.2.2 skrll txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1913 1.1.2.2 skrll txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1914 1.1.2.2 skrll /* Send data at OFDM54. */ 1915 1.1.2.2 skrll txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1916 1.1.2.2 skrll txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1917 1.1.2.2 skrll } else if (type == IEEE80211_FC0_TYPE_MGT) { 1918 1.1.2.2 skrll txd->txdw1 |= htole32( 1919 1.1.2.2 skrll SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1920 1.1.2.2 skrll SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1921 1.1.2.2 skrll SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1922 1.1.2.2 skrll 1923 1.1.2.2 skrll /* Force CCK1. */ 1924 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1925 1.1.2.2 skrll /* Use 1Mbps */ 1926 1.1.2.2 skrll txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1927 1.1.2.2 skrll } else { 1928 1.1.2.2 skrll txd->txdw1 |= htole32( 1929 1.1.2.2 skrll SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1930 1.1.2.2 skrll SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1931 1.1.2.2 skrll 1932 1.1.2.2 skrll /* Force CCK1. */ 1933 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1934 1.1.2.2 skrll /* Use 1Mbps */ 1935 1.1.2.2 skrll txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1936 1.1.2.2 skrll } 1937 1.1.2.2 skrll 1938 1.1.2.2 skrll /* Set sequence number (already little endian). */ 1939 1.1.2.2 skrll seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1940 1.1.2.2 skrll txd->txdseq = htole16(seq); 1941 1.1.2.2 skrll 1942 1.1.2.2 skrll if (!hasqos) { 1943 1.1.2.2 skrll /* Use HW sequence numbering for non-QoS frames. */ 1944 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1945 1.1.2.2 skrll txd->txdseq |= htole16(0x8000); /* WTF? */ 1946 1.1.2.2 skrll } else 1947 1.1.2.2 skrll txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1948 1.1.2.2 skrll 1949 1.1.2.2 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1950 1.1.2.2 skrll BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1951 1.1.2.2 skrll if (error && error != EFBIG) { 1952 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1953 1.1.2.2 skrll error); 1954 1.1.2.2 skrll m_freem(m); 1955 1.1.2.2 skrll return error; 1956 1.1.2.2 skrll } 1957 1.1.2.2 skrll if (error != 0) { 1958 1.1.2.2 skrll /* Too many DMA segments, linearize mbuf. */ 1959 1.1.2.2 skrll if ((m = m_defrag(m, M_DONTWAIT)) == NULL) { 1960 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1961 1.1.2.2 skrll return ENOBUFS; 1962 1.1.2.2 skrll } 1963 1.1.2.2 skrll 1964 1.1.2.2 skrll error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1965 1.1.2.2 skrll BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1966 1.1.2.2 skrll if (error != 0) { 1967 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 1968 1.1.2.2 skrll "can't map mbuf (error %d)\n", error); 1969 1.1.2.2 skrll m_freem(m); 1970 1.1.2.2 skrll return error; 1971 1.1.2.2 skrll } 1972 1.1.2.2 skrll } 1973 1.1.2.2 skrll 1974 1.1.2.2 skrll txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1975 1.1.2.2 skrll txd->txbufsize = htole16(m->m_pkthdr.len); 1976 1.1.2.2 skrll bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1977 1.1.2.2 skrll BUS_SPACE_BARRIER_WRITE); 1978 1.1.2.2 skrll txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1979 1.1.2.2 skrll 1980 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1981 1.1.2.2 skrll sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1982 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1983 1.1.2.2 skrll BUS_DMASYNC_PREWRITE); 1984 1.1.2.2 skrll 1985 1.1.2.2 skrll data->m = m; 1986 1.1.2.2 skrll data->ni = ni; 1987 1.1.2.2 skrll 1988 1.1.2.2 skrll if (__predict_false(sc->sc_drvbpf != NULL)) { 1989 1.1.2.2 skrll struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1990 1.1.2.2 skrll 1991 1.1.2.2 skrll tap->wt_flags = 0; 1992 1.1.2.2 skrll tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1993 1.1.2.2 skrll tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1994 1.1.2.2 skrll if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1995 1.1.2.2 skrll tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1996 1.1.2.2 skrll 1997 1.1.2.2 skrll bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1998 1.1.2.2 skrll } 1999 1.1.2.2 skrll 2000 1.1.2.2 skrll tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2001 1.1.2.2 skrll tx_ring->queued++; 2002 1.1.2.2 skrll 2003 1.1.2.2 skrll if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 2004 1.1.2.2 skrll sc->qfullmsk |= (1 << qid); 2005 1.1.2.2 skrll 2006 1.1.2.2 skrll /* Kick TX. */ 2007 1.1.2.2 skrll rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2008 1.1.2.2 skrll 2009 1.1.2.2 skrll return 0; 2010 1.1.2.2 skrll } 2011 1.1.2.2 skrll 2012 1.1.2.2 skrll static void 2013 1.1.2.2 skrll rtwn_tx_done(struct rtwn_softc *sc, int qid) 2014 1.1.2.2 skrll { 2015 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2016 1.1.2.2 skrll struct ifnet *ifp = IC2IFP(ic); 2017 1.1.2.2 skrll struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2018 1.1.2.2 skrll struct rtwn_tx_data *tx_data; 2019 1.1.2.2 skrll struct r92c_tx_desc *tx_desc; 2020 1.1.2.2 skrll int i; 2021 1.1.2.2 skrll 2022 1.1.2.2 skrll DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2023 1.1.2.2 skrll qid)); 2024 1.1.2.2 skrll 2025 1.1.2.2 skrll bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2026 1.1.2.2 skrll 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2027 1.1.2.2 skrll BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2028 1.1.2.2 skrll 2029 1.1.2.2 skrll for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2030 1.1.2.2 skrll tx_data = &tx_ring->tx_data[i]; 2031 1.1.2.2 skrll if (tx_data->m == NULL) 2032 1.1.2.2 skrll continue; 2033 1.1.2.2 skrll 2034 1.1.2.2 skrll tx_desc = &tx_ring->desc[i]; 2035 1.1.2.2 skrll if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2036 1.1.2.2 skrll continue; 2037 1.1.2.2 skrll 2038 1.1.2.2 skrll bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2039 1.1.2.2 skrll m_freem(tx_data->m); 2040 1.1.2.2 skrll tx_data->m = NULL; 2041 1.1.2.2 skrll ieee80211_free_node(tx_data->ni); 2042 1.1.2.2 skrll tx_data->ni = NULL; 2043 1.1.2.2 skrll 2044 1.1.2.2 skrll ifp->if_opackets++; 2045 1.1.2.2 skrll sc->sc_tx_timer = 0; 2046 1.1.2.2 skrll tx_ring->queued--; 2047 1.1.2.2 skrll } 2048 1.1.2.2 skrll 2049 1.1.2.2 skrll if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 2050 1.1.2.2 skrll sc->qfullmsk &= ~(1 << qid); 2051 1.1.2.2 skrll } 2052 1.1.2.2 skrll 2053 1.1.2.2 skrll static void 2054 1.1.2.2 skrll rtwn_start(struct ifnet *ifp) 2055 1.1.2.2 skrll { 2056 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 2057 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2058 1.1.2.2 skrll struct ether_header *eh; 2059 1.1.2.2 skrll struct ieee80211_node *ni; 2060 1.1.2.2 skrll struct mbuf *m; 2061 1.1.2.2 skrll 2062 1.1.2.2 skrll if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2063 1.1.2.2 skrll return; 2064 1.1.2.2 skrll 2065 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2066 1.1.2.2 skrll 2067 1.1.2.2 skrll for (;;) { 2068 1.1.2.2 skrll if (sc->qfullmsk != 0) { 2069 1.1.2.2 skrll ifp->if_flags |= IFF_OACTIVE; 2070 1.1.2.2 skrll break; 2071 1.1.2.2 skrll } 2072 1.1.2.2 skrll /* Send pending management frames first. */ 2073 1.1.2.2 skrll IF_DEQUEUE(&ic->ic_mgtq, m); 2074 1.1.2.2 skrll if (m != NULL) { 2075 1.1.2.2 skrll ni = (void *)m->m_pkthdr.rcvif; 2076 1.1.2.2 skrll m->m_pkthdr.rcvif = NULL; 2077 1.1.2.2 skrll goto sendit; 2078 1.1.2.2 skrll } 2079 1.1.2.2 skrll if (ic->ic_state != IEEE80211_S_RUN) 2080 1.1.2.2 skrll break; 2081 1.1.2.2 skrll 2082 1.1.2.2 skrll /* Encapsulate and send data frames. */ 2083 1.1.2.2 skrll IFQ_DEQUEUE(&ifp->if_snd, m); 2084 1.1.2.2 skrll if (m == NULL) 2085 1.1.2.2 skrll break; 2086 1.1.2.2 skrll 2087 1.1.2.2 skrll if (m->m_len < (int)sizeof(*eh) && 2088 1.1.2.2 skrll (m = m_pullup(m, sizeof(*eh))) == NULL) { 2089 1.1.2.2 skrll ifp->if_oerrors++; 2090 1.1.2.2 skrll continue; 2091 1.1.2.2 skrll } 2092 1.1.2.2 skrll eh = mtod(m, struct ether_header *); 2093 1.1.2.2 skrll ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2094 1.1.2.2 skrll if (ni == NULL) { 2095 1.1.2.2 skrll m_freem(m); 2096 1.1.2.2 skrll ifp->if_oerrors++; 2097 1.1.2.2 skrll continue; 2098 1.1.2.2 skrll } 2099 1.1.2.2 skrll 2100 1.1.2.2 skrll bpf_mtap(ifp, m); 2101 1.1.2.2 skrll 2102 1.1.2.2 skrll if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2103 1.1.2.2 skrll ieee80211_free_node(ni); 2104 1.1.2.2 skrll ifp->if_oerrors++; 2105 1.1.2.2 skrll continue; 2106 1.1.2.2 skrll } 2107 1.1.2.2 skrll sendit: 2108 1.1.2.2 skrll bpf_mtap3(ic->ic_rawbpf, m); 2109 1.1.2.2 skrll 2110 1.1.2.2 skrll if (rtwn_tx(sc, m, ni) != 0) { 2111 1.1.2.2 skrll ieee80211_free_node(ni); 2112 1.1.2.2 skrll ifp->if_oerrors++; 2113 1.1.2.2 skrll continue; 2114 1.1.2.2 skrll } 2115 1.1.2.2 skrll 2116 1.1.2.2 skrll sc->sc_tx_timer = 5; 2117 1.1.2.2 skrll ifp->if_timer = 1; 2118 1.1.2.2 skrll } 2119 1.1.2.2 skrll 2120 1.1.2.2 skrll DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2121 1.1.2.2 skrll } 2122 1.1.2.2 skrll 2123 1.1.2.2 skrll static void 2124 1.1.2.2 skrll rtwn_watchdog(struct ifnet *ifp) 2125 1.1.2.2 skrll { 2126 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 2127 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2128 1.1.2.2 skrll 2129 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2130 1.1.2.2 skrll 2131 1.1.2.2 skrll ifp->if_timer = 0; 2132 1.1.2.2 skrll 2133 1.1.2.2 skrll if (sc->sc_tx_timer > 0) { 2134 1.1.2.2 skrll if (--sc->sc_tx_timer == 0) { 2135 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "device timeout\n"); 2136 1.1.2.2 skrll softint_schedule(sc->init_task); 2137 1.1.2.2 skrll ifp->if_oerrors++; 2138 1.1.2.2 skrll return; 2139 1.1.2.2 skrll } 2140 1.1.2.2 skrll ifp->if_timer = 1; 2141 1.1.2.2 skrll } 2142 1.1.2.2 skrll ieee80211_watchdog(ic); 2143 1.1.2.2 skrll } 2144 1.1.2.2 skrll 2145 1.1.2.2 skrll static int 2146 1.1.2.2 skrll rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2147 1.1.2.2 skrll { 2148 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 2149 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2150 1.1.2.2 skrll int s, error = 0; 2151 1.1.2.2 skrll 2152 1.1.2.2 skrll DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2153 1.1.2.2 skrll __func__, cmd, data)); 2154 1.1.2.2 skrll 2155 1.1.2.2 skrll s = splnet(); 2156 1.1.2.2 skrll 2157 1.1.2.2 skrll switch (cmd) { 2158 1.1.2.2 skrll case SIOCSIFFLAGS: 2159 1.1.2.2 skrll if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2160 1.1.2.2 skrll break; 2161 1.1.2.2 skrll switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2162 1.1.2.2 skrll case IFF_UP | IFF_RUNNING: 2163 1.1.2.2 skrll break; 2164 1.1.2.2 skrll case IFF_UP: 2165 1.1.2.2 skrll error = rtwn_init(ifp); 2166 1.1.2.2 skrll if (error != 0) 2167 1.1.2.2 skrll ifp->if_flags &= ~IFF_UP; 2168 1.1.2.2 skrll break; 2169 1.1.2.2 skrll case IFF_RUNNING: 2170 1.1.2.2 skrll rtwn_stop(ifp, 1); 2171 1.1.2.2 skrll break; 2172 1.1.2.2 skrll case 0: 2173 1.1.2.2 skrll break; 2174 1.1.2.2 skrll } 2175 1.1.2.2 skrll break; 2176 1.1.2.2 skrll 2177 1.1.2.2 skrll case SIOCADDMULTI: 2178 1.1.2.2 skrll case SIOCDELMULTI: 2179 1.1.2.2 skrll if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2180 1.1.2.2 skrll /* setup multicast filter, etc */ 2181 1.1.2.2 skrll error = 0; 2182 1.1.2.2 skrll } 2183 1.1.2.2 skrll break; 2184 1.1.2.2 skrll 2185 1.1.2.2 skrll case SIOCS80211CHANNEL: 2186 1.1.2.2 skrll error = ieee80211_ioctl(ic, cmd, data); 2187 1.1.2.2 skrll if (error == ENETRESET && 2188 1.1.2.2 skrll ic->ic_opmode == IEEE80211_M_MONITOR) { 2189 1.1.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2190 1.1.2.2 skrll (IFF_UP | IFF_RUNNING)) { 2191 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 2192 1.1.2.2 skrll } 2193 1.1.2.2 skrll error = 0; 2194 1.1.2.2 skrll } 2195 1.1.2.2 skrll break; 2196 1.1.2.2 skrll 2197 1.1.2.2 skrll default: 2198 1.1.2.2 skrll error = ieee80211_ioctl(ic, cmd, data); 2199 1.1.2.2 skrll break; 2200 1.1.2.2 skrll } 2201 1.1.2.2 skrll 2202 1.1.2.2 skrll if (error == ENETRESET) { 2203 1.1.2.2 skrll error = 0; 2204 1.1.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2205 1.1.2.2 skrll (IFF_UP | IFF_RUNNING)) { 2206 1.1.2.2 skrll rtwn_stop(ifp, 0); 2207 1.1.2.2 skrll error = rtwn_init(ifp); 2208 1.1.2.2 skrll } 2209 1.1.2.2 skrll } 2210 1.1.2.2 skrll 2211 1.1.2.2 skrll splx(s); 2212 1.1.2.2 skrll 2213 1.1.2.2 skrll DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2214 1.1.2.2 skrll error)); 2215 1.1.2.2 skrll 2216 1.1.2.2 skrll return error; 2217 1.1.2.2 skrll } 2218 1.1.2.2 skrll 2219 1.1.2.2 skrll static int 2220 1.1.2.2 skrll rtwn_power_on(struct rtwn_softc *sc) 2221 1.1.2.2 skrll { 2222 1.1.2.2 skrll uint32_t reg; 2223 1.1.2.2 skrll int ntries; 2224 1.1.2.2 skrll 2225 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2226 1.1.2.2 skrll 2227 1.1.2.2 skrll /* Wait for autoload done bit. */ 2228 1.1.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 2229 1.1.2.2 skrll if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2230 1.1.2.2 skrll break; 2231 1.1.2.2 skrll DELAY(5); 2232 1.1.2.2 skrll } 2233 1.1.2.2 skrll if (ntries == 1000) { 2234 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2235 1.1.2.2 skrll "timeout waiting for chip autoload\n"); 2236 1.1.2.2 skrll return ETIMEDOUT; 2237 1.1.2.2 skrll } 2238 1.1.2.2 skrll 2239 1.1.2.2 skrll /* Unlock ISO/CLK/Power control register. */ 2240 1.1.2.2 skrll rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2241 1.1.2.2 skrll 2242 1.1.2.2 skrll /* TODO: check if we need this for 8188CE */ 2243 1.1.2.2 skrll if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2244 1.1.2.2 skrll /* bt coex */ 2245 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2246 1.1.2.2 skrll reg |= (R92C_APS_FSMCO_SOP_ABG | 2247 1.1.2.2 skrll R92C_APS_FSMCO_SOP_AMB | 2248 1.1.2.2 skrll R92C_APS_FSMCO_XOP_BTCK); 2249 1.1.2.2 skrll rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2250 1.1.2.2 skrll } 2251 1.1.2.2 skrll 2252 1.1.2.2 skrll /* Move SPS into PWM mode. */ 2253 1.1.2.2 skrll rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2254 1.1.2.2 skrll DELAY(100); 2255 1.1.2.2 skrll 2256 1.1.2.2 skrll /* Set low byte to 0x0f, leave others unchanged. */ 2257 1.1.2.2 skrll rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2258 1.1.2.2 skrll (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2259 1.1.2.2 skrll 2260 1.1.2.2 skrll /* TODO: check if we need this for 8188CE */ 2261 1.1.2.2 skrll if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2262 1.1.2.2 skrll /* bt coex */ 2263 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2264 1.1.2.2 skrll reg &= ~0x00024800; /* XXX magic from linux */ 2265 1.1.2.2 skrll rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2266 1.1.2.2 skrll } 2267 1.1.2.2 skrll 2268 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2269 1.1.2.2 skrll (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2270 1.1.2.2 skrll R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2271 1.1.2.2 skrll DELAY(200); 2272 1.1.2.2 skrll 2273 1.1.2.2 skrll /* TODO: linux does additional btcoex stuff here */ 2274 1.1.2.2 skrll 2275 1.1.2.2 skrll /* Auto enable WLAN. */ 2276 1.1.2.2 skrll rtwn_write_2(sc, R92C_APS_FSMCO, 2277 1.1.2.2 skrll rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2278 1.1.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 2279 1.1.2.2 skrll if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2280 1.1.2.2 skrll R92C_APS_FSMCO_APFM_ONMAC)) 2281 1.1.2.2 skrll break; 2282 1.1.2.2 skrll DELAY(5); 2283 1.1.2.2 skrll } 2284 1.1.2.2 skrll if (ntries == 1000) { 2285 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2286 1.1.2.2 skrll "timeout waiting for MAC auto ON\n"); 2287 1.1.2.2 skrll return ETIMEDOUT; 2288 1.1.2.2 skrll } 2289 1.1.2.2 skrll 2290 1.1.2.2 skrll /* Enable radio, GPIO and LED functions. */ 2291 1.1.2.2 skrll rtwn_write_2(sc, R92C_APS_FSMCO, 2292 1.1.2.2 skrll R92C_APS_FSMCO_AFSM_PCIE | 2293 1.1.2.2 skrll R92C_APS_FSMCO_PDN_EN | 2294 1.1.2.2 skrll R92C_APS_FSMCO_PFM_ALDN); 2295 1.1.2.2 skrll 2296 1.1.2.2 skrll /* Release RF digital isolation. */ 2297 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2298 1.1.2.2 skrll rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2299 1.1.2.2 skrll 2300 1.1.2.2 skrll if (sc->chip & RTWN_CHIP_92C) 2301 1.1.2.2 skrll rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2302 1.1.2.2 skrll else 2303 1.1.2.2 skrll rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2304 1.1.2.2 skrll 2305 1.1.2.2 skrll rtwn_write_4(sc, R92C_INT_MIG, 0); 2306 1.1.2.2 skrll 2307 1.1.2.2 skrll if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2308 1.1.2.2 skrll /* bt coex */ 2309 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2310 1.1.2.2 skrll reg &= 0xfd; /* XXX magic from linux */ 2311 1.1.2.2 skrll rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2312 1.1.2.2 skrll } 2313 1.1.2.2 skrll 2314 1.1.2.2 skrll rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2315 1.1.2.2 skrll rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2316 1.1.2.2 skrll 2317 1.1.2.2 skrll reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2318 1.1.2.2 skrll if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2319 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2320 1.1.2.2 skrll "radio is disabled by hardware switch\n"); 2321 1.1.2.2 skrll return EPERM; /* :-) */ 2322 1.1.2.2 skrll } 2323 1.1.2.2 skrll 2324 1.1.2.2 skrll /* Initialize MAC. */ 2325 1.1.2.2 skrll reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2326 1.1.2.2 skrll rtwn_write_1(sc, R92C_APSD_CTRL, 2327 1.1.2.2 skrll rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2328 1.1.2.2 skrll for (ntries = 0; ntries < 200; ntries++) { 2329 1.1.2.2 skrll if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2330 1.1.2.2 skrll R92C_APSD_CTRL_OFF_STATUS)) 2331 1.1.2.2 skrll break; 2332 1.1.2.2 skrll DELAY(500); 2333 1.1.2.2 skrll } 2334 1.1.2.2 skrll if (ntries == 200) { 2335 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2336 1.1.2.2 skrll "timeout waiting for MAC initialization\n"); 2337 1.1.2.2 skrll return ETIMEDOUT; 2338 1.1.2.2 skrll } 2339 1.1.2.2 skrll 2340 1.1.2.2 skrll /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2341 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_CR); 2342 1.1.2.2 skrll reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2343 1.1.2.2 skrll R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2344 1.1.2.2 skrll R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2345 1.1.2.2 skrll R92C_CR_ENSEC; 2346 1.1.2.2 skrll rtwn_write_2(sc, R92C_CR, reg); 2347 1.1.2.2 skrll 2348 1.1.2.2 skrll rtwn_write_1(sc, 0xfe10, 0x19); 2349 1.1.2.2 skrll 2350 1.1.2.2 skrll return 0; 2351 1.1.2.2 skrll } 2352 1.1.2.2 skrll 2353 1.1.2.2 skrll static int 2354 1.1.2.2 skrll rtwn_llt_init(struct rtwn_softc *sc) 2355 1.1.2.2 skrll { 2356 1.1.2.2 skrll int i, error; 2357 1.1.2.2 skrll 2358 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2359 1.1.2.2 skrll 2360 1.1.2.2 skrll /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2361 1.1.2.2 skrll for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2362 1.1.2.2 skrll if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2363 1.1.2.2 skrll return error; 2364 1.1.2.2 skrll } 2365 1.1.2.2 skrll /* NB: 0xff indicates end-of-list. */ 2366 1.1.2.2 skrll if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2367 1.1.2.2 skrll return error; 2368 1.1.2.2 skrll /* 2369 1.1.2.2 skrll * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2370 1.1.2.2 skrll * as ring buffer. 2371 1.1.2.2 skrll */ 2372 1.1.2.2 skrll for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2373 1.1.2.2 skrll if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2374 1.1.2.2 skrll return error; 2375 1.1.2.2 skrll } 2376 1.1.2.2 skrll /* Make the last page point to the beginning of the ring buffer. */ 2377 1.1.2.2 skrll error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2378 1.1.2.2 skrll return error; 2379 1.1.2.2 skrll } 2380 1.1.2.2 skrll 2381 1.1.2.2 skrll static void 2382 1.1.2.2 skrll rtwn_fw_reset(struct rtwn_softc *sc) 2383 1.1.2.2 skrll { 2384 1.1.2.2 skrll uint16_t reg; 2385 1.1.2.2 skrll int ntries; 2386 1.1.2.2 skrll 2387 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2388 1.1.2.2 skrll 2389 1.1.2.2 skrll /* Tell 8051 to reset itself. */ 2390 1.1.2.2 skrll rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2391 1.1.2.2 skrll 2392 1.1.2.2 skrll /* Wait until 8051 resets by itself. */ 2393 1.1.2.2 skrll for (ntries = 0; ntries < 100; ntries++) { 2394 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2395 1.1.2.2 skrll if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2396 1.1.2.2 skrll goto sleep; 2397 1.1.2.2 skrll DELAY(50); 2398 1.1.2.2 skrll } 2399 1.1.2.2 skrll /* Force 8051 reset. */ 2400 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2401 1.1.2.2 skrll sleep: 2402 1.1.2.2 skrll CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2403 1.1.2.2 skrll #if 0 2404 1.1.2.2 skrll /* 2405 1.1.2.2 skrll * We must sleep for one second to let the firmware settle. 2406 1.1.2.2 skrll * Accessing registers too early will hang the whole system. 2407 1.1.2.2 skrll */ 2408 1.1.2.2 skrll tsleep(®, 0, "rtwnrst", hz); 2409 1.1.2.2 skrll #else 2410 1.1.2.2 skrll DELAY(1000 * 1000); 2411 1.1.2.2 skrll #endif 2412 1.1.2.2 skrll } 2413 1.1.2.2 skrll 2414 1.1.2.2 skrll static int 2415 1.1.2.2 skrll rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2416 1.1.2.2 skrll { 2417 1.1.2.2 skrll uint32_t reg; 2418 1.1.2.2 skrll int off, mlen, error = 0, i; 2419 1.1.2.2 skrll 2420 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2421 1.1.2.2 skrll 2422 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_MCUFWDL); 2423 1.1.2.2 skrll reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2424 1.1.2.2 skrll rtwn_write_4(sc, R92C_MCUFWDL, reg); 2425 1.1.2.2 skrll 2426 1.1.2.2 skrll DELAY(5); 2427 1.1.2.2 skrll 2428 1.1.2.2 skrll off = R92C_FW_START_ADDR; 2429 1.1.2.2 skrll while (len > 0) { 2430 1.1.2.2 skrll if (len > 196) 2431 1.1.2.2 skrll mlen = 196; 2432 1.1.2.2 skrll else if (len > 4) 2433 1.1.2.2 skrll mlen = 4; 2434 1.1.2.2 skrll else 2435 1.1.2.2 skrll mlen = 1; 2436 1.1.2.2 skrll for (i = 0; i < mlen; i++) 2437 1.1.2.2 skrll rtwn_write_1(sc, off++, buf[i]); 2438 1.1.2.2 skrll buf += mlen; 2439 1.1.2.2 skrll len -= mlen; 2440 1.1.2.2 skrll } 2441 1.1.2.2 skrll 2442 1.1.2.2 skrll return error; 2443 1.1.2.2 skrll } 2444 1.1.2.2 skrll 2445 1.1.2.2 skrll static int 2446 1.1.2.2 skrll rtwn_load_firmware(struct rtwn_softc *sc) 2447 1.1.2.2 skrll { 2448 1.1.2.2 skrll firmware_handle_t fwh; 2449 1.1.2.2 skrll const struct r92c_fw_hdr *hdr; 2450 1.1.2.2 skrll const char *name; 2451 1.1.2.2 skrll u_char *fw, *ptr; 2452 1.1.2.2 skrll size_t len; 2453 1.1.2.2 skrll uint32_t reg; 2454 1.1.2.2 skrll int mlen, ntries, page, error; 2455 1.1.2.2 skrll 2456 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2457 1.1.2.2 skrll 2458 1.1.2.2 skrll /* Read firmware image from the filesystem. */ 2459 1.1.2.2 skrll if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2460 1.1.2.2 skrll RTWN_CHIP_UMC_A_CUT) 2461 1.1.2.2 skrll name = "rtl8192cfwU.bin"; 2462 1.1.2.2 skrll else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2463 1.1.2.2 skrll name = "rtl8192cfwU_B.bin"; 2464 1.1.2.2 skrll else 2465 1.1.2.2 skrll name = "rtl8192cfw.bin"; 2466 1.1.2.2 skrll DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2467 1.1.2.2 skrll if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2468 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2469 1.1.2.2 skrll "could not read firmware %s (error %d)\n", name, error); 2470 1.1.2.2 skrll return error; 2471 1.1.2.2 skrll } 2472 1.1.2.2 skrll const size_t fwlen = len = firmware_get_size(fwh); 2473 1.1.2.2 skrll fw = firmware_malloc(len); 2474 1.1.2.2 skrll if (fw == NULL) { 2475 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2476 1.1.2.2 skrll "failed to allocate firmware memory (size=%zu)\n", len); 2477 1.1.2.2 skrll firmware_close(fwh); 2478 1.1.2.2 skrll return ENOMEM; 2479 1.1.2.2 skrll } 2480 1.1.2.2 skrll error = firmware_read(fwh, 0, fw, len); 2481 1.1.2.2 skrll firmware_close(fwh); 2482 1.1.2.2 skrll if (error != 0) { 2483 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2484 1.1.2.2 skrll "failed to read firmware (error %d)\n", error); 2485 1.1.2.2 skrll firmware_free(fw, fwlen); 2486 1.1.2.2 skrll return error; 2487 1.1.2.2 skrll } 2488 1.1.2.2 skrll 2489 1.1.2.2 skrll if (len < sizeof(*hdr)) { 2490 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2491 1.1.2.2 skrll error = EINVAL; 2492 1.1.2.2 skrll goto fail; 2493 1.1.2.2 skrll } 2494 1.1.2.2 skrll ptr = fw; 2495 1.1.2.2 skrll hdr = (const struct r92c_fw_hdr *)ptr; 2496 1.1.2.2 skrll /* Check if there is a valid FW header and skip it. */ 2497 1.1.2.2 skrll if ((le16toh(hdr->signature) >> 4) == 0x88c || 2498 1.1.2.2 skrll (le16toh(hdr->signature) >> 4) == 0x92c) { 2499 1.1.2.2 skrll DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2500 1.1.2.2 skrll le16toh(hdr->version), le16toh(hdr->subversion), 2501 1.1.2.2 skrll hdr->month, hdr->date, hdr->hour, hdr->minute)); 2502 1.1.2.2 skrll ptr += sizeof(*hdr); 2503 1.1.2.2 skrll len -= sizeof(*hdr); 2504 1.1.2.2 skrll } 2505 1.1.2.2 skrll 2506 1.1.2.2 skrll if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2507 1.1.2.2 skrll rtwn_fw_reset(sc); 2508 1.1.2.2 skrll 2509 1.1.2.2 skrll /* Enable FW download. */ 2510 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2511 1.1.2.2 skrll rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2512 1.1.2.2 skrll R92C_SYS_FUNC_EN_CPUEN); 2513 1.1.2.2 skrll rtwn_write_1(sc, R92C_MCUFWDL, 2514 1.1.2.2 skrll rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2515 1.1.2.2 skrll rtwn_write_1(sc, R92C_MCUFWDL + 2, 2516 1.1.2.2 skrll rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2517 1.1.2.2 skrll 2518 1.1.2.2 skrll /* Reset the FWDL checksum. */ 2519 1.1.2.2 skrll rtwn_write_1(sc, R92C_MCUFWDL, 2520 1.1.2.2 skrll rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2521 1.1.2.2 skrll 2522 1.1.2.2 skrll /* download firmware */ 2523 1.1.2.2 skrll for (page = 0; len > 0; page++) { 2524 1.1.2.2 skrll mlen = MIN(len, R92C_FW_PAGE_SIZE); 2525 1.1.2.2 skrll error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2526 1.1.2.2 skrll if (error != 0) { 2527 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2528 1.1.2.2 skrll "could not load firmware page %d\n", page); 2529 1.1.2.2 skrll goto fail; 2530 1.1.2.2 skrll } 2531 1.1.2.2 skrll ptr += mlen; 2532 1.1.2.2 skrll len -= mlen; 2533 1.1.2.2 skrll } 2534 1.1.2.2 skrll 2535 1.1.2.2 skrll /* Disable FW download. */ 2536 1.1.2.2 skrll rtwn_write_1(sc, R92C_MCUFWDL, 2537 1.1.2.2 skrll rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2538 1.1.2.2 skrll rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2539 1.1.2.2 skrll 2540 1.1.2.2 skrll /* Wait for checksum report. */ 2541 1.1.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 2542 1.1.2.2 skrll if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2543 1.1.2.2 skrll break; 2544 1.1.2.2 skrll DELAY(5); 2545 1.1.2.2 skrll } 2546 1.1.2.2 skrll if (ntries == 1000) { 2547 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2548 1.1.2.2 skrll "timeout waiting for checksum report\n"); 2549 1.1.2.2 skrll error = ETIMEDOUT; 2550 1.1.2.2 skrll goto fail; 2551 1.1.2.2 skrll } 2552 1.1.2.2 skrll 2553 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_MCUFWDL); 2554 1.1.2.2 skrll reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2555 1.1.2.2 skrll rtwn_write_4(sc, R92C_MCUFWDL, reg); 2556 1.1.2.2 skrll 2557 1.1.2.2 skrll /* Wait for firmware readiness. */ 2558 1.1.2.2 skrll for (ntries = 0; ntries < 1000; ntries++) { 2559 1.1.2.2 skrll if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2560 1.1.2.2 skrll break; 2561 1.1.2.2 skrll DELAY(5); 2562 1.1.2.2 skrll } 2563 1.1.2.2 skrll if (ntries == 1000) { 2564 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, 2565 1.1.2.2 skrll "timeout waiting for firmware readiness\n"); 2566 1.1.2.2 skrll error = ETIMEDOUT; 2567 1.1.2.2 skrll goto fail; 2568 1.1.2.2 skrll } 2569 1.1.2.2 skrll SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2570 1.1.2.2 skrll 2571 1.1.2.2 skrll fail: 2572 1.1.2.2 skrll firmware_free(fw, fwlen); 2573 1.1.2.2 skrll return error; 2574 1.1.2.2 skrll } 2575 1.1.2.2 skrll 2576 1.1.2.2 skrll static int 2577 1.1.2.2 skrll rtwn_dma_init(struct rtwn_softc *sc) 2578 1.1.2.2 skrll { 2579 1.1.2.2 skrll uint32_t reg; 2580 1.1.2.2 skrll int error; 2581 1.1.2.2 skrll 2582 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2583 1.1.2.2 skrll 2584 1.1.2.2 skrll /* Initialize LLT table. */ 2585 1.1.2.2 skrll error = rtwn_llt_init(sc); 2586 1.1.2.2 skrll if (error != 0) 2587 1.1.2.2 skrll return error; 2588 1.1.2.2 skrll 2589 1.1.2.2 skrll /* Set number of pages for normal priority queue. */ 2590 1.1.2.2 skrll rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2591 1.1.2.2 skrll rtwn_write_4(sc, R92C_RQPN, 2592 1.1.2.2 skrll /* Set number of pages for public queue. */ 2593 1.1.2.2 skrll SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2594 1.1.2.2 skrll /* Set number of pages for high priority queue. */ 2595 1.1.2.2 skrll SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2596 1.1.2.2 skrll /* Set number of pages for low priority queue. */ 2597 1.1.2.2 skrll SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2598 1.1.2.2 skrll /* Load values. */ 2599 1.1.2.2 skrll R92C_RQPN_LD); 2600 1.1.2.2 skrll 2601 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2602 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2603 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2604 1.1.2.2 skrll rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2605 1.1.2.2 skrll rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2606 1.1.2.2 skrll 2607 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2608 1.1.2.2 skrll reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2609 1.1.2.2 skrll reg |= 0xF771; 2610 1.1.2.2 skrll rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2611 1.1.2.2 skrll 2612 1.1.2.2 skrll rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2613 1.1.2.2 skrll 2614 1.1.2.2 skrll /* Configure Tx DMA. */ 2615 1.1.2.2 skrll rtwn_write_4(sc, R92C_BKQ_DESA, 2616 1.1.2.2 skrll sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2617 1.1.2.2 skrll rtwn_write_4(sc, R92C_BEQ_DESA, 2618 1.1.2.2 skrll sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2619 1.1.2.2 skrll rtwn_write_4(sc, R92C_VIQ_DESA, 2620 1.1.2.2 skrll sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2621 1.1.2.2 skrll rtwn_write_4(sc, R92C_VOQ_DESA, 2622 1.1.2.2 skrll sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2623 1.1.2.2 skrll rtwn_write_4(sc, R92C_BCNQ_DESA, 2624 1.1.2.2 skrll sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2625 1.1.2.2 skrll rtwn_write_4(sc, R92C_MGQ_DESA, 2626 1.1.2.2 skrll sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2627 1.1.2.2 skrll rtwn_write_4(sc, R92C_HQ_DESA, 2628 1.1.2.2 skrll sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2629 1.1.2.2 skrll 2630 1.1.2.2 skrll /* Configure Rx DMA. */ 2631 1.1.2.2 skrll rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2632 1.1.2.2 skrll 2633 1.1.2.2 skrll /* Set Tx/Rx transfer page boundary. */ 2634 1.1.2.2 skrll rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2635 1.1.2.2 skrll 2636 1.1.2.2 skrll /* Set Tx/Rx transfer page size. */ 2637 1.1.2.2 skrll rtwn_write_1(sc, R92C_PBP, 2638 1.1.2.2 skrll SM(R92C_PBP_PSRX, R92C_PBP_128) | 2639 1.1.2.2 skrll SM(R92C_PBP_PSTX, R92C_PBP_128)); 2640 1.1.2.2 skrll return 0; 2641 1.1.2.2 skrll } 2642 1.1.2.2 skrll 2643 1.1.2.2 skrll static void 2644 1.1.2.2 skrll rtwn_mac_init(struct rtwn_softc *sc) 2645 1.1.2.2 skrll { 2646 1.1.2.2 skrll int i; 2647 1.1.2.2 skrll 2648 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2649 1.1.2.2 skrll 2650 1.1.2.2 skrll /* Write MAC initialization values. */ 2651 1.1.2.2 skrll for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2652 1.1.2.2 skrll rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2653 1.1.2.2 skrll } 2654 1.1.2.2 skrll 2655 1.1.2.2 skrll static void 2656 1.1.2.2 skrll rtwn_bb_init(struct rtwn_softc *sc) 2657 1.1.2.2 skrll { 2658 1.1.2.2 skrll const struct rtwn_bb_prog *prog; 2659 1.1.2.2 skrll uint32_t reg; 2660 1.1.2.2 skrll int i; 2661 1.1.2.2 skrll 2662 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2663 1.1.2.2 skrll 2664 1.1.2.2 skrll /* Enable BB and RF. */ 2665 1.1.2.2 skrll rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2666 1.1.2.2 skrll rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2667 1.1.2.2 skrll R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2668 1.1.2.2 skrll R92C_SYS_FUNC_EN_DIO_RF); 2669 1.1.2.2 skrll 2670 1.1.2.2 skrll rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2671 1.1.2.2 skrll 2672 1.1.2.2 skrll rtwn_write_1(sc, R92C_RF_CTRL, 2673 1.1.2.2 skrll R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2674 1.1.2.2 skrll 2675 1.1.2.2 skrll rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2676 1.1.2.2 skrll R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2677 1.1.2.2 skrll R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2678 1.1.2.2 skrll R92C_SYS_FUNC_EN_BBRSTB); 2679 1.1.2.2 skrll 2680 1.1.2.2 skrll rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2681 1.1.2.2 skrll 2682 1.1.2.2 skrll rtwn_write_4(sc, R92C_LEDCFG0, 2683 1.1.2.2 skrll rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2684 1.1.2.2 skrll 2685 1.1.2.2 skrll /* Select BB programming. */ 2686 1.1.2.2 skrll prog = (sc->chip & RTWN_CHIP_92C) ? 2687 1.1.2.2 skrll &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2688 1.1.2.2 skrll 2689 1.1.2.2 skrll /* Write BB initialization values. */ 2690 1.1.2.2 skrll for (i = 0; i < prog->count; i++) { 2691 1.1.2.2 skrll rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2692 1.1.2.2 skrll DELAY(1); 2693 1.1.2.2 skrll } 2694 1.1.2.2 skrll 2695 1.1.2.2 skrll if (sc->chip & RTWN_CHIP_92C_1T2R) { 2696 1.1.2.2 skrll /* 8192C 1T only configuration. */ 2697 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2698 1.1.2.2 skrll reg = (reg & ~0x00000003) | 0x2; 2699 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2700 1.1.2.2 skrll 2701 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2702 1.1.2.2 skrll reg = (reg & ~0x00300033) | 0x00200022; 2703 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2704 1.1.2.2 skrll 2705 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2706 1.1.2.2 skrll reg = (reg & ~0xff000000) | 0x45 << 24; 2707 1.1.2.2 skrll rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2708 1.1.2.2 skrll 2709 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2710 1.1.2.2 skrll reg = (reg & ~0x000000ff) | 0x23; 2711 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2712 1.1.2.2 skrll 2713 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2714 1.1.2.2 skrll reg = (reg & ~0x00000030) | 1 << 4; 2715 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2716 1.1.2.2 skrll 2717 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0xe74); 2718 1.1.2.2 skrll reg = (reg & ~0x0c000000) | 2 << 26; 2719 1.1.2.2 skrll rtwn_bb_write(sc, 0xe74, reg); 2720 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0xe78); 2721 1.1.2.2 skrll reg = (reg & ~0x0c000000) | 2 << 26; 2722 1.1.2.2 skrll rtwn_bb_write(sc, 0xe78, reg); 2723 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0xe7c); 2724 1.1.2.2 skrll reg = (reg & ~0x0c000000) | 2 << 26; 2725 1.1.2.2 skrll rtwn_bb_write(sc, 0xe7c, reg); 2726 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0xe80); 2727 1.1.2.2 skrll reg = (reg & ~0x0c000000) | 2 << 26; 2728 1.1.2.2 skrll rtwn_bb_write(sc, 0xe80, reg); 2729 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0xe88); 2730 1.1.2.2 skrll reg = (reg & ~0x0c000000) | 2 << 26; 2731 1.1.2.2 skrll rtwn_bb_write(sc, 0xe88, reg); 2732 1.1.2.2 skrll } 2733 1.1.2.2 skrll 2734 1.1.2.2 skrll /* Write AGC values. */ 2735 1.1.2.2 skrll for (i = 0; i < prog->agccount; i++) { 2736 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2737 1.1.2.2 skrll prog->agcvals[i]); 2738 1.1.2.2 skrll DELAY(1); 2739 1.1.2.2 skrll } 2740 1.1.2.2 skrll 2741 1.1.2.2 skrll if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2742 1.1.2.2 skrll R92C_HSSI_PARAM2_CCK_HIPWR) 2743 1.1.2.2 skrll sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2744 1.1.2.2 skrll } 2745 1.1.2.2 skrll 2746 1.1.2.2 skrll static void 2747 1.1.2.2 skrll rtwn_rf_init(struct rtwn_softc *sc) 2748 1.1.2.2 skrll { 2749 1.1.2.2 skrll const struct rtwn_rf_prog *prog; 2750 1.1.2.2 skrll uint32_t reg, type; 2751 1.1.2.2 skrll int i, j, idx, off; 2752 1.1.2.2 skrll 2753 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2754 1.1.2.2 skrll 2755 1.1.2.2 skrll /* Select RF programming based on board type. */ 2756 1.1.2.2 skrll if (!(sc->chip & RTWN_CHIP_92C)) { 2757 1.1.2.2 skrll if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2758 1.1.2.2 skrll prog = rtl8188ce_rf_prog; 2759 1.1.2.2 skrll else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2760 1.1.2.2 skrll prog = rtl8188ru_rf_prog; 2761 1.1.2.2 skrll else 2762 1.1.2.2 skrll prog = rtl8188cu_rf_prog; 2763 1.1.2.2 skrll } else 2764 1.1.2.2 skrll prog = rtl8192ce_rf_prog; 2765 1.1.2.2 skrll 2766 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) { 2767 1.1.2.2 skrll /* Save RF_ENV control type. */ 2768 1.1.2.2 skrll idx = i / 2; 2769 1.1.2.2 skrll off = (i % 2) * 16; 2770 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2771 1.1.2.2 skrll type = (reg >> off) & 0x10; 2772 1.1.2.2 skrll 2773 1.1.2.2 skrll /* Set RF_ENV enable. */ 2774 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2775 1.1.2.2 skrll reg |= 0x100000; 2776 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2777 1.1.2.2 skrll DELAY(1); 2778 1.1.2.2 skrll /* Set RF_ENV output high. */ 2779 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2780 1.1.2.2 skrll reg |= 0x10; 2781 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2782 1.1.2.2 skrll DELAY(1); 2783 1.1.2.2 skrll /* Set address and data lengths of RF registers. */ 2784 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2785 1.1.2.2 skrll reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2786 1.1.2.2 skrll rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2787 1.1.2.2 skrll DELAY(1); 2788 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2789 1.1.2.2 skrll reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2790 1.1.2.2 skrll rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2791 1.1.2.2 skrll DELAY(1); 2792 1.1.2.2 skrll 2793 1.1.2.2 skrll /* Write RF initialization values for this chain. */ 2794 1.1.2.2 skrll for (j = 0; j < prog[i].count; j++) { 2795 1.1.2.2 skrll if (prog[i].regs[j] >= 0xf9 && 2796 1.1.2.2 skrll prog[i].regs[j] <= 0xfe) { 2797 1.1.2.2 skrll /* 2798 1.1.2.2 skrll * These are fake RF registers offsets that 2799 1.1.2.2 skrll * indicate a delay is required. 2800 1.1.2.2 skrll */ 2801 1.1.2.2 skrll DELAY(50); 2802 1.1.2.2 skrll continue; 2803 1.1.2.2 skrll } 2804 1.1.2.2 skrll rtwn_rf_write(sc, i, prog[i].regs[j], 2805 1.1.2.2 skrll prog[i].vals[j]); 2806 1.1.2.2 skrll DELAY(1); 2807 1.1.2.2 skrll } 2808 1.1.2.2 skrll 2809 1.1.2.2 skrll /* Restore RF_ENV control type. */ 2810 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2811 1.1.2.2 skrll reg &= ~(0x10 << off) | (type << off); 2812 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2813 1.1.2.2 skrll 2814 1.1.2.2 skrll /* Cache RF register CHNLBW. */ 2815 1.1.2.2 skrll sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2816 1.1.2.2 skrll } 2817 1.1.2.2 skrll 2818 1.1.2.2 skrll if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2819 1.1.2.2 skrll RTWN_CHIP_UMC_A_CUT) { 2820 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2821 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2822 1.1.2.2 skrll } 2823 1.1.2.2 skrll } 2824 1.1.2.2 skrll 2825 1.1.2.2 skrll static void 2826 1.1.2.2 skrll rtwn_cam_init(struct rtwn_softc *sc) 2827 1.1.2.2 skrll { 2828 1.1.2.2 skrll 2829 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2830 1.1.2.2 skrll 2831 1.1.2.2 skrll /* Invalidate all CAM entries. */ 2832 1.1.2.2 skrll rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2833 1.1.2.2 skrll } 2834 1.1.2.2 skrll 2835 1.1.2.2 skrll static void 2836 1.1.2.2 skrll rtwn_pa_bias_init(struct rtwn_softc *sc) 2837 1.1.2.2 skrll { 2838 1.1.2.2 skrll uint8_t reg; 2839 1.1.2.2 skrll int i; 2840 1.1.2.2 skrll 2841 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2842 1.1.2.2 skrll 2843 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) { 2844 1.1.2.2 skrll if (sc->pa_setting & (1 << i)) 2845 1.1.2.2 skrll continue; 2846 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2847 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2848 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2849 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2850 1.1.2.2 skrll } 2851 1.1.2.2 skrll if (!(sc->pa_setting & 0x10)) { 2852 1.1.2.2 skrll reg = rtwn_read_1(sc, 0x16); 2853 1.1.2.2 skrll reg = (reg & ~0xf0) | 0x90; 2854 1.1.2.2 skrll rtwn_write_1(sc, 0x16, reg); 2855 1.1.2.2 skrll } 2856 1.1.2.2 skrll } 2857 1.1.2.2 skrll 2858 1.1.2.2 skrll static void 2859 1.1.2.2 skrll rtwn_rxfilter_init(struct rtwn_softc *sc) 2860 1.1.2.2 skrll { 2861 1.1.2.2 skrll 2862 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2863 1.1.2.2 skrll 2864 1.1.2.2 skrll /* Initialize Rx filter. */ 2865 1.1.2.2 skrll /* TODO: use better filter for monitor mode. */ 2866 1.1.2.2 skrll rtwn_write_4(sc, R92C_RCR, 2867 1.1.2.2 skrll R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2868 1.1.2.2 skrll R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2869 1.1.2.2 skrll R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2870 1.1.2.2 skrll /* Accept all multicast frames. */ 2871 1.1.2.2 skrll rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2872 1.1.2.2 skrll rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2873 1.1.2.2 skrll /* Accept all management frames. */ 2874 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2875 1.1.2.2 skrll /* Reject all control frames. */ 2876 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2877 1.1.2.2 skrll /* Accept all data frames. */ 2878 1.1.2.2 skrll rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2879 1.1.2.2 skrll } 2880 1.1.2.2 skrll 2881 1.1.2.2 skrll static void 2882 1.1.2.2 skrll rtwn_edca_init(struct rtwn_softc *sc) 2883 1.1.2.2 skrll { 2884 1.1.2.2 skrll 2885 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2886 1.1.2.2 skrll 2887 1.1.2.2 skrll /* set spec SIFS (used in NAV) */ 2888 1.1.2.2 skrll rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2889 1.1.2.2 skrll rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2890 1.1.2.2 skrll 2891 1.1.2.2 skrll /* set SIFS CCK/OFDM */ 2892 1.1.2.2 skrll rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2893 1.1.2.2 skrll rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2894 1.1.2.2 skrll 2895 1.1.2.2 skrll /* TXOP */ 2896 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2897 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2898 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2899 1.1.2.2 skrll rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2900 1.1.2.2 skrll } 2901 1.1.2.2 skrll 2902 1.1.2.2 skrll static void 2903 1.1.2.2 skrll rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2904 1.1.2.2 skrll uint16_t power[RTWN_RIDX_COUNT]) 2905 1.1.2.2 skrll { 2906 1.1.2.2 skrll uint32_t reg; 2907 1.1.2.2 skrll 2908 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2909 1.1.2.2 skrll 2910 1.1.2.2 skrll /* Write per-CCK rate Tx power. */ 2911 1.1.2.2 skrll if (chain == 0) { 2912 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2913 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2914 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2915 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2916 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2917 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2918 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2919 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2920 1.1.2.2 skrll } else { 2921 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2922 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2923 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2924 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2925 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2926 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2927 1.1.2.2 skrll reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2928 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2929 1.1.2.2 skrll } 2930 1.1.2.2 skrll /* Write per-OFDM rate Tx power. */ 2931 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2932 1.1.2.2 skrll SM(R92C_TXAGC_RATE06, power[ 4]) | 2933 1.1.2.2 skrll SM(R92C_TXAGC_RATE09, power[ 5]) | 2934 1.1.2.2 skrll SM(R92C_TXAGC_RATE12, power[ 6]) | 2935 1.1.2.2 skrll SM(R92C_TXAGC_RATE18, power[ 7])); 2936 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2937 1.1.2.2 skrll SM(R92C_TXAGC_RATE24, power[ 8]) | 2938 1.1.2.2 skrll SM(R92C_TXAGC_RATE36, power[ 9]) | 2939 1.1.2.2 skrll SM(R92C_TXAGC_RATE48, power[10]) | 2940 1.1.2.2 skrll SM(R92C_TXAGC_RATE54, power[11])); 2941 1.1.2.2 skrll /* Write per-MCS Tx power. */ 2942 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2943 1.1.2.2 skrll SM(R92C_TXAGC_MCS00, power[12]) | 2944 1.1.2.2 skrll SM(R92C_TXAGC_MCS01, power[13]) | 2945 1.1.2.2 skrll SM(R92C_TXAGC_MCS02, power[14]) | 2946 1.1.2.2 skrll SM(R92C_TXAGC_MCS03, power[15])); 2947 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2948 1.1.2.2 skrll SM(R92C_TXAGC_MCS04, power[16]) | 2949 1.1.2.2 skrll SM(R92C_TXAGC_MCS05, power[17]) | 2950 1.1.2.2 skrll SM(R92C_TXAGC_MCS06, power[18]) | 2951 1.1.2.2 skrll SM(R92C_TXAGC_MCS07, power[19])); 2952 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2953 1.1.2.2 skrll SM(R92C_TXAGC_MCS08, power[20]) | 2954 1.1.2.2 skrll SM(R92C_TXAGC_MCS09, power[21]) | 2955 1.1.2.2 skrll SM(R92C_TXAGC_MCS10, power[22]) | 2956 1.1.2.2 skrll SM(R92C_TXAGC_MCS11, power[23])); 2957 1.1.2.2 skrll rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2958 1.1.2.2 skrll SM(R92C_TXAGC_MCS12, power[24]) | 2959 1.1.2.2 skrll SM(R92C_TXAGC_MCS13, power[25]) | 2960 1.1.2.2 skrll SM(R92C_TXAGC_MCS14, power[26]) | 2961 1.1.2.2 skrll SM(R92C_TXAGC_MCS15, power[27])); 2962 1.1.2.2 skrll } 2963 1.1.2.2 skrll 2964 1.1.2.2 skrll static void 2965 1.1.2.2 skrll rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2966 1.1.2.2 skrll struct ieee80211_channel *c, struct ieee80211_channel *extc, 2967 1.1.2.2 skrll uint16_t power[RTWN_RIDX_COUNT]) 2968 1.1.2.2 skrll { 2969 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 2970 1.1.2.2 skrll struct r92c_rom *rom = &sc->rom; 2971 1.1.2.2 skrll uint16_t cckpow, ofdmpow, htpow, diff, max; 2972 1.1.2.2 skrll const struct rtwn_txpwr *base; 2973 1.1.2.2 skrll int ridx, chan, group; 2974 1.1.2.2 skrll 2975 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2976 1.1.2.2 skrll 2977 1.1.2.2 skrll /* Determine channel group. */ 2978 1.1.2.2 skrll chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2979 1.1.2.2 skrll if (chan <= 3) 2980 1.1.2.2 skrll group = 0; 2981 1.1.2.2 skrll else if (chan <= 9) 2982 1.1.2.2 skrll group = 1; 2983 1.1.2.2 skrll else 2984 1.1.2.2 skrll group = 2; 2985 1.1.2.2 skrll 2986 1.1.2.2 skrll /* Get original Tx power based on board type and RF chain. */ 2987 1.1.2.2 skrll if (!(sc->chip & RTWN_CHIP_92C)) { 2988 1.1.2.2 skrll if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2989 1.1.2.2 skrll base = &rtl8188ru_txagc[chain]; 2990 1.1.2.2 skrll else 2991 1.1.2.2 skrll base = &rtl8192cu_txagc[chain]; 2992 1.1.2.2 skrll } else 2993 1.1.2.2 skrll base = &rtl8192cu_txagc[chain]; 2994 1.1.2.2 skrll 2995 1.1.2.2 skrll memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2996 1.1.2.2 skrll if (sc->regulatory == 0) { 2997 1.1.2.2 skrll for (ridx = 0; ridx <= 3; ridx++) 2998 1.1.2.2 skrll power[ridx] = base->pwr[0][ridx]; 2999 1.1.2.2 skrll } 3000 1.1.2.2 skrll for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3001 1.1.2.2 skrll if (sc->regulatory == 3) { 3002 1.1.2.2 skrll power[ridx] = base->pwr[0][ridx]; 3003 1.1.2.2 skrll /* Apply vendor limits. */ 3004 1.1.2.2 skrll if (extc != NULL) 3005 1.1.2.2 skrll max = rom->ht40_max_pwr[group]; 3006 1.1.2.2 skrll else 3007 1.1.2.2 skrll max = rom->ht20_max_pwr[group]; 3008 1.1.2.2 skrll max = (max >> (chain * 4)) & 0xf; 3009 1.1.2.2 skrll if (power[ridx] > max) 3010 1.1.2.2 skrll power[ridx] = max; 3011 1.1.2.2 skrll } else if (sc->regulatory == 1) { 3012 1.1.2.2 skrll if (extc == NULL) 3013 1.1.2.2 skrll power[ridx] = base->pwr[group][ridx]; 3014 1.1.2.2 skrll } else if (sc->regulatory != 2) 3015 1.1.2.2 skrll power[ridx] = base->pwr[0][ridx]; 3016 1.1.2.2 skrll } 3017 1.1.2.2 skrll 3018 1.1.2.2 skrll /* Compute per-CCK rate Tx power. */ 3019 1.1.2.2 skrll cckpow = rom->cck_tx_pwr[chain][group]; 3020 1.1.2.2 skrll for (ridx = 0; ridx <= 3; ridx++) { 3021 1.1.2.2 skrll power[ridx] += cckpow; 3022 1.1.2.2 skrll if (power[ridx] > R92C_MAX_TX_PWR) 3023 1.1.2.2 skrll power[ridx] = R92C_MAX_TX_PWR; 3024 1.1.2.2 skrll } 3025 1.1.2.2 skrll 3026 1.1.2.2 skrll htpow = rom->ht40_1s_tx_pwr[chain][group]; 3027 1.1.2.2 skrll if (sc->ntxchains > 1) { 3028 1.1.2.2 skrll /* Apply reduction for 2 spatial streams. */ 3029 1.1.2.2 skrll diff = rom->ht40_2s_tx_pwr_diff[group]; 3030 1.1.2.2 skrll diff = (diff >> (chain * 4)) & 0xf; 3031 1.1.2.2 skrll htpow = (htpow > diff) ? htpow - diff : 0; 3032 1.1.2.2 skrll } 3033 1.1.2.2 skrll 3034 1.1.2.2 skrll /* Compute per-OFDM rate Tx power. */ 3035 1.1.2.2 skrll diff = rom->ofdm_tx_pwr_diff[group]; 3036 1.1.2.2 skrll diff = (diff >> (chain * 4)) & 0xf; 3037 1.1.2.2 skrll ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3038 1.1.2.2 skrll for (ridx = 4; ridx <= 11; ridx++) { 3039 1.1.2.2 skrll power[ridx] += ofdmpow; 3040 1.1.2.2 skrll if (power[ridx] > R92C_MAX_TX_PWR) 3041 1.1.2.2 skrll power[ridx] = R92C_MAX_TX_PWR; 3042 1.1.2.2 skrll } 3043 1.1.2.2 skrll 3044 1.1.2.2 skrll /* Compute per-MCS Tx power. */ 3045 1.1.2.2 skrll if (extc == NULL) { 3046 1.1.2.2 skrll diff = rom->ht20_tx_pwr_diff[group]; 3047 1.1.2.2 skrll diff = (diff >> (chain * 4)) & 0xf; 3048 1.1.2.2 skrll htpow += diff; /* HT40->HT20 correction. */ 3049 1.1.2.2 skrll } 3050 1.1.2.2 skrll for (ridx = 12; ridx <= 27; ridx++) { 3051 1.1.2.2 skrll power[ridx] += htpow; 3052 1.1.2.2 skrll if (power[ridx] > R92C_MAX_TX_PWR) 3053 1.1.2.2 skrll power[ridx] = R92C_MAX_TX_PWR; 3054 1.1.2.2 skrll } 3055 1.1.2.2 skrll #ifdef RTWN_DEBUG 3056 1.1.2.2 skrll if (rtwn_debug >= 4) { 3057 1.1.2.2 skrll /* Dump per-rate Tx power values. */ 3058 1.1.2.2 skrll printf("Tx power for chain %d:\n", chain); 3059 1.1.2.2 skrll for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3060 1.1.2.2 skrll printf("Rate %d = %u\n", ridx, power[ridx]); 3061 1.1.2.2 skrll } 3062 1.1.2.2 skrll #endif 3063 1.1.2.2 skrll } 3064 1.1.2.2 skrll 3065 1.1.2.2 skrll static void 3066 1.1.2.2 skrll rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3067 1.1.2.2 skrll struct ieee80211_channel *extc) 3068 1.1.2.2 skrll { 3069 1.1.2.2 skrll uint16_t power[RTWN_RIDX_COUNT]; 3070 1.1.2.2 skrll int i; 3071 1.1.2.2 skrll 3072 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3073 1.1.2.2 skrll 3074 1.1.2.2 skrll for (i = 0; i < sc->ntxchains; i++) { 3075 1.1.2.2 skrll /* Compute per-rate Tx power values. */ 3076 1.1.2.2 skrll rtwn_get_txpower(sc, i, c, extc, power); 3077 1.1.2.2 skrll /* Write per-rate Tx power values to hardware. */ 3078 1.1.2.2 skrll rtwn_write_txpower(sc, i, power); 3079 1.1.2.2 skrll } 3080 1.1.2.2 skrll } 3081 1.1.2.2 skrll 3082 1.1.2.2 skrll static void 3083 1.1.2.2 skrll rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3084 1.1.2.2 skrll struct ieee80211_channel *extc) 3085 1.1.2.2 skrll { 3086 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3087 1.1.2.2 skrll u_int chan; 3088 1.1.2.2 skrll int i; 3089 1.1.2.2 skrll 3090 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3091 1.1.2.2 skrll 3092 1.1.2.2 skrll chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3093 1.1.2.2 skrll 3094 1.1.2.2 skrll /* Set Tx power for this new channel. */ 3095 1.1.2.2 skrll rtwn_set_txpower(sc, c, extc); 3096 1.1.2.2 skrll 3097 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) { 3098 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3099 1.1.2.2 skrll RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3100 1.1.2.2 skrll } 3101 1.1.2.2 skrll #ifndef IEEE80211_NO_HT 3102 1.1.2.2 skrll if (extc != NULL) { 3103 1.1.2.2 skrll uint32_t reg; 3104 1.1.2.2 skrll 3105 1.1.2.2 skrll /* Is secondary channel below or above primary? */ 3106 1.1.2.2 skrll int prichlo = c->ic_freq < extc->ic_freq; 3107 1.1.2.2 skrll 3108 1.1.2.2 skrll rtwn_write_1(sc, R92C_BWOPMODE, 3109 1.1.2.2 skrll rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3110 1.1.2.2 skrll 3111 1.1.2.2 skrll reg = rtwn_read_1(sc, R92C_RRSR + 2); 3112 1.1.2.2 skrll reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3113 1.1.2.2 skrll rtwn_write_1(sc, R92C_RRSR + 2, reg); 3114 1.1.2.2 skrll 3115 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3116 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3117 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3118 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3119 1.1.2.2 skrll 3120 1.1.2.2 skrll /* Set CCK side band. */ 3121 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3122 1.1.2.2 skrll reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3123 1.1.2.2 skrll rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3124 1.1.2.2 skrll 3125 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3126 1.1.2.2 skrll reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3127 1.1.2.2 skrll rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3128 1.1.2.2 skrll 3129 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3130 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3131 1.1.2.2 skrll ~R92C_FPGA0_ANAPARAM2_CBW20); 3132 1.1.2.2 skrll 3133 1.1.2.2 skrll reg = rtwn_bb_read(sc, 0x818); 3134 1.1.2.2 skrll reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3135 1.1.2.2 skrll rtwn_bb_write(sc, 0x818, reg); 3136 1.1.2.2 skrll 3137 1.1.2.2 skrll /* Select 40MHz bandwidth. */ 3138 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3139 1.1.2.2 skrll (sc->rf_chnlbw[0] & ~0xfff) | chan); 3140 1.1.2.2 skrll } else 3141 1.1.2.2 skrll #endif 3142 1.1.2.2 skrll { 3143 1.1.2.2 skrll rtwn_write_1(sc, R92C_BWOPMODE, 3144 1.1.2.2 skrll rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3145 1.1.2.2 skrll 3146 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3147 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3148 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3149 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3150 1.1.2.2 skrll 3151 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3152 1.1.2.2 skrll rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3153 1.1.2.2 skrll R92C_FPGA0_ANAPARAM2_CBW20); 3154 1.1.2.2 skrll 3155 1.1.2.2 skrll /* Select 20MHz bandwidth. */ 3156 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3157 1.1.2.2 skrll (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3158 1.1.2.2 skrll } 3159 1.1.2.2 skrll } 3160 1.1.2.2 skrll 3161 1.1.2.2 skrll static void 3162 1.1.2.2 skrll rtwn_iq_calib(struct rtwn_softc *sc) 3163 1.1.2.2 skrll { 3164 1.1.2.2 skrll 3165 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3166 1.1.2.2 skrll 3167 1.1.2.2 skrll /* XXX */ 3168 1.1.2.2 skrll } 3169 1.1.2.2 skrll 3170 1.1.2.2 skrll static void 3171 1.1.2.2 skrll rtwn_lc_calib(struct rtwn_softc *sc) 3172 1.1.2.2 skrll { 3173 1.1.2.2 skrll uint32_t rf_ac[2]; 3174 1.1.2.2 skrll uint8_t txmode; 3175 1.1.2.2 skrll int i; 3176 1.1.2.2 skrll 3177 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3178 1.1.2.2 skrll 3179 1.1.2.2 skrll txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3180 1.1.2.2 skrll if ((txmode & 0x70) != 0) { 3181 1.1.2.2 skrll /* Disable all continuous Tx. */ 3182 1.1.2.2 skrll rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3183 1.1.2.2 skrll 3184 1.1.2.2 skrll /* Set RF mode to standby mode. */ 3185 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) { 3186 1.1.2.2 skrll rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3187 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_AC, 3188 1.1.2.2 skrll RW(rf_ac[i], R92C_RF_AC_MODE, 3189 1.1.2.2 skrll R92C_RF_AC_MODE_STANDBY)); 3190 1.1.2.2 skrll } 3191 1.1.2.2 skrll } else { 3192 1.1.2.2 skrll /* Block all Tx queues. */ 3193 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3194 1.1.2.2 skrll } 3195 1.1.2.2 skrll /* Start calibration. */ 3196 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3197 1.1.2.2 skrll rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3198 1.1.2.2 skrll 3199 1.1.2.2 skrll /* Give calibration the time to complete. */ 3200 1.1.2.2 skrll DELAY(100); 3201 1.1.2.2 skrll 3202 1.1.2.2 skrll /* Restore configuration. */ 3203 1.1.2.2 skrll if ((txmode & 0x70) != 0) { 3204 1.1.2.2 skrll /* Restore Tx mode. */ 3205 1.1.2.2 skrll rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3206 1.1.2.2 skrll /* Restore RF mode. */ 3207 1.1.2.2 skrll for (i = 0; i < sc->nrxchains; i++) 3208 1.1.2.2 skrll rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3209 1.1.2.2 skrll } else { 3210 1.1.2.2 skrll /* Unblock all Tx queues. */ 3211 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3212 1.1.2.2 skrll } 3213 1.1.2.2 skrll } 3214 1.1.2.2 skrll 3215 1.1.2.2 skrll static void 3216 1.1.2.2 skrll rtwn_temp_calib(struct rtwn_softc *sc) 3217 1.1.2.2 skrll { 3218 1.1.2.2 skrll int temp; 3219 1.1.2.2 skrll 3220 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3221 1.1.2.2 skrll 3222 1.1.2.2 skrll if (sc->thcal_state == 0) { 3223 1.1.2.2 skrll /* Start measuring temperature. */ 3224 1.1.2.2 skrll rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3225 1.1.2.2 skrll sc->thcal_state = 1; 3226 1.1.2.2 skrll return; 3227 1.1.2.2 skrll } 3228 1.1.2.2 skrll sc->thcal_state = 0; 3229 1.1.2.2 skrll 3230 1.1.2.2 skrll /* Read measured temperature. */ 3231 1.1.2.2 skrll temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3232 1.1.2.2 skrll if (temp == 0) /* Read failed, skip. */ 3233 1.1.2.2 skrll return; 3234 1.1.2.2 skrll DPRINTFN(2, ("temperature=%d\n", temp)); 3235 1.1.2.2 skrll 3236 1.1.2.2 skrll /* 3237 1.1.2.2 skrll * Redo IQ and LC calibration if temperature changed significantly 3238 1.1.2.2 skrll * since last calibration. 3239 1.1.2.2 skrll */ 3240 1.1.2.2 skrll if (sc->thcal_lctemp == 0) { 3241 1.1.2.2 skrll /* First calibration is performed in rtwn_init(). */ 3242 1.1.2.2 skrll sc->thcal_lctemp = temp; 3243 1.1.2.2 skrll } else if (abs(temp - sc->thcal_lctemp) > 1) { 3244 1.1.2.2 skrll DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3245 1.1.2.2 skrll sc->thcal_lctemp, temp)); 3246 1.1.2.2 skrll rtwn_iq_calib(sc); 3247 1.1.2.2 skrll rtwn_lc_calib(sc); 3248 1.1.2.2 skrll /* Record temperature of last calibration. */ 3249 1.1.2.2 skrll sc->thcal_lctemp = temp; 3250 1.1.2.2 skrll } 3251 1.1.2.2 skrll } 3252 1.1.2.2 skrll 3253 1.1.2.2 skrll static int 3254 1.1.2.2 skrll rtwn_init(struct ifnet *ifp) 3255 1.1.2.2 skrll { 3256 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 3257 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3258 1.1.2.2 skrll uint32_t reg; 3259 1.1.2.2 skrll int i, error; 3260 1.1.2.2 skrll 3261 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3262 1.1.2.2 skrll 3263 1.1.2.2 skrll /* Init firmware commands ring. */ 3264 1.1.2.2 skrll sc->fwcur = 0; 3265 1.1.2.2 skrll 3266 1.1.2.2 skrll /* Power on adapter. */ 3267 1.1.2.2 skrll error = rtwn_power_on(sc); 3268 1.1.2.2 skrll if (error != 0) { 3269 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3270 1.1.2.2 skrll goto fail; 3271 1.1.2.2 skrll } 3272 1.1.2.2 skrll 3273 1.1.2.2 skrll /* Initialize DMA. */ 3274 1.1.2.2 skrll error = rtwn_dma_init(sc); 3275 1.1.2.2 skrll if (error != 0) { 3276 1.1.2.2 skrll aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3277 1.1.2.2 skrll goto fail; 3278 1.1.2.2 skrll } 3279 1.1.2.2 skrll 3280 1.1.2.2 skrll /* Set info size in Rx descriptors (in 64-bit words). */ 3281 1.1.2.2 skrll rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3282 1.1.2.2 skrll 3283 1.1.2.2 skrll /* Disable interrupts. */ 3284 1.1.2.2 skrll rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3285 1.1.2.2 skrll rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3286 1.1.2.2 skrll 3287 1.1.2.2 skrll /* Set MAC address. */ 3288 1.1.2.2 skrll IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3289 1.1.2.2 skrll for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3290 1.1.2.2 skrll rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3291 1.1.2.2 skrll 3292 1.1.2.2 skrll /* Set initial network type. */ 3293 1.1.2.2 skrll rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3294 1.1.2.2 skrll 3295 1.1.2.2 skrll rtwn_rxfilter_init(sc); 3296 1.1.2.2 skrll 3297 1.1.2.2 skrll reg = rtwn_read_4(sc, R92C_RRSR); 3298 1.1.2.2 skrll reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3299 1.1.2.2 skrll rtwn_write_4(sc, R92C_RRSR, reg); 3300 1.1.2.2 skrll 3301 1.1.2.2 skrll /* Set short/long retry limits. */ 3302 1.1.2.2 skrll rtwn_write_2(sc, R92C_RL, 3303 1.1.2.2 skrll SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3304 1.1.2.2 skrll 3305 1.1.2.2 skrll /* Initialize EDCA parameters. */ 3306 1.1.2.2 skrll rtwn_edca_init(sc); 3307 1.1.2.2 skrll 3308 1.1.2.2 skrll /* Set data and response automatic rate fallback retry counts. */ 3309 1.1.2.2 skrll rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3310 1.1.2.2 skrll rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3311 1.1.2.2 skrll rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3312 1.1.2.2 skrll rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3313 1.1.2.2 skrll 3314 1.1.2.2 skrll rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3315 1.1.2.2 skrll 3316 1.1.2.2 skrll /* Set ACK timeout. */ 3317 1.1.2.2 skrll rtwn_write_1(sc, R92C_ACKTO, 0x40); 3318 1.1.2.2 skrll 3319 1.1.2.2 skrll /* Initialize beacon parameters. */ 3320 1.1.2.2 skrll rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3321 1.1.2.2 skrll rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3322 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3323 1.1.2.2 skrll rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3324 1.1.2.2 skrll 3325 1.1.2.2 skrll /* Setup AMPDU aggregation. */ 3326 1.1.2.2 skrll rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3327 1.1.2.2 skrll rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3328 1.1.2.2 skrll 3329 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3330 1.1.2.2 skrll rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3331 1.1.2.2 skrll 3332 1.1.2.2 skrll rtwn_write_4(sc, R92C_PIFS, 0x1c); 3333 1.1.2.2 skrll rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3334 1.1.2.2 skrll 3335 1.1.2.2 skrll /* Load 8051 microcode. */ 3336 1.1.2.2 skrll error = rtwn_load_firmware(sc); 3337 1.1.2.2 skrll if (error != 0) 3338 1.1.2.2 skrll goto fail; 3339 1.1.2.2 skrll 3340 1.1.2.2 skrll /* Initialize MAC/BB/RF blocks. */ 3341 1.1.2.2 skrll rtwn_mac_init(sc); 3342 1.1.2.2 skrll rtwn_bb_init(sc); 3343 1.1.2.2 skrll rtwn_rf_init(sc); 3344 1.1.2.2 skrll 3345 1.1.2.2 skrll /* Turn CCK and OFDM blocks on. */ 3346 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3347 1.1.2.2 skrll reg |= R92C_RFMOD_CCK_EN; 3348 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3349 1.1.2.2 skrll reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3350 1.1.2.2 skrll reg |= R92C_RFMOD_OFDM_EN; 3351 1.1.2.2 skrll rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3352 1.1.2.2 skrll 3353 1.1.2.2 skrll /* Clear per-station keys table. */ 3354 1.1.2.2 skrll rtwn_cam_init(sc); 3355 1.1.2.2 skrll 3356 1.1.2.2 skrll /* Enable hardware sequence numbering. */ 3357 1.1.2.2 skrll rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3358 1.1.2.2 skrll 3359 1.1.2.2 skrll /* Perform LO and IQ calibrations. */ 3360 1.1.2.2 skrll rtwn_iq_calib(sc); 3361 1.1.2.2 skrll /* Perform LC calibration. */ 3362 1.1.2.2 skrll rtwn_lc_calib(sc); 3363 1.1.2.2 skrll 3364 1.1.2.2 skrll rtwn_pa_bias_init(sc); 3365 1.1.2.2 skrll 3366 1.1.2.2 skrll /* Initialize GPIO setting. */ 3367 1.1.2.2 skrll rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3368 1.1.2.2 skrll rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3369 1.1.2.2 skrll 3370 1.1.2.2 skrll /* Fix for lower temperature. */ 3371 1.1.2.2 skrll rtwn_write_1(sc, 0x15, 0xe9); 3372 1.1.2.2 skrll 3373 1.1.2.2 skrll /* Set default channel. */ 3374 1.1.2.2 skrll rtwn_set_chan(sc, ic->ic_curchan, NULL); 3375 1.1.2.2 skrll 3376 1.1.2.2 skrll /* Clear pending interrupts. */ 3377 1.1.2.2 skrll rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3378 1.1.2.2 skrll 3379 1.1.2.2 skrll /* Enable interrupts. */ 3380 1.1.2.2 skrll rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3381 1.1.2.2 skrll 3382 1.1.2.2 skrll /* We're ready to go. */ 3383 1.1.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 3384 1.1.2.2 skrll ifp->if_flags |= IFF_RUNNING; 3385 1.1.2.2 skrll 3386 1.1.2.2 skrll if (ic->ic_opmode == IEEE80211_M_MONITOR) 3387 1.1.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3388 1.1.2.2 skrll else 3389 1.1.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3390 1.1.2.2 skrll 3391 1.1.2.2 skrll return 0; 3392 1.1.2.2 skrll 3393 1.1.2.2 skrll fail: 3394 1.1.2.2 skrll rtwn_stop(ifp, 1); 3395 1.1.2.2 skrll return error; 3396 1.1.2.2 skrll } 3397 1.1.2.2 skrll 3398 1.1.2.2 skrll static void 3399 1.1.2.2 skrll rtwn_init_task(void *arg) 3400 1.1.2.2 skrll { 3401 1.1.2.2 skrll struct rtwn_softc *sc = arg; 3402 1.1.2.2 skrll struct ifnet *ifp = GET_IFP(sc); 3403 1.1.2.2 skrll int s; 3404 1.1.2.2 skrll 3405 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3406 1.1.2.2 skrll 3407 1.1.2.2 skrll s = splnet(); 3408 1.1.2.2 skrll 3409 1.1.2.2 skrll rtwn_stop(ifp, 0); 3410 1.1.2.2 skrll 3411 1.1.2.2 skrll if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3412 1.1.2.2 skrll rtwn_init(ifp); 3413 1.1.2.2 skrll 3414 1.1.2.2 skrll splx(s); 3415 1.1.2.2 skrll } 3416 1.1.2.2 skrll 3417 1.1.2.2 skrll static void 3418 1.1.2.2 skrll rtwn_stop(struct ifnet *ifp, int disable) 3419 1.1.2.2 skrll { 3420 1.1.2.2 skrll struct rtwn_softc *sc = ifp->if_softc; 3421 1.1.2.2 skrll struct ieee80211com *ic = &sc->sc_ic; 3422 1.1.2.2 skrll uint16_t reg; 3423 1.1.2.2 skrll int s, i; 3424 1.1.2.2 skrll 3425 1.1.2.2 skrll DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3426 1.1.2.2 skrll 3427 1.1.2.2 skrll sc->sc_tx_timer = 0; 3428 1.1.2.2 skrll ifp->if_timer = 0; 3429 1.1.2.2 skrll ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3430 1.1.2.2 skrll 3431 1.1.2.2 skrll callout_stop(&sc->scan_to); 3432 1.1.2.2 skrll callout_stop(&sc->calib_to); 3433 1.1.2.2 skrll 3434 1.1.2.2 skrll s = splnet(); 3435 1.1.2.2 skrll 3436 1.1.2.2 skrll ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3437 1.1.2.2 skrll 3438 1.1.2.2 skrll /* Disable interrupts. */ 3439 1.1.2.2 skrll rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3440 1.1.2.2 skrll 3441 1.1.2.2 skrll /* Pause MAC TX queue */ 3442 1.1.2.2 skrll rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3443 1.1.2.2 skrll 3444 1.1.2.2 skrll rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3445 1.1.2.2 skrll 3446 1.1.2.2 skrll /* Reset BB state machine */ 3447 1.1.2.2 skrll reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3448 1.1.2.2 skrll reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3449 1.1.2.2 skrll rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3450 1.1.2.2 skrll reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3451 1.1.2.2 skrll rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3452 1.1.2.2 skrll 3453 1.1.2.2 skrll reg = rtwn_read_2(sc, R92C_CR); 3454 1.1.2.2 skrll reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3455 1.1.2.2 skrll R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3456 1.1.2.2 skrll R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3457 1.1.2.2 skrll R92C_CR_ENSEC); 3458 1.1.2.2 skrll rtwn_write_2(sc, R92C_CR, reg); 3459 1.1.2.2 skrll 3460 1.1.2.2 skrll if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3461 1.1.2.2 skrll rtwn_fw_reset(sc); 3462 1.1.2.2 skrll 3463 1.1.2.2 skrll /* Reset MAC and Enable 8051 */ 3464 1.1.2.2 skrll rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3465 1.1.2.2 skrll 3466 1.1.2.2 skrll /* TODO: linux does additional btcoex stuff here */ 3467 1.1.2.2 skrll 3468 1.1.2.2 skrll /* Disable AFE PLL */ 3469 1.1.2.2 skrll rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3470 1.1.2.2 skrll /* Enter PFM mode */ 3471 1.1.2.2 skrll rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3472 1.1.2.2 skrll /* Gated AFE DIG_CLOCK */ 3473 1.1.2.2 skrll rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3474 1.1.2.2 skrll rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3475 1.1.2.2 skrll rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3476 1.1.2.2 skrll 3477 1.1.2.2 skrll for (i = 0; i < RTWN_NTXQUEUES; i++) 3478 1.1.2.2 skrll rtwn_reset_tx_list(sc, i); 3479 1.1.2.2 skrll rtwn_reset_rx_list(sc); 3480 1.1.2.2 skrll 3481 1.1.2.2 skrll splx(s); 3482 1.1.2.2 skrll } 3483 1.1.2.2 skrll 3484 1.1.2.2 skrll static int 3485 1.1.2.2 skrll rtwn_intr(void *xsc) 3486 1.1.2.2 skrll { 3487 1.1.2.2 skrll struct rtwn_softc *sc = xsc; 3488 1.1.2.2 skrll uint32_t status; 3489 1.1.2.2 skrll int i; 3490 1.1.2.2 skrll 3491 1.1.2.2 skrll if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3492 1.1.2.2 skrll return 0; 3493 1.1.2.2 skrll 3494 1.1.2.2 skrll status = rtwn_read_4(sc, R92C_HISR); 3495 1.1.2.2 skrll if (status == 0 || status == 0xffffffff) 3496 1.1.2.2 skrll return 0; 3497 1.1.2.2 skrll 3498 1.1.2.2 skrll /* Disable interrupts. */ 3499 1.1.2.2 skrll rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3500 1.1.2.2 skrll 3501 1.1.2.2 skrll /* Ack interrupts. */ 3502 1.1.2.2 skrll rtwn_write_4(sc, R92C_HISR, status); 3503 1.1.2.2 skrll 3504 1.1.2.2 skrll /* Vendor driver treats RX errors like ROK... */ 3505 1.1.2.2 skrll if (status & RTWN_INT_ENABLE_RX) { 3506 1.1.2.2 skrll for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3507 1.1.2.2 skrll struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3508 1.1.2.2 skrll struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3509 1.1.2.2 skrll 3510 1.1.2.2 skrll if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3511 1.1.2.2 skrll continue; 3512 1.1.2.2 skrll 3513 1.1.2.2 skrll rtwn_rx_frame(sc, rx_desc, rx_data, i); 3514 1.1.2.2 skrll } 3515 1.1.2.2 skrll } 3516 1.1.2.2 skrll 3517 1.1.2.2 skrll if (status & R92C_IMR_BDOK) 3518 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3519 1.1.2.2 skrll if (status & R92C_IMR_HIGHDOK) 3520 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3521 1.1.2.2 skrll if (status & R92C_IMR_MGNTDOK) 3522 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3523 1.1.2.2 skrll if (status & R92C_IMR_BKDOK) 3524 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_BK_QUEUE); 3525 1.1.2.2 skrll if (status & R92C_IMR_BEDOK) 3526 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_BE_QUEUE); 3527 1.1.2.2 skrll if (status & R92C_IMR_VIDOK) 3528 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_VI_QUEUE); 3529 1.1.2.2 skrll if (status & R92C_IMR_VODOK) 3530 1.1.2.2 skrll rtwn_tx_done(sc, RTWN_VO_QUEUE); 3531 1.1.2.2 skrll if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3532 1.1.2.2 skrll struct ifnet *ifp = GET_IFP(sc); 3533 1.1.2.2 skrll ifp->if_flags &= ~IFF_OACTIVE; 3534 1.1.2.2 skrll rtwn_start(ifp); 3535 1.1.2.2 skrll } 3536 1.1.2.2 skrll 3537 1.1.2.2 skrll /* Enable interrupts. */ 3538 1.1.2.2 skrll rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3539 1.1.2.2 skrll 3540 1.1.2.2 skrll return 1; 3541 1.1.2.2 skrll } 3542
Indexes created Thu Oct 02 01:09:59 GMT 2025