if_rtwn.c revision 1.1
1 /* $NetBSD: if_rtwn.c,v 1.1 2015/08/27 14:04:08 nonaka Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.1 2015/08/27 14:04:08 nonaka Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 178 /* Aliases. */ 179 #define rtwn_bb_write rtwn_write_4 180 #define rtwn_bb_read rtwn_read_4 181 182 static const struct rtwn_device * 183 rtwn_lookup(const struct pci_attach_args *pa) 184 { 185 const struct rtwn_device *rd; 186 int i; 187 188 for (i = 0; i < __arraycount(rtwn_devices); i++) { 189 rd = &rtwn_devices[i]; 190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 191 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 192 return rd; 193 } 194 return NULL; 195 } 196 197 static int 198 rtwn_match(device_t parent, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 202 if (rtwn_lookup(pa) != NULL) 203 return 1; 204 return 0; 205 } 206 207 static void 208 rtwn_attach(device_t parent, device_t self, void *aux) 209 { 210 struct rtwn_softc *sc = device_private(self); 211 struct pci_attach_args *pa = aux; 212 struct ieee80211com *ic = &sc->sc_ic; 213 struct ifnet *ifp = GET_IFP(sc); 214 int i, error; 215 pcireg_t memtype; 216 #ifndef __HAVE_PCI_MSI_MSIX 217 pci_intr_handle_t ih; 218 #endif 219 const char *intrstr; 220 char intrbuf[PCI_INTRSTR_LEN]; 221 222 sc->sc_dev = self; 223 sc->sc_dmat = pa->pa_dmat; 224 sc->sc_pc = pa->pa_pc; 225 sc->sc_tag = pa->pa_tag; 226 227 pci_aprint_devinfo(pa, NULL); 228 229 callout_init(&sc->scan_to, 0); 230 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 231 callout_init(&sc->calib_to, 0); 232 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 233 234 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 235 236 /* Power up the device */ 237 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 238 239 /* Map control/status registers. */ 240 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 241 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 242 &sc->sc_sh, NULL, &sc->sc_mapsize); 243 if (error != 0) { 244 aprint_error_dev(self, "can't map mem space\n"); 245 return; 246 } 247 248 /* Install interrupt handler. */ 249 #ifdef __HAVE_PCI_MSI_MSIX 250 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 251 aprint_error_dev(self, "can't map interrupt\n"); 252 return; 253 } 254 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 255 sizeof(intrbuf)); 256 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 257 rtwn_intr, sc); 258 #else /* !__HAVE_PCI_MSI_MSIX */ 259 if (pci_intr_map(pa, &ih)) { 260 aprint_error_dev(self, "can't map interrupt\n"); 261 return; 262 } 263 intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf)); 264 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, rtwn_intr, sc); 265 #endif /* __HAVE_PCI_MSI_MSIX */ 266 if (sc->sc_ih == NULL) { 267 aprint_error_dev(self, "can't establish interrupt"); 268 if (intrstr != NULL) 269 aprint_error(" at %s", intrstr); 270 aprint_error("\n"); 271 return; 272 } 273 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 274 275 error = rtwn_read_chipid(sc); 276 if (error != 0) { 277 aprint_error_dev(self, "unsupported test or unknown chip\n"); 278 return; 279 } 280 281 /* Disable PCIe Active State Power Management (ASPM). */ 282 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 283 &sc->sc_cap_off, NULL)) { 284 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 285 sc->sc_cap_off + PCIE_LCSR); 286 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 287 pci_conf_write(sc->sc_pc, sc->sc_tag, 288 sc->sc_cap_off + PCIE_LCSR, lcsr); 289 } 290 291 /* Allocate Tx/Rx buffers. */ 292 error = rtwn_alloc_rx_list(sc); 293 if (error != 0) { 294 aprint_error_dev(self, "could not allocate Rx buffers\n"); 295 return; 296 } 297 for (i = 0; i < RTWN_NTXQUEUES; i++) { 298 error = rtwn_alloc_tx_list(sc, i); 299 if (error != 0) { 300 aprint_error_dev(self, 301 "could not allocate Tx buffers\n"); 302 return; 303 } 304 } 305 306 /* Determine number of Tx/Rx chains. */ 307 if (sc->chip & RTWN_CHIP_92C) { 308 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 309 sc->nrxchains = 2; 310 } else { 311 sc->ntxchains = 1; 312 sc->nrxchains = 1; 313 } 314 rtwn_read_rom(sc); 315 316 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 317 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 318 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 319 320 /* 321 * Setup the 802.11 device. 322 */ 323 ic->ic_ifp = ifp; 324 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 325 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 326 ic->ic_state = IEEE80211_S_INIT; 327 328 /* Set device capabilities. */ 329 ic->ic_caps = 330 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 331 IEEE80211_C_IBSS | /* IBSS mode supported */ 332 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 333 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 334 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 335 IEEE80211_C_WME | /* 802.11e */ 336 IEEE80211_C_WPA; /* WPA/RSN. */ 337 338 #ifndef IEEE80211_NO_HT 339 /* Set HT capabilities. */ 340 ic->ic_htcaps = 341 IEEE80211_HTCAP_CBW20_40 | 342 IEEE80211_HTCAP_DSSSCCK40; 343 /* Set supported HT rates. */ 344 for (i = 0; i < sc->nrxchains; i++) 345 ic->ic_sup_mcs[i] = 0xff; 346 #endif 347 348 /* Set supported .11b and .11g rates. */ 349 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 350 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 351 352 /* Set supported .11b and .11g channels (1 through 14). */ 353 for (i = 1; i <= 14; i++) { 354 ic->ic_channels[i].ic_freq = 355 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 356 ic->ic_channels[i].ic_flags = 357 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 358 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 359 } 360 361 ifp->if_softc = sc; 362 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 363 ifp->if_init = rtwn_init; 364 ifp->if_ioctl = rtwn_ioctl; 365 ifp->if_start = rtwn_start; 366 ifp->if_watchdog = rtwn_watchdog; 367 IFQ_SET_READY(&ifp->if_snd); 368 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 369 370 if_initialize(ifp); 371 ieee80211_ifattach(ic); 372 if_register(ifp); 373 374 /* override default methods */ 375 ic->ic_newassoc = rtwn_newassoc; 376 ic->ic_reset = rtwn_reset; 377 ic->ic_wme.wme_update = rtwn_wme_update; 378 379 /* Override state transition machine. */ 380 sc->sc_newstate = ic->ic_newstate; 381 ic->ic_newstate = rtwn_newstate; 382 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 383 384 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 385 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 386 &sc->sc_drvbpf); 387 388 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 391 392 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 394 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 395 396 ieee80211_announce(ic); 397 398 if (!pmf_device_register(self, NULL, NULL)) 399 aprint_error_dev(self, "couldn't establish power handler\n"); 400 } 401 402 static int 403 rtwn_detach(device_t self, int flags) 404 { 405 struct rtwn_softc *sc = device_private(self); 406 struct ieee80211com *ic = &sc->sc_ic; 407 struct ifnet *ifp = GET_IFP(sc); 408 int s, i; 409 410 callout_stop(&sc->scan_to); 411 callout_stop(&sc->calib_to); 412 413 s = splnet(); 414 415 if (ifp->if_softc != NULL) { 416 rtwn_stop(ifp, 0); 417 418 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 419 bpf_detach(ifp); 420 ieee80211_ifdetach(ic); 421 if_detach(ifp); 422 } 423 424 /* Free Tx/Rx buffers. */ 425 for (i = 0; i < RTWN_NTXQUEUES; i++) 426 rtwn_free_tx_list(sc, i); 427 rtwn_free_rx_list(sc); 428 429 splx(s); 430 431 callout_destroy(&sc->scan_to); 432 callout_destroy(&sc->calib_to); 433 434 if (sc->init_task != NULL) 435 softint_disestablish(sc->init_task); 436 437 if (sc->sc_ih != NULL) { 438 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 439 #ifdef __HAVE_PCI_MSI_MSIX 440 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 441 #endif 442 } 443 444 pmf_device_deregister(self); 445 446 return 0; 447 } 448 449 static int 450 rtwn_activate(device_t self, enum devact act) 451 { 452 struct rtwn_softc *sc = device_private(self); 453 struct ifnet *ifp = GET_IFP(sc); 454 455 switch (act) { 456 case DVACT_DEACTIVATE: 457 if (ifp->if_flags & IFF_RUNNING) 458 rtwn_stop(ifp, 0); 459 return 0; 460 default: 461 return EOPNOTSUPP; 462 } 463 } 464 465 static void 466 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 467 bus_addr_t addr, size_t len, int idx) 468 { 469 470 memset(desc, 0, sizeof(*desc)); 471 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 472 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 473 desc->rxbufaddr = htole32(addr); 474 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 475 BUS_SPACE_BARRIER_WRITE); 476 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 477 } 478 479 static int 480 rtwn_alloc_rx_list(struct rtwn_softc *sc) 481 { 482 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 483 struct rtwn_rx_data *rx_data; 484 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 485 int i, error = 0; 486 487 /* Allocate Rx descriptors. */ 488 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 489 &rx_ring->map); 490 if (error != 0) { 491 aprint_error_dev(sc->sc_dev, 492 "could not create rx desc DMA map\n"); 493 rx_ring->map = NULL; 494 goto fail; 495 } 496 497 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 498 &rx_ring->nsegs, BUS_DMA_NOWAIT); 499 if (error != 0) { 500 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 501 goto fail; 502 } 503 504 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 505 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 506 if (error != 0) { 507 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 508 rx_ring->desc = NULL; 509 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 510 goto fail; 511 } 512 memset(rx_ring->desc, 0, size); 513 514 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 515 1, size, BUS_DMA_NOWAIT); 516 if (error != 0) { 517 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 518 goto fail; 519 } 520 521 /* Allocate Rx buffers. */ 522 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 523 rx_data = &rx_ring->rx_data[i]; 524 525 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 526 0, BUS_DMA_NOWAIT, &rx_data->map); 527 if (error != 0) { 528 aprint_error_dev(sc->sc_dev, 529 "could not create rx buf DMA map\n"); 530 goto fail; 531 } 532 533 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 534 if (__predict_false(rx_data->m == NULL)) { 535 aprint_error_dev(sc->sc_dev, 536 "couldn't allocate rx mbuf\n"); 537 error = ENOMEM; 538 goto fail; 539 } 540 MCLGET(rx_data->m, M_DONTWAIT); 541 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 542 aprint_error_dev(sc->sc_dev, 543 "couldn't allocate rx mbuf cluster\n"); 544 m_free(rx_data->m); 545 rx_data->m = NULL; 546 error = ENOMEM; 547 goto fail; 548 } 549 550 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 551 mtod(rx_data->m, void *), MCLBYTES, NULL, 552 BUS_DMA_NOWAIT | BUS_DMA_READ); 553 if (error != 0) { 554 aprint_error_dev(sc->sc_dev, 555 "could not load rx buf DMA map\n"); 556 goto fail; 557 } 558 559 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 560 BUS_DMASYNC_PREREAD); 561 562 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 563 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 564 } 565 fail: if (error != 0) 566 rtwn_free_rx_list(sc); 567 return error; 568 } 569 570 static void 571 rtwn_reset_rx_list(struct rtwn_softc *sc) 572 { 573 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 574 struct rtwn_rx_data *rx_data; 575 int i; 576 577 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 578 rx_data = &rx_ring->rx_data[i]; 579 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 580 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 581 } 582 } 583 584 static void 585 rtwn_free_rx_list(struct rtwn_softc *sc) 586 { 587 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 588 struct rtwn_rx_data *rx_data; 589 int i, s; 590 591 s = splnet(); 592 593 if (rx_ring->map) { 594 if (rx_ring->desc) { 595 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 596 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 597 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 598 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 599 rx_ring->nsegs); 600 rx_ring->desc = NULL; 601 } 602 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 603 rx_ring->map = NULL; 604 } 605 606 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 607 rx_data = &rx_ring->rx_data[i]; 608 609 if (rx_data->m != NULL) { 610 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 611 m_freem(rx_data->m); 612 rx_data->m = NULL; 613 } 614 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 615 rx_data->map = NULL; 616 } 617 618 splx(s); 619 } 620 621 static int 622 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 623 { 624 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 625 struct rtwn_tx_data *tx_data; 626 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 627 int i = 0, error = 0; 628 629 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 630 &tx_ring->map); 631 if (error != 0) { 632 aprint_error_dev(sc->sc_dev, 633 "could not create tx ring DMA map\n"); 634 goto fail; 635 } 636 637 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 638 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 639 if (error != 0) { 640 aprint_error_dev(sc->sc_dev, 641 "could not allocate tx ring DMA memory\n"); 642 goto fail; 643 } 644 645 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 646 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 647 if (error != 0) { 648 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 649 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 650 goto fail; 651 } 652 memset(tx_ring->desc, 0, size); 653 654 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 655 size, NULL, BUS_DMA_NOWAIT); 656 if (error != 0) { 657 aprint_error_dev(sc->sc_dev, 658 "could not load tx ring DMA map\n"); 659 goto fail; 660 } 661 662 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 663 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 664 665 /* setup tx desc */ 666 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 667 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 668 669 tx_data = &tx_ring->tx_data[i]; 670 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 671 0, BUS_DMA_NOWAIT, &tx_data->map); 672 if (error != 0) { 673 aprint_error_dev(sc->sc_dev, 674 "could not create tx buf DMA map\n"); 675 goto fail; 676 } 677 tx_data->m = NULL; 678 tx_data->ni = NULL; 679 } 680 681 fail: 682 if (error != 0) 683 rtwn_free_tx_list(sc, qid); 684 return error; 685 } 686 687 static void 688 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 689 { 690 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 691 int i; 692 693 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 694 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 695 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 696 697 memset(desc, 0, sizeof(*desc) - 698 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 699 sizeof(desc->nextdescaddr))); 700 701 if (tx_data->m != NULL) { 702 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 703 m_freem(tx_data->m); 704 tx_data->m = NULL; 705 ieee80211_free_node(tx_data->ni); 706 tx_data->ni = NULL; 707 } 708 } 709 710 sc->qfullmsk &= ~(1 << qid); 711 tx_ring->queued = 0; 712 tx_ring->cur = 0; 713 } 714 715 static void 716 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 717 { 718 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 719 struct rtwn_tx_data *tx_data; 720 int i; 721 722 if (tx_ring->map != NULL) { 723 if (tx_ring->desc != NULL) { 724 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 725 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 726 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 727 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 728 tx_ring->nsegs); 729 } 730 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 731 } 732 733 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 734 tx_data = &tx_ring->tx_data[i]; 735 736 if (tx_data->m != NULL) { 737 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 738 m_freem(tx_data->m); 739 tx_data->m = NULL; 740 } 741 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 742 } 743 744 sc->qfullmsk &= ~(1 << qid); 745 tx_ring->queued = 0; 746 tx_ring->cur = 0; 747 } 748 749 static void 750 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 751 { 752 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 753 } 754 755 static void 756 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 757 { 758 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 759 } 760 761 static void 762 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 763 { 764 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 765 } 766 767 static uint8_t 768 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 769 { 770 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 771 } 772 773 static uint16_t 774 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 775 { 776 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 777 } 778 779 static uint32_t 780 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 781 { 782 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 783 } 784 785 static int 786 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 787 { 788 struct r92c_fw_cmd cmd; 789 uint8_t *cp; 790 int fwcur; 791 int ntries; 792 793 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 794 device_xname(sc->sc_dev), __func__, id, buf, len)); 795 796 fwcur = sc->fwcur; 797 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 798 799 /* Wait for current FW box to be empty. */ 800 for (ntries = 0; ntries < 100; ntries++) { 801 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 802 break; 803 DELAY(1); 804 } 805 if (ntries == 100) { 806 aprint_error_dev(sc->sc_dev, 807 "could not send firmware command %d\n", id); 808 return ETIMEDOUT; 809 } 810 811 memset(&cmd, 0, sizeof(cmd)); 812 KASSERT(len <= sizeof(cmd.msg)); 813 memcpy(cmd.msg, buf, len); 814 815 /* Write the first word last since that will trigger the FW. */ 816 cp = (uint8_t *)&cmd; 817 if (len >= 4) { 818 cmd.id = id | R92C_CMD_FLAG_EXT; 819 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 820 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 821 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 822 } else { 823 cmd.id = id; 824 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 825 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 826 } 827 828 /* Give firmware some time for processing. */ 829 DELAY(2000); 830 831 return 0; 832 } 833 834 static void 835 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 836 { 837 838 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 839 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 840 } 841 842 static uint32_t 843 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 844 { 845 uint32_t reg[R92C_MAX_CHAINS], val; 846 847 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 848 if (chain != 0) 849 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 850 851 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 852 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 853 DELAY(1000); 854 855 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 856 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 857 R92C_HSSI_PARAM2_READ_EDGE); 858 DELAY(1000); 859 860 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 861 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 862 DELAY(1000); 863 864 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 865 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 866 else 867 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 868 return MS(val, R92C_LSSI_READBACK_DATA); 869 } 870 871 static int 872 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 873 { 874 int ntries; 875 876 rtwn_write_4(sc, R92C_LLT_INIT, 877 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 878 SM(R92C_LLT_INIT_ADDR, addr) | 879 SM(R92C_LLT_INIT_DATA, data)); 880 /* Wait for write operation to complete. */ 881 for (ntries = 0; ntries < 20; ntries++) { 882 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 883 R92C_LLT_INIT_OP_NO_ACTIVE) 884 return 0; 885 DELAY(5); 886 } 887 return ETIMEDOUT; 888 } 889 890 static uint8_t 891 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 892 { 893 uint32_t reg; 894 int ntries; 895 896 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 897 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 898 reg &= ~R92C_EFUSE_CTRL_VALID; 899 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 900 /* Wait for read operation to complete. */ 901 for (ntries = 0; ntries < 100; ntries++) { 902 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 903 if (reg & R92C_EFUSE_CTRL_VALID) 904 return MS(reg, R92C_EFUSE_CTRL_DATA); 905 DELAY(5); 906 } 907 aprint_error_dev(sc->sc_dev, 908 "could not read efuse byte at address 0x%x\n", addr); 909 return 0xff; 910 } 911 912 static void 913 rtwn_efuse_read(struct rtwn_softc *sc) 914 { 915 uint8_t *rom = (uint8_t *)&sc->rom; 916 uint32_t reg; 917 uint16_t addr = 0; 918 uint8_t off, msk; 919 int i; 920 921 rtwn_efuse_switch_power(sc); 922 923 memset(&sc->rom, 0xff, sizeof(sc->rom)); 924 while (addr < 512) { 925 reg = rtwn_efuse_read_1(sc, addr); 926 if (reg == 0xff) 927 break; 928 addr++; 929 off = reg >> 4; 930 msk = reg & 0xf; 931 for (i = 0; i < 4; i++) { 932 if (msk & (1 << i)) 933 continue; 934 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 935 addr++; 936 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 937 addr++; 938 } 939 } 940 #ifdef RTWN_DEBUG 941 if (rtwn_debug >= 2) { 942 /* Dump ROM content. */ 943 printf("\n"); 944 for (i = 0; i < sizeof(sc->rom); i++) 945 printf("%02x:", rom[i]); 946 printf("\n"); 947 } 948 #endif 949 } 950 951 static void 952 rtwn_efuse_switch_power(struct rtwn_softc *sc) 953 { 954 uint32_t reg; 955 956 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 957 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 958 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 959 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 960 } 961 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 962 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 963 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 964 reg | R92C_SYS_FUNC_EN_ELDR); 965 } 966 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 967 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 968 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 969 rtwn_write_2(sc, R92C_SYS_CLKR, 970 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 971 } 972 } 973 974 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 975 static int 976 rtwn_read_chipid(struct rtwn_softc *sc) 977 { 978 uint32_t reg; 979 980 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 981 982 reg = rtwn_read_4(sc, R92C_SYS_CFG); 983 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 984 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 985 /* Unsupported test chip. */ 986 return EIO; 987 988 if (reg & R92C_SYS_CFG_TYPE_92C) { 989 sc->chip |= RTWN_CHIP_92C; 990 /* Check if it is a castrated 8192C. */ 991 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 992 R92C_HPON_FSM_CHIP_BONDING_ID) == 993 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 994 sc->chip |= RTWN_CHIP_92C_1T2R; 995 } 996 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 997 sc->chip |= RTWN_CHIP_UMC; 998 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 999 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1000 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 1001 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 1002 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 1003 else 1004 /* Unsupported unknown chip. */ 1005 return EIO; 1006 } 1007 return 0; 1008 } 1009 1010 static void 1011 rtwn_read_rom(struct rtwn_softc *sc) 1012 { 1013 struct ieee80211com *ic = &sc->sc_ic; 1014 struct r92c_rom *rom = &sc->rom; 1015 1016 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1017 1018 /* Read full ROM image. */ 1019 rtwn_efuse_read(sc); 1020 1021 if (rom->id != 0x8129) { 1022 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1023 rom->id); 1024 } 1025 1026 /* XXX Weird but this is what the vendor driver does. */ 1027 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1028 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1029 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1030 1031 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1032 sc->pa_setting, sc->board_type, sc->regulatory)); 1033 1034 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1035 } 1036 1037 static int 1038 rtwn_media_change(struct ifnet *ifp) 1039 { 1040 int error; 1041 1042 error = ieee80211_media_change(ifp); 1043 if (error != ENETRESET) 1044 return error; 1045 1046 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1047 (IFF_UP | IFF_RUNNING)) { 1048 rtwn_stop(ifp, 0); 1049 error = rtwn_init(ifp); 1050 } 1051 return error; 1052 } 1053 1054 /* 1055 * Initialize rate adaptation in firmware. 1056 */ 1057 static int 1058 rtwn_ra_init(struct rtwn_softc *sc) 1059 { 1060 static const uint8_t map[] = { 1061 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1062 }; 1063 struct ieee80211com *ic = &sc->sc_ic; 1064 struct ieee80211_node *ni = ic->ic_bss; 1065 struct ieee80211_rateset *rs = &ni->ni_rates; 1066 struct r92c_fw_cmd_macid_cfg cmd; 1067 uint32_t rates, basicrates; 1068 uint8_t mode; 1069 int maxrate, maxbasicrate, error, i, j; 1070 1071 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1072 1073 /* Get normal and basic rates mask. */ 1074 rates = basicrates = 0; 1075 maxrate = maxbasicrate = 0; 1076 for (i = 0; i < rs->rs_nrates; i++) { 1077 /* Convert 802.11 rate to HW rate index. */ 1078 for (j = 0; j < __arraycount(map); j++) 1079 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1080 break; 1081 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1082 continue; 1083 rates |= 1 << j; 1084 if (j > maxrate) 1085 maxrate = j; 1086 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1087 basicrates |= 1 << j; 1088 if (j > maxbasicrate) 1089 maxbasicrate = j; 1090 } 1091 } 1092 if (ic->ic_curmode == IEEE80211_MODE_11B) 1093 mode = R92C_RAID_11B; 1094 else 1095 mode = R92C_RAID_11BG; 1096 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1097 device_xname(sc->sc_dev), mode, rates, basicrates)); 1098 if (basicrates == 0) 1099 basicrates |= 1; /* add 1Mbps */ 1100 1101 /* Set rates mask for group addressed frames. */ 1102 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1103 cmd.mask = htole32((mode << 28) | basicrates); 1104 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1105 if (error != 0) { 1106 aprint_error_dev(sc->sc_dev, 1107 "could not add broadcast station\n"); 1108 return error; 1109 } 1110 /* Set initial MRR rate. */ 1111 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1112 maxbasicrate)); 1113 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1114 1115 /* Set rates mask for unicast frames. */ 1116 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1117 cmd.mask = htole32((mode << 28) | rates); 1118 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1119 if (error != 0) { 1120 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1121 return error; 1122 } 1123 /* Set initial MRR rate. */ 1124 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1125 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1126 1127 /* Configure Automatic Rate Fallback Register. */ 1128 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1129 if (rates & 0x0c) 1130 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1131 else 1132 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1133 } else 1134 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1135 1136 /* Indicate highest supported rate. */ 1137 ni->ni_txrate = rs->rs_nrates - 1; 1138 return 0; 1139 } 1140 1141 static int 1142 rtwn_get_nettype(struct rtwn_softc *sc) 1143 { 1144 struct ieee80211com *ic = &sc->sc_ic; 1145 int type; 1146 1147 switch (ic->ic_opmode) { 1148 case IEEE80211_M_STA: 1149 type = R92C_CR_NETTYPE_INFRA; 1150 break; 1151 1152 case IEEE80211_M_HOSTAP: 1153 type = R92C_CR_NETTYPE_AP; 1154 break; 1155 1156 case IEEE80211_M_IBSS: 1157 type = R92C_CR_NETTYPE_ADHOC; 1158 break; 1159 1160 default: 1161 type = R92C_CR_NETTYPE_NOLINK; 1162 break; 1163 } 1164 1165 return type; 1166 } 1167 1168 static void 1169 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1170 { 1171 uint32_t reg; 1172 1173 reg = rtwn_read_4(sc, R92C_CR); 1174 reg = RW(reg, R92C_CR_NETTYPE, type); 1175 rtwn_write_4(sc, R92C_CR, reg); 1176 } 1177 1178 static void 1179 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1180 { 1181 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1182 uint64_t tsf; 1183 1184 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1185 1186 /* Enable TSF synchronization. */ 1187 rtwn_write_1(sc, R92C_BCN_CTRL, 1188 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1189 1190 rtwn_write_1(sc, R92C_BCN_CTRL, 1191 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1192 1193 /* Set initial TSF. */ 1194 tsf = ni->ni_tstamp.tsf; 1195 tsf = le64toh(tsf); 1196 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1197 tsf -= IEEE80211_DUR_TU; 1198 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1199 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1200 1201 rtwn_write_1(sc, R92C_BCN_CTRL, 1202 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1203 } 1204 1205 static void 1206 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1207 { 1208 uint8_t reg; 1209 1210 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1211 1212 if (led == RTWN_LED_LINK) { 1213 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1214 if (!on) 1215 reg |= R92C_LEDCFG2_DIS; 1216 else 1217 reg |= R92C_LEDCFG2_EN; 1218 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1219 sc->ledlink = on; /* Save LED state. */ 1220 } 1221 } 1222 1223 static void 1224 rtwn_calib_to(void *arg) 1225 { 1226 struct rtwn_softc *sc = arg; 1227 struct r92c_fw_cmd_rssi cmd; 1228 1229 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1230 1231 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1232 goto restart_timer; 1233 1234 if (sc->avg_pwdb != -1) { 1235 /* Indicate Rx signal strength to FW for rate adaptation. */ 1236 memset(&cmd, 0, sizeof(cmd)); 1237 cmd.macid = 0; /* BSS. */ 1238 cmd.pwdb = sc->avg_pwdb; 1239 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1240 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1241 } 1242 1243 /* Do temperature compensation. */ 1244 rtwn_temp_calib(sc); 1245 1246 restart_timer: 1247 callout_schedule(&sc->calib_to, mstohz(2000)); 1248 } 1249 1250 static void 1251 rtwn_next_scan(void *arg) 1252 { 1253 struct rtwn_softc *sc = arg; 1254 struct ieee80211com *ic = &sc->sc_ic; 1255 int s; 1256 1257 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1258 1259 s = splnet(); 1260 if (ic->ic_state == IEEE80211_S_SCAN) 1261 ieee80211_next_scan(ic); 1262 splx(s); 1263 } 1264 1265 static void 1266 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1267 { 1268 1269 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1270 1271 /* start with lowest Tx rate */ 1272 ni->ni_txrate = 0; 1273 } 1274 1275 static int 1276 rtwn_reset(struct ifnet *ifp) 1277 { 1278 struct rtwn_softc *sc = ifp->if_softc; 1279 struct ieee80211com *ic = &sc->sc_ic; 1280 1281 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1282 return ENETRESET; 1283 1284 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1285 1286 return 0; 1287 } 1288 1289 static int 1290 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1291 { 1292 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1293 struct ieee80211_node *ni; 1294 enum ieee80211_state ostate = ic->ic_state; 1295 uint32_t reg; 1296 int s; 1297 1298 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1299 1300 s = splnet(); 1301 1302 callout_stop(&sc->scan_to); 1303 callout_stop(&sc->calib_to); 1304 1305 if (ostate != nstate) { 1306 DPRINTF(("%s: %s -> %s\n", __func__, 1307 ieee80211_state_name[ostate], 1308 ieee80211_state_name[nstate])); 1309 } 1310 1311 switch (ostate) { 1312 case IEEE80211_S_INIT: 1313 break; 1314 1315 case IEEE80211_S_SCAN: 1316 if (nstate != IEEE80211_S_SCAN) { 1317 /* 1318 * End of scanning 1319 */ 1320 /* flush 4-AC Queue after site_survey */ 1321 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1322 1323 /* Allow Rx from our BSSID only. */ 1324 rtwn_write_4(sc, R92C_RCR, 1325 rtwn_read_4(sc, R92C_RCR) | 1326 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1327 } 1328 break; 1329 1330 case IEEE80211_S_AUTH: 1331 case IEEE80211_S_ASSOC: 1332 break; 1333 1334 case IEEE80211_S_RUN: 1335 /* Turn link LED off. */ 1336 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1337 1338 /* Set media status to 'No Link'. */ 1339 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1340 1341 /* Stop Rx of data frames. */ 1342 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1343 1344 /* Rest TSF. */ 1345 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1346 1347 /* Disable TSF synchronization. */ 1348 rtwn_write_1(sc, R92C_BCN_CTRL, 1349 rtwn_read_1(sc, R92C_BCN_CTRL) | 1350 R92C_BCN_CTRL_DIS_TSF_UDT0); 1351 1352 /* Back to 20MHz mode */ 1353 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1354 1355 /* Reset EDCA parameters. */ 1356 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1357 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1358 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1359 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1360 1361 /* flush all cam entries */ 1362 rtwn_cam_init(sc); 1363 break; 1364 } 1365 1366 switch (nstate) { 1367 case IEEE80211_S_INIT: 1368 /* Turn link LED off. */ 1369 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1370 break; 1371 1372 case IEEE80211_S_SCAN: 1373 if (ostate != IEEE80211_S_SCAN) { 1374 /* 1375 * Begin of scanning 1376 */ 1377 1378 /* Set gain for scanning. */ 1379 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1380 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1381 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1382 1383 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1384 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1385 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1386 1387 /* Allow Rx from any BSSID. */ 1388 rtwn_write_4(sc, R92C_RCR, 1389 rtwn_read_4(sc, R92C_RCR) & 1390 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1391 1392 /* Stop Rx of data frames. */ 1393 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1394 1395 /* Disable update TSF */ 1396 rtwn_write_1(sc, R92C_BCN_CTRL, 1397 rtwn_read_1(sc, R92C_BCN_CTRL) | 1398 R92C_BCN_CTRL_DIS_TSF_UDT0); 1399 } 1400 1401 /* Make link LED blink during scan. */ 1402 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1403 1404 /* Pause AC Tx queues. */ 1405 rtwn_write_1(sc, R92C_TXPAUSE, 1406 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1407 1408 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1409 1410 /* Start periodic scan. */ 1411 callout_schedule(&sc->scan_to, mstohz(200)); 1412 break; 1413 1414 case IEEE80211_S_AUTH: 1415 /* Set initial gain under link. */ 1416 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1417 #ifdef doaslinux 1418 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1419 #else 1420 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1421 #endif 1422 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1423 1424 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1425 #ifdef doaslinux 1426 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1427 #else 1428 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1429 #endif 1430 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1431 1432 /* Set media status to 'No Link'. */ 1433 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1434 1435 /* Allow Rx from any BSSID. */ 1436 rtwn_write_4(sc, R92C_RCR, 1437 rtwn_read_4(sc, R92C_RCR) & 1438 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1439 1440 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1441 break; 1442 1443 case IEEE80211_S_ASSOC: 1444 break; 1445 1446 case IEEE80211_S_RUN: 1447 ni = ic->ic_bss; 1448 1449 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1450 1451 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1452 /* Back to 20Mhz mode */ 1453 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1454 1455 /* Set media status to 'No Link'. */ 1456 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1457 1458 /* Enable Rx of data frames. */ 1459 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1460 1461 /* Allow Rx from any BSSID. */ 1462 rtwn_write_4(sc, R92C_RCR, 1463 rtwn_read_4(sc, R92C_RCR) & 1464 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1465 1466 /* Accept Rx data/control/management frames */ 1467 rtwn_write_4(sc, R92C_RCR, 1468 rtwn_read_4(sc, R92C_RCR) | 1469 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1470 1471 /* Turn link LED on. */ 1472 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1473 break; 1474 } 1475 1476 /* Set media status to 'Associated'. */ 1477 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1478 1479 /* Set BSSID. */ 1480 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1481 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1482 1483 if (ic->ic_curmode == IEEE80211_MODE_11B) 1484 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1485 else /* 802.11b/g */ 1486 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1487 1488 /* Enable Rx of data frames. */ 1489 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1490 1491 /* Flush all AC queues. */ 1492 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1493 1494 /* Set beacon interval. */ 1495 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1496 1497 switch (ic->ic_opmode) { 1498 case IEEE80211_M_STA: 1499 /* Allow Rx from our BSSID only. */ 1500 rtwn_write_4(sc, R92C_RCR, 1501 rtwn_read_4(sc, R92C_RCR) | 1502 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1503 1504 /* Enable TSF synchronization. */ 1505 rtwn_tsf_sync_enable(sc); 1506 break; 1507 1508 case IEEE80211_M_HOSTAP: 1509 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1510 1511 /* Allow Rx from any BSSID. */ 1512 rtwn_write_4(sc, R92C_RCR, 1513 rtwn_read_4(sc, R92C_RCR) & 1514 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1515 1516 /* Reset TSF timer to zero. */ 1517 reg = rtwn_read_4(sc, R92C_TCR); 1518 reg &= ~0x01; 1519 rtwn_write_4(sc, R92C_TCR, reg); 1520 reg |= 0x01; 1521 rtwn_write_4(sc, R92C_TCR, reg); 1522 break; 1523 1524 case IEEE80211_M_MONITOR: 1525 default: 1526 break; 1527 } 1528 1529 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1530 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1531 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1532 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1533 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1534 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1535 1536 /* Intialize rate adaptation. */ 1537 rtwn_ra_init(sc); 1538 1539 /* Turn link LED on. */ 1540 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1541 1542 /* Reset average RSSI. */ 1543 sc->avg_pwdb = -1; 1544 1545 /* Reset temperature calibration state machine. */ 1546 sc->thcal_state = 0; 1547 sc->thcal_lctemp = 0; 1548 1549 /* Start periodic calibration. */ 1550 callout_schedule(&sc->calib_to, mstohz(2000)); 1551 break; 1552 } 1553 1554 (void)sc->sc_newstate(ic, nstate, arg); 1555 1556 splx(s); 1557 1558 return 0; 1559 } 1560 1561 static int 1562 rtwn_wme_update(struct ieee80211com *ic) 1563 { 1564 static const uint16_t aci2reg[WME_NUM_AC] = { 1565 R92C_EDCA_BE_PARAM, 1566 R92C_EDCA_BK_PARAM, 1567 R92C_EDCA_VI_PARAM, 1568 R92C_EDCA_VO_PARAM 1569 }; 1570 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1571 const struct wmeParams *wmep; 1572 int s, aci, aifs, slottime; 1573 1574 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1575 1576 s = splnet(); 1577 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1578 for (aci = 0; aci < WME_NUM_AC; aci++) { 1579 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1580 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1581 aifs = wmep->wmep_aifsn * slottime + 10; 1582 rtwn_write_4(sc, aci2reg[aci], 1583 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1584 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1585 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1586 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1587 } 1588 splx(s); 1589 1590 return 0; 1591 } 1592 1593 static void 1594 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1595 { 1596 int pwdb; 1597 1598 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1599 1600 /* Convert antenna signal to percentage. */ 1601 if (rssi <= -100 || rssi >= 20) 1602 pwdb = 0; 1603 else if (rssi >= 0) 1604 pwdb = 100; 1605 else 1606 pwdb = 100 + rssi; 1607 if (rate <= 3) { 1608 /* CCK gain is smaller than OFDM/MCS gain. */ 1609 pwdb += 6; 1610 if (pwdb > 100) 1611 pwdb = 100; 1612 if (pwdb <= 14) 1613 pwdb -= 4; 1614 else if (pwdb <= 26) 1615 pwdb -= 8; 1616 else if (pwdb <= 34) 1617 pwdb -= 6; 1618 else if (pwdb <= 42) 1619 pwdb -= 2; 1620 } 1621 if (sc->avg_pwdb == -1) /* Init. */ 1622 sc->avg_pwdb = pwdb; 1623 else if (sc->avg_pwdb < pwdb) 1624 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1625 else 1626 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1627 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1628 } 1629 1630 static int8_t 1631 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1632 { 1633 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1634 struct r92c_rx_phystat *phy; 1635 struct r92c_rx_cck *cck; 1636 uint8_t rpt; 1637 int8_t rssi; 1638 1639 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1640 1641 if (rate <= 3) { 1642 cck = (struct r92c_rx_cck *)physt; 1643 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1644 rpt = (cck->agc_rpt >> 5) & 0x3; 1645 rssi = (cck->agc_rpt & 0x1f) << 1; 1646 } else { 1647 rpt = (cck->agc_rpt >> 6) & 0x3; 1648 rssi = cck->agc_rpt & 0x3e; 1649 } 1650 rssi = cckoff[rpt] - rssi; 1651 } else { /* OFDM/HT. */ 1652 phy = (struct r92c_rx_phystat *)physt; 1653 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1654 } 1655 return rssi; 1656 } 1657 1658 static void 1659 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1660 struct rtwn_rx_data *rx_data, int desc_idx) 1661 { 1662 struct ieee80211com *ic = &sc->sc_ic; 1663 struct ifnet *ifp = IC2IFP(ic); 1664 struct ieee80211_frame *wh; 1665 struct ieee80211_node *ni; 1666 struct r92c_rx_phystat *phy = NULL; 1667 uint32_t rxdw0, rxdw3; 1668 struct mbuf *m, *m1; 1669 uint8_t rate; 1670 int8_t rssi = 0; 1671 int infosz, pktlen, shift, totlen, error; 1672 1673 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1674 1675 rxdw0 = le32toh(rx_desc->rxdw0); 1676 rxdw3 = le32toh(rx_desc->rxdw3); 1677 1678 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1679 /* 1680 * This should not happen since we setup our Rx filter 1681 * to not receive these frames. 1682 */ 1683 ifp->if_ierrors++; 1684 return; 1685 } 1686 1687 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1688 /* 1689 * XXX: This will drop most control packets. Do we really 1690 * want this in IEEE80211_M_MONITOR mode? 1691 */ 1692 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1693 ic->ic_stats.is_rx_tooshort++; 1694 ifp->if_ierrors++; 1695 return; 1696 } 1697 if (__predict_false(pktlen > MCLBYTES)) { 1698 ifp->if_ierrors++; 1699 return; 1700 } 1701 1702 rate = MS(rxdw3, R92C_RXDW3_RATE); 1703 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1704 if (infosz > sizeof(struct r92c_rx_phystat)) 1705 infosz = sizeof(struct r92c_rx_phystat); 1706 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1707 totlen = pktlen + infosz + shift; 1708 1709 /* Get RSSI from PHY status descriptor if present. */ 1710 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1711 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1712 rssi = rtwn_get_rssi(sc, rate, phy); 1713 /* Update our average RSSI. */ 1714 rtwn_update_avgrssi(sc, rate, rssi); 1715 } 1716 1717 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1718 pktlen, rate, infosz, shift, rssi)); 1719 1720 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1721 if (__predict_false(m1 == NULL)) { 1722 ic->ic_stats.is_rx_nobuf++; 1723 ifp->if_ierrors++; 1724 return; 1725 } 1726 MCLGET(m1, M_DONTWAIT); 1727 if (__predict_false(!(m1->m_flags & M_EXT))) { 1728 m_freem(m1); 1729 ic->ic_stats.is_rx_nobuf++; 1730 ifp->if_ierrors++; 1731 return; 1732 } 1733 1734 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1735 BUS_DMASYNC_POSTREAD); 1736 1737 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1738 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1739 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1740 if (error != 0) { 1741 m_freem(m1); 1742 1743 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1744 rx_data->m, BUS_DMA_NOWAIT)) 1745 panic("%s: could not load old RX mbuf", 1746 device_xname(sc->sc_dev)); 1747 1748 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1749 BUS_DMASYNC_PREREAD); 1750 1751 /* Physical address may have changed. */ 1752 rtwn_setup_rx_desc(sc, rx_desc, 1753 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1754 1755 ifp->if_ierrors++; 1756 return; 1757 } 1758 1759 /* Finalize mbuf. */ 1760 m = rx_data->m; 1761 rx_data->m = m1; 1762 m->m_pkthdr.len = m->m_len = totlen; 1763 m->m_pkthdr.rcvif = ifp; 1764 1765 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1766 BUS_DMASYNC_PREREAD); 1767 1768 /* Update RX descriptor. */ 1769 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1770 MCLBYTES, desc_idx); 1771 1772 /* Get ieee80211 frame header. */ 1773 if (rxdw0 & R92C_RXDW0_PHYST) 1774 m_adj(m, infosz + shift); 1775 else 1776 m_adj(m, shift); 1777 wh = mtod(m, struct ieee80211_frame *); 1778 1779 if (__predict_false(sc->sc_drvbpf != NULL)) { 1780 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1781 1782 tap->wr_flags = 0; 1783 /* Map HW rate index to 802.11 rate. */ 1784 tap->wr_flags = 2; 1785 if (!(rxdw3 & R92C_RXDW3_HT)) { 1786 switch (rate) { 1787 /* CCK. */ 1788 case 0: tap->wr_rate = 2; break; 1789 case 1: tap->wr_rate = 4; break; 1790 case 2: tap->wr_rate = 11; break; 1791 case 3: tap->wr_rate = 22; break; 1792 /* OFDM. */ 1793 case 4: tap->wr_rate = 12; break; 1794 case 5: tap->wr_rate = 18; break; 1795 case 6: tap->wr_rate = 24; break; 1796 case 7: tap->wr_rate = 36; break; 1797 case 8: tap->wr_rate = 48; break; 1798 case 9: tap->wr_rate = 72; break; 1799 case 10: tap->wr_rate = 96; break; 1800 case 11: tap->wr_rate = 108; break; 1801 } 1802 } else if (rate >= 12) { /* MCS0~15. */ 1803 /* Bit 7 set means HT MCS instead of rate. */ 1804 tap->wr_rate = 0x80 | (rate - 12); 1805 } 1806 tap->wr_dbm_antsignal = rssi; 1807 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1808 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1809 1810 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1811 } 1812 1813 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1814 1815 /* push the frame up to the 802.11 stack */ 1816 ieee80211_input(ic, m, ni, rssi, 0); 1817 1818 /* Node is no longer needed. */ 1819 ieee80211_free_node(ni); 1820 } 1821 1822 static int 1823 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1824 { 1825 struct ieee80211com *ic = &sc->sc_ic; 1826 struct ieee80211_frame *wh; 1827 struct ieee80211_key *k = NULL; 1828 struct rtwn_tx_ring *tx_ring; 1829 struct rtwn_tx_data *data; 1830 struct r92c_tx_desc *txd; 1831 uint16_t qos, seq; 1832 uint8_t raid, type, tid, qid; 1833 int hasqos, error; 1834 1835 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1836 1837 wh = mtod(m, struct ieee80211_frame *); 1838 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1839 1840 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1841 k = ieee80211_crypto_encap(ic, ni, m); 1842 if (k == NULL) 1843 return ENOBUFS; 1844 1845 wh = mtod(m, struct ieee80211_frame *); 1846 } 1847 1848 if ((hasqos = ieee80211_has_qos(wh))) { 1849 /* data frames in 11n mode */ 1850 qos = ieee80211_get_qos(wh); 1851 tid = qos & IEEE80211_QOS_TID; 1852 qid = TID_TO_WME_AC(tid); 1853 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1854 /* Use AC_VO for management frames. */ 1855 tid = 0; /* compiler happy */ 1856 qid = RTWN_VO_QUEUE; 1857 } else { 1858 /* non-qos data frames */ 1859 tid = R92C_TXDW1_QSEL_BE; 1860 qid = RTWN_BE_QUEUE; 1861 } 1862 1863 /* Grab a Tx buffer from the ring. */ 1864 tx_ring = &sc->tx_ring[qid]; 1865 data = &tx_ring->tx_data[tx_ring->cur]; 1866 if (data->m != NULL) { 1867 m_freem(m); 1868 return ENOBUFS; 1869 } 1870 1871 /* Fill Tx descriptor. */ 1872 txd = &tx_ring->desc[tx_ring->cur]; 1873 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1874 m_freem(m); 1875 return ENOBUFS; 1876 } 1877 1878 txd->txdw0 = htole32( 1879 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1880 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1881 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1882 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1883 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1884 1885 txd->txdw1 = 0; 1886 txd->txdw4 = 0; 1887 txd->txdw5 = 0; 1888 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1889 type == IEEE80211_FC0_TYPE_DATA) { 1890 if (ic->ic_curmode == IEEE80211_MODE_11B) 1891 raid = R92C_RAID_11B; 1892 else 1893 raid = R92C_RAID_11BG; 1894 1895 txd->txdw1 |= htole32( 1896 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1897 SM(R92C_TXDW1_QSEL, tid) | 1898 SM(R92C_TXDW1_RAID, raid) | 1899 R92C_TXDW1_AGGBK); 1900 1901 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1902 /* for 11g */ 1903 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1904 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1905 R92C_TXDW4_HWRTSEN); 1906 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1907 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1908 R92C_TXDW4_HWRTSEN); 1909 } 1910 } 1911 /* Send RTS at OFDM24. */ 1912 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1913 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1914 /* Send data at OFDM54. */ 1915 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1916 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1917 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1918 txd->txdw1 |= htole32( 1919 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1920 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1921 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1922 1923 /* Force CCK1. */ 1924 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1925 /* Use 1Mbps */ 1926 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1927 } else { 1928 txd->txdw1 |= htole32( 1929 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1930 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1931 1932 /* Force CCK1. */ 1933 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1934 /* Use 1Mbps */ 1935 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1936 } 1937 1938 /* Set sequence number (already little endian). */ 1939 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1940 txd->txdseq = htole16(seq); 1941 1942 if (!hasqos) { 1943 /* Use HW sequence numbering for non-QoS frames. */ 1944 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1945 txd->txdseq |= htole16(0x8000); /* WTF? */ 1946 } else 1947 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1948 1949 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1950 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1951 if (error && error != EFBIG) { 1952 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1953 error); 1954 m_freem(m); 1955 return error; 1956 } 1957 if (error != 0) { 1958 /* Too many DMA segments, linearize mbuf. */ 1959 if ((m = m_defrag(m, M_DONTWAIT)) == NULL) { 1960 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1961 return ENOBUFS; 1962 } 1963 1964 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1965 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1966 if (error != 0) { 1967 aprint_error_dev(sc->sc_dev, 1968 "can't map mbuf (error %d)\n", error); 1969 m_freem(m); 1970 return error; 1971 } 1972 } 1973 1974 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1975 txd->txbufsize = htole16(m->m_pkthdr.len); 1976 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1977 BUS_SPACE_BARRIER_WRITE); 1978 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1979 1980 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1981 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1982 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1983 BUS_DMASYNC_PREWRITE); 1984 1985 data->m = m; 1986 data->ni = ni; 1987 1988 if (__predict_false(sc->sc_drvbpf != NULL)) { 1989 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1990 1991 tap->wt_flags = 0; 1992 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1993 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1994 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1995 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1996 1997 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1998 } 1999 2000 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2001 tx_ring->queued++; 2002 2003 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 2004 sc->qfullmsk |= (1 << qid); 2005 2006 /* Kick TX. */ 2007 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2008 2009 return 0; 2010 } 2011 2012 static void 2013 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2014 { 2015 struct ieee80211com *ic = &sc->sc_ic; 2016 struct ifnet *ifp = IC2IFP(ic); 2017 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2018 struct rtwn_tx_data *tx_data; 2019 struct r92c_tx_desc *tx_desc; 2020 int i; 2021 2022 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2023 qid)); 2024 2025 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2026 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2028 2029 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2030 tx_data = &tx_ring->tx_data[i]; 2031 if (tx_data->m == NULL) 2032 continue; 2033 2034 tx_desc = &tx_ring->desc[i]; 2035 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2036 continue; 2037 2038 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2039 m_freem(tx_data->m); 2040 tx_data->m = NULL; 2041 ieee80211_free_node(tx_data->ni); 2042 tx_data->ni = NULL; 2043 2044 ifp->if_opackets++; 2045 sc->sc_tx_timer = 0; 2046 tx_ring->queued--; 2047 } 2048 2049 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 2050 sc->qfullmsk &= ~(1 << qid); 2051 } 2052 2053 static void 2054 rtwn_start(struct ifnet *ifp) 2055 { 2056 struct rtwn_softc *sc = ifp->if_softc; 2057 struct ieee80211com *ic = &sc->sc_ic; 2058 struct ether_header *eh; 2059 struct ieee80211_node *ni; 2060 struct mbuf *m; 2061 2062 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2063 return; 2064 2065 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2066 2067 for (;;) { 2068 if (sc->qfullmsk != 0) { 2069 ifp->if_flags |= IFF_OACTIVE; 2070 break; 2071 } 2072 /* Send pending management frames first. */ 2073 IF_DEQUEUE(&ic->ic_mgtq, m); 2074 if (m != NULL) { 2075 ni = (void *)m->m_pkthdr.rcvif; 2076 m->m_pkthdr.rcvif = NULL; 2077 goto sendit; 2078 } 2079 if (ic->ic_state != IEEE80211_S_RUN) 2080 break; 2081 2082 /* Encapsulate and send data frames. */ 2083 IFQ_DEQUEUE(&ifp->if_snd, m); 2084 if (m == NULL) 2085 break; 2086 2087 if (m->m_len < (int)sizeof(*eh) && 2088 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2089 ifp->if_oerrors++; 2090 continue; 2091 } 2092 eh = mtod(m, struct ether_header *); 2093 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2094 if (ni == NULL) { 2095 m_freem(m); 2096 ifp->if_oerrors++; 2097 continue; 2098 } 2099 2100 bpf_mtap(ifp, m); 2101 2102 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2103 ieee80211_free_node(ni); 2104 ifp->if_oerrors++; 2105 continue; 2106 } 2107 sendit: 2108 bpf_mtap3(ic->ic_rawbpf, m); 2109 2110 if (rtwn_tx(sc, m, ni) != 0) { 2111 ieee80211_free_node(ni); 2112 ifp->if_oerrors++; 2113 continue; 2114 } 2115 2116 sc->sc_tx_timer = 5; 2117 ifp->if_timer = 1; 2118 } 2119 2120 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2121 } 2122 2123 static void 2124 rtwn_watchdog(struct ifnet *ifp) 2125 { 2126 struct rtwn_softc *sc = ifp->if_softc; 2127 struct ieee80211com *ic = &sc->sc_ic; 2128 2129 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2130 2131 ifp->if_timer = 0; 2132 2133 if (sc->sc_tx_timer > 0) { 2134 if (--sc->sc_tx_timer == 0) { 2135 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2136 softint_schedule(sc->init_task); 2137 ifp->if_oerrors++; 2138 return; 2139 } 2140 ifp->if_timer = 1; 2141 } 2142 ieee80211_watchdog(ic); 2143 } 2144 2145 static int 2146 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2147 { 2148 struct rtwn_softc *sc = ifp->if_softc; 2149 struct ieee80211com *ic = &sc->sc_ic; 2150 int s, error = 0; 2151 2152 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2153 __func__, cmd, data)); 2154 2155 s = splnet(); 2156 2157 switch (cmd) { 2158 case SIOCSIFFLAGS: 2159 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2160 break; 2161 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2162 case IFF_UP | IFF_RUNNING: 2163 break; 2164 case IFF_UP: 2165 error = rtwn_init(ifp); 2166 if (error != 0) 2167 ifp->if_flags &= ~IFF_UP; 2168 break; 2169 case IFF_RUNNING: 2170 rtwn_stop(ifp, 1); 2171 break; 2172 case 0: 2173 break; 2174 } 2175 break; 2176 2177 case SIOCADDMULTI: 2178 case SIOCDELMULTI: 2179 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2180 /* setup multicast filter, etc */ 2181 error = 0; 2182 } 2183 break; 2184 2185 case SIOCS80211CHANNEL: 2186 error = ieee80211_ioctl(ic, cmd, data); 2187 if (error == ENETRESET && 2188 ic->ic_opmode == IEEE80211_M_MONITOR) { 2189 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2190 (IFF_UP | IFF_RUNNING)) { 2191 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2192 } 2193 error = 0; 2194 } 2195 break; 2196 2197 default: 2198 error = ieee80211_ioctl(ic, cmd, data); 2199 break; 2200 } 2201 2202 if (error == ENETRESET) { 2203 error = 0; 2204 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2205 (IFF_UP | IFF_RUNNING)) { 2206 rtwn_stop(ifp, 0); 2207 error = rtwn_init(ifp); 2208 } 2209 } 2210 2211 splx(s); 2212 2213 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2214 error)); 2215 2216 return error; 2217 } 2218 2219 static int 2220 rtwn_power_on(struct rtwn_softc *sc) 2221 { 2222 uint32_t reg; 2223 int ntries; 2224 2225 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2226 2227 /* Wait for autoload done bit. */ 2228 for (ntries = 0; ntries < 1000; ntries++) { 2229 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2230 break; 2231 DELAY(5); 2232 } 2233 if (ntries == 1000) { 2234 aprint_error_dev(sc->sc_dev, 2235 "timeout waiting for chip autoload\n"); 2236 return ETIMEDOUT; 2237 } 2238 2239 /* Unlock ISO/CLK/Power control register. */ 2240 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2241 2242 /* TODO: check if we need this for 8188CE */ 2243 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2244 /* bt coex */ 2245 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2246 reg |= (R92C_APS_FSMCO_SOP_ABG | 2247 R92C_APS_FSMCO_SOP_AMB | 2248 R92C_APS_FSMCO_XOP_BTCK); 2249 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2250 } 2251 2252 /* Move SPS into PWM mode. */ 2253 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2254 DELAY(100); 2255 2256 /* Set low byte to 0x0f, leave others unchanged. */ 2257 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2258 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2259 2260 /* TODO: check if we need this for 8188CE */ 2261 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2262 /* bt coex */ 2263 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2264 reg &= ~0x00024800; /* XXX magic from linux */ 2265 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2266 } 2267 2268 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2269 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2270 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2271 DELAY(200); 2272 2273 /* TODO: linux does additional btcoex stuff here */ 2274 2275 /* Auto enable WLAN. */ 2276 rtwn_write_2(sc, R92C_APS_FSMCO, 2277 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2278 for (ntries = 0; ntries < 1000; ntries++) { 2279 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2280 R92C_APS_FSMCO_APFM_ONMAC)) 2281 break; 2282 DELAY(5); 2283 } 2284 if (ntries == 1000) { 2285 aprint_error_dev(sc->sc_dev, 2286 "timeout waiting for MAC auto ON\n"); 2287 return ETIMEDOUT; 2288 } 2289 2290 /* Enable radio, GPIO and LED functions. */ 2291 rtwn_write_2(sc, R92C_APS_FSMCO, 2292 R92C_APS_FSMCO_AFSM_PCIE | 2293 R92C_APS_FSMCO_PDN_EN | 2294 R92C_APS_FSMCO_PFM_ALDN); 2295 2296 /* Release RF digital isolation. */ 2297 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2298 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2299 2300 if (sc->chip & RTWN_CHIP_92C) 2301 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2302 else 2303 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2304 2305 rtwn_write_4(sc, R92C_INT_MIG, 0); 2306 2307 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2308 /* bt coex */ 2309 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2310 reg &= 0xfd; /* XXX magic from linux */ 2311 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2312 } 2313 2314 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2315 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2316 2317 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2318 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2319 aprint_error_dev(sc->sc_dev, 2320 "radio is disabled by hardware switch\n"); 2321 return EPERM; /* :-) */ 2322 } 2323 2324 /* Initialize MAC. */ 2325 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2326 rtwn_write_1(sc, R92C_APSD_CTRL, 2327 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2328 for (ntries = 0; ntries < 200; ntries++) { 2329 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2330 R92C_APSD_CTRL_OFF_STATUS)) 2331 break; 2332 DELAY(500); 2333 } 2334 if (ntries == 200) { 2335 aprint_error_dev(sc->sc_dev, 2336 "timeout waiting for MAC initialization\n"); 2337 return ETIMEDOUT; 2338 } 2339 2340 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2341 reg = rtwn_read_2(sc, R92C_CR); 2342 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2343 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2344 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2345 R92C_CR_ENSEC; 2346 rtwn_write_2(sc, R92C_CR, reg); 2347 2348 rtwn_write_1(sc, 0xfe10, 0x19); 2349 2350 return 0; 2351 } 2352 2353 static int 2354 rtwn_llt_init(struct rtwn_softc *sc) 2355 { 2356 int i, error; 2357 2358 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2359 2360 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2361 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2362 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2363 return error; 2364 } 2365 /* NB: 0xff indicates end-of-list. */ 2366 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2367 return error; 2368 /* 2369 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2370 * as ring buffer. 2371 */ 2372 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2373 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2374 return error; 2375 } 2376 /* Make the last page point to the beginning of the ring buffer. */ 2377 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2378 return error; 2379 } 2380 2381 static void 2382 rtwn_fw_reset(struct rtwn_softc *sc) 2383 { 2384 uint16_t reg; 2385 int ntries; 2386 2387 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2388 2389 /* Tell 8051 to reset itself. */ 2390 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2391 2392 /* Wait until 8051 resets by itself. */ 2393 for (ntries = 0; ntries < 100; ntries++) { 2394 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2395 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2396 goto sleep; 2397 DELAY(50); 2398 } 2399 /* Force 8051 reset. */ 2400 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2401 sleep: 2402 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2403 #if 0 2404 /* 2405 * We must sleep for one second to let the firmware settle. 2406 * Accessing registers too early will hang the whole system. 2407 */ 2408 tsleep(®, 0, "rtwnrst", hz); 2409 #else 2410 DELAY(1000 * 1000); 2411 #endif 2412 } 2413 2414 static int 2415 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2416 { 2417 uint32_t reg; 2418 int off, mlen, error = 0, i; 2419 2420 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2421 2422 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2423 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2424 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2425 2426 DELAY(5); 2427 2428 off = R92C_FW_START_ADDR; 2429 while (len > 0) { 2430 if (len > 196) 2431 mlen = 196; 2432 else if (len > 4) 2433 mlen = 4; 2434 else 2435 mlen = 1; 2436 for (i = 0; i < mlen; i++) 2437 rtwn_write_1(sc, off++, buf[i]); 2438 buf += mlen; 2439 len -= mlen; 2440 } 2441 2442 return error; 2443 } 2444 2445 static int 2446 rtwn_load_firmware(struct rtwn_softc *sc) 2447 { 2448 firmware_handle_t fwh; 2449 const struct r92c_fw_hdr *hdr; 2450 const char *name; 2451 u_char *fw, *ptr; 2452 size_t len; 2453 uint32_t reg; 2454 int mlen, ntries, page, error; 2455 2456 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2457 2458 /* Read firmware image from the filesystem. */ 2459 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2460 RTWN_CHIP_UMC_A_CUT) 2461 name = "rtl8192cfwU.bin"; 2462 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2463 name = "rtl8192cfwU_B.bin"; 2464 else 2465 name = "rtl8192cfw.bin"; 2466 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2467 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2468 aprint_error_dev(sc->sc_dev, 2469 "could not read firmware %s (error %d)\n", name, error); 2470 return error; 2471 } 2472 const size_t fwlen = len = firmware_get_size(fwh); 2473 fw = firmware_malloc(len); 2474 if (fw == NULL) { 2475 aprint_error_dev(sc->sc_dev, 2476 "failed to allocate firmware memory (size=%zu)\n", len); 2477 firmware_close(fwh); 2478 return ENOMEM; 2479 } 2480 error = firmware_read(fwh, 0, fw, len); 2481 firmware_close(fwh); 2482 if (error != 0) { 2483 aprint_error_dev(sc->sc_dev, 2484 "failed to read firmware (error %d)\n", error); 2485 firmware_free(fw, fwlen); 2486 return error; 2487 } 2488 2489 if (len < sizeof(*hdr)) { 2490 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2491 error = EINVAL; 2492 goto fail; 2493 } 2494 ptr = fw; 2495 hdr = (const struct r92c_fw_hdr *)ptr; 2496 /* Check if there is a valid FW header and skip it. */ 2497 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2498 (le16toh(hdr->signature) >> 4) == 0x92c) { 2499 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2500 le16toh(hdr->version), le16toh(hdr->subversion), 2501 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2502 ptr += sizeof(*hdr); 2503 len -= sizeof(*hdr); 2504 } 2505 2506 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2507 rtwn_fw_reset(sc); 2508 2509 /* Enable FW download. */ 2510 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2511 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2512 R92C_SYS_FUNC_EN_CPUEN); 2513 rtwn_write_1(sc, R92C_MCUFWDL, 2514 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2515 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2516 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2517 2518 /* Reset the FWDL checksum. */ 2519 rtwn_write_1(sc, R92C_MCUFWDL, 2520 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2521 2522 /* download firmware */ 2523 for (page = 0; len > 0; page++) { 2524 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2525 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2526 if (error != 0) { 2527 aprint_error_dev(sc->sc_dev, 2528 "could not load firmware page %d\n", page); 2529 goto fail; 2530 } 2531 ptr += mlen; 2532 len -= mlen; 2533 } 2534 2535 /* Disable FW download. */ 2536 rtwn_write_1(sc, R92C_MCUFWDL, 2537 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2538 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2539 2540 /* Wait for checksum report. */ 2541 for (ntries = 0; ntries < 1000; ntries++) { 2542 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2543 break; 2544 DELAY(5); 2545 } 2546 if (ntries == 1000) { 2547 aprint_error_dev(sc->sc_dev, 2548 "timeout waiting for checksum report\n"); 2549 error = ETIMEDOUT; 2550 goto fail; 2551 } 2552 2553 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2554 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2555 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2556 2557 /* Wait for firmware readiness. */ 2558 for (ntries = 0; ntries < 1000; ntries++) { 2559 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2560 break; 2561 DELAY(5); 2562 } 2563 if (ntries == 1000) { 2564 aprint_error_dev(sc->sc_dev, 2565 "timeout waiting for firmware readiness\n"); 2566 error = ETIMEDOUT; 2567 goto fail; 2568 } 2569 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2570 2571 fail: 2572 firmware_free(fw, fwlen); 2573 return error; 2574 } 2575 2576 static int 2577 rtwn_dma_init(struct rtwn_softc *sc) 2578 { 2579 uint32_t reg; 2580 int error; 2581 2582 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2583 2584 /* Initialize LLT table. */ 2585 error = rtwn_llt_init(sc); 2586 if (error != 0) 2587 return error; 2588 2589 /* Set number of pages for normal priority queue. */ 2590 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2591 rtwn_write_4(sc, R92C_RQPN, 2592 /* Set number of pages for public queue. */ 2593 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2594 /* Set number of pages for high priority queue. */ 2595 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2596 /* Set number of pages for low priority queue. */ 2597 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2598 /* Load values. */ 2599 R92C_RQPN_LD); 2600 2601 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2602 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2603 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2604 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2605 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2606 2607 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2608 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2609 reg |= 0xF771; 2610 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2611 2612 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2613 2614 /* Configure Tx DMA. */ 2615 rtwn_write_4(sc, R92C_BKQ_DESA, 2616 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2617 rtwn_write_4(sc, R92C_BEQ_DESA, 2618 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2619 rtwn_write_4(sc, R92C_VIQ_DESA, 2620 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2621 rtwn_write_4(sc, R92C_VOQ_DESA, 2622 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2623 rtwn_write_4(sc, R92C_BCNQ_DESA, 2624 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2625 rtwn_write_4(sc, R92C_MGQ_DESA, 2626 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2627 rtwn_write_4(sc, R92C_HQ_DESA, 2628 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2629 2630 /* Configure Rx DMA. */ 2631 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2632 2633 /* Set Tx/Rx transfer page boundary. */ 2634 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2635 2636 /* Set Tx/Rx transfer page size. */ 2637 rtwn_write_1(sc, R92C_PBP, 2638 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2639 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2640 return 0; 2641 } 2642 2643 static void 2644 rtwn_mac_init(struct rtwn_softc *sc) 2645 { 2646 int i; 2647 2648 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2649 2650 /* Write MAC initialization values. */ 2651 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2652 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2653 } 2654 2655 static void 2656 rtwn_bb_init(struct rtwn_softc *sc) 2657 { 2658 const struct rtwn_bb_prog *prog; 2659 uint32_t reg; 2660 int i; 2661 2662 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2663 2664 /* Enable BB and RF. */ 2665 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2666 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2667 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2668 R92C_SYS_FUNC_EN_DIO_RF); 2669 2670 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2671 2672 rtwn_write_1(sc, R92C_RF_CTRL, 2673 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2674 2675 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2676 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2677 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2678 R92C_SYS_FUNC_EN_BBRSTB); 2679 2680 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2681 2682 rtwn_write_4(sc, R92C_LEDCFG0, 2683 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2684 2685 /* Select BB programming. */ 2686 prog = (sc->chip & RTWN_CHIP_92C) ? 2687 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2688 2689 /* Write BB initialization values. */ 2690 for (i = 0; i < prog->count; i++) { 2691 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2692 DELAY(1); 2693 } 2694 2695 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2696 /* 8192C 1T only configuration. */ 2697 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2698 reg = (reg & ~0x00000003) | 0x2; 2699 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2700 2701 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2702 reg = (reg & ~0x00300033) | 0x00200022; 2703 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2704 2705 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2706 reg = (reg & ~0xff000000) | 0x45 << 24; 2707 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2708 2709 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2710 reg = (reg & ~0x000000ff) | 0x23; 2711 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2712 2713 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2714 reg = (reg & ~0x00000030) | 1 << 4; 2715 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2716 2717 reg = rtwn_bb_read(sc, 0xe74); 2718 reg = (reg & ~0x0c000000) | 2 << 26; 2719 rtwn_bb_write(sc, 0xe74, reg); 2720 reg = rtwn_bb_read(sc, 0xe78); 2721 reg = (reg & ~0x0c000000) | 2 << 26; 2722 rtwn_bb_write(sc, 0xe78, reg); 2723 reg = rtwn_bb_read(sc, 0xe7c); 2724 reg = (reg & ~0x0c000000) | 2 << 26; 2725 rtwn_bb_write(sc, 0xe7c, reg); 2726 reg = rtwn_bb_read(sc, 0xe80); 2727 reg = (reg & ~0x0c000000) | 2 << 26; 2728 rtwn_bb_write(sc, 0xe80, reg); 2729 reg = rtwn_bb_read(sc, 0xe88); 2730 reg = (reg & ~0x0c000000) | 2 << 26; 2731 rtwn_bb_write(sc, 0xe88, reg); 2732 } 2733 2734 /* Write AGC values. */ 2735 for (i = 0; i < prog->agccount; i++) { 2736 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2737 prog->agcvals[i]); 2738 DELAY(1); 2739 } 2740 2741 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2742 R92C_HSSI_PARAM2_CCK_HIPWR) 2743 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2744 } 2745 2746 static void 2747 rtwn_rf_init(struct rtwn_softc *sc) 2748 { 2749 const struct rtwn_rf_prog *prog; 2750 uint32_t reg, type; 2751 int i, j, idx, off; 2752 2753 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2754 2755 /* Select RF programming based on board type. */ 2756 if (!(sc->chip & RTWN_CHIP_92C)) { 2757 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2758 prog = rtl8188ce_rf_prog; 2759 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2760 prog = rtl8188ru_rf_prog; 2761 else 2762 prog = rtl8188cu_rf_prog; 2763 } else 2764 prog = rtl8192ce_rf_prog; 2765 2766 for (i = 0; i < sc->nrxchains; i++) { 2767 /* Save RF_ENV control type. */ 2768 idx = i / 2; 2769 off = (i % 2) * 16; 2770 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2771 type = (reg >> off) & 0x10; 2772 2773 /* Set RF_ENV enable. */ 2774 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2775 reg |= 0x100000; 2776 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2777 DELAY(1); 2778 /* Set RF_ENV output high. */ 2779 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2780 reg |= 0x10; 2781 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2782 DELAY(1); 2783 /* Set address and data lengths of RF registers. */ 2784 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2785 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2786 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2787 DELAY(1); 2788 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2789 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2790 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2791 DELAY(1); 2792 2793 /* Write RF initialization values for this chain. */ 2794 for (j = 0; j < prog[i].count; j++) { 2795 if (prog[i].regs[j] >= 0xf9 && 2796 prog[i].regs[j] <= 0xfe) { 2797 /* 2798 * These are fake RF registers offsets that 2799 * indicate a delay is required. 2800 */ 2801 DELAY(50); 2802 continue; 2803 } 2804 rtwn_rf_write(sc, i, prog[i].regs[j], 2805 prog[i].vals[j]); 2806 DELAY(1); 2807 } 2808 2809 /* Restore RF_ENV control type. */ 2810 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2811 reg &= ~(0x10 << off) | (type << off); 2812 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2813 2814 /* Cache RF register CHNLBW. */ 2815 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2816 } 2817 2818 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2819 RTWN_CHIP_UMC_A_CUT) { 2820 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2821 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2822 } 2823 } 2824 2825 static void 2826 rtwn_cam_init(struct rtwn_softc *sc) 2827 { 2828 2829 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2830 2831 /* Invalidate all CAM entries. */ 2832 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2833 } 2834 2835 static void 2836 rtwn_pa_bias_init(struct rtwn_softc *sc) 2837 { 2838 uint8_t reg; 2839 int i; 2840 2841 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2842 2843 for (i = 0; i < sc->nrxchains; i++) { 2844 if (sc->pa_setting & (1 << i)) 2845 continue; 2846 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2847 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2848 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2849 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2850 } 2851 if (!(sc->pa_setting & 0x10)) { 2852 reg = rtwn_read_1(sc, 0x16); 2853 reg = (reg & ~0xf0) | 0x90; 2854 rtwn_write_1(sc, 0x16, reg); 2855 } 2856 } 2857 2858 static void 2859 rtwn_rxfilter_init(struct rtwn_softc *sc) 2860 { 2861 2862 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2863 2864 /* Initialize Rx filter. */ 2865 /* TODO: use better filter for monitor mode. */ 2866 rtwn_write_4(sc, R92C_RCR, 2867 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2868 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2869 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2870 /* Accept all multicast frames. */ 2871 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2872 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2873 /* Accept all management frames. */ 2874 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2875 /* Reject all control frames. */ 2876 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2877 /* Accept all data frames. */ 2878 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2879 } 2880 2881 static void 2882 rtwn_edca_init(struct rtwn_softc *sc) 2883 { 2884 2885 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2886 2887 /* set spec SIFS (used in NAV) */ 2888 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2889 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2890 2891 /* set SIFS CCK/OFDM */ 2892 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2893 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2894 2895 /* TXOP */ 2896 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2897 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2898 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2899 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2900 } 2901 2902 static void 2903 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2904 uint16_t power[RTWN_RIDX_COUNT]) 2905 { 2906 uint32_t reg; 2907 2908 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2909 2910 /* Write per-CCK rate Tx power. */ 2911 if (chain == 0) { 2912 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2913 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2914 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2915 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2916 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2917 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2918 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2919 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2920 } else { 2921 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2922 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2923 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2924 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2925 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2926 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2927 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2928 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2929 } 2930 /* Write per-OFDM rate Tx power. */ 2931 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2932 SM(R92C_TXAGC_RATE06, power[ 4]) | 2933 SM(R92C_TXAGC_RATE09, power[ 5]) | 2934 SM(R92C_TXAGC_RATE12, power[ 6]) | 2935 SM(R92C_TXAGC_RATE18, power[ 7])); 2936 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2937 SM(R92C_TXAGC_RATE24, power[ 8]) | 2938 SM(R92C_TXAGC_RATE36, power[ 9]) | 2939 SM(R92C_TXAGC_RATE48, power[10]) | 2940 SM(R92C_TXAGC_RATE54, power[11])); 2941 /* Write per-MCS Tx power. */ 2942 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2943 SM(R92C_TXAGC_MCS00, power[12]) | 2944 SM(R92C_TXAGC_MCS01, power[13]) | 2945 SM(R92C_TXAGC_MCS02, power[14]) | 2946 SM(R92C_TXAGC_MCS03, power[15])); 2947 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2948 SM(R92C_TXAGC_MCS04, power[16]) | 2949 SM(R92C_TXAGC_MCS05, power[17]) | 2950 SM(R92C_TXAGC_MCS06, power[18]) | 2951 SM(R92C_TXAGC_MCS07, power[19])); 2952 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2953 SM(R92C_TXAGC_MCS08, power[20]) | 2954 SM(R92C_TXAGC_MCS09, power[21]) | 2955 SM(R92C_TXAGC_MCS10, power[22]) | 2956 SM(R92C_TXAGC_MCS11, power[23])); 2957 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2958 SM(R92C_TXAGC_MCS12, power[24]) | 2959 SM(R92C_TXAGC_MCS13, power[25]) | 2960 SM(R92C_TXAGC_MCS14, power[26]) | 2961 SM(R92C_TXAGC_MCS15, power[27])); 2962 } 2963 2964 static void 2965 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2966 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2967 uint16_t power[RTWN_RIDX_COUNT]) 2968 { 2969 struct ieee80211com *ic = &sc->sc_ic; 2970 struct r92c_rom *rom = &sc->rom; 2971 uint16_t cckpow, ofdmpow, htpow, diff, max; 2972 const struct rtwn_txpwr *base; 2973 int ridx, chan, group; 2974 2975 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2976 2977 /* Determine channel group. */ 2978 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2979 if (chan <= 3) 2980 group = 0; 2981 else if (chan <= 9) 2982 group = 1; 2983 else 2984 group = 2; 2985 2986 /* Get original Tx power based on board type and RF chain. */ 2987 if (!(sc->chip & RTWN_CHIP_92C)) { 2988 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2989 base = &rtl8188ru_txagc[chain]; 2990 else 2991 base = &rtl8192cu_txagc[chain]; 2992 } else 2993 base = &rtl8192cu_txagc[chain]; 2994 2995 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2996 if (sc->regulatory == 0) { 2997 for (ridx = 0; ridx <= 3; ridx++) 2998 power[ridx] = base->pwr[0][ridx]; 2999 } 3000 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3001 if (sc->regulatory == 3) { 3002 power[ridx] = base->pwr[0][ridx]; 3003 /* Apply vendor limits. */ 3004 if (extc != NULL) 3005 max = rom->ht40_max_pwr[group]; 3006 else 3007 max = rom->ht20_max_pwr[group]; 3008 max = (max >> (chain * 4)) & 0xf; 3009 if (power[ridx] > max) 3010 power[ridx] = max; 3011 } else if (sc->regulatory == 1) { 3012 if (extc == NULL) 3013 power[ridx] = base->pwr[group][ridx]; 3014 } else if (sc->regulatory != 2) 3015 power[ridx] = base->pwr[0][ridx]; 3016 } 3017 3018 /* Compute per-CCK rate Tx power. */ 3019 cckpow = rom->cck_tx_pwr[chain][group]; 3020 for (ridx = 0; ridx <= 3; ridx++) { 3021 power[ridx] += cckpow; 3022 if (power[ridx] > R92C_MAX_TX_PWR) 3023 power[ridx] = R92C_MAX_TX_PWR; 3024 } 3025 3026 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3027 if (sc->ntxchains > 1) { 3028 /* Apply reduction for 2 spatial streams. */ 3029 diff = rom->ht40_2s_tx_pwr_diff[group]; 3030 diff = (diff >> (chain * 4)) & 0xf; 3031 htpow = (htpow > diff) ? htpow - diff : 0; 3032 } 3033 3034 /* Compute per-OFDM rate Tx power. */ 3035 diff = rom->ofdm_tx_pwr_diff[group]; 3036 diff = (diff >> (chain * 4)) & 0xf; 3037 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3038 for (ridx = 4; ridx <= 11; ridx++) { 3039 power[ridx] += ofdmpow; 3040 if (power[ridx] > R92C_MAX_TX_PWR) 3041 power[ridx] = R92C_MAX_TX_PWR; 3042 } 3043 3044 /* Compute per-MCS Tx power. */ 3045 if (extc == NULL) { 3046 diff = rom->ht20_tx_pwr_diff[group]; 3047 diff = (diff >> (chain * 4)) & 0xf; 3048 htpow += diff; /* HT40->HT20 correction. */ 3049 } 3050 for (ridx = 12; ridx <= 27; ridx++) { 3051 power[ridx] += htpow; 3052 if (power[ridx] > R92C_MAX_TX_PWR) 3053 power[ridx] = R92C_MAX_TX_PWR; 3054 } 3055 #ifdef RTWN_DEBUG 3056 if (rtwn_debug >= 4) { 3057 /* Dump per-rate Tx power values. */ 3058 printf("Tx power for chain %d:\n", chain); 3059 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3060 printf("Rate %d = %u\n", ridx, power[ridx]); 3061 } 3062 #endif 3063 } 3064 3065 static void 3066 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3067 struct ieee80211_channel *extc) 3068 { 3069 uint16_t power[RTWN_RIDX_COUNT]; 3070 int i; 3071 3072 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3073 3074 for (i = 0; i < sc->ntxchains; i++) { 3075 /* Compute per-rate Tx power values. */ 3076 rtwn_get_txpower(sc, i, c, extc, power); 3077 /* Write per-rate Tx power values to hardware. */ 3078 rtwn_write_txpower(sc, i, power); 3079 } 3080 } 3081 3082 static void 3083 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3084 struct ieee80211_channel *extc) 3085 { 3086 struct ieee80211com *ic = &sc->sc_ic; 3087 u_int chan; 3088 int i; 3089 3090 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3091 3092 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3093 3094 /* Set Tx power for this new channel. */ 3095 rtwn_set_txpower(sc, c, extc); 3096 3097 for (i = 0; i < sc->nrxchains; i++) { 3098 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3099 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3100 } 3101 #ifndef IEEE80211_NO_HT 3102 if (extc != NULL) { 3103 uint32_t reg; 3104 3105 /* Is secondary channel below or above primary? */ 3106 int prichlo = c->ic_freq < extc->ic_freq; 3107 3108 rtwn_write_1(sc, R92C_BWOPMODE, 3109 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3110 3111 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3112 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3113 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3114 3115 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3116 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3117 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3118 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3119 3120 /* Set CCK side band. */ 3121 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3122 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3123 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3124 3125 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3126 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3127 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3128 3129 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3130 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3131 ~R92C_FPGA0_ANAPARAM2_CBW20); 3132 3133 reg = rtwn_bb_read(sc, 0x818); 3134 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3135 rtwn_bb_write(sc, 0x818, reg); 3136 3137 /* Select 40MHz bandwidth. */ 3138 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3139 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3140 } else 3141 #endif 3142 { 3143 rtwn_write_1(sc, R92C_BWOPMODE, 3144 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3145 3146 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3147 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3148 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3149 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3150 3151 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3152 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3153 R92C_FPGA0_ANAPARAM2_CBW20); 3154 3155 /* Select 20MHz bandwidth. */ 3156 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3157 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3158 } 3159 } 3160 3161 static void 3162 rtwn_iq_calib(struct rtwn_softc *sc) 3163 { 3164 3165 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3166 3167 /* XXX */ 3168 } 3169 3170 static void 3171 rtwn_lc_calib(struct rtwn_softc *sc) 3172 { 3173 uint32_t rf_ac[2]; 3174 uint8_t txmode; 3175 int i; 3176 3177 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3178 3179 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3180 if ((txmode & 0x70) != 0) { 3181 /* Disable all continuous Tx. */ 3182 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3183 3184 /* Set RF mode to standby mode. */ 3185 for (i = 0; i < sc->nrxchains; i++) { 3186 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3187 rtwn_rf_write(sc, i, R92C_RF_AC, 3188 RW(rf_ac[i], R92C_RF_AC_MODE, 3189 R92C_RF_AC_MODE_STANDBY)); 3190 } 3191 } else { 3192 /* Block all Tx queues. */ 3193 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3194 } 3195 /* Start calibration. */ 3196 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3197 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3198 3199 /* Give calibration the time to complete. */ 3200 DELAY(100); 3201 3202 /* Restore configuration. */ 3203 if ((txmode & 0x70) != 0) { 3204 /* Restore Tx mode. */ 3205 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3206 /* Restore RF mode. */ 3207 for (i = 0; i < sc->nrxchains; i++) 3208 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3209 } else { 3210 /* Unblock all Tx queues. */ 3211 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3212 } 3213 } 3214 3215 static void 3216 rtwn_temp_calib(struct rtwn_softc *sc) 3217 { 3218 int temp; 3219 3220 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3221 3222 if (sc->thcal_state == 0) { 3223 /* Start measuring temperature. */ 3224 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3225 sc->thcal_state = 1; 3226 return; 3227 } 3228 sc->thcal_state = 0; 3229 3230 /* Read measured temperature. */ 3231 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3232 if (temp == 0) /* Read failed, skip. */ 3233 return; 3234 DPRINTFN(2, ("temperature=%d\n", temp)); 3235 3236 /* 3237 * Redo IQ and LC calibration if temperature changed significantly 3238 * since last calibration. 3239 */ 3240 if (sc->thcal_lctemp == 0) { 3241 /* First calibration is performed in rtwn_init(). */ 3242 sc->thcal_lctemp = temp; 3243 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3244 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3245 sc->thcal_lctemp, temp)); 3246 rtwn_iq_calib(sc); 3247 rtwn_lc_calib(sc); 3248 /* Record temperature of last calibration. */ 3249 sc->thcal_lctemp = temp; 3250 } 3251 } 3252 3253 static int 3254 rtwn_init(struct ifnet *ifp) 3255 { 3256 struct rtwn_softc *sc = ifp->if_softc; 3257 struct ieee80211com *ic = &sc->sc_ic; 3258 uint32_t reg; 3259 int i, error; 3260 3261 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3262 3263 /* Init firmware commands ring. */ 3264 sc->fwcur = 0; 3265 3266 /* Power on adapter. */ 3267 error = rtwn_power_on(sc); 3268 if (error != 0) { 3269 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3270 goto fail; 3271 } 3272 3273 /* Initialize DMA. */ 3274 error = rtwn_dma_init(sc); 3275 if (error != 0) { 3276 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3277 goto fail; 3278 } 3279 3280 /* Set info size in Rx descriptors (in 64-bit words). */ 3281 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3282 3283 /* Disable interrupts. */ 3284 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3285 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3286 3287 /* Set MAC address. */ 3288 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3289 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3290 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3291 3292 /* Set initial network type. */ 3293 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3294 3295 rtwn_rxfilter_init(sc); 3296 3297 reg = rtwn_read_4(sc, R92C_RRSR); 3298 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3299 rtwn_write_4(sc, R92C_RRSR, reg); 3300 3301 /* Set short/long retry limits. */ 3302 rtwn_write_2(sc, R92C_RL, 3303 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3304 3305 /* Initialize EDCA parameters. */ 3306 rtwn_edca_init(sc); 3307 3308 /* Set data and response automatic rate fallback retry counts. */ 3309 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3310 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3311 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3312 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3313 3314 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3315 3316 /* Set ACK timeout. */ 3317 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3318 3319 /* Initialize beacon parameters. */ 3320 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3321 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3322 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3323 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3324 3325 /* Setup AMPDU aggregation. */ 3326 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3327 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3328 3329 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3330 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3331 3332 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3333 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3334 3335 /* Load 8051 microcode. */ 3336 error = rtwn_load_firmware(sc); 3337 if (error != 0) 3338 goto fail; 3339 3340 /* Initialize MAC/BB/RF blocks. */ 3341 rtwn_mac_init(sc); 3342 rtwn_bb_init(sc); 3343 rtwn_rf_init(sc); 3344 3345 /* Turn CCK and OFDM blocks on. */ 3346 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3347 reg |= R92C_RFMOD_CCK_EN; 3348 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3349 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3350 reg |= R92C_RFMOD_OFDM_EN; 3351 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3352 3353 /* Clear per-station keys table. */ 3354 rtwn_cam_init(sc); 3355 3356 /* Enable hardware sequence numbering. */ 3357 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3358 3359 /* Perform LO and IQ calibrations. */ 3360 rtwn_iq_calib(sc); 3361 /* Perform LC calibration. */ 3362 rtwn_lc_calib(sc); 3363 3364 rtwn_pa_bias_init(sc); 3365 3366 /* Initialize GPIO setting. */ 3367 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3368 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3369 3370 /* Fix for lower temperature. */ 3371 rtwn_write_1(sc, 0x15, 0xe9); 3372 3373 /* Set default channel. */ 3374 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3375 3376 /* Clear pending interrupts. */ 3377 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3378 3379 /* Enable interrupts. */ 3380 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3381 3382 /* We're ready to go. */ 3383 ifp->if_flags &= ~IFF_OACTIVE; 3384 ifp->if_flags |= IFF_RUNNING; 3385 3386 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3387 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3388 else 3389 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3390 3391 return 0; 3392 3393 fail: 3394 rtwn_stop(ifp, 1); 3395 return error; 3396 } 3397 3398 static void 3399 rtwn_init_task(void *arg) 3400 { 3401 struct rtwn_softc *sc = arg; 3402 struct ifnet *ifp = GET_IFP(sc); 3403 int s; 3404 3405 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3406 3407 s = splnet(); 3408 3409 rtwn_stop(ifp, 0); 3410 3411 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3412 rtwn_init(ifp); 3413 3414 splx(s); 3415 } 3416 3417 static void 3418 rtwn_stop(struct ifnet *ifp, int disable) 3419 { 3420 struct rtwn_softc *sc = ifp->if_softc; 3421 struct ieee80211com *ic = &sc->sc_ic; 3422 uint16_t reg; 3423 int s, i; 3424 3425 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3426 3427 sc->sc_tx_timer = 0; 3428 ifp->if_timer = 0; 3429 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3430 3431 callout_stop(&sc->scan_to); 3432 callout_stop(&sc->calib_to); 3433 3434 s = splnet(); 3435 3436 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3437 3438 /* Disable interrupts. */ 3439 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3440 3441 /* Pause MAC TX queue */ 3442 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3443 3444 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3445 3446 /* Reset BB state machine */ 3447 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3448 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3449 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3450 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3451 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3452 3453 reg = rtwn_read_2(sc, R92C_CR); 3454 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3455 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3456 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3457 R92C_CR_ENSEC); 3458 rtwn_write_2(sc, R92C_CR, reg); 3459 3460 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3461 rtwn_fw_reset(sc); 3462 3463 /* Reset MAC and Enable 8051 */ 3464 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3465 3466 /* TODO: linux does additional btcoex stuff here */ 3467 3468 /* Disable AFE PLL */ 3469 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3470 /* Enter PFM mode */ 3471 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3472 /* Gated AFE DIG_CLOCK */ 3473 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3474 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3475 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3476 3477 for (i = 0; i < RTWN_NTXQUEUES; i++) 3478 rtwn_reset_tx_list(sc, i); 3479 rtwn_reset_rx_list(sc); 3480 3481 splx(s); 3482 } 3483 3484 static int 3485 rtwn_intr(void *xsc) 3486 { 3487 struct rtwn_softc *sc = xsc; 3488 uint32_t status; 3489 int i; 3490 3491 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3492 return 0; 3493 3494 status = rtwn_read_4(sc, R92C_HISR); 3495 if (status == 0 || status == 0xffffffff) 3496 return 0; 3497 3498 /* Disable interrupts. */ 3499 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3500 3501 /* Ack interrupts. */ 3502 rtwn_write_4(sc, R92C_HISR, status); 3503 3504 /* Vendor driver treats RX errors like ROK... */ 3505 if (status & RTWN_INT_ENABLE_RX) { 3506 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3507 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3508 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3509 3510 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3511 continue; 3512 3513 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3514 } 3515 } 3516 3517 if (status & R92C_IMR_BDOK) 3518 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3519 if (status & R92C_IMR_HIGHDOK) 3520 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3521 if (status & R92C_IMR_MGNTDOK) 3522 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3523 if (status & R92C_IMR_BKDOK) 3524 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3525 if (status & R92C_IMR_BEDOK) 3526 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3527 if (status & R92C_IMR_VIDOK) 3528 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3529 if (status & R92C_IMR_VODOK) 3530 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3531 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3532 struct ifnet *ifp = GET_IFP(sc); 3533 ifp->if_flags &= ~IFF_OACTIVE; 3534 rtwn_start(ifp); 3535 } 3536 3537 /* Enable interrupts. */ 3538 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3539 3540 return 1; 3541 } 3542
Indexes created Thu Oct 02 01:09:59 GMT 2025