if_rtwn.c revision 1.1.2.3
1 /* $NetBSD: if_rtwn.c,v 1.1.2.3 2015/12/27 12:09:50 skrll Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.1.2.3 2015/12/27 12:09:50 skrll Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 178 /* Aliases. */ 179 #define rtwn_bb_write rtwn_write_4 180 #define rtwn_bb_read rtwn_read_4 181 182 static const struct rtwn_device * 183 rtwn_lookup(const struct pci_attach_args *pa) 184 { 185 const struct rtwn_device *rd; 186 int i; 187 188 for (i = 0; i < __arraycount(rtwn_devices); i++) { 189 rd = &rtwn_devices[i]; 190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 191 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 192 return rd; 193 } 194 return NULL; 195 } 196 197 static int 198 rtwn_match(device_t parent, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 202 if (rtwn_lookup(pa) != NULL) 203 return 1; 204 return 0; 205 } 206 207 static void 208 rtwn_attach(device_t parent, device_t self, void *aux) 209 { 210 struct rtwn_softc *sc = device_private(self); 211 struct pci_attach_args *pa = aux; 212 struct ieee80211com *ic = &sc->sc_ic; 213 struct ifnet *ifp = GET_IFP(sc); 214 int i, error; 215 pcireg_t memtype; 216 const char *intrstr; 217 char intrbuf[PCI_INTRSTR_LEN]; 218 219 sc->sc_dev = self; 220 sc->sc_dmat = pa->pa_dmat; 221 sc->sc_pc = pa->pa_pc; 222 sc->sc_tag = pa->pa_tag; 223 224 pci_aprint_devinfo(pa, NULL); 225 226 callout_init(&sc->scan_to, 0); 227 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 228 callout_init(&sc->calib_to, 0); 229 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 230 231 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 232 233 /* Power up the device */ 234 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 235 236 /* Map control/status registers. */ 237 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 238 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 239 &sc->sc_sh, NULL, &sc->sc_mapsize); 240 if (error != 0) { 241 aprint_error_dev(self, "can't map mem space\n"); 242 return; 243 } 244 245 /* Install interrupt handler. */ 246 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 247 aprint_error_dev(self, "can't map interrupt\n"); 248 return; 249 } 250 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 251 sizeof(intrbuf)); 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 253 rtwn_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(self, "can't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 return; 260 } 261 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 262 263 error = rtwn_read_chipid(sc); 264 if (error != 0) { 265 aprint_error_dev(self, "unsupported test or unknown chip\n"); 266 return; 267 } 268 269 /* Disable PCIe Active State Power Management (ASPM). */ 270 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 271 &sc->sc_cap_off, NULL)) { 272 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 273 sc->sc_cap_off + PCIE_LCSR); 274 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 275 pci_conf_write(sc->sc_pc, sc->sc_tag, 276 sc->sc_cap_off + PCIE_LCSR, lcsr); 277 } 278 279 /* Allocate Tx/Rx buffers. */ 280 error = rtwn_alloc_rx_list(sc); 281 if (error != 0) { 282 aprint_error_dev(self, "could not allocate Rx buffers\n"); 283 return; 284 } 285 for (i = 0; i < RTWN_NTXQUEUES; i++) { 286 error = rtwn_alloc_tx_list(sc, i); 287 if (error != 0) { 288 aprint_error_dev(self, 289 "could not allocate Tx buffers\n"); 290 return; 291 } 292 } 293 294 /* Determine number of Tx/Rx chains. */ 295 if (sc->chip & RTWN_CHIP_92C) { 296 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 297 sc->nrxchains = 2; 298 } else { 299 sc->ntxchains = 1; 300 sc->nrxchains = 1; 301 } 302 rtwn_read_rom(sc); 303 304 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 305 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 306 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 307 308 /* 309 * Setup the 802.11 device. 310 */ 311 ic->ic_ifp = ifp; 312 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 313 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 314 ic->ic_state = IEEE80211_S_INIT; 315 316 /* Set device capabilities. */ 317 ic->ic_caps = 318 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 319 IEEE80211_C_IBSS | /* IBSS mode supported */ 320 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 321 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 322 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 323 IEEE80211_C_WME | /* 802.11e */ 324 IEEE80211_C_WPA; /* WPA/RSN. */ 325 326 #ifndef IEEE80211_NO_HT 327 /* Set HT capabilities. */ 328 ic->ic_htcaps = 329 IEEE80211_HTCAP_CBW20_40 | 330 IEEE80211_HTCAP_DSSSCCK40; 331 /* Set supported HT rates. */ 332 for (i = 0; i < sc->nrxchains; i++) 333 ic->ic_sup_mcs[i] = 0xff; 334 #endif 335 336 /* Set supported .11b and .11g rates. */ 337 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 338 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 339 340 /* Set supported .11b and .11g channels (1 through 14). */ 341 for (i = 1; i <= 14; i++) { 342 ic->ic_channels[i].ic_freq = 343 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 344 ic->ic_channels[i].ic_flags = 345 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 346 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 347 } 348 349 ifp->if_softc = sc; 350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 351 ifp->if_init = rtwn_init; 352 ifp->if_ioctl = rtwn_ioctl; 353 ifp->if_start = rtwn_start; 354 ifp->if_watchdog = rtwn_watchdog; 355 IFQ_SET_READY(&ifp->if_snd); 356 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 357 358 if_initialize(ifp); 359 ieee80211_ifattach(ic); 360 if_register(ifp); 361 362 /* override default methods */ 363 ic->ic_newassoc = rtwn_newassoc; 364 ic->ic_reset = rtwn_reset; 365 ic->ic_wme.wme_update = rtwn_wme_update; 366 367 /* Override state transition machine. */ 368 sc->sc_newstate = ic->ic_newstate; 369 ic->ic_newstate = rtwn_newstate; 370 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 371 372 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 373 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 374 &sc->sc_drvbpf); 375 376 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 377 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 378 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 379 380 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 381 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 382 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 383 384 ieee80211_announce(ic); 385 386 if (!pmf_device_register(self, NULL, NULL)) 387 aprint_error_dev(self, "couldn't establish power handler\n"); 388 } 389 390 static int 391 rtwn_detach(device_t self, int flags) 392 { 393 struct rtwn_softc *sc = device_private(self); 394 struct ieee80211com *ic = &sc->sc_ic; 395 struct ifnet *ifp = GET_IFP(sc); 396 int s, i; 397 398 callout_stop(&sc->scan_to); 399 callout_stop(&sc->calib_to); 400 401 s = splnet(); 402 403 if (ifp->if_softc != NULL) { 404 rtwn_stop(ifp, 0); 405 406 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 407 bpf_detach(ifp); 408 ieee80211_ifdetach(ic); 409 if_detach(ifp); 410 } 411 412 /* Free Tx/Rx buffers. */ 413 for (i = 0; i < RTWN_NTXQUEUES; i++) 414 rtwn_free_tx_list(sc, i); 415 rtwn_free_rx_list(sc); 416 417 splx(s); 418 419 callout_destroy(&sc->scan_to); 420 callout_destroy(&sc->calib_to); 421 422 if (sc->init_task != NULL) 423 softint_disestablish(sc->init_task); 424 425 if (sc->sc_ih != NULL) { 426 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 427 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 428 } 429 430 pmf_device_deregister(self); 431 432 return 0; 433 } 434 435 static int 436 rtwn_activate(device_t self, enum devact act) 437 { 438 struct rtwn_softc *sc = device_private(self); 439 struct ifnet *ifp = GET_IFP(sc); 440 441 switch (act) { 442 case DVACT_DEACTIVATE: 443 if (ifp->if_flags & IFF_RUNNING) 444 rtwn_stop(ifp, 0); 445 return 0; 446 default: 447 return EOPNOTSUPP; 448 } 449 } 450 451 static void 452 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 453 bus_addr_t addr, size_t len, int idx) 454 { 455 456 memset(desc, 0, sizeof(*desc)); 457 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 458 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 459 desc->rxbufaddr = htole32(addr); 460 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 461 BUS_SPACE_BARRIER_WRITE); 462 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 463 } 464 465 static int 466 rtwn_alloc_rx_list(struct rtwn_softc *sc) 467 { 468 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 469 struct rtwn_rx_data *rx_data; 470 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 471 int i, error = 0; 472 473 /* Allocate Rx descriptors. */ 474 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 475 &rx_ring->map); 476 if (error != 0) { 477 aprint_error_dev(sc->sc_dev, 478 "could not create rx desc DMA map\n"); 479 rx_ring->map = NULL; 480 goto fail; 481 } 482 483 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 484 &rx_ring->nsegs, BUS_DMA_NOWAIT); 485 if (error != 0) { 486 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 487 goto fail; 488 } 489 490 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 491 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 492 if (error != 0) { 493 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 494 rx_ring->desc = NULL; 495 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 496 goto fail; 497 } 498 memset(rx_ring->desc, 0, size); 499 500 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 501 1, size, BUS_DMA_NOWAIT); 502 if (error != 0) { 503 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 504 goto fail; 505 } 506 507 /* Allocate Rx buffers. */ 508 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 509 rx_data = &rx_ring->rx_data[i]; 510 511 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 512 0, BUS_DMA_NOWAIT, &rx_data->map); 513 if (error != 0) { 514 aprint_error_dev(sc->sc_dev, 515 "could not create rx buf DMA map\n"); 516 goto fail; 517 } 518 519 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 520 if (__predict_false(rx_data->m == NULL)) { 521 aprint_error_dev(sc->sc_dev, 522 "couldn't allocate rx mbuf\n"); 523 error = ENOMEM; 524 goto fail; 525 } 526 MCLGET(rx_data->m, M_DONTWAIT); 527 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 528 aprint_error_dev(sc->sc_dev, 529 "couldn't allocate rx mbuf cluster\n"); 530 m_free(rx_data->m); 531 rx_data->m = NULL; 532 error = ENOMEM; 533 goto fail; 534 } 535 536 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 537 mtod(rx_data->m, void *), MCLBYTES, NULL, 538 BUS_DMA_NOWAIT | BUS_DMA_READ); 539 if (error != 0) { 540 aprint_error_dev(sc->sc_dev, 541 "could not load rx buf DMA map\n"); 542 goto fail; 543 } 544 545 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 546 BUS_DMASYNC_PREREAD); 547 548 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 549 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 550 } 551 fail: if (error != 0) 552 rtwn_free_rx_list(sc); 553 return error; 554 } 555 556 static void 557 rtwn_reset_rx_list(struct rtwn_softc *sc) 558 { 559 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 560 struct rtwn_rx_data *rx_data; 561 int i; 562 563 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 564 rx_data = &rx_ring->rx_data[i]; 565 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 566 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 567 } 568 } 569 570 static void 571 rtwn_free_rx_list(struct rtwn_softc *sc) 572 { 573 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 574 struct rtwn_rx_data *rx_data; 575 int i, s; 576 577 s = splnet(); 578 579 if (rx_ring->map) { 580 if (rx_ring->desc) { 581 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 582 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 583 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 584 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 585 rx_ring->nsegs); 586 rx_ring->desc = NULL; 587 } 588 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 589 rx_ring->map = NULL; 590 } 591 592 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 593 rx_data = &rx_ring->rx_data[i]; 594 595 if (rx_data->m != NULL) { 596 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 597 m_freem(rx_data->m); 598 rx_data->m = NULL; 599 } 600 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 601 rx_data->map = NULL; 602 } 603 604 splx(s); 605 } 606 607 static int 608 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 609 { 610 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 611 struct rtwn_tx_data *tx_data; 612 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 613 int i = 0, error = 0; 614 615 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 616 &tx_ring->map); 617 if (error != 0) { 618 aprint_error_dev(sc->sc_dev, 619 "could not create tx ring DMA map\n"); 620 goto fail; 621 } 622 623 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 624 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 625 if (error != 0) { 626 aprint_error_dev(sc->sc_dev, 627 "could not allocate tx ring DMA memory\n"); 628 goto fail; 629 } 630 631 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 632 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 633 if (error != 0) { 634 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 635 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 636 goto fail; 637 } 638 memset(tx_ring->desc, 0, size); 639 640 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 641 size, NULL, BUS_DMA_NOWAIT); 642 if (error != 0) { 643 aprint_error_dev(sc->sc_dev, 644 "could not load tx ring DMA map\n"); 645 goto fail; 646 } 647 648 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 649 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 650 651 /* setup tx desc */ 652 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 653 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 654 655 tx_data = &tx_ring->tx_data[i]; 656 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 657 0, BUS_DMA_NOWAIT, &tx_data->map); 658 if (error != 0) { 659 aprint_error_dev(sc->sc_dev, 660 "could not create tx buf DMA map\n"); 661 goto fail; 662 } 663 tx_data->m = NULL; 664 tx_data->ni = NULL; 665 } 666 667 fail: 668 if (error != 0) 669 rtwn_free_tx_list(sc, qid); 670 return error; 671 } 672 673 static void 674 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 675 { 676 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 677 int i; 678 679 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 680 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 681 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 682 683 memset(desc, 0, sizeof(*desc) - 684 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 685 sizeof(desc->nextdescaddr))); 686 687 if (tx_data->m != NULL) { 688 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 689 m_freem(tx_data->m); 690 tx_data->m = NULL; 691 ieee80211_free_node(tx_data->ni); 692 tx_data->ni = NULL; 693 } 694 } 695 696 sc->qfullmsk &= ~(1 << qid); 697 tx_ring->queued = 0; 698 tx_ring->cur = 0; 699 } 700 701 static void 702 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 703 { 704 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 705 struct rtwn_tx_data *tx_data; 706 int i; 707 708 if (tx_ring->map != NULL) { 709 if (tx_ring->desc != NULL) { 710 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 711 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 712 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 713 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 714 tx_ring->nsegs); 715 } 716 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 717 } 718 719 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 720 tx_data = &tx_ring->tx_data[i]; 721 722 if (tx_data->m != NULL) { 723 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 724 m_freem(tx_data->m); 725 tx_data->m = NULL; 726 } 727 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 728 } 729 730 sc->qfullmsk &= ~(1 << qid); 731 tx_ring->queued = 0; 732 tx_ring->cur = 0; 733 } 734 735 static void 736 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 737 { 738 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 739 } 740 741 static void 742 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 743 { 744 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 745 } 746 747 static void 748 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 749 { 750 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 751 } 752 753 static uint8_t 754 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 755 { 756 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 757 } 758 759 static uint16_t 760 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 761 { 762 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 763 } 764 765 static uint32_t 766 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 767 { 768 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 769 } 770 771 static int 772 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 773 { 774 struct r92c_fw_cmd cmd; 775 uint8_t *cp; 776 int fwcur; 777 int ntries; 778 779 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 780 device_xname(sc->sc_dev), __func__, id, buf, len)); 781 782 fwcur = sc->fwcur; 783 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 784 785 /* Wait for current FW box to be empty. */ 786 for (ntries = 0; ntries < 100; ntries++) { 787 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 788 break; 789 DELAY(1); 790 } 791 if (ntries == 100) { 792 aprint_error_dev(sc->sc_dev, 793 "could not send firmware command %d\n", id); 794 return ETIMEDOUT; 795 } 796 797 memset(&cmd, 0, sizeof(cmd)); 798 KASSERT(len <= sizeof(cmd.msg)); 799 memcpy(cmd.msg, buf, len); 800 801 /* Write the first word last since that will trigger the FW. */ 802 cp = (uint8_t *)&cmd; 803 if (len >= 4) { 804 cmd.id = id | R92C_CMD_FLAG_EXT; 805 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 806 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 807 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 808 } else { 809 cmd.id = id; 810 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 811 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 812 } 813 814 /* Give firmware some time for processing. */ 815 DELAY(2000); 816 817 return 0; 818 } 819 820 static void 821 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 822 { 823 824 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 825 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 826 } 827 828 static uint32_t 829 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 830 { 831 uint32_t reg[R92C_MAX_CHAINS], val; 832 833 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 834 if (chain != 0) 835 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 836 837 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 838 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 839 DELAY(1000); 840 841 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 842 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 843 R92C_HSSI_PARAM2_READ_EDGE); 844 DELAY(1000); 845 846 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 847 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 848 DELAY(1000); 849 850 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 851 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 852 else 853 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 854 return MS(val, R92C_LSSI_READBACK_DATA); 855 } 856 857 static int 858 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 859 { 860 int ntries; 861 862 rtwn_write_4(sc, R92C_LLT_INIT, 863 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 864 SM(R92C_LLT_INIT_ADDR, addr) | 865 SM(R92C_LLT_INIT_DATA, data)); 866 /* Wait for write operation to complete. */ 867 for (ntries = 0; ntries < 20; ntries++) { 868 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 869 R92C_LLT_INIT_OP_NO_ACTIVE) 870 return 0; 871 DELAY(5); 872 } 873 return ETIMEDOUT; 874 } 875 876 static uint8_t 877 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 878 { 879 uint32_t reg; 880 int ntries; 881 882 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 883 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 884 reg &= ~R92C_EFUSE_CTRL_VALID; 885 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 886 /* Wait for read operation to complete. */ 887 for (ntries = 0; ntries < 100; ntries++) { 888 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 889 if (reg & R92C_EFUSE_CTRL_VALID) 890 return MS(reg, R92C_EFUSE_CTRL_DATA); 891 DELAY(5); 892 } 893 aprint_error_dev(sc->sc_dev, 894 "could not read efuse byte at address 0x%x\n", addr); 895 return 0xff; 896 } 897 898 static void 899 rtwn_efuse_read(struct rtwn_softc *sc) 900 { 901 uint8_t *rom = (uint8_t *)&sc->rom; 902 uint32_t reg; 903 uint16_t addr = 0; 904 uint8_t off, msk; 905 int i; 906 907 rtwn_efuse_switch_power(sc); 908 909 memset(&sc->rom, 0xff, sizeof(sc->rom)); 910 while (addr < 512) { 911 reg = rtwn_efuse_read_1(sc, addr); 912 if (reg == 0xff) 913 break; 914 addr++; 915 off = reg >> 4; 916 msk = reg & 0xf; 917 for (i = 0; i < 4; i++) { 918 if (msk & (1 << i)) 919 continue; 920 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 921 addr++; 922 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 923 addr++; 924 } 925 } 926 #ifdef RTWN_DEBUG 927 if (rtwn_debug >= 2) { 928 /* Dump ROM content. */ 929 printf("\n"); 930 for (i = 0; i < sizeof(sc->rom); i++) 931 printf("%02x:", rom[i]); 932 printf("\n"); 933 } 934 #endif 935 } 936 937 static void 938 rtwn_efuse_switch_power(struct rtwn_softc *sc) 939 { 940 uint32_t reg; 941 942 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 943 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 944 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 945 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 946 } 947 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 948 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 949 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 950 reg | R92C_SYS_FUNC_EN_ELDR); 951 } 952 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 953 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 954 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 955 rtwn_write_2(sc, R92C_SYS_CLKR, 956 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 957 } 958 } 959 960 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 961 static int 962 rtwn_read_chipid(struct rtwn_softc *sc) 963 { 964 uint32_t reg; 965 966 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 967 968 reg = rtwn_read_4(sc, R92C_SYS_CFG); 969 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 970 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 971 /* Unsupported test chip. */ 972 return EIO; 973 974 if (reg & R92C_SYS_CFG_TYPE_92C) { 975 sc->chip |= RTWN_CHIP_92C; 976 /* Check if it is a castrated 8192C. */ 977 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 978 R92C_HPON_FSM_CHIP_BONDING_ID) == 979 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 980 sc->chip |= RTWN_CHIP_92C_1T2R; 981 } 982 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 983 sc->chip |= RTWN_CHIP_UMC; 984 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 985 sc->chip |= RTWN_CHIP_UMC_A_CUT; 986 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 987 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 988 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 989 else 990 /* Unsupported unknown chip. */ 991 return EIO; 992 } 993 return 0; 994 } 995 996 static void 997 rtwn_read_rom(struct rtwn_softc *sc) 998 { 999 struct ieee80211com *ic = &sc->sc_ic; 1000 struct r92c_rom *rom = &sc->rom; 1001 1002 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1003 1004 /* Read full ROM image. */ 1005 rtwn_efuse_read(sc); 1006 1007 if (rom->id != 0x8129) { 1008 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1009 rom->id); 1010 } 1011 1012 /* XXX Weird but this is what the vendor driver does. */ 1013 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1014 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1015 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1016 1017 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1018 sc->pa_setting, sc->board_type, sc->regulatory)); 1019 1020 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1021 } 1022 1023 static int 1024 rtwn_media_change(struct ifnet *ifp) 1025 { 1026 int error; 1027 1028 error = ieee80211_media_change(ifp); 1029 if (error != ENETRESET) 1030 return error; 1031 1032 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1033 (IFF_UP | IFF_RUNNING)) { 1034 rtwn_stop(ifp, 0); 1035 error = rtwn_init(ifp); 1036 } 1037 return error; 1038 } 1039 1040 /* 1041 * Initialize rate adaptation in firmware. 1042 */ 1043 static int 1044 rtwn_ra_init(struct rtwn_softc *sc) 1045 { 1046 static const uint8_t map[] = { 1047 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1048 }; 1049 struct ieee80211com *ic = &sc->sc_ic; 1050 struct ieee80211_node *ni = ic->ic_bss; 1051 struct ieee80211_rateset *rs = &ni->ni_rates; 1052 struct r92c_fw_cmd_macid_cfg cmd; 1053 uint32_t rates, basicrates; 1054 uint8_t mode; 1055 int maxrate, maxbasicrate, error, i, j; 1056 1057 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1058 1059 /* Get normal and basic rates mask. */ 1060 rates = basicrates = 0; 1061 maxrate = maxbasicrate = 0; 1062 for (i = 0; i < rs->rs_nrates; i++) { 1063 /* Convert 802.11 rate to HW rate index. */ 1064 for (j = 0; j < __arraycount(map); j++) 1065 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1066 break; 1067 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1068 continue; 1069 rates |= 1 << j; 1070 if (j > maxrate) 1071 maxrate = j; 1072 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1073 basicrates |= 1 << j; 1074 if (j > maxbasicrate) 1075 maxbasicrate = j; 1076 } 1077 } 1078 if (ic->ic_curmode == IEEE80211_MODE_11B) 1079 mode = R92C_RAID_11B; 1080 else 1081 mode = R92C_RAID_11BG; 1082 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1083 device_xname(sc->sc_dev), mode, rates, basicrates)); 1084 if (basicrates == 0) 1085 basicrates |= 1; /* add 1Mbps */ 1086 1087 /* Set rates mask for group addressed frames. */ 1088 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1089 cmd.mask = htole32((mode << 28) | basicrates); 1090 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1091 if (error != 0) { 1092 aprint_error_dev(sc->sc_dev, 1093 "could not add broadcast station\n"); 1094 return error; 1095 } 1096 /* Set initial MRR rate. */ 1097 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1098 maxbasicrate)); 1099 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1100 1101 /* Set rates mask for unicast frames. */ 1102 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1103 cmd.mask = htole32((mode << 28) | rates); 1104 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1105 if (error != 0) { 1106 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1107 return error; 1108 } 1109 /* Set initial MRR rate. */ 1110 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1111 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1112 1113 /* Configure Automatic Rate Fallback Register. */ 1114 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1115 if (rates & 0x0c) 1116 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1117 else 1118 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1119 } else 1120 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1121 1122 /* Indicate highest supported rate. */ 1123 ni->ni_txrate = rs->rs_nrates - 1; 1124 return 0; 1125 } 1126 1127 static int 1128 rtwn_get_nettype(struct rtwn_softc *sc) 1129 { 1130 struct ieee80211com *ic = &sc->sc_ic; 1131 int type; 1132 1133 switch (ic->ic_opmode) { 1134 case IEEE80211_M_STA: 1135 type = R92C_CR_NETTYPE_INFRA; 1136 break; 1137 1138 case IEEE80211_M_HOSTAP: 1139 type = R92C_CR_NETTYPE_AP; 1140 break; 1141 1142 case IEEE80211_M_IBSS: 1143 type = R92C_CR_NETTYPE_ADHOC; 1144 break; 1145 1146 default: 1147 type = R92C_CR_NETTYPE_NOLINK; 1148 break; 1149 } 1150 1151 return type; 1152 } 1153 1154 static void 1155 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1156 { 1157 uint32_t reg; 1158 1159 reg = rtwn_read_4(sc, R92C_CR); 1160 reg = RW(reg, R92C_CR_NETTYPE, type); 1161 rtwn_write_4(sc, R92C_CR, reg); 1162 } 1163 1164 static void 1165 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1166 { 1167 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1168 uint64_t tsf; 1169 1170 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1171 1172 /* Enable TSF synchronization. */ 1173 rtwn_write_1(sc, R92C_BCN_CTRL, 1174 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1175 1176 rtwn_write_1(sc, R92C_BCN_CTRL, 1177 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1178 1179 /* Set initial TSF. */ 1180 tsf = ni->ni_tstamp.tsf; 1181 tsf = le64toh(tsf); 1182 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1183 tsf -= IEEE80211_DUR_TU; 1184 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1185 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1186 1187 rtwn_write_1(sc, R92C_BCN_CTRL, 1188 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1189 } 1190 1191 static void 1192 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1193 { 1194 uint8_t reg; 1195 1196 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1197 1198 if (led == RTWN_LED_LINK) { 1199 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1200 if (!on) 1201 reg |= R92C_LEDCFG2_DIS; 1202 else 1203 reg |= R92C_LEDCFG2_EN; 1204 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1205 sc->ledlink = on; /* Save LED state. */ 1206 } 1207 } 1208 1209 static void 1210 rtwn_calib_to(void *arg) 1211 { 1212 struct rtwn_softc *sc = arg; 1213 struct r92c_fw_cmd_rssi cmd; 1214 1215 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1216 1217 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1218 goto restart_timer; 1219 1220 if (sc->avg_pwdb != -1) { 1221 /* Indicate Rx signal strength to FW for rate adaptation. */ 1222 memset(&cmd, 0, sizeof(cmd)); 1223 cmd.macid = 0; /* BSS. */ 1224 cmd.pwdb = sc->avg_pwdb; 1225 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1226 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1227 } 1228 1229 /* Do temperature compensation. */ 1230 rtwn_temp_calib(sc); 1231 1232 restart_timer: 1233 callout_schedule(&sc->calib_to, mstohz(2000)); 1234 } 1235 1236 static void 1237 rtwn_next_scan(void *arg) 1238 { 1239 struct rtwn_softc *sc = arg; 1240 struct ieee80211com *ic = &sc->sc_ic; 1241 int s; 1242 1243 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1244 1245 s = splnet(); 1246 if (ic->ic_state == IEEE80211_S_SCAN) 1247 ieee80211_next_scan(ic); 1248 splx(s); 1249 } 1250 1251 static void 1252 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1253 { 1254 1255 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1256 1257 /* start with lowest Tx rate */ 1258 ni->ni_txrate = 0; 1259 } 1260 1261 static int 1262 rtwn_reset(struct ifnet *ifp) 1263 { 1264 struct rtwn_softc *sc = ifp->if_softc; 1265 struct ieee80211com *ic = &sc->sc_ic; 1266 1267 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1268 return ENETRESET; 1269 1270 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1271 1272 return 0; 1273 } 1274 1275 static int 1276 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1277 { 1278 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1279 struct ieee80211_node *ni; 1280 enum ieee80211_state ostate = ic->ic_state; 1281 uint32_t reg; 1282 int s; 1283 1284 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1285 1286 s = splnet(); 1287 1288 callout_stop(&sc->scan_to); 1289 callout_stop(&sc->calib_to); 1290 1291 if (ostate != nstate) { 1292 DPRINTF(("%s: %s -> %s\n", __func__, 1293 ieee80211_state_name[ostate], 1294 ieee80211_state_name[nstate])); 1295 } 1296 1297 switch (ostate) { 1298 case IEEE80211_S_INIT: 1299 break; 1300 1301 case IEEE80211_S_SCAN: 1302 if (nstate != IEEE80211_S_SCAN) { 1303 /* 1304 * End of scanning 1305 */ 1306 /* flush 4-AC Queue after site_survey */ 1307 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1308 1309 /* Allow Rx from our BSSID only. */ 1310 rtwn_write_4(sc, R92C_RCR, 1311 rtwn_read_4(sc, R92C_RCR) | 1312 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1313 } 1314 break; 1315 1316 case IEEE80211_S_AUTH: 1317 case IEEE80211_S_ASSOC: 1318 break; 1319 1320 case IEEE80211_S_RUN: 1321 /* Turn link LED off. */ 1322 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1323 1324 /* Set media status to 'No Link'. */ 1325 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1326 1327 /* Stop Rx of data frames. */ 1328 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1329 1330 /* Rest TSF. */ 1331 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1332 1333 /* Disable TSF synchronization. */ 1334 rtwn_write_1(sc, R92C_BCN_CTRL, 1335 rtwn_read_1(sc, R92C_BCN_CTRL) | 1336 R92C_BCN_CTRL_DIS_TSF_UDT0); 1337 1338 /* Back to 20MHz mode */ 1339 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1340 1341 /* Reset EDCA parameters. */ 1342 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1343 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1344 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1345 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1346 1347 /* flush all cam entries */ 1348 rtwn_cam_init(sc); 1349 break; 1350 } 1351 1352 switch (nstate) { 1353 case IEEE80211_S_INIT: 1354 /* Turn link LED off. */ 1355 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1356 break; 1357 1358 case IEEE80211_S_SCAN: 1359 if (ostate != IEEE80211_S_SCAN) { 1360 /* 1361 * Begin of scanning 1362 */ 1363 1364 /* Set gain for scanning. */ 1365 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1366 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1367 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1368 1369 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1370 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1371 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1372 1373 /* Allow Rx from any BSSID. */ 1374 rtwn_write_4(sc, R92C_RCR, 1375 rtwn_read_4(sc, R92C_RCR) & 1376 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1377 1378 /* Stop Rx of data frames. */ 1379 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1380 1381 /* Disable update TSF */ 1382 rtwn_write_1(sc, R92C_BCN_CTRL, 1383 rtwn_read_1(sc, R92C_BCN_CTRL) | 1384 R92C_BCN_CTRL_DIS_TSF_UDT0); 1385 } 1386 1387 /* Make link LED blink during scan. */ 1388 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1389 1390 /* Pause AC Tx queues. */ 1391 rtwn_write_1(sc, R92C_TXPAUSE, 1392 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1393 1394 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1395 1396 /* Start periodic scan. */ 1397 callout_schedule(&sc->scan_to, mstohz(200)); 1398 break; 1399 1400 case IEEE80211_S_AUTH: 1401 /* Set initial gain under link. */ 1402 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1403 #ifdef doaslinux 1404 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1405 #else 1406 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1407 #endif 1408 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1409 1410 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1411 #ifdef doaslinux 1412 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1413 #else 1414 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1415 #endif 1416 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1417 1418 /* Set media status to 'No Link'. */ 1419 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1420 1421 /* Allow Rx from any BSSID. */ 1422 rtwn_write_4(sc, R92C_RCR, 1423 rtwn_read_4(sc, R92C_RCR) & 1424 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1425 1426 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1427 break; 1428 1429 case IEEE80211_S_ASSOC: 1430 break; 1431 1432 case IEEE80211_S_RUN: 1433 ni = ic->ic_bss; 1434 1435 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1436 1437 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1438 /* Back to 20Mhz mode */ 1439 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1440 1441 /* Set media status to 'No Link'. */ 1442 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1443 1444 /* Enable Rx of data frames. */ 1445 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1446 1447 /* Allow Rx from any BSSID. */ 1448 rtwn_write_4(sc, R92C_RCR, 1449 rtwn_read_4(sc, R92C_RCR) & 1450 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1451 1452 /* Accept Rx data/control/management frames */ 1453 rtwn_write_4(sc, R92C_RCR, 1454 rtwn_read_4(sc, R92C_RCR) | 1455 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1456 1457 /* Turn link LED on. */ 1458 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1459 break; 1460 } 1461 1462 /* Set media status to 'Associated'. */ 1463 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1464 1465 /* Set BSSID. */ 1466 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1467 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1468 1469 if (ic->ic_curmode == IEEE80211_MODE_11B) 1470 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1471 else /* 802.11b/g */ 1472 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1473 1474 /* Enable Rx of data frames. */ 1475 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1476 1477 /* Flush all AC queues. */ 1478 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1479 1480 /* Set beacon interval. */ 1481 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1482 1483 switch (ic->ic_opmode) { 1484 case IEEE80211_M_STA: 1485 /* Allow Rx from our BSSID only. */ 1486 rtwn_write_4(sc, R92C_RCR, 1487 rtwn_read_4(sc, R92C_RCR) | 1488 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1489 1490 /* Enable TSF synchronization. */ 1491 rtwn_tsf_sync_enable(sc); 1492 break; 1493 1494 case IEEE80211_M_HOSTAP: 1495 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1496 1497 /* Allow Rx from any BSSID. */ 1498 rtwn_write_4(sc, R92C_RCR, 1499 rtwn_read_4(sc, R92C_RCR) & 1500 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1501 1502 /* Reset TSF timer to zero. */ 1503 reg = rtwn_read_4(sc, R92C_TCR); 1504 reg &= ~0x01; 1505 rtwn_write_4(sc, R92C_TCR, reg); 1506 reg |= 0x01; 1507 rtwn_write_4(sc, R92C_TCR, reg); 1508 break; 1509 1510 case IEEE80211_M_MONITOR: 1511 default: 1512 break; 1513 } 1514 1515 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1516 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1517 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1518 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1519 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1520 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1521 1522 /* Intialize rate adaptation. */ 1523 rtwn_ra_init(sc); 1524 1525 /* Turn link LED on. */ 1526 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1527 1528 /* Reset average RSSI. */ 1529 sc->avg_pwdb = -1; 1530 1531 /* Reset temperature calibration state machine. */ 1532 sc->thcal_state = 0; 1533 sc->thcal_lctemp = 0; 1534 1535 /* Start periodic calibration. */ 1536 callout_schedule(&sc->calib_to, mstohz(2000)); 1537 break; 1538 } 1539 1540 (void)sc->sc_newstate(ic, nstate, arg); 1541 1542 splx(s); 1543 1544 return 0; 1545 } 1546 1547 static int 1548 rtwn_wme_update(struct ieee80211com *ic) 1549 { 1550 static const uint16_t aci2reg[WME_NUM_AC] = { 1551 R92C_EDCA_BE_PARAM, 1552 R92C_EDCA_BK_PARAM, 1553 R92C_EDCA_VI_PARAM, 1554 R92C_EDCA_VO_PARAM 1555 }; 1556 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1557 const struct wmeParams *wmep; 1558 int s, aci, aifs, slottime; 1559 1560 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1561 1562 s = splnet(); 1563 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1564 for (aci = 0; aci < WME_NUM_AC; aci++) { 1565 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1566 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1567 aifs = wmep->wmep_aifsn * slottime + 10; 1568 rtwn_write_4(sc, aci2reg[aci], 1569 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1570 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1571 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1572 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1573 } 1574 splx(s); 1575 1576 return 0; 1577 } 1578 1579 static void 1580 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1581 { 1582 int pwdb; 1583 1584 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1585 1586 /* Convert antenna signal to percentage. */ 1587 if (rssi <= -100 || rssi >= 20) 1588 pwdb = 0; 1589 else if (rssi >= 0) 1590 pwdb = 100; 1591 else 1592 pwdb = 100 + rssi; 1593 if (rate <= 3) { 1594 /* CCK gain is smaller than OFDM/MCS gain. */ 1595 pwdb += 6; 1596 if (pwdb > 100) 1597 pwdb = 100; 1598 if (pwdb <= 14) 1599 pwdb -= 4; 1600 else if (pwdb <= 26) 1601 pwdb -= 8; 1602 else if (pwdb <= 34) 1603 pwdb -= 6; 1604 else if (pwdb <= 42) 1605 pwdb -= 2; 1606 } 1607 if (sc->avg_pwdb == -1) /* Init. */ 1608 sc->avg_pwdb = pwdb; 1609 else if (sc->avg_pwdb < pwdb) 1610 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1611 else 1612 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1613 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1614 } 1615 1616 static int8_t 1617 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1618 { 1619 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1620 struct r92c_rx_phystat *phy; 1621 struct r92c_rx_cck *cck; 1622 uint8_t rpt; 1623 int8_t rssi; 1624 1625 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1626 1627 if (rate <= 3) { 1628 cck = (struct r92c_rx_cck *)physt; 1629 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1630 rpt = (cck->agc_rpt >> 5) & 0x3; 1631 rssi = (cck->agc_rpt & 0x1f) << 1; 1632 } else { 1633 rpt = (cck->agc_rpt >> 6) & 0x3; 1634 rssi = cck->agc_rpt & 0x3e; 1635 } 1636 rssi = cckoff[rpt] - rssi; 1637 } else { /* OFDM/HT. */ 1638 phy = (struct r92c_rx_phystat *)physt; 1639 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1640 } 1641 return rssi; 1642 } 1643 1644 static void 1645 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1646 struct rtwn_rx_data *rx_data, int desc_idx) 1647 { 1648 struct ieee80211com *ic = &sc->sc_ic; 1649 struct ifnet *ifp = IC2IFP(ic); 1650 struct ieee80211_frame *wh; 1651 struct ieee80211_node *ni; 1652 struct r92c_rx_phystat *phy = NULL; 1653 uint32_t rxdw0, rxdw3; 1654 struct mbuf *m, *m1; 1655 uint8_t rate; 1656 int8_t rssi = 0; 1657 int infosz, pktlen, shift, totlen, error; 1658 1659 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1660 1661 rxdw0 = le32toh(rx_desc->rxdw0); 1662 rxdw3 = le32toh(rx_desc->rxdw3); 1663 1664 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1665 /* 1666 * This should not happen since we setup our Rx filter 1667 * to not receive these frames. 1668 */ 1669 ifp->if_ierrors++; 1670 return; 1671 } 1672 1673 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1674 /* 1675 * XXX: This will drop most control packets. Do we really 1676 * want this in IEEE80211_M_MONITOR mode? 1677 */ 1678 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1679 ic->ic_stats.is_rx_tooshort++; 1680 ifp->if_ierrors++; 1681 return; 1682 } 1683 if (__predict_false(pktlen > MCLBYTES)) { 1684 ifp->if_ierrors++; 1685 return; 1686 } 1687 1688 rate = MS(rxdw3, R92C_RXDW3_RATE); 1689 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1690 if (infosz > sizeof(struct r92c_rx_phystat)) 1691 infosz = sizeof(struct r92c_rx_phystat); 1692 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1693 totlen = pktlen + infosz + shift; 1694 1695 /* Get RSSI from PHY status descriptor if present. */ 1696 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1697 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1698 rssi = rtwn_get_rssi(sc, rate, phy); 1699 /* Update our average RSSI. */ 1700 rtwn_update_avgrssi(sc, rate, rssi); 1701 } 1702 1703 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1704 pktlen, rate, infosz, shift, rssi)); 1705 1706 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1707 if (__predict_false(m1 == NULL)) { 1708 ic->ic_stats.is_rx_nobuf++; 1709 ifp->if_ierrors++; 1710 return; 1711 } 1712 MCLGET(m1, M_DONTWAIT); 1713 if (__predict_false(!(m1->m_flags & M_EXT))) { 1714 m_freem(m1); 1715 ic->ic_stats.is_rx_nobuf++; 1716 ifp->if_ierrors++; 1717 return; 1718 } 1719 1720 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1721 BUS_DMASYNC_POSTREAD); 1722 1723 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1724 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1725 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1726 if (error != 0) { 1727 m_freem(m1); 1728 1729 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1730 rx_data->m, BUS_DMA_NOWAIT)) 1731 panic("%s: could not load old RX mbuf", 1732 device_xname(sc->sc_dev)); 1733 1734 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1735 BUS_DMASYNC_PREREAD); 1736 1737 /* Physical address may have changed. */ 1738 rtwn_setup_rx_desc(sc, rx_desc, 1739 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1740 1741 ifp->if_ierrors++; 1742 return; 1743 } 1744 1745 /* Finalize mbuf. */ 1746 m = rx_data->m; 1747 rx_data->m = m1; 1748 m->m_pkthdr.len = m->m_len = totlen; 1749 m->m_pkthdr.rcvif = ifp; 1750 1751 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1752 BUS_DMASYNC_PREREAD); 1753 1754 /* Update RX descriptor. */ 1755 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1756 MCLBYTES, desc_idx); 1757 1758 /* Get ieee80211 frame header. */ 1759 if (rxdw0 & R92C_RXDW0_PHYST) 1760 m_adj(m, infosz + shift); 1761 else 1762 m_adj(m, shift); 1763 wh = mtod(m, struct ieee80211_frame *); 1764 1765 if (__predict_false(sc->sc_drvbpf != NULL)) { 1766 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1767 1768 tap->wr_flags = 0; 1769 /* Map HW rate index to 802.11 rate. */ 1770 tap->wr_flags = 2; 1771 if (!(rxdw3 & R92C_RXDW3_HT)) { 1772 switch (rate) { 1773 /* CCK. */ 1774 case 0: tap->wr_rate = 2; break; 1775 case 1: tap->wr_rate = 4; break; 1776 case 2: tap->wr_rate = 11; break; 1777 case 3: tap->wr_rate = 22; break; 1778 /* OFDM. */ 1779 case 4: tap->wr_rate = 12; break; 1780 case 5: tap->wr_rate = 18; break; 1781 case 6: tap->wr_rate = 24; break; 1782 case 7: tap->wr_rate = 36; break; 1783 case 8: tap->wr_rate = 48; break; 1784 case 9: tap->wr_rate = 72; break; 1785 case 10: tap->wr_rate = 96; break; 1786 case 11: tap->wr_rate = 108; break; 1787 } 1788 } else if (rate >= 12) { /* MCS0~15. */ 1789 /* Bit 7 set means HT MCS instead of rate. */ 1790 tap->wr_rate = 0x80 | (rate - 12); 1791 } 1792 tap->wr_dbm_antsignal = rssi; 1793 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1794 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1795 1796 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1797 } 1798 1799 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1800 1801 /* push the frame up to the 802.11 stack */ 1802 ieee80211_input(ic, m, ni, rssi, 0); 1803 1804 /* Node is no longer needed. */ 1805 ieee80211_free_node(ni); 1806 } 1807 1808 static int 1809 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1810 { 1811 struct ieee80211com *ic = &sc->sc_ic; 1812 struct ieee80211_frame *wh; 1813 struct ieee80211_key *k = NULL; 1814 struct rtwn_tx_ring *tx_ring; 1815 struct rtwn_tx_data *data; 1816 struct r92c_tx_desc *txd; 1817 uint16_t qos, seq; 1818 uint8_t raid, type, tid, qid; 1819 int hasqos, error; 1820 1821 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1822 1823 wh = mtod(m, struct ieee80211_frame *); 1824 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1825 1826 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1827 k = ieee80211_crypto_encap(ic, ni, m); 1828 if (k == NULL) 1829 return ENOBUFS; 1830 1831 wh = mtod(m, struct ieee80211_frame *); 1832 } 1833 1834 if ((hasqos = ieee80211_has_qos(wh))) { 1835 /* data frames in 11n mode */ 1836 qos = ieee80211_get_qos(wh); 1837 tid = qos & IEEE80211_QOS_TID; 1838 qid = TID_TO_WME_AC(tid); 1839 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1840 /* Use AC_VO for management frames. */ 1841 tid = 0; /* compiler happy */ 1842 qid = RTWN_VO_QUEUE; 1843 } else { 1844 /* non-qos data frames */ 1845 tid = R92C_TXDW1_QSEL_BE; 1846 qid = RTWN_BE_QUEUE; 1847 } 1848 1849 /* Grab a Tx buffer from the ring. */ 1850 tx_ring = &sc->tx_ring[qid]; 1851 data = &tx_ring->tx_data[tx_ring->cur]; 1852 if (data->m != NULL) { 1853 m_freem(m); 1854 return ENOBUFS; 1855 } 1856 1857 /* Fill Tx descriptor. */ 1858 txd = &tx_ring->desc[tx_ring->cur]; 1859 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1860 m_freem(m); 1861 return ENOBUFS; 1862 } 1863 1864 txd->txdw0 = htole32( 1865 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1866 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1867 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1868 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1869 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1870 1871 txd->txdw1 = 0; 1872 txd->txdw4 = 0; 1873 txd->txdw5 = 0; 1874 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1875 type == IEEE80211_FC0_TYPE_DATA) { 1876 if (ic->ic_curmode == IEEE80211_MODE_11B) 1877 raid = R92C_RAID_11B; 1878 else 1879 raid = R92C_RAID_11BG; 1880 1881 txd->txdw1 |= htole32( 1882 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1883 SM(R92C_TXDW1_QSEL, tid) | 1884 SM(R92C_TXDW1_RAID, raid) | 1885 R92C_TXDW1_AGGBK); 1886 1887 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1888 /* for 11g */ 1889 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1890 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1891 R92C_TXDW4_HWRTSEN); 1892 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1893 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1894 R92C_TXDW4_HWRTSEN); 1895 } 1896 } 1897 /* Send RTS at OFDM24. */ 1898 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1899 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1900 /* Send data at OFDM54. */ 1901 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1902 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1903 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1904 txd->txdw1 |= htole32( 1905 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1906 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1907 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1908 1909 /* Force CCK1. */ 1910 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1911 /* Use 1Mbps */ 1912 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1913 } else { 1914 txd->txdw1 |= htole32( 1915 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1916 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1917 1918 /* Force CCK1. */ 1919 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1920 /* Use 1Mbps */ 1921 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1922 } 1923 1924 /* Set sequence number (already little endian). */ 1925 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1926 txd->txdseq = htole16(seq); 1927 1928 if (!hasqos) { 1929 /* Use HW sequence numbering for non-QoS frames. */ 1930 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1931 txd->txdseq |= htole16(0x8000); /* WTF? */ 1932 } else 1933 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1934 1935 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1936 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1937 if (error && error != EFBIG) { 1938 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1939 error); 1940 m_freem(m); 1941 return error; 1942 } 1943 if (error != 0) { 1944 /* Too many DMA segments, linearize mbuf. */ 1945 if ((m = m_defrag(m, M_DONTWAIT)) == NULL) { 1946 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1947 return ENOBUFS; 1948 } 1949 1950 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1951 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1952 if (error != 0) { 1953 aprint_error_dev(sc->sc_dev, 1954 "can't map mbuf (error %d)\n", error); 1955 m_freem(m); 1956 return error; 1957 } 1958 } 1959 1960 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1961 txd->txbufsize = htole16(m->m_pkthdr.len); 1962 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1963 BUS_SPACE_BARRIER_WRITE); 1964 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1965 1966 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1967 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1968 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1969 BUS_DMASYNC_PREWRITE); 1970 1971 data->m = m; 1972 data->ni = ni; 1973 1974 if (__predict_false(sc->sc_drvbpf != NULL)) { 1975 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1976 1977 tap->wt_flags = 0; 1978 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1979 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1980 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1981 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1982 1983 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1984 } 1985 1986 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1987 tx_ring->queued++; 1988 1989 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1990 sc->qfullmsk |= (1 << qid); 1991 1992 /* Kick TX. */ 1993 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1994 1995 return 0; 1996 } 1997 1998 static void 1999 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2000 { 2001 struct ieee80211com *ic = &sc->sc_ic; 2002 struct ifnet *ifp = IC2IFP(ic); 2003 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2004 struct rtwn_tx_data *tx_data; 2005 struct r92c_tx_desc *tx_desc; 2006 int i; 2007 2008 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2009 qid)); 2010 2011 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2012 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2014 2015 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2016 tx_data = &tx_ring->tx_data[i]; 2017 if (tx_data->m == NULL) 2018 continue; 2019 2020 tx_desc = &tx_ring->desc[i]; 2021 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2022 continue; 2023 2024 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2025 m_freem(tx_data->m); 2026 tx_data->m = NULL; 2027 ieee80211_free_node(tx_data->ni); 2028 tx_data->ni = NULL; 2029 2030 ifp->if_opackets++; 2031 sc->sc_tx_timer = 0; 2032 tx_ring->queued--; 2033 } 2034 2035 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 2036 sc->qfullmsk &= ~(1 << qid); 2037 } 2038 2039 static void 2040 rtwn_start(struct ifnet *ifp) 2041 { 2042 struct rtwn_softc *sc = ifp->if_softc; 2043 struct ieee80211com *ic = &sc->sc_ic; 2044 struct ether_header *eh; 2045 struct ieee80211_node *ni; 2046 struct mbuf *m; 2047 2048 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2049 return; 2050 2051 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2052 2053 for (;;) { 2054 if (sc->qfullmsk != 0) { 2055 ifp->if_flags |= IFF_OACTIVE; 2056 break; 2057 } 2058 /* Send pending management frames first. */ 2059 IF_DEQUEUE(&ic->ic_mgtq, m); 2060 if (m != NULL) { 2061 ni = (void *)m->m_pkthdr.rcvif; 2062 m->m_pkthdr.rcvif = NULL; 2063 goto sendit; 2064 } 2065 if (ic->ic_state != IEEE80211_S_RUN) 2066 break; 2067 2068 /* Encapsulate and send data frames. */ 2069 IFQ_DEQUEUE(&ifp->if_snd, m); 2070 if (m == NULL) 2071 break; 2072 2073 if (m->m_len < (int)sizeof(*eh) && 2074 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2075 ifp->if_oerrors++; 2076 continue; 2077 } 2078 eh = mtod(m, struct ether_header *); 2079 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2080 if (ni == NULL) { 2081 m_freem(m); 2082 ifp->if_oerrors++; 2083 continue; 2084 } 2085 2086 bpf_mtap(ifp, m); 2087 2088 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2089 ieee80211_free_node(ni); 2090 ifp->if_oerrors++; 2091 continue; 2092 } 2093 sendit: 2094 bpf_mtap3(ic->ic_rawbpf, m); 2095 2096 if (rtwn_tx(sc, m, ni) != 0) { 2097 ieee80211_free_node(ni); 2098 ifp->if_oerrors++; 2099 continue; 2100 } 2101 2102 sc->sc_tx_timer = 5; 2103 ifp->if_timer = 1; 2104 } 2105 2106 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2107 } 2108 2109 static void 2110 rtwn_watchdog(struct ifnet *ifp) 2111 { 2112 struct rtwn_softc *sc = ifp->if_softc; 2113 struct ieee80211com *ic = &sc->sc_ic; 2114 2115 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2116 2117 ifp->if_timer = 0; 2118 2119 if (sc->sc_tx_timer > 0) { 2120 if (--sc->sc_tx_timer == 0) { 2121 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2122 softint_schedule(sc->init_task); 2123 ifp->if_oerrors++; 2124 return; 2125 } 2126 ifp->if_timer = 1; 2127 } 2128 ieee80211_watchdog(ic); 2129 } 2130 2131 static int 2132 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2133 { 2134 struct rtwn_softc *sc = ifp->if_softc; 2135 struct ieee80211com *ic = &sc->sc_ic; 2136 int s, error = 0; 2137 2138 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2139 __func__, cmd, data)); 2140 2141 s = splnet(); 2142 2143 switch (cmd) { 2144 case SIOCSIFFLAGS: 2145 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2146 break; 2147 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2148 case IFF_UP | IFF_RUNNING: 2149 break; 2150 case IFF_UP: 2151 error = rtwn_init(ifp); 2152 if (error != 0) 2153 ifp->if_flags &= ~IFF_UP; 2154 break; 2155 case IFF_RUNNING: 2156 rtwn_stop(ifp, 1); 2157 break; 2158 case 0: 2159 break; 2160 } 2161 break; 2162 2163 case SIOCADDMULTI: 2164 case SIOCDELMULTI: 2165 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2166 /* setup multicast filter, etc */ 2167 error = 0; 2168 } 2169 break; 2170 2171 case SIOCS80211CHANNEL: 2172 error = ieee80211_ioctl(ic, cmd, data); 2173 if (error == ENETRESET && 2174 ic->ic_opmode == IEEE80211_M_MONITOR) { 2175 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2176 (IFF_UP | IFF_RUNNING)) { 2177 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2178 } 2179 error = 0; 2180 } 2181 break; 2182 2183 default: 2184 error = ieee80211_ioctl(ic, cmd, data); 2185 break; 2186 } 2187 2188 if (error == ENETRESET) { 2189 error = 0; 2190 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2191 (IFF_UP | IFF_RUNNING)) { 2192 rtwn_stop(ifp, 0); 2193 error = rtwn_init(ifp); 2194 } 2195 } 2196 2197 splx(s); 2198 2199 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2200 error)); 2201 2202 return error; 2203 } 2204 2205 static int 2206 rtwn_power_on(struct rtwn_softc *sc) 2207 { 2208 uint32_t reg; 2209 int ntries; 2210 2211 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2212 2213 /* Wait for autoload done bit. */ 2214 for (ntries = 0; ntries < 1000; ntries++) { 2215 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2216 break; 2217 DELAY(5); 2218 } 2219 if (ntries == 1000) { 2220 aprint_error_dev(sc->sc_dev, 2221 "timeout waiting for chip autoload\n"); 2222 return ETIMEDOUT; 2223 } 2224 2225 /* Unlock ISO/CLK/Power control register. */ 2226 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2227 2228 /* TODO: check if we need this for 8188CE */ 2229 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2230 /* bt coex */ 2231 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2232 reg |= (R92C_APS_FSMCO_SOP_ABG | 2233 R92C_APS_FSMCO_SOP_AMB | 2234 R92C_APS_FSMCO_XOP_BTCK); 2235 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2236 } 2237 2238 /* Move SPS into PWM mode. */ 2239 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2240 DELAY(100); 2241 2242 /* Set low byte to 0x0f, leave others unchanged. */ 2243 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2244 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2245 2246 /* TODO: check if we need this for 8188CE */ 2247 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2248 /* bt coex */ 2249 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2250 reg &= ~0x00024800; /* XXX magic from linux */ 2251 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2252 } 2253 2254 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2255 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2256 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2257 DELAY(200); 2258 2259 /* TODO: linux does additional btcoex stuff here */ 2260 2261 /* Auto enable WLAN. */ 2262 rtwn_write_2(sc, R92C_APS_FSMCO, 2263 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2264 for (ntries = 0; ntries < 1000; ntries++) { 2265 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2266 R92C_APS_FSMCO_APFM_ONMAC)) 2267 break; 2268 DELAY(5); 2269 } 2270 if (ntries == 1000) { 2271 aprint_error_dev(sc->sc_dev, 2272 "timeout waiting for MAC auto ON\n"); 2273 return ETIMEDOUT; 2274 } 2275 2276 /* Enable radio, GPIO and LED functions. */ 2277 rtwn_write_2(sc, R92C_APS_FSMCO, 2278 R92C_APS_FSMCO_AFSM_PCIE | 2279 R92C_APS_FSMCO_PDN_EN | 2280 R92C_APS_FSMCO_PFM_ALDN); 2281 2282 /* Release RF digital isolation. */ 2283 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2284 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2285 2286 if (sc->chip & RTWN_CHIP_92C) 2287 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2288 else 2289 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2290 2291 rtwn_write_4(sc, R92C_INT_MIG, 0); 2292 2293 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2294 /* bt coex */ 2295 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2296 reg &= 0xfd; /* XXX magic from linux */ 2297 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2298 } 2299 2300 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2301 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2302 2303 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2304 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2305 aprint_error_dev(sc->sc_dev, 2306 "radio is disabled by hardware switch\n"); 2307 return EPERM; /* :-) */ 2308 } 2309 2310 /* Initialize MAC. */ 2311 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2312 rtwn_write_1(sc, R92C_APSD_CTRL, 2313 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2314 for (ntries = 0; ntries < 200; ntries++) { 2315 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2316 R92C_APSD_CTRL_OFF_STATUS)) 2317 break; 2318 DELAY(500); 2319 } 2320 if (ntries == 200) { 2321 aprint_error_dev(sc->sc_dev, 2322 "timeout waiting for MAC initialization\n"); 2323 return ETIMEDOUT; 2324 } 2325 2326 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2327 reg = rtwn_read_2(sc, R92C_CR); 2328 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2329 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2330 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2331 R92C_CR_ENSEC; 2332 rtwn_write_2(sc, R92C_CR, reg); 2333 2334 rtwn_write_1(sc, 0xfe10, 0x19); 2335 2336 return 0; 2337 } 2338 2339 static int 2340 rtwn_llt_init(struct rtwn_softc *sc) 2341 { 2342 int i, error; 2343 2344 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2345 2346 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2347 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2348 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2349 return error; 2350 } 2351 /* NB: 0xff indicates end-of-list. */ 2352 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2353 return error; 2354 /* 2355 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2356 * as ring buffer. 2357 */ 2358 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2359 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2360 return error; 2361 } 2362 /* Make the last page point to the beginning of the ring buffer. */ 2363 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2364 return error; 2365 } 2366 2367 static void 2368 rtwn_fw_reset(struct rtwn_softc *sc) 2369 { 2370 uint16_t reg; 2371 int ntries; 2372 2373 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2374 2375 /* Tell 8051 to reset itself. */ 2376 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2377 2378 /* Wait until 8051 resets by itself. */ 2379 for (ntries = 0; ntries < 100; ntries++) { 2380 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2381 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2382 goto sleep; 2383 DELAY(50); 2384 } 2385 /* Force 8051 reset. */ 2386 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2387 sleep: 2388 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2389 #if 0 2390 /* 2391 * We must sleep for one second to let the firmware settle. 2392 * Accessing registers too early will hang the whole system. 2393 */ 2394 tsleep(®, 0, "rtwnrst", hz); 2395 #else 2396 DELAY(1000 * 1000); 2397 #endif 2398 } 2399 2400 static int 2401 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2402 { 2403 uint32_t reg; 2404 int off, mlen, error = 0, i; 2405 2406 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2407 2408 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2409 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2410 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2411 2412 DELAY(5); 2413 2414 off = R92C_FW_START_ADDR; 2415 while (len > 0) { 2416 if (len > 196) 2417 mlen = 196; 2418 else if (len > 4) 2419 mlen = 4; 2420 else 2421 mlen = 1; 2422 for (i = 0; i < mlen; i++) 2423 rtwn_write_1(sc, off++, buf[i]); 2424 buf += mlen; 2425 len -= mlen; 2426 } 2427 2428 return error; 2429 } 2430 2431 static int 2432 rtwn_load_firmware(struct rtwn_softc *sc) 2433 { 2434 firmware_handle_t fwh; 2435 const struct r92c_fw_hdr *hdr; 2436 const char *name; 2437 u_char *fw, *ptr; 2438 size_t len; 2439 uint32_t reg; 2440 int mlen, ntries, page, error; 2441 2442 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2443 2444 /* Read firmware image from the filesystem. */ 2445 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2446 RTWN_CHIP_UMC_A_CUT) 2447 name = "rtl8192cfwU.bin"; 2448 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2449 name = "rtl8192cfwU_B.bin"; 2450 else 2451 name = "rtl8192cfw.bin"; 2452 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2453 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2454 aprint_error_dev(sc->sc_dev, 2455 "could not read firmware %s (error %d)\n", name, error); 2456 return error; 2457 } 2458 const size_t fwlen = len = firmware_get_size(fwh); 2459 fw = firmware_malloc(len); 2460 if (fw == NULL) { 2461 aprint_error_dev(sc->sc_dev, 2462 "failed to allocate firmware memory (size=%zu)\n", len); 2463 firmware_close(fwh); 2464 return ENOMEM; 2465 } 2466 error = firmware_read(fwh, 0, fw, len); 2467 firmware_close(fwh); 2468 if (error != 0) { 2469 aprint_error_dev(sc->sc_dev, 2470 "failed to read firmware (error %d)\n", error); 2471 firmware_free(fw, fwlen); 2472 return error; 2473 } 2474 2475 if (len < sizeof(*hdr)) { 2476 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2477 error = EINVAL; 2478 goto fail; 2479 } 2480 ptr = fw; 2481 hdr = (const struct r92c_fw_hdr *)ptr; 2482 /* Check if there is a valid FW header and skip it. */ 2483 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2484 (le16toh(hdr->signature) >> 4) == 0x92c) { 2485 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2486 le16toh(hdr->version), le16toh(hdr->subversion), 2487 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2488 ptr += sizeof(*hdr); 2489 len -= sizeof(*hdr); 2490 } 2491 2492 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2493 rtwn_fw_reset(sc); 2494 2495 /* Enable FW download. */ 2496 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2497 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2498 R92C_SYS_FUNC_EN_CPUEN); 2499 rtwn_write_1(sc, R92C_MCUFWDL, 2500 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2501 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2502 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2503 2504 /* Reset the FWDL checksum. */ 2505 rtwn_write_1(sc, R92C_MCUFWDL, 2506 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2507 2508 /* download firmware */ 2509 for (page = 0; len > 0; page++) { 2510 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2511 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2512 if (error != 0) { 2513 aprint_error_dev(sc->sc_dev, 2514 "could not load firmware page %d\n", page); 2515 goto fail; 2516 } 2517 ptr += mlen; 2518 len -= mlen; 2519 } 2520 2521 /* Disable FW download. */ 2522 rtwn_write_1(sc, R92C_MCUFWDL, 2523 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2524 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2525 2526 /* Wait for checksum report. */ 2527 for (ntries = 0; ntries < 1000; ntries++) { 2528 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2529 break; 2530 DELAY(5); 2531 } 2532 if (ntries == 1000) { 2533 aprint_error_dev(sc->sc_dev, 2534 "timeout waiting for checksum report\n"); 2535 error = ETIMEDOUT; 2536 goto fail; 2537 } 2538 2539 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2540 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2541 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2542 2543 /* Wait for firmware readiness. */ 2544 for (ntries = 0; ntries < 1000; ntries++) { 2545 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2546 break; 2547 DELAY(5); 2548 } 2549 if (ntries == 1000) { 2550 aprint_error_dev(sc->sc_dev, 2551 "timeout waiting for firmware readiness\n"); 2552 error = ETIMEDOUT; 2553 goto fail; 2554 } 2555 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2556 2557 fail: 2558 firmware_free(fw, fwlen); 2559 return error; 2560 } 2561 2562 static int 2563 rtwn_dma_init(struct rtwn_softc *sc) 2564 { 2565 uint32_t reg; 2566 int error; 2567 2568 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2569 2570 /* Initialize LLT table. */ 2571 error = rtwn_llt_init(sc); 2572 if (error != 0) 2573 return error; 2574 2575 /* Set number of pages for normal priority queue. */ 2576 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2577 rtwn_write_4(sc, R92C_RQPN, 2578 /* Set number of pages for public queue. */ 2579 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2580 /* Set number of pages for high priority queue. */ 2581 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2582 /* Set number of pages for low priority queue. */ 2583 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2584 /* Load values. */ 2585 R92C_RQPN_LD); 2586 2587 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2588 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2589 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2590 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2591 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2592 2593 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2594 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2595 reg |= 0xF771; 2596 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2597 2598 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2599 2600 /* Configure Tx DMA. */ 2601 rtwn_write_4(sc, R92C_BKQ_DESA, 2602 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2603 rtwn_write_4(sc, R92C_BEQ_DESA, 2604 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2605 rtwn_write_4(sc, R92C_VIQ_DESA, 2606 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2607 rtwn_write_4(sc, R92C_VOQ_DESA, 2608 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2609 rtwn_write_4(sc, R92C_BCNQ_DESA, 2610 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2611 rtwn_write_4(sc, R92C_MGQ_DESA, 2612 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2613 rtwn_write_4(sc, R92C_HQ_DESA, 2614 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2615 2616 /* Configure Rx DMA. */ 2617 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2618 2619 /* Set Tx/Rx transfer page boundary. */ 2620 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2621 2622 /* Set Tx/Rx transfer page size. */ 2623 rtwn_write_1(sc, R92C_PBP, 2624 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2625 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2626 return 0; 2627 } 2628 2629 static void 2630 rtwn_mac_init(struct rtwn_softc *sc) 2631 { 2632 int i; 2633 2634 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2635 2636 /* Write MAC initialization values. */ 2637 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2638 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2639 } 2640 2641 static void 2642 rtwn_bb_init(struct rtwn_softc *sc) 2643 { 2644 const struct rtwn_bb_prog *prog; 2645 uint32_t reg; 2646 int i; 2647 2648 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2649 2650 /* Enable BB and RF. */ 2651 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2652 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2653 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2654 R92C_SYS_FUNC_EN_DIO_RF); 2655 2656 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2657 2658 rtwn_write_1(sc, R92C_RF_CTRL, 2659 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2660 2661 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2662 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2663 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2664 R92C_SYS_FUNC_EN_BBRSTB); 2665 2666 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2667 2668 rtwn_write_4(sc, R92C_LEDCFG0, 2669 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2670 2671 /* Select BB programming. */ 2672 prog = (sc->chip & RTWN_CHIP_92C) ? 2673 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2674 2675 /* Write BB initialization values. */ 2676 for (i = 0; i < prog->count; i++) { 2677 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2678 DELAY(1); 2679 } 2680 2681 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2682 /* 8192C 1T only configuration. */ 2683 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2684 reg = (reg & ~0x00000003) | 0x2; 2685 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2686 2687 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2688 reg = (reg & ~0x00300033) | 0x00200022; 2689 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2690 2691 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2692 reg = (reg & ~0xff000000) | 0x45 << 24; 2693 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2694 2695 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2696 reg = (reg & ~0x000000ff) | 0x23; 2697 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2698 2699 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2700 reg = (reg & ~0x00000030) | 1 << 4; 2701 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2702 2703 reg = rtwn_bb_read(sc, 0xe74); 2704 reg = (reg & ~0x0c000000) | 2 << 26; 2705 rtwn_bb_write(sc, 0xe74, reg); 2706 reg = rtwn_bb_read(sc, 0xe78); 2707 reg = (reg & ~0x0c000000) | 2 << 26; 2708 rtwn_bb_write(sc, 0xe78, reg); 2709 reg = rtwn_bb_read(sc, 0xe7c); 2710 reg = (reg & ~0x0c000000) | 2 << 26; 2711 rtwn_bb_write(sc, 0xe7c, reg); 2712 reg = rtwn_bb_read(sc, 0xe80); 2713 reg = (reg & ~0x0c000000) | 2 << 26; 2714 rtwn_bb_write(sc, 0xe80, reg); 2715 reg = rtwn_bb_read(sc, 0xe88); 2716 reg = (reg & ~0x0c000000) | 2 << 26; 2717 rtwn_bb_write(sc, 0xe88, reg); 2718 } 2719 2720 /* Write AGC values. */ 2721 for (i = 0; i < prog->agccount; i++) { 2722 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2723 prog->agcvals[i]); 2724 DELAY(1); 2725 } 2726 2727 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2728 R92C_HSSI_PARAM2_CCK_HIPWR) 2729 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2730 } 2731 2732 static void 2733 rtwn_rf_init(struct rtwn_softc *sc) 2734 { 2735 const struct rtwn_rf_prog *prog; 2736 uint32_t reg, type; 2737 int i, j, idx, off; 2738 2739 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2740 2741 /* Select RF programming based on board type. */ 2742 if (!(sc->chip & RTWN_CHIP_92C)) { 2743 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2744 prog = rtl8188ce_rf_prog; 2745 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2746 prog = rtl8188ru_rf_prog; 2747 else 2748 prog = rtl8188cu_rf_prog; 2749 } else 2750 prog = rtl8192ce_rf_prog; 2751 2752 for (i = 0; i < sc->nrxchains; i++) { 2753 /* Save RF_ENV control type. */ 2754 idx = i / 2; 2755 off = (i % 2) * 16; 2756 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2757 type = (reg >> off) & 0x10; 2758 2759 /* Set RF_ENV enable. */ 2760 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2761 reg |= 0x100000; 2762 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2763 DELAY(1); 2764 /* Set RF_ENV output high. */ 2765 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2766 reg |= 0x10; 2767 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2768 DELAY(1); 2769 /* Set address and data lengths of RF registers. */ 2770 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2771 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2772 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2773 DELAY(1); 2774 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2775 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2776 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2777 DELAY(1); 2778 2779 /* Write RF initialization values for this chain. */ 2780 for (j = 0; j < prog[i].count; j++) { 2781 if (prog[i].regs[j] >= 0xf9 && 2782 prog[i].regs[j] <= 0xfe) { 2783 /* 2784 * These are fake RF registers offsets that 2785 * indicate a delay is required. 2786 */ 2787 DELAY(50); 2788 continue; 2789 } 2790 rtwn_rf_write(sc, i, prog[i].regs[j], 2791 prog[i].vals[j]); 2792 DELAY(1); 2793 } 2794 2795 /* Restore RF_ENV control type. */ 2796 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2797 reg &= ~(0x10 << off) | (type << off); 2798 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2799 2800 /* Cache RF register CHNLBW. */ 2801 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2802 } 2803 2804 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2805 RTWN_CHIP_UMC_A_CUT) { 2806 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2807 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2808 } 2809 } 2810 2811 static void 2812 rtwn_cam_init(struct rtwn_softc *sc) 2813 { 2814 2815 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2816 2817 /* Invalidate all CAM entries. */ 2818 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2819 } 2820 2821 static void 2822 rtwn_pa_bias_init(struct rtwn_softc *sc) 2823 { 2824 uint8_t reg; 2825 int i; 2826 2827 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2828 2829 for (i = 0; i < sc->nrxchains; i++) { 2830 if (sc->pa_setting & (1 << i)) 2831 continue; 2832 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2833 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2834 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2835 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2836 } 2837 if (!(sc->pa_setting & 0x10)) { 2838 reg = rtwn_read_1(sc, 0x16); 2839 reg = (reg & ~0xf0) | 0x90; 2840 rtwn_write_1(sc, 0x16, reg); 2841 } 2842 } 2843 2844 static void 2845 rtwn_rxfilter_init(struct rtwn_softc *sc) 2846 { 2847 2848 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2849 2850 /* Initialize Rx filter. */ 2851 /* TODO: use better filter for monitor mode. */ 2852 rtwn_write_4(sc, R92C_RCR, 2853 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2854 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2855 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2856 /* Accept all multicast frames. */ 2857 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2858 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2859 /* Accept all management frames. */ 2860 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2861 /* Reject all control frames. */ 2862 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2863 /* Accept all data frames. */ 2864 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2865 } 2866 2867 static void 2868 rtwn_edca_init(struct rtwn_softc *sc) 2869 { 2870 2871 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2872 2873 /* set spec SIFS (used in NAV) */ 2874 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2875 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2876 2877 /* set SIFS CCK/OFDM */ 2878 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2879 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2880 2881 /* TXOP */ 2882 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2883 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2884 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2885 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2886 } 2887 2888 static void 2889 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2890 uint16_t power[RTWN_RIDX_COUNT]) 2891 { 2892 uint32_t reg; 2893 2894 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2895 2896 /* Write per-CCK rate Tx power. */ 2897 if (chain == 0) { 2898 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2899 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2900 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2901 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2902 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2903 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2904 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2905 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2906 } else { 2907 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2908 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2909 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2910 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2911 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2912 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2913 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2914 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2915 } 2916 /* Write per-OFDM rate Tx power. */ 2917 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2918 SM(R92C_TXAGC_RATE06, power[ 4]) | 2919 SM(R92C_TXAGC_RATE09, power[ 5]) | 2920 SM(R92C_TXAGC_RATE12, power[ 6]) | 2921 SM(R92C_TXAGC_RATE18, power[ 7])); 2922 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2923 SM(R92C_TXAGC_RATE24, power[ 8]) | 2924 SM(R92C_TXAGC_RATE36, power[ 9]) | 2925 SM(R92C_TXAGC_RATE48, power[10]) | 2926 SM(R92C_TXAGC_RATE54, power[11])); 2927 /* Write per-MCS Tx power. */ 2928 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2929 SM(R92C_TXAGC_MCS00, power[12]) | 2930 SM(R92C_TXAGC_MCS01, power[13]) | 2931 SM(R92C_TXAGC_MCS02, power[14]) | 2932 SM(R92C_TXAGC_MCS03, power[15])); 2933 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2934 SM(R92C_TXAGC_MCS04, power[16]) | 2935 SM(R92C_TXAGC_MCS05, power[17]) | 2936 SM(R92C_TXAGC_MCS06, power[18]) | 2937 SM(R92C_TXAGC_MCS07, power[19])); 2938 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2939 SM(R92C_TXAGC_MCS08, power[20]) | 2940 SM(R92C_TXAGC_MCS09, power[21]) | 2941 SM(R92C_TXAGC_MCS10, power[22]) | 2942 SM(R92C_TXAGC_MCS11, power[23])); 2943 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2944 SM(R92C_TXAGC_MCS12, power[24]) | 2945 SM(R92C_TXAGC_MCS13, power[25]) | 2946 SM(R92C_TXAGC_MCS14, power[26]) | 2947 SM(R92C_TXAGC_MCS15, power[27])); 2948 } 2949 2950 static void 2951 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2952 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2953 uint16_t power[RTWN_RIDX_COUNT]) 2954 { 2955 struct ieee80211com *ic = &sc->sc_ic; 2956 struct r92c_rom *rom = &sc->rom; 2957 uint16_t cckpow, ofdmpow, htpow, diff, max; 2958 const struct rtwn_txpwr *base; 2959 int ridx, chan, group; 2960 2961 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2962 2963 /* Determine channel group. */ 2964 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2965 if (chan <= 3) 2966 group = 0; 2967 else if (chan <= 9) 2968 group = 1; 2969 else 2970 group = 2; 2971 2972 /* Get original Tx power based on board type and RF chain. */ 2973 if (!(sc->chip & RTWN_CHIP_92C)) { 2974 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2975 base = &rtl8188ru_txagc[chain]; 2976 else 2977 base = &rtl8192cu_txagc[chain]; 2978 } else 2979 base = &rtl8192cu_txagc[chain]; 2980 2981 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2982 if (sc->regulatory == 0) { 2983 for (ridx = 0; ridx <= 3; ridx++) 2984 power[ridx] = base->pwr[0][ridx]; 2985 } 2986 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 2987 if (sc->regulatory == 3) { 2988 power[ridx] = base->pwr[0][ridx]; 2989 /* Apply vendor limits. */ 2990 if (extc != NULL) 2991 max = rom->ht40_max_pwr[group]; 2992 else 2993 max = rom->ht20_max_pwr[group]; 2994 max = (max >> (chain * 4)) & 0xf; 2995 if (power[ridx] > max) 2996 power[ridx] = max; 2997 } else if (sc->regulatory == 1) { 2998 if (extc == NULL) 2999 power[ridx] = base->pwr[group][ridx]; 3000 } else if (sc->regulatory != 2) 3001 power[ridx] = base->pwr[0][ridx]; 3002 } 3003 3004 /* Compute per-CCK rate Tx power. */ 3005 cckpow = rom->cck_tx_pwr[chain][group]; 3006 for (ridx = 0; ridx <= 3; ridx++) { 3007 power[ridx] += cckpow; 3008 if (power[ridx] > R92C_MAX_TX_PWR) 3009 power[ridx] = R92C_MAX_TX_PWR; 3010 } 3011 3012 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3013 if (sc->ntxchains > 1) { 3014 /* Apply reduction for 2 spatial streams. */ 3015 diff = rom->ht40_2s_tx_pwr_diff[group]; 3016 diff = (diff >> (chain * 4)) & 0xf; 3017 htpow = (htpow > diff) ? htpow - diff : 0; 3018 } 3019 3020 /* Compute per-OFDM rate Tx power. */ 3021 diff = rom->ofdm_tx_pwr_diff[group]; 3022 diff = (diff >> (chain * 4)) & 0xf; 3023 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3024 for (ridx = 4; ridx <= 11; ridx++) { 3025 power[ridx] += ofdmpow; 3026 if (power[ridx] > R92C_MAX_TX_PWR) 3027 power[ridx] = R92C_MAX_TX_PWR; 3028 } 3029 3030 /* Compute per-MCS Tx power. */ 3031 if (extc == NULL) { 3032 diff = rom->ht20_tx_pwr_diff[group]; 3033 diff = (diff >> (chain * 4)) & 0xf; 3034 htpow += diff; /* HT40->HT20 correction. */ 3035 } 3036 for (ridx = 12; ridx <= 27; ridx++) { 3037 power[ridx] += htpow; 3038 if (power[ridx] > R92C_MAX_TX_PWR) 3039 power[ridx] = R92C_MAX_TX_PWR; 3040 } 3041 #ifdef RTWN_DEBUG 3042 if (rtwn_debug >= 4) { 3043 /* Dump per-rate Tx power values. */ 3044 printf("Tx power for chain %d:\n", chain); 3045 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3046 printf("Rate %d = %u\n", ridx, power[ridx]); 3047 } 3048 #endif 3049 } 3050 3051 static void 3052 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3053 struct ieee80211_channel *extc) 3054 { 3055 uint16_t power[RTWN_RIDX_COUNT]; 3056 int i; 3057 3058 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3059 3060 for (i = 0; i < sc->ntxchains; i++) { 3061 /* Compute per-rate Tx power values. */ 3062 rtwn_get_txpower(sc, i, c, extc, power); 3063 /* Write per-rate Tx power values to hardware. */ 3064 rtwn_write_txpower(sc, i, power); 3065 } 3066 } 3067 3068 static void 3069 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3070 struct ieee80211_channel *extc) 3071 { 3072 struct ieee80211com *ic = &sc->sc_ic; 3073 u_int chan; 3074 int i; 3075 3076 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3077 3078 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3079 3080 /* Set Tx power for this new channel. */ 3081 rtwn_set_txpower(sc, c, extc); 3082 3083 for (i = 0; i < sc->nrxchains; i++) { 3084 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3085 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3086 } 3087 #ifndef IEEE80211_NO_HT 3088 if (extc != NULL) { 3089 uint32_t reg; 3090 3091 /* Is secondary channel below or above primary? */ 3092 int prichlo = c->ic_freq < extc->ic_freq; 3093 3094 rtwn_write_1(sc, R92C_BWOPMODE, 3095 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3096 3097 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3098 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3099 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3100 3101 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3102 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3103 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3104 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3105 3106 /* Set CCK side band. */ 3107 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3108 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3109 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3110 3111 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3112 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3113 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3114 3115 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3116 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3117 ~R92C_FPGA0_ANAPARAM2_CBW20); 3118 3119 reg = rtwn_bb_read(sc, 0x818); 3120 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3121 rtwn_bb_write(sc, 0x818, reg); 3122 3123 /* Select 40MHz bandwidth. */ 3124 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3125 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3126 } else 3127 #endif 3128 { 3129 rtwn_write_1(sc, R92C_BWOPMODE, 3130 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3131 3132 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3133 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3134 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3135 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3136 3137 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3138 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3139 R92C_FPGA0_ANAPARAM2_CBW20); 3140 3141 /* Select 20MHz bandwidth. */ 3142 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3143 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3144 } 3145 } 3146 3147 static void 3148 rtwn_iq_calib(struct rtwn_softc *sc) 3149 { 3150 3151 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3152 3153 /* XXX */ 3154 } 3155 3156 static void 3157 rtwn_lc_calib(struct rtwn_softc *sc) 3158 { 3159 uint32_t rf_ac[2]; 3160 uint8_t txmode; 3161 int i; 3162 3163 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3164 3165 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3166 if ((txmode & 0x70) != 0) { 3167 /* Disable all continuous Tx. */ 3168 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3169 3170 /* Set RF mode to standby mode. */ 3171 for (i = 0; i < sc->nrxchains; i++) { 3172 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3173 rtwn_rf_write(sc, i, R92C_RF_AC, 3174 RW(rf_ac[i], R92C_RF_AC_MODE, 3175 R92C_RF_AC_MODE_STANDBY)); 3176 } 3177 } else { 3178 /* Block all Tx queues. */ 3179 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3180 } 3181 /* Start calibration. */ 3182 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3183 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3184 3185 /* Give calibration the time to complete. */ 3186 DELAY(100); 3187 3188 /* Restore configuration. */ 3189 if ((txmode & 0x70) != 0) { 3190 /* Restore Tx mode. */ 3191 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3192 /* Restore RF mode. */ 3193 for (i = 0; i < sc->nrxchains; i++) 3194 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3195 } else { 3196 /* Unblock all Tx queues. */ 3197 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3198 } 3199 } 3200 3201 static void 3202 rtwn_temp_calib(struct rtwn_softc *sc) 3203 { 3204 int temp; 3205 3206 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3207 3208 if (sc->thcal_state == 0) { 3209 /* Start measuring temperature. */ 3210 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3211 sc->thcal_state = 1; 3212 return; 3213 } 3214 sc->thcal_state = 0; 3215 3216 /* Read measured temperature. */ 3217 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3218 if (temp == 0) /* Read failed, skip. */ 3219 return; 3220 DPRINTFN(2, ("temperature=%d\n", temp)); 3221 3222 /* 3223 * Redo IQ and LC calibration if temperature changed significantly 3224 * since last calibration. 3225 */ 3226 if (sc->thcal_lctemp == 0) { 3227 /* First calibration is performed in rtwn_init(). */ 3228 sc->thcal_lctemp = temp; 3229 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3230 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3231 sc->thcal_lctemp, temp)); 3232 rtwn_iq_calib(sc); 3233 rtwn_lc_calib(sc); 3234 /* Record temperature of last calibration. */ 3235 sc->thcal_lctemp = temp; 3236 } 3237 } 3238 3239 static int 3240 rtwn_init(struct ifnet *ifp) 3241 { 3242 struct rtwn_softc *sc = ifp->if_softc; 3243 struct ieee80211com *ic = &sc->sc_ic; 3244 uint32_t reg; 3245 int i, error; 3246 3247 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3248 3249 /* Init firmware commands ring. */ 3250 sc->fwcur = 0; 3251 3252 /* Power on adapter. */ 3253 error = rtwn_power_on(sc); 3254 if (error != 0) { 3255 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3256 goto fail; 3257 } 3258 3259 /* Initialize DMA. */ 3260 error = rtwn_dma_init(sc); 3261 if (error != 0) { 3262 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3263 goto fail; 3264 } 3265 3266 /* Set info size in Rx descriptors (in 64-bit words). */ 3267 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3268 3269 /* Disable interrupts. */ 3270 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3271 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3272 3273 /* Set MAC address. */ 3274 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3275 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3276 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3277 3278 /* Set initial network type. */ 3279 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3280 3281 rtwn_rxfilter_init(sc); 3282 3283 reg = rtwn_read_4(sc, R92C_RRSR); 3284 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3285 rtwn_write_4(sc, R92C_RRSR, reg); 3286 3287 /* Set short/long retry limits. */ 3288 rtwn_write_2(sc, R92C_RL, 3289 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3290 3291 /* Initialize EDCA parameters. */ 3292 rtwn_edca_init(sc); 3293 3294 /* Set data and response automatic rate fallback retry counts. */ 3295 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3296 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3297 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3298 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3299 3300 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3301 3302 /* Set ACK timeout. */ 3303 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3304 3305 /* Initialize beacon parameters. */ 3306 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3307 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3308 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3309 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3310 3311 /* Setup AMPDU aggregation. */ 3312 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3313 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3314 3315 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3316 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3317 3318 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3319 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3320 3321 /* Load 8051 microcode. */ 3322 error = rtwn_load_firmware(sc); 3323 if (error != 0) 3324 goto fail; 3325 3326 /* Initialize MAC/BB/RF blocks. */ 3327 rtwn_mac_init(sc); 3328 rtwn_bb_init(sc); 3329 rtwn_rf_init(sc); 3330 3331 /* Turn CCK and OFDM blocks on. */ 3332 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3333 reg |= R92C_RFMOD_CCK_EN; 3334 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3335 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3336 reg |= R92C_RFMOD_OFDM_EN; 3337 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3338 3339 /* Clear per-station keys table. */ 3340 rtwn_cam_init(sc); 3341 3342 /* Enable hardware sequence numbering. */ 3343 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3344 3345 /* Perform LO and IQ calibrations. */ 3346 rtwn_iq_calib(sc); 3347 /* Perform LC calibration. */ 3348 rtwn_lc_calib(sc); 3349 3350 rtwn_pa_bias_init(sc); 3351 3352 /* Initialize GPIO setting. */ 3353 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3354 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3355 3356 /* Fix for lower temperature. */ 3357 rtwn_write_1(sc, 0x15, 0xe9); 3358 3359 /* Set default channel. */ 3360 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3361 3362 /* Clear pending interrupts. */ 3363 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3364 3365 /* Enable interrupts. */ 3366 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3367 3368 /* We're ready to go. */ 3369 ifp->if_flags &= ~IFF_OACTIVE; 3370 ifp->if_flags |= IFF_RUNNING; 3371 3372 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3373 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3374 else 3375 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3376 3377 return 0; 3378 3379 fail: 3380 rtwn_stop(ifp, 1); 3381 return error; 3382 } 3383 3384 static void 3385 rtwn_init_task(void *arg) 3386 { 3387 struct rtwn_softc *sc = arg; 3388 struct ifnet *ifp = GET_IFP(sc); 3389 int s; 3390 3391 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3392 3393 s = splnet(); 3394 3395 rtwn_stop(ifp, 0); 3396 3397 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3398 rtwn_init(ifp); 3399 3400 splx(s); 3401 } 3402 3403 static void 3404 rtwn_stop(struct ifnet *ifp, int disable) 3405 { 3406 struct rtwn_softc *sc = ifp->if_softc; 3407 struct ieee80211com *ic = &sc->sc_ic; 3408 uint16_t reg; 3409 int s, i; 3410 3411 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3412 3413 sc->sc_tx_timer = 0; 3414 ifp->if_timer = 0; 3415 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3416 3417 callout_stop(&sc->scan_to); 3418 callout_stop(&sc->calib_to); 3419 3420 s = splnet(); 3421 3422 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3423 3424 /* Disable interrupts. */ 3425 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3426 3427 /* Pause MAC TX queue */ 3428 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3429 3430 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3431 3432 /* Reset BB state machine */ 3433 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3434 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3435 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3436 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3437 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3438 3439 reg = rtwn_read_2(sc, R92C_CR); 3440 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3441 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3442 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3443 R92C_CR_ENSEC); 3444 rtwn_write_2(sc, R92C_CR, reg); 3445 3446 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3447 rtwn_fw_reset(sc); 3448 3449 /* Reset MAC and Enable 8051 */ 3450 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3451 3452 /* TODO: linux does additional btcoex stuff here */ 3453 3454 /* Disable AFE PLL */ 3455 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3456 /* Enter PFM mode */ 3457 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3458 /* Gated AFE DIG_CLOCK */ 3459 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3460 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3461 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3462 3463 for (i = 0; i < RTWN_NTXQUEUES; i++) 3464 rtwn_reset_tx_list(sc, i); 3465 rtwn_reset_rx_list(sc); 3466 3467 splx(s); 3468 } 3469 3470 static int 3471 rtwn_intr(void *xsc) 3472 { 3473 struct rtwn_softc *sc = xsc; 3474 uint32_t status; 3475 int i; 3476 3477 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3478 return 0; 3479 3480 status = rtwn_read_4(sc, R92C_HISR); 3481 if (status == 0 || status == 0xffffffff) 3482 return 0; 3483 3484 /* Disable interrupts. */ 3485 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3486 3487 /* Ack interrupts. */ 3488 rtwn_write_4(sc, R92C_HISR, status); 3489 3490 /* Vendor driver treats RX errors like ROK... */ 3491 if (status & RTWN_INT_ENABLE_RX) { 3492 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3493 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3494 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3495 3496 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3497 continue; 3498 3499 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3500 } 3501 } 3502 3503 if (status & R92C_IMR_BDOK) 3504 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3505 if (status & R92C_IMR_HIGHDOK) 3506 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3507 if (status & R92C_IMR_MGNTDOK) 3508 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3509 if (status & R92C_IMR_BKDOK) 3510 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3511 if (status & R92C_IMR_BEDOK) 3512 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3513 if (status & R92C_IMR_VIDOK) 3514 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3515 if (status & R92C_IMR_VODOK) 3516 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3517 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3518 struct ifnet *ifp = GET_IFP(sc); 3519 ifp->if_flags &= ~IFF_OACTIVE; 3520 rtwn_start(ifp); 3521 } 3522 3523 /* Enable interrupts. */ 3524 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3525 3526 return 1; 3527 } 3528
Indexes created Thu Oct 02 01:09:59 GMT 2025