if_rtwn.c revision 1.1.2.8
1 /* $NetBSD: if_rtwn.c,v 1.1.2.8 2017/08/28 17:52:05 skrll Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.1.2.8 2017/08/28 17:52:05 skrll Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 static void rtwn_softintr(void *); 178 179 /* Aliases. */ 180 #define rtwn_bb_write rtwn_write_4 181 #define rtwn_bb_read rtwn_read_4 182 183 static const struct rtwn_device * 184 rtwn_lookup(const struct pci_attach_args *pa) 185 { 186 const struct rtwn_device *rd; 187 int i; 188 189 for (i = 0; i < __arraycount(rtwn_devices); i++) { 190 rd = &rtwn_devices[i]; 191 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 192 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 193 return rd; 194 } 195 return NULL; 196 } 197 198 static int 199 rtwn_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (rtwn_lookup(pa) != NULL) 204 return 1; 205 return 0; 206 } 207 208 static void 209 rtwn_attach(device_t parent, device_t self, void *aux) 210 { 211 struct rtwn_softc *sc = device_private(self); 212 struct pci_attach_args *pa = aux; 213 struct ieee80211com *ic = &sc->sc_ic; 214 struct ifnet *ifp = GET_IFP(sc); 215 int i, error; 216 pcireg_t memtype; 217 const char *intrstr; 218 char intrbuf[PCI_INTRSTR_LEN]; 219 220 sc->sc_dev = self; 221 sc->sc_dmat = pa->pa_dmat; 222 sc->sc_pc = pa->pa_pc; 223 sc->sc_tag = pa->pa_tag; 224 225 pci_aprint_devinfo(pa, NULL); 226 227 callout_init(&sc->scan_to, 0); 228 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 229 callout_init(&sc->calib_to, 0); 230 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 231 232 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc); 233 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 234 235 /* Power up the device */ 236 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 237 238 /* Map control/status registers. */ 239 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 240 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 241 &sc->sc_sh, NULL, &sc->sc_mapsize); 242 if (error != 0) { 243 aprint_error_dev(self, "can't map mem space\n"); 244 return; 245 } 246 247 /* Install interrupt handler. */ 248 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 249 aprint_error_dev(self, "can't map interrupt\n"); 250 return; 251 } 252 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 253 sizeof(intrbuf)); 254 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 255 rtwn_intr, sc); 256 if (sc->sc_ih == NULL) { 257 aprint_error_dev(self, "can't establish interrupt"); 258 if (intrstr != NULL) 259 aprint_error(" at %s", intrstr); 260 aprint_error("\n"); 261 return; 262 } 263 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 264 265 error = rtwn_read_chipid(sc); 266 if (error != 0) { 267 aprint_error_dev(self, "unsupported test or unknown chip\n"); 268 return; 269 } 270 271 /* Disable PCIe Active State Power Management (ASPM). */ 272 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 273 &sc->sc_cap_off, NULL)) { 274 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 275 sc->sc_cap_off + PCIE_LCSR); 276 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 277 pci_conf_write(sc->sc_pc, sc->sc_tag, 278 sc->sc_cap_off + PCIE_LCSR, lcsr); 279 } 280 281 /* Allocate Tx/Rx buffers. */ 282 error = rtwn_alloc_rx_list(sc); 283 if (error != 0) { 284 aprint_error_dev(self, "could not allocate Rx buffers\n"); 285 return; 286 } 287 for (i = 0; i < RTWN_NTXQUEUES; i++) { 288 error = rtwn_alloc_tx_list(sc, i); 289 if (error != 0) { 290 aprint_error_dev(self, 291 "could not allocate Tx buffers\n"); 292 return; 293 } 294 } 295 296 /* Determine number of Tx/Rx chains. */ 297 if (sc->chip & RTWN_CHIP_92C) { 298 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 299 sc->nrxchains = 2; 300 } else { 301 sc->ntxchains = 1; 302 sc->nrxchains = 1; 303 } 304 rtwn_read_rom(sc); 305 306 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 307 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 308 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 309 310 /* 311 * Setup the 802.11 device. 312 */ 313 ic->ic_ifp = ifp; 314 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 315 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 316 ic->ic_state = IEEE80211_S_INIT; 317 318 /* Set device capabilities. */ 319 ic->ic_caps = 320 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 321 IEEE80211_C_IBSS | /* IBSS mode supported */ 322 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 323 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 324 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 325 IEEE80211_C_WME | /* 802.11e */ 326 IEEE80211_C_WPA; /* WPA/RSN. */ 327 328 #ifndef IEEE80211_NO_HT 329 /* Set HT capabilities. */ 330 ic->ic_htcaps = 331 IEEE80211_HTCAP_CBW20_40 | 332 IEEE80211_HTCAP_DSSSCCK40; 333 /* Set supported HT rates. */ 334 for (i = 0; i < sc->nrxchains; i++) 335 ic->ic_sup_mcs[i] = 0xff; 336 #endif 337 338 /* Set supported .11b and .11g rates. */ 339 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 340 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 341 342 /* Set supported .11b and .11g channels (1 through 14). */ 343 for (i = 1; i <= 14; i++) { 344 ic->ic_channels[i].ic_freq = 345 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 346 ic->ic_channels[i].ic_flags = 347 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 348 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 349 } 350 351 ifp->if_softc = sc; 352 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 353 ifp->if_init = rtwn_init; 354 ifp->if_ioctl = rtwn_ioctl; 355 ifp->if_start = rtwn_start; 356 ifp->if_watchdog = rtwn_watchdog; 357 IFQ_SET_READY(&ifp->if_snd); 358 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 359 360 if_initialize(ifp); 361 ieee80211_ifattach(ic); 362 /* Use common softint-based if_input */ 363 ifp->if_percpuq = if_percpuq_create(ifp); 364 if_register(ifp); 365 366 /* override default methods */ 367 ic->ic_newassoc = rtwn_newassoc; 368 ic->ic_reset = rtwn_reset; 369 ic->ic_wme.wme_update = rtwn_wme_update; 370 371 /* Override state transition machine. */ 372 sc->sc_newstate = ic->ic_newstate; 373 ic->ic_newstate = rtwn_newstate; 374 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 375 376 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 377 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 378 &sc->sc_drvbpf); 379 380 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 381 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 382 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 383 384 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 385 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 386 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 387 388 ieee80211_announce(ic); 389 390 if (!pmf_device_register(self, NULL, NULL)) 391 aprint_error_dev(self, "couldn't establish power handler\n"); 392 } 393 394 static int 395 rtwn_detach(device_t self, int flags) 396 { 397 struct rtwn_softc *sc = device_private(self); 398 struct ieee80211com *ic = &sc->sc_ic; 399 struct ifnet *ifp = GET_IFP(sc); 400 int s, i; 401 402 callout_stop(&sc->scan_to); 403 callout_stop(&sc->calib_to); 404 405 s = splnet(); 406 407 if (ifp->if_softc != NULL) { 408 rtwn_stop(ifp, 0); 409 410 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 411 bpf_detach(ifp); 412 ieee80211_ifdetach(ic); 413 if_detach(ifp); 414 } 415 416 /* Free Tx/Rx buffers. */ 417 for (i = 0; i < RTWN_NTXQUEUES; i++) 418 rtwn_free_tx_list(sc, i); 419 rtwn_free_rx_list(sc); 420 421 splx(s); 422 423 callout_destroy(&sc->scan_to); 424 callout_destroy(&sc->calib_to); 425 426 if (sc->init_task != NULL) 427 softint_disestablish(sc->init_task); 428 if (sc->sc_soft_ih != NULL) 429 softint_disestablish(sc->sc_soft_ih); 430 431 if (sc->sc_ih != NULL) { 432 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 433 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 434 } 435 436 pmf_device_deregister(self); 437 438 return 0; 439 } 440 441 static int 442 rtwn_activate(device_t self, enum devact act) 443 { 444 struct rtwn_softc *sc = device_private(self); 445 struct ifnet *ifp = GET_IFP(sc); 446 447 switch (act) { 448 case DVACT_DEACTIVATE: 449 if (ifp->if_flags & IFF_RUNNING) 450 rtwn_stop(ifp, 0); 451 return 0; 452 default: 453 return EOPNOTSUPP; 454 } 455 } 456 457 static void 458 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 459 bus_addr_t addr, size_t len, int idx) 460 { 461 462 memset(desc, 0, sizeof(*desc)); 463 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 464 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 465 desc->rxbufaddr = htole32(addr); 466 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 467 BUS_SPACE_BARRIER_WRITE); 468 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 469 } 470 471 static int 472 rtwn_alloc_rx_list(struct rtwn_softc *sc) 473 { 474 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 475 struct rtwn_rx_data *rx_data; 476 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 477 int i, error = 0; 478 479 /* Allocate Rx descriptors. */ 480 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 481 &rx_ring->map); 482 if (error != 0) { 483 aprint_error_dev(sc->sc_dev, 484 "could not create rx desc DMA map\n"); 485 rx_ring->map = NULL; 486 goto fail; 487 } 488 489 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 490 &rx_ring->nsegs, BUS_DMA_NOWAIT); 491 if (error != 0) { 492 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 493 goto fail; 494 } 495 496 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 497 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 498 if (error != 0) { 499 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 500 rx_ring->desc = NULL; 501 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 502 goto fail; 503 } 504 memset(rx_ring->desc, 0, size); 505 506 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 507 1, size, BUS_DMA_NOWAIT); 508 if (error != 0) { 509 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 510 goto fail; 511 } 512 513 /* Allocate Rx buffers. */ 514 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 515 rx_data = &rx_ring->rx_data[i]; 516 517 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 518 0, BUS_DMA_NOWAIT, &rx_data->map); 519 if (error != 0) { 520 aprint_error_dev(sc->sc_dev, 521 "could not create rx buf DMA map\n"); 522 goto fail; 523 } 524 525 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 526 if (__predict_false(rx_data->m == NULL)) { 527 aprint_error_dev(sc->sc_dev, 528 "couldn't allocate rx mbuf\n"); 529 error = ENOMEM; 530 goto fail; 531 } 532 MCLGET(rx_data->m, M_DONTWAIT); 533 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 534 aprint_error_dev(sc->sc_dev, 535 "couldn't allocate rx mbuf cluster\n"); 536 m_free(rx_data->m); 537 rx_data->m = NULL; 538 error = ENOMEM; 539 goto fail; 540 } 541 542 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 543 mtod(rx_data->m, void *), MCLBYTES, NULL, 544 BUS_DMA_NOWAIT | BUS_DMA_READ); 545 if (error != 0) { 546 aprint_error_dev(sc->sc_dev, 547 "could not load rx buf DMA map\n"); 548 goto fail; 549 } 550 551 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 552 BUS_DMASYNC_PREREAD); 553 554 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 555 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 556 } 557 fail: if (error != 0) 558 rtwn_free_rx_list(sc); 559 return error; 560 } 561 562 static void 563 rtwn_reset_rx_list(struct rtwn_softc *sc) 564 { 565 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 566 struct rtwn_rx_data *rx_data; 567 int i; 568 569 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 570 rx_data = &rx_ring->rx_data[i]; 571 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 572 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 573 } 574 } 575 576 static void 577 rtwn_free_rx_list(struct rtwn_softc *sc) 578 { 579 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 580 struct rtwn_rx_data *rx_data; 581 int i, s; 582 583 s = splnet(); 584 585 if (rx_ring->map) { 586 if (rx_ring->desc) { 587 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 588 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 589 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 590 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 591 rx_ring->nsegs); 592 rx_ring->desc = NULL; 593 } 594 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 595 rx_ring->map = NULL; 596 } 597 598 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 599 rx_data = &rx_ring->rx_data[i]; 600 601 if (rx_data->m != NULL) { 602 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 603 m_freem(rx_data->m); 604 rx_data->m = NULL; 605 } 606 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 607 rx_data->map = NULL; 608 } 609 610 splx(s); 611 } 612 613 static int 614 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 615 { 616 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 617 struct rtwn_tx_data *tx_data; 618 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 619 int i = 0, error = 0; 620 621 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 622 &tx_ring->map); 623 if (error != 0) { 624 aprint_error_dev(sc->sc_dev, 625 "could not create tx ring DMA map\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 630 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 631 if (error != 0) { 632 aprint_error_dev(sc->sc_dev, 633 "could not allocate tx ring DMA memory\n"); 634 goto fail; 635 } 636 637 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 638 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 639 if (error != 0) { 640 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 641 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 642 goto fail; 643 } 644 memset(tx_ring->desc, 0, size); 645 646 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 647 size, NULL, BUS_DMA_NOWAIT); 648 if (error != 0) { 649 aprint_error_dev(sc->sc_dev, 650 "could not load tx ring DMA map\n"); 651 goto fail; 652 } 653 654 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 655 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 656 657 /* setup tx desc */ 658 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 659 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 660 661 tx_data = &tx_ring->tx_data[i]; 662 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 663 0, BUS_DMA_NOWAIT, &tx_data->map); 664 if (error != 0) { 665 aprint_error_dev(sc->sc_dev, 666 "could not create tx buf DMA map\n"); 667 goto fail; 668 } 669 tx_data->m = NULL; 670 tx_data->ni = NULL; 671 } 672 673 fail: 674 if (error != 0) 675 rtwn_free_tx_list(sc, qid); 676 return error; 677 } 678 679 static void 680 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 681 { 682 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 683 int i; 684 685 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 686 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 687 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 688 689 memset(desc, 0, sizeof(*desc) - 690 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 691 sizeof(desc->nextdescaddr))); 692 693 if (tx_data->m != NULL) { 694 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 695 m_freem(tx_data->m); 696 tx_data->m = NULL; 697 ieee80211_free_node(tx_data->ni); 698 tx_data->ni = NULL; 699 } 700 } 701 702 sc->qfullmsk &= ~(1 << qid); 703 tx_ring->queued = 0; 704 tx_ring->cur = 0; 705 } 706 707 static void 708 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 709 { 710 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 711 struct rtwn_tx_data *tx_data; 712 int i; 713 714 if (tx_ring->map != NULL) { 715 if (tx_ring->desc != NULL) { 716 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 717 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 718 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 719 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 720 tx_ring->nsegs); 721 } 722 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 723 } 724 725 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 726 tx_data = &tx_ring->tx_data[i]; 727 728 if (tx_data->m != NULL) { 729 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 730 m_freem(tx_data->m); 731 tx_data->m = NULL; 732 } 733 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 734 } 735 736 sc->qfullmsk &= ~(1 << qid); 737 tx_ring->queued = 0; 738 tx_ring->cur = 0; 739 } 740 741 static void 742 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 743 { 744 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 745 } 746 747 static void 748 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 749 { 750 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 751 } 752 753 static void 754 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 755 { 756 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 757 } 758 759 static uint8_t 760 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 761 { 762 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 763 } 764 765 static uint16_t 766 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 767 { 768 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 769 } 770 771 static uint32_t 772 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 773 { 774 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 775 } 776 777 static int 778 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 779 { 780 struct r92c_fw_cmd cmd; 781 uint8_t *cp; 782 int fwcur; 783 int ntries; 784 785 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 786 device_xname(sc->sc_dev), __func__, id, buf, len)); 787 788 fwcur = sc->fwcur; 789 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 790 791 /* Wait for current FW box to be empty. */ 792 for (ntries = 0; ntries < 100; ntries++) { 793 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 794 break; 795 DELAY(1); 796 } 797 if (ntries == 100) { 798 aprint_error_dev(sc->sc_dev, 799 "could not send firmware command %d\n", id); 800 return ETIMEDOUT; 801 } 802 803 memset(&cmd, 0, sizeof(cmd)); 804 KASSERT(len <= sizeof(cmd.msg)); 805 memcpy(cmd.msg, buf, len); 806 807 /* Write the first word last since that will trigger the FW. */ 808 cp = (uint8_t *)&cmd; 809 if (len >= 4) { 810 cmd.id = id | R92C_CMD_FLAG_EXT; 811 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 812 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 813 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 814 } else { 815 cmd.id = id; 816 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 817 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 818 } 819 820 /* Give firmware some time for processing. */ 821 DELAY(2000); 822 823 return 0; 824 } 825 826 static void 827 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 828 { 829 830 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 831 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 832 } 833 834 static uint32_t 835 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 836 { 837 uint32_t reg[R92C_MAX_CHAINS], val; 838 839 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 840 if (chain != 0) 841 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 842 843 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 844 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 845 DELAY(1000); 846 847 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 848 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 849 R92C_HSSI_PARAM2_READ_EDGE); 850 DELAY(1000); 851 852 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 853 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 854 DELAY(1000); 855 856 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 857 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 858 else 859 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 860 return MS(val, R92C_LSSI_READBACK_DATA); 861 } 862 863 static int 864 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 865 { 866 int ntries; 867 868 rtwn_write_4(sc, R92C_LLT_INIT, 869 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 870 SM(R92C_LLT_INIT_ADDR, addr) | 871 SM(R92C_LLT_INIT_DATA, data)); 872 /* Wait for write operation to complete. */ 873 for (ntries = 0; ntries < 20; ntries++) { 874 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 875 R92C_LLT_INIT_OP_NO_ACTIVE) 876 return 0; 877 DELAY(5); 878 } 879 return ETIMEDOUT; 880 } 881 882 static uint8_t 883 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 884 { 885 uint32_t reg; 886 int ntries; 887 888 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 889 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 890 reg &= ~R92C_EFUSE_CTRL_VALID; 891 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 892 /* Wait for read operation to complete. */ 893 for (ntries = 0; ntries < 100; ntries++) { 894 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 895 if (reg & R92C_EFUSE_CTRL_VALID) 896 return MS(reg, R92C_EFUSE_CTRL_DATA); 897 DELAY(5); 898 } 899 aprint_error_dev(sc->sc_dev, 900 "could not read efuse byte at address 0x%x\n", addr); 901 return 0xff; 902 } 903 904 static void 905 rtwn_efuse_read(struct rtwn_softc *sc) 906 { 907 uint8_t *rom = (uint8_t *)&sc->rom; 908 uint32_t reg; 909 uint16_t addr = 0; 910 uint8_t off, msk; 911 int i; 912 913 rtwn_efuse_switch_power(sc); 914 915 memset(&sc->rom, 0xff, sizeof(sc->rom)); 916 while (addr < 512) { 917 reg = rtwn_efuse_read_1(sc, addr); 918 if (reg == 0xff) 919 break; 920 addr++; 921 off = reg >> 4; 922 msk = reg & 0xf; 923 for (i = 0; i < 4; i++) { 924 if (msk & (1 << i)) 925 continue; 926 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 927 addr++; 928 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 929 addr++; 930 } 931 } 932 #ifdef RTWN_DEBUG 933 if (rtwn_debug >= 2) { 934 /* Dump ROM content. */ 935 printf("\n"); 936 for (i = 0; i < sizeof(sc->rom); i++) 937 printf("%02x:", rom[i]); 938 printf("\n"); 939 } 940 #endif 941 } 942 943 static void 944 rtwn_efuse_switch_power(struct rtwn_softc *sc) 945 { 946 uint32_t reg; 947 948 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 949 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 950 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 951 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 952 } 953 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 954 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 955 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 956 reg | R92C_SYS_FUNC_EN_ELDR); 957 } 958 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 959 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 960 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 961 rtwn_write_2(sc, R92C_SYS_CLKR, 962 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 963 } 964 } 965 966 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 967 static int 968 rtwn_read_chipid(struct rtwn_softc *sc) 969 { 970 uint32_t reg; 971 972 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 973 974 reg = rtwn_read_4(sc, R92C_SYS_CFG); 975 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 976 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 977 /* Unsupported test chip. */ 978 return EIO; 979 980 if (reg & R92C_SYS_CFG_TYPE_92C) { 981 sc->chip |= RTWN_CHIP_92C; 982 /* Check if it is a castrated 8192C. */ 983 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 984 R92C_HPON_FSM_CHIP_BONDING_ID) == 985 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 986 sc->chip |= RTWN_CHIP_92C_1T2R; 987 } 988 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 989 sc->chip |= RTWN_CHIP_UMC; 990 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 991 sc->chip |= RTWN_CHIP_UMC_A_CUT; 992 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 993 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 994 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 995 else 996 /* Unsupported unknown chip. */ 997 return EIO; 998 } 999 return 0; 1000 } 1001 1002 static void 1003 rtwn_read_rom(struct rtwn_softc *sc) 1004 { 1005 struct ieee80211com *ic = &sc->sc_ic; 1006 struct r92c_rom *rom = &sc->rom; 1007 1008 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1009 1010 /* Read full ROM image. */ 1011 rtwn_efuse_read(sc); 1012 1013 if (rom->id != 0x8129) { 1014 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1015 rom->id); 1016 } 1017 1018 /* XXX Weird but this is what the vendor driver does. */ 1019 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1020 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1021 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1022 1023 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1024 sc->pa_setting, sc->board_type, sc->regulatory)); 1025 1026 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1027 } 1028 1029 static int 1030 rtwn_media_change(struct ifnet *ifp) 1031 { 1032 int error; 1033 1034 error = ieee80211_media_change(ifp); 1035 if (error != ENETRESET) 1036 return error; 1037 1038 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1039 (IFF_UP | IFF_RUNNING)) { 1040 rtwn_stop(ifp, 0); 1041 error = rtwn_init(ifp); 1042 } 1043 return error; 1044 } 1045 1046 /* 1047 * Initialize rate adaptation in firmware. 1048 */ 1049 static int 1050 rtwn_ra_init(struct rtwn_softc *sc) 1051 { 1052 static const uint8_t map[] = { 1053 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1054 }; 1055 struct ieee80211com *ic = &sc->sc_ic; 1056 struct ieee80211_node *ni = ic->ic_bss; 1057 struct ieee80211_rateset *rs = &ni->ni_rates; 1058 struct r92c_fw_cmd_macid_cfg cmd; 1059 uint32_t rates, basicrates; 1060 uint8_t mode; 1061 int maxrate, maxbasicrate, error, i, j; 1062 1063 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1064 1065 /* Get normal and basic rates mask. */ 1066 rates = basicrates = 0; 1067 maxrate = maxbasicrate = 0; 1068 for (i = 0; i < rs->rs_nrates; i++) { 1069 /* Convert 802.11 rate to HW rate index. */ 1070 for (j = 0; j < __arraycount(map); j++) 1071 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1072 break; 1073 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1074 continue; 1075 rates |= 1 << j; 1076 if (j > maxrate) 1077 maxrate = j; 1078 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1079 basicrates |= 1 << j; 1080 if (j > maxbasicrate) 1081 maxbasicrate = j; 1082 } 1083 } 1084 if (ic->ic_curmode == IEEE80211_MODE_11B) 1085 mode = R92C_RAID_11B; 1086 else 1087 mode = R92C_RAID_11BG; 1088 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1089 device_xname(sc->sc_dev), mode, rates, basicrates)); 1090 if (basicrates == 0) 1091 basicrates |= 1; /* add 1Mbps */ 1092 1093 /* Set rates mask for group addressed frames. */ 1094 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1095 cmd.mask = htole32((mode << 28) | basicrates); 1096 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1097 if (error != 0) { 1098 aprint_error_dev(sc->sc_dev, 1099 "could not add broadcast station\n"); 1100 return error; 1101 } 1102 /* Set initial MRR rate. */ 1103 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1104 maxbasicrate)); 1105 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1106 1107 /* Set rates mask for unicast frames. */ 1108 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1109 cmd.mask = htole32((mode << 28) | rates); 1110 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1111 if (error != 0) { 1112 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1113 return error; 1114 } 1115 /* Set initial MRR rate. */ 1116 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1117 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1118 1119 /* Configure Automatic Rate Fallback Register. */ 1120 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1121 if (rates & 0x0c) 1122 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1123 else 1124 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1125 } else 1126 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1127 1128 /* Indicate highest supported rate. */ 1129 ni->ni_txrate = rs->rs_nrates - 1; 1130 return 0; 1131 } 1132 1133 static int 1134 rtwn_get_nettype(struct rtwn_softc *sc) 1135 { 1136 struct ieee80211com *ic = &sc->sc_ic; 1137 int type; 1138 1139 switch (ic->ic_opmode) { 1140 case IEEE80211_M_STA: 1141 type = R92C_CR_NETTYPE_INFRA; 1142 break; 1143 1144 case IEEE80211_M_HOSTAP: 1145 type = R92C_CR_NETTYPE_AP; 1146 break; 1147 1148 case IEEE80211_M_IBSS: 1149 type = R92C_CR_NETTYPE_ADHOC; 1150 break; 1151 1152 default: 1153 type = R92C_CR_NETTYPE_NOLINK; 1154 break; 1155 } 1156 1157 return type; 1158 } 1159 1160 static void 1161 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1162 { 1163 uint32_t reg; 1164 1165 reg = rtwn_read_4(sc, R92C_CR); 1166 reg = RW(reg, R92C_CR_NETTYPE, type); 1167 rtwn_write_4(sc, R92C_CR, reg); 1168 } 1169 1170 static void 1171 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1172 { 1173 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1174 uint64_t tsf; 1175 1176 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1177 1178 /* Enable TSF synchronization. */ 1179 rtwn_write_1(sc, R92C_BCN_CTRL, 1180 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1181 1182 rtwn_write_1(sc, R92C_BCN_CTRL, 1183 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1184 1185 /* Set initial TSF. */ 1186 tsf = ni->ni_tstamp.tsf; 1187 tsf = le64toh(tsf); 1188 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1189 tsf -= IEEE80211_DUR_TU; 1190 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1191 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1192 1193 rtwn_write_1(sc, R92C_BCN_CTRL, 1194 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1195 } 1196 1197 static void 1198 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1199 { 1200 uint8_t reg; 1201 1202 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1203 1204 if (led == RTWN_LED_LINK) { 1205 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1206 if (!on) 1207 reg |= R92C_LEDCFG2_DIS; 1208 else 1209 reg |= R92C_LEDCFG2_EN; 1210 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1211 sc->ledlink = on; /* Save LED state. */ 1212 } 1213 } 1214 1215 static void 1216 rtwn_calib_to(void *arg) 1217 { 1218 struct rtwn_softc *sc = arg; 1219 struct r92c_fw_cmd_rssi cmd; 1220 int s; 1221 1222 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1223 1224 s = splnet(); 1225 1226 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1227 goto restart_timer; 1228 1229 if (sc->avg_pwdb != -1) { 1230 /* Indicate Rx signal strength to FW for rate adaptation. */ 1231 memset(&cmd, 0, sizeof(cmd)); 1232 cmd.macid = 0; /* BSS. */ 1233 cmd.pwdb = sc->avg_pwdb; 1234 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1235 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1236 } 1237 1238 /* Do temperature compensation. */ 1239 rtwn_temp_calib(sc); 1240 1241 restart_timer: 1242 callout_schedule(&sc->calib_to, mstohz(2000)); 1243 1244 splx(s); 1245 } 1246 1247 static void 1248 rtwn_next_scan(void *arg) 1249 { 1250 struct rtwn_softc *sc = arg; 1251 struct ieee80211com *ic = &sc->sc_ic; 1252 int s; 1253 1254 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1255 1256 s = splnet(); 1257 if (ic->ic_state == IEEE80211_S_SCAN) 1258 ieee80211_next_scan(ic); 1259 splx(s); 1260 } 1261 1262 static void 1263 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1264 { 1265 1266 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1267 1268 /* start with lowest Tx rate */ 1269 ni->ni_txrate = 0; 1270 } 1271 1272 static int 1273 rtwn_reset(struct ifnet *ifp) 1274 { 1275 struct rtwn_softc *sc = ifp->if_softc; 1276 struct ieee80211com *ic = &sc->sc_ic; 1277 1278 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1279 return ENETRESET; 1280 1281 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1282 1283 return 0; 1284 } 1285 1286 static int 1287 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1288 { 1289 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1290 struct ieee80211_node *ni; 1291 enum ieee80211_state ostate = ic->ic_state; 1292 uint32_t reg; 1293 int s; 1294 1295 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1296 1297 s = splnet(); 1298 1299 callout_stop(&sc->scan_to); 1300 callout_stop(&sc->calib_to); 1301 1302 if (ostate != nstate) { 1303 DPRINTF(("%s: %s -> %s\n", __func__, 1304 ieee80211_state_name[ostate], 1305 ieee80211_state_name[nstate])); 1306 } 1307 1308 switch (ostate) { 1309 case IEEE80211_S_INIT: 1310 break; 1311 1312 case IEEE80211_S_SCAN: 1313 if (nstate != IEEE80211_S_SCAN) { 1314 /* 1315 * End of scanning 1316 */ 1317 /* flush 4-AC Queue after site_survey */ 1318 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1319 1320 /* Allow Rx from our BSSID only. */ 1321 rtwn_write_4(sc, R92C_RCR, 1322 rtwn_read_4(sc, R92C_RCR) | 1323 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1324 } 1325 break; 1326 1327 case IEEE80211_S_AUTH: 1328 case IEEE80211_S_ASSOC: 1329 break; 1330 1331 case IEEE80211_S_RUN: 1332 /* Turn link LED off. */ 1333 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1334 1335 /* Set media status to 'No Link'. */ 1336 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1337 1338 /* Stop Rx of data frames. */ 1339 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1340 1341 /* Rest TSF. */ 1342 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1343 1344 /* Disable TSF synchronization. */ 1345 rtwn_write_1(sc, R92C_BCN_CTRL, 1346 rtwn_read_1(sc, R92C_BCN_CTRL) | 1347 R92C_BCN_CTRL_DIS_TSF_UDT0); 1348 1349 /* Back to 20MHz mode */ 1350 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1351 1352 /* Reset EDCA parameters. */ 1353 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1354 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1355 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1356 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1357 1358 /* flush all cam entries */ 1359 rtwn_cam_init(sc); 1360 break; 1361 } 1362 1363 switch (nstate) { 1364 case IEEE80211_S_INIT: 1365 /* Turn link LED off. */ 1366 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1367 break; 1368 1369 case IEEE80211_S_SCAN: 1370 if (ostate != IEEE80211_S_SCAN) { 1371 /* 1372 * Begin of scanning 1373 */ 1374 1375 /* Set gain for scanning. */ 1376 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1377 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1378 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1379 1380 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1381 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1382 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1383 1384 /* Allow Rx from any BSSID. */ 1385 rtwn_write_4(sc, R92C_RCR, 1386 rtwn_read_4(sc, R92C_RCR) & 1387 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1388 1389 /* Stop Rx of data frames. */ 1390 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1391 1392 /* Disable update TSF */ 1393 rtwn_write_1(sc, R92C_BCN_CTRL, 1394 rtwn_read_1(sc, R92C_BCN_CTRL) | 1395 R92C_BCN_CTRL_DIS_TSF_UDT0); 1396 } 1397 1398 /* Make link LED blink during scan. */ 1399 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1400 1401 /* Pause AC Tx queues. */ 1402 rtwn_write_1(sc, R92C_TXPAUSE, 1403 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1404 1405 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1406 1407 /* Start periodic scan. */ 1408 callout_schedule(&sc->scan_to, mstohz(200)); 1409 break; 1410 1411 case IEEE80211_S_AUTH: 1412 /* Set initial gain under link. */ 1413 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1414 #ifdef doaslinux 1415 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1416 #else 1417 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1418 #endif 1419 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1420 1421 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1422 #ifdef doaslinux 1423 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1424 #else 1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1426 #endif 1427 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1428 1429 /* Set media status to 'No Link'. */ 1430 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1431 1432 /* Allow Rx from any BSSID. */ 1433 rtwn_write_4(sc, R92C_RCR, 1434 rtwn_read_4(sc, R92C_RCR) & 1435 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1436 1437 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1438 break; 1439 1440 case IEEE80211_S_ASSOC: 1441 break; 1442 1443 case IEEE80211_S_RUN: 1444 ni = ic->ic_bss; 1445 1446 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1447 1448 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1449 /* Back to 20Mhz mode */ 1450 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1451 1452 /* Set media status to 'No Link'. */ 1453 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1454 1455 /* Enable Rx of data frames. */ 1456 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1457 1458 /* Allow Rx from any BSSID. */ 1459 rtwn_write_4(sc, R92C_RCR, 1460 rtwn_read_4(sc, R92C_RCR) & 1461 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1462 1463 /* Accept Rx data/control/management frames */ 1464 rtwn_write_4(sc, R92C_RCR, 1465 rtwn_read_4(sc, R92C_RCR) | 1466 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1467 1468 /* Turn link LED on. */ 1469 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1470 break; 1471 } 1472 1473 /* Set media status to 'Associated'. */ 1474 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1475 1476 /* Set BSSID. */ 1477 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1478 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1479 1480 if (ic->ic_curmode == IEEE80211_MODE_11B) 1481 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1482 else /* 802.11b/g */ 1483 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1484 1485 /* Enable Rx of data frames. */ 1486 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1487 1488 /* Flush all AC queues. */ 1489 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1490 1491 /* Set beacon interval. */ 1492 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1493 1494 switch (ic->ic_opmode) { 1495 case IEEE80211_M_STA: 1496 /* Allow Rx from our BSSID only. */ 1497 rtwn_write_4(sc, R92C_RCR, 1498 rtwn_read_4(sc, R92C_RCR) | 1499 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1500 1501 /* Enable TSF synchronization. */ 1502 rtwn_tsf_sync_enable(sc); 1503 break; 1504 1505 case IEEE80211_M_HOSTAP: 1506 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1507 1508 /* Allow Rx from any BSSID. */ 1509 rtwn_write_4(sc, R92C_RCR, 1510 rtwn_read_4(sc, R92C_RCR) & 1511 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1512 1513 /* Reset TSF timer to zero. */ 1514 reg = rtwn_read_4(sc, R92C_TCR); 1515 reg &= ~0x01; 1516 rtwn_write_4(sc, R92C_TCR, reg); 1517 reg |= 0x01; 1518 rtwn_write_4(sc, R92C_TCR, reg); 1519 break; 1520 1521 case IEEE80211_M_MONITOR: 1522 default: 1523 break; 1524 } 1525 1526 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1527 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1528 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1529 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1530 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1531 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1532 1533 /* Intialize rate adaptation. */ 1534 rtwn_ra_init(sc); 1535 1536 /* Turn link LED on. */ 1537 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1538 1539 /* Reset average RSSI. */ 1540 sc->avg_pwdb = -1; 1541 1542 /* Reset temperature calibration state machine. */ 1543 sc->thcal_state = 0; 1544 sc->thcal_lctemp = 0; 1545 1546 /* Start periodic calibration. */ 1547 callout_schedule(&sc->calib_to, mstohz(2000)); 1548 break; 1549 } 1550 1551 (void)sc->sc_newstate(ic, nstate, arg); 1552 1553 splx(s); 1554 1555 return 0; 1556 } 1557 1558 static int 1559 rtwn_wme_update(struct ieee80211com *ic) 1560 { 1561 static const uint16_t aci2reg[WME_NUM_AC] = { 1562 R92C_EDCA_BE_PARAM, 1563 R92C_EDCA_BK_PARAM, 1564 R92C_EDCA_VI_PARAM, 1565 R92C_EDCA_VO_PARAM 1566 }; 1567 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1568 const struct wmeParams *wmep; 1569 int s, aci, aifs, slottime; 1570 1571 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1572 1573 s = splnet(); 1574 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1575 for (aci = 0; aci < WME_NUM_AC; aci++) { 1576 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1577 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1578 aifs = wmep->wmep_aifsn * slottime + 10; 1579 rtwn_write_4(sc, aci2reg[aci], 1580 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1581 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1582 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1583 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1584 } 1585 splx(s); 1586 1587 return 0; 1588 } 1589 1590 static void 1591 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1592 { 1593 int pwdb; 1594 1595 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1596 1597 /* Convert antenna signal to percentage. */ 1598 if (rssi <= -100 || rssi >= 20) 1599 pwdb = 0; 1600 else if (rssi >= 0) 1601 pwdb = 100; 1602 else 1603 pwdb = 100 + rssi; 1604 if (rate <= 3) { 1605 /* CCK gain is smaller than OFDM/MCS gain. */ 1606 pwdb += 6; 1607 if (pwdb > 100) 1608 pwdb = 100; 1609 if (pwdb <= 14) 1610 pwdb -= 4; 1611 else if (pwdb <= 26) 1612 pwdb -= 8; 1613 else if (pwdb <= 34) 1614 pwdb -= 6; 1615 else if (pwdb <= 42) 1616 pwdb -= 2; 1617 } 1618 if (sc->avg_pwdb == -1) /* Init. */ 1619 sc->avg_pwdb = pwdb; 1620 else if (sc->avg_pwdb < pwdb) 1621 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1622 else 1623 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1624 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1625 } 1626 1627 static int8_t 1628 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1629 { 1630 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1631 struct r92c_rx_phystat *phy; 1632 struct r92c_rx_cck *cck; 1633 uint8_t rpt; 1634 int8_t rssi; 1635 1636 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1637 1638 if (rate <= 3) { 1639 cck = (struct r92c_rx_cck *)physt; 1640 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1641 rpt = (cck->agc_rpt >> 5) & 0x3; 1642 rssi = (cck->agc_rpt & 0x1f) << 1; 1643 } else { 1644 rpt = (cck->agc_rpt >> 6) & 0x3; 1645 rssi = cck->agc_rpt & 0x3e; 1646 } 1647 rssi = cckoff[rpt] - rssi; 1648 } else { /* OFDM/HT. */ 1649 phy = (struct r92c_rx_phystat *)physt; 1650 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1651 } 1652 return rssi; 1653 } 1654 1655 static void 1656 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1657 struct rtwn_rx_data *rx_data, int desc_idx) 1658 { 1659 struct ieee80211com *ic = &sc->sc_ic; 1660 struct ifnet *ifp = IC2IFP(ic); 1661 struct ieee80211_frame *wh; 1662 struct ieee80211_node *ni; 1663 struct r92c_rx_phystat *phy = NULL; 1664 uint32_t rxdw0, rxdw3; 1665 struct mbuf *m, *m1; 1666 uint8_t rate; 1667 int8_t rssi = 0; 1668 int infosz, pktlen, shift, totlen, error, s; 1669 1670 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1671 1672 rxdw0 = le32toh(rx_desc->rxdw0); 1673 rxdw3 = le32toh(rx_desc->rxdw3); 1674 1675 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1676 /* 1677 * This should not happen since we setup our Rx filter 1678 * to not receive these frames. 1679 */ 1680 ifp->if_ierrors++; 1681 return; 1682 } 1683 1684 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1685 /* 1686 * XXX: This will drop most control packets. Do we really 1687 * want this in IEEE80211_M_MONITOR mode? 1688 */ 1689 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1690 ic->ic_stats.is_rx_tooshort++; 1691 ifp->if_ierrors++; 1692 return; 1693 } 1694 if (__predict_false(pktlen > MCLBYTES)) { 1695 ifp->if_ierrors++; 1696 return; 1697 } 1698 1699 rate = MS(rxdw3, R92C_RXDW3_RATE); 1700 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1701 if (infosz > sizeof(struct r92c_rx_phystat)) 1702 infosz = sizeof(struct r92c_rx_phystat); 1703 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1704 totlen = pktlen + infosz + shift; 1705 1706 /* Get RSSI from PHY status descriptor if present. */ 1707 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1708 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1709 rssi = rtwn_get_rssi(sc, rate, phy); 1710 /* Update our average RSSI. */ 1711 rtwn_update_avgrssi(sc, rate, rssi); 1712 } 1713 1714 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1715 pktlen, rate, infosz, shift, rssi)); 1716 1717 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1718 if (__predict_false(m1 == NULL)) { 1719 ic->ic_stats.is_rx_nobuf++; 1720 ifp->if_ierrors++; 1721 return; 1722 } 1723 MCLGET(m1, M_DONTWAIT); 1724 if (__predict_false(!(m1->m_flags & M_EXT))) { 1725 m_freem(m1); 1726 ic->ic_stats.is_rx_nobuf++; 1727 ifp->if_ierrors++; 1728 return; 1729 } 1730 1731 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1732 BUS_DMASYNC_POSTREAD); 1733 1734 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1735 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1736 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1737 if (error != 0) { 1738 m_freem(m1); 1739 1740 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1741 rx_data->m, BUS_DMA_NOWAIT)) 1742 panic("%s: could not load old RX mbuf", 1743 device_xname(sc->sc_dev)); 1744 1745 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1746 BUS_DMASYNC_PREREAD); 1747 1748 /* Physical address may have changed. */ 1749 rtwn_setup_rx_desc(sc, rx_desc, 1750 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1751 1752 ifp->if_ierrors++; 1753 return; 1754 } 1755 1756 /* Finalize mbuf. */ 1757 m = rx_data->m; 1758 rx_data->m = m1; 1759 m->m_pkthdr.len = m->m_len = totlen; 1760 m_set_rcvif(m, ifp); 1761 1762 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1763 BUS_DMASYNC_PREREAD); 1764 1765 /* Update RX descriptor. */ 1766 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1767 MCLBYTES, desc_idx); 1768 1769 /* Get ieee80211 frame header. */ 1770 if (rxdw0 & R92C_RXDW0_PHYST) 1771 m_adj(m, infosz + shift); 1772 else 1773 m_adj(m, shift); 1774 wh = mtod(m, struct ieee80211_frame *); 1775 1776 s = splnet(); 1777 1778 if (__predict_false(sc->sc_drvbpf != NULL)) { 1779 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1780 1781 tap->wr_flags = 0; 1782 /* Map HW rate index to 802.11 rate. */ 1783 tap->wr_flags = 2; 1784 if (!(rxdw3 & R92C_RXDW3_HT)) { 1785 switch (rate) { 1786 /* CCK. */ 1787 case 0: tap->wr_rate = 2; break; 1788 case 1: tap->wr_rate = 4; break; 1789 case 2: tap->wr_rate = 11; break; 1790 case 3: tap->wr_rate = 22; break; 1791 /* OFDM. */ 1792 case 4: tap->wr_rate = 12; break; 1793 case 5: tap->wr_rate = 18; break; 1794 case 6: tap->wr_rate = 24; break; 1795 case 7: tap->wr_rate = 36; break; 1796 case 8: tap->wr_rate = 48; break; 1797 case 9: tap->wr_rate = 72; break; 1798 case 10: tap->wr_rate = 96; break; 1799 case 11: tap->wr_rate = 108; break; 1800 } 1801 } else if (rate >= 12) { /* MCS0~15. */ 1802 /* Bit 7 set means HT MCS instead of rate. */ 1803 tap->wr_rate = 0x80 | (rate - 12); 1804 } 1805 tap->wr_dbm_antsignal = rssi; 1806 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1807 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1808 1809 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1810 } 1811 1812 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1813 1814 /* push the frame up to the 802.11 stack */ 1815 ieee80211_input(ic, m, ni, rssi, 0); 1816 1817 /* Node is no longer needed. */ 1818 ieee80211_free_node(ni); 1819 1820 splx(s); 1821 } 1822 1823 static int 1824 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1825 { 1826 struct ieee80211com *ic = &sc->sc_ic; 1827 struct ieee80211_frame *wh; 1828 struct ieee80211_key *k = NULL; 1829 struct rtwn_tx_ring *tx_ring; 1830 struct rtwn_tx_data *data; 1831 struct r92c_tx_desc *txd; 1832 uint16_t qos, seq; 1833 uint8_t raid, type, tid, qid; 1834 int hasqos, error; 1835 1836 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1837 1838 wh = mtod(m, struct ieee80211_frame *); 1839 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1840 1841 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1842 k = ieee80211_crypto_encap(ic, ni, m); 1843 if (k == NULL) 1844 return ENOBUFS; 1845 1846 wh = mtod(m, struct ieee80211_frame *); 1847 } 1848 1849 if ((hasqos = ieee80211_has_qos(wh))) { 1850 /* data frames in 11n mode */ 1851 qos = ieee80211_get_qos(wh); 1852 tid = qos & IEEE80211_QOS_TID; 1853 qid = TID_TO_WME_AC(tid); 1854 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1855 /* Use AC_VO for management frames. */ 1856 tid = 0; /* compiler happy */ 1857 qid = RTWN_VO_QUEUE; 1858 } else { 1859 /* non-qos data frames */ 1860 tid = R92C_TXDW1_QSEL_BE; 1861 qid = RTWN_BE_QUEUE; 1862 } 1863 1864 /* Grab a Tx buffer from the ring. */ 1865 tx_ring = &sc->tx_ring[qid]; 1866 data = &tx_ring->tx_data[tx_ring->cur]; 1867 if (data->m != NULL) { 1868 m_freem(m); 1869 return ENOBUFS; 1870 } 1871 1872 /* Fill Tx descriptor. */ 1873 txd = &tx_ring->desc[tx_ring->cur]; 1874 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1875 m_freem(m); 1876 return ENOBUFS; 1877 } 1878 1879 txd->txdw0 = htole32( 1880 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1881 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1882 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1883 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1884 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1885 1886 txd->txdw1 = 0; 1887 txd->txdw4 = 0; 1888 txd->txdw5 = 0; 1889 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1890 type == IEEE80211_FC0_TYPE_DATA) { 1891 if (ic->ic_curmode == IEEE80211_MODE_11B) 1892 raid = R92C_RAID_11B; 1893 else 1894 raid = R92C_RAID_11BG; 1895 1896 txd->txdw1 |= htole32( 1897 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1898 SM(R92C_TXDW1_QSEL, tid) | 1899 SM(R92C_TXDW1_RAID, raid) | 1900 R92C_TXDW1_AGGBK); 1901 1902 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1903 /* for 11g */ 1904 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1905 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1906 R92C_TXDW4_HWRTSEN); 1907 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1908 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1909 R92C_TXDW4_HWRTSEN); 1910 } 1911 } 1912 /* Send RTS at OFDM24. */ 1913 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1914 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1915 /* Send data at OFDM54. */ 1916 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1917 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1918 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1919 txd->txdw1 |= htole32( 1920 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1921 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1922 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1923 1924 /* Force CCK1. */ 1925 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1926 /* Use 1Mbps */ 1927 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1928 } else { 1929 txd->txdw1 |= htole32( 1930 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1931 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1932 1933 /* Force CCK1. */ 1934 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1935 /* Use 1Mbps */ 1936 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1937 } 1938 1939 /* Set sequence number (already little endian). */ 1940 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1941 txd->txdseq = htole16(seq); 1942 1943 if (!hasqos) { 1944 /* Use HW sequence numbering for non-QoS frames. */ 1945 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1946 txd->txdseq |= htole16(0x8000); /* WTF? */ 1947 } else 1948 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1949 1950 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1951 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1952 if (error && error != EFBIG) { 1953 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1954 error); 1955 m_freem(m); 1956 return error; 1957 } 1958 if (error != 0) { 1959 /* Too many DMA segments, linearize mbuf. */ 1960 struct mbuf *newm = m_defrag(m, M_DONTWAIT); 1961 if (newm == NULL) { 1962 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1963 m_freem(m); 1964 return ENOBUFS; 1965 } 1966 m = newm; 1967 1968 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1969 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1970 if (error != 0) { 1971 aprint_error_dev(sc->sc_dev, 1972 "can't map mbuf (error %d)\n", error); 1973 m_freem(m); 1974 return error; 1975 } 1976 } 1977 1978 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1979 txd->txbufsize = htole16(m->m_pkthdr.len); 1980 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1981 BUS_SPACE_BARRIER_WRITE); 1982 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1983 1984 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1985 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1986 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1987 BUS_DMASYNC_PREWRITE); 1988 1989 data->m = m; 1990 data->ni = ni; 1991 1992 if (__predict_false(sc->sc_drvbpf != NULL)) { 1993 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1994 1995 tap->wt_flags = 0; 1996 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1997 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1998 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1999 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2000 2001 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2002 } 2003 2004 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2005 tx_ring->queued++; 2006 2007 if (tx_ring->queued > RTWN_TX_LIST_HIMARK) 2008 sc->qfullmsk |= (1 << qid); 2009 2010 /* Kick TX. */ 2011 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2012 2013 return 0; 2014 } 2015 2016 static void 2017 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2018 { 2019 struct ieee80211com *ic = &sc->sc_ic; 2020 struct ifnet *ifp = IC2IFP(ic); 2021 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2022 struct rtwn_tx_data *tx_data; 2023 struct r92c_tx_desc *tx_desc; 2024 int i, s; 2025 2026 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2027 qid)); 2028 2029 s = splnet(); 2030 2031 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2032 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2033 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2034 2035 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2036 tx_data = &tx_ring->tx_data[i]; 2037 if (tx_data->m == NULL) 2038 continue; 2039 2040 tx_desc = &tx_ring->desc[i]; 2041 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2042 continue; 2043 2044 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2045 m_freem(tx_data->m); 2046 tx_data->m = NULL; 2047 ieee80211_free_node(tx_data->ni); 2048 tx_data->ni = NULL; 2049 2050 ifp->if_opackets++; 2051 sc->sc_tx_timer = 0; 2052 tx_ring->queued--; 2053 } 2054 2055 if (tx_ring->queued < RTWN_TX_LIST_LOMARK) 2056 sc->qfullmsk &= ~(1 << qid); 2057 2058 splx(s); 2059 } 2060 2061 static void 2062 rtwn_start(struct ifnet *ifp) 2063 { 2064 struct rtwn_softc *sc = ifp->if_softc; 2065 struct ieee80211com *ic = &sc->sc_ic; 2066 struct ether_header *eh; 2067 struct ieee80211_node *ni; 2068 struct mbuf *m; 2069 2070 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2071 return; 2072 2073 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2074 2075 for (;;) { 2076 if (sc->qfullmsk != 0) { 2077 ifp->if_flags |= IFF_OACTIVE; 2078 break; 2079 } 2080 /* Send pending management frames first. */ 2081 IF_DEQUEUE(&ic->ic_mgtq, m); 2082 if (m != NULL) { 2083 ni = M_GETCTX(m, struct ieee80211_node *); 2084 M_CLEARCTX(m); 2085 goto sendit; 2086 } 2087 if (ic->ic_state != IEEE80211_S_RUN) 2088 break; 2089 2090 /* Encapsulate and send data frames. */ 2091 IFQ_DEQUEUE(&ifp->if_snd, m); 2092 if (m == NULL) 2093 break; 2094 2095 if (m->m_len < (int)sizeof(*eh) && 2096 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2097 ifp->if_oerrors++; 2098 continue; 2099 } 2100 eh = mtod(m, struct ether_header *); 2101 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2102 if (ni == NULL) { 2103 m_freem(m); 2104 ifp->if_oerrors++; 2105 continue; 2106 } 2107 2108 bpf_mtap(ifp, m); 2109 2110 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2111 ieee80211_free_node(ni); 2112 ifp->if_oerrors++; 2113 continue; 2114 } 2115 sendit: 2116 bpf_mtap3(ic->ic_rawbpf, m); 2117 2118 if (rtwn_tx(sc, m, ni) != 0) { 2119 ieee80211_free_node(ni); 2120 ifp->if_oerrors++; 2121 continue; 2122 } 2123 2124 sc->sc_tx_timer = 5; 2125 ifp->if_timer = 1; 2126 } 2127 2128 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2129 } 2130 2131 static void 2132 rtwn_watchdog(struct ifnet *ifp) 2133 { 2134 struct rtwn_softc *sc = ifp->if_softc; 2135 struct ieee80211com *ic = &sc->sc_ic; 2136 2137 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2138 2139 ifp->if_timer = 0; 2140 2141 if (sc->sc_tx_timer > 0) { 2142 if (--sc->sc_tx_timer == 0) { 2143 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2144 softint_schedule(sc->init_task); 2145 ifp->if_oerrors++; 2146 return; 2147 } 2148 ifp->if_timer = 1; 2149 } 2150 ieee80211_watchdog(ic); 2151 } 2152 2153 static int 2154 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2155 { 2156 struct rtwn_softc *sc = ifp->if_softc; 2157 struct ieee80211com *ic = &sc->sc_ic; 2158 int s, error = 0; 2159 2160 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2161 __func__, cmd, data)); 2162 2163 s = splnet(); 2164 2165 switch (cmd) { 2166 case SIOCSIFFLAGS: 2167 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2168 break; 2169 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2170 case IFF_UP | IFF_RUNNING: 2171 break; 2172 case IFF_UP: 2173 error = rtwn_init(ifp); 2174 if (error != 0) 2175 ifp->if_flags &= ~IFF_UP; 2176 break; 2177 case IFF_RUNNING: 2178 rtwn_stop(ifp, 1); 2179 break; 2180 case 0: 2181 break; 2182 } 2183 break; 2184 2185 case SIOCADDMULTI: 2186 case SIOCDELMULTI: 2187 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2188 /* setup multicast filter, etc */ 2189 error = 0; 2190 } 2191 break; 2192 2193 case SIOCS80211CHANNEL: 2194 error = ieee80211_ioctl(ic, cmd, data); 2195 if (error == ENETRESET && 2196 ic->ic_opmode == IEEE80211_M_MONITOR) { 2197 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2198 (IFF_UP | IFF_RUNNING)) { 2199 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2200 } 2201 error = 0; 2202 } 2203 break; 2204 2205 default: 2206 error = ieee80211_ioctl(ic, cmd, data); 2207 break; 2208 } 2209 2210 if (error == ENETRESET) { 2211 error = 0; 2212 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2213 (IFF_UP | IFF_RUNNING)) { 2214 rtwn_stop(ifp, 0); 2215 error = rtwn_init(ifp); 2216 } 2217 } 2218 2219 splx(s); 2220 2221 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2222 error)); 2223 2224 return error; 2225 } 2226 2227 static int 2228 rtwn_power_on(struct rtwn_softc *sc) 2229 { 2230 uint32_t reg; 2231 int ntries; 2232 2233 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2234 2235 /* Wait for autoload done bit. */ 2236 for (ntries = 0; ntries < 1000; ntries++) { 2237 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2238 break; 2239 DELAY(5); 2240 } 2241 if (ntries == 1000) { 2242 aprint_error_dev(sc->sc_dev, 2243 "timeout waiting for chip autoload\n"); 2244 return ETIMEDOUT; 2245 } 2246 2247 /* Unlock ISO/CLK/Power control register. */ 2248 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2249 2250 /* TODO: check if we need this for 8188CE */ 2251 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2252 /* bt coex */ 2253 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2254 reg |= (R92C_APS_FSMCO_SOP_ABG | 2255 R92C_APS_FSMCO_SOP_AMB | 2256 R92C_APS_FSMCO_XOP_BTCK); 2257 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2258 } 2259 2260 /* Move SPS into PWM mode. */ 2261 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2262 DELAY(100); 2263 2264 /* Set low byte to 0x0f, leave others unchanged. */ 2265 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2266 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2267 2268 /* TODO: check if we need this for 8188CE */ 2269 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2270 /* bt coex */ 2271 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2272 reg &= ~0x00024800; /* XXX magic from linux */ 2273 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2274 } 2275 2276 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2277 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2278 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2279 DELAY(200); 2280 2281 /* TODO: linux does additional btcoex stuff here */ 2282 2283 /* Auto enable WLAN. */ 2284 rtwn_write_2(sc, R92C_APS_FSMCO, 2285 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2286 for (ntries = 0; ntries < 1000; ntries++) { 2287 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2288 R92C_APS_FSMCO_APFM_ONMAC)) 2289 break; 2290 DELAY(5); 2291 } 2292 if (ntries == 1000) { 2293 aprint_error_dev(sc->sc_dev, 2294 "timeout waiting for MAC auto ON\n"); 2295 return ETIMEDOUT; 2296 } 2297 2298 /* Enable radio, GPIO and LED functions. */ 2299 rtwn_write_2(sc, R92C_APS_FSMCO, 2300 R92C_APS_FSMCO_AFSM_PCIE | 2301 R92C_APS_FSMCO_PDN_EN | 2302 R92C_APS_FSMCO_PFM_ALDN); 2303 2304 /* Release RF digital isolation. */ 2305 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2306 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2307 2308 if (sc->chip & RTWN_CHIP_92C) 2309 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2310 else 2311 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2312 2313 rtwn_write_4(sc, R92C_INT_MIG, 0); 2314 2315 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2316 /* bt coex */ 2317 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2318 reg &= 0xfd; /* XXX magic from linux */ 2319 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2320 } 2321 2322 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2323 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2324 2325 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2326 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2327 aprint_error_dev(sc->sc_dev, 2328 "radio is disabled by hardware switch\n"); 2329 return EPERM; /* :-) */ 2330 } 2331 2332 /* Initialize MAC. */ 2333 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2334 rtwn_write_1(sc, R92C_APSD_CTRL, 2335 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2336 for (ntries = 0; ntries < 200; ntries++) { 2337 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2338 R92C_APSD_CTRL_OFF_STATUS)) 2339 break; 2340 DELAY(500); 2341 } 2342 if (ntries == 200) { 2343 aprint_error_dev(sc->sc_dev, 2344 "timeout waiting for MAC initialization\n"); 2345 return ETIMEDOUT; 2346 } 2347 2348 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2349 reg = rtwn_read_2(sc, R92C_CR); 2350 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2351 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2352 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2353 R92C_CR_ENSEC; 2354 rtwn_write_2(sc, R92C_CR, reg); 2355 2356 rtwn_write_1(sc, 0xfe10, 0x19); 2357 2358 return 0; 2359 } 2360 2361 static int 2362 rtwn_llt_init(struct rtwn_softc *sc) 2363 { 2364 int i, error; 2365 2366 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2367 2368 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2369 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2370 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2371 return error; 2372 } 2373 /* NB: 0xff indicates end-of-list. */ 2374 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2375 return error; 2376 /* 2377 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2378 * as ring buffer. 2379 */ 2380 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2381 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2382 return error; 2383 } 2384 /* Make the last page point to the beginning of the ring buffer. */ 2385 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2386 return error; 2387 } 2388 2389 static void 2390 rtwn_fw_reset(struct rtwn_softc *sc) 2391 { 2392 uint16_t reg; 2393 int ntries; 2394 2395 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2396 2397 /* Tell 8051 to reset itself. */ 2398 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2399 2400 /* Wait until 8051 resets by itself. */ 2401 for (ntries = 0; ntries < 100; ntries++) { 2402 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2403 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2404 goto sleep; 2405 DELAY(50); 2406 } 2407 /* Force 8051 reset. */ 2408 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2409 sleep: 2410 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2411 #if 0 2412 /* 2413 * We must sleep for one second to let the firmware settle. 2414 * Accessing registers too early will hang the whole system. 2415 */ 2416 tsleep(®, 0, "rtwnrst", hz); 2417 #else 2418 DELAY(1000 * 1000); 2419 #endif 2420 } 2421 2422 static int 2423 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2424 { 2425 uint32_t reg; 2426 int off, mlen, error = 0, i; 2427 2428 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2429 2430 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2431 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2432 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2433 2434 DELAY(5); 2435 2436 off = R92C_FW_START_ADDR; 2437 while (len > 0) { 2438 if (len > 196) 2439 mlen = 196; 2440 else if (len > 4) 2441 mlen = 4; 2442 else 2443 mlen = 1; 2444 for (i = 0; i < mlen; i++) 2445 rtwn_write_1(sc, off++, buf[i]); 2446 buf += mlen; 2447 len -= mlen; 2448 } 2449 2450 return error; 2451 } 2452 2453 static int 2454 rtwn_load_firmware(struct rtwn_softc *sc) 2455 { 2456 firmware_handle_t fwh; 2457 const struct r92c_fw_hdr *hdr; 2458 const char *name; 2459 u_char *fw, *ptr; 2460 size_t len; 2461 uint32_t reg; 2462 int mlen, ntries, page, error; 2463 2464 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2465 2466 /* Read firmware image from the filesystem. */ 2467 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2468 RTWN_CHIP_UMC_A_CUT) 2469 name = "rtl8192cfwU.bin"; 2470 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2471 name = "rtl8192cfwU_B.bin"; 2472 else 2473 name = "rtl8192cfw.bin"; 2474 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2475 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2476 aprint_error_dev(sc->sc_dev, 2477 "could not read firmware %s (error %d)\n", name, error); 2478 return error; 2479 } 2480 const size_t fwlen = len = firmware_get_size(fwh); 2481 fw = firmware_malloc(len); 2482 if (fw == NULL) { 2483 aprint_error_dev(sc->sc_dev, 2484 "failed to allocate firmware memory (size=%zu)\n", len); 2485 firmware_close(fwh); 2486 return ENOMEM; 2487 } 2488 error = firmware_read(fwh, 0, fw, len); 2489 firmware_close(fwh); 2490 if (error != 0) { 2491 aprint_error_dev(sc->sc_dev, 2492 "failed to read firmware (error %d)\n", error); 2493 firmware_free(fw, fwlen); 2494 return error; 2495 } 2496 2497 if (len < sizeof(*hdr)) { 2498 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2499 error = EINVAL; 2500 goto fail; 2501 } 2502 ptr = fw; 2503 hdr = (const struct r92c_fw_hdr *)ptr; 2504 /* Check if there is a valid FW header and skip it. */ 2505 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2506 (le16toh(hdr->signature) >> 4) == 0x92c) { 2507 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2508 le16toh(hdr->version), le16toh(hdr->subversion), 2509 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2510 ptr += sizeof(*hdr); 2511 len -= sizeof(*hdr); 2512 } 2513 2514 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2515 rtwn_fw_reset(sc); 2516 2517 /* Enable FW download. */ 2518 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2519 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2520 R92C_SYS_FUNC_EN_CPUEN); 2521 rtwn_write_1(sc, R92C_MCUFWDL, 2522 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2523 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2524 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2525 2526 /* Reset the FWDL checksum. */ 2527 rtwn_write_1(sc, R92C_MCUFWDL, 2528 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2529 2530 /* download firmware */ 2531 for (page = 0; len > 0; page++) { 2532 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2533 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2534 if (error != 0) { 2535 aprint_error_dev(sc->sc_dev, 2536 "could not load firmware page %d\n", page); 2537 goto fail; 2538 } 2539 ptr += mlen; 2540 len -= mlen; 2541 } 2542 2543 /* Disable FW download. */ 2544 rtwn_write_1(sc, R92C_MCUFWDL, 2545 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2546 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2547 2548 /* Wait for checksum report. */ 2549 for (ntries = 0; ntries < 1000; ntries++) { 2550 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2551 break; 2552 DELAY(5); 2553 } 2554 if (ntries == 1000) { 2555 aprint_error_dev(sc->sc_dev, 2556 "timeout waiting for checksum report\n"); 2557 error = ETIMEDOUT; 2558 goto fail; 2559 } 2560 2561 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2562 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2563 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2564 2565 /* Wait for firmware readiness. */ 2566 for (ntries = 0; ntries < 1000; ntries++) { 2567 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2568 break; 2569 DELAY(5); 2570 } 2571 if (ntries == 1000) { 2572 aprint_error_dev(sc->sc_dev, 2573 "timeout waiting for firmware readiness\n"); 2574 error = ETIMEDOUT; 2575 goto fail; 2576 } 2577 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2578 2579 fail: 2580 firmware_free(fw, fwlen); 2581 return error; 2582 } 2583 2584 static int 2585 rtwn_dma_init(struct rtwn_softc *sc) 2586 { 2587 uint32_t reg; 2588 int error; 2589 2590 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2591 2592 /* Initialize LLT table. */ 2593 error = rtwn_llt_init(sc); 2594 if (error != 0) 2595 return error; 2596 2597 /* Set number of pages for normal priority queue. */ 2598 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2599 rtwn_write_4(sc, R92C_RQPN, 2600 /* Set number of pages for public queue. */ 2601 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2602 /* Set number of pages for high priority queue. */ 2603 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2604 /* Set number of pages for low priority queue. */ 2605 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2606 /* Load values. */ 2607 R92C_RQPN_LD); 2608 2609 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2610 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2611 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2612 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2613 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2614 2615 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2616 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2617 reg |= 0xF771; 2618 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2619 2620 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2621 2622 /* Configure Tx DMA. */ 2623 rtwn_write_4(sc, R92C_BKQ_DESA, 2624 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2625 rtwn_write_4(sc, R92C_BEQ_DESA, 2626 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2627 rtwn_write_4(sc, R92C_VIQ_DESA, 2628 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2629 rtwn_write_4(sc, R92C_VOQ_DESA, 2630 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2631 rtwn_write_4(sc, R92C_BCNQ_DESA, 2632 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2633 rtwn_write_4(sc, R92C_MGQ_DESA, 2634 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2635 rtwn_write_4(sc, R92C_HQ_DESA, 2636 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2637 2638 /* Configure Rx DMA. */ 2639 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2640 2641 /* Set Tx/Rx transfer page boundary. */ 2642 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2643 2644 /* Set Tx/Rx transfer page size. */ 2645 rtwn_write_1(sc, R92C_PBP, 2646 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2647 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2648 return 0; 2649 } 2650 2651 static void 2652 rtwn_mac_init(struct rtwn_softc *sc) 2653 { 2654 int i; 2655 2656 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2657 2658 /* Write MAC initialization values. */ 2659 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2660 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2661 } 2662 2663 static void 2664 rtwn_bb_init(struct rtwn_softc *sc) 2665 { 2666 const struct rtwn_bb_prog *prog; 2667 uint32_t reg; 2668 int i; 2669 2670 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2671 2672 /* Enable BB and RF. */ 2673 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2674 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2675 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2676 R92C_SYS_FUNC_EN_DIO_RF); 2677 2678 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2679 2680 rtwn_write_1(sc, R92C_RF_CTRL, 2681 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2682 2683 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2684 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2685 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2686 R92C_SYS_FUNC_EN_BBRSTB); 2687 2688 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2689 2690 rtwn_write_4(sc, R92C_LEDCFG0, 2691 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2692 2693 /* Select BB programming. */ 2694 prog = (sc->chip & RTWN_CHIP_92C) ? 2695 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2696 2697 /* Write BB initialization values. */ 2698 for (i = 0; i < prog->count; i++) { 2699 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2700 DELAY(1); 2701 } 2702 2703 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2704 /* 8192C 1T only configuration. */ 2705 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2706 reg = (reg & ~0x00000003) | 0x2; 2707 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2708 2709 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2710 reg = (reg & ~0x00300033) | 0x00200022; 2711 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2712 2713 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2714 reg = (reg & ~0xff000000) | 0x45 << 24; 2715 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2716 2717 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2718 reg = (reg & ~0x000000ff) | 0x23; 2719 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2720 2721 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2722 reg = (reg & ~0x00000030) | 1 << 4; 2723 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2724 2725 reg = rtwn_bb_read(sc, 0xe74); 2726 reg = (reg & ~0x0c000000) | 2 << 26; 2727 rtwn_bb_write(sc, 0xe74, reg); 2728 reg = rtwn_bb_read(sc, 0xe78); 2729 reg = (reg & ~0x0c000000) | 2 << 26; 2730 rtwn_bb_write(sc, 0xe78, reg); 2731 reg = rtwn_bb_read(sc, 0xe7c); 2732 reg = (reg & ~0x0c000000) | 2 << 26; 2733 rtwn_bb_write(sc, 0xe7c, reg); 2734 reg = rtwn_bb_read(sc, 0xe80); 2735 reg = (reg & ~0x0c000000) | 2 << 26; 2736 rtwn_bb_write(sc, 0xe80, reg); 2737 reg = rtwn_bb_read(sc, 0xe88); 2738 reg = (reg & ~0x0c000000) | 2 << 26; 2739 rtwn_bb_write(sc, 0xe88, reg); 2740 } 2741 2742 /* Write AGC values. */ 2743 for (i = 0; i < prog->agccount; i++) { 2744 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2745 prog->agcvals[i]); 2746 DELAY(1); 2747 } 2748 2749 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2750 R92C_HSSI_PARAM2_CCK_HIPWR) 2751 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2752 } 2753 2754 static void 2755 rtwn_rf_init(struct rtwn_softc *sc) 2756 { 2757 const struct rtwn_rf_prog *prog; 2758 uint32_t reg, type; 2759 int i, j, idx, off; 2760 2761 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2762 2763 /* Select RF programming based on board type. */ 2764 if (!(sc->chip & RTWN_CHIP_92C)) { 2765 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2766 prog = rtl8188ce_rf_prog; 2767 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2768 prog = rtl8188ru_rf_prog; 2769 else 2770 prog = rtl8188cu_rf_prog; 2771 } else 2772 prog = rtl8192ce_rf_prog; 2773 2774 for (i = 0; i < sc->nrxchains; i++) { 2775 /* Save RF_ENV control type. */ 2776 idx = i / 2; 2777 off = (i % 2) * 16; 2778 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2779 type = (reg >> off) & 0x10; 2780 2781 /* Set RF_ENV enable. */ 2782 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2783 reg |= 0x100000; 2784 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2785 DELAY(1); 2786 /* Set RF_ENV output high. */ 2787 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2788 reg |= 0x10; 2789 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2790 DELAY(1); 2791 /* Set address and data lengths of RF registers. */ 2792 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2793 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2794 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2795 DELAY(1); 2796 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2797 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2798 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2799 DELAY(1); 2800 2801 /* Write RF initialization values for this chain. */ 2802 for (j = 0; j < prog[i].count; j++) { 2803 if (prog[i].regs[j] >= 0xf9 && 2804 prog[i].regs[j] <= 0xfe) { 2805 /* 2806 * These are fake RF registers offsets that 2807 * indicate a delay is required. 2808 */ 2809 DELAY(50); 2810 continue; 2811 } 2812 rtwn_rf_write(sc, i, prog[i].regs[j], 2813 prog[i].vals[j]); 2814 DELAY(1); 2815 } 2816 2817 /* Restore RF_ENV control type. */ 2818 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2819 reg &= ~(0x10 << off) | (type << off); 2820 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2821 2822 /* Cache RF register CHNLBW. */ 2823 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2824 } 2825 2826 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2827 RTWN_CHIP_UMC_A_CUT) { 2828 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2829 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2830 } 2831 } 2832 2833 static void 2834 rtwn_cam_init(struct rtwn_softc *sc) 2835 { 2836 2837 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2838 2839 /* Invalidate all CAM entries. */ 2840 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2841 } 2842 2843 static void 2844 rtwn_pa_bias_init(struct rtwn_softc *sc) 2845 { 2846 uint8_t reg; 2847 int i; 2848 2849 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2850 2851 for (i = 0; i < sc->nrxchains; i++) { 2852 if (sc->pa_setting & (1 << i)) 2853 continue; 2854 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2855 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2856 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2857 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2858 } 2859 if (!(sc->pa_setting & 0x10)) { 2860 reg = rtwn_read_1(sc, 0x16); 2861 reg = (reg & ~0xf0) | 0x90; 2862 rtwn_write_1(sc, 0x16, reg); 2863 } 2864 } 2865 2866 static void 2867 rtwn_rxfilter_init(struct rtwn_softc *sc) 2868 { 2869 2870 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2871 2872 /* Initialize Rx filter. */ 2873 /* TODO: use better filter for monitor mode. */ 2874 rtwn_write_4(sc, R92C_RCR, 2875 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2876 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2877 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2878 /* Accept all multicast frames. */ 2879 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2880 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2881 /* Accept all management frames. */ 2882 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2883 /* Reject all control frames. */ 2884 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2885 /* Accept all data frames. */ 2886 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2887 } 2888 2889 static void 2890 rtwn_edca_init(struct rtwn_softc *sc) 2891 { 2892 2893 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2894 2895 /* set spec SIFS (used in NAV) */ 2896 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2897 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2898 2899 /* set SIFS CCK/OFDM */ 2900 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2901 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2902 2903 /* TXOP */ 2904 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2905 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2906 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2907 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2908 } 2909 2910 static void 2911 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2912 uint16_t power[RTWN_RIDX_COUNT]) 2913 { 2914 uint32_t reg; 2915 2916 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2917 2918 /* Write per-CCK rate Tx power. */ 2919 if (chain == 0) { 2920 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2921 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2922 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2923 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2924 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2925 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2926 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2927 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2928 } else { 2929 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2930 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2931 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2932 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2933 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2934 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2935 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2936 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2937 } 2938 /* Write per-OFDM rate Tx power. */ 2939 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2940 SM(R92C_TXAGC_RATE06, power[ 4]) | 2941 SM(R92C_TXAGC_RATE09, power[ 5]) | 2942 SM(R92C_TXAGC_RATE12, power[ 6]) | 2943 SM(R92C_TXAGC_RATE18, power[ 7])); 2944 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2945 SM(R92C_TXAGC_RATE24, power[ 8]) | 2946 SM(R92C_TXAGC_RATE36, power[ 9]) | 2947 SM(R92C_TXAGC_RATE48, power[10]) | 2948 SM(R92C_TXAGC_RATE54, power[11])); 2949 /* Write per-MCS Tx power. */ 2950 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2951 SM(R92C_TXAGC_MCS00, power[12]) | 2952 SM(R92C_TXAGC_MCS01, power[13]) | 2953 SM(R92C_TXAGC_MCS02, power[14]) | 2954 SM(R92C_TXAGC_MCS03, power[15])); 2955 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2956 SM(R92C_TXAGC_MCS04, power[16]) | 2957 SM(R92C_TXAGC_MCS05, power[17]) | 2958 SM(R92C_TXAGC_MCS06, power[18]) | 2959 SM(R92C_TXAGC_MCS07, power[19])); 2960 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2961 SM(R92C_TXAGC_MCS08, power[20]) | 2962 SM(R92C_TXAGC_MCS09, power[21]) | 2963 SM(R92C_TXAGC_MCS10, power[22]) | 2964 SM(R92C_TXAGC_MCS11, power[23])); 2965 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2966 SM(R92C_TXAGC_MCS12, power[24]) | 2967 SM(R92C_TXAGC_MCS13, power[25]) | 2968 SM(R92C_TXAGC_MCS14, power[26]) | 2969 SM(R92C_TXAGC_MCS15, power[27])); 2970 } 2971 2972 static void 2973 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2974 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2975 uint16_t power[RTWN_RIDX_COUNT]) 2976 { 2977 struct ieee80211com *ic = &sc->sc_ic; 2978 struct r92c_rom *rom = &sc->rom; 2979 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2980 const struct rtwn_txpwr *base; 2981 int ridx, chan, group; 2982 2983 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2984 2985 /* Determine channel group. */ 2986 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2987 if (chan <= 3) 2988 group = 0; 2989 else if (chan <= 9) 2990 group = 1; 2991 else 2992 group = 2; 2993 2994 /* Get original Tx power based on board type and RF chain. */ 2995 if (!(sc->chip & RTWN_CHIP_92C)) { 2996 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2997 base = &rtl8188ru_txagc[chain]; 2998 else 2999 base = &rtl8192cu_txagc[chain]; 3000 } else 3001 base = &rtl8192cu_txagc[chain]; 3002 3003 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 3004 if (sc->regulatory == 0) { 3005 for (ridx = 0; ridx <= 3; ridx++) 3006 power[ridx] = base->pwr[0][ridx]; 3007 } 3008 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3009 if (sc->regulatory == 3) { 3010 power[ridx] = base->pwr[0][ridx]; 3011 /* Apply vendor limits. */ 3012 if (extc != NULL) 3013 maxpwr = rom->ht40_max_pwr[group]; 3014 else 3015 maxpwr = rom->ht20_max_pwr[group]; 3016 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 3017 if (power[ridx] > maxpwr) 3018 power[ridx] = maxpwr; 3019 } else if (sc->regulatory == 1) { 3020 if (extc == NULL) 3021 power[ridx] = base->pwr[group][ridx]; 3022 } else if (sc->regulatory != 2) 3023 power[ridx] = base->pwr[0][ridx]; 3024 } 3025 3026 /* Compute per-CCK rate Tx power. */ 3027 cckpow = rom->cck_tx_pwr[chain][group]; 3028 for (ridx = 0; ridx <= 3; ridx++) { 3029 power[ridx] += cckpow; 3030 if (power[ridx] > R92C_MAX_TX_PWR) 3031 power[ridx] = R92C_MAX_TX_PWR; 3032 } 3033 3034 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3035 if (sc->ntxchains > 1) { 3036 /* Apply reduction for 2 spatial streams. */ 3037 diff = rom->ht40_2s_tx_pwr_diff[group]; 3038 diff = (diff >> (chain * 4)) & 0xf; 3039 htpow = (htpow > diff) ? htpow - diff : 0; 3040 } 3041 3042 /* Compute per-OFDM rate Tx power. */ 3043 diff = rom->ofdm_tx_pwr_diff[group]; 3044 diff = (diff >> (chain * 4)) & 0xf; 3045 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3046 for (ridx = 4; ridx <= 11; ridx++) { 3047 power[ridx] += ofdmpow; 3048 if (power[ridx] > R92C_MAX_TX_PWR) 3049 power[ridx] = R92C_MAX_TX_PWR; 3050 } 3051 3052 /* Compute per-MCS Tx power. */ 3053 if (extc == NULL) { 3054 diff = rom->ht20_tx_pwr_diff[group]; 3055 diff = (diff >> (chain * 4)) & 0xf; 3056 htpow += diff; /* HT40->HT20 correction. */ 3057 } 3058 for (ridx = 12; ridx <= 27; ridx++) { 3059 power[ridx] += htpow; 3060 if (power[ridx] > R92C_MAX_TX_PWR) 3061 power[ridx] = R92C_MAX_TX_PWR; 3062 } 3063 #ifdef RTWN_DEBUG 3064 if (rtwn_debug >= 4) { 3065 /* Dump per-rate Tx power values. */ 3066 printf("Tx power for chain %d:\n", chain); 3067 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3068 printf("Rate %d = %u\n", ridx, power[ridx]); 3069 } 3070 #endif 3071 } 3072 3073 static void 3074 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3075 struct ieee80211_channel *extc) 3076 { 3077 uint16_t power[RTWN_RIDX_COUNT]; 3078 int i; 3079 3080 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3081 3082 for (i = 0; i < sc->ntxchains; i++) { 3083 /* Compute per-rate Tx power values. */ 3084 rtwn_get_txpower(sc, i, c, extc, power); 3085 /* Write per-rate Tx power values to hardware. */ 3086 rtwn_write_txpower(sc, i, power); 3087 } 3088 } 3089 3090 static void 3091 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3092 struct ieee80211_channel *extc) 3093 { 3094 struct ieee80211com *ic = &sc->sc_ic; 3095 u_int chan; 3096 int i; 3097 3098 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3099 3100 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3101 3102 /* Set Tx power for this new channel. */ 3103 rtwn_set_txpower(sc, c, extc); 3104 3105 for (i = 0; i < sc->nrxchains; i++) { 3106 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3107 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3108 } 3109 #ifndef IEEE80211_NO_HT 3110 if (extc != NULL) { 3111 uint32_t reg; 3112 3113 /* Is secondary channel below or above primary? */ 3114 int prichlo = c->ic_freq < extc->ic_freq; 3115 3116 rtwn_write_1(sc, R92C_BWOPMODE, 3117 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3118 3119 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3120 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3121 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3122 3123 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3124 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3125 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3126 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3127 3128 /* Set CCK side band. */ 3129 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3130 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3131 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3132 3133 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3134 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3135 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3136 3137 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3138 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3139 ~R92C_FPGA0_ANAPARAM2_CBW20); 3140 3141 reg = rtwn_bb_read(sc, 0x818); 3142 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3143 rtwn_bb_write(sc, 0x818, reg); 3144 3145 /* Select 40MHz bandwidth. */ 3146 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3147 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3148 } else 3149 #endif 3150 { 3151 rtwn_write_1(sc, R92C_BWOPMODE, 3152 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3153 3154 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3155 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3156 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3157 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3158 3159 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3160 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3161 R92C_FPGA0_ANAPARAM2_CBW20); 3162 3163 /* Select 20MHz bandwidth. */ 3164 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3165 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3166 } 3167 } 3168 3169 static void 3170 rtwn_iq_calib(struct rtwn_softc *sc) 3171 { 3172 3173 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3174 3175 /* XXX */ 3176 } 3177 3178 static void 3179 rtwn_lc_calib(struct rtwn_softc *sc) 3180 { 3181 uint32_t rf_ac[2]; 3182 uint8_t txmode; 3183 int i; 3184 3185 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3186 3187 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3188 if ((txmode & 0x70) != 0) { 3189 /* Disable all continuous Tx. */ 3190 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3191 3192 /* Set RF mode to standby mode. */ 3193 for (i = 0; i < sc->nrxchains; i++) { 3194 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3195 rtwn_rf_write(sc, i, R92C_RF_AC, 3196 RW(rf_ac[i], R92C_RF_AC_MODE, 3197 R92C_RF_AC_MODE_STANDBY)); 3198 } 3199 } else { 3200 /* Block all Tx queues. */ 3201 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3202 } 3203 /* Start calibration. */ 3204 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3205 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3206 3207 /* Give calibration the time to complete. */ 3208 DELAY(100); 3209 3210 /* Restore configuration. */ 3211 if ((txmode & 0x70) != 0) { 3212 /* Restore Tx mode. */ 3213 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3214 /* Restore RF mode. */ 3215 for (i = 0; i < sc->nrxchains; i++) 3216 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3217 } else { 3218 /* Unblock all Tx queues. */ 3219 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3220 } 3221 } 3222 3223 static void 3224 rtwn_temp_calib(struct rtwn_softc *sc) 3225 { 3226 int temp; 3227 3228 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3229 3230 if (sc->thcal_state == 0) { 3231 /* Start measuring temperature. */ 3232 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3233 sc->thcal_state = 1; 3234 return; 3235 } 3236 sc->thcal_state = 0; 3237 3238 /* Read measured temperature. */ 3239 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3240 if (temp == 0) /* Read failed, skip. */ 3241 return; 3242 DPRINTFN(2, ("temperature=%d\n", temp)); 3243 3244 /* 3245 * Redo IQ and LC calibration if temperature changed significantly 3246 * since last calibration. 3247 */ 3248 if (sc->thcal_lctemp == 0) { 3249 /* First calibration is performed in rtwn_init(). */ 3250 sc->thcal_lctemp = temp; 3251 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3252 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3253 sc->thcal_lctemp, temp)); 3254 rtwn_iq_calib(sc); 3255 rtwn_lc_calib(sc); 3256 /* Record temperature of last calibration. */ 3257 sc->thcal_lctemp = temp; 3258 } 3259 } 3260 3261 static int 3262 rtwn_init(struct ifnet *ifp) 3263 { 3264 struct rtwn_softc *sc = ifp->if_softc; 3265 struct ieee80211com *ic = &sc->sc_ic; 3266 uint32_t reg; 3267 int i, error; 3268 3269 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3270 3271 /* Init firmware commands ring. */ 3272 sc->fwcur = 0; 3273 3274 /* Power on adapter. */ 3275 error = rtwn_power_on(sc); 3276 if (error != 0) { 3277 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3278 goto fail; 3279 } 3280 3281 /* Initialize DMA. */ 3282 error = rtwn_dma_init(sc); 3283 if (error != 0) { 3284 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3285 goto fail; 3286 } 3287 3288 /* Set info size in Rx descriptors (in 64-bit words). */ 3289 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3290 3291 /* Disable interrupts. */ 3292 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3293 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3294 3295 /* Set MAC address. */ 3296 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3297 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3298 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3299 3300 /* Set initial network type. */ 3301 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3302 3303 rtwn_rxfilter_init(sc); 3304 3305 reg = rtwn_read_4(sc, R92C_RRSR); 3306 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3307 rtwn_write_4(sc, R92C_RRSR, reg); 3308 3309 /* Set short/long retry limits. */ 3310 rtwn_write_2(sc, R92C_RL, 3311 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3312 3313 /* Initialize EDCA parameters. */ 3314 rtwn_edca_init(sc); 3315 3316 /* Set data and response automatic rate fallback retry counts. */ 3317 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3318 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3319 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3320 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3321 3322 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3323 3324 /* Set ACK timeout. */ 3325 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3326 3327 /* Initialize beacon parameters. */ 3328 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3329 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3330 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3331 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3332 3333 /* Setup AMPDU aggregation. */ 3334 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3335 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3336 3337 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3338 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3339 3340 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3341 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3342 3343 /* Load 8051 microcode. */ 3344 error = rtwn_load_firmware(sc); 3345 if (error != 0) 3346 goto fail; 3347 3348 /* Initialize MAC/BB/RF blocks. */ 3349 rtwn_mac_init(sc); 3350 rtwn_bb_init(sc); 3351 rtwn_rf_init(sc); 3352 3353 /* Turn CCK and OFDM blocks on. */ 3354 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3355 reg |= R92C_RFMOD_CCK_EN; 3356 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3357 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3358 reg |= R92C_RFMOD_OFDM_EN; 3359 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3360 3361 /* Clear per-station keys table. */ 3362 rtwn_cam_init(sc); 3363 3364 /* Enable hardware sequence numbering. */ 3365 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3366 3367 /* Perform LO and IQ calibrations. */ 3368 rtwn_iq_calib(sc); 3369 /* Perform LC calibration. */ 3370 rtwn_lc_calib(sc); 3371 3372 rtwn_pa_bias_init(sc); 3373 3374 /* Initialize GPIO setting. */ 3375 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3376 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3377 3378 /* Fix for lower temperature. */ 3379 rtwn_write_1(sc, 0x15, 0xe9); 3380 3381 /* Set default channel. */ 3382 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3383 3384 /* Clear pending interrupts. */ 3385 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3386 3387 /* Enable interrupts. */ 3388 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3389 3390 /* We're ready to go. */ 3391 ifp->if_flags &= ~IFF_OACTIVE; 3392 ifp->if_flags |= IFF_RUNNING; 3393 3394 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3395 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3396 else 3397 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3398 3399 return 0; 3400 3401 fail: 3402 rtwn_stop(ifp, 1); 3403 return error; 3404 } 3405 3406 static void 3407 rtwn_init_task(void *arg) 3408 { 3409 struct rtwn_softc *sc = arg; 3410 struct ifnet *ifp = GET_IFP(sc); 3411 int s; 3412 3413 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3414 3415 s = splnet(); 3416 3417 rtwn_stop(ifp, 0); 3418 3419 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3420 rtwn_init(ifp); 3421 3422 splx(s); 3423 } 3424 3425 static void 3426 rtwn_stop(struct ifnet *ifp, int disable) 3427 { 3428 struct rtwn_softc *sc = ifp->if_softc; 3429 struct ieee80211com *ic = &sc->sc_ic; 3430 uint16_t reg; 3431 int s, i; 3432 3433 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3434 3435 sc->sc_tx_timer = 0; 3436 ifp->if_timer = 0; 3437 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3438 3439 callout_stop(&sc->scan_to); 3440 callout_stop(&sc->calib_to); 3441 3442 s = splnet(); 3443 3444 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3445 3446 /* Disable interrupts. */ 3447 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3448 3449 /* Pause MAC TX queue */ 3450 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3451 3452 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3453 3454 /* Reset BB state machine */ 3455 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3456 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3457 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3458 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3459 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3460 3461 reg = rtwn_read_2(sc, R92C_CR); 3462 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3463 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3464 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3465 R92C_CR_ENSEC); 3466 rtwn_write_2(sc, R92C_CR, reg); 3467 3468 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3469 rtwn_fw_reset(sc); 3470 3471 /* Reset MAC and Enable 8051 */ 3472 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3473 3474 /* TODO: linux does additional btcoex stuff here */ 3475 3476 /* Disable AFE PLL */ 3477 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3478 /* Enter PFM mode */ 3479 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3480 /* Gated AFE DIG_CLOCK */ 3481 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3482 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3483 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3484 3485 for (i = 0; i < RTWN_NTXQUEUES; i++) 3486 rtwn_reset_tx_list(sc, i); 3487 rtwn_reset_rx_list(sc); 3488 3489 splx(s); 3490 } 3491 3492 static int 3493 rtwn_intr(void *xsc) 3494 { 3495 struct rtwn_softc *sc = xsc; 3496 uint32_t status; 3497 3498 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3499 return 0; 3500 3501 status = rtwn_read_4(sc, R92C_HISR); 3502 if (status == 0 || status == 0xffffffff) 3503 return 0; 3504 3505 /* Disable interrupts. */ 3506 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3507 3508 softint_schedule(sc->sc_soft_ih); 3509 return 1; 3510 } 3511 3512 static void 3513 rtwn_softintr(void *xsc) 3514 { 3515 struct rtwn_softc *sc = xsc; 3516 uint32_t status; 3517 int i, s; 3518 3519 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3520 return; 3521 3522 status = rtwn_read_4(sc, R92C_HISR); 3523 if (status == 0 || status == 0xffffffff) 3524 goto out; 3525 3526 /* Ack interrupts. */ 3527 rtwn_write_4(sc, R92C_HISR, status); 3528 3529 /* Vendor driver treats RX errors like ROK... */ 3530 if (status & RTWN_INT_ENABLE_RX) { 3531 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3532 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3533 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3534 3535 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3536 continue; 3537 3538 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3539 } 3540 } 3541 3542 if (status & R92C_IMR_BDOK) 3543 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3544 if (status & R92C_IMR_HIGHDOK) 3545 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3546 if (status & R92C_IMR_MGNTDOK) 3547 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3548 if (status & R92C_IMR_BKDOK) 3549 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3550 if (status & R92C_IMR_BEDOK) 3551 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3552 if (status & R92C_IMR_VIDOK) 3553 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3554 if (status & R92C_IMR_VODOK) 3555 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3556 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3557 struct ifnet *ifp = GET_IFP(sc); 3558 s = splnet(); 3559 ifp->if_flags &= ~IFF_OACTIVE; 3560 rtwn_start(ifp); 3561 splx(s); 3562 } 3563 3564 out: 3565 /* Enable interrupts. */ 3566 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3567 } 3568
Indexes created Thu Oct 02 01:09:59 GMT 2025