if_rtwn.c revision 1.13.2.2
1 /* $NetBSD: if_rtwn.c,v 1.13.2.2 2017/12/03 11:37:08 jdolecek Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.13.2.2 2017/12/03 11:37:08 jdolecek Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 static void rtwn_softintr(void *); 178 179 /* Aliases. */ 180 #define rtwn_bb_write rtwn_write_4 181 #define rtwn_bb_read rtwn_read_4 182 183 static const struct rtwn_device * 184 rtwn_lookup(const struct pci_attach_args *pa) 185 { 186 const struct rtwn_device *rd; 187 int i; 188 189 for (i = 0; i < __arraycount(rtwn_devices); i++) { 190 rd = &rtwn_devices[i]; 191 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 192 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 193 return rd; 194 } 195 return NULL; 196 } 197 198 static int 199 rtwn_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (rtwn_lookup(pa) != NULL) 204 return 1; 205 return 0; 206 } 207 208 static void 209 rtwn_attach(device_t parent, device_t self, void *aux) 210 { 211 struct rtwn_softc *sc = device_private(self); 212 struct pci_attach_args *pa = aux; 213 struct ieee80211com *ic = &sc->sc_ic; 214 struct ifnet *ifp = GET_IFP(sc); 215 int i, error; 216 pcireg_t memtype; 217 const char *intrstr; 218 char intrbuf[PCI_INTRSTR_LEN]; 219 220 sc->sc_dev = self; 221 sc->sc_dmat = pa->pa_dmat; 222 sc->sc_pc = pa->pa_pc; 223 sc->sc_tag = pa->pa_tag; 224 225 pci_aprint_devinfo(pa, NULL); 226 227 callout_init(&sc->scan_to, 0); 228 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 229 callout_init(&sc->calib_to, 0); 230 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 231 232 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc); 233 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 234 235 /* Power up the device */ 236 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 237 238 /* Map control/status registers. */ 239 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 240 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 241 &sc->sc_sh, NULL, &sc->sc_mapsize); 242 if (error != 0) { 243 aprint_error_dev(self, "can't map mem space\n"); 244 return; 245 } 246 247 /* Install interrupt handler. */ 248 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 249 aprint_error_dev(self, "can't map interrupt\n"); 250 return; 251 } 252 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 253 sizeof(intrbuf)); 254 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 255 rtwn_intr, sc); 256 if (sc->sc_ih == NULL) { 257 aprint_error_dev(self, "can't establish interrupt"); 258 if (intrstr != NULL) 259 aprint_error(" at %s", intrstr); 260 aprint_error("\n"); 261 return; 262 } 263 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 264 265 error = rtwn_read_chipid(sc); 266 if (error != 0) { 267 aprint_error_dev(self, "unsupported test or unknown chip\n"); 268 return; 269 } 270 271 /* Disable PCIe Active State Power Management (ASPM). */ 272 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 273 &sc->sc_cap_off, NULL)) { 274 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 275 sc->sc_cap_off + PCIE_LCSR); 276 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 277 pci_conf_write(sc->sc_pc, sc->sc_tag, 278 sc->sc_cap_off + PCIE_LCSR, lcsr); 279 } 280 281 /* Allocate Tx/Rx buffers. */ 282 error = rtwn_alloc_rx_list(sc); 283 if (error != 0) { 284 aprint_error_dev(self, "could not allocate Rx buffers\n"); 285 return; 286 } 287 for (i = 0; i < RTWN_NTXQUEUES; i++) { 288 error = rtwn_alloc_tx_list(sc, i); 289 if (error != 0) { 290 aprint_error_dev(self, 291 "could not allocate Tx buffers\n"); 292 return; 293 } 294 } 295 296 /* Determine number of Tx/Rx chains. */ 297 if (sc->chip & RTWN_CHIP_92C) { 298 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 299 sc->nrxchains = 2; 300 } else { 301 sc->ntxchains = 1; 302 sc->nrxchains = 1; 303 } 304 rtwn_read_rom(sc); 305 306 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 307 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 308 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 309 310 /* 311 * Setup the 802.11 device. 312 */ 313 ic->ic_ifp = ifp; 314 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 315 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 316 ic->ic_state = IEEE80211_S_INIT; 317 318 /* Set device capabilities. */ 319 ic->ic_caps = 320 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 321 IEEE80211_C_IBSS | /* IBSS mode supported */ 322 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 323 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 324 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 325 IEEE80211_C_WME | /* 802.11e */ 326 IEEE80211_C_WPA; /* WPA/RSN. */ 327 328 #ifndef IEEE80211_NO_HT 329 /* Set HT capabilities. */ 330 ic->ic_htcaps = 331 IEEE80211_HTCAP_CBW20_40 | 332 IEEE80211_HTCAP_DSSSCCK40; 333 /* Set supported HT rates. */ 334 for (i = 0; i < sc->nrxchains; i++) 335 ic->ic_sup_mcs[i] = 0xff; 336 #endif 337 338 /* Set supported .11b and .11g rates. */ 339 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 340 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 341 342 /* Set supported .11b and .11g channels (1 through 14). */ 343 for (i = 1; i <= 14; i++) { 344 ic->ic_channels[i].ic_freq = 345 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 346 ic->ic_channels[i].ic_flags = 347 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 348 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 349 } 350 351 ifp->if_softc = sc; 352 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 353 ifp->if_init = rtwn_init; 354 ifp->if_ioctl = rtwn_ioctl; 355 ifp->if_start = rtwn_start; 356 ifp->if_watchdog = rtwn_watchdog; 357 IFQ_SET_READY(&ifp->if_snd); 358 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 359 360 error = if_initialize(ifp); 361 if (error != 0) { 362 ifp->if_softc = NULL; /* For rtwn_detach() */ 363 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 364 error); 365 goto fail; 366 } 367 ieee80211_ifattach(ic); 368 /* Use common softint-based if_input */ 369 ifp->if_percpuq = if_percpuq_create(ifp); 370 if_register(ifp); 371 372 /* override default methods */ 373 ic->ic_newassoc = rtwn_newassoc; 374 ic->ic_reset = rtwn_reset; 375 ic->ic_wme.wme_update = rtwn_wme_update; 376 377 /* Override state transition machine. */ 378 sc->sc_newstate = ic->ic_newstate; 379 ic->ic_newstate = rtwn_newstate; 380 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 381 382 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 383 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 384 &sc->sc_drvbpf); 385 386 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 387 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 388 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 389 390 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 391 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 392 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 393 394 ieee80211_announce(ic); 395 396 if (!pmf_device_register(self, NULL, NULL)) 397 aprint_error_dev(self, "couldn't establish power handler\n"); 398 399 fail: 400 rtwn_detach(self, 0); 401 } 402 403 static int 404 rtwn_detach(device_t self, int flags) 405 { 406 struct rtwn_softc *sc = device_private(self); 407 struct ieee80211com *ic = &sc->sc_ic; 408 struct ifnet *ifp = GET_IFP(sc); 409 int s, i; 410 411 callout_stop(&sc->scan_to); 412 callout_stop(&sc->calib_to); 413 414 s = splnet(); 415 416 if (ifp->if_softc != NULL) { 417 rtwn_stop(ifp, 0); 418 419 pmf_device_deregister(self); 420 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 421 bpf_detach(ifp); 422 ieee80211_ifdetach(ic); 423 if_detach(ifp); 424 } 425 426 /* Free Tx/Rx buffers. */ 427 for (i = 0; i < RTWN_NTXQUEUES; i++) 428 rtwn_free_tx_list(sc, i); 429 rtwn_free_rx_list(sc); 430 431 splx(s); 432 433 callout_destroy(&sc->scan_to); 434 callout_destroy(&sc->calib_to); 435 436 if (sc->init_task != NULL) 437 softint_disestablish(sc->init_task); 438 if (sc->sc_soft_ih != NULL) 439 softint_disestablish(sc->sc_soft_ih); 440 441 if (sc->sc_ih != NULL) { 442 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 443 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 444 } 445 446 return 0; 447 } 448 449 static int 450 rtwn_activate(device_t self, enum devact act) 451 { 452 struct rtwn_softc *sc = device_private(self); 453 struct ifnet *ifp = GET_IFP(sc); 454 455 switch (act) { 456 case DVACT_DEACTIVATE: 457 if (ifp->if_flags & IFF_RUNNING) 458 rtwn_stop(ifp, 0); 459 return 0; 460 default: 461 return EOPNOTSUPP; 462 } 463 } 464 465 static void 466 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 467 bus_addr_t addr, size_t len, int idx) 468 { 469 470 memset(desc, 0, sizeof(*desc)); 471 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 472 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 473 desc->rxbufaddr = htole32(addr); 474 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 475 BUS_SPACE_BARRIER_WRITE); 476 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 477 } 478 479 static int 480 rtwn_alloc_rx_list(struct rtwn_softc *sc) 481 { 482 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 483 struct rtwn_rx_data *rx_data; 484 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 485 int i, error = 0; 486 487 /* Allocate Rx descriptors. */ 488 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 489 &rx_ring->map); 490 if (error != 0) { 491 aprint_error_dev(sc->sc_dev, 492 "could not create rx desc DMA map\n"); 493 rx_ring->map = NULL; 494 goto fail; 495 } 496 497 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 498 &rx_ring->nsegs, BUS_DMA_NOWAIT); 499 if (error != 0) { 500 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 501 goto fail; 502 } 503 504 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 505 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 506 if (error != 0) { 507 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 508 rx_ring->desc = NULL; 509 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 510 goto fail; 511 } 512 memset(rx_ring->desc, 0, size); 513 514 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 515 1, size, BUS_DMA_NOWAIT); 516 if (error != 0) { 517 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 518 goto fail; 519 } 520 521 /* Allocate Rx buffers. */ 522 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 523 rx_data = &rx_ring->rx_data[i]; 524 525 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 526 0, BUS_DMA_NOWAIT, &rx_data->map); 527 if (error != 0) { 528 aprint_error_dev(sc->sc_dev, 529 "could not create rx buf DMA map\n"); 530 goto fail; 531 } 532 533 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 534 if (__predict_false(rx_data->m == NULL)) { 535 aprint_error_dev(sc->sc_dev, 536 "couldn't allocate rx mbuf\n"); 537 error = ENOMEM; 538 goto fail; 539 } 540 MCLGET(rx_data->m, M_DONTWAIT); 541 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 542 aprint_error_dev(sc->sc_dev, 543 "couldn't allocate rx mbuf cluster\n"); 544 m_free(rx_data->m); 545 rx_data->m = NULL; 546 error = ENOMEM; 547 goto fail; 548 } 549 550 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 551 mtod(rx_data->m, void *), MCLBYTES, NULL, 552 BUS_DMA_NOWAIT | BUS_DMA_READ); 553 if (error != 0) { 554 aprint_error_dev(sc->sc_dev, 555 "could not load rx buf DMA map\n"); 556 goto fail; 557 } 558 559 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 560 BUS_DMASYNC_PREREAD); 561 562 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 563 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 564 } 565 fail: if (error != 0) 566 rtwn_free_rx_list(sc); 567 return error; 568 } 569 570 static void 571 rtwn_reset_rx_list(struct rtwn_softc *sc) 572 { 573 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 574 struct rtwn_rx_data *rx_data; 575 int i; 576 577 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 578 rx_data = &rx_ring->rx_data[i]; 579 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 580 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 581 } 582 } 583 584 static void 585 rtwn_free_rx_list(struct rtwn_softc *sc) 586 { 587 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 588 struct rtwn_rx_data *rx_data; 589 int i, s; 590 591 s = splnet(); 592 593 if (rx_ring->map) { 594 if (rx_ring->desc) { 595 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 596 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 597 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 598 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 599 rx_ring->nsegs); 600 rx_ring->desc = NULL; 601 } 602 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 603 rx_ring->map = NULL; 604 } 605 606 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 607 rx_data = &rx_ring->rx_data[i]; 608 609 if (rx_data->m != NULL) { 610 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 611 m_freem(rx_data->m); 612 rx_data->m = NULL; 613 } 614 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 615 rx_data->map = NULL; 616 } 617 618 splx(s); 619 } 620 621 static int 622 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 623 { 624 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 625 struct rtwn_tx_data *tx_data; 626 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 627 int i = 0, error = 0; 628 629 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 630 &tx_ring->map); 631 if (error != 0) { 632 aprint_error_dev(sc->sc_dev, 633 "could not create tx ring DMA map\n"); 634 goto fail; 635 } 636 637 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 638 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 639 if (error != 0) { 640 aprint_error_dev(sc->sc_dev, 641 "could not allocate tx ring DMA memory\n"); 642 goto fail; 643 } 644 645 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 646 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 647 if (error != 0) { 648 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 649 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 650 goto fail; 651 } 652 memset(tx_ring->desc, 0, size); 653 654 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 655 size, NULL, BUS_DMA_NOWAIT); 656 if (error != 0) { 657 aprint_error_dev(sc->sc_dev, 658 "could not load tx ring DMA map\n"); 659 goto fail; 660 } 661 662 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 663 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 664 665 /* setup tx desc */ 666 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 667 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 668 669 tx_data = &tx_ring->tx_data[i]; 670 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 671 0, BUS_DMA_NOWAIT, &tx_data->map); 672 if (error != 0) { 673 aprint_error_dev(sc->sc_dev, 674 "could not create tx buf DMA map\n"); 675 goto fail; 676 } 677 tx_data->m = NULL; 678 tx_data->ni = NULL; 679 } 680 681 fail: 682 if (error != 0) 683 rtwn_free_tx_list(sc, qid); 684 return error; 685 } 686 687 static void 688 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 689 { 690 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 691 int i; 692 693 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 694 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 695 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 696 697 memset(desc, 0, sizeof(*desc) - 698 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 699 sizeof(desc->nextdescaddr))); 700 701 if (tx_data->m != NULL) { 702 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 703 m_freem(tx_data->m); 704 tx_data->m = NULL; 705 ieee80211_free_node(tx_data->ni); 706 tx_data->ni = NULL; 707 } 708 } 709 710 sc->qfullmsk &= ~(1 << qid); 711 tx_ring->queued = 0; 712 tx_ring->cur = 0; 713 } 714 715 static void 716 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 717 { 718 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 719 struct rtwn_tx_data *tx_data; 720 int i; 721 722 if (tx_ring->map != NULL) { 723 if (tx_ring->desc != NULL) { 724 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 725 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 726 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 727 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 728 tx_ring->nsegs); 729 } 730 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 731 } 732 733 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 734 tx_data = &tx_ring->tx_data[i]; 735 736 if (tx_data->m != NULL) { 737 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 738 m_freem(tx_data->m); 739 tx_data->m = NULL; 740 } 741 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 742 } 743 744 sc->qfullmsk &= ~(1 << qid); 745 tx_ring->queued = 0; 746 tx_ring->cur = 0; 747 } 748 749 static void 750 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 751 { 752 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 753 } 754 755 static void 756 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 757 { 758 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 759 } 760 761 static void 762 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 763 { 764 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 765 } 766 767 static uint8_t 768 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 769 { 770 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 771 } 772 773 static uint16_t 774 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 775 { 776 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 777 } 778 779 static uint32_t 780 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 781 { 782 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 783 } 784 785 static int 786 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 787 { 788 struct r92c_fw_cmd cmd; 789 uint8_t *cp; 790 int fwcur; 791 int ntries; 792 793 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 794 device_xname(sc->sc_dev), __func__, id, buf, len)); 795 796 fwcur = sc->fwcur; 797 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 798 799 /* Wait for current FW box to be empty. */ 800 for (ntries = 0; ntries < 100; ntries++) { 801 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 802 break; 803 DELAY(1); 804 } 805 if (ntries == 100) { 806 aprint_error_dev(sc->sc_dev, 807 "could not send firmware command %d\n", id); 808 return ETIMEDOUT; 809 } 810 811 memset(&cmd, 0, sizeof(cmd)); 812 KASSERT(len <= sizeof(cmd.msg)); 813 memcpy(cmd.msg, buf, len); 814 815 /* Write the first word last since that will trigger the FW. */ 816 cp = (uint8_t *)&cmd; 817 if (len >= 4) { 818 cmd.id = id | R92C_CMD_FLAG_EXT; 819 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 820 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 821 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 822 } else { 823 cmd.id = id; 824 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 825 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 826 } 827 828 /* Give firmware some time for processing. */ 829 DELAY(2000); 830 831 return 0; 832 } 833 834 static void 835 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 836 { 837 838 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 839 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 840 } 841 842 static uint32_t 843 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 844 { 845 uint32_t reg[R92C_MAX_CHAINS], val; 846 847 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 848 if (chain != 0) 849 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 850 851 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 852 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 853 DELAY(1000); 854 855 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 856 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 857 R92C_HSSI_PARAM2_READ_EDGE); 858 DELAY(1000); 859 860 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 861 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 862 DELAY(1000); 863 864 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 865 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 866 else 867 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 868 return MS(val, R92C_LSSI_READBACK_DATA); 869 } 870 871 static int 872 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 873 { 874 int ntries; 875 876 rtwn_write_4(sc, R92C_LLT_INIT, 877 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 878 SM(R92C_LLT_INIT_ADDR, addr) | 879 SM(R92C_LLT_INIT_DATA, data)); 880 /* Wait for write operation to complete. */ 881 for (ntries = 0; ntries < 20; ntries++) { 882 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 883 R92C_LLT_INIT_OP_NO_ACTIVE) 884 return 0; 885 DELAY(5); 886 } 887 return ETIMEDOUT; 888 } 889 890 static uint8_t 891 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 892 { 893 uint32_t reg; 894 int ntries; 895 896 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 897 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 898 reg &= ~R92C_EFUSE_CTRL_VALID; 899 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 900 /* Wait for read operation to complete. */ 901 for (ntries = 0; ntries < 100; ntries++) { 902 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 903 if (reg & R92C_EFUSE_CTRL_VALID) 904 return MS(reg, R92C_EFUSE_CTRL_DATA); 905 DELAY(5); 906 } 907 aprint_error_dev(sc->sc_dev, 908 "could not read efuse byte at address 0x%x\n", addr); 909 return 0xff; 910 } 911 912 static void 913 rtwn_efuse_read(struct rtwn_softc *sc) 914 { 915 uint8_t *rom = (uint8_t *)&sc->rom; 916 uint32_t reg; 917 uint16_t addr = 0; 918 uint8_t off, msk; 919 int i; 920 921 rtwn_efuse_switch_power(sc); 922 923 memset(&sc->rom, 0xff, sizeof(sc->rom)); 924 while (addr < 512) { 925 reg = rtwn_efuse_read_1(sc, addr); 926 if (reg == 0xff) 927 break; 928 addr++; 929 off = reg >> 4; 930 msk = reg & 0xf; 931 for (i = 0; i < 4; i++) { 932 if (msk & (1 << i)) 933 continue; 934 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 935 addr++; 936 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 937 addr++; 938 } 939 } 940 #ifdef RTWN_DEBUG 941 if (rtwn_debug >= 2) { 942 /* Dump ROM content. */ 943 printf("\n"); 944 for (i = 0; i < sizeof(sc->rom); i++) 945 printf("%02x:", rom[i]); 946 printf("\n"); 947 } 948 #endif 949 } 950 951 static void 952 rtwn_efuse_switch_power(struct rtwn_softc *sc) 953 { 954 uint32_t reg; 955 956 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 957 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 958 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 959 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 960 } 961 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 962 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 963 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 964 reg | R92C_SYS_FUNC_EN_ELDR); 965 } 966 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 967 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 968 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 969 rtwn_write_2(sc, R92C_SYS_CLKR, 970 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 971 } 972 } 973 974 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 975 static int 976 rtwn_read_chipid(struct rtwn_softc *sc) 977 { 978 uint32_t reg; 979 980 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 981 982 reg = rtwn_read_4(sc, R92C_SYS_CFG); 983 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 984 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 985 /* Unsupported test chip. */ 986 return EIO; 987 988 if (reg & R92C_SYS_CFG_TYPE_92C) { 989 sc->chip |= RTWN_CHIP_92C; 990 /* Check if it is a castrated 8192C. */ 991 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 992 R92C_HPON_FSM_CHIP_BONDING_ID) == 993 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 994 sc->chip |= RTWN_CHIP_92C_1T2R; 995 } 996 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 997 sc->chip |= RTWN_CHIP_UMC; 998 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 999 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1000 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 1001 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 1002 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 1003 else 1004 /* Unsupported unknown chip. */ 1005 return EIO; 1006 } 1007 return 0; 1008 } 1009 1010 static void 1011 rtwn_read_rom(struct rtwn_softc *sc) 1012 { 1013 struct ieee80211com *ic = &sc->sc_ic; 1014 struct r92c_rom *rom = &sc->rom; 1015 1016 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1017 1018 /* Read full ROM image. */ 1019 rtwn_efuse_read(sc); 1020 1021 if (rom->id != 0x8129) { 1022 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1023 rom->id); 1024 } 1025 1026 /* XXX Weird but this is what the vendor driver does. */ 1027 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1028 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1029 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1030 1031 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1032 sc->pa_setting, sc->board_type, sc->regulatory)); 1033 1034 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1035 } 1036 1037 static int 1038 rtwn_media_change(struct ifnet *ifp) 1039 { 1040 int error; 1041 1042 error = ieee80211_media_change(ifp); 1043 if (error != ENETRESET) 1044 return error; 1045 1046 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1047 (IFF_UP | IFF_RUNNING)) { 1048 rtwn_stop(ifp, 0); 1049 error = rtwn_init(ifp); 1050 } 1051 return error; 1052 } 1053 1054 /* 1055 * Initialize rate adaptation in firmware. 1056 */ 1057 static int 1058 rtwn_ra_init(struct rtwn_softc *sc) 1059 { 1060 static const uint8_t map[] = { 1061 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1062 }; 1063 struct ieee80211com *ic = &sc->sc_ic; 1064 struct ieee80211_node *ni = ic->ic_bss; 1065 struct ieee80211_rateset *rs = &ni->ni_rates; 1066 struct r92c_fw_cmd_macid_cfg cmd; 1067 uint32_t rates, basicrates; 1068 uint8_t mode; 1069 int maxrate, maxbasicrate, error, i, j; 1070 1071 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1072 1073 /* Get normal and basic rates mask. */ 1074 rates = basicrates = 0; 1075 maxrate = maxbasicrate = 0; 1076 for (i = 0; i < rs->rs_nrates; i++) { 1077 /* Convert 802.11 rate to HW rate index. */ 1078 for (j = 0; j < __arraycount(map); j++) 1079 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1080 break; 1081 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1082 continue; 1083 rates |= 1 << j; 1084 if (j > maxrate) 1085 maxrate = j; 1086 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1087 basicrates |= 1 << j; 1088 if (j > maxbasicrate) 1089 maxbasicrate = j; 1090 } 1091 } 1092 if (ic->ic_curmode == IEEE80211_MODE_11B) 1093 mode = R92C_RAID_11B; 1094 else 1095 mode = R92C_RAID_11BG; 1096 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1097 device_xname(sc->sc_dev), mode, rates, basicrates)); 1098 if (basicrates == 0) 1099 basicrates |= 1; /* add 1Mbps */ 1100 1101 /* Set rates mask for group addressed frames. */ 1102 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1103 cmd.mask = htole32((mode << 28) | basicrates); 1104 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1105 if (error != 0) { 1106 aprint_error_dev(sc->sc_dev, 1107 "could not add broadcast station\n"); 1108 return error; 1109 } 1110 /* Set initial MRR rate. */ 1111 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1112 maxbasicrate)); 1113 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1114 1115 /* Set rates mask for unicast frames. */ 1116 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1117 cmd.mask = htole32((mode << 28) | rates); 1118 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1119 if (error != 0) { 1120 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1121 return error; 1122 } 1123 /* Set initial MRR rate. */ 1124 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1125 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1126 1127 /* Configure Automatic Rate Fallback Register. */ 1128 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1129 if (rates & 0x0c) 1130 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1131 else 1132 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1133 } else 1134 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1135 1136 /* Indicate highest supported rate. */ 1137 ni->ni_txrate = rs->rs_nrates - 1; 1138 return 0; 1139 } 1140 1141 static int 1142 rtwn_get_nettype(struct rtwn_softc *sc) 1143 { 1144 struct ieee80211com *ic = &sc->sc_ic; 1145 int type; 1146 1147 switch (ic->ic_opmode) { 1148 case IEEE80211_M_STA: 1149 type = R92C_CR_NETTYPE_INFRA; 1150 break; 1151 1152 case IEEE80211_M_HOSTAP: 1153 type = R92C_CR_NETTYPE_AP; 1154 break; 1155 1156 case IEEE80211_M_IBSS: 1157 type = R92C_CR_NETTYPE_ADHOC; 1158 break; 1159 1160 default: 1161 type = R92C_CR_NETTYPE_NOLINK; 1162 break; 1163 } 1164 1165 return type; 1166 } 1167 1168 static void 1169 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1170 { 1171 uint32_t reg; 1172 1173 reg = rtwn_read_4(sc, R92C_CR); 1174 reg = RW(reg, R92C_CR_NETTYPE, type); 1175 rtwn_write_4(sc, R92C_CR, reg); 1176 } 1177 1178 static void 1179 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1180 { 1181 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1182 uint64_t tsf; 1183 1184 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1185 1186 /* Enable TSF synchronization. */ 1187 rtwn_write_1(sc, R92C_BCN_CTRL, 1188 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1189 1190 rtwn_write_1(sc, R92C_BCN_CTRL, 1191 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1192 1193 /* Set initial TSF. */ 1194 tsf = ni->ni_tstamp.tsf; 1195 tsf = le64toh(tsf); 1196 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1197 tsf -= IEEE80211_DUR_TU; 1198 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1199 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1200 1201 rtwn_write_1(sc, R92C_BCN_CTRL, 1202 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1203 } 1204 1205 static void 1206 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1207 { 1208 uint8_t reg; 1209 1210 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1211 1212 if (led == RTWN_LED_LINK) { 1213 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1214 if (!on) 1215 reg |= R92C_LEDCFG2_DIS; 1216 else 1217 reg |= R92C_LEDCFG2_EN; 1218 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1219 sc->ledlink = on; /* Save LED state. */ 1220 } 1221 } 1222 1223 static void 1224 rtwn_calib_to(void *arg) 1225 { 1226 struct rtwn_softc *sc = arg; 1227 struct r92c_fw_cmd_rssi cmd; 1228 int s; 1229 1230 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1231 1232 s = splnet(); 1233 1234 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1235 goto restart_timer; 1236 1237 if (sc->avg_pwdb != -1) { 1238 /* Indicate Rx signal strength to FW for rate adaptation. */ 1239 memset(&cmd, 0, sizeof(cmd)); 1240 cmd.macid = 0; /* BSS. */ 1241 cmd.pwdb = sc->avg_pwdb; 1242 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1243 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1244 } 1245 1246 /* Do temperature compensation. */ 1247 rtwn_temp_calib(sc); 1248 1249 restart_timer: 1250 callout_schedule(&sc->calib_to, mstohz(2000)); 1251 1252 splx(s); 1253 } 1254 1255 static void 1256 rtwn_next_scan(void *arg) 1257 { 1258 struct rtwn_softc *sc = arg; 1259 struct ieee80211com *ic = &sc->sc_ic; 1260 int s; 1261 1262 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1263 1264 s = splnet(); 1265 if (ic->ic_state == IEEE80211_S_SCAN) 1266 ieee80211_next_scan(ic); 1267 splx(s); 1268 } 1269 1270 static void 1271 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1272 { 1273 1274 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1275 1276 /* start with lowest Tx rate */ 1277 ni->ni_txrate = 0; 1278 } 1279 1280 static int 1281 rtwn_reset(struct ifnet *ifp) 1282 { 1283 struct rtwn_softc *sc = ifp->if_softc; 1284 struct ieee80211com *ic = &sc->sc_ic; 1285 1286 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1287 return ENETRESET; 1288 1289 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1290 1291 return 0; 1292 } 1293 1294 static int 1295 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1296 { 1297 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1298 struct ieee80211_node *ni; 1299 enum ieee80211_state ostate = ic->ic_state; 1300 uint32_t reg; 1301 int s; 1302 1303 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1304 1305 s = splnet(); 1306 1307 callout_stop(&sc->scan_to); 1308 callout_stop(&sc->calib_to); 1309 1310 if (ostate != nstate) { 1311 DPRINTF(("%s: %s -> %s\n", __func__, 1312 ieee80211_state_name[ostate], 1313 ieee80211_state_name[nstate])); 1314 } 1315 1316 switch (ostate) { 1317 case IEEE80211_S_INIT: 1318 break; 1319 1320 case IEEE80211_S_SCAN: 1321 if (nstate != IEEE80211_S_SCAN) { 1322 /* 1323 * End of scanning 1324 */ 1325 /* flush 4-AC Queue after site_survey */ 1326 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1327 1328 /* Allow Rx from our BSSID only. */ 1329 rtwn_write_4(sc, R92C_RCR, 1330 rtwn_read_4(sc, R92C_RCR) | 1331 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1332 } 1333 break; 1334 1335 case IEEE80211_S_AUTH: 1336 case IEEE80211_S_ASSOC: 1337 break; 1338 1339 case IEEE80211_S_RUN: 1340 /* Turn link LED off. */ 1341 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1342 1343 /* Set media status to 'No Link'. */ 1344 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1345 1346 /* Stop Rx of data frames. */ 1347 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1348 1349 /* Rest TSF. */ 1350 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1351 1352 /* Disable TSF synchronization. */ 1353 rtwn_write_1(sc, R92C_BCN_CTRL, 1354 rtwn_read_1(sc, R92C_BCN_CTRL) | 1355 R92C_BCN_CTRL_DIS_TSF_UDT0); 1356 1357 /* Back to 20MHz mode */ 1358 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1359 1360 /* Reset EDCA parameters. */ 1361 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1362 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1363 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1364 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1365 1366 /* flush all cam entries */ 1367 rtwn_cam_init(sc); 1368 break; 1369 } 1370 1371 switch (nstate) { 1372 case IEEE80211_S_INIT: 1373 /* Turn link LED off. */ 1374 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1375 break; 1376 1377 case IEEE80211_S_SCAN: 1378 if (ostate != IEEE80211_S_SCAN) { 1379 /* 1380 * Begin of scanning 1381 */ 1382 1383 /* Set gain for scanning. */ 1384 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1385 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1386 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1387 1388 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1389 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1390 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1391 1392 /* Allow Rx from any BSSID. */ 1393 rtwn_write_4(sc, R92C_RCR, 1394 rtwn_read_4(sc, R92C_RCR) & 1395 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1396 1397 /* Stop Rx of data frames. */ 1398 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1399 1400 /* Disable update TSF */ 1401 rtwn_write_1(sc, R92C_BCN_CTRL, 1402 rtwn_read_1(sc, R92C_BCN_CTRL) | 1403 R92C_BCN_CTRL_DIS_TSF_UDT0); 1404 } 1405 1406 /* Make link LED blink during scan. */ 1407 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1408 1409 /* Pause AC Tx queues. */ 1410 rtwn_write_1(sc, R92C_TXPAUSE, 1411 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1412 1413 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1414 1415 /* Start periodic scan. */ 1416 callout_schedule(&sc->scan_to, mstohz(200)); 1417 break; 1418 1419 case IEEE80211_S_AUTH: 1420 /* Set initial gain under link. */ 1421 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1422 #ifdef doaslinux 1423 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1424 #else 1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1426 #endif 1427 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1428 1429 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1430 #ifdef doaslinux 1431 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1432 #else 1433 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1434 #endif 1435 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1436 1437 /* Set media status to 'No Link'. */ 1438 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1439 1440 /* Allow Rx from any BSSID. */ 1441 rtwn_write_4(sc, R92C_RCR, 1442 rtwn_read_4(sc, R92C_RCR) & 1443 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1444 1445 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1446 break; 1447 1448 case IEEE80211_S_ASSOC: 1449 break; 1450 1451 case IEEE80211_S_RUN: 1452 ni = ic->ic_bss; 1453 1454 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1455 1456 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1457 /* Back to 20Mhz mode */ 1458 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1459 1460 /* Set media status to 'No Link'. */ 1461 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1462 1463 /* Enable Rx of data frames. */ 1464 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1465 1466 /* Allow Rx from any BSSID. */ 1467 rtwn_write_4(sc, R92C_RCR, 1468 rtwn_read_4(sc, R92C_RCR) & 1469 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1470 1471 /* Accept Rx data/control/management frames */ 1472 rtwn_write_4(sc, R92C_RCR, 1473 rtwn_read_4(sc, R92C_RCR) | 1474 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1475 1476 /* Turn link LED on. */ 1477 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1478 break; 1479 } 1480 1481 /* Set media status to 'Associated'. */ 1482 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1483 1484 /* Set BSSID. */ 1485 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1486 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1487 1488 if (ic->ic_curmode == IEEE80211_MODE_11B) 1489 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1490 else /* 802.11b/g */ 1491 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1492 1493 /* Enable Rx of data frames. */ 1494 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1495 1496 /* Flush all AC queues. */ 1497 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1498 1499 /* Set beacon interval. */ 1500 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1501 1502 switch (ic->ic_opmode) { 1503 case IEEE80211_M_STA: 1504 /* Allow Rx from our BSSID only. */ 1505 rtwn_write_4(sc, R92C_RCR, 1506 rtwn_read_4(sc, R92C_RCR) | 1507 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1508 1509 /* Enable TSF synchronization. */ 1510 rtwn_tsf_sync_enable(sc); 1511 break; 1512 1513 case IEEE80211_M_HOSTAP: 1514 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1515 1516 /* Allow Rx from any BSSID. */ 1517 rtwn_write_4(sc, R92C_RCR, 1518 rtwn_read_4(sc, R92C_RCR) & 1519 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1520 1521 /* Reset TSF timer to zero. */ 1522 reg = rtwn_read_4(sc, R92C_TCR); 1523 reg &= ~0x01; 1524 rtwn_write_4(sc, R92C_TCR, reg); 1525 reg |= 0x01; 1526 rtwn_write_4(sc, R92C_TCR, reg); 1527 break; 1528 1529 case IEEE80211_M_MONITOR: 1530 default: 1531 break; 1532 } 1533 1534 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1535 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1536 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1537 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1538 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1539 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1540 1541 /* Intialize rate adaptation. */ 1542 rtwn_ra_init(sc); 1543 1544 /* Turn link LED on. */ 1545 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1546 1547 /* Reset average RSSI. */ 1548 sc->avg_pwdb = -1; 1549 1550 /* Reset temperature calibration state machine. */ 1551 sc->thcal_state = 0; 1552 sc->thcal_lctemp = 0; 1553 1554 /* Start periodic calibration. */ 1555 callout_schedule(&sc->calib_to, mstohz(2000)); 1556 break; 1557 } 1558 1559 (void)sc->sc_newstate(ic, nstate, arg); 1560 1561 splx(s); 1562 1563 return 0; 1564 } 1565 1566 static int 1567 rtwn_wme_update(struct ieee80211com *ic) 1568 { 1569 static const uint16_t aci2reg[WME_NUM_AC] = { 1570 R92C_EDCA_BE_PARAM, 1571 R92C_EDCA_BK_PARAM, 1572 R92C_EDCA_VI_PARAM, 1573 R92C_EDCA_VO_PARAM 1574 }; 1575 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1576 const struct wmeParams *wmep; 1577 int s, aci, aifs, slottime; 1578 1579 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1580 1581 s = splnet(); 1582 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1583 for (aci = 0; aci < WME_NUM_AC; aci++) { 1584 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1585 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1586 aifs = wmep->wmep_aifsn * slottime + 10; 1587 rtwn_write_4(sc, aci2reg[aci], 1588 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1589 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1590 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1591 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1592 } 1593 splx(s); 1594 1595 return 0; 1596 } 1597 1598 static void 1599 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1600 { 1601 int pwdb; 1602 1603 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1604 1605 /* Convert antenna signal to percentage. */ 1606 if (rssi <= -100 || rssi >= 20) 1607 pwdb = 0; 1608 else if (rssi >= 0) 1609 pwdb = 100; 1610 else 1611 pwdb = 100 + rssi; 1612 if (rate <= 3) { 1613 /* CCK gain is smaller than OFDM/MCS gain. */ 1614 pwdb += 6; 1615 if (pwdb > 100) 1616 pwdb = 100; 1617 if (pwdb <= 14) 1618 pwdb -= 4; 1619 else if (pwdb <= 26) 1620 pwdb -= 8; 1621 else if (pwdb <= 34) 1622 pwdb -= 6; 1623 else if (pwdb <= 42) 1624 pwdb -= 2; 1625 } 1626 if (sc->avg_pwdb == -1) /* Init. */ 1627 sc->avg_pwdb = pwdb; 1628 else if (sc->avg_pwdb < pwdb) 1629 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1630 else 1631 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1632 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1633 } 1634 1635 static int8_t 1636 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1637 { 1638 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1639 struct r92c_rx_phystat *phy; 1640 struct r92c_rx_cck *cck; 1641 uint8_t rpt; 1642 int8_t rssi; 1643 1644 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1645 1646 if (rate <= 3) { 1647 cck = (struct r92c_rx_cck *)physt; 1648 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1649 rpt = (cck->agc_rpt >> 5) & 0x3; 1650 rssi = (cck->agc_rpt & 0x1f) << 1; 1651 } else { 1652 rpt = (cck->agc_rpt >> 6) & 0x3; 1653 rssi = cck->agc_rpt & 0x3e; 1654 } 1655 rssi = cckoff[rpt] - rssi; 1656 } else { /* OFDM/HT. */ 1657 phy = (struct r92c_rx_phystat *)physt; 1658 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1659 } 1660 return rssi; 1661 } 1662 1663 static void 1664 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1665 struct rtwn_rx_data *rx_data, int desc_idx) 1666 { 1667 struct ieee80211com *ic = &sc->sc_ic; 1668 struct ifnet *ifp = IC2IFP(ic); 1669 struct ieee80211_frame *wh; 1670 struct ieee80211_node *ni; 1671 struct r92c_rx_phystat *phy = NULL; 1672 uint32_t rxdw0, rxdw3; 1673 struct mbuf *m, *m1; 1674 uint8_t rate; 1675 int8_t rssi = 0; 1676 int infosz, pktlen, shift, totlen, error, s; 1677 1678 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1679 1680 rxdw0 = le32toh(rx_desc->rxdw0); 1681 rxdw3 = le32toh(rx_desc->rxdw3); 1682 1683 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1684 /* 1685 * This should not happen since we setup our Rx filter 1686 * to not receive these frames. 1687 */ 1688 ifp->if_ierrors++; 1689 return; 1690 } 1691 1692 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1693 /* 1694 * XXX: This will drop most control packets. Do we really 1695 * want this in IEEE80211_M_MONITOR mode? 1696 */ 1697 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1698 ic->ic_stats.is_rx_tooshort++; 1699 ifp->if_ierrors++; 1700 return; 1701 } 1702 if (__predict_false(pktlen > MCLBYTES)) { 1703 ifp->if_ierrors++; 1704 return; 1705 } 1706 1707 rate = MS(rxdw3, R92C_RXDW3_RATE); 1708 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1709 if (infosz > sizeof(struct r92c_rx_phystat)) 1710 infosz = sizeof(struct r92c_rx_phystat); 1711 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1712 totlen = pktlen + infosz + shift; 1713 1714 /* Get RSSI from PHY status descriptor if present. */ 1715 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1716 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1717 rssi = rtwn_get_rssi(sc, rate, phy); 1718 /* Update our average RSSI. */ 1719 rtwn_update_avgrssi(sc, rate, rssi); 1720 } 1721 1722 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1723 pktlen, rate, infosz, shift, rssi)); 1724 1725 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1726 if (__predict_false(m1 == NULL)) { 1727 ic->ic_stats.is_rx_nobuf++; 1728 ifp->if_ierrors++; 1729 return; 1730 } 1731 MCLGET(m1, M_DONTWAIT); 1732 if (__predict_false(!(m1->m_flags & M_EXT))) { 1733 m_freem(m1); 1734 ic->ic_stats.is_rx_nobuf++; 1735 ifp->if_ierrors++; 1736 return; 1737 } 1738 1739 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1740 BUS_DMASYNC_POSTREAD); 1741 1742 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1743 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1744 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1745 if (error != 0) { 1746 m_freem(m1); 1747 1748 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1749 rx_data->m, BUS_DMA_NOWAIT)) 1750 panic("%s: could not load old RX mbuf", 1751 device_xname(sc->sc_dev)); 1752 1753 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1754 BUS_DMASYNC_PREREAD); 1755 1756 /* Physical address may have changed. */ 1757 rtwn_setup_rx_desc(sc, rx_desc, 1758 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1759 1760 ifp->if_ierrors++; 1761 return; 1762 } 1763 1764 /* Finalize mbuf. */ 1765 m = rx_data->m; 1766 rx_data->m = m1; 1767 m->m_pkthdr.len = m->m_len = totlen; 1768 m_set_rcvif(m, ifp); 1769 1770 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1771 BUS_DMASYNC_PREREAD); 1772 1773 /* Update RX descriptor. */ 1774 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1775 MCLBYTES, desc_idx); 1776 1777 /* Get ieee80211 frame header. */ 1778 if (rxdw0 & R92C_RXDW0_PHYST) 1779 m_adj(m, infosz + shift); 1780 else 1781 m_adj(m, shift); 1782 wh = mtod(m, struct ieee80211_frame *); 1783 1784 s = splnet(); 1785 1786 if (__predict_false(sc->sc_drvbpf != NULL)) { 1787 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1788 1789 tap->wr_flags = 0; 1790 /* Map HW rate index to 802.11 rate. */ 1791 tap->wr_flags = 2; 1792 if (!(rxdw3 & R92C_RXDW3_HT)) { 1793 switch (rate) { 1794 /* CCK. */ 1795 case 0: tap->wr_rate = 2; break; 1796 case 1: tap->wr_rate = 4; break; 1797 case 2: tap->wr_rate = 11; break; 1798 case 3: tap->wr_rate = 22; break; 1799 /* OFDM. */ 1800 case 4: tap->wr_rate = 12; break; 1801 case 5: tap->wr_rate = 18; break; 1802 case 6: tap->wr_rate = 24; break; 1803 case 7: tap->wr_rate = 36; break; 1804 case 8: tap->wr_rate = 48; break; 1805 case 9: tap->wr_rate = 72; break; 1806 case 10: tap->wr_rate = 96; break; 1807 case 11: tap->wr_rate = 108; break; 1808 } 1809 } else if (rate >= 12) { /* MCS0~15. */ 1810 /* Bit 7 set means HT MCS instead of rate. */ 1811 tap->wr_rate = 0x80 | (rate - 12); 1812 } 1813 tap->wr_dbm_antsignal = rssi; 1814 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1815 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1816 1817 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1818 } 1819 1820 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1821 1822 /* push the frame up to the 802.11 stack */ 1823 ieee80211_input(ic, m, ni, rssi, 0); 1824 1825 /* Node is no longer needed. */ 1826 ieee80211_free_node(ni); 1827 1828 splx(s); 1829 } 1830 1831 static int 1832 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1833 { 1834 struct ieee80211com *ic = &sc->sc_ic; 1835 struct ieee80211_frame *wh; 1836 struct ieee80211_key *k = NULL; 1837 struct rtwn_tx_ring *tx_ring; 1838 struct rtwn_tx_data *data; 1839 struct r92c_tx_desc *txd; 1840 uint16_t qos, seq; 1841 uint8_t raid, type, tid, qid; 1842 int hasqos, error; 1843 1844 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1845 1846 wh = mtod(m, struct ieee80211_frame *); 1847 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1848 1849 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1850 k = ieee80211_crypto_encap(ic, ni, m); 1851 if (k == NULL) 1852 return ENOBUFS; 1853 1854 wh = mtod(m, struct ieee80211_frame *); 1855 } 1856 1857 if ((hasqos = ieee80211_has_qos(wh))) { 1858 /* data frames in 11n mode */ 1859 qos = ieee80211_get_qos(wh); 1860 tid = qos & IEEE80211_QOS_TID; 1861 qid = TID_TO_WME_AC(tid); 1862 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1863 /* Use AC_VO for management frames. */ 1864 tid = 0; /* compiler happy */ 1865 qid = RTWN_VO_QUEUE; 1866 } else { 1867 /* non-qos data frames */ 1868 tid = R92C_TXDW1_QSEL_BE; 1869 qid = RTWN_BE_QUEUE; 1870 } 1871 1872 /* Grab a Tx buffer from the ring. */ 1873 tx_ring = &sc->tx_ring[qid]; 1874 data = &tx_ring->tx_data[tx_ring->cur]; 1875 if (data->m != NULL) { 1876 m_freem(m); 1877 return ENOBUFS; 1878 } 1879 1880 /* Fill Tx descriptor. */ 1881 txd = &tx_ring->desc[tx_ring->cur]; 1882 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1883 m_freem(m); 1884 return ENOBUFS; 1885 } 1886 1887 txd->txdw0 = htole32( 1888 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1889 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1890 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1891 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1892 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1893 1894 txd->txdw1 = 0; 1895 txd->txdw4 = 0; 1896 txd->txdw5 = 0; 1897 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1898 type == IEEE80211_FC0_TYPE_DATA) { 1899 if (ic->ic_curmode == IEEE80211_MODE_11B) 1900 raid = R92C_RAID_11B; 1901 else 1902 raid = R92C_RAID_11BG; 1903 1904 txd->txdw1 |= htole32( 1905 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1906 SM(R92C_TXDW1_QSEL, tid) | 1907 SM(R92C_TXDW1_RAID, raid) | 1908 R92C_TXDW1_AGGBK); 1909 1910 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1911 /* for 11g */ 1912 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1913 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1914 R92C_TXDW4_HWRTSEN); 1915 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1916 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1917 R92C_TXDW4_HWRTSEN); 1918 } 1919 } 1920 /* Send RTS at OFDM24. */ 1921 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1922 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1923 /* Send data at OFDM54. */ 1924 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1925 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1926 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1927 txd->txdw1 |= htole32( 1928 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1929 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1930 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1931 1932 /* Force CCK1. */ 1933 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1934 /* Use 1Mbps */ 1935 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1936 } else { 1937 txd->txdw1 |= htole32( 1938 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1939 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1940 1941 /* Force CCK1. */ 1942 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1943 /* Use 1Mbps */ 1944 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1945 } 1946 1947 /* Set sequence number (already little endian). */ 1948 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1949 txd->txdseq = htole16(seq); 1950 1951 if (!hasqos) { 1952 /* Use HW sequence numbering for non-QoS frames. */ 1953 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1954 txd->txdseq |= htole16(0x8000); /* WTF? */ 1955 } else 1956 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1957 1958 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1959 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1960 if (error && error != EFBIG) { 1961 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1962 error); 1963 m_freem(m); 1964 return error; 1965 } 1966 if (error != 0) { 1967 /* Too many DMA segments, linearize mbuf. */ 1968 struct mbuf *newm = m_defrag(m, M_DONTWAIT); 1969 if (newm == NULL) { 1970 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1971 m_freem(m); 1972 return ENOBUFS; 1973 } 1974 m = newm; 1975 1976 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1977 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1978 if (error != 0) { 1979 aprint_error_dev(sc->sc_dev, 1980 "can't map mbuf (error %d)\n", error); 1981 m_freem(m); 1982 return error; 1983 } 1984 } 1985 1986 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1987 txd->txbufsize = htole16(m->m_pkthdr.len); 1988 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1989 BUS_SPACE_BARRIER_WRITE); 1990 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1991 1992 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1993 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1994 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1995 BUS_DMASYNC_PREWRITE); 1996 1997 data->m = m; 1998 data->ni = ni; 1999 2000 if (__predict_false(sc->sc_drvbpf != NULL)) { 2001 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2002 2003 tap->wt_flags = 0; 2004 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2005 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2006 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2007 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2008 2009 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 2010 } 2011 2012 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2013 tx_ring->queued++; 2014 2015 if (tx_ring->queued > RTWN_TX_LIST_HIMARK) 2016 sc->qfullmsk |= (1 << qid); 2017 2018 /* Kick TX. */ 2019 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2020 2021 return 0; 2022 } 2023 2024 static void 2025 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2026 { 2027 struct ieee80211com *ic = &sc->sc_ic; 2028 struct ifnet *ifp = IC2IFP(ic); 2029 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2030 struct rtwn_tx_data *tx_data; 2031 struct r92c_tx_desc *tx_desc; 2032 int i, s; 2033 2034 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2035 qid)); 2036 2037 s = splnet(); 2038 2039 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2040 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2041 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2042 2043 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2044 tx_data = &tx_ring->tx_data[i]; 2045 if (tx_data->m == NULL) 2046 continue; 2047 2048 tx_desc = &tx_ring->desc[i]; 2049 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2050 continue; 2051 2052 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2053 m_freem(tx_data->m); 2054 tx_data->m = NULL; 2055 ieee80211_free_node(tx_data->ni); 2056 tx_data->ni = NULL; 2057 2058 ifp->if_opackets++; 2059 sc->sc_tx_timer = 0; 2060 tx_ring->queued--; 2061 } 2062 2063 if (tx_ring->queued < RTWN_TX_LIST_LOMARK) 2064 sc->qfullmsk &= ~(1 << qid); 2065 2066 splx(s); 2067 } 2068 2069 static void 2070 rtwn_start(struct ifnet *ifp) 2071 { 2072 struct rtwn_softc *sc = ifp->if_softc; 2073 struct ieee80211com *ic = &sc->sc_ic; 2074 struct ether_header *eh; 2075 struct ieee80211_node *ni; 2076 struct mbuf *m; 2077 2078 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2079 return; 2080 2081 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2082 2083 for (;;) { 2084 if (sc->qfullmsk != 0) { 2085 ifp->if_flags |= IFF_OACTIVE; 2086 break; 2087 } 2088 /* Send pending management frames first. */ 2089 IF_DEQUEUE(&ic->ic_mgtq, m); 2090 if (m != NULL) { 2091 ni = M_GETCTX(m, struct ieee80211_node *); 2092 M_CLEARCTX(m); 2093 goto sendit; 2094 } 2095 if (ic->ic_state != IEEE80211_S_RUN) 2096 break; 2097 2098 /* Encapsulate and send data frames. */ 2099 IFQ_DEQUEUE(&ifp->if_snd, m); 2100 if (m == NULL) 2101 break; 2102 2103 if (m->m_len < (int)sizeof(*eh) && 2104 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2105 ifp->if_oerrors++; 2106 continue; 2107 } 2108 eh = mtod(m, struct ether_header *); 2109 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2110 if (ni == NULL) { 2111 m_freem(m); 2112 ifp->if_oerrors++; 2113 continue; 2114 } 2115 2116 bpf_mtap(ifp, m); 2117 2118 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2119 ieee80211_free_node(ni); 2120 ifp->if_oerrors++; 2121 continue; 2122 } 2123 sendit: 2124 bpf_mtap3(ic->ic_rawbpf, m); 2125 2126 if (rtwn_tx(sc, m, ni) != 0) { 2127 ieee80211_free_node(ni); 2128 ifp->if_oerrors++; 2129 continue; 2130 } 2131 2132 sc->sc_tx_timer = 5; 2133 ifp->if_timer = 1; 2134 } 2135 2136 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2137 } 2138 2139 static void 2140 rtwn_watchdog(struct ifnet *ifp) 2141 { 2142 struct rtwn_softc *sc = ifp->if_softc; 2143 struct ieee80211com *ic = &sc->sc_ic; 2144 2145 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2146 2147 ifp->if_timer = 0; 2148 2149 if (sc->sc_tx_timer > 0) { 2150 if (--sc->sc_tx_timer == 0) { 2151 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2152 softint_schedule(sc->init_task); 2153 ifp->if_oerrors++; 2154 return; 2155 } 2156 ifp->if_timer = 1; 2157 } 2158 ieee80211_watchdog(ic); 2159 } 2160 2161 static int 2162 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2163 { 2164 struct rtwn_softc *sc = ifp->if_softc; 2165 struct ieee80211com *ic = &sc->sc_ic; 2166 int s, error = 0; 2167 2168 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2169 __func__, cmd, data)); 2170 2171 s = splnet(); 2172 2173 switch (cmd) { 2174 case SIOCSIFFLAGS: 2175 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2176 break; 2177 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2178 case IFF_UP | IFF_RUNNING: 2179 break; 2180 case IFF_UP: 2181 error = rtwn_init(ifp); 2182 if (error != 0) 2183 ifp->if_flags &= ~IFF_UP; 2184 break; 2185 case IFF_RUNNING: 2186 rtwn_stop(ifp, 1); 2187 break; 2188 case 0: 2189 break; 2190 } 2191 break; 2192 2193 case SIOCADDMULTI: 2194 case SIOCDELMULTI: 2195 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2196 /* setup multicast filter, etc */ 2197 error = 0; 2198 } 2199 break; 2200 2201 case SIOCS80211CHANNEL: 2202 error = ieee80211_ioctl(ic, cmd, data); 2203 if (error == ENETRESET && 2204 ic->ic_opmode == IEEE80211_M_MONITOR) { 2205 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2206 (IFF_UP | IFF_RUNNING)) { 2207 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2208 } 2209 error = 0; 2210 } 2211 break; 2212 2213 default: 2214 error = ieee80211_ioctl(ic, cmd, data); 2215 break; 2216 } 2217 2218 if (error == ENETRESET) { 2219 error = 0; 2220 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2221 (IFF_UP | IFF_RUNNING)) { 2222 rtwn_stop(ifp, 0); 2223 error = rtwn_init(ifp); 2224 } 2225 } 2226 2227 splx(s); 2228 2229 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2230 error)); 2231 2232 return error; 2233 } 2234 2235 static int 2236 rtwn_power_on(struct rtwn_softc *sc) 2237 { 2238 uint32_t reg; 2239 int ntries; 2240 2241 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2242 2243 /* Wait for autoload done bit. */ 2244 for (ntries = 0; ntries < 1000; ntries++) { 2245 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2246 break; 2247 DELAY(5); 2248 } 2249 if (ntries == 1000) { 2250 aprint_error_dev(sc->sc_dev, 2251 "timeout waiting for chip autoload\n"); 2252 return ETIMEDOUT; 2253 } 2254 2255 /* Unlock ISO/CLK/Power control register. */ 2256 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2257 2258 /* TODO: check if we need this for 8188CE */ 2259 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2260 /* bt coex */ 2261 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2262 reg |= (R92C_APS_FSMCO_SOP_ABG | 2263 R92C_APS_FSMCO_SOP_AMB | 2264 R92C_APS_FSMCO_XOP_BTCK); 2265 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2266 } 2267 2268 /* Move SPS into PWM mode. */ 2269 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2270 DELAY(100); 2271 2272 /* Set low byte to 0x0f, leave others unchanged. */ 2273 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2274 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2275 2276 /* TODO: check if we need this for 8188CE */ 2277 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2278 /* bt coex */ 2279 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2280 reg &= ~0x00024800; /* XXX magic from linux */ 2281 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2282 } 2283 2284 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2285 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2286 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2287 DELAY(200); 2288 2289 /* TODO: linux does additional btcoex stuff here */ 2290 2291 /* Auto enable WLAN. */ 2292 rtwn_write_2(sc, R92C_APS_FSMCO, 2293 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2294 for (ntries = 0; ntries < 1000; ntries++) { 2295 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2296 R92C_APS_FSMCO_APFM_ONMAC)) 2297 break; 2298 DELAY(5); 2299 } 2300 if (ntries == 1000) { 2301 aprint_error_dev(sc->sc_dev, 2302 "timeout waiting for MAC auto ON\n"); 2303 return ETIMEDOUT; 2304 } 2305 2306 /* Enable radio, GPIO and LED functions. */ 2307 rtwn_write_2(sc, R92C_APS_FSMCO, 2308 R92C_APS_FSMCO_AFSM_PCIE | 2309 R92C_APS_FSMCO_PDN_EN | 2310 R92C_APS_FSMCO_PFM_ALDN); 2311 2312 /* Release RF digital isolation. */ 2313 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2314 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2315 2316 if (sc->chip & RTWN_CHIP_92C) 2317 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2318 else 2319 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2320 2321 rtwn_write_4(sc, R92C_INT_MIG, 0); 2322 2323 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2324 /* bt coex */ 2325 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2326 reg &= 0xfd; /* XXX magic from linux */ 2327 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2328 } 2329 2330 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2331 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2332 2333 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2334 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2335 aprint_error_dev(sc->sc_dev, 2336 "radio is disabled by hardware switch\n"); 2337 return EPERM; /* :-) */ 2338 } 2339 2340 /* Initialize MAC. */ 2341 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2342 rtwn_write_1(sc, R92C_APSD_CTRL, 2343 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2344 for (ntries = 0; ntries < 200; ntries++) { 2345 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2346 R92C_APSD_CTRL_OFF_STATUS)) 2347 break; 2348 DELAY(500); 2349 } 2350 if (ntries == 200) { 2351 aprint_error_dev(sc->sc_dev, 2352 "timeout waiting for MAC initialization\n"); 2353 return ETIMEDOUT; 2354 } 2355 2356 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2357 reg = rtwn_read_2(sc, R92C_CR); 2358 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2359 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2360 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2361 R92C_CR_ENSEC; 2362 rtwn_write_2(sc, R92C_CR, reg); 2363 2364 rtwn_write_1(sc, 0xfe10, 0x19); 2365 2366 return 0; 2367 } 2368 2369 static int 2370 rtwn_llt_init(struct rtwn_softc *sc) 2371 { 2372 int i, error; 2373 2374 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2375 2376 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2377 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2378 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2379 return error; 2380 } 2381 /* NB: 0xff indicates end-of-list. */ 2382 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2383 return error; 2384 /* 2385 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2386 * as ring buffer. 2387 */ 2388 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2389 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2390 return error; 2391 } 2392 /* Make the last page point to the beginning of the ring buffer. */ 2393 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2394 return error; 2395 } 2396 2397 static void 2398 rtwn_fw_reset(struct rtwn_softc *sc) 2399 { 2400 uint16_t reg; 2401 int ntries; 2402 2403 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2404 2405 /* Tell 8051 to reset itself. */ 2406 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2407 2408 /* Wait until 8051 resets by itself. */ 2409 for (ntries = 0; ntries < 100; ntries++) { 2410 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2411 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2412 goto sleep; 2413 DELAY(50); 2414 } 2415 /* Force 8051 reset. */ 2416 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2417 sleep: 2418 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2419 #if 0 2420 /* 2421 * We must sleep for one second to let the firmware settle. 2422 * Accessing registers too early will hang the whole system. 2423 */ 2424 tsleep(®, 0, "rtwnrst", hz); 2425 #else 2426 DELAY(1000 * 1000); 2427 #endif 2428 } 2429 2430 static int 2431 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2432 { 2433 uint32_t reg; 2434 int off, mlen, error = 0, i; 2435 2436 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2437 2438 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2439 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2440 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2441 2442 DELAY(5); 2443 2444 off = R92C_FW_START_ADDR; 2445 while (len > 0) { 2446 if (len > 196) 2447 mlen = 196; 2448 else if (len > 4) 2449 mlen = 4; 2450 else 2451 mlen = 1; 2452 for (i = 0; i < mlen; i++) 2453 rtwn_write_1(sc, off++, buf[i]); 2454 buf += mlen; 2455 len -= mlen; 2456 } 2457 2458 return error; 2459 } 2460 2461 static int 2462 rtwn_load_firmware(struct rtwn_softc *sc) 2463 { 2464 firmware_handle_t fwh; 2465 const struct r92c_fw_hdr *hdr; 2466 const char *name; 2467 u_char *fw, *ptr; 2468 size_t len; 2469 uint32_t reg; 2470 int mlen, ntries, page, error; 2471 2472 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2473 2474 /* Read firmware image from the filesystem. */ 2475 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2476 RTWN_CHIP_UMC_A_CUT) 2477 name = "rtl8192cfwU.bin"; 2478 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2479 name = "rtl8192cfwU_B.bin"; 2480 else 2481 name = "rtl8192cfw.bin"; 2482 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2483 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2484 aprint_error_dev(sc->sc_dev, 2485 "could not read firmware %s (error %d)\n", name, error); 2486 return error; 2487 } 2488 const size_t fwlen = len = firmware_get_size(fwh); 2489 fw = firmware_malloc(len); 2490 if (fw == NULL) { 2491 aprint_error_dev(sc->sc_dev, 2492 "failed to allocate firmware memory (size=%zu)\n", len); 2493 firmware_close(fwh); 2494 return ENOMEM; 2495 } 2496 error = firmware_read(fwh, 0, fw, len); 2497 firmware_close(fwh); 2498 if (error != 0) { 2499 aprint_error_dev(sc->sc_dev, 2500 "failed to read firmware (error %d)\n", error); 2501 firmware_free(fw, fwlen); 2502 return error; 2503 } 2504 2505 if (len < sizeof(*hdr)) { 2506 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2507 error = EINVAL; 2508 goto fail; 2509 } 2510 ptr = fw; 2511 hdr = (const struct r92c_fw_hdr *)ptr; 2512 /* Check if there is a valid FW header and skip it. */ 2513 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2514 (le16toh(hdr->signature) >> 4) == 0x92c) { 2515 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2516 le16toh(hdr->version), le16toh(hdr->subversion), 2517 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2518 ptr += sizeof(*hdr); 2519 len -= sizeof(*hdr); 2520 } 2521 2522 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2523 rtwn_fw_reset(sc); 2524 2525 /* Enable FW download. */ 2526 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2527 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2528 R92C_SYS_FUNC_EN_CPUEN); 2529 rtwn_write_1(sc, R92C_MCUFWDL, 2530 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2531 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2532 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2533 2534 /* Reset the FWDL checksum. */ 2535 rtwn_write_1(sc, R92C_MCUFWDL, 2536 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2537 2538 /* download firmware */ 2539 for (page = 0; len > 0; page++) { 2540 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2541 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2542 if (error != 0) { 2543 aprint_error_dev(sc->sc_dev, 2544 "could not load firmware page %d\n", page); 2545 goto fail; 2546 } 2547 ptr += mlen; 2548 len -= mlen; 2549 } 2550 2551 /* Disable FW download. */ 2552 rtwn_write_1(sc, R92C_MCUFWDL, 2553 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2554 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2555 2556 /* Wait for checksum report. */ 2557 for (ntries = 0; ntries < 1000; ntries++) { 2558 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2559 break; 2560 DELAY(5); 2561 } 2562 if (ntries == 1000) { 2563 aprint_error_dev(sc->sc_dev, 2564 "timeout waiting for checksum report\n"); 2565 error = ETIMEDOUT; 2566 goto fail; 2567 } 2568 2569 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2570 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2571 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2572 2573 /* Wait for firmware readiness. */ 2574 for (ntries = 0; ntries < 1000; ntries++) { 2575 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2576 break; 2577 DELAY(5); 2578 } 2579 if (ntries == 1000) { 2580 aprint_error_dev(sc->sc_dev, 2581 "timeout waiting for firmware readiness\n"); 2582 error = ETIMEDOUT; 2583 goto fail; 2584 } 2585 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2586 2587 fail: 2588 firmware_free(fw, fwlen); 2589 return error; 2590 } 2591 2592 static int 2593 rtwn_dma_init(struct rtwn_softc *sc) 2594 { 2595 uint32_t reg; 2596 int error; 2597 2598 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2599 2600 /* Initialize LLT table. */ 2601 error = rtwn_llt_init(sc); 2602 if (error != 0) 2603 return error; 2604 2605 /* Set number of pages for normal priority queue. */ 2606 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2607 rtwn_write_4(sc, R92C_RQPN, 2608 /* Set number of pages for public queue. */ 2609 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2610 /* Set number of pages for high priority queue. */ 2611 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2612 /* Set number of pages for low priority queue. */ 2613 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2614 /* Load values. */ 2615 R92C_RQPN_LD); 2616 2617 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2618 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2619 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2620 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2621 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2622 2623 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2624 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2625 reg |= 0xF771; 2626 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2627 2628 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2629 2630 /* Configure Tx DMA. */ 2631 rtwn_write_4(sc, R92C_BKQ_DESA, 2632 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2633 rtwn_write_4(sc, R92C_BEQ_DESA, 2634 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2635 rtwn_write_4(sc, R92C_VIQ_DESA, 2636 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2637 rtwn_write_4(sc, R92C_VOQ_DESA, 2638 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2639 rtwn_write_4(sc, R92C_BCNQ_DESA, 2640 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2641 rtwn_write_4(sc, R92C_MGQ_DESA, 2642 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2643 rtwn_write_4(sc, R92C_HQ_DESA, 2644 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2645 2646 /* Configure Rx DMA. */ 2647 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2648 2649 /* Set Tx/Rx transfer page boundary. */ 2650 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2651 2652 /* Set Tx/Rx transfer page size. */ 2653 rtwn_write_1(sc, R92C_PBP, 2654 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2655 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2656 return 0; 2657 } 2658 2659 static void 2660 rtwn_mac_init(struct rtwn_softc *sc) 2661 { 2662 int i; 2663 2664 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2665 2666 /* Write MAC initialization values. */ 2667 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2668 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2669 } 2670 2671 static void 2672 rtwn_bb_init(struct rtwn_softc *sc) 2673 { 2674 const struct rtwn_bb_prog *prog; 2675 uint32_t reg; 2676 int i; 2677 2678 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2679 2680 /* Enable BB and RF. */ 2681 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2682 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2683 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2684 R92C_SYS_FUNC_EN_DIO_RF); 2685 2686 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2687 2688 rtwn_write_1(sc, R92C_RF_CTRL, 2689 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2690 2691 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2692 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2693 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2694 R92C_SYS_FUNC_EN_BBRSTB); 2695 2696 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2697 2698 rtwn_write_4(sc, R92C_LEDCFG0, 2699 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2700 2701 /* Select BB programming. */ 2702 prog = (sc->chip & RTWN_CHIP_92C) ? 2703 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2704 2705 /* Write BB initialization values. */ 2706 for (i = 0; i < prog->count; i++) { 2707 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2708 DELAY(1); 2709 } 2710 2711 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2712 /* 8192C 1T only configuration. */ 2713 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2714 reg = (reg & ~0x00000003) | 0x2; 2715 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2716 2717 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2718 reg = (reg & ~0x00300033) | 0x00200022; 2719 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2720 2721 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2722 reg = (reg & ~0xff000000) | 0x45 << 24; 2723 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2724 2725 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2726 reg = (reg & ~0x000000ff) | 0x23; 2727 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2728 2729 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2730 reg = (reg & ~0x00000030) | 1 << 4; 2731 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2732 2733 reg = rtwn_bb_read(sc, 0xe74); 2734 reg = (reg & ~0x0c000000) | 2 << 26; 2735 rtwn_bb_write(sc, 0xe74, reg); 2736 reg = rtwn_bb_read(sc, 0xe78); 2737 reg = (reg & ~0x0c000000) | 2 << 26; 2738 rtwn_bb_write(sc, 0xe78, reg); 2739 reg = rtwn_bb_read(sc, 0xe7c); 2740 reg = (reg & ~0x0c000000) | 2 << 26; 2741 rtwn_bb_write(sc, 0xe7c, reg); 2742 reg = rtwn_bb_read(sc, 0xe80); 2743 reg = (reg & ~0x0c000000) | 2 << 26; 2744 rtwn_bb_write(sc, 0xe80, reg); 2745 reg = rtwn_bb_read(sc, 0xe88); 2746 reg = (reg & ~0x0c000000) | 2 << 26; 2747 rtwn_bb_write(sc, 0xe88, reg); 2748 } 2749 2750 /* Write AGC values. */ 2751 for (i = 0; i < prog->agccount; i++) { 2752 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2753 prog->agcvals[i]); 2754 DELAY(1); 2755 } 2756 2757 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2758 R92C_HSSI_PARAM2_CCK_HIPWR) 2759 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2760 } 2761 2762 static void 2763 rtwn_rf_init(struct rtwn_softc *sc) 2764 { 2765 const struct rtwn_rf_prog *prog; 2766 uint32_t reg, type; 2767 int i, j, idx, off; 2768 2769 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2770 2771 /* Select RF programming based on board type. */ 2772 if (!(sc->chip & RTWN_CHIP_92C)) { 2773 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2774 prog = rtl8188ce_rf_prog; 2775 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2776 prog = rtl8188ru_rf_prog; 2777 else 2778 prog = rtl8188cu_rf_prog; 2779 } else 2780 prog = rtl8192ce_rf_prog; 2781 2782 for (i = 0; i < sc->nrxchains; i++) { 2783 /* Save RF_ENV control type. */ 2784 idx = i / 2; 2785 off = (i % 2) * 16; 2786 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2787 type = (reg >> off) & 0x10; 2788 2789 /* Set RF_ENV enable. */ 2790 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2791 reg |= 0x100000; 2792 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2793 DELAY(1); 2794 /* Set RF_ENV output high. */ 2795 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2796 reg |= 0x10; 2797 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2798 DELAY(1); 2799 /* Set address and data lengths of RF registers. */ 2800 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2801 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2802 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2803 DELAY(1); 2804 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2805 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2806 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2807 DELAY(1); 2808 2809 /* Write RF initialization values for this chain. */ 2810 for (j = 0; j < prog[i].count; j++) { 2811 if (prog[i].regs[j] >= 0xf9 && 2812 prog[i].regs[j] <= 0xfe) { 2813 /* 2814 * These are fake RF registers offsets that 2815 * indicate a delay is required. 2816 */ 2817 DELAY(50); 2818 continue; 2819 } 2820 rtwn_rf_write(sc, i, prog[i].regs[j], 2821 prog[i].vals[j]); 2822 DELAY(1); 2823 } 2824 2825 /* Restore RF_ENV control type. */ 2826 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2827 reg &= ~(0x10 << off) | (type << off); 2828 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2829 2830 /* Cache RF register CHNLBW. */ 2831 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2832 } 2833 2834 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2835 RTWN_CHIP_UMC_A_CUT) { 2836 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2837 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2838 } 2839 } 2840 2841 static void 2842 rtwn_cam_init(struct rtwn_softc *sc) 2843 { 2844 2845 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2846 2847 /* Invalidate all CAM entries. */ 2848 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2849 } 2850 2851 static void 2852 rtwn_pa_bias_init(struct rtwn_softc *sc) 2853 { 2854 uint8_t reg; 2855 int i; 2856 2857 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2858 2859 for (i = 0; i < sc->nrxchains; i++) { 2860 if (sc->pa_setting & (1 << i)) 2861 continue; 2862 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2863 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2864 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2865 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2866 } 2867 if (!(sc->pa_setting & 0x10)) { 2868 reg = rtwn_read_1(sc, 0x16); 2869 reg = (reg & ~0xf0) | 0x90; 2870 rtwn_write_1(sc, 0x16, reg); 2871 } 2872 } 2873 2874 static void 2875 rtwn_rxfilter_init(struct rtwn_softc *sc) 2876 { 2877 2878 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2879 2880 /* Initialize Rx filter. */ 2881 /* TODO: use better filter for monitor mode. */ 2882 rtwn_write_4(sc, R92C_RCR, 2883 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2884 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2885 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2886 /* Accept all multicast frames. */ 2887 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2888 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2889 /* Accept all management frames. */ 2890 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2891 /* Reject all control frames. */ 2892 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2893 /* Accept all data frames. */ 2894 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2895 } 2896 2897 static void 2898 rtwn_edca_init(struct rtwn_softc *sc) 2899 { 2900 2901 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2902 2903 /* set spec SIFS (used in NAV) */ 2904 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2905 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2906 2907 /* set SIFS CCK/OFDM */ 2908 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2909 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2910 2911 /* TXOP */ 2912 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2913 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2914 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2915 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2916 } 2917 2918 static void 2919 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2920 uint16_t power[RTWN_RIDX_COUNT]) 2921 { 2922 uint32_t reg; 2923 2924 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2925 2926 /* Write per-CCK rate Tx power. */ 2927 if (chain == 0) { 2928 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2929 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2930 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2931 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2932 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2933 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2934 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2935 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2936 } else { 2937 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2938 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2939 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2940 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2941 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2942 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2943 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2944 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2945 } 2946 /* Write per-OFDM rate Tx power. */ 2947 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2948 SM(R92C_TXAGC_RATE06, power[ 4]) | 2949 SM(R92C_TXAGC_RATE09, power[ 5]) | 2950 SM(R92C_TXAGC_RATE12, power[ 6]) | 2951 SM(R92C_TXAGC_RATE18, power[ 7])); 2952 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2953 SM(R92C_TXAGC_RATE24, power[ 8]) | 2954 SM(R92C_TXAGC_RATE36, power[ 9]) | 2955 SM(R92C_TXAGC_RATE48, power[10]) | 2956 SM(R92C_TXAGC_RATE54, power[11])); 2957 /* Write per-MCS Tx power. */ 2958 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2959 SM(R92C_TXAGC_MCS00, power[12]) | 2960 SM(R92C_TXAGC_MCS01, power[13]) | 2961 SM(R92C_TXAGC_MCS02, power[14]) | 2962 SM(R92C_TXAGC_MCS03, power[15])); 2963 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2964 SM(R92C_TXAGC_MCS04, power[16]) | 2965 SM(R92C_TXAGC_MCS05, power[17]) | 2966 SM(R92C_TXAGC_MCS06, power[18]) | 2967 SM(R92C_TXAGC_MCS07, power[19])); 2968 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2969 SM(R92C_TXAGC_MCS08, power[20]) | 2970 SM(R92C_TXAGC_MCS09, power[21]) | 2971 SM(R92C_TXAGC_MCS10, power[22]) | 2972 SM(R92C_TXAGC_MCS11, power[23])); 2973 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2974 SM(R92C_TXAGC_MCS12, power[24]) | 2975 SM(R92C_TXAGC_MCS13, power[25]) | 2976 SM(R92C_TXAGC_MCS14, power[26]) | 2977 SM(R92C_TXAGC_MCS15, power[27])); 2978 } 2979 2980 static void 2981 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2982 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2983 uint16_t power[RTWN_RIDX_COUNT]) 2984 { 2985 struct ieee80211com *ic = &sc->sc_ic; 2986 struct r92c_rom *rom = &sc->rom; 2987 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2988 const struct rtwn_txpwr *base; 2989 int ridx, chan, group; 2990 2991 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2992 2993 /* Determine channel group. */ 2994 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2995 if (chan <= 3) 2996 group = 0; 2997 else if (chan <= 9) 2998 group = 1; 2999 else 3000 group = 2; 3001 3002 /* Get original Tx power based on board type and RF chain. */ 3003 if (!(sc->chip & RTWN_CHIP_92C)) { 3004 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3005 base = &rtl8188ru_txagc[chain]; 3006 else 3007 base = &rtl8192cu_txagc[chain]; 3008 } else 3009 base = &rtl8192cu_txagc[chain]; 3010 3011 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 3012 if (sc->regulatory == 0) { 3013 for (ridx = 0; ridx <= 3; ridx++) 3014 power[ridx] = base->pwr[0][ridx]; 3015 } 3016 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3017 if (sc->regulatory == 3) { 3018 power[ridx] = base->pwr[0][ridx]; 3019 /* Apply vendor limits. */ 3020 if (extc != NULL) 3021 maxpwr = rom->ht40_max_pwr[group]; 3022 else 3023 maxpwr = rom->ht20_max_pwr[group]; 3024 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 3025 if (power[ridx] > maxpwr) 3026 power[ridx] = maxpwr; 3027 } else if (sc->regulatory == 1) { 3028 if (extc == NULL) 3029 power[ridx] = base->pwr[group][ridx]; 3030 } else if (sc->regulatory != 2) 3031 power[ridx] = base->pwr[0][ridx]; 3032 } 3033 3034 /* Compute per-CCK rate Tx power. */ 3035 cckpow = rom->cck_tx_pwr[chain][group]; 3036 for (ridx = 0; ridx <= 3; ridx++) { 3037 power[ridx] += cckpow; 3038 if (power[ridx] > R92C_MAX_TX_PWR) 3039 power[ridx] = R92C_MAX_TX_PWR; 3040 } 3041 3042 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3043 if (sc->ntxchains > 1) { 3044 /* Apply reduction for 2 spatial streams. */ 3045 diff = rom->ht40_2s_tx_pwr_diff[group]; 3046 diff = (diff >> (chain * 4)) & 0xf; 3047 htpow = (htpow > diff) ? htpow - diff : 0; 3048 } 3049 3050 /* Compute per-OFDM rate Tx power. */ 3051 diff = rom->ofdm_tx_pwr_diff[group]; 3052 diff = (diff >> (chain * 4)) & 0xf; 3053 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3054 for (ridx = 4; ridx <= 11; ridx++) { 3055 power[ridx] += ofdmpow; 3056 if (power[ridx] > R92C_MAX_TX_PWR) 3057 power[ridx] = R92C_MAX_TX_PWR; 3058 } 3059 3060 /* Compute per-MCS Tx power. */ 3061 if (extc == NULL) { 3062 diff = rom->ht20_tx_pwr_diff[group]; 3063 diff = (diff >> (chain * 4)) & 0xf; 3064 htpow += diff; /* HT40->HT20 correction. */ 3065 } 3066 for (ridx = 12; ridx <= 27; ridx++) { 3067 power[ridx] += htpow; 3068 if (power[ridx] > R92C_MAX_TX_PWR) 3069 power[ridx] = R92C_MAX_TX_PWR; 3070 } 3071 #ifdef RTWN_DEBUG 3072 if (rtwn_debug >= 4) { 3073 /* Dump per-rate Tx power values. */ 3074 printf("Tx power for chain %d:\n", chain); 3075 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3076 printf("Rate %d = %u\n", ridx, power[ridx]); 3077 } 3078 #endif 3079 } 3080 3081 static void 3082 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3083 struct ieee80211_channel *extc) 3084 { 3085 uint16_t power[RTWN_RIDX_COUNT]; 3086 int i; 3087 3088 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3089 3090 for (i = 0; i < sc->ntxchains; i++) { 3091 /* Compute per-rate Tx power values. */ 3092 rtwn_get_txpower(sc, i, c, extc, power); 3093 /* Write per-rate Tx power values to hardware. */ 3094 rtwn_write_txpower(sc, i, power); 3095 } 3096 } 3097 3098 static void 3099 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3100 struct ieee80211_channel *extc) 3101 { 3102 struct ieee80211com *ic = &sc->sc_ic; 3103 u_int chan; 3104 int i; 3105 3106 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3107 3108 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3109 3110 /* Set Tx power for this new channel. */ 3111 rtwn_set_txpower(sc, c, extc); 3112 3113 for (i = 0; i < sc->nrxchains; i++) { 3114 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3115 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3116 } 3117 #ifndef IEEE80211_NO_HT 3118 if (extc != NULL) { 3119 uint32_t reg; 3120 3121 /* Is secondary channel below or above primary? */ 3122 int prichlo = c->ic_freq < extc->ic_freq; 3123 3124 rtwn_write_1(sc, R92C_BWOPMODE, 3125 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3126 3127 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3128 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3129 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3130 3131 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3132 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3133 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3134 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3135 3136 /* Set CCK side band. */ 3137 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3138 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3139 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3140 3141 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3142 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3143 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3144 3145 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3146 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3147 ~R92C_FPGA0_ANAPARAM2_CBW20); 3148 3149 reg = rtwn_bb_read(sc, 0x818); 3150 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3151 rtwn_bb_write(sc, 0x818, reg); 3152 3153 /* Select 40MHz bandwidth. */ 3154 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3155 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3156 } else 3157 #endif 3158 { 3159 rtwn_write_1(sc, R92C_BWOPMODE, 3160 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3161 3162 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3163 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3164 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3165 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3166 3167 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3168 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3169 R92C_FPGA0_ANAPARAM2_CBW20); 3170 3171 /* Select 20MHz bandwidth. */ 3172 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3173 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3174 } 3175 } 3176 3177 static void 3178 rtwn_iq_calib(struct rtwn_softc *sc) 3179 { 3180 3181 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3182 3183 /* XXX */ 3184 } 3185 3186 static void 3187 rtwn_lc_calib(struct rtwn_softc *sc) 3188 { 3189 uint32_t rf_ac[2]; 3190 uint8_t txmode; 3191 int i; 3192 3193 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3194 3195 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3196 if ((txmode & 0x70) != 0) { 3197 /* Disable all continuous Tx. */ 3198 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3199 3200 /* Set RF mode to standby mode. */ 3201 for (i = 0; i < sc->nrxchains; i++) { 3202 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3203 rtwn_rf_write(sc, i, R92C_RF_AC, 3204 RW(rf_ac[i], R92C_RF_AC_MODE, 3205 R92C_RF_AC_MODE_STANDBY)); 3206 } 3207 } else { 3208 /* Block all Tx queues. */ 3209 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3210 } 3211 /* Start calibration. */ 3212 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3213 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3214 3215 /* Give calibration the time to complete. */ 3216 DELAY(100); 3217 3218 /* Restore configuration. */ 3219 if ((txmode & 0x70) != 0) { 3220 /* Restore Tx mode. */ 3221 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3222 /* Restore RF mode. */ 3223 for (i = 0; i < sc->nrxchains; i++) 3224 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3225 } else { 3226 /* Unblock all Tx queues. */ 3227 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3228 } 3229 } 3230 3231 static void 3232 rtwn_temp_calib(struct rtwn_softc *sc) 3233 { 3234 int temp; 3235 3236 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3237 3238 if (sc->thcal_state == 0) { 3239 /* Start measuring temperature. */ 3240 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3241 sc->thcal_state = 1; 3242 return; 3243 } 3244 sc->thcal_state = 0; 3245 3246 /* Read measured temperature. */ 3247 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3248 if (temp == 0) /* Read failed, skip. */ 3249 return; 3250 DPRINTFN(2, ("temperature=%d\n", temp)); 3251 3252 /* 3253 * Redo IQ and LC calibration if temperature changed significantly 3254 * since last calibration. 3255 */ 3256 if (sc->thcal_lctemp == 0) { 3257 /* First calibration is performed in rtwn_init(). */ 3258 sc->thcal_lctemp = temp; 3259 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3260 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3261 sc->thcal_lctemp, temp)); 3262 rtwn_iq_calib(sc); 3263 rtwn_lc_calib(sc); 3264 /* Record temperature of last calibration. */ 3265 sc->thcal_lctemp = temp; 3266 } 3267 } 3268 3269 static int 3270 rtwn_init(struct ifnet *ifp) 3271 { 3272 struct rtwn_softc *sc = ifp->if_softc; 3273 struct ieee80211com *ic = &sc->sc_ic; 3274 uint32_t reg; 3275 int i, error; 3276 3277 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3278 3279 /* Init firmware commands ring. */ 3280 sc->fwcur = 0; 3281 3282 /* Power on adapter. */ 3283 error = rtwn_power_on(sc); 3284 if (error != 0) { 3285 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3286 goto fail; 3287 } 3288 3289 /* Initialize DMA. */ 3290 error = rtwn_dma_init(sc); 3291 if (error != 0) { 3292 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3293 goto fail; 3294 } 3295 3296 /* Set info size in Rx descriptors (in 64-bit words). */ 3297 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3298 3299 /* Disable interrupts. */ 3300 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3301 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3302 3303 /* Set MAC address. */ 3304 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3305 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3306 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3307 3308 /* Set initial network type. */ 3309 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3310 3311 rtwn_rxfilter_init(sc); 3312 3313 reg = rtwn_read_4(sc, R92C_RRSR); 3314 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3315 rtwn_write_4(sc, R92C_RRSR, reg); 3316 3317 /* Set short/long retry limits. */ 3318 rtwn_write_2(sc, R92C_RL, 3319 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3320 3321 /* Initialize EDCA parameters. */ 3322 rtwn_edca_init(sc); 3323 3324 /* Set data and response automatic rate fallback retry counts. */ 3325 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3326 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3327 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3328 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3329 3330 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3331 3332 /* Set ACK timeout. */ 3333 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3334 3335 /* Initialize beacon parameters. */ 3336 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3337 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3338 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3339 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3340 3341 /* Setup AMPDU aggregation. */ 3342 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3343 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3344 3345 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3346 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3347 3348 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3349 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3350 3351 /* Load 8051 microcode. */ 3352 error = rtwn_load_firmware(sc); 3353 if (error != 0) 3354 goto fail; 3355 3356 /* Initialize MAC/BB/RF blocks. */ 3357 rtwn_mac_init(sc); 3358 rtwn_bb_init(sc); 3359 rtwn_rf_init(sc); 3360 3361 /* Turn CCK and OFDM blocks on. */ 3362 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3363 reg |= R92C_RFMOD_CCK_EN; 3364 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3365 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3366 reg |= R92C_RFMOD_OFDM_EN; 3367 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3368 3369 /* Clear per-station keys table. */ 3370 rtwn_cam_init(sc); 3371 3372 /* Enable hardware sequence numbering. */ 3373 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3374 3375 /* Perform LO and IQ calibrations. */ 3376 rtwn_iq_calib(sc); 3377 /* Perform LC calibration. */ 3378 rtwn_lc_calib(sc); 3379 3380 rtwn_pa_bias_init(sc); 3381 3382 /* Initialize GPIO setting. */ 3383 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3384 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3385 3386 /* Fix for lower temperature. */ 3387 rtwn_write_1(sc, 0x15, 0xe9); 3388 3389 /* Set default channel. */ 3390 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3391 3392 /* Clear pending interrupts. */ 3393 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3394 3395 /* Enable interrupts. */ 3396 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3397 3398 /* We're ready to go. */ 3399 ifp->if_flags &= ~IFF_OACTIVE; 3400 ifp->if_flags |= IFF_RUNNING; 3401 3402 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3403 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3404 else 3405 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3406 3407 return 0; 3408 3409 fail: 3410 rtwn_stop(ifp, 1); 3411 return error; 3412 } 3413 3414 static void 3415 rtwn_init_task(void *arg) 3416 { 3417 struct rtwn_softc *sc = arg; 3418 struct ifnet *ifp = GET_IFP(sc); 3419 int s; 3420 3421 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3422 3423 s = splnet(); 3424 3425 rtwn_stop(ifp, 0); 3426 3427 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3428 rtwn_init(ifp); 3429 3430 splx(s); 3431 } 3432 3433 static void 3434 rtwn_stop(struct ifnet *ifp, int disable) 3435 { 3436 struct rtwn_softc *sc = ifp->if_softc; 3437 struct ieee80211com *ic = &sc->sc_ic; 3438 uint16_t reg; 3439 int s, i; 3440 3441 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3442 3443 sc->sc_tx_timer = 0; 3444 ifp->if_timer = 0; 3445 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3446 3447 callout_stop(&sc->scan_to); 3448 callout_stop(&sc->calib_to); 3449 3450 s = splnet(); 3451 3452 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3453 3454 /* Disable interrupts. */ 3455 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3456 3457 /* Pause MAC TX queue */ 3458 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3459 3460 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3461 3462 /* Reset BB state machine */ 3463 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3464 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3465 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3466 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3467 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3468 3469 reg = rtwn_read_2(sc, R92C_CR); 3470 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3471 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3472 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3473 R92C_CR_ENSEC); 3474 rtwn_write_2(sc, R92C_CR, reg); 3475 3476 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3477 rtwn_fw_reset(sc); 3478 3479 /* Reset MAC and Enable 8051 */ 3480 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3481 3482 /* TODO: linux does additional btcoex stuff here */ 3483 3484 /* Disable AFE PLL */ 3485 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3486 /* Enter PFM mode */ 3487 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3488 /* Gated AFE DIG_CLOCK */ 3489 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3490 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3491 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3492 3493 for (i = 0; i < RTWN_NTXQUEUES; i++) 3494 rtwn_reset_tx_list(sc, i); 3495 rtwn_reset_rx_list(sc); 3496 3497 splx(s); 3498 } 3499 3500 static int 3501 rtwn_intr(void *xsc) 3502 { 3503 struct rtwn_softc *sc = xsc; 3504 uint32_t status; 3505 3506 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3507 return 0; 3508 3509 status = rtwn_read_4(sc, R92C_HISR); 3510 if (status == 0 || status == 0xffffffff) 3511 return 0; 3512 3513 /* Disable interrupts. */ 3514 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3515 3516 softint_schedule(sc->sc_soft_ih); 3517 return 1; 3518 } 3519 3520 static void 3521 rtwn_softintr(void *xsc) 3522 { 3523 struct rtwn_softc *sc = xsc; 3524 uint32_t status; 3525 int i, s; 3526 3527 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3528 return; 3529 3530 status = rtwn_read_4(sc, R92C_HISR); 3531 if (status == 0 || status == 0xffffffff) 3532 goto out; 3533 3534 /* Ack interrupts. */ 3535 rtwn_write_4(sc, R92C_HISR, status); 3536 3537 /* Vendor driver treats RX errors like ROK... */ 3538 if (status & RTWN_INT_ENABLE_RX) { 3539 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3540 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3541 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3542 3543 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3544 continue; 3545 3546 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3547 } 3548 } 3549 3550 if (status & R92C_IMR_BDOK) 3551 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3552 if (status & R92C_IMR_HIGHDOK) 3553 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3554 if (status & R92C_IMR_MGNTDOK) 3555 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3556 if (status & R92C_IMR_BKDOK) 3557 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3558 if (status & R92C_IMR_BEDOK) 3559 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3560 if (status & R92C_IMR_VIDOK) 3561 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3562 if (status & R92C_IMR_VODOK) 3563 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3564 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3565 struct ifnet *ifp = GET_IFP(sc); 3566 s = splnet(); 3567 ifp->if_flags &= ~IFF_OACTIVE; 3568 rtwn_start(ifp); 3569 splx(s); 3570 } 3571 3572 out: 3573 /* Enable interrupts. */ 3574 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3575 } 3576
Indexes created Thu Oct 02 01:09:59 GMT 2025