if_rtwn.c revision 1.16
1 /* $NetBSD: if_rtwn.c,v 1.16 2018/06/26 06:48:01 msaitoh Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.16 2018/06/26 06:48:01 msaitoh Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 static void rtwn_softintr(void *); 178 179 /* Aliases. */ 180 #define rtwn_bb_write rtwn_write_4 181 #define rtwn_bb_read rtwn_read_4 182 183 static const struct rtwn_device * 184 rtwn_lookup(const struct pci_attach_args *pa) 185 { 186 const struct rtwn_device *rd; 187 int i; 188 189 for (i = 0; i < __arraycount(rtwn_devices); i++) { 190 rd = &rtwn_devices[i]; 191 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 192 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 193 return rd; 194 } 195 return NULL; 196 } 197 198 static int 199 rtwn_match(device_t parent, cfdata_t match, void *aux) 200 { 201 struct pci_attach_args *pa = aux; 202 203 if (rtwn_lookup(pa) != NULL) 204 return 1; 205 return 0; 206 } 207 208 static void 209 rtwn_attach(device_t parent, device_t self, void *aux) 210 { 211 struct rtwn_softc *sc = device_private(self); 212 struct pci_attach_args *pa = aux; 213 struct ieee80211com *ic = &sc->sc_ic; 214 struct ifnet *ifp = GET_IFP(sc); 215 int i, error; 216 pcireg_t memtype; 217 const char *intrstr; 218 char intrbuf[PCI_INTRSTR_LEN]; 219 220 sc->sc_dev = self; 221 sc->sc_dmat = pa->pa_dmat; 222 sc->sc_pc = pa->pa_pc; 223 sc->sc_tag = pa->pa_tag; 224 225 pci_aprint_devinfo(pa, NULL); 226 227 callout_init(&sc->scan_to, 0); 228 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 229 callout_init(&sc->calib_to, 0); 230 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 231 232 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc); 233 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 234 235 /* Power up the device */ 236 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 237 238 /* Map control/status registers. */ 239 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 240 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 241 &sc->sc_sh, NULL, &sc->sc_mapsize); 242 if (error != 0) { 243 aprint_error_dev(self, "can't map mem space\n"); 244 return; 245 } 246 247 /* Install interrupt handler. */ 248 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 249 aprint_error_dev(self, "can't map interrupt\n"); 250 return; 251 } 252 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 253 sizeof(intrbuf)); 254 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 255 rtwn_intr, sc); 256 if (sc->sc_ih == NULL) { 257 aprint_error_dev(self, "can't establish interrupt"); 258 if (intrstr != NULL) 259 aprint_error(" at %s", intrstr); 260 aprint_error("\n"); 261 return; 262 } 263 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 264 265 error = rtwn_read_chipid(sc); 266 if (error != 0) { 267 aprint_error_dev(self, "unsupported test or unknown chip\n"); 268 return; 269 } 270 271 /* Disable PCIe Active State Power Management (ASPM). */ 272 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 273 &sc->sc_cap_off, NULL)) { 274 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 275 sc->sc_cap_off + PCIE_LCSR); 276 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 277 pci_conf_write(sc->sc_pc, sc->sc_tag, 278 sc->sc_cap_off + PCIE_LCSR, lcsr); 279 } 280 281 /* Allocate Tx/Rx buffers. */ 282 error = rtwn_alloc_rx_list(sc); 283 if (error != 0) { 284 aprint_error_dev(self, "could not allocate Rx buffers\n"); 285 return; 286 } 287 for (i = 0; i < RTWN_NTXQUEUES; i++) { 288 error = rtwn_alloc_tx_list(sc, i); 289 if (error != 0) { 290 aprint_error_dev(self, 291 "could not allocate Tx buffers\n"); 292 return; 293 } 294 } 295 296 /* Determine number of Tx/Rx chains. */ 297 if (sc->chip & RTWN_CHIP_92C) { 298 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 299 sc->nrxchains = 2; 300 } else { 301 sc->ntxchains = 1; 302 sc->nrxchains = 1; 303 } 304 rtwn_read_rom(sc); 305 306 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 307 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 308 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 309 310 /* 311 * Setup the 802.11 device. 312 */ 313 ic->ic_ifp = ifp; 314 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 315 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 316 ic->ic_state = IEEE80211_S_INIT; 317 318 /* Set device capabilities. */ 319 ic->ic_caps = 320 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 321 IEEE80211_C_IBSS | /* IBSS mode supported */ 322 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 323 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 324 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 325 IEEE80211_C_WME | /* 802.11e */ 326 IEEE80211_C_WPA; /* WPA/RSN. */ 327 328 #ifndef IEEE80211_NO_HT 329 /* Set HT capabilities. */ 330 ic->ic_htcaps = 331 IEEE80211_HTCAP_CBW20_40 | 332 IEEE80211_HTCAP_DSSSCCK40; 333 /* Set supported HT rates. */ 334 for (i = 0; i < sc->nrxchains; i++) 335 ic->ic_sup_mcs[i] = 0xff; 336 #endif 337 338 /* Set supported .11b and .11g rates. */ 339 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 340 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 341 342 /* Set supported .11b and .11g channels (1 through 14). */ 343 for (i = 1; i <= 14; i++) { 344 ic->ic_channels[i].ic_freq = 345 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 346 ic->ic_channels[i].ic_flags = 347 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 348 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 349 } 350 351 ifp->if_softc = sc; 352 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 353 ifp->if_init = rtwn_init; 354 ifp->if_ioctl = rtwn_ioctl; 355 ifp->if_start = rtwn_start; 356 ifp->if_watchdog = rtwn_watchdog; 357 IFQ_SET_READY(&ifp->if_snd); 358 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 359 360 error = if_initialize(ifp); 361 if (error != 0) { 362 ifp->if_softc = NULL; /* For rtwn_detach() */ 363 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 364 error); 365 goto fail; 366 } 367 ieee80211_ifattach(ic); 368 /* Use common softint-based if_input */ 369 ifp->if_percpuq = if_percpuq_create(ifp); 370 if_register(ifp); 371 372 /* override default methods */ 373 ic->ic_newassoc = rtwn_newassoc; 374 ic->ic_reset = rtwn_reset; 375 ic->ic_wme.wme_update = rtwn_wme_update; 376 377 /* Override state transition machine. */ 378 sc->sc_newstate = ic->ic_newstate; 379 ic->ic_newstate = rtwn_newstate; 380 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 381 382 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 383 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 384 &sc->sc_drvbpf); 385 386 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 387 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 388 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 389 390 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 391 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 392 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 393 394 ieee80211_announce(ic); 395 396 if (!pmf_device_register(self, NULL, NULL)) 397 aprint_error_dev(self, "couldn't establish power handler\n"); 398 399 return; 400 401 fail: 402 rtwn_detach(self, 0); 403 } 404 405 static int 406 rtwn_detach(device_t self, int flags) 407 { 408 struct rtwn_softc *sc = device_private(self); 409 struct ieee80211com *ic = &sc->sc_ic; 410 struct ifnet *ifp = GET_IFP(sc); 411 int s, i; 412 413 callout_stop(&sc->scan_to); 414 callout_stop(&sc->calib_to); 415 416 s = splnet(); 417 418 if (ifp->if_softc != NULL) { 419 rtwn_stop(ifp, 0); 420 421 pmf_device_deregister(self); 422 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 423 bpf_detach(ifp); 424 ieee80211_ifdetach(ic); 425 if_detach(ifp); 426 } 427 428 /* Free Tx/Rx buffers. */ 429 for (i = 0; i < RTWN_NTXQUEUES; i++) 430 rtwn_free_tx_list(sc, i); 431 rtwn_free_rx_list(sc); 432 433 splx(s); 434 435 callout_destroy(&sc->scan_to); 436 callout_destroy(&sc->calib_to); 437 438 if (sc->init_task != NULL) 439 softint_disestablish(sc->init_task); 440 if (sc->sc_soft_ih != NULL) 441 softint_disestablish(sc->sc_soft_ih); 442 443 if (sc->sc_ih != NULL) { 444 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 445 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 446 } 447 448 return 0; 449 } 450 451 static int 452 rtwn_activate(device_t self, enum devact act) 453 { 454 struct rtwn_softc *sc = device_private(self); 455 struct ifnet *ifp = GET_IFP(sc); 456 457 switch (act) { 458 case DVACT_DEACTIVATE: 459 if (ifp->if_flags & IFF_RUNNING) 460 rtwn_stop(ifp, 0); 461 return 0; 462 default: 463 return EOPNOTSUPP; 464 } 465 } 466 467 static void 468 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 469 bus_addr_t addr, size_t len, int idx) 470 { 471 472 memset(desc, 0, sizeof(*desc)); 473 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 474 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 475 desc->rxbufaddr = htole32(addr); 476 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 477 BUS_SPACE_BARRIER_WRITE); 478 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 479 } 480 481 static int 482 rtwn_alloc_rx_list(struct rtwn_softc *sc) 483 { 484 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 485 struct rtwn_rx_data *rx_data; 486 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 487 int i, error = 0; 488 489 /* Allocate Rx descriptors. */ 490 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 491 &rx_ring->map); 492 if (error != 0) { 493 aprint_error_dev(sc->sc_dev, 494 "could not create rx desc DMA map\n"); 495 rx_ring->map = NULL; 496 goto fail; 497 } 498 499 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 500 &rx_ring->nsegs, BUS_DMA_NOWAIT); 501 if (error != 0) { 502 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 503 goto fail; 504 } 505 506 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 507 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 508 if (error != 0) { 509 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 510 rx_ring->desc = NULL; 511 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 512 goto fail; 513 } 514 memset(rx_ring->desc, 0, size); 515 516 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 517 1, size, BUS_DMA_NOWAIT); 518 if (error != 0) { 519 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 520 goto fail; 521 } 522 523 /* Allocate Rx buffers. */ 524 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 525 rx_data = &rx_ring->rx_data[i]; 526 527 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 528 0, BUS_DMA_NOWAIT, &rx_data->map); 529 if (error != 0) { 530 aprint_error_dev(sc->sc_dev, 531 "could not create rx buf DMA map\n"); 532 goto fail; 533 } 534 535 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 536 if (__predict_false(rx_data->m == NULL)) { 537 aprint_error_dev(sc->sc_dev, 538 "couldn't allocate rx mbuf\n"); 539 error = ENOMEM; 540 goto fail; 541 } 542 MCLGET(rx_data->m, M_DONTWAIT); 543 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 544 aprint_error_dev(sc->sc_dev, 545 "couldn't allocate rx mbuf cluster\n"); 546 m_free(rx_data->m); 547 rx_data->m = NULL; 548 error = ENOMEM; 549 goto fail; 550 } 551 552 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 553 mtod(rx_data->m, void *), MCLBYTES, NULL, 554 BUS_DMA_NOWAIT | BUS_DMA_READ); 555 if (error != 0) { 556 aprint_error_dev(sc->sc_dev, 557 "could not load rx buf DMA map\n"); 558 goto fail; 559 } 560 561 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 562 BUS_DMASYNC_PREREAD); 563 564 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 565 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 566 } 567 fail: if (error != 0) 568 rtwn_free_rx_list(sc); 569 return error; 570 } 571 572 static void 573 rtwn_reset_rx_list(struct rtwn_softc *sc) 574 { 575 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 576 struct rtwn_rx_data *rx_data; 577 int i; 578 579 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 580 rx_data = &rx_ring->rx_data[i]; 581 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 582 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 583 } 584 } 585 586 static void 587 rtwn_free_rx_list(struct rtwn_softc *sc) 588 { 589 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 590 struct rtwn_rx_data *rx_data; 591 int i, s; 592 593 s = splnet(); 594 595 if (rx_ring->map) { 596 if (rx_ring->desc) { 597 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 598 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 599 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 600 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 601 rx_ring->nsegs); 602 rx_ring->desc = NULL; 603 } 604 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 605 rx_ring->map = NULL; 606 } 607 608 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 609 rx_data = &rx_ring->rx_data[i]; 610 611 if (rx_data->m != NULL) { 612 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 613 m_freem(rx_data->m); 614 rx_data->m = NULL; 615 } 616 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 617 rx_data->map = NULL; 618 } 619 620 splx(s); 621 } 622 623 static int 624 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 625 { 626 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 627 struct rtwn_tx_data *tx_data; 628 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 629 int i = 0, error = 0; 630 631 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 632 &tx_ring->map); 633 if (error != 0) { 634 aprint_error_dev(sc->sc_dev, 635 "could not create tx ring DMA map\n"); 636 goto fail; 637 } 638 639 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 640 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 641 if (error != 0) { 642 aprint_error_dev(sc->sc_dev, 643 "could not allocate tx ring DMA memory\n"); 644 goto fail; 645 } 646 647 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 648 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 649 if (error != 0) { 650 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 651 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 652 goto fail; 653 } 654 memset(tx_ring->desc, 0, size); 655 656 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 657 size, NULL, BUS_DMA_NOWAIT); 658 if (error != 0) { 659 aprint_error_dev(sc->sc_dev, 660 "could not load tx ring DMA map\n"); 661 goto fail; 662 } 663 664 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 665 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 666 667 /* setup tx desc */ 668 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 669 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 670 671 tx_data = &tx_ring->tx_data[i]; 672 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 673 0, BUS_DMA_NOWAIT, &tx_data->map); 674 if (error != 0) { 675 aprint_error_dev(sc->sc_dev, 676 "could not create tx buf DMA map\n"); 677 goto fail; 678 } 679 tx_data->m = NULL; 680 tx_data->ni = NULL; 681 } 682 683 fail: 684 if (error != 0) 685 rtwn_free_tx_list(sc, qid); 686 return error; 687 } 688 689 static void 690 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 691 { 692 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 693 int i; 694 695 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 696 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 697 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 698 699 memset(desc, 0, sizeof(*desc) - 700 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 701 sizeof(desc->nextdescaddr))); 702 703 if (tx_data->m != NULL) { 704 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 705 m_freem(tx_data->m); 706 tx_data->m = NULL; 707 ieee80211_free_node(tx_data->ni); 708 tx_data->ni = NULL; 709 } 710 } 711 712 sc->qfullmsk &= ~(1 << qid); 713 tx_ring->queued = 0; 714 tx_ring->cur = 0; 715 } 716 717 static void 718 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 719 { 720 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 721 struct rtwn_tx_data *tx_data; 722 int i; 723 724 if (tx_ring->map != NULL) { 725 if (tx_ring->desc != NULL) { 726 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 727 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 728 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 729 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 730 tx_ring->nsegs); 731 } 732 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 733 } 734 735 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 736 tx_data = &tx_ring->tx_data[i]; 737 738 if (tx_data->m != NULL) { 739 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 740 m_freem(tx_data->m); 741 tx_data->m = NULL; 742 } 743 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 744 } 745 746 sc->qfullmsk &= ~(1 << qid); 747 tx_ring->queued = 0; 748 tx_ring->cur = 0; 749 } 750 751 static void 752 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 753 { 754 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 755 } 756 757 static void 758 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 759 { 760 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 761 } 762 763 static void 764 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 765 { 766 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 767 } 768 769 static uint8_t 770 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 771 { 772 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 773 } 774 775 static uint16_t 776 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 777 { 778 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 779 } 780 781 static uint32_t 782 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 783 { 784 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 785 } 786 787 static int 788 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 789 { 790 struct r92c_fw_cmd cmd; 791 uint8_t *cp; 792 int fwcur; 793 int ntries; 794 795 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 796 device_xname(sc->sc_dev), __func__, id, buf, len)); 797 798 fwcur = sc->fwcur; 799 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 800 801 /* Wait for current FW box to be empty. */ 802 for (ntries = 0; ntries < 100; ntries++) { 803 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 804 break; 805 DELAY(1); 806 } 807 if (ntries == 100) { 808 aprint_error_dev(sc->sc_dev, 809 "could not send firmware command %d\n", id); 810 return ETIMEDOUT; 811 } 812 813 memset(&cmd, 0, sizeof(cmd)); 814 KASSERT(len <= sizeof(cmd.msg)); 815 memcpy(cmd.msg, buf, len); 816 817 /* Write the first word last since that will trigger the FW. */ 818 cp = (uint8_t *)&cmd; 819 if (len >= 4) { 820 cmd.id = id | R92C_CMD_FLAG_EXT; 821 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 822 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 823 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 824 } else { 825 cmd.id = id; 826 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 827 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 828 } 829 830 /* Give firmware some time for processing. */ 831 DELAY(2000); 832 833 return 0; 834 } 835 836 static void 837 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 838 { 839 840 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 841 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 842 } 843 844 static uint32_t 845 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 846 { 847 uint32_t reg[R92C_MAX_CHAINS], val; 848 849 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 850 if (chain != 0) 851 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 852 853 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 854 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 855 DELAY(1000); 856 857 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 858 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 859 R92C_HSSI_PARAM2_READ_EDGE); 860 DELAY(1000); 861 862 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 863 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 864 DELAY(1000); 865 866 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 867 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 868 else 869 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 870 return MS(val, R92C_LSSI_READBACK_DATA); 871 } 872 873 static int 874 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 875 { 876 int ntries; 877 878 rtwn_write_4(sc, R92C_LLT_INIT, 879 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 880 SM(R92C_LLT_INIT_ADDR, addr) | 881 SM(R92C_LLT_INIT_DATA, data)); 882 /* Wait for write operation to complete. */ 883 for (ntries = 0; ntries < 20; ntries++) { 884 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 885 R92C_LLT_INIT_OP_NO_ACTIVE) 886 return 0; 887 DELAY(5); 888 } 889 return ETIMEDOUT; 890 } 891 892 static uint8_t 893 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 894 { 895 uint32_t reg; 896 int ntries; 897 898 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 899 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 900 reg &= ~R92C_EFUSE_CTRL_VALID; 901 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 902 /* Wait for read operation to complete. */ 903 for (ntries = 0; ntries < 100; ntries++) { 904 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 905 if (reg & R92C_EFUSE_CTRL_VALID) 906 return MS(reg, R92C_EFUSE_CTRL_DATA); 907 DELAY(5); 908 } 909 aprint_error_dev(sc->sc_dev, 910 "could not read efuse byte at address 0x%x\n", addr); 911 return 0xff; 912 } 913 914 static void 915 rtwn_efuse_read(struct rtwn_softc *sc) 916 { 917 uint8_t *rom = (uint8_t *)&sc->rom; 918 uint32_t reg; 919 uint16_t addr = 0; 920 uint8_t off, msk; 921 int i; 922 923 rtwn_efuse_switch_power(sc); 924 925 memset(&sc->rom, 0xff, sizeof(sc->rom)); 926 while (addr < 512) { 927 reg = rtwn_efuse_read_1(sc, addr); 928 if (reg == 0xff) 929 break; 930 addr++; 931 off = reg >> 4; 932 msk = reg & 0xf; 933 for (i = 0; i < 4; i++) { 934 if (msk & (1 << i)) 935 continue; 936 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 937 addr++; 938 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 939 addr++; 940 } 941 } 942 #ifdef RTWN_DEBUG 943 if (rtwn_debug >= 2) { 944 /* Dump ROM content. */ 945 printf("\n"); 946 for (i = 0; i < sizeof(sc->rom); i++) 947 printf("%02x:", rom[i]); 948 printf("\n"); 949 } 950 #endif 951 } 952 953 static void 954 rtwn_efuse_switch_power(struct rtwn_softc *sc) 955 { 956 uint32_t reg; 957 958 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 959 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 960 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 961 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 962 } 963 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 964 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 965 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 966 reg | R92C_SYS_FUNC_EN_ELDR); 967 } 968 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 969 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 970 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 971 rtwn_write_2(sc, R92C_SYS_CLKR, 972 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 973 } 974 } 975 976 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 977 static int 978 rtwn_read_chipid(struct rtwn_softc *sc) 979 { 980 uint32_t reg; 981 982 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 983 984 reg = rtwn_read_4(sc, R92C_SYS_CFG); 985 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 986 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 987 /* Unsupported test chip. */ 988 return EIO; 989 990 if (reg & R92C_SYS_CFG_TYPE_92C) { 991 sc->chip |= RTWN_CHIP_92C; 992 /* Check if it is a castrated 8192C. */ 993 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 994 R92C_HPON_FSM_CHIP_BONDING_ID) == 995 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 996 sc->chip |= RTWN_CHIP_92C_1T2R; 997 } 998 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 999 sc->chip |= RTWN_CHIP_UMC; 1000 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1001 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1002 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 1003 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 1004 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 1005 else 1006 /* Unsupported unknown chip. */ 1007 return EIO; 1008 } 1009 return 0; 1010 } 1011 1012 static void 1013 rtwn_read_rom(struct rtwn_softc *sc) 1014 { 1015 struct ieee80211com *ic = &sc->sc_ic; 1016 struct r92c_rom *rom = &sc->rom; 1017 1018 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1019 1020 /* Read full ROM image. */ 1021 rtwn_efuse_read(sc); 1022 1023 if (rom->id != 0x8129) { 1024 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1025 rom->id); 1026 } 1027 1028 /* XXX Weird but this is what the vendor driver does. */ 1029 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1030 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1031 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1032 1033 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1034 sc->pa_setting, sc->board_type, sc->regulatory)); 1035 1036 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1037 } 1038 1039 static int 1040 rtwn_media_change(struct ifnet *ifp) 1041 { 1042 int error; 1043 1044 error = ieee80211_media_change(ifp); 1045 if (error != ENETRESET) 1046 return error; 1047 1048 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1049 (IFF_UP | IFF_RUNNING)) { 1050 rtwn_stop(ifp, 0); 1051 error = rtwn_init(ifp); 1052 } 1053 return error; 1054 } 1055 1056 /* 1057 * Initialize rate adaptation in firmware. 1058 */ 1059 static int 1060 rtwn_ra_init(struct rtwn_softc *sc) 1061 { 1062 static const uint8_t map[] = { 1063 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1064 }; 1065 struct ieee80211com *ic = &sc->sc_ic; 1066 struct ieee80211_node *ni = ic->ic_bss; 1067 struct ieee80211_rateset *rs = &ni->ni_rates; 1068 struct r92c_fw_cmd_macid_cfg cmd; 1069 uint32_t rates, basicrates; 1070 uint8_t mode; 1071 int maxrate, maxbasicrate, error, i, j; 1072 1073 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1074 1075 /* Get normal and basic rates mask. */ 1076 rates = basicrates = 0; 1077 maxrate = maxbasicrate = 0; 1078 for (i = 0; i < rs->rs_nrates; i++) { 1079 /* Convert 802.11 rate to HW rate index. */ 1080 for (j = 0; j < __arraycount(map); j++) 1081 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1082 break; 1083 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1084 continue; 1085 rates |= 1 << j; 1086 if (j > maxrate) 1087 maxrate = j; 1088 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1089 basicrates |= 1 << j; 1090 if (j > maxbasicrate) 1091 maxbasicrate = j; 1092 } 1093 } 1094 if (ic->ic_curmode == IEEE80211_MODE_11B) 1095 mode = R92C_RAID_11B; 1096 else 1097 mode = R92C_RAID_11BG; 1098 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1099 device_xname(sc->sc_dev), mode, rates, basicrates)); 1100 if (basicrates == 0) 1101 basicrates |= 1; /* add 1Mbps */ 1102 1103 /* Set rates mask for group addressed frames. */ 1104 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1105 cmd.mask = htole32((mode << 28) | basicrates); 1106 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1107 if (error != 0) { 1108 aprint_error_dev(sc->sc_dev, 1109 "could not add broadcast station\n"); 1110 return error; 1111 } 1112 /* Set initial MRR rate. */ 1113 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1114 maxbasicrate)); 1115 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1116 1117 /* Set rates mask for unicast frames. */ 1118 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1119 cmd.mask = htole32((mode << 28) | rates); 1120 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1121 if (error != 0) { 1122 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1123 return error; 1124 } 1125 /* Set initial MRR rate. */ 1126 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1127 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1128 1129 /* Configure Automatic Rate Fallback Register. */ 1130 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1131 if (rates & 0x0c) 1132 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1133 else 1134 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1135 } else 1136 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1137 1138 /* Indicate highest supported rate. */ 1139 ni->ni_txrate = rs->rs_nrates - 1; 1140 return 0; 1141 } 1142 1143 static int 1144 rtwn_get_nettype(struct rtwn_softc *sc) 1145 { 1146 struct ieee80211com *ic = &sc->sc_ic; 1147 int type; 1148 1149 switch (ic->ic_opmode) { 1150 case IEEE80211_M_STA: 1151 type = R92C_CR_NETTYPE_INFRA; 1152 break; 1153 1154 case IEEE80211_M_HOSTAP: 1155 type = R92C_CR_NETTYPE_AP; 1156 break; 1157 1158 case IEEE80211_M_IBSS: 1159 type = R92C_CR_NETTYPE_ADHOC; 1160 break; 1161 1162 default: 1163 type = R92C_CR_NETTYPE_NOLINK; 1164 break; 1165 } 1166 1167 return type; 1168 } 1169 1170 static void 1171 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1172 { 1173 uint32_t reg; 1174 1175 reg = rtwn_read_4(sc, R92C_CR); 1176 reg = RW(reg, R92C_CR_NETTYPE, type); 1177 rtwn_write_4(sc, R92C_CR, reg); 1178 } 1179 1180 static void 1181 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1182 { 1183 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1184 uint64_t tsf; 1185 1186 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1187 1188 /* Enable TSF synchronization. */ 1189 rtwn_write_1(sc, R92C_BCN_CTRL, 1190 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1191 1192 rtwn_write_1(sc, R92C_BCN_CTRL, 1193 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1194 1195 /* Set initial TSF. */ 1196 tsf = ni->ni_tstamp.tsf; 1197 tsf = le64toh(tsf); 1198 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1199 tsf -= IEEE80211_DUR_TU; 1200 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1201 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1202 1203 rtwn_write_1(sc, R92C_BCN_CTRL, 1204 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1205 } 1206 1207 static void 1208 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1209 { 1210 uint8_t reg; 1211 1212 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1213 1214 if (led == RTWN_LED_LINK) { 1215 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1216 if (!on) 1217 reg |= R92C_LEDCFG2_DIS; 1218 else 1219 reg |= R92C_LEDCFG2_EN; 1220 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1221 sc->ledlink = on; /* Save LED state. */ 1222 } 1223 } 1224 1225 static void 1226 rtwn_calib_to(void *arg) 1227 { 1228 struct rtwn_softc *sc = arg; 1229 struct r92c_fw_cmd_rssi cmd; 1230 int s; 1231 1232 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1233 1234 s = splnet(); 1235 1236 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1237 goto restart_timer; 1238 1239 if (sc->avg_pwdb != -1) { 1240 /* Indicate Rx signal strength to FW for rate adaptation. */ 1241 memset(&cmd, 0, sizeof(cmd)); 1242 cmd.macid = 0; /* BSS. */ 1243 cmd.pwdb = sc->avg_pwdb; 1244 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1245 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1246 } 1247 1248 /* Do temperature compensation. */ 1249 rtwn_temp_calib(sc); 1250 1251 restart_timer: 1252 callout_schedule(&sc->calib_to, mstohz(2000)); 1253 1254 splx(s); 1255 } 1256 1257 static void 1258 rtwn_next_scan(void *arg) 1259 { 1260 struct rtwn_softc *sc = arg; 1261 struct ieee80211com *ic = &sc->sc_ic; 1262 int s; 1263 1264 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1265 1266 s = splnet(); 1267 if (ic->ic_state == IEEE80211_S_SCAN) 1268 ieee80211_next_scan(ic); 1269 splx(s); 1270 } 1271 1272 static void 1273 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1274 { 1275 1276 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1277 1278 /* start with lowest Tx rate */ 1279 ni->ni_txrate = 0; 1280 } 1281 1282 static int 1283 rtwn_reset(struct ifnet *ifp) 1284 { 1285 struct rtwn_softc *sc = ifp->if_softc; 1286 struct ieee80211com *ic = &sc->sc_ic; 1287 1288 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1289 return ENETRESET; 1290 1291 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1292 1293 return 0; 1294 } 1295 1296 static int 1297 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1298 { 1299 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1300 struct ieee80211_node *ni; 1301 enum ieee80211_state ostate = ic->ic_state; 1302 uint32_t reg; 1303 int s; 1304 1305 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1306 1307 s = splnet(); 1308 1309 callout_stop(&sc->scan_to); 1310 callout_stop(&sc->calib_to); 1311 1312 if (ostate != nstate) { 1313 DPRINTF(("%s: %s -> %s\n", __func__, 1314 ieee80211_state_name[ostate], 1315 ieee80211_state_name[nstate])); 1316 } 1317 1318 switch (ostate) { 1319 case IEEE80211_S_INIT: 1320 break; 1321 1322 case IEEE80211_S_SCAN: 1323 if (nstate != IEEE80211_S_SCAN) { 1324 /* 1325 * End of scanning 1326 */ 1327 /* flush 4-AC Queue after site_survey */ 1328 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1329 1330 /* Allow Rx from our BSSID only. */ 1331 rtwn_write_4(sc, R92C_RCR, 1332 rtwn_read_4(sc, R92C_RCR) | 1333 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1334 } 1335 break; 1336 1337 case IEEE80211_S_AUTH: 1338 case IEEE80211_S_ASSOC: 1339 break; 1340 1341 case IEEE80211_S_RUN: 1342 /* Turn link LED off. */ 1343 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1344 1345 /* Set media status to 'No Link'. */ 1346 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1347 1348 /* Stop Rx of data frames. */ 1349 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1350 1351 /* Rest TSF. */ 1352 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1353 1354 /* Disable TSF synchronization. */ 1355 rtwn_write_1(sc, R92C_BCN_CTRL, 1356 rtwn_read_1(sc, R92C_BCN_CTRL) | 1357 R92C_BCN_CTRL_DIS_TSF_UDT0); 1358 1359 /* Back to 20MHz mode */ 1360 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1361 1362 /* Reset EDCA parameters. */ 1363 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1364 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1365 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1366 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1367 1368 /* flush all cam entries */ 1369 rtwn_cam_init(sc); 1370 break; 1371 } 1372 1373 switch (nstate) { 1374 case IEEE80211_S_INIT: 1375 /* Turn link LED off. */ 1376 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1377 break; 1378 1379 case IEEE80211_S_SCAN: 1380 if (ostate != IEEE80211_S_SCAN) { 1381 /* 1382 * Begin of scanning 1383 */ 1384 1385 /* Set gain for scanning. */ 1386 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1387 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1388 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1389 1390 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1391 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1392 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1393 1394 /* Allow Rx from any BSSID. */ 1395 rtwn_write_4(sc, R92C_RCR, 1396 rtwn_read_4(sc, R92C_RCR) & 1397 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1398 1399 /* Stop Rx of data frames. */ 1400 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1401 1402 /* Disable update TSF */ 1403 rtwn_write_1(sc, R92C_BCN_CTRL, 1404 rtwn_read_1(sc, R92C_BCN_CTRL) | 1405 R92C_BCN_CTRL_DIS_TSF_UDT0); 1406 } 1407 1408 /* Make link LED blink during scan. */ 1409 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1410 1411 /* Pause AC Tx queues. */ 1412 rtwn_write_1(sc, R92C_TXPAUSE, 1413 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1414 1415 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1416 1417 /* Start periodic scan. */ 1418 callout_schedule(&sc->scan_to, mstohz(200)); 1419 break; 1420 1421 case IEEE80211_S_AUTH: 1422 /* Set initial gain under link. */ 1423 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1424 #ifdef doaslinux 1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1426 #else 1427 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1428 #endif 1429 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1430 1431 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1432 #ifdef doaslinux 1433 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1434 #else 1435 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1436 #endif 1437 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1438 1439 /* Set media status to 'No Link'. */ 1440 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1441 1442 /* Allow Rx from any BSSID. */ 1443 rtwn_write_4(sc, R92C_RCR, 1444 rtwn_read_4(sc, R92C_RCR) & 1445 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1446 1447 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1448 break; 1449 1450 case IEEE80211_S_ASSOC: 1451 break; 1452 1453 case IEEE80211_S_RUN: 1454 ni = ic->ic_bss; 1455 1456 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1457 1458 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1459 /* Back to 20Mhz mode */ 1460 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1461 1462 /* Set media status to 'No Link'. */ 1463 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1464 1465 /* Enable Rx of data frames. */ 1466 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1467 1468 /* Allow Rx from any BSSID. */ 1469 rtwn_write_4(sc, R92C_RCR, 1470 rtwn_read_4(sc, R92C_RCR) & 1471 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1472 1473 /* Accept Rx data/control/management frames */ 1474 rtwn_write_4(sc, R92C_RCR, 1475 rtwn_read_4(sc, R92C_RCR) | 1476 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1477 1478 /* Turn link LED on. */ 1479 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1480 break; 1481 } 1482 1483 /* Set media status to 'Associated'. */ 1484 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1485 1486 /* Set BSSID. */ 1487 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1488 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1489 1490 if (ic->ic_curmode == IEEE80211_MODE_11B) 1491 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1492 else /* 802.11b/g */ 1493 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1494 1495 /* Enable Rx of data frames. */ 1496 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1497 1498 /* Flush all AC queues. */ 1499 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1500 1501 /* Set beacon interval. */ 1502 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1503 1504 switch (ic->ic_opmode) { 1505 case IEEE80211_M_STA: 1506 /* Allow Rx from our BSSID only. */ 1507 rtwn_write_4(sc, R92C_RCR, 1508 rtwn_read_4(sc, R92C_RCR) | 1509 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1510 1511 /* Enable TSF synchronization. */ 1512 rtwn_tsf_sync_enable(sc); 1513 break; 1514 1515 case IEEE80211_M_HOSTAP: 1516 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1517 1518 /* Allow Rx from any BSSID. */ 1519 rtwn_write_4(sc, R92C_RCR, 1520 rtwn_read_4(sc, R92C_RCR) & 1521 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1522 1523 /* Reset TSF timer to zero. */ 1524 reg = rtwn_read_4(sc, R92C_TCR); 1525 reg &= ~0x01; 1526 rtwn_write_4(sc, R92C_TCR, reg); 1527 reg |= 0x01; 1528 rtwn_write_4(sc, R92C_TCR, reg); 1529 break; 1530 1531 case IEEE80211_M_MONITOR: 1532 default: 1533 break; 1534 } 1535 1536 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1537 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1538 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1539 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1540 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1541 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1542 1543 /* Initialize rate adaptation. */ 1544 rtwn_ra_init(sc); 1545 1546 /* Turn link LED on. */ 1547 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1548 1549 /* Reset average RSSI. */ 1550 sc->avg_pwdb = -1; 1551 1552 /* Reset temperature calibration state machine. */ 1553 sc->thcal_state = 0; 1554 sc->thcal_lctemp = 0; 1555 1556 /* Start periodic calibration. */ 1557 callout_schedule(&sc->calib_to, mstohz(2000)); 1558 break; 1559 } 1560 1561 (void)sc->sc_newstate(ic, nstate, arg); 1562 1563 splx(s); 1564 1565 return 0; 1566 } 1567 1568 static int 1569 rtwn_wme_update(struct ieee80211com *ic) 1570 { 1571 static const uint16_t aci2reg[WME_NUM_AC] = { 1572 R92C_EDCA_BE_PARAM, 1573 R92C_EDCA_BK_PARAM, 1574 R92C_EDCA_VI_PARAM, 1575 R92C_EDCA_VO_PARAM 1576 }; 1577 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1578 const struct wmeParams *wmep; 1579 int s, aci, aifs, slottime; 1580 1581 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1582 1583 s = splnet(); 1584 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1585 for (aci = 0; aci < WME_NUM_AC; aci++) { 1586 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1587 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1588 aifs = wmep->wmep_aifsn * slottime + 10; 1589 rtwn_write_4(sc, aci2reg[aci], 1590 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1591 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1592 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1593 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1594 } 1595 splx(s); 1596 1597 return 0; 1598 } 1599 1600 static void 1601 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1602 { 1603 int pwdb; 1604 1605 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1606 1607 /* Convert antenna signal to percentage. */ 1608 if (rssi <= -100 || rssi >= 20) 1609 pwdb = 0; 1610 else if (rssi >= 0) 1611 pwdb = 100; 1612 else 1613 pwdb = 100 + rssi; 1614 if (rate <= 3) { 1615 /* CCK gain is smaller than OFDM/MCS gain. */ 1616 pwdb += 6; 1617 if (pwdb > 100) 1618 pwdb = 100; 1619 if (pwdb <= 14) 1620 pwdb -= 4; 1621 else if (pwdb <= 26) 1622 pwdb -= 8; 1623 else if (pwdb <= 34) 1624 pwdb -= 6; 1625 else if (pwdb <= 42) 1626 pwdb -= 2; 1627 } 1628 if (sc->avg_pwdb == -1) /* Init. */ 1629 sc->avg_pwdb = pwdb; 1630 else if (sc->avg_pwdb < pwdb) 1631 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1632 else 1633 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1634 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1635 } 1636 1637 static int8_t 1638 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1639 { 1640 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1641 struct r92c_rx_phystat *phy; 1642 struct r92c_rx_cck *cck; 1643 uint8_t rpt; 1644 int8_t rssi; 1645 1646 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1647 1648 if (rate <= 3) { 1649 cck = (struct r92c_rx_cck *)physt; 1650 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1651 rpt = (cck->agc_rpt >> 5) & 0x3; 1652 rssi = (cck->agc_rpt & 0x1f) << 1; 1653 } else { 1654 rpt = (cck->agc_rpt >> 6) & 0x3; 1655 rssi = cck->agc_rpt & 0x3e; 1656 } 1657 rssi = cckoff[rpt] - rssi; 1658 } else { /* OFDM/HT. */ 1659 phy = (struct r92c_rx_phystat *)physt; 1660 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1661 } 1662 return rssi; 1663 } 1664 1665 static void 1666 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1667 struct rtwn_rx_data *rx_data, int desc_idx) 1668 { 1669 struct ieee80211com *ic = &sc->sc_ic; 1670 struct ifnet *ifp = IC2IFP(ic); 1671 struct ieee80211_frame *wh; 1672 struct ieee80211_node *ni; 1673 struct r92c_rx_phystat *phy = NULL; 1674 uint32_t rxdw0, rxdw3; 1675 struct mbuf *m, *m1; 1676 uint8_t rate; 1677 int8_t rssi = 0; 1678 int infosz, pktlen, shift, totlen, error, s; 1679 1680 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1681 1682 rxdw0 = le32toh(rx_desc->rxdw0); 1683 rxdw3 = le32toh(rx_desc->rxdw3); 1684 1685 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1686 /* 1687 * This should not happen since we setup our Rx filter 1688 * to not receive these frames. 1689 */ 1690 ifp->if_ierrors++; 1691 return; 1692 } 1693 1694 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1695 /* 1696 * XXX: This will drop most control packets. Do we really 1697 * want this in IEEE80211_M_MONITOR mode? 1698 */ 1699 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1700 ic->ic_stats.is_rx_tooshort++; 1701 ifp->if_ierrors++; 1702 return; 1703 } 1704 if (__predict_false(pktlen > MCLBYTES)) { 1705 ifp->if_ierrors++; 1706 return; 1707 } 1708 1709 rate = MS(rxdw3, R92C_RXDW3_RATE); 1710 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1711 if (infosz > sizeof(struct r92c_rx_phystat)) 1712 infosz = sizeof(struct r92c_rx_phystat); 1713 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1714 totlen = pktlen + infosz + shift; 1715 1716 /* Get RSSI from PHY status descriptor if present. */ 1717 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1718 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1719 rssi = rtwn_get_rssi(sc, rate, phy); 1720 /* Update our average RSSI. */ 1721 rtwn_update_avgrssi(sc, rate, rssi); 1722 } 1723 1724 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1725 pktlen, rate, infosz, shift, rssi)); 1726 1727 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1728 if (__predict_false(m1 == NULL)) { 1729 ic->ic_stats.is_rx_nobuf++; 1730 ifp->if_ierrors++; 1731 return; 1732 } 1733 MCLGET(m1, M_DONTWAIT); 1734 if (__predict_false(!(m1->m_flags & M_EXT))) { 1735 m_freem(m1); 1736 ic->ic_stats.is_rx_nobuf++; 1737 ifp->if_ierrors++; 1738 return; 1739 } 1740 1741 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1742 BUS_DMASYNC_POSTREAD); 1743 1744 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1745 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1746 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1747 if (error != 0) { 1748 m_freem(m1); 1749 1750 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1751 rx_data->m, BUS_DMA_NOWAIT)) 1752 panic("%s: could not load old RX mbuf", 1753 device_xname(sc->sc_dev)); 1754 1755 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1756 BUS_DMASYNC_PREREAD); 1757 1758 /* Physical address may have changed. */ 1759 rtwn_setup_rx_desc(sc, rx_desc, 1760 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1761 1762 ifp->if_ierrors++; 1763 return; 1764 } 1765 1766 /* Finalize mbuf. */ 1767 m = rx_data->m; 1768 rx_data->m = m1; 1769 m->m_pkthdr.len = m->m_len = totlen; 1770 m_set_rcvif(m, ifp); 1771 1772 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1773 BUS_DMASYNC_PREREAD); 1774 1775 /* Update RX descriptor. */ 1776 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1777 MCLBYTES, desc_idx); 1778 1779 /* Get ieee80211 frame header. */ 1780 if (rxdw0 & R92C_RXDW0_PHYST) 1781 m_adj(m, infosz + shift); 1782 else 1783 m_adj(m, shift); 1784 wh = mtod(m, struct ieee80211_frame *); 1785 1786 s = splnet(); 1787 1788 if (__predict_false(sc->sc_drvbpf != NULL)) { 1789 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1790 1791 tap->wr_flags = 0; 1792 /* Map HW rate index to 802.11 rate. */ 1793 tap->wr_flags = 2; 1794 if (!(rxdw3 & R92C_RXDW3_HT)) { 1795 switch (rate) { 1796 /* CCK. */ 1797 case 0: tap->wr_rate = 2; break; 1798 case 1: tap->wr_rate = 4; break; 1799 case 2: tap->wr_rate = 11; break; 1800 case 3: tap->wr_rate = 22; break; 1801 /* OFDM. */ 1802 case 4: tap->wr_rate = 12; break; 1803 case 5: tap->wr_rate = 18; break; 1804 case 6: tap->wr_rate = 24; break; 1805 case 7: tap->wr_rate = 36; break; 1806 case 8: tap->wr_rate = 48; break; 1807 case 9: tap->wr_rate = 72; break; 1808 case 10: tap->wr_rate = 96; break; 1809 case 11: tap->wr_rate = 108; break; 1810 } 1811 } else if (rate >= 12) { /* MCS0~15. */ 1812 /* Bit 7 set means HT MCS instead of rate. */ 1813 tap->wr_rate = 0x80 | (rate - 12); 1814 } 1815 tap->wr_dbm_antsignal = rssi; 1816 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1817 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1818 1819 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1820 } 1821 1822 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1823 1824 /* push the frame up to the 802.11 stack */ 1825 ieee80211_input(ic, m, ni, rssi, 0); 1826 1827 /* Node is no longer needed. */ 1828 ieee80211_free_node(ni); 1829 1830 splx(s); 1831 } 1832 1833 static int 1834 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1835 { 1836 struct ieee80211com *ic = &sc->sc_ic; 1837 struct ieee80211_frame *wh; 1838 struct ieee80211_key *k = NULL; 1839 struct rtwn_tx_ring *tx_ring; 1840 struct rtwn_tx_data *data; 1841 struct r92c_tx_desc *txd; 1842 uint16_t qos, seq; 1843 uint8_t raid, type, tid, qid; 1844 int hasqos, error; 1845 1846 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1847 1848 wh = mtod(m, struct ieee80211_frame *); 1849 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1850 1851 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1852 k = ieee80211_crypto_encap(ic, ni, m); 1853 if (k == NULL) 1854 return ENOBUFS; 1855 1856 wh = mtod(m, struct ieee80211_frame *); 1857 } 1858 1859 if ((hasqos = ieee80211_has_qos(wh))) { 1860 /* data frames in 11n mode */ 1861 qos = ieee80211_get_qos(wh); 1862 tid = qos & IEEE80211_QOS_TID; 1863 qid = TID_TO_WME_AC(tid); 1864 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1865 /* Use AC_VO for management frames. */ 1866 tid = 0; /* compiler happy */ 1867 qid = RTWN_VO_QUEUE; 1868 } else { 1869 /* non-qos data frames */ 1870 tid = R92C_TXDW1_QSEL_BE; 1871 qid = RTWN_BE_QUEUE; 1872 } 1873 1874 /* Grab a Tx buffer from the ring. */ 1875 tx_ring = &sc->tx_ring[qid]; 1876 data = &tx_ring->tx_data[tx_ring->cur]; 1877 if (data->m != NULL) { 1878 m_freem(m); 1879 return ENOBUFS; 1880 } 1881 1882 /* Fill Tx descriptor. */ 1883 txd = &tx_ring->desc[tx_ring->cur]; 1884 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1885 m_freem(m); 1886 return ENOBUFS; 1887 } 1888 1889 txd->txdw0 = htole32( 1890 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1891 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1892 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1893 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1894 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1895 1896 txd->txdw1 = 0; 1897 txd->txdw4 = 0; 1898 txd->txdw5 = 0; 1899 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1900 type == IEEE80211_FC0_TYPE_DATA) { 1901 if (ic->ic_curmode == IEEE80211_MODE_11B) 1902 raid = R92C_RAID_11B; 1903 else 1904 raid = R92C_RAID_11BG; 1905 1906 txd->txdw1 |= htole32( 1907 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1908 SM(R92C_TXDW1_QSEL, tid) | 1909 SM(R92C_TXDW1_RAID, raid) | 1910 R92C_TXDW1_AGGBK); 1911 1912 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1913 /* for 11g */ 1914 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1915 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1916 R92C_TXDW4_HWRTSEN); 1917 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1918 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1919 R92C_TXDW4_HWRTSEN); 1920 } 1921 } 1922 /* Send RTS at OFDM24. */ 1923 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1924 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1925 /* Send data at OFDM54. */ 1926 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1927 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1928 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1929 txd->txdw1 |= htole32( 1930 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1931 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1932 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1933 1934 /* Force CCK1. */ 1935 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1936 /* Use 1Mbps */ 1937 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1938 } else { 1939 txd->txdw1 |= htole32( 1940 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1941 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1942 1943 /* Force CCK1. */ 1944 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1945 /* Use 1Mbps */ 1946 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1947 } 1948 1949 /* Set sequence number (already little endian). */ 1950 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1951 txd->txdseq = htole16(seq); 1952 1953 if (!hasqos) { 1954 /* Use HW sequence numbering for non-QoS frames. */ 1955 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1956 txd->txdseq |= htole16(0x8000); /* WTF? */ 1957 } else 1958 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1959 1960 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1961 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1962 if (error && error != EFBIG) { 1963 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1964 error); 1965 m_freem(m); 1966 return error; 1967 } 1968 if (error != 0) { 1969 /* Too many DMA segments, linearize mbuf. */ 1970 struct mbuf *newm = m_defrag(m, M_DONTWAIT); 1971 if (newm == NULL) { 1972 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1973 m_freem(m); 1974 return ENOBUFS; 1975 } 1976 m = newm; 1977 1978 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1979 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1980 if (error != 0) { 1981 aprint_error_dev(sc->sc_dev, 1982 "can't map mbuf (error %d)\n", error); 1983 m_freem(m); 1984 return error; 1985 } 1986 } 1987 1988 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1989 txd->txbufsize = htole16(m->m_pkthdr.len); 1990 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1991 BUS_SPACE_BARRIER_WRITE); 1992 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1993 1994 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1995 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1996 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1997 BUS_DMASYNC_PREWRITE); 1998 1999 data->m = m; 2000 data->ni = ni; 2001 2002 if (__predict_false(sc->sc_drvbpf != NULL)) { 2003 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2004 2005 tap->wt_flags = 0; 2006 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2007 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2008 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2009 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2010 2011 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2012 } 2013 2014 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2015 tx_ring->queued++; 2016 2017 if (tx_ring->queued > RTWN_TX_LIST_HIMARK) 2018 sc->qfullmsk |= (1 << qid); 2019 2020 /* Kick TX. */ 2021 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2022 2023 return 0; 2024 } 2025 2026 static void 2027 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2028 { 2029 struct ieee80211com *ic = &sc->sc_ic; 2030 struct ifnet *ifp = IC2IFP(ic); 2031 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2032 struct rtwn_tx_data *tx_data; 2033 struct r92c_tx_desc *tx_desc; 2034 int i, s; 2035 2036 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2037 qid)); 2038 2039 s = splnet(); 2040 2041 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2042 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2043 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2044 2045 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2046 tx_data = &tx_ring->tx_data[i]; 2047 if (tx_data->m == NULL) 2048 continue; 2049 2050 tx_desc = &tx_ring->desc[i]; 2051 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2052 continue; 2053 2054 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2055 m_freem(tx_data->m); 2056 tx_data->m = NULL; 2057 ieee80211_free_node(tx_data->ni); 2058 tx_data->ni = NULL; 2059 2060 ifp->if_opackets++; 2061 sc->sc_tx_timer = 0; 2062 tx_ring->queued--; 2063 } 2064 2065 if (tx_ring->queued < RTWN_TX_LIST_LOMARK) 2066 sc->qfullmsk &= ~(1 << qid); 2067 2068 splx(s); 2069 } 2070 2071 static void 2072 rtwn_start(struct ifnet *ifp) 2073 { 2074 struct rtwn_softc *sc = ifp->if_softc; 2075 struct ieee80211com *ic = &sc->sc_ic; 2076 struct ether_header *eh; 2077 struct ieee80211_node *ni; 2078 struct mbuf *m; 2079 2080 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2081 return; 2082 2083 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2084 2085 for (;;) { 2086 if (sc->qfullmsk != 0) { 2087 ifp->if_flags |= IFF_OACTIVE; 2088 break; 2089 } 2090 /* Send pending management frames first. */ 2091 IF_DEQUEUE(&ic->ic_mgtq, m); 2092 if (m != NULL) { 2093 ni = M_GETCTX(m, struct ieee80211_node *); 2094 M_CLEARCTX(m); 2095 goto sendit; 2096 } 2097 if (ic->ic_state != IEEE80211_S_RUN) 2098 break; 2099 2100 /* Encapsulate and send data frames. */ 2101 IFQ_DEQUEUE(&ifp->if_snd, m); 2102 if (m == NULL) 2103 break; 2104 2105 if (m->m_len < (int)sizeof(*eh) && 2106 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2107 ifp->if_oerrors++; 2108 continue; 2109 } 2110 eh = mtod(m, struct ether_header *); 2111 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2112 if (ni == NULL) { 2113 m_freem(m); 2114 ifp->if_oerrors++; 2115 continue; 2116 } 2117 2118 bpf_mtap(ifp, m, BPF_D_OUT); 2119 2120 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2121 ieee80211_free_node(ni); 2122 ifp->if_oerrors++; 2123 continue; 2124 } 2125 sendit: 2126 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2127 2128 if (rtwn_tx(sc, m, ni) != 0) { 2129 ieee80211_free_node(ni); 2130 ifp->if_oerrors++; 2131 continue; 2132 } 2133 2134 sc->sc_tx_timer = 5; 2135 ifp->if_timer = 1; 2136 } 2137 2138 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2139 } 2140 2141 static void 2142 rtwn_watchdog(struct ifnet *ifp) 2143 { 2144 struct rtwn_softc *sc = ifp->if_softc; 2145 struct ieee80211com *ic = &sc->sc_ic; 2146 2147 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2148 2149 ifp->if_timer = 0; 2150 2151 if (sc->sc_tx_timer > 0) { 2152 if (--sc->sc_tx_timer == 0) { 2153 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2154 softint_schedule(sc->init_task); 2155 ifp->if_oerrors++; 2156 return; 2157 } 2158 ifp->if_timer = 1; 2159 } 2160 ieee80211_watchdog(ic); 2161 } 2162 2163 static int 2164 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2165 { 2166 struct rtwn_softc *sc = ifp->if_softc; 2167 struct ieee80211com *ic = &sc->sc_ic; 2168 int s, error = 0; 2169 2170 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2171 __func__, cmd, data)); 2172 2173 s = splnet(); 2174 2175 switch (cmd) { 2176 case SIOCSIFFLAGS: 2177 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2178 break; 2179 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2180 case IFF_UP | IFF_RUNNING: 2181 break; 2182 case IFF_UP: 2183 error = rtwn_init(ifp); 2184 if (error != 0) 2185 ifp->if_flags &= ~IFF_UP; 2186 break; 2187 case IFF_RUNNING: 2188 rtwn_stop(ifp, 1); 2189 break; 2190 case 0: 2191 break; 2192 } 2193 break; 2194 2195 case SIOCADDMULTI: 2196 case SIOCDELMULTI: 2197 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2198 /* setup multicast filter, etc */ 2199 error = 0; 2200 } 2201 break; 2202 2203 case SIOCS80211CHANNEL: 2204 error = ieee80211_ioctl(ic, cmd, data); 2205 if (error == ENETRESET && 2206 ic->ic_opmode == IEEE80211_M_MONITOR) { 2207 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2208 (IFF_UP | IFF_RUNNING)) { 2209 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2210 } 2211 error = 0; 2212 } 2213 break; 2214 2215 default: 2216 error = ieee80211_ioctl(ic, cmd, data); 2217 break; 2218 } 2219 2220 if (error == ENETRESET) { 2221 error = 0; 2222 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2223 (IFF_UP | IFF_RUNNING)) { 2224 rtwn_stop(ifp, 0); 2225 error = rtwn_init(ifp); 2226 } 2227 } 2228 2229 splx(s); 2230 2231 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2232 error)); 2233 2234 return error; 2235 } 2236 2237 static int 2238 rtwn_power_on(struct rtwn_softc *sc) 2239 { 2240 uint32_t reg; 2241 int ntries; 2242 2243 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2244 2245 /* Wait for autoload done bit. */ 2246 for (ntries = 0; ntries < 1000; ntries++) { 2247 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2248 break; 2249 DELAY(5); 2250 } 2251 if (ntries == 1000) { 2252 aprint_error_dev(sc->sc_dev, 2253 "timeout waiting for chip autoload\n"); 2254 return ETIMEDOUT; 2255 } 2256 2257 /* Unlock ISO/CLK/Power control register. */ 2258 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2259 2260 /* TODO: check if we need this for 8188CE */ 2261 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2262 /* bt coex */ 2263 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2264 reg |= (R92C_APS_FSMCO_SOP_ABG | 2265 R92C_APS_FSMCO_SOP_AMB | 2266 R92C_APS_FSMCO_XOP_BTCK); 2267 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2268 } 2269 2270 /* Move SPS into PWM mode. */ 2271 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2272 DELAY(100); 2273 2274 /* Set low byte to 0x0f, leave others unchanged. */ 2275 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2276 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2277 2278 /* TODO: check if we need this for 8188CE */ 2279 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2280 /* bt coex */ 2281 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2282 reg &= ~0x00024800; /* XXX magic from linux */ 2283 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2284 } 2285 2286 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2287 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2288 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2289 DELAY(200); 2290 2291 /* TODO: linux does additional btcoex stuff here */ 2292 2293 /* Auto enable WLAN. */ 2294 rtwn_write_2(sc, R92C_APS_FSMCO, 2295 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2296 for (ntries = 0; ntries < 1000; ntries++) { 2297 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2298 R92C_APS_FSMCO_APFM_ONMAC)) 2299 break; 2300 DELAY(5); 2301 } 2302 if (ntries == 1000) { 2303 aprint_error_dev(sc->sc_dev, 2304 "timeout waiting for MAC auto ON\n"); 2305 return ETIMEDOUT; 2306 } 2307 2308 /* Enable radio, GPIO and LED functions. */ 2309 rtwn_write_2(sc, R92C_APS_FSMCO, 2310 R92C_APS_FSMCO_AFSM_PCIE | 2311 R92C_APS_FSMCO_PDN_EN | 2312 R92C_APS_FSMCO_PFM_ALDN); 2313 2314 /* Release RF digital isolation. */ 2315 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2316 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2317 2318 if (sc->chip & RTWN_CHIP_92C) 2319 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2320 else 2321 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2322 2323 rtwn_write_4(sc, R92C_INT_MIG, 0); 2324 2325 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2326 /* bt coex */ 2327 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2328 reg &= 0xfd; /* XXX magic from linux */ 2329 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2330 } 2331 2332 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2333 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2334 2335 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2336 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2337 aprint_error_dev(sc->sc_dev, 2338 "radio is disabled by hardware switch\n"); 2339 return EPERM; /* :-) */ 2340 } 2341 2342 /* Initialize MAC. */ 2343 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2344 rtwn_write_1(sc, R92C_APSD_CTRL, 2345 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2346 for (ntries = 0; ntries < 200; ntries++) { 2347 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2348 R92C_APSD_CTRL_OFF_STATUS)) 2349 break; 2350 DELAY(500); 2351 } 2352 if (ntries == 200) { 2353 aprint_error_dev(sc->sc_dev, 2354 "timeout waiting for MAC initialization\n"); 2355 return ETIMEDOUT; 2356 } 2357 2358 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2359 reg = rtwn_read_2(sc, R92C_CR); 2360 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2361 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2362 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2363 R92C_CR_ENSEC; 2364 rtwn_write_2(sc, R92C_CR, reg); 2365 2366 rtwn_write_1(sc, 0xfe10, 0x19); 2367 2368 return 0; 2369 } 2370 2371 static int 2372 rtwn_llt_init(struct rtwn_softc *sc) 2373 { 2374 int i, error; 2375 2376 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2377 2378 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2379 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2380 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2381 return error; 2382 } 2383 /* NB: 0xff indicates end-of-list. */ 2384 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2385 return error; 2386 /* 2387 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2388 * as ring buffer. 2389 */ 2390 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2391 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2392 return error; 2393 } 2394 /* Make the last page point to the beginning of the ring buffer. */ 2395 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2396 return error; 2397 } 2398 2399 static void 2400 rtwn_fw_reset(struct rtwn_softc *sc) 2401 { 2402 uint16_t reg; 2403 int ntries; 2404 2405 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2406 2407 /* Tell 8051 to reset itself. */ 2408 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2409 2410 /* Wait until 8051 resets by itself. */ 2411 for (ntries = 0; ntries < 100; ntries++) { 2412 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2413 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2414 goto sleep; 2415 DELAY(50); 2416 } 2417 /* Force 8051 reset. */ 2418 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2419 sleep: 2420 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2421 #if 0 2422 /* 2423 * We must sleep for one second to let the firmware settle. 2424 * Accessing registers too early will hang the whole system. 2425 */ 2426 tsleep(®, 0, "rtwnrst", hz); 2427 #else 2428 DELAY(1000 * 1000); 2429 #endif 2430 } 2431 2432 static int 2433 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2434 { 2435 uint32_t reg; 2436 int off, mlen, error = 0, i; 2437 2438 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2439 2440 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2441 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2442 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2443 2444 DELAY(5); 2445 2446 off = R92C_FW_START_ADDR; 2447 while (len > 0) { 2448 if (len > 196) 2449 mlen = 196; 2450 else if (len > 4) 2451 mlen = 4; 2452 else 2453 mlen = 1; 2454 for (i = 0; i < mlen; i++) 2455 rtwn_write_1(sc, off++, buf[i]); 2456 buf += mlen; 2457 len -= mlen; 2458 } 2459 2460 return error; 2461 } 2462 2463 static int 2464 rtwn_load_firmware(struct rtwn_softc *sc) 2465 { 2466 firmware_handle_t fwh; 2467 const struct r92c_fw_hdr *hdr; 2468 const char *name; 2469 u_char *fw, *ptr; 2470 size_t len; 2471 uint32_t reg; 2472 int mlen, ntries, page, error; 2473 2474 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2475 2476 /* Read firmware image from the filesystem. */ 2477 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2478 RTWN_CHIP_UMC_A_CUT) 2479 name = "rtl8192cfwU.bin"; 2480 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2481 name = "rtl8192cfwU_B.bin"; 2482 else 2483 name = "rtl8192cfw.bin"; 2484 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2485 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2486 aprint_error_dev(sc->sc_dev, 2487 "could not read firmware %s (error %d)\n", name, error); 2488 return error; 2489 } 2490 const size_t fwlen = len = firmware_get_size(fwh); 2491 fw = firmware_malloc(len); 2492 if (fw == NULL) { 2493 aprint_error_dev(sc->sc_dev, 2494 "failed to allocate firmware memory (size=%zu)\n", len); 2495 firmware_close(fwh); 2496 return ENOMEM; 2497 } 2498 error = firmware_read(fwh, 0, fw, len); 2499 firmware_close(fwh); 2500 if (error != 0) { 2501 aprint_error_dev(sc->sc_dev, 2502 "failed to read firmware (error %d)\n", error); 2503 firmware_free(fw, fwlen); 2504 return error; 2505 } 2506 2507 if (len < sizeof(*hdr)) { 2508 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2509 error = EINVAL; 2510 goto fail; 2511 } 2512 ptr = fw; 2513 hdr = (const struct r92c_fw_hdr *)ptr; 2514 /* Check if there is a valid FW header and skip it. */ 2515 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2516 (le16toh(hdr->signature) >> 4) == 0x92c) { 2517 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2518 le16toh(hdr->version), le16toh(hdr->subversion), 2519 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2520 ptr += sizeof(*hdr); 2521 len -= sizeof(*hdr); 2522 } 2523 2524 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2525 rtwn_fw_reset(sc); 2526 2527 /* Enable FW download. */ 2528 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2529 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2530 R92C_SYS_FUNC_EN_CPUEN); 2531 rtwn_write_1(sc, R92C_MCUFWDL, 2532 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2533 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2534 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2535 2536 /* Reset the FWDL checksum. */ 2537 rtwn_write_1(sc, R92C_MCUFWDL, 2538 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2539 2540 /* download firmware */ 2541 for (page = 0; len > 0; page++) { 2542 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2543 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2544 if (error != 0) { 2545 aprint_error_dev(sc->sc_dev, 2546 "could not load firmware page %d\n", page); 2547 goto fail; 2548 } 2549 ptr += mlen; 2550 len -= mlen; 2551 } 2552 2553 /* Disable FW download. */ 2554 rtwn_write_1(sc, R92C_MCUFWDL, 2555 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2556 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2557 2558 /* Wait for checksum report. */ 2559 for (ntries = 0; ntries < 1000; ntries++) { 2560 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2561 break; 2562 DELAY(5); 2563 } 2564 if (ntries == 1000) { 2565 aprint_error_dev(sc->sc_dev, 2566 "timeout waiting for checksum report\n"); 2567 error = ETIMEDOUT; 2568 goto fail; 2569 } 2570 2571 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2572 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2573 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2574 2575 /* Wait for firmware readiness. */ 2576 for (ntries = 0; ntries < 1000; ntries++) { 2577 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2578 break; 2579 DELAY(5); 2580 } 2581 if (ntries == 1000) { 2582 aprint_error_dev(sc->sc_dev, 2583 "timeout waiting for firmware readiness\n"); 2584 error = ETIMEDOUT; 2585 goto fail; 2586 } 2587 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2588 2589 fail: 2590 firmware_free(fw, fwlen); 2591 return error; 2592 } 2593 2594 static int 2595 rtwn_dma_init(struct rtwn_softc *sc) 2596 { 2597 uint32_t reg; 2598 int error; 2599 2600 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2601 2602 /* Initialize LLT table. */ 2603 error = rtwn_llt_init(sc); 2604 if (error != 0) 2605 return error; 2606 2607 /* Set number of pages for normal priority queue. */ 2608 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2609 rtwn_write_4(sc, R92C_RQPN, 2610 /* Set number of pages for public queue. */ 2611 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2612 /* Set number of pages for high priority queue. */ 2613 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2614 /* Set number of pages for low priority queue. */ 2615 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2616 /* Load values. */ 2617 R92C_RQPN_LD); 2618 2619 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2620 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2621 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2622 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2623 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2624 2625 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2626 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2627 reg |= 0xF771; 2628 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2629 2630 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2631 2632 /* Configure Tx DMA. */ 2633 rtwn_write_4(sc, R92C_BKQ_DESA, 2634 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2635 rtwn_write_4(sc, R92C_BEQ_DESA, 2636 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2637 rtwn_write_4(sc, R92C_VIQ_DESA, 2638 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2639 rtwn_write_4(sc, R92C_VOQ_DESA, 2640 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2641 rtwn_write_4(sc, R92C_BCNQ_DESA, 2642 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2643 rtwn_write_4(sc, R92C_MGQ_DESA, 2644 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2645 rtwn_write_4(sc, R92C_HQ_DESA, 2646 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2647 2648 /* Configure Rx DMA. */ 2649 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2650 2651 /* Set Tx/Rx transfer page boundary. */ 2652 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2653 2654 /* Set Tx/Rx transfer page size. */ 2655 rtwn_write_1(sc, R92C_PBP, 2656 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2657 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2658 return 0; 2659 } 2660 2661 static void 2662 rtwn_mac_init(struct rtwn_softc *sc) 2663 { 2664 int i; 2665 2666 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2667 2668 /* Write MAC initialization values. */ 2669 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2670 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2671 } 2672 2673 static void 2674 rtwn_bb_init(struct rtwn_softc *sc) 2675 { 2676 const struct rtwn_bb_prog *prog; 2677 uint32_t reg; 2678 int i; 2679 2680 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2681 2682 /* Enable BB and RF. */ 2683 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2684 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2685 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2686 R92C_SYS_FUNC_EN_DIO_RF); 2687 2688 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2689 2690 rtwn_write_1(sc, R92C_RF_CTRL, 2691 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2692 2693 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2694 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2695 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2696 R92C_SYS_FUNC_EN_BBRSTB); 2697 2698 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2699 2700 rtwn_write_4(sc, R92C_LEDCFG0, 2701 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2702 2703 /* Select BB programming. */ 2704 prog = (sc->chip & RTWN_CHIP_92C) ? 2705 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2706 2707 /* Write BB initialization values. */ 2708 for (i = 0; i < prog->count; i++) { 2709 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2710 DELAY(1); 2711 } 2712 2713 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2714 /* 8192C 1T only configuration. */ 2715 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2716 reg = (reg & ~0x00000003) | 0x2; 2717 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2718 2719 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2720 reg = (reg & ~0x00300033) | 0x00200022; 2721 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2722 2723 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2724 reg = (reg & ~0xff000000) | 0x45 << 24; 2725 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2726 2727 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2728 reg = (reg & ~0x000000ff) | 0x23; 2729 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2730 2731 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2732 reg = (reg & ~0x00000030) | 1 << 4; 2733 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2734 2735 reg = rtwn_bb_read(sc, 0xe74); 2736 reg = (reg & ~0x0c000000) | 2 << 26; 2737 rtwn_bb_write(sc, 0xe74, reg); 2738 reg = rtwn_bb_read(sc, 0xe78); 2739 reg = (reg & ~0x0c000000) | 2 << 26; 2740 rtwn_bb_write(sc, 0xe78, reg); 2741 reg = rtwn_bb_read(sc, 0xe7c); 2742 reg = (reg & ~0x0c000000) | 2 << 26; 2743 rtwn_bb_write(sc, 0xe7c, reg); 2744 reg = rtwn_bb_read(sc, 0xe80); 2745 reg = (reg & ~0x0c000000) | 2 << 26; 2746 rtwn_bb_write(sc, 0xe80, reg); 2747 reg = rtwn_bb_read(sc, 0xe88); 2748 reg = (reg & ~0x0c000000) | 2 << 26; 2749 rtwn_bb_write(sc, 0xe88, reg); 2750 } 2751 2752 /* Write AGC values. */ 2753 for (i = 0; i < prog->agccount; i++) { 2754 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2755 prog->agcvals[i]); 2756 DELAY(1); 2757 } 2758 2759 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2760 R92C_HSSI_PARAM2_CCK_HIPWR) 2761 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2762 } 2763 2764 static void 2765 rtwn_rf_init(struct rtwn_softc *sc) 2766 { 2767 const struct rtwn_rf_prog *prog; 2768 uint32_t reg, type; 2769 int i, j, idx, off; 2770 2771 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2772 2773 /* Select RF programming based on board type. */ 2774 if (!(sc->chip & RTWN_CHIP_92C)) { 2775 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2776 prog = rtl8188ce_rf_prog; 2777 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2778 prog = rtl8188ru_rf_prog; 2779 else 2780 prog = rtl8188cu_rf_prog; 2781 } else 2782 prog = rtl8192ce_rf_prog; 2783 2784 for (i = 0; i < sc->nrxchains; i++) { 2785 /* Save RF_ENV control type. */ 2786 idx = i / 2; 2787 off = (i % 2) * 16; 2788 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2789 type = (reg >> off) & 0x10; 2790 2791 /* Set RF_ENV enable. */ 2792 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2793 reg |= 0x100000; 2794 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2795 DELAY(1); 2796 /* Set RF_ENV output high. */ 2797 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2798 reg |= 0x10; 2799 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2800 DELAY(1); 2801 /* Set address and data lengths of RF registers. */ 2802 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2803 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2804 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2805 DELAY(1); 2806 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2807 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2808 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2809 DELAY(1); 2810 2811 /* Write RF initialization values for this chain. */ 2812 for (j = 0; j < prog[i].count; j++) { 2813 if (prog[i].regs[j] >= 0xf9 && 2814 prog[i].regs[j] <= 0xfe) { 2815 /* 2816 * These are fake RF registers offsets that 2817 * indicate a delay is required. 2818 */ 2819 DELAY(50); 2820 continue; 2821 } 2822 rtwn_rf_write(sc, i, prog[i].regs[j], 2823 prog[i].vals[j]); 2824 DELAY(1); 2825 } 2826 2827 /* Restore RF_ENV control type. */ 2828 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2829 reg &= ~(0x10 << off) | (type << off); 2830 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2831 2832 /* Cache RF register CHNLBW. */ 2833 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2834 } 2835 2836 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2837 RTWN_CHIP_UMC_A_CUT) { 2838 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2839 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2840 } 2841 } 2842 2843 static void 2844 rtwn_cam_init(struct rtwn_softc *sc) 2845 { 2846 2847 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2848 2849 /* Invalidate all CAM entries. */ 2850 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2851 } 2852 2853 static void 2854 rtwn_pa_bias_init(struct rtwn_softc *sc) 2855 { 2856 uint8_t reg; 2857 int i; 2858 2859 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2860 2861 for (i = 0; i < sc->nrxchains; i++) { 2862 if (sc->pa_setting & (1 << i)) 2863 continue; 2864 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2865 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2866 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2867 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2868 } 2869 if (!(sc->pa_setting & 0x10)) { 2870 reg = rtwn_read_1(sc, 0x16); 2871 reg = (reg & ~0xf0) | 0x90; 2872 rtwn_write_1(sc, 0x16, reg); 2873 } 2874 } 2875 2876 static void 2877 rtwn_rxfilter_init(struct rtwn_softc *sc) 2878 { 2879 2880 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2881 2882 /* Initialize Rx filter. */ 2883 /* TODO: use better filter for monitor mode. */ 2884 rtwn_write_4(sc, R92C_RCR, 2885 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2886 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2887 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2888 /* Accept all multicast frames. */ 2889 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2890 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2891 /* Accept all management frames. */ 2892 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2893 /* Reject all control frames. */ 2894 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2895 /* Accept all data frames. */ 2896 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2897 } 2898 2899 static void 2900 rtwn_edca_init(struct rtwn_softc *sc) 2901 { 2902 2903 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2904 2905 /* set spec SIFS (used in NAV) */ 2906 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2907 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2908 2909 /* set SIFS CCK/OFDM */ 2910 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2911 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2912 2913 /* TXOP */ 2914 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2915 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2916 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2917 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2918 } 2919 2920 static void 2921 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2922 uint16_t power[RTWN_RIDX_COUNT]) 2923 { 2924 uint32_t reg; 2925 2926 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2927 2928 /* Write per-CCK rate Tx power. */ 2929 if (chain == 0) { 2930 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2931 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2932 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2933 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2934 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2935 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2936 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2937 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2938 } else { 2939 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2940 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2941 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2942 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2943 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2944 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2945 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2946 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2947 } 2948 /* Write per-OFDM rate Tx power. */ 2949 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2950 SM(R92C_TXAGC_RATE06, power[ 4]) | 2951 SM(R92C_TXAGC_RATE09, power[ 5]) | 2952 SM(R92C_TXAGC_RATE12, power[ 6]) | 2953 SM(R92C_TXAGC_RATE18, power[ 7])); 2954 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2955 SM(R92C_TXAGC_RATE24, power[ 8]) | 2956 SM(R92C_TXAGC_RATE36, power[ 9]) | 2957 SM(R92C_TXAGC_RATE48, power[10]) | 2958 SM(R92C_TXAGC_RATE54, power[11])); 2959 /* Write per-MCS Tx power. */ 2960 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2961 SM(R92C_TXAGC_MCS00, power[12]) | 2962 SM(R92C_TXAGC_MCS01, power[13]) | 2963 SM(R92C_TXAGC_MCS02, power[14]) | 2964 SM(R92C_TXAGC_MCS03, power[15])); 2965 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2966 SM(R92C_TXAGC_MCS04, power[16]) | 2967 SM(R92C_TXAGC_MCS05, power[17]) | 2968 SM(R92C_TXAGC_MCS06, power[18]) | 2969 SM(R92C_TXAGC_MCS07, power[19])); 2970 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2971 SM(R92C_TXAGC_MCS08, power[20]) | 2972 SM(R92C_TXAGC_MCS09, power[21]) | 2973 SM(R92C_TXAGC_MCS10, power[22]) | 2974 SM(R92C_TXAGC_MCS11, power[23])); 2975 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2976 SM(R92C_TXAGC_MCS12, power[24]) | 2977 SM(R92C_TXAGC_MCS13, power[25]) | 2978 SM(R92C_TXAGC_MCS14, power[26]) | 2979 SM(R92C_TXAGC_MCS15, power[27])); 2980 } 2981 2982 static void 2983 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2984 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2985 uint16_t power[RTWN_RIDX_COUNT]) 2986 { 2987 struct ieee80211com *ic = &sc->sc_ic; 2988 struct r92c_rom *rom = &sc->rom; 2989 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2990 const struct rtwn_txpwr *base; 2991 int ridx, chan, group; 2992 2993 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2994 2995 /* Determine channel group. */ 2996 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2997 if (chan <= 3) 2998 group = 0; 2999 else if (chan <= 9) 3000 group = 1; 3001 else 3002 group = 2; 3003 3004 /* Get original Tx power based on board type and RF chain. */ 3005 if (!(sc->chip & RTWN_CHIP_92C)) { 3006 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3007 base = &rtl8188ru_txagc[chain]; 3008 else 3009 base = &rtl8192cu_txagc[chain]; 3010 } else 3011 base = &rtl8192cu_txagc[chain]; 3012 3013 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 3014 if (sc->regulatory == 0) { 3015 for (ridx = 0; ridx <= 3; ridx++) 3016 power[ridx] = base->pwr[0][ridx]; 3017 } 3018 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3019 if (sc->regulatory == 3) { 3020 power[ridx] = base->pwr[0][ridx]; 3021 /* Apply vendor limits. */ 3022 if (extc != NULL) 3023 maxpwr = rom->ht40_max_pwr[group]; 3024 else 3025 maxpwr = rom->ht20_max_pwr[group]; 3026 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 3027 if (power[ridx] > maxpwr) 3028 power[ridx] = maxpwr; 3029 } else if (sc->regulatory == 1) { 3030 if (extc == NULL) 3031 power[ridx] = base->pwr[group][ridx]; 3032 } else if (sc->regulatory != 2) 3033 power[ridx] = base->pwr[0][ridx]; 3034 } 3035 3036 /* Compute per-CCK rate Tx power. */ 3037 cckpow = rom->cck_tx_pwr[chain][group]; 3038 for (ridx = 0; ridx <= 3; ridx++) { 3039 power[ridx] += cckpow; 3040 if (power[ridx] > R92C_MAX_TX_PWR) 3041 power[ridx] = R92C_MAX_TX_PWR; 3042 } 3043 3044 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3045 if (sc->ntxchains > 1) { 3046 /* Apply reduction for 2 spatial streams. */ 3047 diff = rom->ht40_2s_tx_pwr_diff[group]; 3048 diff = (diff >> (chain * 4)) & 0xf; 3049 htpow = (htpow > diff) ? htpow - diff : 0; 3050 } 3051 3052 /* Compute per-OFDM rate Tx power. */ 3053 diff = rom->ofdm_tx_pwr_diff[group]; 3054 diff = (diff >> (chain * 4)) & 0xf; 3055 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3056 for (ridx = 4; ridx <= 11; ridx++) { 3057 power[ridx] += ofdmpow; 3058 if (power[ridx] > R92C_MAX_TX_PWR) 3059 power[ridx] = R92C_MAX_TX_PWR; 3060 } 3061 3062 /* Compute per-MCS Tx power. */ 3063 if (extc == NULL) { 3064 diff = rom->ht20_tx_pwr_diff[group]; 3065 diff = (diff >> (chain * 4)) & 0xf; 3066 htpow += diff; /* HT40->HT20 correction. */ 3067 } 3068 for (ridx = 12; ridx <= 27; ridx++) { 3069 power[ridx] += htpow; 3070 if (power[ridx] > R92C_MAX_TX_PWR) 3071 power[ridx] = R92C_MAX_TX_PWR; 3072 } 3073 #ifdef RTWN_DEBUG 3074 if (rtwn_debug >= 4) { 3075 /* Dump per-rate Tx power values. */ 3076 printf("Tx power for chain %d:\n", chain); 3077 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3078 printf("Rate %d = %u\n", ridx, power[ridx]); 3079 } 3080 #endif 3081 } 3082 3083 static void 3084 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3085 struct ieee80211_channel *extc) 3086 { 3087 uint16_t power[RTWN_RIDX_COUNT]; 3088 int i; 3089 3090 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3091 3092 for (i = 0; i < sc->ntxchains; i++) { 3093 /* Compute per-rate Tx power values. */ 3094 rtwn_get_txpower(sc, i, c, extc, power); 3095 /* Write per-rate Tx power values to hardware. */ 3096 rtwn_write_txpower(sc, i, power); 3097 } 3098 } 3099 3100 static void 3101 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3102 struct ieee80211_channel *extc) 3103 { 3104 struct ieee80211com *ic = &sc->sc_ic; 3105 u_int chan; 3106 int i; 3107 3108 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3109 3110 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3111 3112 /* Set Tx power for this new channel. */ 3113 rtwn_set_txpower(sc, c, extc); 3114 3115 for (i = 0; i < sc->nrxchains; i++) { 3116 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3117 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3118 } 3119 #ifndef IEEE80211_NO_HT 3120 if (extc != NULL) { 3121 uint32_t reg; 3122 3123 /* Is secondary channel below or above primary? */ 3124 int prichlo = c->ic_freq < extc->ic_freq; 3125 3126 rtwn_write_1(sc, R92C_BWOPMODE, 3127 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3128 3129 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3130 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3131 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3132 3133 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3134 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3135 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3136 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3137 3138 /* Set CCK side band. */ 3139 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3140 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3141 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3142 3143 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3144 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3145 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3146 3147 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3148 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3149 ~R92C_FPGA0_ANAPARAM2_CBW20); 3150 3151 reg = rtwn_bb_read(sc, 0x818); 3152 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3153 rtwn_bb_write(sc, 0x818, reg); 3154 3155 /* Select 40MHz bandwidth. */ 3156 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3157 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3158 } else 3159 #endif 3160 { 3161 rtwn_write_1(sc, R92C_BWOPMODE, 3162 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3163 3164 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3165 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3166 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3167 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3168 3169 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3170 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3171 R92C_FPGA0_ANAPARAM2_CBW20); 3172 3173 /* Select 20MHz bandwidth. */ 3174 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3175 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3176 } 3177 } 3178 3179 static void 3180 rtwn_iq_calib(struct rtwn_softc *sc) 3181 { 3182 3183 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3184 3185 /* XXX */ 3186 } 3187 3188 static void 3189 rtwn_lc_calib(struct rtwn_softc *sc) 3190 { 3191 uint32_t rf_ac[2]; 3192 uint8_t txmode; 3193 int i; 3194 3195 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3196 3197 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3198 if ((txmode & 0x70) != 0) { 3199 /* Disable all continuous Tx. */ 3200 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3201 3202 /* Set RF mode to standby mode. */ 3203 for (i = 0; i < sc->nrxchains; i++) { 3204 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3205 rtwn_rf_write(sc, i, R92C_RF_AC, 3206 RW(rf_ac[i], R92C_RF_AC_MODE, 3207 R92C_RF_AC_MODE_STANDBY)); 3208 } 3209 } else { 3210 /* Block all Tx queues. */ 3211 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3212 } 3213 /* Start calibration. */ 3214 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3215 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3216 3217 /* Give calibration the time to complete. */ 3218 DELAY(100); 3219 3220 /* Restore configuration. */ 3221 if ((txmode & 0x70) != 0) { 3222 /* Restore Tx mode. */ 3223 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3224 /* Restore RF mode. */ 3225 for (i = 0; i < sc->nrxchains; i++) 3226 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3227 } else { 3228 /* Unblock all Tx queues. */ 3229 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3230 } 3231 } 3232 3233 static void 3234 rtwn_temp_calib(struct rtwn_softc *sc) 3235 { 3236 int temp; 3237 3238 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3239 3240 if (sc->thcal_state == 0) { 3241 /* Start measuring temperature. */ 3242 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3243 sc->thcal_state = 1; 3244 return; 3245 } 3246 sc->thcal_state = 0; 3247 3248 /* Read measured temperature. */ 3249 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3250 if (temp == 0) /* Read failed, skip. */ 3251 return; 3252 DPRINTFN(2, ("temperature=%d\n", temp)); 3253 3254 /* 3255 * Redo IQ and LC calibration if temperature changed significantly 3256 * since last calibration. 3257 */ 3258 if (sc->thcal_lctemp == 0) { 3259 /* First calibration is performed in rtwn_init(). */ 3260 sc->thcal_lctemp = temp; 3261 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3262 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3263 sc->thcal_lctemp, temp)); 3264 rtwn_iq_calib(sc); 3265 rtwn_lc_calib(sc); 3266 /* Record temperature of last calibration. */ 3267 sc->thcal_lctemp = temp; 3268 } 3269 } 3270 3271 static int 3272 rtwn_init(struct ifnet *ifp) 3273 { 3274 struct rtwn_softc *sc = ifp->if_softc; 3275 struct ieee80211com *ic = &sc->sc_ic; 3276 uint32_t reg; 3277 int i, error; 3278 3279 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3280 3281 /* Init firmware commands ring. */ 3282 sc->fwcur = 0; 3283 3284 /* Power on adapter. */ 3285 error = rtwn_power_on(sc); 3286 if (error != 0) { 3287 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3288 goto fail; 3289 } 3290 3291 /* Initialize DMA. */ 3292 error = rtwn_dma_init(sc); 3293 if (error != 0) { 3294 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3295 goto fail; 3296 } 3297 3298 /* Set info size in Rx descriptors (in 64-bit words). */ 3299 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3300 3301 /* Disable interrupts. */ 3302 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3303 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3304 3305 /* Set MAC address. */ 3306 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3307 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3308 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3309 3310 /* Set initial network type. */ 3311 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3312 3313 rtwn_rxfilter_init(sc); 3314 3315 reg = rtwn_read_4(sc, R92C_RRSR); 3316 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3317 rtwn_write_4(sc, R92C_RRSR, reg); 3318 3319 /* Set short/long retry limits. */ 3320 rtwn_write_2(sc, R92C_RL, 3321 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3322 3323 /* Initialize EDCA parameters. */ 3324 rtwn_edca_init(sc); 3325 3326 /* Set data and response automatic rate fallback retry counts. */ 3327 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3328 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3329 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3330 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3331 3332 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3333 3334 /* Set ACK timeout. */ 3335 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3336 3337 /* Initialize beacon parameters. */ 3338 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3339 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3340 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3341 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3342 3343 /* Setup AMPDU aggregation. */ 3344 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3345 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3346 3347 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3348 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3349 3350 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3351 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3352 3353 /* Load 8051 microcode. */ 3354 error = rtwn_load_firmware(sc); 3355 if (error != 0) 3356 goto fail; 3357 3358 /* Initialize MAC/BB/RF blocks. */ 3359 rtwn_mac_init(sc); 3360 rtwn_bb_init(sc); 3361 rtwn_rf_init(sc); 3362 3363 /* Turn CCK and OFDM blocks on. */ 3364 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3365 reg |= R92C_RFMOD_CCK_EN; 3366 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3367 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3368 reg |= R92C_RFMOD_OFDM_EN; 3369 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3370 3371 /* Clear per-station keys table. */ 3372 rtwn_cam_init(sc); 3373 3374 /* Enable hardware sequence numbering. */ 3375 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3376 3377 /* Perform LO and IQ calibrations. */ 3378 rtwn_iq_calib(sc); 3379 /* Perform LC calibration. */ 3380 rtwn_lc_calib(sc); 3381 3382 rtwn_pa_bias_init(sc); 3383 3384 /* Initialize GPIO setting. */ 3385 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3386 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3387 3388 /* Fix for lower temperature. */ 3389 rtwn_write_1(sc, 0x15, 0xe9); 3390 3391 /* Set default channel. */ 3392 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3393 3394 /* Clear pending interrupts. */ 3395 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3396 3397 /* Enable interrupts. */ 3398 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3399 3400 /* We're ready to go. */ 3401 ifp->if_flags &= ~IFF_OACTIVE; 3402 ifp->if_flags |= IFF_RUNNING; 3403 3404 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3405 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3406 else 3407 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3408 3409 return 0; 3410 3411 fail: 3412 rtwn_stop(ifp, 1); 3413 return error; 3414 } 3415 3416 static void 3417 rtwn_init_task(void *arg) 3418 { 3419 struct rtwn_softc *sc = arg; 3420 struct ifnet *ifp = GET_IFP(sc); 3421 int s; 3422 3423 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3424 3425 s = splnet(); 3426 3427 rtwn_stop(ifp, 0); 3428 3429 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3430 rtwn_init(ifp); 3431 3432 splx(s); 3433 } 3434 3435 static void 3436 rtwn_stop(struct ifnet *ifp, int disable) 3437 { 3438 struct rtwn_softc *sc = ifp->if_softc; 3439 struct ieee80211com *ic = &sc->sc_ic; 3440 uint16_t reg; 3441 int s, i; 3442 3443 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3444 3445 sc->sc_tx_timer = 0; 3446 ifp->if_timer = 0; 3447 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3448 3449 callout_stop(&sc->scan_to); 3450 callout_stop(&sc->calib_to); 3451 3452 s = splnet(); 3453 3454 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3455 3456 /* Disable interrupts. */ 3457 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3458 3459 /* Pause MAC TX queue */ 3460 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3461 3462 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3463 3464 /* Reset BB state machine */ 3465 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3466 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3467 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3468 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3469 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3470 3471 reg = rtwn_read_2(sc, R92C_CR); 3472 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3473 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3474 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3475 R92C_CR_ENSEC); 3476 rtwn_write_2(sc, R92C_CR, reg); 3477 3478 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3479 rtwn_fw_reset(sc); 3480 3481 /* Reset MAC and Enable 8051 */ 3482 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3483 3484 /* TODO: linux does additional btcoex stuff here */ 3485 3486 /* Disable AFE PLL */ 3487 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3488 /* Enter PFM mode */ 3489 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3490 /* Gated AFE DIG_CLOCK */ 3491 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3492 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3493 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3494 3495 for (i = 0; i < RTWN_NTXQUEUES; i++) 3496 rtwn_reset_tx_list(sc, i); 3497 rtwn_reset_rx_list(sc); 3498 3499 splx(s); 3500 } 3501 3502 static int 3503 rtwn_intr(void *xsc) 3504 { 3505 struct rtwn_softc *sc = xsc; 3506 uint32_t status; 3507 3508 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3509 return 0; 3510 3511 status = rtwn_read_4(sc, R92C_HISR); 3512 if (status == 0 || status == 0xffffffff) 3513 return 0; 3514 3515 /* Disable interrupts. */ 3516 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3517 3518 softint_schedule(sc->sc_soft_ih); 3519 return 1; 3520 } 3521 3522 static void 3523 rtwn_softintr(void *xsc) 3524 { 3525 struct rtwn_softc *sc = xsc; 3526 uint32_t status; 3527 int i, s; 3528 3529 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3530 return; 3531 3532 status = rtwn_read_4(sc, R92C_HISR); 3533 if (status == 0 || status == 0xffffffff) 3534 goto out; 3535 3536 /* Ack interrupts. */ 3537 rtwn_write_4(sc, R92C_HISR, status); 3538 3539 /* Vendor driver treats RX errors like ROK... */ 3540 if (status & RTWN_INT_ENABLE_RX) { 3541 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3542 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3543 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3544 3545 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3546 continue; 3547 3548 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3549 } 3550 } 3551 3552 if (status & R92C_IMR_BDOK) 3553 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3554 if (status & R92C_IMR_HIGHDOK) 3555 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3556 if (status & R92C_IMR_MGNTDOK) 3557 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3558 if (status & R92C_IMR_BKDOK) 3559 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3560 if (status & R92C_IMR_BEDOK) 3561 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3562 if (status & R92C_IMR_VIDOK) 3563 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3564 if (status & R92C_IMR_VODOK) 3565 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3566 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3567 struct ifnet *ifp = GET_IFP(sc); 3568 s = splnet(); 3569 ifp->if_flags &= ~IFF_OACTIVE; 3570 rtwn_start(ifp); 3571 splx(s); 3572 } 3573 3574 out: 3575 /* Enable interrupts. */ 3576 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3577 } 3578
Indexes created Thu Oct 02 01:09:59 GMT 2025