if_rtwn.c revision 1.18.6.1
1 /* $NetBSD: if_rtwn.c,v 1.18.6.1 2020/02/29 20:19:10 ad Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.18.6.1 2020/02/29 20:19:10 ad Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/ic/rtwnreg.h> 63 #include <dev/ic/rtwn_data.h> 64 #include <dev/pci/if_rtwnreg.h> 65 66 #ifdef RTWN_DEBUG 67 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 69 int rtwn_debug = 0; 70 #else 71 #define DPRINTF(x) 72 #define DPRINTFN(n, x) 73 #endif 74 75 /* 76 * PCI configuration space registers. 77 */ 78 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 79 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 80 81 #define RTWN_INT_ENABLE_TX \ 82 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 83 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 84 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 85 #define RTWN_INT_ENABLE_RX \ 86 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 87 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 88 89 static const struct rtwn_device { 90 pci_vendor_id_t rd_vendor; 91 pci_product_id_t rd_product; 92 } rtwn_devices[] = { 93 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 94 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 95 }; 96 97 static int rtwn_match(device_t, cfdata_t, void *); 98 static void rtwn_attach(device_t, device_t, void *); 99 static int rtwn_detach(device_t, int); 100 static int rtwn_activate(device_t, enum devact); 101 102 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 103 rtwn_attach, rtwn_detach, rtwn_activate); 104 105 static int rtwn_alloc_rx_list(struct rtwn_softc *); 106 static void rtwn_reset_rx_list(struct rtwn_softc *); 107 static void rtwn_free_rx_list(struct rtwn_softc *); 108 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc_pci *, 109 bus_addr_t, size_t, int); 110 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 112 static void rtwn_free_tx_list(struct rtwn_softc *, int); 113 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 114 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 115 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 116 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 117 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 118 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 119 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 120 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 121 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 122 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 123 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 124 static void rtwn_efuse_read(struct rtwn_softc *); 125 static int rtwn_read_chipid(struct rtwn_softc *); 126 static void rtwn_efuse_switch_power(struct rtwn_softc *); 127 static void rtwn_read_rom(struct rtwn_softc *); 128 static int rtwn_media_change(struct ifnet *); 129 static int rtwn_ra_init(struct rtwn_softc *); 130 static int rtwn_get_nettype(struct rtwn_softc *); 131 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 132 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 133 static void rtwn_set_led(struct rtwn_softc *, int, int); 134 static void rtwn_calib_to(void *); 135 static void rtwn_next_scan(void *); 136 static void rtwn_newassoc(struct ieee80211_node *, int); 137 static int rtwn_reset(struct ifnet *); 138 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 139 int); 140 static int rtwn_wme_update(struct ieee80211com *); 141 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 142 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 143 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc_pci *, 144 struct rtwn_rx_data *, int); 145 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 146 struct ieee80211_node *); 147 static void rtwn_tx_done(struct rtwn_softc *, int); 148 static void rtwn_start(struct ifnet *); 149 static void rtwn_watchdog(struct ifnet *); 150 static int rtwn_ioctl(struct ifnet *, u_long, void *); 151 static int rtwn_power_on(struct rtwn_softc *); 152 static int rtwn_llt_init(struct rtwn_softc *); 153 static void rtwn_fw_reset(struct rtwn_softc *); 154 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 155 static int rtwn_load_firmware(struct rtwn_softc *); 156 static int rtwn_dma_init(struct rtwn_softc *); 157 static void rtwn_mac_init(struct rtwn_softc *); 158 static void rtwn_bb_init(struct rtwn_softc *); 159 static void rtwn_rf_init(struct rtwn_softc *); 160 static void rtwn_cam_init(struct rtwn_softc *); 161 static void rtwn_pa_bias_init(struct rtwn_softc *); 162 static void rtwn_rxfilter_init(struct rtwn_softc *); 163 static void rtwn_edca_init(struct rtwn_softc *); 164 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 165 static void rtwn_get_txpower(struct rtwn_softc *, int, 166 struct ieee80211_channel *, struct ieee80211_channel *, 167 uint16_t[]); 168 static void rtwn_set_txpower(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_set_chan(struct rtwn_softc *, 171 struct ieee80211_channel *, struct ieee80211_channel *); 172 static void rtwn_iq_calib(struct rtwn_softc *); 173 static void rtwn_lc_calib(struct rtwn_softc *); 174 static void rtwn_temp_calib(struct rtwn_softc *); 175 static int rtwn_init(struct ifnet *); 176 static void rtwn_init_task(void *); 177 static void rtwn_stop(struct ifnet *, int); 178 static int rtwn_intr(void *); 179 static void rtwn_softintr(void *); 180 181 /* Aliases. */ 182 #define rtwn_bb_write rtwn_write_4 183 #define rtwn_bb_read rtwn_read_4 184 185 static const struct rtwn_device * 186 rtwn_lookup(const struct pci_attach_args *pa) 187 { 188 const struct rtwn_device *rd; 189 int i; 190 191 for (i = 0; i < __arraycount(rtwn_devices); i++) { 192 rd = &rtwn_devices[i]; 193 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 194 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 195 return rd; 196 } 197 return NULL; 198 } 199 200 static int 201 rtwn_match(device_t parent, cfdata_t match, void *aux) 202 { 203 struct pci_attach_args *pa = aux; 204 205 if (rtwn_lookup(pa) != NULL) 206 return 1; 207 return 0; 208 } 209 210 static void 211 rtwn_attach(device_t parent, device_t self, void *aux) 212 { 213 struct rtwn_softc *sc = device_private(self); 214 struct pci_attach_args *pa = aux; 215 struct ieee80211com *ic = &sc->sc_ic; 216 struct ifnet *ifp = GET_IFP(sc); 217 int i, error; 218 pcireg_t memtype; 219 const char *intrstr; 220 char intrbuf[PCI_INTRSTR_LEN]; 221 222 sc->sc_dev = self; 223 sc->sc_dmat = pa->pa_dmat; 224 sc->sc_pc = pa->pa_pc; 225 sc->sc_tag = pa->pa_tag; 226 227 pci_aprint_devinfo(pa, NULL); 228 229 callout_init(&sc->scan_to, 0); 230 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 231 callout_init(&sc->calib_to, 0); 232 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 233 234 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc); 235 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 236 237 /* Power up the device */ 238 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 239 240 /* Map control/status registers. */ 241 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 242 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 243 &sc->sc_sh, NULL, &sc->sc_mapsize); 244 if (error != 0) { 245 aprint_error_dev(self, "can't map mem space\n"); 246 return; 247 } 248 249 /* Install interrupt handler. */ 250 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 251 aprint_error_dev(self, "can't map interrupt\n"); 252 return; 253 } 254 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 255 sizeof(intrbuf)); 256 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 257 rtwn_intr, sc, device_xname(self)); 258 if (sc->sc_ih == NULL) { 259 aprint_error_dev(self, "can't establish interrupt"); 260 if (intrstr != NULL) 261 aprint_error(" at %s", intrstr); 262 aprint_error("\n"); 263 return; 264 } 265 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 266 267 error = rtwn_read_chipid(sc); 268 if (error != 0) { 269 aprint_error_dev(self, "unsupported test or unknown chip\n"); 270 return; 271 } 272 273 /* Disable PCIe Active State Power Management (ASPM). */ 274 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 275 &sc->sc_cap_off, NULL)) { 276 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 277 sc->sc_cap_off + PCIE_LCSR); 278 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 279 pci_conf_write(sc->sc_pc, sc->sc_tag, 280 sc->sc_cap_off + PCIE_LCSR, lcsr); 281 } 282 283 /* Allocate Tx/Rx buffers. */ 284 error = rtwn_alloc_rx_list(sc); 285 if (error != 0) { 286 aprint_error_dev(self, "could not allocate Rx buffers\n"); 287 return; 288 } 289 for (i = 0; i < RTWN_NTXQUEUES; i++) { 290 error = rtwn_alloc_tx_list(sc, i); 291 if (error != 0) { 292 aprint_error_dev(self, 293 "could not allocate Tx buffers\n"); 294 return; 295 } 296 } 297 298 /* Determine number of Tx/Rx chains. */ 299 if (sc->chip & RTWN_CHIP_92C) { 300 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 301 sc->nrxchains = 2; 302 } else { 303 sc->ntxchains = 1; 304 sc->nrxchains = 1; 305 } 306 rtwn_read_rom(sc); 307 308 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 309 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 310 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 311 312 /* 313 * Setup the 802.11 device. 314 */ 315 ic->ic_ifp = ifp; 316 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 317 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 318 ic->ic_state = IEEE80211_S_INIT; 319 320 /* Set device capabilities. */ 321 ic->ic_caps = 322 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 323 IEEE80211_C_IBSS | /* IBSS mode supported */ 324 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 325 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 326 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 327 IEEE80211_C_WME | /* 802.11e */ 328 IEEE80211_C_WPA; /* WPA/RSN. */ 329 330 #ifndef IEEE80211_NO_HT 331 /* Set HT capabilities. */ 332 ic->ic_htcaps = 333 IEEE80211_HTCAP_CBW20_40 | 334 IEEE80211_HTCAP_DSSSCCK40; 335 /* Set supported HT rates. */ 336 for (i = 0; i < sc->nrxchains; i++) 337 ic->ic_sup_mcs[i] = 0xff; 338 #endif 339 340 /* Set supported .11b and .11g rates. */ 341 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 342 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 343 344 /* Set supported .11b and .11g channels (1 through 14). */ 345 for (i = 1; i <= 14; i++) { 346 ic->ic_channels[i].ic_freq = 347 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 348 ic->ic_channels[i].ic_flags = 349 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 350 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 351 } 352 353 ifp->if_softc = sc; 354 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 355 ifp->if_init = rtwn_init; 356 ifp->if_ioctl = rtwn_ioctl; 357 ifp->if_start = rtwn_start; 358 ifp->if_watchdog = rtwn_watchdog; 359 IFQ_SET_READY(&ifp->if_snd); 360 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 361 362 error = if_initialize(ifp); 363 if (error != 0) { 364 ifp->if_softc = NULL; /* For rtwn_detach() */ 365 aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n", 366 error); 367 goto fail; 368 } 369 ieee80211_ifattach(ic); 370 /* Use common softint-based if_input */ 371 ifp->if_percpuq = if_percpuq_create(ifp); 372 if_register(ifp); 373 374 /* override default methods */ 375 ic->ic_newassoc = rtwn_newassoc; 376 ic->ic_reset = rtwn_reset; 377 ic->ic_wme.wme_update = rtwn_wme_update; 378 379 /* Override state transition machine. */ 380 sc->sc_newstate = ic->ic_newstate; 381 ic->ic_newstate = rtwn_newstate; 382 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 383 384 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 385 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 386 &sc->sc_drvbpf); 387 388 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 391 392 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 394 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 395 396 ieee80211_announce(ic); 397 398 if (!pmf_device_register(self, NULL, NULL)) 399 aprint_error_dev(self, "couldn't establish power handler\n"); 400 401 return; 402 403 fail: 404 rtwn_detach(self, 0); 405 } 406 407 static int 408 rtwn_detach(device_t self, int flags) 409 { 410 struct rtwn_softc *sc = device_private(self); 411 struct ieee80211com *ic = &sc->sc_ic; 412 struct ifnet *ifp = GET_IFP(sc); 413 int s, i; 414 415 callout_stop(&sc->scan_to); 416 callout_stop(&sc->calib_to); 417 418 s = splnet(); 419 420 if (ifp->if_softc != NULL) { 421 rtwn_stop(ifp, 0); 422 423 pmf_device_deregister(self); 424 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 425 bpf_detach(ifp); 426 ieee80211_ifdetach(ic); 427 if_detach(ifp); 428 } 429 430 /* Free Tx/Rx buffers. */ 431 for (i = 0; i < RTWN_NTXQUEUES; i++) 432 rtwn_free_tx_list(sc, i); 433 rtwn_free_rx_list(sc); 434 435 splx(s); 436 437 callout_destroy(&sc->scan_to); 438 callout_destroy(&sc->calib_to); 439 440 if (sc->init_task != NULL) 441 softint_disestablish(sc->init_task); 442 if (sc->sc_soft_ih != NULL) 443 softint_disestablish(sc->sc_soft_ih); 444 445 if (sc->sc_ih != NULL) { 446 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 447 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 448 } 449 450 return 0; 451 } 452 453 static int 454 rtwn_activate(device_t self, enum devact act) 455 { 456 struct rtwn_softc *sc = device_private(self); 457 struct ifnet *ifp = GET_IFP(sc); 458 459 switch (act) { 460 case DVACT_DEACTIVATE: 461 if (ifp->if_flags & IFF_RUNNING) 462 rtwn_stop(ifp, 0); 463 return 0; 464 default: 465 return EOPNOTSUPP; 466 } 467 } 468 469 static void 470 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc_pci *desc, 471 bus_addr_t addr, size_t len, int idx) 472 { 473 474 memset(desc, 0, sizeof(*desc)); 475 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 476 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 477 desc->rxbufaddr = htole32(addr); 478 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 479 BUS_SPACE_BARRIER_WRITE); 480 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 481 } 482 483 static int 484 rtwn_alloc_rx_list(struct rtwn_softc *sc) 485 { 486 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 487 struct rtwn_rx_data *rx_data; 488 const size_t size = sizeof(struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT; 489 int i, error = 0; 490 491 /* Allocate Rx descriptors. */ 492 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 493 &rx_ring->map); 494 if (error != 0) { 495 aprint_error_dev(sc->sc_dev, 496 "could not create rx desc DMA map\n"); 497 rx_ring->map = NULL; 498 goto fail; 499 } 500 501 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 502 &rx_ring->nsegs, BUS_DMA_NOWAIT); 503 if (error != 0) { 504 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 505 goto fail; 506 } 507 508 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 509 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 510 if (error != 0) { 511 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 512 rx_ring->desc = NULL; 513 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 514 goto fail; 515 } 516 memset(rx_ring->desc, 0, size); 517 518 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 519 1, size, BUS_DMA_NOWAIT); 520 if (error != 0) { 521 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 522 goto fail; 523 } 524 525 /* Allocate Rx buffers. */ 526 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 527 rx_data = &rx_ring->rx_data[i]; 528 529 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 530 0, BUS_DMA_NOWAIT, &rx_data->map); 531 if (error != 0) { 532 aprint_error_dev(sc->sc_dev, 533 "could not create rx buf DMA map\n"); 534 goto fail; 535 } 536 537 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 538 if (__predict_false(rx_data->m == NULL)) { 539 aprint_error_dev(sc->sc_dev, 540 "couldn't allocate rx mbuf\n"); 541 error = ENOMEM; 542 goto fail; 543 } 544 MCLGET(rx_data->m, M_DONTWAIT); 545 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 546 aprint_error_dev(sc->sc_dev, 547 "couldn't allocate rx mbuf cluster\n"); 548 m_free(rx_data->m); 549 rx_data->m = NULL; 550 error = ENOMEM; 551 goto fail; 552 } 553 554 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 555 mtod(rx_data->m, void *), MCLBYTES, NULL, 556 BUS_DMA_NOWAIT | BUS_DMA_READ); 557 if (error != 0) { 558 aprint_error_dev(sc->sc_dev, 559 "could not load rx buf DMA map\n"); 560 goto fail; 561 } 562 563 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 564 BUS_DMASYNC_PREREAD); 565 566 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 567 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 568 } 569 fail: if (error != 0) 570 rtwn_free_rx_list(sc); 571 return error; 572 } 573 574 static void 575 rtwn_reset_rx_list(struct rtwn_softc *sc) 576 { 577 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 578 struct rtwn_rx_data *rx_data; 579 int i; 580 581 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 582 rx_data = &rx_ring->rx_data[i]; 583 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 584 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 585 } 586 } 587 588 static void 589 rtwn_free_rx_list(struct rtwn_softc *sc) 590 { 591 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 592 struct rtwn_rx_data *rx_data; 593 int i, s; 594 595 s = splnet(); 596 597 if (rx_ring->map) { 598 if (rx_ring->desc) { 599 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 600 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 601 sizeof (struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT); 602 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 603 rx_ring->nsegs); 604 rx_ring->desc = NULL; 605 } 606 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 607 rx_ring->map = NULL; 608 } 609 610 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 611 rx_data = &rx_ring->rx_data[i]; 612 613 if (rx_data->m != NULL) { 614 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 615 m_freem(rx_data->m); 616 rx_data->m = NULL; 617 } 618 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 619 rx_data->map = NULL; 620 } 621 622 splx(s); 623 } 624 625 static int 626 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 627 { 628 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 629 struct rtwn_tx_data *tx_data; 630 const size_t size = sizeof(struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT; 631 int i = 0, error = 0; 632 633 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 634 &tx_ring->map); 635 if (error != 0) { 636 aprint_error_dev(sc->sc_dev, 637 "could not create tx ring DMA map\n"); 638 goto fail; 639 } 640 641 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 642 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 643 if (error != 0) { 644 aprint_error_dev(sc->sc_dev, 645 "could not allocate tx ring DMA memory\n"); 646 goto fail; 647 } 648 649 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 650 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 651 if (error != 0) { 652 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 653 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 654 goto fail; 655 } 656 memset(tx_ring->desc, 0, size); 657 658 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 659 size, NULL, BUS_DMA_NOWAIT); 660 if (error != 0) { 661 aprint_error_dev(sc->sc_dev, 662 "could not load tx ring DMA map\n"); 663 goto fail; 664 } 665 666 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 667 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i]; 668 669 /* setup tx desc */ 670 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 671 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 672 673 tx_data = &tx_ring->tx_data[i]; 674 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 675 0, BUS_DMA_NOWAIT, &tx_data->map); 676 if (error != 0) { 677 aprint_error_dev(sc->sc_dev, 678 "could not create tx buf DMA map\n"); 679 goto fail; 680 } 681 tx_data->m = NULL; 682 tx_data->ni = NULL; 683 } 684 685 fail: 686 if (error != 0) 687 rtwn_free_tx_list(sc, qid); 688 return error; 689 } 690 691 static void 692 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 693 { 694 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 695 int i; 696 697 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 698 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i]; 699 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 700 701 memset(desc, 0, sizeof(*desc) - 702 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 703 sizeof(desc->nextdescaddr))); 704 705 if (tx_data->m != NULL) { 706 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 707 m_freem(tx_data->m); 708 tx_data->m = NULL; 709 ieee80211_free_node(tx_data->ni); 710 tx_data->ni = NULL; 711 } 712 } 713 714 sc->qfullmsk &= ~(1 << qid); 715 tx_ring->queued = 0; 716 tx_ring->cur = 0; 717 } 718 719 static void 720 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 721 { 722 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 723 struct rtwn_tx_data *tx_data; 724 int i; 725 726 if (tx_ring->map != NULL) { 727 if (tx_ring->desc != NULL) { 728 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 729 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 730 sizeof (struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT); 731 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 732 tx_ring->nsegs); 733 } 734 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 735 } 736 737 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 738 tx_data = &tx_ring->tx_data[i]; 739 740 if (tx_data->m != NULL) { 741 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 742 m_freem(tx_data->m); 743 tx_data->m = NULL; 744 } 745 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 746 } 747 748 sc->qfullmsk &= ~(1 << qid); 749 tx_ring->queued = 0; 750 tx_ring->cur = 0; 751 } 752 753 static void 754 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 755 { 756 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 757 } 758 759 static void 760 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 761 { 762 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 763 } 764 765 static void 766 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 767 { 768 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 769 } 770 771 static uint8_t 772 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 773 { 774 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 775 } 776 777 static uint16_t 778 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 779 { 780 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 781 } 782 783 static uint32_t 784 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 785 { 786 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 787 } 788 789 static int 790 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 791 { 792 struct r92c_fw_cmd cmd; 793 uint8_t *cp; 794 int fwcur; 795 int ntries; 796 797 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 798 device_xname(sc->sc_dev), __func__, id, buf, len)); 799 800 fwcur = sc->fwcur; 801 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 802 803 /* Wait for current FW box to be empty. */ 804 for (ntries = 0; ntries < 100; ntries++) { 805 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 806 break; 807 DELAY(1); 808 } 809 if (ntries == 100) { 810 aprint_error_dev(sc->sc_dev, 811 "could not send firmware command %d\n", id); 812 return ETIMEDOUT; 813 } 814 815 memset(&cmd, 0, sizeof(cmd)); 816 KASSERT(len <= sizeof(cmd.msg)); 817 memcpy(cmd.msg, buf, len); 818 819 /* Write the first word last since that will trigger the FW. */ 820 cp = (uint8_t *)&cmd; 821 if (len >= 4) { 822 cmd.id = id | R92C_CMD_FLAG_EXT; 823 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 824 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 825 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 826 } else { 827 cmd.id = id; 828 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 829 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 830 } 831 832 /* Give firmware some time for processing. */ 833 DELAY(2000); 834 835 return 0; 836 } 837 838 static void 839 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 840 { 841 842 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 843 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 844 } 845 846 static uint32_t 847 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 848 { 849 uint32_t reg[R92C_MAX_CHAINS], val; 850 851 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 852 if (chain != 0) 853 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 854 855 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 856 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 857 DELAY(1000); 858 859 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 860 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 861 R92C_HSSI_PARAM2_READ_EDGE); 862 DELAY(1000); 863 864 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 865 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 866 DELAY(1000); 867 868 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 869 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 870 else 871 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 872 return MS(val, R92C_LSSI_READBACK_DATA); 873 } 874 875 static int 876 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 877 { 878 int ntries; 879 880 rtwn_write_4(sc, R92C_LLT_INIT, 881 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 882 SM(R92C_LLT_INIT_ADDR, addr) | 883 SM(R92C_LLT_INIT_DATA, data)); 884 /* Wait for write operation to complete. */ 885 for (ntries = 0; ntries < 20; ntries++) { 886 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 887 R92C_LLT_INIT_OP_NO_ACTIVE) 888 return 0; 889 DELAY(5); 890 } 891 return ETIMEDOUT; 892 } 893 894 static uint8_t 895 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 896 { 897 uint32_t reg; 898 int ntries; 899 900 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 901 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 902 reg &= ~R92C_EFUSE_CTRL_VALID; 903 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 904 /* Wait for read operation to complete. */ 905 for (ntries = 0; ntries < 100; ntries++) { 906 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 907 if (reg & R92C_EFUSE_CTRL_VALID) 908 return MS(reg, R92C_EFUSE_CTRL_DATA); 909 DELAY(5); 910 } 911 aprint_error_dev(sc->sc_dev, 912 "could not read efuse byte at address 0x%x\n", addr); 913 return 0xff; 914 } 915 916 static void 917 rtwn_efuse_read(struct rtwn_softc *sc) 918 { 919 uint8_t *rom = (uint8_t *)&sc->rom; 920 uint32_t reg; 921 uint16_t addr = 0; 922 uint8_t off, msk; 923 int i; 924 925 rtwn_efuse_switch_power(sc); 926 927 memset(&sc->rom, 0xff, sizeof(sc->rom)); 928 while (addr < 512) { 929 reg = rtwn_efuse_read_1(sc, addr); 930 if (reg == 0xff) 931 break; 932 addr++; 933 off = reg >> 4; 934 msk = reg & 0xf; 935 for (i = 0; i < 4; i++) { 936 if (msk & (1 << i)) 937 continue; 938 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 939 addr++; 940 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 941 addr++; 942 } 943 } 944 #ifdef RTWN_DEBUG 945 if (rtwn_debug >= 2) { 946 /* Dump ROM content. */ 947 printf("\n"); 948 for (i = 0; i < sizeof(sc->rom); i++) 949 printf("%02x:", rom[i]); 950 printf("\n"); 951 } 952 #endif 953 } 954 955 static void 956 rtwn_efuse_switch_power(struct rtwn_softc *sc) 957 { 958 uint32_t reg; 959 960 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 961 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 962 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 963 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 964 } 965 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 966 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 967 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 968 reg | R92C_SYS_FUNC_EN_ELDR); 969 } 970 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 971 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 972 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 973 rtwn_write_2(sc, R92C_SYS_CLKR, 974 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 975 } 976 } 977 978 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 979 static int 980 rtwn_read_chipid(struct rtwn_softc *sc) 981 { 982 uint32_t reg; 983 984 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 985 986 reg = rtwn_read_4(sc, R92C_SYS_CFG); 987 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 988 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 989 /* Unsupported test chip. */ 990 return EIO; 991 992 if (reg & R92C_SYS_CFG_TYPE_92C) { 993 sc->chip |= RTWN_CHIP_92C; 994 /* Check if it is a castrated 8192C. */ 995 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 996 R92C_HPON_FSM_CHIP_BONDING_ID) == 997 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 998 sc->chip |= RTWN_CHIP_92C_1T2R; 999 } 1000 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1001 sc->chip |= RTWN_CHIP_UMC; 1002 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1003 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1004 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 1005 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 1006 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 1007 else 1008 /* Unsupported unknown chip. */ 1009 return EIO; 1010 } 1011 return 0; 1012 } 1013 1014 static void 1015 rtwn_read_rom(struct rtwn_softc *sc) 1016 { 1017 struct ieee80211com *ic = &sc->sc_ic; 1018 struct r92c_rom *rom = &sc->rom; 1019 1020 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1021 1022 /* Read full ROM image. */ 1023 rtwn_efuse_read(sc); 1024 1025 if (rom->id != 0x8129) { 1026 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1027 rom->id); 1028 } 1029 1030 /* XXX Weird but this is what the vendor driver does. */ 1031 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1032 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1033 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1034 1035 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1036 sc->pa_setting, sc->board_type, sc->regulatory)); 1037 1038 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1039 } 1040 1041 static int 1042 rtwn_media_change(struct ifnet *ifp) 1043 { 1044 int error; 1045 1046 error = ieee80211_media_change(ifp); 1047 if (error != ENETRESET) 1048 return error; 1049 1050 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1051 (IFF_UP | IFF_RUNNING)) { 1052 rtwn_stop(ifp, 0); 1053 error = rtwn_init(ifp); 1054 } 1055 return error; 1056 } 1057 1058 /* 1059 * Initialize rate adaptation in firmware. 1060 */ 1061 static int 1062 rtwn_ra_init(struct rtwn_softc *sc) 1063 { 1064 static const uint8_t map[] = { 1065 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1066 }; 1067 struct ieee80211com *ic = &sc->sc_ic; 1068 struct ieee80211_node *ni = ic->ic_bss; 1069 struct ieee80211_rateset *rs = &ni->ni_rates; 1070 struct r92c_fw_cmd_macid_cfg cmd; 1071 uint32_t rates, basicrates; 1072 uint8_t mode; 1073 int maxrate, maxbasicrate, error, i, j; 1074 1075 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1076 1077 /* Get normal and basic rates mask. */ 1078 rates = basicrates = 0; 1079 maxrate = maxbasicrate = 0; 1080 for (i = 0; i < rs->rs_nrates; i++) { 1081 /* Convert 802.11 rate to HW rate index. */ 1082 for (j = 0; j < __arraycount(map); j++) 1083 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1084 break; 1085 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1086 continue; 1087 rates |= 1 << j; 1088 if (j > maxrate) 1089 maxrate = j; 1090 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1091 basicrates |= 1 << j; 1092 if (j > maxbasicrate) 1093 maxbasicrate = j; 1094 } 1095 } 1096 if (ic->ic_curmode == IEEE80211_MODE_11B) 1097 mode = R92C_RAID_11B; 1098 else 1099 mode = R92C_RAID_11BG; 1100 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1101 device_xname(sc->sc_dev), mode, rates, basicrates)); 1102 if (basicrates == 0) 1103 basicrates |= 1; /* add 1Mbps */ 1104 1105 /* Set rates mask for group addressed frames. */ 1106 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1107 cmd.mask = htole32((mode << 28) | basicrates); 1108 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1109 if (error != 0) { 1110 aprint_error_dev(sc->sc_dev, 1111 "could not add broadcast station\n"); 1112 return error; 1113 } 1114 /* Set initial MRR rate. */ 1115 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1116 maxbasicrate)); 1117 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1118 1119 /* Set rates mask for unicast frames. */ 1120 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1121 cmd.mask = htole32((mode << 28) | rates); 1122 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1123 if (error != 0) { 1124 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1125 return error; 1126 } 1127 /* Set initial MRR rate. */ 1128 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1129 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1130 1131 /* Configure Automatic Rate Fallback Register. */ 1132 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1133 if (rates & 0x0c) 1134 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1135 else 1136 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1137 } else 1138 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1139 1140 /* Indicate highest supported rate. */ 1141 ni->ni_txrate = rs->rs_nrates - 1; 1142 return 0; 1143 } 1144 1145 static int 1146 rtwn_get_nettype(struct rtwn_softc *sc) 1147 { 1148 struct ieee80211com *ic = &sc->sc_ic; 1149 int type; 1150 1151 switch (ic->ic_opmode) { 1152 case IEEE80211_M_STA: 1153 type = R92C_CR_NETTYPE_INFRA; 1154 break; 1155 1156 case IEEE80211_M_HOSTAP: 1157 type = R92C_CR_NETTYPE_AP; 1158 break; 1159 1160 case IEEE80211_M_IBSS: 1161 type = R92C_CR_NETTYPE_ADHOC; 1162 break; 1163 1164 default: 1165 type = R92C_CR_NETTYPE_NOLINK; 1166 break; 1167 } 1168 1169 return type; 1170 } 1171 1172 static void 1173 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1174 { 1175 uint32_t reg; 1176 1177 reg = rtwn_read_4(sc, R92C_CR); 1178 reg = RW(reg, R92C_CR_NETTYPE, type); 1179 rtwn_write_4(sc, R92C_CR, reg); 1180 } 1181 1182 static void 1183 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1184 { 1185 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1186 uint64_t tsf; 1187 1188 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1189 1190 /* Enable TSF synchronization. */ 1191 rtwn_write_1(sc, R92C_BCN_CTRL, 1192 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1193 1194 rtwn_write_1(sc, R92C_BCN_CTRL, 1195 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1196 1197 /* Set initial TSF. */ 1198 tsf = ni->ni_tstamp.tsf; 1199 tsf = le64toh(tsf); 1200 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1201 tsf -= IEEE80211_DUR_TU; 1202 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1203 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1204 1205 rtwn_write_1(sc, R92C_BCN_CTRL, 1206 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1207 } 1208 1209 static void 1210 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1211 { 1212 uint8_t reg; 1213 1214 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1215 1216 if (led == RTWN_LED_LINK) { 1217 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1218 if (!on) 1219 reg |= R92C_LEDCFG2_DIS; 1220 else 1221 reg |= R92C_LEDCFG2_EN; 1222 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1223 sc->ledlink = on; /* Save LED state. */ 1224 } 1225 } 1226 1227 static void 1228 rtwn_calib_to(void *arg) 1229 { 1230 struct rtwn_softc *sc = arg; 1231 struct r92c_fw_cmd_rssi cmd; 1232 int s; 1233 1234 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1235 1236 s = splnet(); 1237 1238 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1239 goto restart_timer; 1240 1241 if (sc->avg_pwdb != -1) { 1242 /* Indicate Rx signal strength to FW for rate adaptation. */ 1243 memset(&cmd, 0, sizeof(cmd)); 1244 cmd.macid = 0; /* BSS. */ 1245 cmd.pwdb = sc->avg_pwdb; 1246 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1247 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1248 } 1249 1250 /* Do temperature compensation. */ 1251 rtwn_temp_calib(sc); 1252 1253 restart_timer: 1254 callout_schedule(&sc->calib_to, mstohz(2000)); 1255 1256 splx(s); 1257 } 1258 1259 static void 1260 rtwn_next_scan(void *arg) 1261 { 1262 struct rtwn_softc *sc = arg; 1263 struct ieee80211com *ic = &sc->sc_ic; 1264 int s; 1265 1266 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1267 1268 s = splnet(); 1269 if (ic->ic_state == IEEE80211_S_SCAN) 1270 ieee80211_next_scan(ic); 1271 splx(s); 1272 } 1273 1274 static void 1275 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1276 { 1277 1278 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1279 1280 /* start with lowest Tx rate */ 1281 ni->ni_txrate = 0; 1282 } 1283 1284 static int 1285 rtwn_reset(struct ifnet *ifp) 1286 { 1287 struct rtwn_softc *sc = ifp->if_softc; 1288 struct ieee80211com *ic = &sc->sc_ic; 1289 1290 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1291 return ENETRESET; 1292 1293 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1294 1295 return 0; 1296 } 1297 1298 static int 1299 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1300 { 1301 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1302 struct ieee80211_node *ni; 1303 enum ieee80211_state ostate = ic->ic_state; 1304 uint32_t reg; 1305 int s; 1306 1307 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1308 1309 s = splnet(); 1310 1311 callout_stop(&sc->scan_to); 1312 callout_stop(&sc->calib_to); 1313 1314 if (ostate != nstate) { 1315 DPRINTF(("%s: %s -> %s\n", __func__, 1316 ieee80211_state_name[ostate], 1317 ieee80211_state_name[nstate])); 1318 } 1319 1320 switch (ostate) { 1321 case IEEE80211_S_INIT: 1322 break; 1323 1324 case IEEE80211_S_SCAN: 1325 if (nstate != IEEE80211_S_SCAN) { 1326 /* 1327 * End of scanning 1328 */ 1329 /* flush 4-AC Queue after site_survey */ 1330 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1331 1332 /* Allow Rx from our BSSID only. */ 1333 rtwn_write_4(sc, R92C_RCR, 1334 rtwn_read_4(sc, R92C_RCR) | 1335 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1336 } 1337 break; 1338 1339 case IEEE80211_S_AUTH: 1340 case IEEE80211_S_ASSOC: 1341 break; 1342 1343 case IEEE80211_S_RUN: 1344 /* Turn link LED off. */ 1345 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1346 1347 /* Set media status to 'No Link'. */ 1348 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1349 1350 /* Stop Rx of data frames. */ 1351 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1352 1353 /* Rest TSF. */ 1354 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1355 1356 /* Disable TSF synchronization. */ 1357 rtwn_write_1(sc, R92C_BCN_CTRL, 1358 rtwn_read_1(sc, R92C_BCN_CTRL) | 1359 R92C_BCN_CTRL_DIS_TSF_UDT0); 1360 1361 /* Back to 20MHz mode */ 1362 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1363 1364 /* Reset EDCA parameters. */ 1365 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1366 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1367 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1368 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1369 1370 /* flush all cam entries */ 1371 rtwn_cam_init(sc); 1372 break; 1373 } 1374 1375 switch (nstate) { 1376 case IEEE80211_S_INIT: 1377 /* Turn link LED off. */ 1378 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1379 break; 1380 1381 case IEEE80211_S_SCAN: 1382 if (ostate != IEEE80211_S_SCAN) { 1383 /* 1384 * Begin of scanning 1385 */ 1386 1387 /* Set gain for scanning. */ 1388 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1389 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1390 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1391 1392 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1393 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1394 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1395 1396 /* Allow Rx from any BSSID. */ 1397 rtwn_write_4(sc, R92C_RCR, 1398 rtwn_read_4(sc, R92C_RCR) & 1399 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1400 1401 /* Stop Rx of data frames. */ 1402 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1403 1404 /* Disable update TSF */ 1405 rtwn_write_1(sc, R92C_BCN_CTRL, 1406 rtwn_read_1(sc, R92C_BCN_CTRL) | 1407 R92C_BCN_CTRL_DIS_TSF_UDT0); 1408 } 1409 1410 /* Make link LED blink during scan. */ 1411 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1412 1413 /* Pause AC Tx queues. */ 1414 rtwn_write_1(sc, R92C_TXPAUSE, 1415 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1416 1417 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1418 1419 /* Start periodic scan. */ 1420 callout_schedule(&sc->scan_to, mstohz(200)); 1421 break; 1422 1423 case IEEE80211_S_AUTH: 1424 /* Set initial gain under link. */ 1425 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1426 #ifdef doaslinux 1427 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1428 #else 1429 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1430 #endif 1431 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1432 1433 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1434 #ifdef doaslinux 1435 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1436 #else 1437 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1438 #endif 1439 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1440 1441 /* Set media status to 'No Link'. */ 1442 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1443 1444 /* Allow Rx from any BSSID. */ 1445 rtwn_write_4(sc, R92C_RCR, 1446 rtwn_read_4(sc, R92C_RCR) & 1447 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1448 1449 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1450 break; 1451 1452 case IEEE80211_S_ASSOC: 1453 break; 1454 1455 case IEEE80211_S_RUN: 1456 ni = ic->ic_bss; 1457 1458 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1459 1460 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1461 /* Back to 20Mhz mode */ 1462 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1463 1464 /* Set media status to 'No Link'. */ 1465 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1466 1467 /* Enable Rx of data frames. */ 1468 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1469 1470 /* Allow Rx from any BSSID. */ 1471 rtwn_write_4(sc, R92C_RCR, 1472 rtwn_read_4(sc, R92C_RCR) & 1473 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1474 1475 /* Accept Rx data/control/management frames */ 1476 rtwn_write_4(sc, R92C_RCR, 1477 rtwn_read_4(sc, R92C_RCR) | 1478 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1479 1480 /* Turn link LED on. */ 1481 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1482 break; 1483 } 1484 1485 /* Set media status to 'Associated'. */ 1486 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1487 1488 /* Set BSSID. */ 1489 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1490 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1491 1492 if (ic->ic_curmode == IEEE80211_MODE_11B) 1493 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1494 else /* 802.11b/g */ 1495 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1496 1497 /* Enable Rx of data frames. */ 1498 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1499 1500 /* Flush all AC queues. */ 1501 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1502 1503 /* Set beacon interval. */ 1504 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1505 1506 switch (ic->ic_opmode) { 1507 case IEEE80211_M_STA: 1508 /* Allow Rx from our BSSID only. */ 1509 rtwn_write_4(sc, R92C_RCR, 1510 rtwn_read_4(sc, R92C_RCR) | 1511 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1512 1513 /* Enable TSF synchronization. */ 1514 rtwn_tsf_sync_enable(sc); 1515 break; 1516 1517 case IEEE80211_M_HOSTAP: 1518 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1519 1520 /* Allow Rx from any BSSID. */ 1521 rtwn_write_4(sc, R92C_RCR, 1522 rtwn_read_4(sc, R92C_RCR) & 1523 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1524 1525 /* Reset TSF timer to zero. */ 1526 reg = rtwn_read_4(sc, R92C_TCR); 1527 reg &= ~0x01; 1528 rtwn_write_4(sc, R92C_TCR, reg); 1529 reg |= 0x01; 1530 rtwn_write_4(sc, R92C_TCR, reg); 1531 break; 1532 1533 case IEEE80211_M_MONITOR: 1534 default: 1535 break; 1536 } 1537 1538 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1539 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1540 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1541 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1542 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1543 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1544 1545 /* Initialize rate adaptation. */ 1546 rtwn_ra_init(sc); 1547 1548 /* Turn link LED on. */ 1549 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1550 1551 /* Reset average RSSI. */ 1552 sc->avg_pwdb = -1; 1553 1554 /* Reset temperature calibration state machine. */ 1555 sc->thcal_state = 0; 1556 sc->thcal_lctemp = 0; 1557 1558 /* Start periodic calibration. */ 1559 callout_schedule(&sc->calib_to, mstohz(2000)); 1560 break; 1561 } 1562 1563 (void)sc->sc_newstate(ic, nstate, arg); 1564 1565 splx(s); 1566 1567 return 0; 1568 } 1569 1570 static int 1571 rtwn_wme_update(struct ieee80211com *ic) 1572 { 1573 static const uint16_t aci2reg[WME_NUM_AC] = { 1574 R92C_EDCA_BE_PARAM, 1575 R92C_EDCA_BK_PARAM, 1576 R92C_EDCA_VI_PARAM, 1577 R92C_EDCA_VO_PARAM 1578 }; 1579 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1580 const struct wmeParams *wmep; 1581 int s, aci, aifs, slottime; 1582 1583 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1584 1585 s = splnet(); 1586 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1587 for (aci = 0; aci < WME_NUM_AC; aci++) { 1588 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1589 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1590 aifs = wmep->wmep_aifsn * slottime + 10; 1591 rtwn_write_4(sc, aci2reg[aci], 1592 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1593 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1594 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1595 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1596 } 1597 splx(s); 1598 1599 return 0; 1600 } 1601 1602 static void 1603 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1604 { 1605 int pwdb; 1606 1607 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1608 1609 /* Convert antenna signal to percentage. */ 1610 if (rssi <= -100 || rssi >= 20) 1611 pwdb = 0; 1612 else if (rssi >= 0) 1613 pwdb = 100; 1614 else 1615 pwdb = 100 + rssi; 1616 if (rate <= 3) { 1617 /* CCK gain is smaller than OFDM/MCS gain. */ 1618 pwdb += 6; 1619 if (pwdb > 100) 1620 pwdb = 100; 1621 if (pwdb <= 14) 1622 pwdb -= 4; 1623 else if (pwdb <= 26) 1624 pwdb -= 8; 1625 else if (pwdb <= 34) 1626 pwdb -= 6; 1627 else if (pwdb <= 42) 1628 pwdb -= 2; 1629 } 1630 if (sc->avg_pwdb == -1) /* Init. */ 1631 sc->avg_pwdb = pwdb; 1632 else if (sc->avg_pwdb < pwdb) 1633 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1634 else 1635 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1636 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1637 } 1638 1639 static int8_t 1640 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1641 { 1642 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1643 struct r92c_rx_phystat *phy; 1644 struct r92c_rx_cck *cck; 1645 uint8_t rpt; 1646 int8_t rssi; 1647 1648 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1649 1650 if (rate <= 3) { 1651 cck = (struct r92c_rx_cck *)physt; 1652 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1653 rpt = (cck->agc_rpt >> 5) & 0x3; 1654 rssi = (cck->agc_rpt & 0x1f) << 1; 1655 } else { 1656 rpt = (cck->agc_rpt >> 6) & 0x3; 1657 rssi = cck->agc_rpt & 0x3e; 1658 } 1659 rssi = cckoff[rpt] - rssi; 1660 } else { /* OFDM/HT. */ 1661 phy = (struct r92c_rx_phystat *)physt; 1662 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1663 } 1664 return rssi; 1665 } 1666 1667 static void 1668 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc_pci *rx_desc, 1669 struct rtwn_rx_data *rx_data, int desc_idx) 1670 { 1671 struct ieee80211com *ic = &sc->sc_ic; 1672 struct ifnet *ifp = IC2IFP(ic); 1673 struct ieee80211_frame *wh; 1674 struct ieee80211_node *ni; 1675 struct r92c_rx_phystat *phy = NULL; 1676 uint32_t rxdw0, rxdw3; 1677 struct mbuf *m, *m1; 1678 uint8_t rate; 1679 int8_t rssi = 0; 1680 int infosz, pktlen, shift, totlen, error, s; 1681 1682 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1683 1684 rxdw0 = le32toh(rx_desc->rxdw0); 1685 rxdw3 = le32toh(rx_desc->rxdw3); 1686 1687 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1688 /* 1689 * This should not happen since we setup our Rx filter 1690 * to not receive these frames. 1691 */ 1692 if_statinc(ifp, if_ierrors); 1693 return; 1694 } 1695 1696 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1697 /* 1698 * XXX: This will drop most control packets. Do we really 1699 * want this in IEEE80211_M_MONITOR mode? 1700 */ 1701 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1702 ic->ic_stats.is_rx_tooshort++; 1703 if_statinc(ifp, if_ierrors); 1704 return; 1705 } 1706 if (__predict_false(pktlen > MCLBYTES)) { 1707 if_statinc(ifp, if_ierrors); 1708 return; 1709 } 1710 1711 rate = MS(rxdw3, R92C_RXDW3_RATE); 1712 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1713 if (infosz > sizeof(struct r92c_rx_phystat)) 1714 infosz = sizeof(struct r92c_rx_phystat); 1715 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1716 totlen = pktlen + infosz + shift; 1717 1718 /* Get RSSI from PHY status descriptor if present. */ 1719 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1720 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1721 rssi = rtwn_get_rssi(sc, rate, phy); 1722 /* Update our average RSSI. */ 1723 rtwn_update_avgrssi(sc, rate, rssi); 1724 } 1725 1726 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1727 pktlen, rate, infosz, shift, rssi)); 1728 1729 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1730 if (__predict_false(m1 == NULL)) { 1731 ic->ic_stats.is_rx_nobuf++; 1732 if_statinc(ifp, if_ierrors); 1733 return; 1734 } 1735 MCLGET(m1, M_DONTWAIT); 1736 if (__predict_false(!(m1->m_flags & M_EXT))) { 1737 m_freem(m1); 1738 ic->ic_stats.is_rx_nobuf++; 1739 if_statinc(ifp, if_ierrors); 1740 return; 1741 } 1742 1743 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1744 BUS_DMASYNC_POSTREAD); 1745 1746 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1747 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1748 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1749 if (error != 0) { 1750 m_freem(m1); 1751 1752 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1753 rx_data->m, BUS_DMA_NOWAIT)) 1754 panic("%s: could not load old RX mbuf", 1755 device_xname(sc->sc_dev)); 1756 1757 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1758 BUS_DMASYNC_PREREAD); 1759 1760 /* Physical address may have changed. */ 1761 rtwn_setup_rx_desc(sc, rx_desc, 1762 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1763 1764 if_statinc(ifp, if_ierrors); 1765 return; 1766 } 1767 1768 /* Finalize mbuf. */ 1769 m = rx_data->m; 1770 rx_data->m = m1; 1771 m->m_pkthdr.len = m->m_len = totlen; 1772 m_set_rcvif(m, ifp); 1773 1774 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1775 BUS_DMASYNC_PREREAD); 1776 1777 /* Update RX descriptor. */ 1778 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1779 MCLBYTES, desc_idx); 1780 1781 /* Get ieee80211 frame header. */ 1782 if (rxdw0 & R92C_RXDW0_PHYST) 1783 m_adj(m, infosz + shift); 1784 else 1785 m_adj(m, shift); 1786 wh = mtod(m, struct ieee80211_frame *); 1787 1788 s = splnet(); 1789 1790 if (__predict_false(sc->sc_drvbpf != NULL)) { 1791 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1792 1793 tap->wr_flags = 0; 1794 /* Map HW rate index to 802.11 rate. */ 1795 tap->wr_flags = 2; 1796 if (!(rxdw3 & R92C_RXDW3_HT)) { 1797 switch (rate) { 1798 /* CCK. */ 1799 case 0: tap->wr_rate = 2; break; 1800 case 1: tap->wr_rate = 4; break; 1801 case 2: tap->wr_rate = 11; break; 1802 case 3: tap->wr_rate = 22; break; 1803 /* OFDM. */ 1804 case 4: tap->wr_rate = 12; break; 1805 case 5: tap->wr_rate = 18; break; 1806 case 6: tap->wr_rate = 24; break; 1807 case 7: tap->wr_rate = 36; break; 1808 case 8: tap->wr_rate = 48; break; 1809 case 9: tap->wr_rate = 72; break; 1810 case 10: tap->wr_rate = 96; break; 1811 case 11: tap->wr_rate = 108; break; 1812 } 1813 } else if (rate >= 12) { /* MCS0~15. */ 1814 /* Bit 7 set means HT MCS instead of rate. */ 1815 tap->wr_rate = 0x80 | (rate - 12); 1816 } 1817 tap->wr_dbm_antsignal = rssi; 1818 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1819 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1820 1821 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1822 } 1823 1824 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1825 1826 /* push the frame up to the 802.11 stack */ 1827 ieee80211_input(ic, m, ni, rssi, 0); 1828 1829 /* Node is no longer needed. */ 1830 ieee80211_free_node(ni); 1831 1832 splx(s); 1833 } 1834 1835 static int 1836 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1837 { 1838 struct ieee80211com *ic = &sc->sc_ic; 1839 struct ieee80211_frame *wh; 1840 struct ieee80211_key *k = NULL; 1841 struct rtwn_tx_ring *tx_ring; 1842 struct rtwn_tx_data *data; 1843 struct r92c_tx_desc_pci *txd; 1844 uint16_t qos, seq; 1845 uint8_t raid, type, tid, qid; 1846 int hasqos, error; 1847 1848 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1849 1850 wh = mtod(m, struct ieee80211_frame *); 1851 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1852 1853 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1854 k = ieee80211_crypto_encap(ic, ni, m); 1855 if (k == NULL) 1856 return ENOBUFS; 1857 1858 wh = mtod(m, struct ieee80211_frame *); 1859 } 1860 1861 if ((hasqos = ieee80211_has_qos(wh))) { 1862 /* data frames in 11n mode */ 1863 qos = ieee80211_get_qos(wh); 1864 tid = qos & IEEE80211_QOS_TID; 1865 qid = TID_TO_WME_AC(tid); 1866 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1867 /* Use AC_VO for management frames. */ 1868 tid = 0; /* compiler happy */ 1869 qid = RTWN_VO_QUEUE; 1870 } else { 1871 /* non-qos data frames */ 1872 tid = R92C_TXDW1_QSEL_BE; 1873 qid = RTWN_BE_QUEUE; 1874 } 1875 1876 /* Grab a Tx buffer from the ring. */ 1877 tx_ring = &sc->tx_ring[qid]; 1878 data = &tx_ring->tx_data[tx_ring->cur]; 1879 if (data->m != NULL) { 1880 m_freem(m); 1881 return ENOBUFS; 1882 } 1883 1884 /* Fill Tx descriptor. */ 1885 txd = &tx_ring->desc[tx_ring->cur]; 1886 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1887 m_freem(m); 1888 return ENOBUFS; 1889 } 1890 1891 txd->txdw0 = htole32( 1892 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1893 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1894 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1895 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1896 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1897 1898 txd->txdw1 = 0; 1899 txd->txdw4 = 0; 1900 txd->txdw5 = 0; 1901 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1902 type == IEEE80211_FC0_TYPE_DATA) { 1903 if (ic->ic_curmode == IEEE80211_MODE_11B) 1904 raid = R92C_RAID_11B; 1905 else 1906 raid = R92C_RAID_11BG; 1907 1908 txd->txdw1 |= htole32( 1909 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1910 SM(R92C_TXDW1_QSEL, tid) | 1911 SM(R92C_TXDW1_RAID, raid) | 1912 R92C_TXDW1_AGGBK); 1913 1914 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1915 /* for 11g */ 1916 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1917 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1918 R92C_TXDW4_HWRTSEN); 1919 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1920 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1921 R92C_TXDW4_HWRTSEN); 1922 } 1923 } 1924 /* Send RTS at OFDM24. */ 1925 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1926 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1927 /* Send data at OFDM54. */ 1928 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1929 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1930 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1931 txd->txdw1 |= htole32( 1932 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1933 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1934 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1935 1936 /* Force CCK1. */ 1937 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1938 /* Use 1Mbps */ 1939 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1940 } else { 1941 txd->txdw1 |= htole32( 1942 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1943 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1944 1945 /* Force CCK1. */ 1946 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1947 /* Use 1Mbps */ 1948 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1949 } 1950 1951 /* Set sequence number (already little endian). */ 1952 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1953 txd->txdseq = htole16(seq); 1954 1955 if (!hasqos) { 1956 /* Use HW sequence numbering for non-QoS frames. */ 1957 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1958 txd->txdseq |= htole16(0x8000); /* WTF? */ 1959 } else 1960 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1961 1962 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1963 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1964 if (error && error != EFBIG) { 1965 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1966 error); 1967 m_freem(m); 1968 return error; 1969 } 1970 if (error != 0) { 1971 /* Too many DMA segments, linearize mbuf. */ 1972 struct mbuf *newm = m_defrag(m, M_DONTWAIT); 1973 if (newm == NULL) { 1974 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1975 m_freem(m); 1976 return ENOBUFS; 1977 } 1978 m = newm; 1979 1980 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1981 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1982 if (error != 0) { 1983 aprint_error_dev(sc->sc_dev, 1984 "can't map mbuf (error %d)\n", error); 1985 m_freem(m); 1986 return error; 1987 } 1988 } 1989 1990 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1991 txd->txbufsize = htole16(m->m_pkthdr.len); 1992 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1993 BUS_SPACE_BARRIER_WRITE); 1994 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1995 1996 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1997 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1998 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1999 BUS_DMASYNC_PREWRITE); 2000 2001 data->m = m; 2002 data->ni = ni; 2003 2004 if (__predict_false(sc->sc_drvbpf != NULL)) { 2005 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 2006 2007 tap->wt_flags = 0; 2008 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2009 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2010 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2011 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2012 2013 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2014 } 2015 2016 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2017 tx_ring->queued++; 2018 2019 if (tx_ring->queued > RTWN_TX_LIST_HIMARK) 2020 sc->qfullmsk |= (1 << qid); 2021 2022 /* Kick TX. */ 2023 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2024 2025 return 0; 2026 } 2027 2028 static void 2029 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2030 { 2031 struct ieee80211com *ic = &sc->sc_ic; 2032 struct ifnet *ifp = IC2IFP(ic); 2033 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2034 struct rtwn_tx_data *tx_data; 2035 struct r92c_tx_desc_pci *tx_desc; 2036 int i, s; 2037 2038 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2039 qid)); 2040 2041 s = splnet(); 2042 2043 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2044 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2046 2047 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2048 tx_data = &tx_ring->tx_data[i]; 2049 if (tx_data->m == NULL) 2050 continue; 2051 2052 tx_desc = &tx_ring->desc[i]; 2053 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2054 continue; 2055 2056 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2057 m_freem(tx_data->m); 2058 tx_data->m = NULL; 2059 ieee80211_free_node(tx_data->ni); 2060 tx_data->ni = NULL; 2061 2062 if_statinc(ifp, if_opackets); 2063 sc->sc_tx_timer = 0; 2064 tx_ring->queued--; 2065 } 2066 2067 if (tx_ring->queued < RTWN_TX_LIST_LOMARK) 2068 sc->qfullmsk &= ~(1 << qid); 2069 2070 splx(s); 2071 } 2072 2073 static void 2074 rtwn_start(struct ifnet *ifp) 2075 { 2076 struct rtwn_softc *sc = ifp->if_softc; 2077 struct ieee80211com *ic = &sc->sc_ic; 2078 struct ether_header *eh; 2079 struct ieee80211_node *ni; 2080 struct mbuf *m; 2081 2082 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2083 return; 2084 2085 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2086 2087 for (;;) { 2088 if (sc->qfullmsk != 0) { 2089 ifp->if_flags |= IFF_OACTIVE; 2090 break; 2091 } 2092 /* Send pending management frames first. */ 2093 IF_DEQUEUE(&ic->ic_mgtq, m); 2094 if (m != NULL) { 2095 ni = M_GETCTX(m, struct ieee80211_node *); 2096 M_CLEARCTX(m); 2097 goto sendit; 2098 } 2099 if (ic->ic_state != IEEE80211_S_RUN) 2100 break; 2101 2102 /* Encapsulate and send data frames. */ 2103 IFQ_DEQUEUE(&ifp->if_snd, m); 2104 if (m == NULL) 2105 break; 2106 2107 if (m->m_len < (int)sizeof(*eh) && 2108 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2109 if_statinc(ifp, if_oerrors); 2110 continue; 2111 } 2112 eh = mtod(m, struct ether_header *); 2113 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2114 if (ni == NULL) { 2115 m_freem(m); 2116 if_statinc(ifp, if_oerrors); 2117 continue; 2118 } 2119 2120 bpf_mtap(ifp, m, BPF_D_OUT); 2121 2122 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2123 ieee80211_free_node(ni); 2124 if_statinc(ifp, if_oerrors); 2125 continue; 2126 } 2127 sendit: 2128 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2129 2130 if (rtwn_tx(sc, m, ni) != 0) { 2131 ieee80211_free_node(ni); 2132 if_statinc(ifp, if_oerrors); 2133 continue; 2134 } 2135 2136 sc->sc_tx_timer = 5; 2137 ifp->if_timer = 1; 2138 } 2139 2140 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2141 } 2142 2143 static void 2144 rtwn_watchdog(struct ifnet *ifp) 2145 { 2146 struct rtwn_softc *sc = ifp->if_softc; 2147 struct ieee80211com *ic = &sc->sc_ic; 2148 2149 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2150 2151 ifp->if_timer = 0; 2152 2153 if (sc->sc_tx_timer > 0) { 2154 if (--sc->sc_tx_timer == 0) { 2155 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2156 softint_schedule(sc->init_task); 2157 if_statinc(ifp, if_oerrors); 2158 return; 2159 } 2160 ifp->if_timer = 1; 2161 } 2162 ieee80211_watchdog(ic); 2163 } 2164 2165 static int 2166 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2167 { 2168 struct rtwn_softc *sc = ifp->if_softc; 2169 struct ieee80211com *ic = &sc->sc_ic; 2170 int s, error = 0; 2171 2172 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2173 __func__, cmd, data)); 2174 2175 s = splnet(); 2176 2177 switch (cmd) { 2178 case SIOCSIFFLAGS: 2179 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2180 break; 2181 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2182 case IFF_UP | IFF_RUNNING: 2183 break; 2184 case IFF_UP: 2185 error = rtwn_init(ifp); 2186 if (error != 0) 2187 ifp->if_flags &= ~IFF_UP; 2188 break; 2189 case IFF_RUNNING: 2190 rtwn_stop(ifp, 1); 2191 break; 2192 case 0: 2193 break; 2194 } 2195 break; 2196 2197 case SIOCADDMULTI: 2198 case SIOCDELMULTI: 2199 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2200 /* setup multicast filter, etc */ 2201 error = 0; 2202 } 2203 break; 2204 2205 case SIOCS80211CHANNEL: 2206 error = ieee80211_ioctl(ic, cmd, data); 2207 if (error == ENETRESET && 2208 ic->ic_opmode == IEEE80211_M_MONITOR) { 2209 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2210 (IFF_UP | IFF_RUNNING)) { 2211 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2212 } 2213 error = 0; 2214 } 2215 break; 2216 2217 default: 2218 error = ieee80211_ioctl(ic, cmd, data); 2219 break; 2220 } 2221 2222 if (error == ENETRESET) { 2223 error = 0; 2224 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2225 (IFF_UP | IFF_RUNNING)) { 2226 rtwn_stop(ifp, 0); 2227 error = rtwn_init(ifp); 2228 } 2229 } 2230 2231 splx(s); 2232 2233 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2234 error)); 2235 2236 return error; 2237 } 2238 2239 static int 2240 rtwn_power_on(struct rtwn_softc *sc) 2241 { 2242 uint32_t reg; 2243 int ntries; 2244 2245 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2246 2247 /* Wait for autoload done bit. */ 2248 for (ntries = 0; ntries < 1000; ntries++) { 2249 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2250 break; 2251 DELAY(5); 2252 } 2253 if (ntries == 1000) { 2254 aprint_error_dev(sc->sc_dev, 2255 "timeout waiting for chip autoload\n"); 2256 return ETIMEDOUT; 2257 } 2258 2259 /* Unlock ISO/CLK/Power control register. */ 2260 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2261 2262 /* TODO: check if we need this for 8188CE */ 2263 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2264 /* bt coex */ 2265 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2266 reg |= (R92C_APS_FSMCO_SOP_ABG | 2267 R92C_APS_FSMCO_SOP_AMB | 2268 R92C_APS_FSMCO_XOP_BTCK); 2269 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2270 } 2271 2272 /* Move SPS into PWM mode. */ 2273 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2274 DELAY(100); 2275 2276 /* Set low byte to 0x0f, leave others unchanged. */ 2277 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2278 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2279 2280 /* TODO: check if we need this for 8188CE */ 2281 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2282 /* bt coex */ 2283 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2284 reg &= ~0x00024800; /* XXX magic from linux */ 2285 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2286 } 2287 2288 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2289 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2290 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2291 DELAY(200); 2292 2293 /* TODO: linux does additional btcoex stuff here */ 2294 2295 /* Auto enable WLAN. */ 2296 rtwn_write_2(sc, R92C_APS_FSMCO, 2297 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2298 for (ntries = 0; ntries < 1000; ntries++) { 2299 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2300 R92C_APS_FSMCO_APFM_ONMAC)) 2301 break; 2302 DELAY(5); 2303 } 2304 if (ntries == 1000) { 2305 aprint_error_dev(sc->sc_dev, 2306 "timeout waiting for MAC auto ON\n"); 2307 return ETIMEDOUT; 2308 } 2309 2310 /* Enable radio, GPIO and LED functions. */ 2311 rtwn_write_2(sc, R92C_APS_FSMCO, 2312 R92C_APS_FSMCO_AFSM_PCIE | 2313 R92C_APS_FSMCO_PDN_EN | 2314 R92C_APS_FSMCO_PFM_ALDN); 2315 2316 /* Release RF digital isolation. */ 2317 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2318 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2319 2320 if (sc->chip & RTWN_CHIP_92C) 2321 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2322 else 2323 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2324 2325 rtwn_write_4(sc, R92C_INT_MIG, 0); 2326 2327 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2328 /* bt coex */ 2329 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2330 reg &= 0xfd; /* XXX magic from linux */ 2331 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2332 } 2333 2334 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2335 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2336 2337 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2338 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2339 aprint_error_dev(sc->sc_dev, 2340 "radio is disabled by hardware switch\n"); 2341 return EPERM; /* :-) */ 2342 } 2343 2344 /* Initialize MAC. */ 2345 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2346 rtwn_write_1(sc, R92C_APSD_CTRL, 2347 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2348 for (ntries = 0; ntries < 200; ntries++) { 2349 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2350 R92C_APSD_CTRL_OFF_STATUS)) 2351 break; 2352 DELAY(500); 2353 } 2354 if (ntries == 200) { 2355 aprint_error_dev(sc->sc_dev, 2356 "timeout waiting for MAC initialization\n"); 2357 return ETIMEDOUT; 2358 } 2359 2360 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2361 reg = rtwn_read_2(sc, R92C_CR); 2362 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2363 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2364 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2365 R92C_CR_ENSEC; 2366 rtwn_write_2(sc, R92C_CR, reg); 2367 2368 rtwn_write_1(sc, 0xfe10, 0x19); 2369 2370 return 0; 2371 } 2372 2373 static int 2374 rtwn_llt_init(struct rtwn_softc *sc) 2375 { 2376 int i, error; 2377 2378 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2379 2380 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2381 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2382 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2383 return error; 2384 } 2385 /* NB: 0xff indicates end-of-list. */ 2386 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2387 return error; 2388 /* 2389 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2390 * as ring buffer. 2391 */ 2392 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2393 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2394 return error; 2395 } 2396 /* Make the last page point to the beginning of the ring buffer. */ 2397 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2398 return error; 2399 } 2400 2401 static void 2402 rtwn_fw_reset(struct rtwn_softc *sc) 2403 { 2404 uint16_t reg; 2405 int ntries; 2406 2407 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2408 2409 /* Tell 8051 to reset itself. */ 2410 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2411 2412 /* Wait until 8051 resets by itself. */ 2413 for (ntries = 0; ntries < 100; ntries++) { 2414 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2415 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2416 goto sleep; 2417 DELAY(50); 2418 } 2419 /* Force 8051 reset. */ 2420 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2421 sleep: 2422 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2423 #if 0 2424 /* 2425 * We must sleep for one second to let the firmware settle. 2426 * Accessing registers too early will hang the whole system. 2427 */ 2428 tsleep(®, 0, "rtwnrst", hz); 2429 #else 2430 DELAY(1000 * 1000); 2431 #endif 2432 } 2433 2434 static int 2435 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2436 { 2437 uint32_t reg; 2438 int off, mlen, error = 0, i; 2439 2440 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2441 2442 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2443 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2444 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2445 2446 DELAY(5); 2447 2448 off = R92C_FW_START_ADDR; 2449 while (len > 0) { 2450 if (len > 196) 2451 mlen = 196; 2452 else if (len > 4) 2453 mlen = 4; 2454 else 2455 mlen = 1; 2456 for (i = 0; i < mlen; i++) 2457 rtwn_write_1(sc, off++, buf[i]); 2458 buf += mlen; 2459 len -= mlen; 2460 } 2461 2462 return error; 2463 } 2464 2465 static int 2466 rtwn_load_firmware(struct rtwn_softc *sc) 2467 { 2468 firmware_handle_t fwh; 2469 const struct r92c_fw_hdr *hdr; 2470 const char *name; 2471 u_char *fw, *ptr; 2472 size_t len; 2473 uint32_t reg; 2474 int mlen, ntries, page, error; 2475 2476 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2477 2478 /* Read firmware image from the filesystem. */ 2479 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2480 RTWN_CHIP_UMC_A_CUT) 2481 name = "rtl8192cfwU.bin"; 2482 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2483 name = "rtl8192cfwU_B.bin"; 2484 else 2485 name = "rtl8192cfw.bin"; 2486 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2487 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2488 aprint_error_dev(sc->sc_dev, 2489 "could not read firmware %s (error %d)\n", name, error); 2490 return error; 2491 } 2492 const size_t fwlen = len = firmware_get_size(fwh); 2493 fw = firmware_malloc(len); 2494 if (fw == NULL) { 2495 aprint_error_dev(sc->sc_dev, 2496 "failed to allocate firmware memory (size=%zu)\n", len); 2497 firmware_close(fwh); 2498 return ENOMEM; 2499 } 2500 error = firmware_read(fwh, 0, fw, len); 2501 firmware_close(fwh); 2502 if (error != 0) { 2503 aprint_error_dev(sc->sc_dev, 2504 "failed to read firmware (error %d)\n", error); 2505 firmware_free(fw, fwlen); 2506 return error; 2507 } 2508 2509 if (len < sizeof(*hdr)) { 2510 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2511 error = EINVAL; 2512 goto fail; 2513 } 2514 ptr = fw; 2515 hdr = (const struct r92c_fw_hdr *)ptr; 2516 /* Check if there is a valid FW header and skip it. */ 2517 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2518 (le16toh(hdr->signature) >> 4) == 0x92c) { 2519 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2520 le16toh(hdr->version), le16toh(hdr->subversion), 2521 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2522 ptr += sizeof(*hdr); 2523 len -= sizeof(*hdr); 2524 } 2525 2526 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2527 rtwn_fw_reset(sc); 2528 2529 /* Enable FW download. */ 2530 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2531 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2532 R92C_SYS_FUNC_EN_CPUEN); 2533 rtwn_write_1(sc, R92C_MCUFWDL, 2534 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2535 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2536 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2537 2538 /* Reset the FWDL checksum. */ 2539 rtwn_write_1(sc, R92C_MCUFWDL, 2540 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2541 2542 /* download firmware */ 2543 for (page = 0; len > 0; page++) { 2544 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2545 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2546 if (error != 0) { 2547 aprint_error_dev(sc->sc_dev, 2548 "could not load firmware page %d\n", page); 2549 goto fail; 2550 } 2551 ptr += mlen; 2552 len -= mlen; 2553 } 2554 2555 /* Disable FW download. */ 2556 rtwn_write_1(sc, R92C_MCUFWDL, 2557 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2558 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2559 2560 /* Wait for checksum report. */ 2561 for (ntries = 0; ntries < 1000; ntries++) { 2562 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2563 break; 2564 DELAY(5); 2565 } 2566 if (ntries == 1000) { 2567 aprint_error_dev(sc->sc_dev, 2568 "timeout waiting for checksum report\n"); 2569 error = ETIMEDOUT; 2570 goto fail; 2571 } 2572 2573 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2574 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2575 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2576 2577 /* Wait for firmware readiness. */ 2578 for (ntries = 0; ntries < 1000; ntries++) { 2579 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2580 break; 2581 DELAY(5); 2582 } 2583 if (ntries == 1000) { 2584 aprint_error_dev(sc->sc_dev, 2585 "timeout waiting for firmware readiness\n"); 2586 error = ETIMEDOUT; 2587 goto fail; 2588 } 2589 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2590 2591 fail: 2592 firmware_free(fw, fwlen); 2593 return error; 2594 } 2595 2596 static int 2597 rtwn_dma_init(struct rtwn_softc *sc) 2598 { 2599 uint32_t reg; 2600 int error; 2601 2602 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2603 2604 /* Initialize LLT table. */ 2605 error = rtwn_llt_init(sc); 2606 if (error != 0) 2607 return error; 2608 2609 /* Set number of pages for normal priority queue. */ 2610 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2611 rtwn_write_4(sc, R92C_RQPN, 2612 /* Set number of pages for public queue. */ 2613 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2614 /* Set number of pages for high priority queue. */ 2615 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2616 /* Set number of pages for low priority queue. */ 2617 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2618 /* Load values. */ 2619 R92C_RQPN_LD); 2620 2621 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2622 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2623 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2624 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2625 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2626 2627 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2628 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2629 reg |= 0xF771; 2630 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2631 2632 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2633 2634 /* Configure Tx DMA. */ 2635 rtwn_write_4(sc, R92C_BKQ_DESA, 2636 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2637 rtwn_write_4(sc, R92C_BEQ_DESA, 2638 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2639 rtwn_write_4(sc, R92C_VIQ_DESA, 2640 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2641 rtwn_write_4(sc, R92C_VOQ_DESA, 2642 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2643 rtwn_write_4(sc, R92C_BCNQ_DESA, 2644 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2645 rtwn_write_4(sc, R92C_MGQ_DESA, 2646 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2647 rtwn_write_4(sc, R92C_HQ_DESA, 2648 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2649 2650 /* Configure Rx DMA. */ 2651 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2652 2653 /* Set Tx/Rx transfer page boundary. */ 2654 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2655 2656 /* Set Tx/Rx transfer page size. */ 2657 rtwn_write_1(sc, R92C_PBP, 2658 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2659 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2660 return 0; 2661 } 2662 2663 static void 2664 rtwn_mac_init(struct rtwn_softc *sc) 2665 { 2666 int i; 2667 2668 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2669 2670 /* Write MAC initialization values. */ 2671 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2672 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2673 } 2674 2675 static void 2676 rtwn_bb_init(struct rtwn_softc *sc) 2677 { 2678 const struct rtwn_bb_prog *prog; 2679 uint32_t reg; 2680 int i; 2681 2682 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2683 2684 /* Enable BB and RF. */ 2685 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2686 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2687 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2688 R92C_SYS_FUNC_EN_DIO_RF); 2689 2690 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2691 2692 rtwn_write_1(sc, R92C_RF_CTRL, 2693 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2694 2695 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2696 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2697 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2698 R92C_SYS_FUNC_EN_BBRSTB); 2699 2700 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2701 2702 rtwn_write_4(sc, R92C_LEDCFG0, 2703 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2704 2705 /* Select BB programming. */ 2706 prog = (sc->chip & RTWN_CHIP_92C) ? 2707 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2708 2709 /* Write BB initialization values. */ 2710 for (i = 0; i < prog->count; i++) { 2711 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2712 DELAY(1); 2713 } 2714 2715 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2716 /* 8192C 1T only configuration. */ 2717 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2718 reg = (reg & ~0x00000003) | 0x2; 2719 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2720 2721 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2722 reg = (reg & ~0x00300033) | 0x00200022; 2723 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2724 2725 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2726 reg = (reg & ~0xff000000) | 0x45 << 24; 2727 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2728 2729 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2730 reg = (reg & ~0x000000ff) | 0x23; 2731 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2732 2733 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2734 reg = (reg & ~0x00000030) | 1 << 4; 2735 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2736 2737 reg = rtwn_bb_read(sc, 0xe74); 2738 reg = (reg & ~0x0c000000) | 2 << 26; 2739 rtwn_bb_write(sc, 0xe74, reg); 2740 reg = rtwn_bb_read(sc, 0xe78); 2741 reg = (reg & ~0x0c000000) | 2 << 26; 2742 rtwn_bb_write(sc, 0xe78, reg); 2743 reg = rtwn_bb_read(sc, 0xe7c); 2744 reg = (reg & ~0x0c000000) | 2 << 26; 2745 rtwn_bb_write(sc, 0xe7c, reg); 2746 reg = rtwn_bb_read(sc, 0xe80); 2747 reg = (reg & ~0x0c000000) | 2 << 26; 2748 rtwn_bb_write(sc, 0xe80, reg); 2749 reg = rtwn_bb_read(sc, 0xe88); 2750 reg = (reg & ~0x0c000000) | 2 << 26; 2751 rtwn_bb_write(sc, 0xe88, reg); 2752 } 2753 2754 /* Write AGC values. */ 2755 for (i = 0; i < prog->agccount; i++) { 2756 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2757 prog->agcvals[i]); 2758 DELAY(1); 2759 } 2760 2761 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2762 R92C_HSSI_PARAM2_CCK_HIPWR) 2763 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2764 } 2765 2766 static void 2767 rtwn_rf_init(struct rtwn_softc *sc) 2768 { 2769 const struct rtwn_rf_prog *prog; 2770 uint32_t reg, type; 2771 int i, j, idx, off; 2772 2773 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2774 2775 /* Select RF programming based on board type. */ 2776 if (!(sc->chip & RTWN_CHIP_92C)) { 2777 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2778 prog = rtl8188ce_rf_prog; 2779 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2780 prog = rtl8188ru_rf_prog; 2781 else 2782 prog = rtl8188cu_rf_prog; 2783 } else 2784 prog = rtl8192ce_rf_prog; 2785 2786 for (i = 0; i < sc->nrxchains; i++) { 2787 /* Save RF_ENV control type. */ 2788 idx = i / 2; 2789 off = (i % 2) * 16; 2790 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2791 type = (reg >> off) & 0x10; 2792 2793 /* Set RF_ENV enable. */ 2794 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2795 reg |= 0x100000; 2796 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2797 DELAY(1); 2798 /* Set RF_ENV output high. */ 2799 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2800 reg |= 0x10; 2801 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2802 DELAY(1); 2803 /* Set address and data lengths of RF registers. */ 2804 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2805 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2806 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2807 DELAY(1); 2808 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2809 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2810 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2811 DELAY(1); 2812 2813 /* Write RF initialization values for this chain. */ 2814 for (j = 0; j < prog[i].count; j++) { 2815 if (prog[i].regs[j] >= 0xf9 && 2816 prog[i].regs[j] <= 0xfe) { 2817 /* 2818 * These are fake RF registers offsets that 2819 * indicate a delay is required. 2820 */ 2821 DELAY(50); 2822 continue; 2823 } 2824 rtwn_rf_write(sc, i, prog[i].regs[j], 2825 prog[i].vals[j]); 2826 DELAY(1); 2827 } 2828 2829 /* Restore RF_ENV control type. */ 2830 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2831 reg &= ~(0x10 << off) | (type << off); 2832 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2833 2834 /* Cache RF register CHNLBW. */ 2835 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2836 } 2837 2838 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2839 RTWN_CHIP_UMC_A_CUT) { 2840 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2841 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2842 } 2843 } 2844 2845 static void 2846 rtwn_cam_init(struct rtwn_softc *sc) 2847 { 2848 2849 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2850 2851 /* Invalidate all CAM entries. */ 2852 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2853 } 2854 2855 static void 2856 rtwn_pa_bias_init(struct rtwn_softc *sc) 2857 { 2858 uint8_t reg; 2859 int i; 2860 2861 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2862 2863 for (i = 0; i < sc->nrxchains; i++) { 2864 if (sc->pa_setting & (1 << i)) 2865 continue; 2866 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2867 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2868 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2869 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2870 } 2871 if (!(sc->pa_setting & 0x10)) { 2872 reg = rtwn_read_1(sc, 0x16); 2873 reg = (reg & ~0xf0) | 0x90; 2874 rtwn_write_1(sc, 0x16, reg); 2875 } 2876 } 2877 2878 static void 2879 rtwn_rxfilter_init(struct rtwn_softc *sc) 2880 { 2881 2882 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2883 2884 /* Initialize Rx filter. */ 2885 /* TODO: use better filter for monitor mode. */ 2886 rtwn_write_4(sc, R92C_RCR, 2887 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2888 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2889 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2890 /* Accept all multicast frames. */ 2891 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2892 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2893 /* Accept all management frames. */ 2894 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2895 /* Reject all control frames. */ 2896 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2897 /* Accept all data frames. */ 2898 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2899 } 2900 2901 static void 2902 rtwn_edca_init(struct rtwn_softc *sc) 2903 { 2904 2905 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2906 2907 /* set spec SIFS (used in NAV) */ 2908 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2909 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2910 2911 /* set SIFS CCK/OFDM */ 2912 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2913 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2914 2915 /* TXOP */ 2916 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2917 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2918 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2919 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2920 } 2921 2922 static void 2923 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2924 uint16_t power[RTWN_RIDX_COUNT]) 2925 { 2926 uint32_t reg; 2927 2928 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2929 2930 /* Write per-CCK rate Tx power. */ 2931 if (chain == 0) { 2932 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2933 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2934 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2935 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2936 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2937 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2938 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2939 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2940 } else { 2941 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2942 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2943 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2944 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2945 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2946 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2947 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2948 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2949 } 2950 /* Write per-OFDM rate Tx power. */ 2951 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2952 SM(R92C_TXAGC_RATE06, power[ 4]) | 2953 SM(R92C_TXAGC_RATE09, power[ 5]) | 2954 SM(R92C_TXAGC_RATE12, power[ 6]) | 2955 SM(R92C_TXAGC_RATE18, power[ 7])); 2956 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2957 SM(R92C_TXAGC_RATE24, power[ 8]) | 2958 SM(R92C_TXAGC_RATE36, power[ 9]) | 2959 SM(R92C_TXAGC_RATE48, power[10]) | 2960 SM(R92C_TXAGC_RATE54, power[11])); 2961 /* Write per-MCS Tx power. */ 2962 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2963 SM(R92C_TXAGC_MCS00, power[12]) | 2964 SM(R92C_TXAGC_MCS01, power[13]) | 2965 SM(R92C_TXAGC_MCS02, power[14]) | 2966 SM(R92C_TXAGC_MCS03, power[15])); 2967 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2968 SM(R92C_TXAGC_MCS04, power[16]) | 2969 SM(R92C_TXAGC_MCS05, power[17]) | 2970 SM(R92C_TXAGC_MCS06, power[18]) | 2971 SM(R92C_TXAGC_MCS07, power[19])); 2972 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2973 SM(R92C_TXAGC_MCS08, power[20]) | 2974 SM(R92C_TXAGC_MCS09, power[21]) | 2975 SM(R92C_TXAGC_MCS10, power[22]) | 2976 SM(R92C_TXAGC_MCS11, power[23])); 2977 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2978 SM(R92C_TXAGC_MCS12, power[24]) | 2979 SM(R92C_TXAGC_MCS13, power[25]) | 2980 SM(R92C_TXAGC_MCS14, power[26]) | 2981 SM(R92C_TXAGC_MCS15, power[27])); 2982 } 2983 2984 static void 2985 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2986 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2987 uint16_t power[RTWN_RIDX_COUNT]) 2988 { 2989 struct ieee80211com *ic = &sc->sc_ic; 2990 struct r92c_rom *rom = &sc->rom; 2991 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2992 const struct rtwn_txpwr *base; 2993 int ridx, chan, group; 2994 2995 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2996 2997 /* Determine channel group. */ 2998 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2999 if (chan <= 3) 3000 group = 0; 3001 else if (chan <= 9) 3002 group = 1; 3003 else 3004 group = 2; 3005 3006 /* Get original Tx power based on board type and RF chain. */ 3007 if (!(sc->chip & RTWN_CHIP_92C)) { 3008 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 3009 base = &rtl8188ru_txagc[chain]; 3010 else 3011 base = &rtl8192cu_txagc[chain]; 3012 } else 3013 base = &rtl8192cu_txagc[chain]; 3014 3015 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 3016 if (sc->regulatory == 0) { 3017 for (ridx = 0; ridx <= 3; ridx++) 3018 power[ridx] = base->pwr[0][ridx]; 3019 } 3020 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3021 if (sc->regulatory == 3) { 3022 power[ridx] = base->pwr[0][ridx]; 3023 /* Apply vendor limits. */ 3024 if (extc != NULL) 3025 maxpwr = rom->ht40_max_pwr[group]; 3026 else 3027 maxpwr = rom->ht20_max_pwr[group]; 3028 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 3029 if (power[ridx] > maxpwr) 3030 power[ridx] = maxpwr; 3031 } else if (sc->regulatory == 1) { 3032 if (extc == NULL) 3033 power[ridx] = base->pwr[group][ridx]; 3034 } else if (sc->regulatory != 2) 3035 power[ridx] = base->pwr[0][ridx]; 3036 } 3037 3038 /* Compute per-CCK rate Tx power. */ 3039 cckpow = rom->cck_tx_pwr[chain][group]; 3040 for (ridx = 0; ridx <= 3; ridx++) { 3041 power[ridx] += cckpow; 3042 if (power[ridx] > R92C_MAX_TX_PWR) 3043 power[ridx] = R92C_MAX_TX_PWR; 3044 } 3045 3046 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3047 if (sc->ntxchains > 1) { 3048 /* Apply reduction for 2 spatial streams. */ 3049 diff = rom->ht40_2s_tx_pwr_diff[group]; 3050 diff = (diff >> (chain * 4)) & 0xf; 3051 htpow = (htpow > diff) ? htpow - diff : 0; 3052 } 3053 3054 /* Compute per-OFDM rate Tx power. */ 3055 diff = rom->ofdm_tx_pwr_diff[group]; 3056 diff = (diff >> (chain * 4)) & 0xf; 3057 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3058 for (ridx = 4; ridx <= 11; ridx++) { 3059 power[ridx] += ofdmpow; 3060 if (power[ridx] > R92C_MAX_TX_PWR) 3061 power[ridx] = R92C_MAX_TX_PWR; 3062 } 3063 3064 /* Compute per-MCS Tx power. */ 3065 if (extc == NULL) { 3066 diff = rom->ht20_tx_pwr_diff[group]; 3067 diff = (diff >> (chain * 4)) & 0xf; 3068 htpow += diff; /* HT40->HT20 correction. */ 3069 } 3070 for (ridx = 12; ridx <= 27; ridx++) { 3071 power[ridx] += htpow; 3072 if (power[ridx] > R92C_MAX_TX_PWR) 3073 power[ridx] = R92C_MAX_TX_PWR; 3074 } 3075 #ifdef RTWN_DEBUG 3076 if (rtwn_debug >= 4) { 3077 /* Dump per-rate Tx power values. */ 3078 printf("Tx power for chain %d:\n", chain); 3079 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3080 printf("Rate %d = %u\n", ridx, power[ridx]); 3081 } 3082 #endif 3083 } 3084 3085 static void 3086 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3087 struct ieee80211_channel *extc) 3088 { 3089 uint16_t power[RTWN_RIDX_COUNT]; 3090 int i; 3091 3092 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3093 3094 for (i = 0; i < sc->ntxchains; i++) { 3095 /* Compute per-rate Tx power values. */ 3096 rtwn_get_txpower(sc, i, c, extc, power); 3097 /* Write per-rate Tx power values to hardware. */ 3098 rtwn_write_txpower(sc, i, power); 3099 } 3100 } 3101 3102 static void 3103 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3104 struct ieee80211_channel *extc) 3105 { 3106 struct ieee80211com *ic = &sc->sc_ic; 3107 u_int chan; 3108 int i; 3109 3110 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3111 3112 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3113 3114 /* Set Tx power for this new channel. */ 3115 rtwn_set_txpower(sc, c, extc); 3116 3117 for (i = 0; i < sc->nrxchains; i++) { 3118 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3119 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3120 } 3121 #ifndef IEEE80211_NO_HT 3122 if (extc != NULL) { 3123 uint32_t reg; 3124 3125 /* Is secondary channel below or above primary? */ 3126 int prichlo = c->ic_freq < extc->ic_freq; 3127 3128 rtwn_write_1(sc, R92C_BWOPMODE, 3129 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3130 3131 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3132 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3133 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3134 3135 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3136 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3137 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3138 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3139 3140 /* Set CCK side band. */ 3141 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3142 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3143 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3144 3145 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3146 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3147 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3148 3149 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3150 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3151 ~R92C_FPGA0_ANAPARAM2_CBW20); 3152 3153 reg = rtwn_bb_read(sc, 0x818); 3154 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3155 rtwn_bb_write(sc, 0x818, reg); 3156 3157 /* Select 40MHz bandwidth. */ 3158 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3159 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3160 } else 3161 #endif 3162 { 3163 rtwn_write_1(sc, R92C_BWOPMODE, 3164 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3165 3166 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3167 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3168 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3169 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3170 3171 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3172 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3173 R92C_FPGA0_ANAPARAM2_CBW20); 3174 3175 /* Select 20MHz bandwidth. */ 3176 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3177 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3178 } 3179 } 3180 3181 static void 3182 rtwn_iq_calib(struct rtwn_softc *sc) 3183 { 3184 3185 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3186 3187 /* XXX */ 3188 } 3189 3190 static void 3191 rtwn_lc_calib(struct rtwn_softc *sc) 3192 { 3193 uint32_t rf_ac[2]; 3194 uint8_t txmode; 3195 int i; 3196 3197 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3198 3199 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3200 if ((txmode & 0x70) != 0) { 3201 /* Disable all continuous Tx. */ 3202 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3203 3204 /* Set RF mode to standby mode. */ 3205 for (i = 0; i < sc->nrxchains; i++) { 3206 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3207 rtwn_rf_write(sc, i, R92C_RF_AC, 3208 RW(rf_ac[i], R92C_RF_AC_MODE, 3209 R92C_RF_AC_MODE_STANDBY)); 3210 } 3211 } else { 3212 /* Block all Tx queues. */ 3213 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3214 } 3215 /* Start calibration. */ 3216 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3217 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3218 3219 /* Give calibration the time to complete. */ 3220 DELAY(100); 3221 3222 /* Restore configuration. */ 3223 if ((txmode & 0x70) != 0) { 3224 /* Restore Tx mode. */ 3225 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3226 /* Restore RF mode. */ 3227 for (i = 0; i < sc->nrxchains; i++) 3228 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3229 } else { 3230 /* Unblock all Tx queues. */ 3231 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3232 } 3233 } 3234 3235 static void 3236 rtwn_temp_calib(struct rtwn_softc *sc) 3237 { 3238 int temp; 3239 3240 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3241 3242 if (sc->thcal_state == 0) { 3243 /* Start measuring temperature. */ 3244 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3245 sc->thcal_state = 1; 3246 return; 3247 } 3248 sc->thcal_state = 0; 3249 3250 /* Read measured temperature. */ 3251 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3252 if (temp == 0) /* Read failed, skip. */ 3253 return; 3254 DPRINTFN(2, ("temperature=%d\n", temp)); 3255 3256 /* 3257 * Redo IQ and LC calibration if temperature changed significantly 3258 * since last calibration. 3259 */ 3260 if (sc->thcal_lctemp == 0) { 3261 /* First calibration is performed in rtwn_init(). */ 3262 sc->thcal_lctemp = temp; 3263 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3264 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3265 sc->thcal_lctemp, temp)); 3266 rtwn_iq_calib(sc); 3267 rtwn_lc_calib(sc); 3268 /* Record temperature of last calibration. */ 3269 sc->thcal_lctemp = temp; 3270 } 3271 } 3272 3273 static int 3274 rtwn_init(struct ifnet *ifp) 3275 { 3276 struct rtwn_softc *sc = ifp->if_softc; 3277 struct ieee80211com *ic = &sc->sc_ic; 3278 uint32_t reg; 3279 int i, error; 3280 3281 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3282 3283 /* Init firmware commands ring. */ 3284 sc->fwcur = 0; 3285 3286 /* Power on adapter. */ 3287 error = rtwn_power_on(sc); 3288 if (error != 0) { 3289 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3290 goto fail; 3291 } 3292 3293 /* Initialize DMA. */ 3294 error = rtwn_dma_init(sc); 3295 if (error != 0) { 3296 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3297 goto fail; 3298 } 3299 3300 /* Set info size in Rx descriptors (in 64-bit words). */ 3301 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3302 3303 /* Disable interrupts. */ 3304 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3305 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3306 3307 /* Set MAC address. */ 3308 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3309 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3310 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3311 3312 /* Set initial network type. */ 3313 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3314 3315 rtwn_rxfilter_init(sc); 3316 3317 reg = rtwn_read_4(sc, R92C_RRSR); 3318 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3319 rtwn_write_4(sc, R92C_RRSR, reg); 3320 3321 /* Set short/long retry limits. */ 3322 rtwn_write_2(sc, R92C_RL, 3323 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3324 3325 /* Initialize EDCA parameters. */ 3326 rtwn_edca_init(sc); 3327 3328 /* Set data and response automatic rate fallback retry counts. */ 3329 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3330 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3331 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3332 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3333 3334 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3335 3336 /* Set ACK timeout. */ 3337 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3338 3339 /* Initialize beacon parameters. */ 3340 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3341 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3342 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3343 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3344 3345 /* Setup AMPDU aggregation. */ 3346 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3347 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3348 3349 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3350 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3351 3352 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3353 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3354 3355 /* Load 8051 microcode. */ 3356 error = rtwn_load_firmware(sc); 3357 if (error != 0) 3358 goto fail; 3359 3360 /* Initialize MAC/BB/RF blocks. */ 3361 rtwn_mac_init(sc); 3362 rtwn_bb_init(sc); 3363 rtwn_rf_init(sc); 3364 3365 /* Turn CCK and OFDM blocks on. */ 3366 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3367 reg |= R92C_RFMOD_CCK_EN; 3368 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3369 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3370 reg |= R92C_RFMOD_OFDM_EN; 3371 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3372 3373 /* Clear per-station keys table. */ 3374 rtwn_cam_init(sc); 3375 3376 /* Enable hardware sequence numbering. */ 3377 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3378 3379 /* Perform LO and IQ calibrations. */ 3380 rtwn_iq_calib(sc); 3381 /* Perform LC calibration. */ 3382 rtwn_lc_calib(sc); 3383 3384 rtwn_pa_bias_init(sc); 3385 3386 /* Initialize GPIO setting. */ 3387 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3388 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3389 3390 /* Fix for lower temperature. */ 3391 rtwn_write_1(sc, 0x15, 0xe9); 3392 3393 /* Set default channel. */ 3394 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3395 3396 /* Clear pending interrupts. */ 3397 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3398 3399 /* Enable interrupts. */ 3400 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3401 3402 /* We're ready to go. */ 3403 ifp->if_flags &= ~IFF_OACTIVE; 3404 ifp->if_flags |= IFF_RUNNING; 3405 3406 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3407 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3408 else 3409 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3410 3411 return 0; 3412 3413 fail: 3414 rtwn_stop(ifp, 1); 3415 return error; 3416 } 3417 3418 static void 3419 rtwn_init_task(void *arg) 3420 { 3421 struct rtwn_softc *sc = arg; 3422 struct ifnet *ifp = GET_IFP(sc); 3423 int s; 3424 3425 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3426 3427 s = splnet(); 3428 3429 rtwn_stop(ifp, 0); 3430 3431 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3432 rtwn_init(ifp); 3433 3434 splx(s); 3435 } 3436 3437 static void 3438 rtwn_stop(struct ifnet *ifp, int disable) 3439 { 3440 struct rtwn_softc *sc = ifp->if_softc; 3441 struct ieee80211com *ic = &sc->sc_ic; 3442 uint16_t reg; 3443 int s, i; 3444 3445 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3446 3447 sc->sc_tx_timer = 0; 3448 ifp->if_timer = 0; 3449 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3450 3451 callout_stop(&sc->scan_to); 3452 callout_stop(&sc->calib_to); 3453 3454 s = splnet(); 3455 3456 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3457 3458 /* Disable interrupts. */ 3459 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3460 3461 /* Pause MAC TX queue */ 3462 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3463 3464 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3465 3466 /* Reset BB state machine */ 3467 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3468 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3469 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3470 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3471 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3472 3473 reg = rtwn_read_2(sc, R92C_CR); 3474 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3475 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3476 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3477 R92C_CR_ENSEC); 3478 rtwn_write_2(sc, R92C_CR, reg); 3479 3480 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3481 rtwn_fw_reset(sc); 3482 3483 /* Reset MAC and Enable 8051 */ 3484 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3485 3486 /* TODO: linux does additional btcoex stuff here */ 3487 3488 /* Disable AFE PLL */ 3489 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3490 /* Enter PFM mode */ 3491 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3492 /* Gated AFE DIG_CLOCK */ 3493 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3494 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3495 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3496 3497 for (i = 0; i < RTWN_NTXQUEUES; i++) 3498 rtwn_reset_tx_list(sc, i); 3499 rtwn_reset_rx_list(sc); 3500 3501 splx(s); 3502 } 3503 3504 static int 3505 rtwn_intr(void *xsc) 3506 { 3507 struct rtwn_softc *sc = xsc; 3508 uint32_t status; 3509 3510 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3511 return 0; 3512 3513 status = rtwn_read_4(sc, R92C_HISR); 3514 if (status == 0 || status == 0xffffffff) 3515 return 0; 3516 3517 /* Disable interrupts. */ 3518 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3519 3520 softint_schedule(sc->sc_soft_ih); 3521 return 1; 3522 } 3523 3524 static void 3525 rtwn_softintr(void *xsc) 3526 { 3527 struct rtwn_softc *sc = xsc; 3528 uint32_t status; 3529 int i, s; 3530 3531 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3532 return; 3533 3534 status = rtwn_read_4(sc, R92C_HISR); 3535 if (status == 0 || status == 0xffffffff) 3536 goto out; 3537 3538 /* Ack interrupts. */ 3539 rtwn_write_4(sc, R92C_HISR, status); 3540 3541 /* Vendor driver treats RX errors like ROK... */ 3542 if (status & RTWN_INT_ENABLE_RX) { 3543 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3544 struct r92c_rx_desc_pci *rx_desc = &sc->rx_ring.desc[i]; 3545 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3546 3547 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3548 continue; 3549 3550 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3551 } 3552 } 3553 3554 if (status & R92C_IMR_BDOK) 3555 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3556 if (status & R92C_IMR_HIGHDOK) 3557 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3558 if (status & R92C_IMR_MGNTDOK) 3559 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3560 if (status & R92C_IMR_BKDOK) 3561 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3562 if (status & R92C_IMR_BEDOK) 3563 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3564 if (status & R92C_IMR_VIDOK) 3565 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3566 if (status & R92C_IMR_VODOK) 3567 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3568 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3569 struct ifnet *ifp = GET_IFP(sc); 3570 s = splnet(); 3571 ifp->if_flags &= ~IFF_OACTIVE; 3572 rtwn_start(ifp); 3573 splx(s); 3574 } 3575 3576 out: 3577 /* Enable interrupts. */ 3578 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3579 } 3580
Indexes created Thu Oct 02 01:09:59 GMT 2025