if_rtwn.c revision 1.19.10.1
1 /* $NetBSD: if_rtwn.c,v 1.19.10.1 2021/06/17 04:46:29 thorpej Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.19.10.1 2021/06/17 04:46:29 thorpej Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/ic/rtwnreg.h> 63 #include <dev/ic/rtwn_data.h> 64 #include <dev/pci/if_rtwnreg.h> 65 66 #ifdef RTWN_DEBUG 67 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 68 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 69 int rtwn_debug = 0; 70 #else 71 #define DPRINTF(x) 72 #define DPRINTFN(n, x) 73 #endif 74 75 /* 76 * PCI configuration space registers. 77 */ 78 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 79 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 80 81 #define RTWN_INT_ENABLE_TX \ 82 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 83 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 84 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 85 #define RTWN_INT_ENABLE_RX \ 86 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 87 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 88 89 static const struct rtwn_device { 90 pci_vendor_id_t rd_vendor; 91 pci_product_id_t rd_product; 92 } rtwn_devices[] = { 93 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 94 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 95 }; 96 97 static int rtwn_match(device_t, cfdata_t, void *); 98 static void rtwn_attach(device_t, device_t, void *); 99 static int rtwn_detach(device_t, int); 100 static int rtwn_activate(device_t, enum devact); 101 102 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 103 rtwn_attach, rtwn_detach, rtwn_activate); 104 105 static int rtwn_alloc_rx_list(struct rtwn_softc *); 106 static void rtwn_reset_rx_list(struct rtwn_softc *); 107 static void rtwn_free_rx_list(struct rtwn_softc *); 108 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc_pci *, 109 bus_addr_t, size_t, int); 110 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 112 static void rtwn_free_tx_list(struct rtwn_softc *, int); 113 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 114 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 115 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 116 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 117 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 118 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 119 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 120 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 121 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 122 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 123 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 124 static void rtwn_efuse_read(struct rtwn_softc *); 125 static int rtwn_read_chipid(struct rtwn_softc *); 126 static void rtwn_efuse_switch_power(struct rtwn_softc *); 127 static void rtwn_read_rom(struct rtwn_softc *); 128 static int rtwn_media_change(struct ifnet *); 129 static int rtwn_ra_init(struct rtwn_softc *); 130 static int rtwn_get_nettype(struct rtwn_softc *); 131 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 132 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 133 static void rtwn_set_led(struct rtwn_softc *, int, int); 134 static void rtwn_calib_to(void *); 135 static void rtwn_next_scan(void *); 136 static void rtwn_newassoc(struct ieee80211_node *, int); 137 static int rtwn_reset(struct ifnet *); 138 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 139 int); 140 static int rtwn_wme_update(struct ieee80211com *); 141 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 142 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 143 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc_pci *, 144 struct rtwn_rx_data *, int); 145 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 146 struct ieee80211_node *); 147 static void rtwn_tx_done(struct rtwn_softc *, int); 148 static void rtwn_start(struct ifnet *); 149 static void rtwn_watchdog(struct ifnet *); 150 static int rtwn_ioctl(struct ifnet *, u_long, void *); 151 static int rtwn_power_on(struct rtwn_softc *); 152 static int rtwn_llt_init(struct rtwn_softc *); 153 static void rtwn_fw_reset(struct rtwn_softc *); 154 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 155 static int rtwn_load_firmware(struct rtwn_softc *); 156 static int rtwn_dma_init(struct rtwn_softc *); 157 static void rtwn_mac_init(struct rtwn_softc *); 158 static void rtwn_bb_init(struct rtwn_softc *); 159 static void rtwn_rf_init(struct rtwn_softc *); 160 static void rtwn_cam_init(struct rtwn_softc *); 161 static void rtwn_pa_bias_init(struct rtwn_softc *); 162 static void rtwn_rxfilter_init(struct rtwn_softc *); 163 static void rtwn_edca_init(struct rtwn_softc *); 164 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 165 static void rtwn_get_txpower(struct rtwn_softc *, int, 166 struct ieee80211_channel *, struct ieee80211_channel *, 167 uint16_t[]); 168 static void rtwn_set_txpower(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_set_chan(struct rtwn_softc *, 171 struct ieee80211_channel *, struct ieee80211_channel *); 172 static void rtwn_iq_calib(struct rtwn_softc *); 173 static void rtwn_lc_calib(struct rtwn_softc *); 174 static void rtwn_temp_calib(struct rtwn_softc *); 175 static int rtwn_init(struct ifnet *); 176 static void rtwn_init_task(void *); 177 static void rtwn_stop(struct ifnet *, int); 178 static int rtwn_intr(void *); 179 static void rtwn_softintr(void *); 180 181 /* Aliases. */ 182 #define rtwn_bb_write rtwn_write_4 183 #define rtwn_bb_read rtwn_read_4 184 185 static const struct rtwn_device * 186 rtwn_lookup(const struct pci_attach_args *pa) 187 { 188 const struct rtwn_device *rd; 189 int i; 190 191 for (i = 0; i < __arraycount(rtwn_devices); i++) { 192 rd = &rtwn_devices[i]; 193 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 194 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 195 return rd; 196 } 197 return NULL; 198 } 199 200 static int 201 rtwn_match(device_t parent, cfdata_t match, void *aux) 202 { 203 struct pci_attach_args *pa = aux; 204 205 if (rtwn_lookup(pa) != NULL) 206 return 1; 207 return 0; 208 } 209 210 static void 211 rtwn_attach(device_t parent, device_t self, void *aux) 212 { 213 struct rtwn_softc *sc = device_private(self); 214 struct pci_attach_args *pa = aux; 215 struct ieee80211com *ic = &sc->sc_ic; 216 struct ifnet *ifp = GET_IFP(sc); 217 int i, error; 218 pcireg_t memtype; 219 const char *intrstr; 220 char intrbuf[PCI_INTRSTR_LEN]; 221 222 sc->sc_dev = self; 223 sc->sc_dmat = pa->pa_dmat; 224 sc->sc_pc = pa->pa_pc; 225 sc->sc_tag = pa->pa_tag; 226 227 pci_aprint_devinfo(pa, NULL); 228 229 callout_init(&sc->scan_to, 0); 230 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 231 callout_init(&sc->calib_to, 0); 232 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 233 234 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc); 235 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 236 237 /* Power up the device */ 238 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 239 240 /* Map control/status registers. */ 241 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 242 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 243 &sc->sc_sh, NULL, &sc->sc_mapsize); 244 if (error != 0) { 245 aprint_error_dev(self, "can't map mem space\n"); 246 return; 247 } 248 249 /* Install interrupt handler. */ 250 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 251 aprint_error_dev(self, "can't map interrupt\n"); 252 return; 253 } 254 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 255 sizeof(intrbuf)); 256 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 257 rtwn_intr, sc, device_xname(self)); 258 if (sc->sc_ih == NULL) { 259 aprint_error_dev(self, "can't establish interrupt"); 260 if (intrstr != NULL) 261 aprint_error(" at %s", intrstr); 262 aprint_error("\n"); 263 return; 264 } 265 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 266 267 error = rtwn_read_chipid(sc); 268 if (error != 0) { 269 aprint_error_dev(self, "unsupported test or unknown chip\n"); 270 return; 271 } 272 273 /* Disable PCIe Active State Power Management (ASPM). */ 274 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 275 &sc->sc_cap_off, NULL)) { 276 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 277 sc->sc_cap_off + PCIE_LCSR); 278 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 279 pci_conf_write(sc->sc_pc, sc->sc_tag, 280 sc->sc_cap_off + PCIE_LCSR, lcsr); 281 } 282 283 /* Allocate Tx/Rx buffers. */ 284 error = rtwn_alloc_rx_list(sc); 285 if (error != 0) { 286 aprint_error_dev(self, "could not allocate Rx buffers\n"); 287 return; 288 } 289 for (i = 0; i < RTWN_NTXQUEUES; i++) { 290 error = rtwn_alloc_tx_list(sc, i); 291 if (error != 0) { 292 aprint_error_dev(self, 293 "could not allocate Tx buffers\n"); 294 return; 295 } 296 } 297 298 /* Determine number of Tx/Rx chains. */ 299 if (sc->chip & RTWN_CHIP_92C) { 300 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 301 sc->nrxchains = 2; 302 } else { 303 sc->ntxchains = 1; 304 sc->nrxchains = 1; 305 } 306 rtwn_read_rom(sc); 307 308 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 309 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 310 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 311 312 /* 313 * Setup the 802.11 device. 314 */ 315 ic->ic_ifp = ifp; 316 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 317 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 318 ic->ic_state = IEEE80211_S_INIT; 319 320 /* Set device capabilities. */ 321 ic->ic_caps = 322 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 323 IEEE80211_C_IBSS | /* IBSS mode supported */ 324 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 325 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 326 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 327 IEEE80211_C_WME | /* 802.11e */ 328 IEEE80211_C_WPA; /* WPA/RSN. */ 329 330 #ifndef IEEE80211_NO_HT 331 /* Set HT capabilities. */ 332 ic->ic_htcaps = 333 IEEE80211_HTCAP_CBW20_40 | 334 IEEE80211_HTCAP_DSSSCCK40; 335 /* Set supported HT rates. */ 336 for (i = 0; i < sc->nrxchains; i++) 337 ic->ic_sup_mcs[i] = 0xff; 338 #endif 339 340 /* Set supported .11b and .11g rates. */ 341 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 342 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 343 344 /* Set supported .11b and .11g channels (1 through 14). */ 345 for (i = 1; i <= 14; i++) { 346 ic->ic_channels[i].ic_freq = 347 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 348 ic->ic_channels[i].ic_flags = 349 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 350 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 351 } 352 353 ifp->if_softc = sc; 354 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 355 ifp->if_init = rtwn_init; 356 ifp->if_ioctl = rtwn_ioctl; 357 ifp->if_start = rtwn_start; 358 ifp->if_watchdog = rtwn_watchdog; 359 IFQ_SET_READY(&ifp->if_snd); 360 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 361 362 if_initialize(ifp); 363 ieee80211_ifattach(ic); 364 /* Use common softint-based if_input */ 365 ifp->if_percpuq = if_percpuq_create(ifp); 366 if_register(ifp); 367 368 /* override default methods */ 369 ic->ic_newassoc = rtwn_newassoc; 370 ic->ic_reset = rtwn_reset; 371 ic->ic_wme.wme_update = rtwn_wme_update; 372 373 /* Override state transition machine. */ 374 sc->sc_newstate = ic->ic_newstate; 375 ic->ic_newstate = rtwn_newstate; 376 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 377 378 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 379 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 380 &sc->sc_drvbpf); 381 382 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 383 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 384 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 385 386 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 387 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 388 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 389 390 ieee80211_announce(ic); 391 392 if (!pmf_device_register(self, NULL, NULL)) 393 aprint_error_dev(self, "couldn't establish power handler\n"); 394 } 395 396 static int 397 rtwn_detach(device_t self, int flags) 398 { 399 struct rtwn_softc *sc = device_private(self); 400 struct ieee80211com *ic = &sc->sc_ic; 401 struct ifnet *ifp = GET_IFP(sc); 402 int s, i; 403 404 callout_stop(&sc->scan_to); 405 callout_stop(&sc->calib_to); 406 407 s = splnet(); 408 409 if (ifp->if_softc != NULL) { 410 rtwn_stop(ifp, 0); 411 412 pmf_device_deregister(self); 413 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 414 bpf_detach(ifp); 415 ieee80211_ifdetach(ic); 416 if_detach(ifp); 417 } 418 419 /* Free Tx/Rx buffers. */ 420 for (i = 0; i < RTWN_NTXQUEUES; i++) 421 rtwn_free_tx_list(sc, i); 422 rtwn_free_rx_list(sc); 423 424 splx(s); 425 426 callout_destroy(&sc->scan_to); 427 callout_destroy(&sc->calib_to); 428 429 if (sc->init_task != NULL) 430 softint_disestablish(sc->init_task); 431 if (sc->sc_soft_ih != NULL) 432 softint_disestablish(sc->sc_soft_ih); 433 434 if (sc->sc_ih != NULL) { 435 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 436 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 437 } 438 439 return 0; 440 } 441 442 static int 443 rtwn_activate(device_t self, enum devact act) 444 { 445 struct rtwn_softc *sc = device_private(self); 446 struct ifnet *ifp = GET_IFP(sc); 447 448 switch (act) { 449 case DVACT_DEACTIVATE: 450 if (ifp->if_flags & IFF_RUNNING) 451 rtwn_stop(ifp, 0); 452 return 0; 453 default: 454 return EOPNOTSUPP; 455 } 456 } 457 458 static void 459 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc_pci *desc, 460 bus_addr_t addr, size_t len, int idx) 461 { 462 463 memset(desc, 0, sizeof(*desc)); 464 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 465 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 466 desc->rxbufaddr = htole32(addr); 467 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 468 BUS_SPACE_BARRIER_WRITE); 469 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 470 } 471 472 static int 473 rtwn_alloc_rx_list(struct rtwn_softc *sc) 474 { 475 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 476 struct rtwn_rx_data *rx_data; 477 const size_t size = sizeof(struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT; 478 int i, error = 0; 479 480 /* Allocate Rx descriptors. */ 481 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 482 &rx_ring->map); 483 if (error != 0) { 484 aprint_error_dev(sc->sc_dev, 485 "could not create rx desc DMA map\n"); 486 rx_ring->map = NULL; 487 goto fail; 488 } 489 490 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 491 &rx_ring->nsegs, BUS_DMA_NOWAIT); 492 if (error != 0) { 493 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 494 goto fail; 495 } 496 497 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 498 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 499 if (error != 0) { 500 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 501 rx_ring->desc = NULL; 502 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 503 goto fail; 504 } 505 memset(rx_ring->desc, 0, size); 506 507 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 508 1, size, BUS_DMA_NOWAIT); 509 if (error != 0) { 510 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 511 goto fail; 512 } 513 514 /* Allocate Rx buffers. */ 515 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 516 rx_data = &rx_ring->rx_data[i]; 517 518 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 519 0, BUS_DMA_NOWAIT, &rx_data->map); 520 if (error != 0) { 521 aprint_error_dev(sc->sc_dev, 522 "could not create rx buf DMA map\n"); 523 goto fail; 524 } 525 526 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 527 if (__predict_false(rx_data->m == NULL)) { 528 aprint_error_dev(sc->sc_dev, 529 "couldn't allocate rx mbuf\n"); 530 error = ENOMEM; 531 goto fail; 532 } 533 MCLGET(rx_data->m, M_DONTWAIT); 534 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 535 aprint_error_dev(sc->sc_dev, 536 "couldn't allocate rx mbuf cluster\n"); 537 m_free(rx_data->m); 538 rx_data->m = NULL; 539 error = ENOMEM; 540 goto fail; 541 } 542 543 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 544 mtod(rx_data->m, void *), MCLBYTES, NULL, 545 BUS_DMA_NOWAIT | BUS_DMA_READ); 546 if (error != 0) { 547 aprint_error_dev(sc->sc_dev, 548 "could not load rx buf DMA map\n"); 549 goto fail; 550 } 551 552 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 553 BUS_DMASYNC_PREREAD); 554 555 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 556 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 557 } 558 fail: if (error != 0) 559 rtwn_free_rx_list(sc); 560 return error; 561 } 562 563 static void 564 rtwn_reset_rx_list(struct rtwn_softc *sc) 565 { 566 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 567 struct rtwn_rx_data *rx_data; 568 int i; 569 570 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 571 rx_data = &rx_ring->rx_data[i]; 572 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 573 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 574 } 575 } 576 577 static void 578 rtwn_free_rx_list(struct rtwn_softc *sc) 579 { 580 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 581 struct rtwn_rx_data *rx_data; 582 int i, s; 583 584 s = splnet(); 585 586 if (rx_ring->map) { 587 if (rx_ring->desc) { 588 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 589 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 590 sizeof (struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT); 591 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 592 rx_ring->nsegs); 593 rx_ring->desc = NULL; 594 } 595 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 596 rx_ring->map = NULL; 597 } 598 599 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 600 rx_data = &rx_ring->rx_data[i]; 601 602 if (rx_data->m != NULL) { 603 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 604 m_freem(rx_data->m); 605 rx_data->m = NULL; 606 } 607 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 608 rx_data->map = NULL; 609 } 610 611 splx(s); 612 } 613 614 static int 615 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 616 { 617 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 618 struct rtwn_tx_data *tx_data; 619 const size_t size = sizeof(struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT; 620 int i = 0, error = 0; 621 622 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 623 &tx_ring->map); 624 if (error != 0) { 625 aprint_error_dev(sc->sc_dev, 626 "could not create tx ring DMA map\n"); 627 goto fail; 628 } 629 630 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 631 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 632 if (error != 0) { 633 aprint_error_dev(sc->sc_dev, 634 "could not allocate tx ring DMA memory\n"); 635 goto fail; 636 } 637 638 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 639 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 640 if (error != 0) { 641 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 642 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 643 goto fail; 644 } 645 memset(tx_ring->desc, 0, size); 646 647 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 648 size, NULL, BUS_DMA_NOWAIT); 649 if (error != 0) { 650 aprint_error_dev(sc->sc_dev, 651 "could not load tx ring DMA map\n"); 652 goto fail; 653 } 654 655 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 656 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i]; 657 658 /* setup tx desc */ 659 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 660 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 661 662 tx_data = &tx_ring->tx_data[i]; 663 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 664 0, BUS_DMA_NOWAIT, &tx_data->map); 665 if (error != 0) { 666 aprint_error_dev(sc->sc_dev, 667 "could not create tx buf DMA map\n"); 668 goto fail; 669 } 670 tx_data->m = NULL; 671 tx_data->ni = NULL; 672 } 673 674 fail: 675 if (error != 0) 676 rtwn_free_tx_list(sc, qid); 677 return error; 678 } 679 680 static void 681 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 682 { 683 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 684 int i; 685 686 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 687 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i]; 688 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 689 690 memset(desc, 0, sizeof(*desc) - 691 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 692 sizeof(desc->nextdescaddr))); 693 694 if (tx_data->m != NULL) { 695 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 696 m_freem(tx_data->m); 697 tx_data->m = NULL; 698 ieee80211_free_node(tx_data->ni); 699 tx_data->ni = NULL; 700 } 701 } 702 703 sc->qfullmsk &= ~(1 << qid); 704 tx_ring->queued = 0; 705 tx_ring->cur = 0; 706 } 707 708 static void 709 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 710 { 711 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 712 struct rtwn_tx_data *tx_data; 713 int i; 714 715 if (tx_ring->map != NULL) { 716 if (tx_ring->desc != NULL) { 717 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 718 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 719 sizeof (struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT); 720 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 721 tx_ring->nsegs); 722 } 723 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 724 } 725 726 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 727 tx_data = &tx_ring->tx_data[i]; 728 729 if (tx_data->m != NULL) { 730 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 731 m_freem(tx_data->m); 732 tx_data->m = NULL; 733 } 734 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 735 } 736 737 sc->qfullmsk &= ~(1 << qid); 738 tx_ring->queued = 0; 739 tx_ring->cur = 0; 740 } 741 742 static void 743 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 744 { 745 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 746 } 747 748 static void 749 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 750 { 751 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 752 } 753 754 static void 755 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 756 { 757 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 758 } 759 760 static uint8_t 761 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 762 { 763 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 764 } 765 766 static uint16_t 767 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 768 { 769 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 770 } 771 772 static uint32_t 773 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 774 { 775 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 776 } 777 778 static int 779 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 780 { 781 struct r92c_fw_cmd cmd; 782 uint8_t *cp; 783 int fwcur; 784 int ntries; 785 786 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 787 device_xname(sc->sc_dev), __func__, id, buf, len)); 788 789 fwcur = sc->fwcur; 790 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 791 792 /* Wait for current FW box to be empty. */ 793 for (ntries = 0; ntries < 100; ntries++) { 794 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 795 break; 796 DELAY(1); 797 } 798 if (ntries == 100) { 799 aprint_error_dev(sc->sc_dev, 800 "could not send firmware command %d\n", id); 801 return ETIMEDOUT; 802 } 803 804 memset(&cmd, 0, sizeof(cmd)); 805 KASSERT(len <= sizeof(cmd.msg)); 806 memcpy(cmd.msg, buf, len); 807 808 /* Write the first word last since that will trigger the FW. */ 809 cp = (uint8_t *)&cmd; 810 if (len >= 4) { 811 cmd.id = id | R92C_CMD_FLAG_EXT; 812 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 813 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 814 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 815 } else { 816 cmd.id = id; 817 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 818 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 819 } 820 821 /* Give firmware some time for processing. */ 822 DELAY(2000); 823 824 return 0; 825 } 826 827 static void 828 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 829 { 830 831 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 832 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 833 } 834 835 static uint32_t 836 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 837 { 838 uint32_t reg[R92C_MAX_CHAINS], val; 839 840 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 841 if (chain != 0) 842 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 843 844 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 845 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 846 DELAY(1000); 847 848 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 849 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 850 R92C_HSSI_PARAM2_READ_EDGE); 851 DELAY(1000); 852 853 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 854 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 855 DELAY(1000); 856 857 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 858 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 859 else 860 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 861 return MS(val, R92C_LSSI_READBACK_DATA); 862 } 863 864 static int 865 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 866 { 867 int ntries; 868 869 rtwn_write_4(sc, R92C_LLT_INIT, 870 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 871 SM(R92C_LLT_INIT_ADDR, addr) | 872 SM(R92C_LLT_INIT_DATA, data)); 873 /* Wait for write operation to complete. */ 874 for (ntries = 0; ntries < 20; ntries++) { 875 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 876 R92C_LLT_INIT_OP_NO_ACTIVE) 877 return 0; 878 DELAY(5); 879 } 880 return ETIMEDOUT; 881 } 882 883 static uint8_t 884 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 885 { 886 uint32_t reg; 887 int ntries; 888 889 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 890 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 891 reg &= ~R92C_EFUSE_CTRL_VALID; 892 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 893 /* Wait for read operation to complete. */ 894 for (ntries = 0; ntries < 100; ntries++) { 895 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 896 if (reg & R92C_EFUSE_CTRL_VALID) 897 return MS(reg, R92C_EFUSE_CTRL_DATA); 898 DELAY(5); 899 } 900 aprint_error_dev(sc->sc_dev, 901 "could not read efuse byte at address 0x%x\n", addr); 902 return 0xff; 903 } 904 905 static void 906 rtwn_efuse_read(struct rtwn_softc *sc) 907 { 908 uint8_t *rom = (uint8_t *)&sc->rom; 909 uint32_t reg; 910 uint16_t addr = 0; 911 uint8_t off, msk; 912 int i; 913 914 rtwn_efuse_switch_power(sc); 915 916 memset(&sc->rom, 0xff, sizeof(sc->rom)); 917 while (addr < 512) { 918 reg = rtwn_efuse_read_1(sc, addr); 919 if (reg == 0xff) 920 break; 921 addr++; 922 off = reg >> 4; 923 msk = reg & 0xf; 924 for (i = 0; i < 4; i++) { 925 if (msk & (1 << i)) 926 continue; 927 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 928 addr++; 929 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 930 addr++; 931 } 932 } 933 #ifdef RTWN_DEBUG 934 if (rtwn_debug >= 2) { 935 /* Dump ROM content. */ 936 printf("\n"); 937 for (i = 0; i < sizeof(sc->rom); i++) 938 printf("%02x:", rom[i]); 939 printf("\n"); 940 } 941 #endif 942 } 943 944 static void 945 rtwn_efuse_switch_power(struct rtwn_softc *sc) 946 { 947 uint32_t reg; 948 949 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 950 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 951 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 952 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 953 } 954 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 955 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 956 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 957 reg | R92C_SYS_FUNC_EN_ELDR); 958 } 959 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 960 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 961 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 962 rtwn_write_2(sc, R92C_SYS_CLKR, 963 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 964 } 965 } 966 967 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 968 static int 969 rtwn_read_chipid(struct rtwn_softc *sc) 970 { 971 uint32_t reg; 972 973 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 974 975 reg = rtwn_read_4(sc, R92C_SYS_CFG); 976 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 977 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 978 /* Unsupported test chip. */ 979 return EIO; 980 981 if (reg & R92C_SYS_CFG_TYPE_92C) { 982 sc->chip |= RTWN_CHIP_92C; 983 /* Check if it is a castrated 8192C. */ 984 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 985 R92C_HPON_FSM_CHIP_BONDING_ID) == 986 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 987 sc->chip |= RTWN_CHIP_92C_1T2R; 988 } 989 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 990 sc->chip |= RTWN_CHIP_UMC; 991 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 992 sc->chip |= RTWN_CHIP_UMC_A_CUT; 993 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 994 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 995 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 996 else 997 /* Unsupported unknown chip. */ 998 return EIO; 999 } 1000 return 0; 1001 } 1002 1003 static void 1004 rtwn_read_rom(struct rtwn_softc *sc) 1005 { 1006 struct ieee80211com *ic = &sc->sc_ic; 1007 struct r92c_rom *rom = &sc->rom; 1008 1009 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1010 1011 /* Read full ROM image. */ 1012 rtwn_efuse_read(sc); 1013 1014 if (rom->id != 0x8129) { 1015 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1016 rom->id); 1017 } 1018 1019 /* XXX Weird but this is what the vendor driver does. */ 1020 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1021 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1022 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1023 1024 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1025 sc->pa_setting, sc->board_type, sc->regulatory)); 1026 1027 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1028 } 1029 1030 static int 1031 rtwn_media_change(struct ifnet *ifp) 1032 { 1033 int error; 1034 1035 error = ieee80211_media_change(ifp); 1036 if (error != ENETRESET) 1037 return error; 1038 1039 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1040 (IFF_UP | IFF_RUNNING)) { 1041 rtwn_stop(ifp, 0); 1042 error = rtwn_init(ifp); 1043 } 1044 return error; 1045 } 1046 1047 /* 1048 * Initialize rate adaptation in firmware. 1049 */ 1050 static int 1051 rtwn_ra_init(struct rtwn_softc *sc) 1052 { 1053 static const uint8_t map[] = { 1054 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1055 }; 1056 struct ieee80211com *ic = &sc->sc_ic; 1057 struct ieee80211_node *ni = ic->ic_bss; 1058 struct ieee80211_rateset *rs = &ni->ni_rates; 1059 struct r92c_fw_cmd_macid_cfg cmd; 1060 uint32_t rates, basicrates; 1061 uint8_t mode; 1062 int maxrate, maxbasicrate, error, i, j; 1063 1064 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1065 1066 /* Get normal and basic rates mask. */ 1067 rates = basicrates = 0; 1068 maxrate = maxbasicrate = 0; 1069 for (i = 0; i < rs->rs_nrates; i++) { 1070 /* Convert 802.11 rate to HW rate index. */ 1071 for (j = 0; j < __arraycount(map); j++) 1072 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1073 break; 1074 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1075 continue; 1076 rates |= 1 << j; 1077 if (j > maxrate) 1078 maxrate = j; 1079 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1080 basicrates |= 1 << j; 1081 if (j > maxbasicrate) 1082 maxbasicrate = j; 1083 } 1084 } 1085 if (ic->ic_curmode == IEEE80211_MODE_11B) 1086 mode = R92C_RAID_11B; 1087 else 1088 mode = R92C_RAID_11BG; 1089 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1090 device_xname(sc->sc_dev), mode, rates, basicrates)); 1091 if (basicrates == 0) 1092 basicrates |= 1; /* add 1Mbps */ 1093 1094 /* Set rates mask for group addressed frames. */ 1095 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1096 cmd.mask = htole32((mode << 28) | basicrates); 1097 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1098 if (error != 0) { 1099 aprint_error_dev(sc->sc_dev, 1100 "could not add broadcast station\n"); 1101 return error; 1102 } 1103 /* Set initial MRR rate. */ 1104 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1105 maxbasicrate)); 1106 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1107 1108 /* Set rates mask for unicast frames. */ 1109 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1110 cmd.mask = htole32((mode << 28) | rates); 1111 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1112 if (error != 0) { 1113 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1114 return error; 1115 } 1116 /* Set initial MRR rate. */ 1117 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1118 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1119 1120 /* Configure Automatic Rate Fallback Register. */ 1121 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1122 if (rates & 0x0c) 1123 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1124 else 1125 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1126 } else 1127 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1128 1129 /* Indicate highest supported rate. */ 1130 ni->ni_txrate = rs->rs_nrates - 1; 1131 return 0; 1132 } 1133 1134 static int 1135 rtwn_get_nettype(struct rtwn_softc *sc) 1136 { 1137 struct ieee80211com *ic = &sc->sc_ic; 1138 int type; 1139 1140 switch (ic->ic_opmode) { 1141 case IEEE80211_M_STA: 1142 type = R92C_CR_NETTYPE_INFRA; 1143 break; 1144 1145 case IEEE80211_M_HOSTAP: 1146 type = R92C_CR_NETTYPE_AP; 1147 break; 1148 1149 case IEEE80211_M_IBSS: 1150 type = R92C_CR_NETTYPE_ADHOC; 1151 break; 1152 1153 default: 1154 type = R92C_CR_NETTYPE_NOLINK; 1155 break; 1156 } 1157 1158 return type; 1159 } 1160 1161 static void 1162 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1163 { 1164 uint32_t reg; 1165 1166 reg = rtwn_read_4(sc, R92C_CR); 1167 reg = RW(reg, R92C_CR_NETTYPE, type); 1168 rtwn_write_4(sc, R92C_CR, reg); 1169 } 1170 1171 static void 1172 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1173 { 1174 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1175 uint64_t tsf; 1176 1177 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1178 1179 /* Enable TSF synchronization. */ 1180 rtwn_write_1(sc, R92C_BCN_CTRL, 1181 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1182 1183 rtwn_write_1(sc, R92C_BCN_CTRL, 1184 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1185 1186 /* Set initial TSF. */ 1187 tsf = ni->ni_tstamp.tsf; 1188 tsf = le64toh(tsf); 1189 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1190 tsf -= IEEE80211_DUR_TU; 1191 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1192 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1193 1194 rtwn_write_1(sc, R92C_BCN_CTRL, 1195 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1196 } 1197 1198 static void 1199 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1200 { 1201 uint8_t reg; 1202 1203 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1204 1205 if (led == RTWN_LED_LINK) { 1206 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1207 if (!on) 1208 reg |= R92C_LEDCFG2_DIS; 1209 else 1210 reg |= R92C_LEDCFG2_EN; 1211 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1212 sc->ledlink = on; /* Save LED state. */ 1213 } 1214 } 1215 1216 static void 1217 rtwn_calib_to(void *arg) 1218 { 1219 struct rtwn_softc *sc = arg; 1220 struct r92c_fw_cmd_rssi cmd; 1221 int s; 1222 1223 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1224 1225 s = splnet(); 1226 1227 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1228 goto restart_timer; 1229 1230 if (sc->avg_pwdb != -1) { 1231 /* Indicate Rx signal strength to FW for rate adaptation. */ 1232 memset(&cmd, 0, sizeof(cmd)); 1233 cmd.macid = 0; /* BSS. */ 1234 cmd.pwdb = sc->avg_pwdb; 1235 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1236 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1237 } 1238 1239 /* Do temperature compensation. */ 1240 rtwn_temp_calib(sc); 1241 1242 restart_timer: 1243 callout_schedule(&sc->calib_to, mstohz(2000)); 1244 1245 splx(s); 1246 } 1247 1248 static void 1249 rtwn_next_scan(void *arg) 1250 { 1251 struct rtwn_softc *sc = arg; 1252 struct ieee80211com *ic = &sc->sc_ic; 1253 int s; 1254 1255 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1256 1257 s = splnet(); 1258 if (ic->ic_state == IEEE80211_S_SCAN) 1259 ieee80211_next_scan(ic); 1260 splx(s); 1261 } 1262 1263 static void 1264 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1265 { 1266 1267 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1268 1269 /* start with lowest Tx rate */ 1270 ni->ni_txrate = 0; 1271 } 1272 1273 static int 1274 rtwn_reset(struct ifnet *ifp) 1275 { 1276 struct rtwn_softc *sc = ifp->if_softc; 1277 struct ieee80211com *ic = &sc->sc_ic; 1278 1279 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1280 return ENETRESET; 1281 1282 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1283 1284 return 0; 1285 } 1286 1287 static int 1288 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1289 { 1290 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1291 struct ieee80211_node *ni; 1292 enum ieee80211_state ostate = ic->ic_state; 1293 uint32_t reg; 1294 int s; 1295 1296 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1297 1298 s = splnet(); 1299 1300 callout_stop(&sc->scan_to); 1301 callout_stop(&sc->calib_to); 1302 1303 if (ostate != nstate) { 1304 DPRINTF(("%s: %s -> %s\n", __func__, 1305 ieee80211_state_name[ostate], 1306 ieee80211_state_name[nstate])); 1307 } 1308 1309 switch (ostate) { 1310 case IEEE80211_S_INIT: 1311 break; 1312 1313 case IEEE80211_S_SCAN: 1314 if (nstate != IEEE80211_S_SCAN) { 1315 /* 1316 * End of scanning 1317 */ 1318 /* flush 4-AC Queue after site_survey */ 1319 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1320 1321 /* Allow Rx from our BSSID only. */ 1322 rtwn_write_4(sc, R92C_RCR, 1323 rtwn_read_4(sc, R92C_RCR) | 1324 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1325 } 1326 break; 1327 1328 case IEEE80211_S_AUTH: 1329 case IEEE80211_S_ASSOC: 1330 break; 1331 1332 case IEEE80211_S_RUN: 1333 /* Turn link LED off. */ 1334 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1335 1336 /* Set media status to 'No Link'. */ 1337 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1338 1339 /* Stop Rx of data frames. */ 1340 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1341 1342 /* Rest TSF. */ 1343 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1344 1345 /* Disable TSF synchronization. */ 1346 rtwn_write_1(sc, R92C_BCN_CTRL, 1347 rtwn_read_1(sc, R92C_BCN_CTRL) | 1348 R92C_BCN_CTRL_DIS_TSF_UDT0); 1349 1350 /* Back to 20MHz mode */ 1351 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1352 1353 /* Reset EDCA parameters. */ 1354 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1355 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1356 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1357 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1358 1359 /* flush all cam entries */ 1360 rtwn_cam_init(sc); 1361 break; 1362 } 1363 1364 switch (nstate) { 1365 case IEEE80211_S_INIT: 1366 /* Turn link LED off. */ 1367 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1368 break; 1369 1370 case IEEE80211_S_SCAN: 1371 if (ostate != IEEE80211_S_SCAN) { 1372 /* 1373 * Begin of scanning 1374 */ 1375 1376 /* Set gain for scanning. */ 1377 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1378 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1379 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1380 1381 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1382 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1383 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1384 1385 /* Allow Rx from any BSSID. */ 1386 rtwn_write_4(sc, R92C_RCR, 1387 rtwn_read_4(sc, R92C_RCR) & 1388 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1389 1390 /* Stop Rx of data frames. */ 1391 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1392 1393 /* Disable update TSF */ 1394 rtwn_write_1(sc, R92C_BCN_CTRL, 1395 rtwn_read_1(sc, R92C_BCN_CTRL) | 1396 R92C_BCN_CTRL_DIS_TSF_UDT0); 1397 } 1398 1399 /* Make link LED blink during scan. */ 1400 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1401 1402 /* Pause AC Tx queues. */ 1403 rtwn_write_1(sc, R92C_TXPAUSE, 1404 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1405 1406 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1407 1408 /* Start periodic scan. */ 1409 callout_schedule(&sc->scan_to, mstohz(200)); 1410 break; 1411 1412 case IEEE80211_S_AUTH: 1413 /* Set initial gain under link. */ 1414 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1415 #ifdef doaslinux 1416 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1417 #else 1418 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1419 #endif 1420 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1421 1422 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1423 #ifdef doaslinux 1424 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1425 #else 1426 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1427 #endif 1428 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1429 1430 /* Set media status to 'No Link'. */ 1431 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1432 1433 /* Allow Rx from any BSSID. */ 1434 rtwn_write_4(sc, R92C_RCR, 1435 rtwn_read_4(sc, R92C_RCR) & 1436 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1437 1438 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1439 break; 1440 1441 case IEEE80211_S_ASSOC: 1442 break; 1443 1444 case IEEE80211_S_RUN: 1445 ni = ic->ic_bss; 1446 1447 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1448 1449 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1450 /* Back to 20Mhz mode */ 1451 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1452 1453 /* Set media status to 'No Link'. */ 1454 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1455 1456 /* Enable Rx of data frames. */ 1457 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1458 1459 /* Allow Rx from any BSSID. */ 1460 rtwn_write_4(sc, R92C_RCR, 1461 rtwn_read_4(sc, R92C_RCR) & 1462 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1463 1464 /* Accept Rx data/control/management frames */ 1465 rtwn_write_4(sc, R92C_RCR, 1466 rtwn_read_4(sc, R92C_RCR) | 1467 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1468 1469 /* Turn link LED on. */ 1470 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1471 break; 1472 } 1473 1474 /* Set media status to 'Associated'. */ 1475 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1476 1477 /* Set BSSID. */ 1478 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1479 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1480 1481 if (ic->ic_curmode == IEEE80211_MODE_11B) 1482 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1483 else /* 802.11b/g */ 1484 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1485 1486 /* Enable Rx of data frames. */ 1487 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1488 1489 /* Flush all AC queues. */ 1490 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1491 1492 /* Set beacon interval. */ 1493 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1494 1495 switch (ic->ic_opmode) { 1496 case IEEE80211_M_STA: 1497 /* Allow Rx from our BSSID only. */ 1498 rtwn_write_4(sc, R92C_RCR, 1499 rtwn_read_4(sc, R92C_RCR) | 1500 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1501 1502 /* Enable TSF synchronization. */ 1503 rtwn_tsf_sync_enable(sc); 1504 break; 1505 1506 case IEEE80211_M_HOSTAP: 1507 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1508 1509 /* Allow Rx from any BSSID. */ 1510 rtwn_write_4(sc, R92C_RCR, 1511 rtwn_read_4(sc, R92C_RCR) & 1512 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1513 1514 /* Reset TSF timer to zero. */ 1515 reg = rtwn_read_4(sc, R92C_TCR); 1516 reg &= ~0x01; 1517 rtwn_write_4(sc, R92C_TCR, reg); 1518 reg |= 0x01; 1519 rtwn_write_4(sc, R92C_TCR, reg); 1520 break; 1521 1522 case IEEE80211_M_MONITOR: 1523 default: 1524 break; 1525 } 1526 1527 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1528 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1529 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1530 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1531 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1532 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1533 1534 /* Initialize rate adaptation. */ 1535 rtwn_ra_init(sc); 1536 1537 /* Turn link LED on. */ 1538 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1539 1540 /* Reset average RSSI. */ 1541 sc->avg_pwdb = -1; 1542 1543 /* Reset temperature calibration state machine. */ 1544 sc->thcal_state = 0; 1545 sc->thcal_lctemp = 0; 1546 1547 /* Start periodic calibration. */ 1548 callout_schedule(&sc->calib_to, mstohz(2000)); 1549 break; 1550 } 1551 1552 (void)sc->sc_newstate(ic, nstate, arg); 1553 1554 splx(s); 1555 1556 return 0; 1557 } 1558 1559 static int 1560 rtwn_wme_update(struct ieee80211com *ic) 1561 { 1562 static const uint16_t aci2reg[WME_NUM_AC] = { 1563 R92C_EDCA_BE_PARAM, 1564 R92C_EDCA_BK_PARAM, 1565 R92C_EDCA_VI_PARAM, 1566 R92C_EDCA_VO_PARAM 1567 }; 1568 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1569 const struct wmeParams *wmep; 1570 int s, aci, aifs, slottime; 1571 1572 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1573 1574 s = splnet(); 1575 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1576 for (aci = 0; aci < WME_NUM_AC; aci++) { 1577 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1578 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1579 aifs = wmep->wmep_aifsn * slottime + 10; 1580 rtwn_write_4(sc, aci2reg[aci], 1581 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1582 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1583 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1584 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1585 } 1586 splx(s); 1587 1588 return 0; 1589 } 1590 1591 static void 1592 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1593 { 1594 int pwdb; 1595 1596 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1597 1598 /* Convert antenna signal to percentage. */ 1599 if (rssi <= -100 || rssi >= 20) 1600 pwdb = 0; 1601 else if (rssi >= 0) 1602 pwdb = 100; 1603 else 1604 pwdb = 100 + rssi; 1605 if (rate <= 3) { 1606 /* CCK gain is smaller than OFDM/MCS gain. */ 1607 pwdb += 6; 1608 if (pwdb > 100) 1609 pwdb = 100; 1610 if (pwdb <= 14) 1611 pwdb -= 4; 1612 else if (pwdb <= 26) 1613 pwdb -= 8; 1614 else if (pwdb <= 34) 1615 pwdb -= 6; 1616 else if (pwdb <= 42) 1617 pwdb -= 2; 1618 } 1619 if (sc->avg_pwdb == -1) /* Init. */ 1620 sc->avg_pwdb = pwdb; 1621 else if (sc->avg_pwdb < pwdb) 1622 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1623 else 1624 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1625 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1626 } 1627 1628 static int8_t 1629 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1630 { 1631 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1632 struct r92c_rx_phystat *phy; 1633 struct r92c_rx_cck *cck; 1634 uint8_t rpt; 1635 int8_t rssi; 1636 1637 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1638 1639 if (rate <= 3) { 1640 cck = (struct r92c_rx_cck *)physt; 1641 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1642 rpt = (cck->agc_rpt >> 5) & 0x3; 1643 rssi = (cck->agc_rpt & 0x1f) << 1; 1644 } else { 1645 rpt = (cck->agc_rpt >> 6) & 0x3; 1646 rssi = cck->agc_rpt & 0x3e; 1647 } 1648 rssi = cckoff[rpt] - rssi; 1649 } else { /* OFDM/HT. */ 1650 phy = (struct r92c_rx_phystat *)physt; 1651 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1652 } 1653 return rssi; 1654 } 1655 1656 static void 1657 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc_pci *rx_desc, 1658 struct rtwn_rx_data *rx_data, int desc_idx) 1659 { 1660 struct ieee80211com *ic = &sc->sc_ic; 1661 struct ifnet *ifp = IC2IFP(ic); 1662 struct ieee80211_frame *wh; 1663 struct ieee80211_node *ni; 1664 struct r92c_rx_phystat *phy = NULL; 1665 uint32_t rxdw0, rxdw3; 1666 struct mbuf *m, *m1; 1667 uint8_t rate; 1668 int8_t rssi = 0; 1669 int infosz, pktlen, shift, totlen, error, s; 1670 1671 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1672 1673 rxdw0 = le32toh(rx_desc->rxdw0); 1674 rxdw3 = le32toh(rx_desc->rxdw3); 1675 1676 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1677 /* 1678 * This should not happen since we setup our Rx filter 1679 * to not receive these frames. 1680 */ 1681 if_statinc(ifp, if_ierrors); 1682 return; 1683 } 1684 1685 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1686 /* 1687 * XXX: This will drop most control packets. Do we really 1688 * want this in IEEE80211_M_MONITOR mode? 1689 */ 1690 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1691 ic->ic_stats.is_rx_tooshort++; 1692 if_statinc(ifp, if_ierrors); 1693 return; 1694 } 1695 if (__predict_false(pktlen > MCLBYTES)) { 1696 if_statinc(ifp, if_ierrors); 1697 return; 1698 } 1699 1700 rate = MS(rxdw3, R92C_RXDW3_RATE); 1701 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1702 if (infosz > sizeof(struct r92c_rx_phystat)) 1703 infosz = sizeof(struct r92c_rx_phystat); 1704 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1705 totlen = pktlen + infosz + shift; 1706 1707 /* Get RSSI from PHY status descriptor if present. */ 1708 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1709 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1710 rssi = rtwn_get_rssi(sc, rate, phy); 1711 /* Update our average RSSI. */ 1712 rtwn_update_avgrssi(sc, rate, rssi); 1713 } 1714 1715 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1716 pktlen, rate, infosz, shift, rssi)); 1717 1718 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1719 if (__predict_false(m1 == NULL)) { 1720 ic->ic_stats.is_rx_nobuf++; 1721 if_statinc(ifp, if_ierrors); 1722 return; 1723 } 1724 MCLGET(m1, M_DONTWAIT); 1725 if (__predict_false(!(m1->m_flags & M_EXT))) { 1726 m_freem(m1); 1727 ic->ic_stats.is_rx_nobuf++; 1728 if_statinc(ifp, if_ierrors); 1729 return; 1730 } 1731 1732 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1733 BUS_DMASYNC_POSTREAD); 1734 1735 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1736 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1737 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1738 if (error != 0) { 1739 m_freem(m1); 1740 1741 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1742 rx_data->m, BUS_DMA_NOWAIT)) 1743 panic("%s: could not load old RX mbuf", 1744 device_xname(sc->sc_dev)); 1745 1746 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1747 BUS_DMASYNC_PREREAD); 1748 1749 /* Physical address may have changed. */ 1750 rtwn_setup_rx_desc(sc, rx_desc, 1751 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1752 1753 if_statinc(ifp, if_ierrors); 1754 return; 1755 } 1756 1757 /* Finalize mbuf. */ 1758 m = rx_data->m; 1759 rx_data->m = m1; 1760 m->m_pkthdr.len = m->m_len = totlen; 1761 m_set_rcvif(m, ifp); 1762 1763 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1764 BUS_DMASYNC_PREREAD); 1765 1766 /* Update RX descriptor. */ 1767 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1768 MCLBYTES, desc_idx); 1769 1770 /* Get ieee80211 frame header. */ 1771 if (rxdw0 & R92C_RXDW0_PHYST) 1772 m_adj(m, infosz + shift); 1773 else 1774 m_adj(m, shift); 1775 wh = mtod(m, struct ieee80211_frame *); 1776 1777 s = splnet(); 1778 1779 if (__predict_false(sc->sc_drvbpf != NULL)) { 1780 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1781 1782 tap->wr_flags = 0; 1783 /* Map HW rate index to 802.11 rate. */ 1784 tap->wr_flags = 2; 1785 if (!(rxdw3 & R92C_RXDW3_HT)) { 1786 switch (rate) { 1787 /* CCK. */ 1788 case 0: tap->wr_rate = 2; break; 1789 case 1: tap->wr_rate = 4; break; 1790 case 2: tap->wr_rate = 11; break; 1791 case 3: tap->wr_rate = 22; break; 1792 /* OFDM. */ 1793 case 4: tap->wr_rate = 12; break; 1794 case 5: tap->wr_rate = 18; break; 1795 case 6: tap->wr_rate = 24; break; 1796 case 7: tap->wr_rate = 36; break; 1797 case 8: tap->wr_rate = 48; break; 1798 case 9: tap->wr_rate = 72; break; 1799 case 10: tap->wr_rate = 96; break; 1800 case 11: tap->wr_rate = 108; break; 1801 } 1802 } else if (rate >= 12) { /* MCS0~15. */ 1803 /* Bit 7 set means HT MCS instead of rate. */ 1804 tap->wr_rate = 0x80 | (rate - 12); 1805 } 1806 tap->wr_dbm_antsignal = rssi; 1807 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1808 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1809 1810 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN); 1811 } 1812 1813 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1814 1815 /* push the frame up to the 802.11 stack */ 1816 ieee80211_input(ic, m, ni, rssi, 0); 1817 1818 /* Node is no longer needed. */ 1819 ieee80211_free_node(ni); 1820 1821 splx(s); 1822 } 1823 1824 static int 1825 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1826 { 1827 struct ieee80211com *ic = &sc->sc_ic; 1828 struct ieee80211_frame *wh; 1829 struct ieee80211_key *k = NULL; 1830 struct rtwn_tx_ring *tx_ring; 1831 struct rtwn_tx_data *data; 1832 struct r92c_tx_desc_pci *txd; 1833 uint16_t qos, seq; 1834 uint8_t raid, type, tid, qid; 1835 int hasqos, error; 1836 1837 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1838 1839 wh = mtod(m, struct ieee80211_frame *); 1840 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1841 1842 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1843 k = ieee80211_crypto_encap(ic, ni, m); 1844 if (k == NULL) 1845 return ENOBUFS; 1846 1847 wh = mtod(m, struct ieee80211_frame *); 1848 } 1849 1850 if ((hasqos = ieee80211_has_qos(wh))) { 1851 /* data frames in 11n mode */ 1852 qos = ieee80211_get_qos(wh); 1853 tid = qos & IEEE80211_QOS_TID; 1854 qid = TID_TO_WME_AC(tid); 1855 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1856 /* Use AC_VO for management frames. */ 1857 tid = 0; /* compiler happy */ 1858 qid = RTWN_VO_QUEUE; 1859 } else { 1860 /* non-qos data frames */ 1861 tid = R92C_TXDW1_QSEL_BE; 1862 qid = RTWN_BE_QUEUE; 1863 } 1864 1865 /* Grab a Tx buffer from the ring. */ 1866 tx_ring = &sc->tx_ring[qid]; 1867 data = &tx_ring->tx_data[tx_ring->cur]; 1868 if (data->m != NULL) { 1869 m_freem(m); 1870 return ENOBUFS; 1871 } 1872 1873 /* Fill Tx descriptor. */ 1874 txd = &tx_ring->desc[tx_ring->cur]; 1875 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1876 m_freem(m); 1877 return ENOBUFS; 1878 } 1879 1880 txd->txdw0 = htole32( 1881 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1882 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1883 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1884 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1885 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1886 1887 txd->txdw1 = 0; 1888 txd->txdw4 = 0; 1889 txd->txdw5 = 0; 1890 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1891 type == IEEE80211_FC0_TYPE_DATA) { 1892 if (ic->ic_curmode == IEEE80211_MODE_11B) 1893 raid = R92C_RAID_11B; 1894 else 1895 raid = R92C_RAID_11BG; 1896 1897 txd->txdw1 |= htole32( 1898 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1899 SM(R92C_TXDW1_QSEL, tid) | 1900 SM(R92C_TXDW1_RAID, raid) | 1901 R92C_TXDW1_AGGBK); 1902 1903 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1904 /* for 11g */ 1905 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1906 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1907 R92C_TXDW4_HWRTSEN); 1908 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1909 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1910 R92C_TXDW4_HWRTSEN); 1911 } 1912 } 1913 /* Send RTS at OFDM24. */ 1914 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1915 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1916 /* Send data at OFDM54. */ 1917 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1918 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1919 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1920 txd->txdw1 |= htole32( 1921 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1922 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1923 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1924 1925 /* Force CCK1. */ 1926 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1927 /* Use 1Mbps */ 1928 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1929 } else { 1930 txd->txdw1 |= htole32( 1931 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1932 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1933 1934 /* Force CCK1. */ 1935 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1936 /* Use 1Mbps */ 1937 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1938 } 1939 1940 /* Set sequence number (already little endian). */ 1941 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1942 txd->txdseq = htole16(seq); 1943 1944 if (!hasqos) { 1945 /* Use HW sequence numbering for non-QoS frames. */ 1946 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1947 txd->txdseq |= htole16(0x8000); /* WTF? */ 1948 } else 1949 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1950 1951 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1952 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1953 if (error && error != EFBIG) { 1954 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1955 error); 1956 m_freem(m); 1957 return error; 1958 } 1959 if (error != 0) { 1960 /* Too many DMA segments, linearize mbuf. */ 1961 struct mbuf *newm = m_defrag(m, M_DONTWAIT); 1962 if (newm == NULL) { 1963 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1964 m_freem(m); 1965 return ENOBUFS; 1966 } 1967 m = newm; 1968 1969 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1970 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1971 if (error != 0) { 1972 aprint_error_dev(sc->sc_dev, 1973 "can't map mbuf (error %d)\n", error); 1974 m_freem(m); 1975 return error; 1976 } 1977 } 1978 1979 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1980 txd->txbufsize = htole16(m->m_pkthdr.len); 1981 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1982 BUS_SPACE_BARRIER_WRITE); 1983 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1984 1985 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1986 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1987 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1988 BUS_DMASYNC_PREWRITE); 1989 1990 data->m = m; 1991 data->ni = ni; 1992 1993 if (__predict_false(sc->sc_drvbpf != NULL)) { 1994 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1995 1996 tap->wt_flags = 0; 1997 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1998 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1999 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2000 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2001 2002 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT); 2003 } 2004 2005 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 2006 tx_ring->queued++; 2007 2008 if (tx_ring->queued > RTWN_TX_LIST_HIMARK) 2009 sc->qfullmsk |= (1 << qid); 2010 2011 /* Kick TX. */ 2012 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 2013 2014 return 0; 2015 } 2016 2017 static void 2018 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2019 { 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 struct ifnet *ifp = IC2IFP(ic); 2022 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2023 struct rtwn_tx_data *tx_data; 2024 struct r92c_tx_desc_pci *tx_desc; 2025 int i, s; 2026 2027 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2028 qid)); 2029 2030 s = splnet(); 2031 2032 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2033 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2034 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2035 2036 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2037 tx_data = &tx_ring->tx_data[i]; 2038 if (tx_data->m == NULL) 2039 continue; 2040 2041 tx_desc = &tx_ring->desc[i]; 2042 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2043 continue; 2044 2045 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2046 m_freem(tx_data->m); 2047 tx_data->m = NULL; 2048 ieee80211_free_node(tx_data->ni); 2049 tx_data->ni = NULL; 2050 2051 if_statinc(ifp, if_opackets); 2052 sc->sc_tx_timer = 0; 2053 tx_ring->queued--; 2054 } 2055 2056 if (tx_ring->queued < RTWN_TX_LIST_LOMARK) 2057 sc->qfullmsk &= ~(1 << qid); 2058 2059 splx(s); 2060 } 2061 2062 static void 2063 rtwn_start(struct ifnet *ifp) 2064 { 2065 struct rtwn_softc *sc = ifp->if_softc; 2066 struct ieee80211com *ic = &sc->sc_ic; 2067 struct ether_header *eh; 2068 struct ieee80211_node *ni; 2069 struct mbuf *m; 2070 2071 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2072 return; 2073 2074 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2075 2076 for (;;) { 2077 if (sc->qfullmsk != 0) { 2078 ifp->if_flags |= IFF_OACTIVE; 2079 break; 2080 } 2081 /* Send pending management frames first. */ 2082 IF_DEQUEUE(&ic->ic_mgtq, m); 2083 if (m != NULL) { 2084 ni = M_GETCTX(m, struct ieee80211_node *); 2085 M_CLEARCTX(m); 2086 goto sendit; 2087 } 2088 if (ic->ic_state != IEEE80211_S_RUN) 2089 break; 2090 2091 /* Encapsulate and send data frames. */ 2092 IFQ_DEQUEUE(&ifp->if_snd, m); 2093 if (m == NULL) 2094 break; 2095 2096 if (m->m_len < (int)sizeof(*eh) && 2097 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2098 if_statinc(ifp, if_oerrors); 2099 continue; 2100 } 2101 eh = mtod(m, struct ether_header *); 2102 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2103 if (ni == NULL) { 2104 m_freem(m); 2105 if_statinc(ifp, if_oerrors); 2106 continue; 2107 } 2108 2109 bpf_mtap(ifp, m, BPF_D_OUT); 2110 2111 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2112 ieee80211_free_node(ni); 2113 if_statinc(ifp, if_oerrors); 2114 continue; 2115 } 2116 sendit: 2117 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT); 2118 2119 if (rtwn_tx(sc, m, ni) != 0) { 2120 ieee80211_free_node(ni); 2121 if_statinc(ifp, if_oerrors); 2122 continue; 2123 } 2124 2125 sc->sc_tx_timer = 5; 2126 ifp->if_timer = 1; 2127 } 2128 2129 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2130 } 2131 2132 static void 2133 rtwn_watchdog(struct ifnet *ifp) 2134 { 2135 struct rtwn_softc *sc = ifp->if_softc; 2136 struct ieee80211com *ic = &sc->sc_ic; 2137 2138 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2139 2140 ifp->if_timer = 0; 2141 2142 if (sc->sc_tx_timer > 0) { 2143 if (--sc->sc_tx_timer == 0) { 2144 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2145 softint_schedule(sc->init_task); 2146 if_statinc(ifp, if_oerrors); 2147 return; 2148 } 2149 ifp->if_timer = 1; 2150 } 2151 ieee80211_watchdog(ic); 2152 } 2153 2154 static int 2155 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2156 { 2157 struct rtwn_softc *sc = ifp->if_softc; 2158 struct ieee80211com *ic = &sc->sc_ic; 2159 int s, error = 0; 2160 2161 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2162 __func__, cmd, data)); 2163 2164 s = splnet(); 2165 2166 switch (cmd) { 2167 case SIOCSIFFLAGS: 2168 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2169 break; 2170 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2171 case IFF_UP | IFF_RUNNING: 2172 break; 2173 case IFF_UP: 2174 error = rtwn_init(ifp); 2175 if (error != 0) 2176 ifp->if_flags &= ~IFF_UP; 2177 break; 2178 case IFF_RUNNING: 2179 rtwn_stop(ifp, 1); 2180 break; 2181 case 0: 2182 break; 2183 } 2184 break; 2185 2186 case SIOCADDMULTI: 2187 case SIOCDELMULTI: 2188 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2189 /* setup multicast filter, etc */ 2190 error = 0; 2191 } 2192 break; 2193 2194 case SIOCS80211CHANNEL: 2195 error = ieee80211_ioctl(ic, cmd, data); 2196 if (error == ENETRESET && 2197 ic->ic_opmode == IEEE80211_M_MONITOR) { 2198 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2199 (IFF_UP | IFF_RUNNING)) { 2200 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2201 } 2202 error = 0; 2203 } 2204 break; 2205 2206 default: 2207 error = ieee80211_ioctl(ic, cmd, data); 2208 break; 2209 } 2210 2211 if (error == ENETRESET) { 2212 error = 0; 2213 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2214 (IFF_UP | IFF_RUNNING)) { 2215 rtwn_stop(ifp, 0); 2216 error = rtwn_init(ifp); 2217 } 2218 } 2219 2220 splx(s); 2221 2222 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2223 error)); 2224 2225 return error; 2226 } 2227 2228 static int 2229 rtwn_power_on(struct rtwn_softc *sc) 2230 { 2231 uint32_t reg; 2232 int ntries; 2233 2234 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2235 2236 /* Wait for autoload done bit. */ 2237 for (ntries = 0; ntries < 1000; ntries++) { 2238 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2239 break; 2240 DELAY(5); 2241 } 2242 if (ntries == 1000) { 2243 aprint_error_dev(sc->sc_dev, 2244 "timeout waiting for chip autoload\n"); 2245 return ETIMEDOUT; 2246 } 2247 2248 /* Unlock ISO/CLK/Power control register. */ 2249 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2250 2251 /* TODO: check if we need this for 8188CE */ 2252 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2253 /* bt coex */ 2254 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2255 reg |= (R92C_APS_FSMCO_SOP_ABG | 2256 R92C_APS_FSMCO_SOP_AMB | 2257 R92C_APS_FSMCO_XOP_BTCK); 2258 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2259 } 2260 2261 /* Move SPS into PWM mode. */ 2262 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2263 DELAY(100); 2264 2265 /* Set low byte to 0x0f, leave others unchanged. */ 2266 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2267 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2268 2269 /* TODO: check if we need this for 8188CE */ 2270 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2271 /* bt coex */ 2272 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2273 reg &= ~0x00024800; /* XXX magic from linux */ 2274 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2275 } 2276 2277 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2278 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2279 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2280 DELAY(200); 2281 2282 /* TODO: linux does additional btcoex stuff here */ 2283 2284 /* Auto enable WLAN. */ 2285 rtwn_write_2(sc, R92C_APS_FSMCO, 2286 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2287 for (ntries = 0; ntries < 1000; ntries++) { 2288 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2289 R92C_APS_FSMCO_APFM_ONMAC)) 2290 break; 2291 DELAY(5); 2292 } 2293 if (ntries == 1000) { 2294 aprint_error_dev(sc->sc_dev, 2295 "timeout waiting for MAC auto ON\n"); 2296 return ETIMEDOUT; 2297 } 2298 2299 /* Enable radio, GPIO and LED functions. */ 2300 rtwn_write_2(sc, R92C_APS_FSMCO, 2301 R92C_APS_FSMCO_AFSM_PCIE | 2302 R92C_APS_FSMCO_PDN_EN | 2303 R92C_APS_FSMCO_PFM_ALDN); 2304 2305 /* Release RF digital isolation. */ 2306 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2307 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2308 2309 if (sc->chip & RTWN_CHIP_92C) 2310 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2311 else 2312 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2313 2314 rtwn_write_4(sc, R92C_INT_MIG, 0); 2315 2316 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2317 /* bt coex */ 2318 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2319 reg &= 0xfd; /* XXX magic from linux */ 2320 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2321 } 2322 2323 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2324 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2325 2326 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2327 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2328 aprint_error_dev(sc->sc_dev, 2329 "radio is disabled by hardware switch\n"); 2330 return EPERM; /* :-) */ 2331 } 2332 2333 /* Initialize MAC. */ 2334 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2335 rtwn_write_1(sc, R92C_APSD_CTRL, 2336 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2337 for (ntries = 0; ntries < 200; ntries++) { 2338 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2339 R92C_APSD_CTRL_OFF_STATUS)) 2340 break; 2341 DELAY(500); 2342 } 2343 if (ntries == 200) { 2344 aprint_error_dev(sc->sc_dev, 2345 "timeout waiting for MAC initialization\n"); 2346 return ETIMEDOUT; 2347 } 2348 2349 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2350 reg = rtwn_read_2(sc, R92C_CR); 2351 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2352 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2353 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2354 R92C_CR_ENSEC; 2355 rtwn_write_2(sc, R92C_CR, reg); 2356 2357 rtwn_write_1(sc, 0xfe10, 0x19); 2358 2359 return 0; 2360 } 2361 2362 static int 2363 rtwn_llt_init(struct rtwn_softc *sc) 2364 { 2365 int i, error; 2366 2367 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2368 2369 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2370 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2371 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2372 return error; 2373 } 2374 /* NB: 0xff indicates end-of-list. */ 2375 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2376 return error; 2377 /* 2378 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2379 * as ring buffer. 2380 */ 2381 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2382 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2383 return error; 2384 } 2385 /* Make the last page point to the beginning of the ring buffer. */ 2386 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2387 return error; 2388 } 2389 2390 static void 2391 rtwn_fw_reset(struct rtwn_softc *sc) 2392 { 2393 uint16_t reg; 2394 int ntries; 2395 2396 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2397 2398 /* Tell 8051 to reset itself. */ 2399 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2400 2401 /* Wait until 8051 resets by itself. */ 2402 for (ntries = 0; ntries < 100; ntries++) { 2403 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2404 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2405 goto sleep; 2406 DELAY(50); 2407 } 2408 /* Force 8051 reset. */ 2409 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2410 sleep: 2411 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2412 #if 0 2413 /* 2414 * We must sleep for one second to let the firmware settle. 2415 * Accessing registers too early will hang the whole system. 2416 */ 2417 tsleep(®, 0, "rtwnrst", hz); 2418 #else 2419 DELAY(1000 * 1000); 2420 #endif 2421 } 2422 2423 static int 2424 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2425 { 2426 uint32_t reg; 2427 int off, mlen, error = 0, i; 2428 2429 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2430 2431 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2432 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2433 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2434 2435 DELAY(5); 2436 2437 off = R92C_FW_START_ADDR; 2438 while (len > 0) { 2439 if (len > 196) 2440 mlen = 196; 2441 else if (len > 4) 2442 mlen = 4; 2443 else 2444 mlen = 1; 2445 for (i = 0; i < mlen; i++) 2446 rtwn_write_1(sc, off++, buf[i]); 2447 buf += mlen; 2448 len -= mlen; 2449 } 2450 2451 return error; 2452 } 2453 2454 static int 2455 rtwn_load_firmware(struct rtwn_softc *sc) 2456 { 2457 firmware_handle_t fwh; 2458 const struct r92c_fw_hdr *hdr; 2459 const char *name; 2460 u_char *fw, *ptr; 2461 size_t len; 2462 uint32_t reg; 2463 int mlen, ntries, page, error; 2464 2465 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2466 2467 /* Read firmware image from the filesystem. */ 2468 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2469 RTWN_CHIP_UMC_A_CUT) 2470 name = "rtl8192cfwU.bin"; 2471 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2472 name = "rtl8192cfwU_B.bin"; 2473 else 2474 name = "rtl8192cfw.bin"; 2475 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2476 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2477 aprint_error_dev(sc->sc_dev, 2478 "could not read firmware %s (error %d)\n", name, error); 2479 return error; 2480 } 2481 const size_t fwlen = len = firmware_get_size(fwh); 2482 fw = firmware_malloc(len); 2483 if (fw == NULL) { 2484 aprint_error_dev(sc->sc_dev, 2485 "failed to allocate firmware memory (size=%zu)\n", len); 2486 firmware_close(fwh); 2487 return ENOMEM; 2488 } 2489 error = firmware_read(fwh, 0, fw, len); 2490 firmware_close(fwh); 2491 if (error != 0) { 2492 aprint_error_dev(sc->sc_dev, 2493 "failed to read firmware (error %d)\n", error); 2494 firmware_free(fw, fwlen); 2495 return error; 2496 } 2497 2498 if (len < sizeof(*hdr)) { 2499 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2500 error = EINVAL; 2501 goto fail; 2502 } 2503 ptr = fw; 2504 hdr = (const struct r92c_fw_hdr *)ptr; 2505 /* Check if there is a valid FW header and skip it. */ 2506 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2507 (le16toh(hdr->signature) >> 4) == 0x92c) { 2508 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2509 le16toh(hdr->version), le16toh(hdr->subversion), 2510 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2511 ptr += sizeof(*hdr); 2512 len -= sizeof(*hdr); 2513 } 2514 2515 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2516 rtwn_fw_reset(sc); 2517 2518 /* Enable FW download. */ 2519 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2520 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2521 R92C_SYS_FUNC_EN_CPUEN); 2522 rtwn_write_1(sc, R92C_MCUFWDL, 2523 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2524 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2525 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2526 2527 /* Reset the FWDL checksum. */ 2528 rtwn_write_1(sc, R92C_MCUFWDL, 2529 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2530 2531 /* download firmware */ 2532 for (page = 0; len > 0; page++) { 2533 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2534 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2535 if (error != 0) { 2536 aprint_error_dev(sc->sc_dev, 2537 "could not load firmware page %d\n", page); 2538 goto fail; 2539 } 2540 ptr += mlen; 2541 len -= mlen; 2542 } 2543 2544 /* Disable FW download. */ 2545 rtwn_write_1(sc, R92C_MCUFWDL, 2546 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2547 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2548 2549 /* Wait for checksum report. */ 2550 for (ntries = 0; ntries < 1000; ntries++) { 2551 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2552 break; 2553 DELAY(5); 2554 } 2555 if (ntries == 1000) { 2556 aprint_error_dev(sc->sc_dev, 2557 "timeout waiting for checksum report\n"); 2558 error = ETIMEDOUT; 2559 goto fail; 2560 } 2561 2562 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2563 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2564 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2565 2566 /* Wait for firmware readiness. */ 2567 for (ntries = 0; ntries < 1000; ntries++) { 2568 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2569 break; 2570 DELAY(5); 2571 } 2572 if (ntries == 1000) { 2573 aprint_error_dev(sc->sc_dev, 2574 "timeout waiting for firmware readiness\n"); 2575 error = ETIMEDOUT; 2576 goto fail; 2577 } 2578 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2579 2580 fail: 2581 firmware_free(fw, fwlen); 2582 return error; 2583 } 2584 2585 static int 2586 rtwn_dma_init(struct rtwn_softc *sc) 2587 { 2588 uint32_t reg; 2589 int error; 2590 2591 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2592 2593 /* Initialize LLT table. */ 2594 error = rtwn_llt_init(sc); 2595 if (error != 0) 2596 return error; 2597 2598 /* Set number of pages for normal priority queue. */ 2599 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2600 rtwn_write_4(sc, R92C_RQPN, 2601 /* Set number of pages for public queue. */ 2602 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2603 /* Set number of pages for high priority queue. */ 2604 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2605 /* Set number of pages for low priority queue. */ 2606 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2607 /* Load values. */ 2608 R92C_RQPN_LD); 2609 2610 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2611 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2612 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2613 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2614 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2615 2616 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2617 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2618 reg |= 0xF771; 2619 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2620 2621 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2622 2623 /* Configure Tx DMA. */ 2624 rtwn_write_4(sc, R92C_BKQ_DESA, 2625 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2626 rtwn_write_4(sc, R92C_BEQ_DESA, 2627 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2628 rtwn_write_4(sc, R92C_VIQ_DESA, 2629 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2630 rtwn_write_4(sc, R92C_VOQ_DESA, 2631 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2632 rtwn_write_4(sc, R92C_BCNQ_DESA, 2633 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2634 rtwn_write_4(sc, R92C_MGQ_DESA, 2635 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2636 rtwn_write_4(sc, R92C_HQ_DESA, 2637 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2638 2639 /* Configure Rx DMA. */ 2640 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2641 2642 /* Set Tx/Rx transfer page boundary. */ 2643 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2644 2645 /* Set Tx/Rx transfer page size. */ 2646 rtwn_write_1(sc, R92C_PBP, 2647 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2648 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2649 return 0; 2650 } 2651 2652 static void 2653 rtwn_mac_init(struct rtwn_softc *sc) 2654 { 2655 int i; 2656 2657 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2658 2659 /* Write MAC initialization values. */ 2660 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2661 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2662 } 2663 2664 static void 2665 rtwn_bb_init(struct rtwn_softc *sc) 2666 { 2667 const struct rtwn_bb_prog *prog; 2668 uint32_t reg; 2669 int i; 2670 2671 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2672 2673 /* Enable BB and RF. */ 2674 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2675 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2676 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2677 R92C_SYS_FUNC_EN_DIO_RF); 2678 2679 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2680 2681 rtwn_write_1(sc, R92C_RF_CTRL, 2682 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2683 2684 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2685 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2686 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2687 R92C_SYS_FUNC_EN_BBRSTB); 2688 2689 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2690 2691 rtwn_write_4(sc, R92C_LEDCFG0, 2692 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2693 2694 /* Select BB programming. */ 2695 prog = (sc->chip & RTWN_CHIP_92C) ? 2696 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2697 2698 /* Write BB initialization values. */ 2699 for (i = 0; i < prog->count; i++) { 2700 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2701 DELAY(1); 2702 } 2703 2704 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2705 /* 8192C 1T only configuration. */ 2706 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2707 reg = (reg & ~0x00000003) | 0x2; 2708 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2709 2710 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2711 reg = (reg & ~0x00300033) | 0x00200022; 2712 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2713 2714 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2715 reg = (reg & ~0xff000000) | 0x45 << 24; 2716 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2717 2718 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2719 reg = (reg & ~0x000000ff) | 0x23; 2720 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2721 2722 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2723 reg = (reg & ~0x00000030) | 1 << 4; 2724 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2725 2726 reg = rtwn_bb_read(sc, 0xe74); 2727 reg = (reg & ~0x0c000000) | 2 << 26; 2728 rtwn_bb_write(sc, 0xe74, reg); 2729 reg = rtwn_bb_read(sc, 0xe78); 2730 reg = (reg & ~0x0c000000) | 2 << 26; 2731 rtwn_bb_write(sc, 0xe78, reg); 2732 reg = rtwn_bb_read(sc, 0xe7c); 2733 reg = (reg & ~0x0c000000) | 2 << 26; 2734 rtwn_bb_write(sc, 0xe7c, reg); 2735 reg = rtwn_bb_read(sc, 0xe80); 2736 reg = (reg & ~0x0c000000) | 2 << 26; 2737 rtwn_bb_write(sc, 0xe80, reg); 2738 reg = rtwn_bb_read(sc, 0xe88); 2739 reg = (reg & ~0x0c000000) | 2 << 26; 2740 rtwn_bb_write(sc, 0xe88, reg); 2741 } 2742 2743 /* Write AGC values. */ 2744 for (i = 0; i < prog->agccount; i++) { 2745 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2746 prog->agcvals[i]); 2747 DELAY(1); 2748 } 2749 2750 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2751 R92C_HSSI_PARAM2_CCK_HIPWR) 2752 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2753 } 2754 2755 static void 2756 rtwn_rf_init(struct rtwn_softc *sc) 2757 { 2758 const struct rtwn_rf_prog *prog; 2759 uint32_t reg, type; 2760 int i, j, idx, off; 2761 2762 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2763 2764 /* Select RF programming based on board type. */ 2765 if (!(sc->chip & RTWN_CHIP_92C)) { 2766 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2767 prog = rtl8188ce_rf_prog; 2768 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2769 prog = rtl8188ru_rf_prog; 2770 else 2771 prog = rtl8188cu_rf_prog; 2772 } else 2773 prog = rtl8192ce_rf_prog; 2774 2775 for (i = 0; i < sc->nrxchains; i++) { 2776 /* Save RF_ENV control type. */ 2777 idx = i / 2; 2778 off = (i % 2) * 16; 2779 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2780 type = (reg >> off) & 0x10; 2781 2782 /* Set RF_ENV enable. */ 2783 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2784 reg |= 0x100000; 2785 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2786 DELAY(1); 2787 /* Set RF_ENV output high. */ 2788 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2789 reg |= 0x10; 2790 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2791 DELAY(1); 2792 /* Set address and data lengths of RF registers. */ 2793 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2794 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2795 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2796 DELAY(1); 2797 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2798 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2799 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2800 DELAY(1); 2801 2802 /* Write RF initialization values for this chain. */ 2803 for (j = 0; j < prog[i].count; j++) { 2804 if (prog[i].regs[j] >= 0xf9 && 2805 prog[i].regs[j] <= 0xfe) { 2806 /* 2807 * These are fake RF registers offsets that 2808 * indicate a delay is required. 2809 */ 2810 DELAY(50); 2811 continue; 2812 } 2813 rtwn_rf_write(sc, i, prog[i].regs[j], 2814 prog[i].vals[j]); 2815 DELAY(1); 2816 } 2817 2818 /* Restore RF_ENV control type. */ 2819 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2820 reg &= ~(0x10 << off) | (type << off); 2821 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2822 2823 /* Cache RF register CHNLBW. */ 2824 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2825 } 2826 2827 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2828 RTWN_CHIP_UMC_A_CUT) { 2829 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2830 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2831 } 2832 } 2833 2834 static void 2835 rtwn_cam_init(struct rtwn_softc *sc) 2836 { 2837 2838 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2839 2840 /* Invalidate all CAM entries. */ 2841 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2842 } 2843 2844 static void 2845 rtwn_pa_bias_init(struct rtwn_softc *sc) 2846 { 2847 uint8_t reg; 2848 int i; 2849 2850 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2851 2852 for (i = 0; i < sc->nrxchains; i++) { 2853 if (sc->pa_setting & (1 << i)) 2854 continue; 2855 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2856 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2857 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2858 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2859 } 2860 if (!(sc->pa_setting & 0x10)) { 2861 reg = rtwn_read_1(sc, 0x16); 2862 reg = (reg & ~0xf0) | 0x90; 2863 rtwn_write_1(sc, 0x16, reg); 2864 } 2865 } 2866 2867 static void 2868 rtwn_rxfilter_init(struct rtwn_softc *sc) 2869 { 2870 2871 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2872 2873 /* Initialize Rx filter. */ 2874 /* TODO: use better filter for monitor mode. */ 2875 rtwn_write_4(sc, R92C_RCR, 2876 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2877 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2878 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2879 /* Accept all multicast frames. */ 2880 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2881 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2882 /* Accept all management frames. */ 2883 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2884 /* Reject all control frames. */ 2885 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2886 /* Accept all data frames. */ 2887 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2888 } 2889 2890 static void 2891 rtwn_edca_init(struct rtwn_softc *sc) 2892 { 2893 2894 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2895 2896 /* set spec SIFS (used in NAV) */ 2897 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2898 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2899 2900 /* set SIFS CCK/OFDM */ 2901 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2902 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2903 2904 /* TXOP */ 2905 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2906 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2907 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2908 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2909 } 2910 2911 static void 2912 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2913 uint16_t power[RTWN_RIDX_COUNT]) 2914 { 2915 uint32_t reg; 2916 2917 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2918 2919 /* Write per-CCK rate Tx power. */ 2920 if (chain == 0) { 2921 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2922 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2923 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2924 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2925 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2926 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2927 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2928 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2929 } else { 2930 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2931 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2932 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2933 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2934 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2935 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2936 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2937 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2938 } 2939 /* Write per-OFDM rate Tx power. */ 2940 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2941 SM(R92C_TXAGC_RATE06, power[ 4]) | 2942 SM(R92C_TXAGC_RATE09, power[ 5]) | 2943 SM(R92C_TXAGC_RATE12, power[ 6]) | 2944 SM(R92C_TXAGC_RATE18, power[ 7])); 2945 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2946 SM(R92C_TXAGC_RATE24, power[ 8]) | 2947 SM(R92C_TXAGC_RATE36, power[ 9]) | 2948 SM(R92C_TXAGC_RATE48, power[10]) | 2949 SM(R92C_TXAGC_RATE54, power[11])); 2950 /* Write per-MCS Tx power. */ 2951 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2952 SM(R92C_TXAGC_MCS00, power[12]) | 2953 SM(R92C_TXAGC_MCS01, power[13]) | 2954 SM(R92C_TXAGC_MCS02, power[14]) | 2955 SM(R92C_TXAGC_MCS03, power[15])); 2956 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2957 SM(R92C_TXAGC_MCS04, power[16]) | 2958 SM(R92C_TXAGC_MCS05, power[17]) | 2959 SM(R92C_TXAGC_MCS06, power[18]) | 2960 SM(R92C_TXAGC_MCS07, power[19])); 2961 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2962 SM(R92C_TXAGC_MCS08, power[20]) | 2963 SM(R92C_TXAGC_MCS09, power[21]) | 2964 SM(R92C_TXAGC_MCS10, power[22]) | 2965 SM(R92C_TXAGC_MCS11, power[23])); 2966 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2967 SM(R92C_TXAGC_MCS12, power[24]) | 2968 SM(R92C_TXAGC_MCS13, power[25]) | 2969 SM(R92C_TXAGC_MCS14, power[26]) | 2970 SM(R92C_TXAGC_MCS15, power[27])); 2971 } 2972 2973 static void 2974 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2975 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2976 uint16_t power[RTWN_RIDX_COUNT]) 2977 { 2978 struct ieee80211com *ic = &sc->sc_ic; 2979 struct r92c_rom *rom = &sc->rom; 2980 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2981 const struct rtwn_txpwr *base; 2982 int ridx, chan, group; 2983 2984 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2985 2986 /* Determine channel group. */ 2987 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2988 if (chan <= 3) 2989 group = 0; 2990 else if (chan <= 9) 2991 group = 1; 2992 else 2993 group = 2; 2994 2995 /* Get original Tx power based on board type and RF chain. */ 2996 if (!(sc->chip & RTWN_CHIP_92C)) { 2997 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2998 base = &rtl8188ru_txagc[chain]; 2999 else 3000 base = &rtl8192cu_txagc[chain]; 3001 } else 3002 base = &rtl8192cu_txagc[chain]; 3003 3004 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 3005 if (sc->regulatory == 0) { 3006 for (ridx = 0; ridx <= 3; ridx++) 3007 power[ridx] = base->pwr[0][ridx]; 3008 } 3009 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 3010 if (sc->regulatory == 3) { 3011 power[ridx] = base->pwr[0][ridx]; 3012 /* Apply vendor limits. */ 3013 if (extc != NULL) 3014 maxpwr = rom->ht40_max_pwr[group]; 3015 else 3016 maxpwr = rom->ht20_max_pwr[group]; 3017 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 3018 if (power[ridx] > maxpwr) 3019 power[ridx] = maxpwr; 3020 } else if (sc->regulatory == 1) { 3021 if (extc == NULL) 3022 power[ridx] = base->pwr[group][ridx]; 3023 } else if (sc->regulatory != 2) 3024 power[ridx] = base->pwr[0][ridx]; 3025 } 3026 3027 /* Compute per-CCK rate Tx power. */ 3028 cckpow = rom->cck_tx_pwr[chain][group]; 3029 for (ridx = 0; ridx <= 3; ridx++) { 3030 power[ridx] += cckpow; 3031 if (power[ridx] > R92C_MAX_TX_PWR) 3032 power[ridx] = R92C_MAX_TX_PWR; 3033 } 3034 3035 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3036 if (sc->ntxchains > 1) { 3037 /* Apply reduction for 2 spatial streams. */ 3038 diff = rom->ht40_2s_tx_pwr_diff[group]; 3039 diff = (diff >> (chain * 4)) & 0xf; 3040 htpow = (htpow > diff) ? htpow - diff : 0; 3041 } 3042 3043 /* Compute per-OFDM rate Tx power. */ 3044 diff = rom->ofdm_tx_pwr_diff[group]; 3045 diff = (diff >> (chain * 4)) & 0xf; 3046 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3047 for (ridx = 4; ridx <= 11; ridx++) { 3048 power[ridx] += ofdmpow; 3049 if (power[ridx] > R92C_MAX_TX_PWR) 3050 power[ridx] = R92C_MAX_TX_PWR; 3051 } 3052 3053 /* Compute per-MCS Tx power. */ 3054 if (extc == NULL) { 3055 diff = rom->ht20_tx_pwr_diff[group]; 3056 diff = (diff >> (chain * 4)) & 0xf; 3057 htpow += diff; /* HT40->HT20 correction. */ 3058 } 3059 for (ridx = 12; ridx <= 27; ridx++) { 3060 power[ridx] += htpow; 3061 if (power[ridx] > R92C_MAX_TX_PWR) 3062 power[ridx] = R92C_MAX_TX_PWR; 3063 } 3064 #ifdef RTWN_DEBUG 3065 if (rtwn_debug >= 4) { 3066 /* Dump per-rate Tx power values. */ 3067 printf("Tx power for chain %d:\n", chain); 3068 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3069 printf("Rate %d = %u\n", ridx, power[ridx]); 3070 } 3071 #endif 3072 } 3073 3074 static void 3075 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3076 struct ieee80211_channel *extc) 3077 { 3078 uint16_t power[RTWN_RIDX_COUNT]; 3079 int i; 3080 3081 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3082 3083 for (i = 0; i < sc->ntxchains; i++) { 3084 /* Compute per-rate Tx power values. */ 3085 rtwn_get_txpower(sc, i, c, extc, power); 3086 /* Write per-rate Tx power values to hardware. */ 3087 rtwn_write_txpower(sc, i, power); 3088 } 3089 } 3090 3091 static void 3092 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3093 struct ieee80211_channel *extc) 3094 { 3095 struct ieee80211com *ic = &sc->sc_ic; 3096 u_int chan; 3097 int i; 3098 3099 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3100 3101 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3102 3103 /* Set Tx power for this new channel. */ 3104 rtwn_set_txpower(sc, c, extc); 3105 3106 for (i = 0; i < sc->nrxchains; i++) { 3107 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3108 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3109 } 3110 #ifndef IEEE80211_NO_HT 3111 if (extc != NULL) { 3112 uint32_t reg; 3113 3114 /* Is secondary channel below or above primary? */ 3115 int prichlo = c->ic_freq < extc->ic_freq; 3116 3117 rtwn_write_1(sc, R92C_BWOPMODE, 3118 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3119 3120 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3121 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3122 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3123 3124 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3125 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3126 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3127 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3128 3129 /* Set CCK side band. */ 3130 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3131 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3132 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3133 3134 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3135 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3136 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3137 3138 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3139 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3140 ~R92C_FPGA0_ANAPARAM2_CBW20); 3141 3142 reg = rtwn_bb_read(sc, 0x818); 3143 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3144 rtwn_bb_write(sc, 0x818, reg); 3145 3146 /* Select 40MHz bandwidth. */ 3147 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3148 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3149 } else 3150 #endif 3151 { 3152 rtwn_write_1(sc, R92C_BWOPMODE, 3153 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3154 3155 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3156 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3157 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3158 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3159 3160 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3161 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3162 R92C_FPGA0_ANAPARAM2_CBW20); 3163 3164 /* Select 20MHz bandwidth. */ 3165 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3166 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3167 } 3168 } 3169 3170 static void 3171 rtwn_iq_calib(struct rtwn_softc *sc) 3172 { 3173 3174 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3175 3176 /* XXX */ 3177 } 3178 3179 static void 3180 rtwn_lc_calib(struct rtwn_softc *sc) 3181 { 3182 uint32_t rf_ac[2]; 3183 uint8_t txmode; 3184 int i; 3185 3186 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3187 3188 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3189 if ((txmode & 0x70) != 0) { 3190 /* Disable all continuous Tx. */ 3191 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3192 3193 /* Set RF mode to standby mode. */ 3194 for (i = 0; i < sc->nrxchains; i++) { 3195 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3196 rtwn_rf_write(sc, i, R92C_RF_AC, 3197 RW(rf_ac[i], R92C_RF_AC_MODE, 3198 R92C_RF_AC_MODE_STANDBY)); 3199 } 3200 } else { 3201 /* Block all Tx queues. */ 3202 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3203 } 3204 /* Start calibration. */ 3205 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3206 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3207 3208 /* Give calibration the time to complete. */ 3209 DELAY(100); 3210 3211 /* Restore configuration. */ 3212 if ((txmode & 0x70) != 0) { 3213 /* Restore Tx mode. */ 3214 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3215 /* Restore RF mode. */ 3216 for (i = 0; i < sc->nrxchains; i++) 3217 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3218 } else { 3219 /* Unblock all Tx queues. */ 3220 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3221 } 3222 } 3223 3224 static void 3225 rtwn_temp_calib(struct rtwn_softc *sc) 3226 { 3227 int temp; 3228 3229 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3230 3231 if (sc->thcal_state == 0) { 3232 /* Start measuring temperature. */ 3233 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3234 sc->thcal_state = 1; 3235 return; 3236 } 3237 sc->thcal_state = 0; 3238 3239 /* Read measured temperature. */ 3240 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3241 if (temp == 0) /* Read failed, skip. */ 3242 return; 3243 DPRINTFN(2, ("temperature=%d\n", temp)); 3244 3245 /* 3246 * Redo IQ and LC calibration if temperature changed significantly 3247 * since last calibration. 3248 */ 3249 if (sc->thcal_lctemp == 0) { 3250 /* First calibration is performed in rtwn_init(). */ 3251 sc->thcal_lctemp = temp; 3252 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3253 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3254 sc->thcal_lctemp, temp)); 3255 rtwn_iq_calib(sc); 3256 rtwn_lc_calib(sc); 3257 /* Record temperature of last calibration. */ 3258 sc->thcal_lctemp = temp; 3259 } 3260 } 3261 3262 static int 3263 rtwn_init(struct ifnet *ifp) 3264 { 3265 struct rtwn_softc *sc = ifp->if_softc; 3266 struct ieee80211com *ic = &sc->sc_ic; 3267 uint32_t reg; 3268 int i, error; 3269 3270 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3271 3272 /* Init firmware commands ring. */ 3273 sc->fwcur = 0; 3274 3275 /* Power on adapter. */ 3276 error = rtwn_power_on(sc); 3277 if (error != 0) { 3278 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3279 goto fail; 3280 } 3281 3282 /* Initialize DMA. */ 3283 error = rtwn_dma_init(sc); 3284 if (error != 0) { 3285 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3286 goto fail; 3287 } 3288 3289 /* Set info size in Rx descriptors (in 64-bit words). */ 3290 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3291 3292 /* Disable interrupts. */ 3293 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3294 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3295 3296 /* Set MAC address. */ 3297 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3298 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3299 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3300 3301 /* Set initial network type. */ 3302 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3303 3304 rtwn_rxfilter_init(sc); 3305 3306 reg = rtwn_read_4(sc, R92C_RRSR); 3307 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3308 rtwn_write_4(sc, R92C_RRSR, reg); 3309 3310 /* Set short/long retry limits. */ 3311 rtwn_write_2(sc, R92C_RL, 3312 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3313 3314 /* Initialize EDCA parameters. */ 3315 rtwn_edca_init(sc); 3316 3317 /* Set data and response automatic rate fallback retry counts. */ 3318 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3319 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3320 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3321 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3322 3323 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3324 3325 /* Set ACK timeout. */ 3326 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3327 3328 /* Initialize beacon parameters. */ 3329 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3330 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3331 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3332 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3333 3334 /* Setup AMPDU aggregation. */ 3335 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3336 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3337 3338 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3339 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3340 3341 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3342 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3343 3344 /* Load 8051 microcode. */ 3345 error = rtwn_load_firmware(sc); 3346 if (error != 0) 3347 goto fail; 3348 3349 /* Initialize MAC/BB/RF blocks. */ 3350 rtwn_mac_init(sc); 3351 rtwn_bb_init(sc); 3352 rtwn_rf_init(sc); 3353 3354 /* Turn CCK and OFDM blocks on. */ 3355 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3356 reg |= R92C_RFMOD_CCK_EN; 3357 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3358 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3359 reg |= R92C_RFMOD_OFDM_EN; 3360 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3361 3362 /* Clear per-station keys table. */ 3363 rtwn_cam_init(sc); 3364 3365 /* Enable hardware sequence numbering. */ 3366 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3367 3368 /* Perform LO and IQ calibrations. */ 3369 rtwn_iq_calib(sc); 3370 /* Perform LC calibration. */ 3371 rtwn_lc_calib(sc); 3372 3373 rtwn_pa_bias_init(sc); 3374 3375 /* Initialize GPIO setting. */ 3376 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3377 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3378 3379 /* Fix for lower temperature. */ 3380 rtwn_write_1(sc, 0x15, 0xe9); 3381 3382 /* Set default channel. */ 3383 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3384 3385 /* Clear pending interrupts. */ 3386 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3387 3388 /* Enable interrupts. */ 3389 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3390 3391 /* We're ready to go. */ 3392 ifp->if_flags &= ~IFF_OACTIVE; 3393 ifp->if_flags |= IFF_RUNNING; 3394 3395 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3396 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3397 else 3398 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3399 3400 return 0; 3401 3402 fail: 3403 rtwn_stop(ifp, 1); 3404 return error; 3405 } 3406 3407 static void 3408 rtwn_init_task(void *arg) 3409 { 3410 struct rtwn_softc *sc = arg; 3411 struct ifnet *ifp = GET_IFP(sc); 3412 int s; 3413 3414 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3415 3416 s = splnet(); 3417 3418 rtwn_stop(ifp, 0); 3419 3420 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3421 rtwn_init(ifp); 3422 3423 splx(s); 3424 } 3425 3426 static void 3427 rtwn_stop(struct ifnet *ifp, int disable) 3428 { 3429 struct rtwn_softc *sc = ifp->if_softc; 3430 struct ieee80211com *ic = &sc->sc_ic; 3431 uint16_t reg; 3432 int s, i; 3433 3434 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3435 3436 sc->sc_tx_timer = 0; 3437 ifp->if_timer = 0; 3438 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3439 3440 callout_stop(&sc->scan_to); 3441 callout_stop(&sc->calib_to); 3442 3443 s = splnet(); 3444 3445 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3446 3447 /* Disable interrupts. */ 3448 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3449 3450 /* Pause MAC TX queue */ 3451 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3452 3453 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3454 3455 /* Reset BB state machine */ 3456 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3457 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3458 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3459 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3460 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3461 3462 reg = rtwn_read_2(sc, R92C_CR); 3463 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3464 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3465 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3466 R92C_CR_ENSEC); 3467 rtwn_write_2(sc, R92C_CR, reg); 3468 3469 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3470 rtwn_fw_reset(sc); 3471 3472 /* Reset MAC and Enable 8051 */ 3473 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3474 3475 /* TODO: linux does additional btcoex stuff here */ 3476 3477 /* Disable AFE PLL */ 3478 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3479 /* Enter PFM mode */ 3480 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3481 /* Gated AFE DIG_CLOCK */ 3482 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3483 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3484 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3485 3486 for (i = 0; i < RTWN_NTXQUEUES; i++) 3487 rtwn_reset_tx_list(sc, i); 3488 rtwn_reset_rx_list(sc); 3489 3490 splx(s); 3491 } 3492 3493 static int 3494 rtwn_intr(void *xsc) 3495 { 3496 struct rtwn_softc *sc = xsc; 3497 uint32_t status; 3498 3499 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3500 return 0; 3501 3502 status = rtwn_read_4(sc, R92C_HISR); 3503 if (status == 0 || status == 0xffffffff) 3504 return 0; 3505 3506 /* Disable interrupts. */ 3507 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3508 3509 softint_schedule(sc->sc_soft_ih); 3510 return 1; 3511 } 3512 3513 static void 3514 rtwn_softintr(void *xsc) 3515 { 3516 struct rtwn_softc *sc = xsc; 3517 uint32_t status; 3518 int i, s; 3519 3520 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3521 return; 3522 3523 status = rtwn_read_4(sc, R92C_HISR); 3524 if (status == 0 || status == 0xffffffff) 3525 goto out; 3526 3527 /* Ack interrupts. */ 3528 rtwn_write_4(sc, R92C_HISR, status); 3529 3530 /* Vendor driver treats RX errors like ROK... */ 3531 if (status & RTWN_INT_ENABLE_RX) { 3532 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3533 struct r92c_rx_desc_pci *rx_desc = &sc->rx_ring.desc[i]; 3534 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3535 3536 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3537 continue; 3538 3539 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3540 } 3541 } 3542 3543 if (status & R92C_IMR_BDOK) 3544 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3545 if (status & R92C_IMR_HIGHDOK) 3546 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3547 if (status & R92C_IMR_MGNTDOK) 3548 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3549 if (status & R92C_IMR_BKDOK) 3550 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3551 if (status & R92C_IMR_BEDOK) 3552 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3553 if (status & R92C_IMR_VIDOK) 3554 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3555 if (status & R92C_IMR_VODOK) 3556 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3557 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3558 struct ifnet *ifp = GET_IFP(sc); 3559 s = splnet(); 3560 ifp->if_flags &= ~IFF_OACTIVE; 3561 rtwn_start(ifp); 3562 splx(s); 3563 } 3564 3565 out: 3566 /* Enable interrupts. */ 3567 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3568 } 3569
Indexes created Thu Oct 02 01:09:59 GMT 2025