if_rtwn.c revision 1.8
1 /* $NetBSD: if_rtwn.c,v 1.8 2016/06/10 13:27:14 ozaki-r Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.8 2016/06/10 13:27:14 ozaki-r Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 178 /* Aliases. */ 179 #define rtwn_bb_write rtwn_write_4 180 #define rtwn_bb_read rtwn_read_4 181 182 static const struct rtwn_device * 183 rtwn_lookup(const struct pci_attach_args *pa) 184 { 185 const struct rtwn_device *rd; 186 int i; 187 188 for (i = 0; i < __arraycount(rtwn_devices); i++) { 189 rd = &rtwn_devices[i]; 190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 191 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 192 return rd; 193 } 194 return NULL; 195 } 196 197 static int 198 rtwn_match(device_t parent, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 202 if (rtwn_lookup(pa) != NULL) 203 return 1; 204 return 0; 205 } 206 207 static void 208 rtwn_attach(device_t parent, device_t self, void *aux) 209 { 210 struct rtwn_softc *sc = device_private(self); 211 struct pci_attach_args *pa = aux; 212 struct ieee80211com *ic = &sc->sc_ic; 213 struct ifnet *ifp = GET_IFP(sc); 214 int i, error; 215 pcireg_t memtype; 216 const char *intrstr; 217 char intrbuf[PCI_INTRSTR_LEN]; 218 219 sc->sc_dev = self; 220 sc->sc_dmat = pa->pa_dmat; 221 sc->sc_pc = pa->pa_pc; 222 sc->sc_tag = pa->pa_tag; 223 224 pci_aprint_devinfo(pa, NULL); 225 226 callout_init(&sc->scan_to, 0); 227 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 228 callout_init(&sc->calib_to, 0); 229 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 230 231 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 232 233 /* Power up the device */ 234 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 235 236 /* Map control/status registers. */ 237 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 238 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 239 &sc->sc_sh, NULL, &sc->sc_mapsize); 240 if (error != 0) { 241 aprint_error_dev(self, "can't map mem space\n"); 242 return; 243 } 244 245 /* Install interrupt handler. */ 246 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 247 aprint_error_dev(self, "can't map interrupt\n"); 248 return; 249 } 250 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 251 sizeof(intrbuf)); 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 253 rtwn_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(self, "can't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 return; 260 } 261 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 262 263 error = rtwn_read_chipid(sc); 264 if (error != 0) { 265 aprint_error_dev(self, "unsupported test or unknown chip\n"); 266 return; 267 } 268 269 /* Disable PCIe Active State Power Management (ASPM). */ 270 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 271 &sc->sc_cap_off, NULL)) { 272 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 273 sc->sc_cap_off + PCIE_LCSR); 274 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 275 pci_conf_write(sc->sc_pc, sc->sc_tag, 276 sc->sc_cap_off + PCIE_LCSR, lcsr); 277 } 278 279 /* Allocate Tx/Rx buffers. */ 280 error = rtwn_alloc_rx_list(sc); 281 if (error != 0) { 282 aprint_error_dev(self, "could not allocate Rx buffers\n"); 283 return; 284 } 285 for (i = 0; i < RTWN_NTXQUEUES; i++) { 286 error = rtwn_alloc_tx_list(sc, i); 287 if (error != 0) { 288 aprint_error_dev(self, 289 "could not allocate Tx buffers\n"); 290 return; 291 } 292 } 293 294 /* Determine number of Tx/Rx chains. */ 295 if (sc->chip & RTWN_CHIP_92C) { 296 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 297 sc->nrxchains = 2; 298 } else { 299 sc->ntxchains = 1; 300 sc->nrxchains = 1; 301 } 302 rtwn_read_rom(sc); 303 304 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 305 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 306 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 307 308 /* 309 * Setup the 802.11 device. 310 */ 311 ic->ic_ifp = ifp; 312 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 313 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 314 ic->ic_state = IEEE80211_S_INIT; 315 316 /* Set device capabilities. */ 317 ic->ic_caps = 318 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 319 IEEE80211_C_IBSS | /* IBSS mode supported */ 320 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 321 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 322 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 323 IEEE80211_C_WME | /* 802.11e */ 324 IEEE80211_C_WPA; /* WPA/RSN. */ 325 326 #ifndef IEEE80211_NO_HT 327 /* Set HT capabilities. */ 328 ic->ic_htcaps = 329 IEEE80211_HTCAP_CBW20_40 | 330 IEEE80211_HTCAP_DSSSCCK40; 331 /* Set supported HT rates. */ 332 for (i = 0; i < sc->nrxchains; i++) 333 ic->ic_sup_mcs[i] = 0xff; 334 #endif 335 336 /* Set supported .11b and .11g rates. */ 337 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 338 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 339 340 /* Set supported .11b and .11g channels (1 through 14). */ 341 for (i = 1; i <= 14; i++) { 342 ic->ic_channels[i].ic_freq = 343 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 344 ic->ic_channels[i].ic_flags = 345 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 346 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 347 } 348 349 ifp->if_softc = sc; 350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 351 ifp->if_init = rtwn_init; 352 ifp->if_ioctl = rtwn_ioctl; 353 ifp->if_start = rtwn_start; 354 ifp->if_watchdog = rtwn_watchdog; 355 IFQ_SET_READY(&ifp->if_snd); 356 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 357 358 if_initialize(ifp); 359 ieee80211_ifattach(ic); 360 if_register(ifp); 361 /* Use common softint-based if_input */ 362 ifp->if_percpuq = if_percpuq_create(ifp); 363 364 /* override default methods */ 365 ic->ic_newassoc = rtwn_newassoc; 366 ic->ic_reset = rtwn_reset; 367 ic->ic_wme.wme_update = rtwn_wme_update; 368 369 /* Override state transition machine. */ 370 sc->sc_newstate = ic->ic_newstate; 371 ic->ic_newstate = rtwn_newstate; 372 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 373 374 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 375 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 376 &sc->sc_drvbpf); 377 378 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 379 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 380 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 381 382 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 383 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 384 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 385 386 ieee80211_announce(ic); 387 388 if (!pmf_device_register(self, NULL, NULL)) 389 aprint_error_dev(self, "couldn't establish power handler\n"); 390 } 391 392 static int 393 rtwn_detach(device_t self, int flags) 394 { 395 struct rtwn_softc *sc = device_private(self); 396 struct ieee80211com *ic = &sc->sc_ic; 397 struct ifnet *ifp = GET_IFP(sc); 398 int s, i; 399 400 callout_stop(&sc->scan_to); 401 callout_stop(&sc->calib_to); 402 403 s = splnet(); 404 405 if (ifp->if_softc != NULL) { 406 rtwn_stop(ifp, 0); 407 408 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 409 bpf_detach(ifp); 410 ieee80211_ifdetach(ic); 411 if_detach(ifp); 412 } 413 414 /* Free Tx/Rx buffers. */ 415 for (i = 0; i < RTWN_NTXQUEUES; i++) 416 rtwn_free_tx_list(sc, i); 417 rtwn_free_rx_list(sc); 418 419 splx(s); 420 421 callout_destroy(&sc->scan_to); 422 callout_destroy(&sc->calib_to); 423 424 if (sc->init_task != NULL) 425 softint_disestablish(sc->init_task); 426 427 if (sc->sc_ih != NULL) { 428 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 429 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 430 } 431 432 pmf_device_deregister(self); 433 434 return 0; 435 } 436 437 static int 438 rtwn_activate(device_t self, enum devact act) 439 { 440 struct rtwn_softc *sc = device_private(self); 441 struct ifnet *ifp = GET_IFP(sc); 442 443 switch (act) { 444 case DVACT_DEACTIVATE: 445 if (ifp->if_flags & IFF_RUNNING) 446 rtwn_stop(ifp, 0); 447 return 0; 448 default: 449 return EOPNOTSUPP; 450 } 451 } 452 453 static void 454 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 455 bus_addr_t addr, size_t len, int idx) 456 { 457 458 memset(desc, 0, sizeof(*desc)); 459 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 460 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 461 desc->rxbufaddr = htole32(addr); 462 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 463 BUS_SPACE_BARRIER_WRITE); 464 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 465 } 466 467 static int 468 rtwn_alloc_rx_list(struct rtwn_softc *sc) 469 { 470 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 471 struct rtwn_rx_data *rx_data; 472 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 473 int i, error = 0; 474 475 /* Allocate Rx descriptors. */ 476 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 477 &rx_ring->map); 478 if (error != 0) { 479 aprint_error_dev(sc->sc_dev, 480 "could not create rx desc DMA map\n"); 481 rx_ring->map = NULL; 482 goto fail; 483 } 484 485 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 486 &rx_ring->nsegs, BUS_DMA_NOWAIT); 487 if (error != 0) { 488 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 489 goto fail; 490 } 491 492 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 493 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 494 if (error != 0) { 495 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 496 rx_ring->desc = NULL; 497 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 498 goto fail; 499 } 500 memset(rx_ring->desc, 0, size); 501 502 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 503 1, size, BUS_DMA_NOWAIT); 504 if (error != 0) { 505 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 506 goto fail; 507 } 508 509 /* Allocate Rx buffers. */ 510 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 511 rx_data = &rx_ring->rx_data[i]; 512 513 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 514 0, BUS_DMA_NOWAIT, &rx_data->map); 515 if (error != 0) { 516 aprint_error_dev(sc->sc_dev, 517 "could not create rx buf DMA map\n"); 518 goto fail; 519 } 520 521 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 522 if (__predict_false(rx_data->m == NULL)) { 523 aprint_error_dev(sc->sc_dev, 524 "couldn't allocate rx mbuf\n"); 525 error = ENOMEM; 526 goto fail; 527 } 528 MCLGET(rx_data->m, M_DONTWAIT); 529 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 530 aprint_error_dev(sc->sc_dev, 531 "couldn't allocate rx mbuf cluster\n"); 532 m_free(rx_data->m); 533 rx_data->m = NULL; 534 error = ENOMEM; 535 goto fail; 536 } 537 538 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 539 mtod(rx_data->m, void *), MCLBYTES, NULL, 540 BUS_DMA_NOWAIT | BUS_DMA_READ); 541 if (error != 0) { 542 aprint_error_dev(sc->sc_dev, 543 "could not load rx buf DMA map\n"); 544 goto fail; 545 } 546 547 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 548 BUS_DMASYNC_PREREAD); 549 550 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 551 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 552 } 553 fail: if (error != 0) 554 rtwn_free_rx_list(sc); 555 return error; 556 } 557 558 static void 559 rtwn_reset_rx_list(struct rtwn_softc *sc) 560 { 561 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 562 struct rtwn_rx_data *rx_data; 563 int i; 564 565 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 566 rx_data = &rx_ring->rx_data[i]; 567 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 568 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 569 } 570 } 571 572 static void 573 rtwn_free_rx_list(struct rtwn_softc *sc) 574 { 575 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 576 struct rtwn_rx_data *rx_data; 577 int i, s; 578 579 s = splnet(); 580 581 if (rx_ring->map) { 582 if (rx_ring->desc) { 583 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 584 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 585 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 586 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 587 rx_ring->nsegs); 588 rx_ring->desc = NULL; 589 } 590 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 591 rx_ring->map = NULL; 592 } 593 594 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 595 rx_data = &rx_ring->rx_data[i]; 596 597 if (rx_data->m != NULL) { 598 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 599 m_freem(rx_data->m); 600 rx_data->m = NULL; 601 } 602 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 603 rx_data->map = NULL; 604 } 605 606 splx(s); 607 } 608 609 static int 610 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 611 { 612 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 613 struct rtwn_tx_data *tx_data; 614 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 615 int i = 0, error = 0; 616 617 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 618 &tx_ring->map); 619 if (error != 0) { 620 aprint_error_dev(sc->sc_dev, 621 "could not create tx ring DMA map\n"); 622 goto fail; 623 } 624 625 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 626 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 627 if (error != 0) { 628 aprint_error_dev(sc->sc_dev, 629 "could not allocate tx ring DMA memory\n"); 630 goto fail; 631 } 632 633 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 634 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 635 if (error != 0) { 636 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 637 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 638 goto fail; 639 } 640 memset(tx_ring->desc, 0, size); 641 642 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 643 size, NULL, BUS_DMA_NOWAIT); 644 if (error != 0) { 645 aprint_error_dev(sc->sc_dev, 646 "could not load tx ring DMA map\n"); 647 goto fail; 648 } 649 650 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 651 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 652 653 /* setup tx desc */ 654 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 655 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 656 657 tx_data = &tx_ring->tx_data[i]; 658 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 659 0, BUS_DMA_NOWAIT, &tx_data->map); 660 if (error != 0) { 661 aprint_error_dev(sc->sc_dev, 662 "could not create tx buf DMA map\n"); 663 goto fail; 664 } 665 tx_data->m = NULL; 666 tx_data->ni = NULL; 667 } 668 669 fail: 670 if (error != 0) 671 rtwn_free_tx_list(sc, qid); 672 return error; 673 } 674 675 static void 676 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 677 { 678 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 679 int i; 680 681 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 682 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 683 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 684 685 memset(desc, 0, sizeof(*desc) - 686 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 687 sizeof(desc->nextdescaddr))); 688 689 if (tx_data->m != NULL) { 690 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 691 m_freem(tx_data->m); 692 tx_data->m = NULL; 693 ieee80211_free_node(tx_data->ni); 694 tx_data->ni = NULL; 695 } 696 } 697 698 sc->qfullmsk &= ~(1 << qid); 699 tx_ring->queued = 0; 700 tx_ring->cur = 0; 701 } 702 703 static void 704 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 705 { 706 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 707 struct rtwn_tx_data *tx_data; 708 int i; 709 710 if (tx_ring->map != NULL) { 711 if (tx_ring->desc != NULL) { 712 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 713 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 714 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 715 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 716 tx_ring->nsegs); 717 } 718 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 719 } 720 721 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 722 tx_data = &tx_ring->tx_data[i]; 723 724 if (tx_data->m != NULL) { 725 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 726 m_freem(tx_data->m); 727 tx_data->m = NULL; 728 } 729 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 730 } 731 732 sc->qfullmsk &= ~(1 << qid); 733 tx_ring->queued = 0; 734 tx_ring->cur = 0; 735 } 736 737 static void 738 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 739 { 740 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 741 } 742 743 static void 744 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 745 { 746 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 747 } 748 749 static void 750 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 751 { 752 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 753 } 754 755 static uint8_t 756 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 757 { 758 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 759 } 760 761 static uint16_t 762 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 763 { 764 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 765 } 766 767 static uint32_t 768 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 769 { 770 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 771 } 772 773 static int 774 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 775 { 776 struct r92c_fw_cmd cmd; 777 uint8_t *cp; 778 int fwcur; 779 int ntries; 780 781 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 782 device_xname(sc->sc_dev), __func__, id, buf, len)); 783 784 fwcur = sc->fwcur; 785 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 786 787 /* Wait for current FW box to be empty. */ 788 for (ntries = 0; ntries < 100; ntries++) { 789 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 790 break; 791 DELAY(1); 792 } 793 if (ntries == 100) { 794 aprint_error_dev(sc->sc_dev, 795 "could not send firmware command %d\n", id); 796 return ETIMEDOUT; 797 } 798 799 memset(&cmd, 0, sizeof(cmd)); 800 KASSERT(len <= sizeof(cmd.msg)); 801 memcpy(cmd.msg, buf, len); 802 803 /* Write the first word last since that will trigger the FW. */ 804 cp = (uint8_t *)&cmd; 805 if (len >= 4) { 806 cmd.id = id | R92C_CMD_FLAG_EXT; 807 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 808 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 809 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 810 } else { 811 cmd.id = id; 812 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 813 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 814 } 815 816 /* Give firmware some time for processing. */ 817 DELAY(2000); 818 819 return 0; 820 } 821 822 static void 823 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 824 { 825 826 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 827 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 828 } 829 830 static uint32_t 831 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 832 { 833 uint32_t reg[R92C_MAX_CHAINS], val; 834 835 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 836 if (chain != 0) 837 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 838 839 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 840 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 841 DELAY(1000); 842 843 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 844 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 845 R92C_HSSI_PARAM2_READ_EDGE); 846 DELAY(1000); 847 848 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 849 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 850 DELAY(1000); 851 852 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 853 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 854 else 855 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 856 return MS(val, R92C_LSSI_READBACK_DATA); 857 } 858 859 static int 860 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 861 { 862 int ntries; 863 864 rtwn_write_4(sc, R92C_LLT_INIT, 865 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 866 SM(R92C_LLT_INIT_ADDR, addr) | 867 SM(R92C_LLT_INIT_DATA, data)); 868 /* Wait for write operation to complete. */ 869 for (ntries = 0; ntries < 20; ntries++) { 870 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 871 R92C_LLT_INIT_OP_NO_ACTIVE) 872 return 0; 873 DELAY(5); 874 } 875 return ETIMEDOUT; 876 } 877 878 static uint8_t 879 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 880 { 881 uint32_t reg; 882 int ntries; 883 884 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 885 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 886 reg &= ~R92C_EFUSE_CTRL_VALID; 887 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 888 /* Wait for read operation to complete. */ 889 for (ntries = 0; ntries < 100; ntries++) { 890 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 891 if (reg & R92C_EFUSE_CTRL_VALID) 892 return MS(reg, R92C_EFUSE_CTRL_DATA); 893 DELAY(5); 894 } 895 aprint_error_dev(sc->sc_dev, 896 "could not read efuse byte at address 0x%x\n", addr); 897 return 0xff; 898 } 899 900 static void 901 rtwn_efuse_read(struct rtwn_softc *sc) 902 { 903 uint8_t *rom = (uint8_t *)&sc->rom; 904 uint32_t reg; 905 uint16_t addr = 0; 906 uint8_t off, msk; 907 int i; 908 909 rtwn_efuse_switch_power(sc); 910 911 memset(&sc->rom, 0xff, sizeof(sc->rom)); 912 while (addr < 512) { 913 reg = rtwn_efuse_read_1(sc, addr); 914 if (reg == 0xff) 915 break; 916 addr++; 917 off = reg >> 4; 918 msk = reg & 0xf; 919 for (i = 0; i < 4; i++) { 920 if (msk & (1 << i)) 921 continue; 922 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 923 addr++; 924 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 925 addr++; 926 } 927 } 928 #ifdef RTWN_DEBUG 929 if (rtwn_debug >= 2) { 930 /* Dump ROM content. */ 931 printf("\n"); 932 for (i = 0; i < sizeof(sc->rom); i++) 933 printf("%02x:", rom[i]); 934 printf("\n"); 935 } 936 #endif 937 } 938 939 static void 940 rtwn_efuse_switch_power(struct rtwn_softc *sc) 941 { 942 uint32_t reg; 943 944 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 945 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 946 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 947 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 948 } 949 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 950 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 951 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 952 reg | R92C_SYS_FUNC_EN_ELDR); 953 } 954 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 955 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 956 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 957 rtwn_write_2(sc, R92C_SYS_CLKR, 958 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 959 } 960 } 961 962 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 963 static int 964 rtwn_read_chipid(struct rtwn_softc *sc) 965 { 966 uint32_t reg; 967 968 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 969 970 reg = rtwn_read_4(sc, R92C_SYS_CFG); 971 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 972 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 973 /* Unsupported test chip. */ 974 return EIO; 975 976 if (reg & R92C_SYS_CFG_TYPE_92C) { 977 sc->chip |= RTWN_CHIP_92C; 978 /* Check if it is a castrated 8192C. */ 979 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 980 R92C_HPON_FSM_CHIP_BONDING_ID) == 981 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 982 sc->chip |= RTWN_CHIP_92C_1T2R; 983 } 984 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 985 sc->chip |= RTWN_CHIP_UMC; 986 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 987 sc->chip |= RTWN_CHIP_UMC_A_CUT; 988 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 989 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 990 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 991 else 992 /* Unsupported unknown chip. */ 993 return EIO; 994 } 995 return 0; 996 } 997 998 static void 999 rtwn_read_rom(struct rtwn_softc *sc) 1000 { 1001 struct ieee80211com *ic = &sc->sc_ic; 1002 struct r92c_rom *rom = &sc->rom; 1003 1004 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1005 1006 /* Read full ROM image. */ 1007 rtwn_efuse_read(sc); 1008 1009 if (rom->id != 0x8129) { 1010 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1011 rom->id); 1012 } 1013 1014 /* XXX Weird but this is what the vendor driver does. */ 1015 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1016 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1017 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1018 1019 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1020 sc->pa_setting, sc->board_type, sc->regulatory)); 1021 1022 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1023 } 1024 1025 static int 1026 rtwn_media_change(struct ifnet *ifp) 1027 { 1028 int error; 1029 1030 error = ieee80211_media_change(ifp); 1031 if (error != ENETRESET) 1032 return error; 1033 1034 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1035 (IFF_UP | IFF_RUNNING)) { 1036 rtwn_stop(ifp, 0); 1037 error = rtwn_init(ifp); 1038 } 1039 return error; 1040 } 1041 1042 /* 1043 * Initialize rate adaptation in firmware. 1044 */ 1045 static int 1046 rtwn_ra_init(struct rtwn_softc *sc) 1047 { 1048 static const uint8_t map[] = { 1049 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1050 }; 1051 struct ieee80211com *ic = &sc->sc_ic; 1052 struct ieee80211_node *ni = ic->ic_bss; 1053 struct ieee80211_rateset *rs = &ni->ni_rates; 1054 struct r92c_fw_cmd_macid_cfg cmd; 1055 uint32_t rates, basicrates; 1056 uint8_t mode; 1057 int maxrate, maxbasicrate, error, i, j; 1058 1059 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1060 1061 /* Get normal and basic rates mask. */ 1062 rates = basicrates = 0; 1063 maxrate = maxbasicrate = 0; 1064 for (i = 0; i < rs->rs_nrates; i++) { 1065 /* Convert 802.11 rate to HW rate index. */ 1066 for (j = 0; j < __arraycount(map); j++) 1067 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1068 break; 1069 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1070 continue; 1071 rates |= 1 << j; 1072 if (j > maxrate) 1073 maxrate = j; 1074 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1075 basicrates |= 1 << j; 1076 if (j > maxbasicrate) 1077 maxbasicrate = j; 1078 } 1079 } 1080 if (ic->ic_curmode == IEEE80211_MODE_11B) 1081 mode = R92C_RAID_11B; 1082 else 1083 mode = R92C_RAID_11BG; 1084 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1085 device_xname(sc->sc_dev), mode, rates, basicrates)); 1086 if (basicrates == 0) 1087 basicrates |= 1; /* add 1Mbps */ 1088 1089 /* Set rates mask for group addressed frames. */ 1090 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1091 cmd.mask = htole32((mode << 28) | basicrates); 1092 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1093 if (error != 0) { 1094 aprint_error_dev(sc->sc_dev, 1095 "could not add broadcast station\n"); 1096 return error; 1097 } 1098 /* Set initial MRR rate. */ 1099 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1100 maxbasicrate)); 1101 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1102 1103 /* Set rates mask for unicast frames. */ 1104 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1105 cmd.mask = htole32((mode << 28) | rates); 1106 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1107 if (error != 0) { 1108 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1109 return error; 1110 } 1111 /* Set initial MRR rate. */ 1112 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1113 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1114 1115 /* Configure Automatic Rate Fallback Register. */ 1116 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1117 if (rates & 0x0c) 1118 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1119 else 1120 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1121 } else 1122 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1123 1124 /* Indicate highest supported rate. */ 1125 ni->ni_txrate = rs->rs_nrates - 1; 1126 return 0; 1127 } 1128 1129 static int 1130 rtwn_get_nettype(struct rtwn_softc *sc) 1131 { 1132 struct ieee80211com *ic = &sc->sc_ic; 1133 int type; 1134 1135 switch (ic->ic_opmode) { 1136 case IEEE80211_M_STA: 1137 type = R92C_CR_NETTYPE_INFRA; 1138 break; 1139 1140 case IEEE80211_M_HOSTAP: 1141 type = R92C_CR_NETTYPE_AP; 1142 break; 1143 1144 case IEEE80211_M_IBSS: 1145 type = R92C_CR_NETTYPE_ADHOC; 1146 break; 1147 1148 default: 1149 type = R92C_CR_NETTYPE_NOLINK; 1150 break; 1151 } 1152 1153 return type; 1154 } 1155 1156 static void 1157 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1158 { 1159 uint32_t reg; 1160 1161 reg = rtwn_read_4(sc, R92C_CR); 1162 reg = RW(reg, R92C_CR_NETTYPE, type); 1163 rtwn_write_4(sc, R92C_CR, reg); 1164 } 1165 1166 static void 1167 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1168 { 1169 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1170 uint64_t tsf; 1171 1172 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1173 1174 /* Enable TSF synchronization. */ 1175 rtwn_write_1(sc, R92C_BCN_CTRL, 1176 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1177 1178 rtwn_write_1(sc, R92C_BCN_CTRL, 1179 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1180 1181 /* Set initial TSF. */ 1182 tsf = ni->ni_tstamp.tsf; 1183 tsf = le64toh(tsf); 1184 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1185 tsf -= IEEE80211_DUR_TU; 1186 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1187 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1188 1189 rtwn_write_1(sc, R92C_BCN_CTRL, 1190 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1191 } 1192 1193 static void 1194 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1195 { 1196 uint8_t reg; 1197 1198 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1199 1200 if (led == RTWN_LED_LINK) { 1201 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1202 if (!on) 1203 reg |= R92C_LEDCFG2_DIS; 1204 else 1205 reg |= R92C_LEDCFG2_EN; 1206 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1207 sc->ledlink = on; /* Save LED state. */ 1208 } 1209 } 1210 1211 static void 1212 rtwn_calib_to(void *arg) 1213 { 1214 struct rtwn_softc *sc = arg; 1215 struct r92c_fw_cmd_rssi cmd; 1216 1217 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1218 1219 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1220 goto restart_timer; 1221 1222 if (sc->avg_pwdb != -1) { 1223 /* Indicate Rx signal strength to FW for rate adaptation. */ 1224 memset(&cmd, 0, sizeof(cmd)); 1225 cmd.macid = 0; /* BSS. */ 1226 cmd.pwdb = sc->avg_pwdb; 1227 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1228 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1229 } 1230 1231 /* Do temperature compensation. */ 1232 rtwn_temp_calib(sc); 1233 1234 restart_timer: 1235 callout_schedule(&sc->calib_to, mstohz(2000)); 1236 } 1237 1238 static void 1239 rtwn_next_scan(void *arg) 1240 { 1241 struct rtwn_softc *sc = arg; 1242 struct ieee80211com *ic = &sc->sc_ic; 1243 int s; 1244 1245 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1246 1247 s = splnet(); 1248 if (ic->ic_state == IEEE80211_S_SCAN) 1249 ieee80211_next_scan(ic); 1250 splx(s); 1251 } 1252 1253 static void 1254 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1255 { 1256 1257 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1258 1259 /* start with lowest Tx rate */ 1260 ni->ni_txrate = 0; 1261 } 1262 1263 static int 1264 rtwn_reset(struct ifnet *ifp) 1265 { 1266 struct rtwn_softc *sc = ifp->if_softc; 1267 struct ieee80211com *ic = &sc->sc_ic; 1268 1269 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1270 return ENETRESET; 1271 1272 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1273 1274 return 0; 1275 } 1276 1277 static int 1278 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1279 { 1280 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1281 struct ieee80211_node *ni; 1282 enum ieee80211_state ostate = ic->ic_state; 1283 uint32_t reg; 1284 int s; 1285 1286 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1287 1288 s = splnet(); 1289 1290 callout_stop(&sc->scan_to); 1291 callout_stop(&sc->calib_to); 1292 1293 if (ostate != nstate) { 1294 DPRINTF(("%s: %s -> %s\n", __func__, 1295 ieee80211_state_name[ostate], 1296 ieee80211_state_name[nstate])); 1297 } 1298 1299 switch (ostate) { 1300 case IEEE80211_S_INIT: 1301 break; 1302 1303 case IEEE80211_S_SCAN: 1304 if (nstate != IEEE80211_S_SCAN) { 1305 /* 1306 * End of scanning 1307 */ 1308 /* flush 4-AC Queue after site_survey */ 1309 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1310 1311 /* Allow Rx from our BSSID only. */ 1312 rtwn_write_4(sc, R92C_RCR, 1313 rtwn_read_4(sc, R92C_RCR) | 1314 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1315 } 1316 break; 1317 1318 case IEEE80211_S_AUTH: 1319 case IEEE80211_S_ASSOC: 1320 break; 1321 1322 case IEEE80211_S_RUN: 1323 /* Turn link LED off. */ 1324 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1325 1326 /* Set media status to 'No Link'. */ 1327 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1328 1329 /* Stop Rx of data frames. */ 1330 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1331 1332 /* Rest TSF. */ 1333 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1334 1335 /* Disable TSF synchronization. */ 1336 rtwn_write_1(sc, R92C_BCN_CTRL, 1337 rtwn_read_1(sc, R92C_BCN_CTRL) | 1338 R92C_BCN_CTRL_DIS_TSF_UDT0); 1339 1340 /* Back to 20MHz mode */ 1341 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1342 1343 /* Reset EDCA parameters. */ 1344 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1345 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1346 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1347 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1348 1349 /* flush all cam entries */ 1350 rtwn_cam_init(sc); 1351 break; 1352 } 1353 1354 switch (nstate) { 1355 case IEEE80211_S_INIT: 1356 /* Turn link LED off. */ 1357 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1358 break; 1359 1360 case IEEE80211_S_SCAN: 1361 if (ostate != IEEE80211_S_SCAN) { 1362 /* 1363 * Begin of scanning 1364 */ 1365 1366 /* Set gain for scanning. */ 1367 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1368 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1369 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1370 1371 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1372 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1373 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1374 1375 /* Allow Rx from any BSSID. */ 1376 rtwn_write_4(sc, R92C_RCR, 1377 rtwn_read_4(sc, R92C_RCR) & 1378 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1379 1380 /* Stop Rx of data frames. */ 1381 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1382 1383 /* Disable update TSF */ 1384 rtwn_write_1(sc, R92C_BCN_CTRL, 1385 rtwn_read_1(sc, R92C_BCN_CTRL) | 1386 R92C_BCN_CTRL_DIS_TSF_UDT0); 1387 } 1388 1389 /* Make link LED blink during scan. */ 1390 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1391 1392 /* Pause AC Tx queues. */ 1393 rtwn_write_1(sc, R92C_TXPAUSE, 1394 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1395 1396 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1397 1398 /* Start periodic scan. */ 1399 callout_schedule(&sc->scan_to, mstohz(200)); 1400 break; 1401 1402 case IEEE80211_S_AUTH: 1403 /* Set initial gain under link. */ 1404 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1405 #ifdef doaslinux 1406 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1407 #else 1408 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1409 #endif 1410 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1411 1412 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1413 #ifdef doaslinux 1414 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1415 #else 1416 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1417 #endif 1418 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1419 1420 /* Set media status to 'No Link'. */ 1421 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1422 1423 /* Allow Rx from any BSSID. */ 1424 rtwn_write_4(sc, R92C_RCR, 1425 rtwn_read_4(sc, R92C_RCR) & 1426 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1427 1428 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1429 break; 1430 1431 case IEEE80211_S_ASSOC: 1432 break; 1433 1434 case IEEE80211_S_RUN: 1435 ni = ic->ic_bss; 1436 1437 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1438 1439 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1440 /* Back to 20Mhz mode */ 1441 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1442 1443 /* Set media status to 'No Link'. */ 1444 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1445 1446 /* Enable Rx of data frames. */ 1447 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1448 1449 /* Allow Rx from any BSSID. */ 1450 rtwn_write_4(sc, R92C_RCR, 1451 rtwn_read_4(sc, R92C_RCR) & 1452 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1453 1454 /* Accept Rx data/control/management frames */ 1455 rtwn_write_4(sc, R92C_RCR, 1456 rtwn_read_4(sc, R92C_RCR) | 1457 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1458 1459 /* Turn link LED on. */ 1460 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1461 break; 1462 } 1463 1464 /* Set media status to 'Associated'. */ 1465 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1466 1467 /* Set BSSID. */ 1468 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1469 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1470 1471 if (ic->ic_curmode == IEEE80211_MODE_11B) 1472 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1473 else /* 802.11b/g */ 1474 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1475 1476 /* Enable Rx of data frames. */ 1477 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1478 1479 /* Flush all AC queues. */ 1480 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1481 1482 /* Set beacon interval. */ 1483 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1484 1485 switch (ic->ic_opmode) { 1486 case IEEE80211_M_STA: 1487 /* Allow Rx from our BSSID only. */ 1488 rtwn_write_4(sc, R92C_RCR, 1489 rtwn_read_4(sc, R92C_RCR) | 1490 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1491 1492 /* Enable TSF synchronization. */ 1493 rtwn_tsf_sync_enable(sc); 1494 break; 1495 1496 case IEEE80211_M_HOSTAP: 1497 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1498 1499 /* Allow Rx from any BSSID. */ 1500 rtwn_write_4(sc, R92C_RCR, 1501 rtwn_read_4(sc, R92C_RCR) & 1502 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1503 1504 /* Reset TSF timer to zero. */ 1505 reg = rtwn_read_4(sc, R92C_TCR); 1506 reg &= ~0x01; 1507 rtwn_write_4(sc, R92C_TCR, reg); 1508 reg |= 0x01; 1509 rtwn_write_4(sc, R92C_TCR, reg); 1510 break; 1511 1512 case IEEE80211_M_MONITOR: 1513 default: 1514 break; 1515 } 1516 1517 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1518 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1519 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1520 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1521 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1522 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1523 1524 /* Intialize rate adaptation. */ 1525 rtwn_ra_init(sc); 1526 1527 /* Turn link LED on. */ 1528 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1529 1530 /* Reset average RSSI. */ 1531 sc->avg_pwdb = -1; 1532 1533 /* Reset temperature calibration state machine. */ 1534 sc->thcal_state = 0; 1535 sc->thcal_lctemp = 0; 1536 1537 /* Start periodic calibration. */ 1538 callout_schedule(&sc->calib_to, mstohz(2000)); 1539 break; 1540 } 1541 1542 (void)sc->sc_newstate(ic, nstate, arg); 1543 1544 splx(s); 1545 1546 return 0; 1547 } 1548 1549 static int 1550 rtwn_wme_update(struct ieee80211com *ic) 1551 { 1552 static const uint16_t aci2reg[WME_NUM_AC] = { 1553 R92C_EDCA_BE_PARAM, 1554 R92C_EDCA_BK_PARAM, 1555 R92C_EDCA_VI_PARAM, 1556 R92C_EDCA_VO_PARAM 1557 }; 1558 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1559 const struct wmeParams *wmep; 1560 int s, aci, aifs, slottime; 1561 1562 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1563 1564 s = splnet(); 1565 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1566 for (aci = 0; aci < WME_NUM_AC; aci++) { 1567 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1568 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1569 aifs = wmep->wmep_aifsn * slottime + 10; 1570 rtwn_write_4(sc, aci2reg[aci], 1571 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1572 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1573 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1574 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1575 } 1576 splx(s); 1577 1578 return 0; 1579 } 1580 1581 static void 1582 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1583 { 1584 int pwdb; 1585 1586 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1587 1588 /* Convert antenna signal to percentage. */ 1589 if (rssi <= -100 || rssi >= 20) 1590 pwdb = 0; 1591 else if (rssi >= 0) 1592 pwdb = 100; 1593 else 1594 pwdb = 100 + rssi; 1595 if (rate <= 3) { 1596 /* CCK gain is smaller than OFDM/MCS gain. */ 1597 pwdb += 6; 1598 if (pwdb > 100) 1599 pwdb = 100; 1600 if (pwdb <= 14) 1601 pwdb -= 4; 1602 else if (pwdb <= 26) 1603 pwdb -= 8; 1604 else if (pwdb <= 34) 1605 pwdb -= 6; 1606 else if (pwdb <= 42) 1607 pwdb -= 2; 1608 } 1609 if (sc->avg_pwdb == -1) /* Init. */ 1610 sc->avg_pwdb = pwdb; 1611 else if (sc->avg_pwdb < pwdb) 1612 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1613 else 1614 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1615 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1616 } 1617 1618 static int8_t 1619 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1620 { 1621 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1622 struct r92c_rx_phystat *phy; 1623 struct r92c_rx_cck *cck; 1624 uint8_t rpt; 1625 int8_t rssi; 1626 1627 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1628 1629 if (rate <= 3) { 1630 cck = (struct r92c_rx_cck *)physt; 1631 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1632 rpt = (cck->agc_rpt >> 5) & 0x3; 1633 rssi = (cck->agc_rpt & 0x1f) << 1; 1634 } else { 1635 rpt = (cck->agc_rpt >> 6) & 0x3; 1636 rssi = cck->agc_rpt & 0x3e; 1637 } 1638 rssi = cckoff[rpt] - rssi; 1639 } else { /* OFDM/HT. */ 1640 phy = (struct r92c_rx_phystat *)physt; 1641 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1642 } 1643 return rssi; 1644 } 1645 1646 static void 1647 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1648 struct rtwn_rx_data *rx_data, int desc_idx) 1649 { 1650 struct ieee80211com *ic = &sc->sc_ic; 1651 struct ifnet *ifp = IC2IFP(ic); 1652 struct ieee80211_frame *wh; 1653 struct ieee80211_node *ni; 1654 struct r92c_rx_phystat *phy = NULL; 1655 uint32_t rxdw0, rxdw3; 1656 struct mbuf *m, *m1; 1657 uint8_t rate; 1658 int8_t rssi = 0; 1659 int infosz, pktlen, shift, totlen, error; 1660 1661 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1662 1663 rxdw0 = le32toh(rx_desc->rxdw0); 1664 rxdw3 = le32toh(rx_desc->rxdw3); 1665 1666 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1667 /* 1668 * This should not happen since we setup our Rx filter 1669 * to not receive these frames. 1670 */ 1671 ifp->if_ierrors++; 1672 return; 1673 } 1674 1675 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1676 /* 1677 * XXX: This will drop most control packets. Do we really 1678 * want this in IEEE80211_M_MONITOR mode? 1679 */ 1680 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1681 ic->ic_stats.is_rx_tooshort++; 1682 ifp->if_ierrors++; 1683 return; 1684 } 1685 if (__predict_false(pktlen > MCLBYTES)) { 1686 ifp->if_ierrors++; 1687 return; 1688 } 1689 1690 rate = MS(rxdw3, R92C_RXDW3_RATE); 1691 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1692 if (infosz > sizeof(struct r92c_rx_phystat)) 1693 infosz = sizeof(struct r92c_rx_phystat); 1694 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1695 totlen = pktlen + infosz + shift; 1696 1697 /* Get RSSI from PHY status descriptor if present. */ 1698 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1699 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1700 rssi = rtwn_get_rssi(sc, rate, phy); 1701 /* Update our average RSSI. */ 1702 rtwn_update_avgrssi(sc, rate, rssi); 1703 } 1704 1705 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1706 pktlen, rate, infosz, shift, rssi)); 1707 1708 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1709 if (__predict_false(m1 == NULL)) { 1710 ic->ic_stats.is_rx_nobuf++; 1711 ifp->if_ierrors++; 1712 return; 1713 } 1714 MCLGET(m1, M_DONTWAIT); 1715 if (__predict_false(!(m1->m_flags & M_EXT))) { 1716 m_freem(m1); 1717 ic->ic_stats.is_rx_nobuf++; 1718 ifp->if_ierrors++; 1719 return; 1720 } 1721 1722 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1723 BUS_DMASYNC_POSTREAD); 1724 1725 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1726 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1727 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1728 if (error != 0) { 1729 m_freem(m1); 1730 1731 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1732 rx_data->m, BUS_DMA_NOWAIT)) 1733 panic("%s: could not load old RX mbuf", 1734 device_xname(sc->sc_dev)); 1735 1736 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1737 BUS_DMASYNC_PREREAD); 1738 1739 /* Physical address may have changed. */ 1740 rtwn_setup_rx_desc(sc, rx_desc, 1741 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1742 1743 ifp->if_ierrors++; 1744 return; 1745 } 1746 1747 /* Finalize mbuf. */ 1748 m = rx_data->m; 1749 rx_data->m = m1; 1750 m->m_pkthdr.len = m->m_len = totlen; 1751 m_set_rcvif(m, ifp); 1752 1753 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1754 BUS_DMASYNC_PREREAD); 1755 1756 /* Update RX descriptor. */ 1757 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1758 MCLBYTES, desc_idx); 1759 1760 /* Get ieee80211 frame header. */ 1761 if (rxdw0 & R92C_RXDW0_PHYST) 1762 m_adj(m, infosz + shift); 1763 else 1764 m_adj(m, shift); 1765 wh = mtod(m, struct ieee80211_frame *); 1766 1767 if (__predict_false(sc->sc_drvbpf != NULL)) { 1768 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1769 1770 tap->wr_flags = 0; 1771 /* Map HW rate index to 802.11 rate. */ 1772 tap->wr_flags = 2; 1773 if (!(rxdw3 & R92C_RXDW3_HT)) { 1774 switch (rate) { 1775 /* CCK. */ 1776 case 0: tap->wr_rate = 2; break; 1777 case 1: tap->wr_rate = 4; break; 1778 case 2: tap->wr_rate = 11; break; 1779 case 3: tap->wr_rate = 22; break; 1780 /* OFDM. */ 1781 case 4: tap->wr_rate = 12; break; 1782 case 5: tap->wr_rate = 18; break; 1783 case 6: tap->wr_rate = 24; break; 1784 case 7: tap->wr_rate = 36; break; 1785 case 8: tap->wr_rate = 48; break; 1786 case 9: tap->wr_rate = 72; break; 1787 case 10: tap->wr_rate = 96; break; 1788 case 11: tap->wr_rate = 108; break; 1789 } 1790 } else if (rate >= 12) { /* MCS0~15. */ 1791 /* Bit 7 set means HT MCS instead of rate. */ 1792 tap->wr_rate = 0x80 | (rate - 12); 1793 } 1794 tap->wr_dbm_antsignal = rssi; 1795 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1796 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1797 1798 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1799 } 1800 1801 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1802 1803 /* push the frame up to the 802.11 stack */ 1804 ieee80211_input(ic, m, ni, rssi, 0); 1805 1806 /* Node is no longer needed. */ 1807 ieee80211_free_node(ni); 1808 } 1809 1810 static int 1811 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1812 { 1813 struct ieee80211com *ic = &sc->sc_ic; 1814 struct ieee80211_frame *wh; 1815 struct ieee80211_key *k = NULL; 1816 struct rtwn_tx_ring *tx_ring; 1817 struct rtwn_tx_data *data; 1818 struct r92c_tx_desc *txd; 1819 uint16_t qos, seq; 1820 uint8_t raid, type, tid, qid; 1821 int hasqos, error; 1822 1823 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1824 1825 wh = mtod(m, struct ieee80211_frame *); 1826 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1827 1828 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1829 k = ieee80211_crypto_encap(ic, ni, m); 1830 if (k == NULL) 1831 return ENOBUFS; 1832 1833 wh = mtod(m, struct ieee80211_frame *); 1834 } 1835 1836 if ((hasqos = ieee80211_has_qos(wh))) { 1837 /* data frames in 11n mode */ 1838 qos = ieee80211_get_qos(wh); 1839 tid = qos & IEEE80211_QOS_TID; 1840 qid = TID_TO_WME_AC(tid); 1841 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1842 /* Use AC_VO for management frames. */ 1843 tid = 0; /* compiler happy */ 1844 qid = RTWN_VO_QUEUE; 1845 } else { 1846 /* non-qos data frames */ 1847 tid = R92C_TXDW1_QSEL_BE; 1848 qid = RTWN_BE_QUEUE; 1849 } 1850 1851 /* Grab a Tx buffer from the ring. */ 1852 tx_ring = &sc->tx_ring[qid]; 1853 data = &tx_ring->tx_data[tx_ring->cur]; 1854 if (data->m != NULL) { 1855 m_freem(m); 1856 return ENOBUFS; 1857 } 1858 1859 /* Fill Tx descriptor. */ 1860 txd = &tx_ring->desc[tx_ring->cur]; 1861 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1862 m_freem(m); 1863 return ENOBUFS; 1864 } 1865 1866 txd->txdw0 = htole32( 1867 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1868 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1869 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1870 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1871 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1872 1873 txd->txdw1 = 0; 1874 txd->txdw4 = 0; 1875 txd->txdw5 = 0; 1876 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1877 type == IEEE80211_FC0_TYPE_DATA) { 1878 if (ic->ic_curmode == IEEE80211_MODE_11B) 1879 raid = R92C_RAID_11B; 1880 else 1881 raid = R92C_RAID_11BG; 1882 1883 txd->txdw1 |= htole32( 1884 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1885 SM(R92C_TXDW1_QSEL, tid) | 1886 SM(R92C_TXDW1_RAID, raid) | 1887 R92C_TXDW1_AGGBK); 1888 1889 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1890 /* for 11g */ 1891 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1892 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1893 R92C_TXDW4_HWRTSEN); 1894 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1895 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1896 R92C_TXDW4_HWRTSEN); 1897 } 1898 } 1899 /* Send RTS at OFDM24. */ 1900 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1901 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1902 /* Send data at OFDM54. */ 1903 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1904 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1905 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1906 txd->txdw1 |= htole32( 1907 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1908 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1909 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1910 1911 /* Force CCK1. */ 1912 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1913 /* Use 1Mbps */ 1914 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1915 } else { 1916 txd->txdw1 |= htole32( 1917 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1918 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1919 1920 /* Force CCK1. */ 1921 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1922 /* Use 1Mbps */ 1923 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1924 } 1925 1926 /* Set sequence number (already little endian). */ 1927 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1928 txd->txdseq = htole16(seq); 1929 1930 if (!hasqos) { 1931 /* Use HW sequence numbering for non-QoS frames. */ 1932 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1933 txd->txdseq |= htole16(0x8000); /* WTF? */ 1934 } else 1935 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1936 1937 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1938 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1939 if (error && error != EFBIG) { 1940 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1941 error); 1942 m_freem(m); 1943 return error; 1944 } 1945 if (error != 0) { 1946 /* Too many DMA segments, linearize mbuf. */ 1947 if ((m = m_defrag(m, M_DONTWAIT)) == NULL) { 1948 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1949 return ENOBUFS; 1950 } 1951 1952 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1953 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1954 if (error != 0) { 1955 aprint_error_dev(sc->sc_dev, 1956 "can't map mbuf (error %d)\n", error); 1957 m_freem(m); 1958 return error; 1959 } 1960 } 1961 1962 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1963 txd->txbufsize = htole16(m->m_pkthdr.len); 1964 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1965 BUS_SPACE_BARRIER_WRITE); 1966 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1967 1968 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1969 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1970 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1971 BUS_DMASYNC_PREWRITE); 1972 1973 data->m = m; 1974 data->ni = ni; 1975 1976 if (__predict_false(sc->sc_drvbpf != NULL)) { 1977 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1978 1979 tap->wt_flags = 0; 1980 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1981 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1982 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1983 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1984 1985 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1986 } 1987 1988 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1989 tx_ring->queued++; 1990 1991 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1992 sc->qfullmsk |= (1 << qid); 1993 1994 /* Kick TX. */ 1995 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1996 1997 return 0; 1998 } 1999 2000 static void 2001 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2002 { 2003 struct ieee80211com *ic = &sc->sc_ic; 2004 struct ifnet *ifp = IC2IFP(ic); 2005 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2006 struct rtwn_tx_data *tx_data; 2007 struct r92c_tx_desc *tx_desc; 2008 int i; 2009 2010 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2011 qid)); 2012 2013 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2014 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2016 2017 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2018 tx_data = &tx_ring->tx_data[i]; 2019 if (tx_data->m == NULL) 2020 continue; 2021 2022 tx_desc = &tx_ring->desc[i]; 2023 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2024 continue; 2025 2026 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2027 m_freem(tx_data->m); 2028 tx_data->m = NULL; 2029 ieee80211_free_node(tx_data->ni); 2030 tx_data->ni = NULL; 2031 2032 ifp->if_opackets++; 2033 sc->sc_tx_timer = 0; 2034 tx_ring->queued--; 2035 } 2036 2037 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 2038 sc->qfullmsk &= ~(1 << qid); 2039 } 2040 2041 static void 2042 rtwn_start(struct ifnet *ifp) 2043 { 2044 struct rtwn_softc *sc = ifp->if_softc; 2045 struct ieee80211com *ic = &sc->sc_ic; 2046 struct ether_header *eh; 2047 struct ieee80211_node *ni; 2048 struct mbuf *m; 2049 2050 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2051 return; 2052 2053 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2054 2055 for (;;) { 2056 if (sc->qfullmsk != 0) { 2057 ifp->if_flags |= IFF_OACTIVE; 2058 break; 2059 } 2060 /* Send pending management frames first. */ 2061 IF_DEQUEUE(&ic->ic_mgtq, m); 2062 if (m != NULL) { 2063 ni = M_GETCTX(m, struct ieee80211_node *); 2064 M_CLEARCTX(m); 2065 goto sendit; 2066 } 2067 if (ic->ic_state != IEEE80211_S_RUN) 2068 break; 2069 2070 /* Encapsulate and send data frames. */ 2071 IFQ_DEQUEUE(&ifp->if_snd, m); 2072 if (m == NULL) 2073 break; 2074 2075 if (m->m_len < (int)sizeof(*eh) && 2076 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2077 ifp->if_oerrors++; 2078 continue; 2079 } 2080 eh = mtod(m, struct ether_header *); 2081 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2082 if (ni == NULL) { 2083 m_freem(m); 2084 ifp->if_oerrors++; 2085 continue; 2086 } 2087 2088 bpf_mtap(ifp, m); 2089 2090 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2091 ieee80211_free_node(ni); 2092 ifp->if_oerrors++; 2093 continue; 2094 } 2095 sendit: 2096 bpf_mtap3(ic->ic_rawbpf, m); 2097 2098 if (rtwn_tx(sc, m, ni) != 0) { 2099 ieee80211_free_node(ni); 2100 ifp->if_oerrors++; 2101 continue; 2102 } 2103 2104 sc->sc_tx_timer = 5; 2105 ifp->if_timer = 1; 2106 } 2107 2108 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2109 } 2110 2111 static void 2112 rtwn_watchdog(struct ifnet *ifp) 2113 { 2114 struct rtwn_softc *sc = ifp->if_softc; 2115 struct ieee80211com *ic = &sc->sc_ic; 2116 2117 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2118 2119 ifp->if_timer = 0; 2120 2121 if (sc->sc_tx_timer > 0) { 2122 if (--sc->sc_tx_timer == 0) { 2123 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2124 softint_schedule(sc->init_task); 2125 ifp->if_oerrors++; 2126 return; 2127 } 2128 ifp->if_timer = 1; 2129 } 2130 ieee80211_watchdog(ic); 2131 } 2132 2133 static int 2134 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2135 { 2136 struct rtwn_softc *sc = ifp->if_softc; 2137 struct ieee80211com *ic = &sc->sc_ic; 2138 int s, error = 0; 2139 2140 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2141 __func__, cmd, data)); 2142 2143 s = splnet(); 2144 2145 switch (cmd) { 2146 case SIOCSIFFLAGS: 2147 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2148 break; 2149 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2150 case IFF_UP | IFF_RUNNING: 2151 break; 2152 case IFF_UP: 2153 error = rtwn_init(ifp); 2154 if (error != 0) 2155 ifp->if_flags &= ~IFF_UP; 2156 break; 2157 case IFF_RUNNING: 2158 rtwn_stop(ifp, 1); 2159 break; 2160 case 0: 2161 break; 2162 } 2163 break; 2164 2165 case SIOCADDMULTI: 2166 case SIOCDELMULTI: 2167 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2168 /* setup multicast filter, etc */ 2169 error = 0; 2170 } 2171 break; 2172 2173 case SIOCS80211CHANNEL: 2174 error = ieee80211_ioctl(ic, cmd, data); 2175 if (error == ENETRESET && 2176 ic->ic_opmode == IEEE80211_M_MONITOR) { 2177 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2178 (IFF_UP | IFF_RUNNING)) { 2179 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2180 } 2181 error = 0; 2182 } 2183 break; 2184 2185 default: 2186 error = ieee80211_ioctl(ic, cmd, data); 2187 break; 2188 } 2189 2190 if (error == ENETRESET) { 2191 error = 0; 2192 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2193 (IFF_UP | IFF_RUNNING)) { 2194 rtwn_stop(ifp, 0); 2195 error = rtwn_init(ifp); 2196 } 2197 } 2198 2199 splx(s); 2200 2201 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2202 error)); 2203 2204 return error; 2205 } 2206 2207 static int 2208 rtwn_power_on(struct rtwn_softc *sc) 2209 { 2210 uint32_t reg; 2211 int ntries; 2212 2213 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2214 2215 /* Wait for autoload done bit. */ 2216 for (ntries = 0; ntries < 1000; ntries++) { 2217 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2218 break; 2219 DELAY(5); 2220 } 2221 if (ntries == 1000) { 2222 aprint_error_dev(sc->sc_dev, 2223 "timeout waiting for chip autoload\n"); 2224 return ETIMEDOUT; 2225 } 2226 2227 /* Unlock ISO/CLK/Power control register. */ 2228 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2229 2230 /* TODO: check if we need this for 8188CE */ 2231 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2232 /* bt coex */ 2233 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2234 reg |= (R92C_APS_FSMCO_SOP_ABG | 2235 R92C_APS_FSMCO_SOP_AMB | 2236 R92C_APS_FSMCO_XOP_BTCK); 2237 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2238 } 2239 2240 /* Move SPS into PWM mode. */ 2241 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2242 DELAY(100); 2243 2244 /* Set low byte to 0x0f, leave others unchanged. */ 2245 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2246 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2247 2248 /* TODO: check if we need this for 8188CE */ 2249 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2250 /* bt coex */ 2251 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2252 reg &= ~0x00024800; /* XXX magic from linux */ 2253 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2254 } 2255 2256 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2257 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2258 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2259 DELAY(200); 2260 2261 /* TODO: linux does additional btcoex stuff here */ 2262 2263 /* Auto enable WLAN. */ 2264 rtwn_write_2(sc, R92C_APS_FSMCO, 2265 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2266 for (ntries = 0; ntries < 1000; ntries++) { 2267 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2268 R92C_APS_FSMCO_APFM_ONMAC)) 2269 break; 2270 DELAY(5); 2271 } 2272 if (ntries == 1000) { 2273 aprint_error_dev(sc->sc_dev, 2274 "timeout waiting for MAC auto ON\n"); 2275 return ETIMEDOUT; 2276 } 2277 2278 /* Enable radio, GPIO and LED functions. */ 2279 rtwn_write_2(sc, R92C_APS_FSMCO, 2280 R92C_APS_FSMCO_AFSM_PCIE | 2281 R92C_APS_FSMCO_PDN_EN | 2282 R92C_APS_FSMCO_PFM_ALDN); 2283 2284 /* Release RF digital isolation. */ 2285 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2286 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2287 2288 if (sc->chip & RTWN_CHIP_92C) 2289 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2290 else 2291 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2292 2293 rtwn_write_4(sc, R92C_INT_MIG, 0); 2294 2295 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2296 /* bt coex */ 2297 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2298 reg &= 0xfd; /* XXX magic from linux */ 2299 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2300 } 2301 2302 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2303 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2304 2305 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2306 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2307 aprint_error_dev(sc->sc_dev, 2308 "radio is disabled by hardware switch\n"); 2309 return EPERM; /* :-) */ 2310 } 2311 2312 /* Initialize MAC. */ 2313 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2314 rtwn_write_1(sc, R92C_APSD_CTRL, 2315 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2316 for (ntries = 0; ntries < 200; ntries++) { 2317 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2318 R92C_APSD_CTRL_OFF_STATUS)) 2319 break; 2320 DELAY(500); 2321 } 2322 if (ntries == 200) { 2323 aprint_error_dev(sc->sc_dev, 2324 "timeout waiting for MAC initialization\n"); 2325 return ETIMEDOUT; 2326 } 2327 2328 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2329 reg = rtwn_read_2(sc, R92C_CR); 2330 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2331 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2332 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2333 R92C_CR_ENSEC; 2334 rtwn_write_2(sc, R92C_CR, reg); 2335 2336 rtwn_write_1(sc, 0xfe10, 0x19); 2337 2338 return 0; 2339 } 2340 2341 static int 2342 rtwn_llt_init(struct rtwn_softc *sc) 2343 { 2344 int i, error; 2345 2346 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2347 2348 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2349 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2350 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2351 return error; 2352 } 2353 /* NB: 0xff indicates end-of-list. */ 2354 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2355 return error; 2356 /* 2357 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2358 * as ring buffer. 2359 */ 2360 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2361 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2362 return error; 2363 } 2364 /* Make the last page point to the beginning of the ring buffer. */ 2365 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2366 return error; 2367 } 2368 2369 static void 2370 rtwn_fw_reset(struct rtwn_softc *sc) 2371 { 2372 uint16_t reg; 2373 int ntries; 2374 2375 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2376 2377 /* Tell 8051 to reset itself. */ 2378 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2379 2380 /* Wait until 8051 resets by itself. */ 2381 for (ntries = 0; ntries < 100; ntries++) { 2382 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2383 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2384 goto sleep; 2385 DELAY(50); 2386 } 2387 /* Force 8051 reset. */ 2388 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2389 sleep: 2390 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2391 #if 0 2392 /* 2393 * We must sleep for one second to let the firmware settle. 2394 * Accessing registers too early will hang the whole system. 2395 */ 2396 tsleep(®, 0, "rtwnrst", hz); 2397 #else 2398 DELAY(1000 * 1000); 2399 #endif 2400 } 2401 2402 static int 2403 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2404 { 2405 uint32_t reg; 2406 int off, mlen, error = 0, i; 2407 2408 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2409 2410 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2411 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2412 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2413 2414 DELAY(5); 2415 2416 off = R92C_FW_START_ADDR; 2417 while (len > 0) { 2418 if (len > 196) 2419 mlen = 196; 2420 else if (len > 4) 2421 mlen = 4; 2422 else 2423 mlen = 1; 2424 for (i = 0; i < mlen; i++) 2425 rtwn_write_1(sc, off++, buf[i]); 2426 buf += mlen; 2427 len -= mlen; 2428 } 2429 2430 return error; 2431 } 2432 2433 static int 2434 rtwn_load_firmware(struct rtwn_softc *sc) 2435 { 2436 firmware_handle_t fwh; 2437 const struct r92c_fw_hdr *hdr; 2438 const char *name; 2439 u_char *fw, *ptr; 2440 size_t len; 2441 uint32_t reg; 2442 int mlen, ntries, page, error; 2443 2444 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2445 2446 /* Read firmware image from the filesystem. */ 2447 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2448 RTWN_CHIP_UMC_A_CUT) 2449 name = "rtl8192cfwU.bin"; 2450 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2451 name = "rtl8192cfwU_B.bin"; 2452 else 2453 name = "rtl8192cfw.bin"; 2454 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2455 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2456 aprint_error_dev(sc->sc_dev, 2457 "could not read firmware %s (error %d)\n", name, error); 2458 return error; 2459 } 2460 const size_t fwlen = len = firmware_get_size(fwh); 2461 fw = firmware_malloc(len); 2462 if (fw == NULL) { 2463 aprint_error_dev(sc->sc_dev, 2464 "failed to allocate firmware memory (size=%zu)\n", len); 2465 firmware_close(fwh); 2466 return ENOMEM; 2467 } 2468 error = firmware_read(fwh, 0, fw, len); 2469 firmware_close(fwh); 2470 if (error != 0) { 2471 aprint_error_dev(sc->sc_dev, 2472 "failed to read firmware (error %d)\n", error); 2473 firmware_free(fw, fwlen); 2474 return error; 2475 } 2476 2477 if (len < sizeof(*hdr)) { 2478 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2479 error = EINVAL; 2480 goto fail; 2481 } 2482 ptr = fw; 2483 hdr = (const struct r92c_fw_hdr *)ptr; 2484 /* Check if there is a valid FW header and skip it. */ 2485 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2486 (le16toh(hdr->signature) >> 4) == 0x92c) { 2487 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2488 le16toh(hdr->version), le16toh(hdr->subversion), 2489 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2490 ptr += sizeof(*hdr); 2491 len -= sizeof(*hdr); 2492 } 2493 2494 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2495 rtwn_fw_reset(sc); 2496 2497 /* Enable FW download. */ 2498 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2499 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2500 R92C_SYS_FUNC_EN_CPUEN); 2501 rtwn_write_1(sc, R92C_MCUFWDL, 2502 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2503 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2504 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2505 2506 /* Reset the FWDL checksum. */ 2507 rtwn_write_1(sc, R92C_MCUFWDL, 2508 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2509 2510 /* download firmware */ 2511 for (page = 0; len > 0; page++) { 2512 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2513 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2514 if (error != 0) { 2515 aprint_error_dev(sc->sc_dev, 2516 "could not load firmware page %d\n", page); 2517 goto fail; 2518 } 2519 ptr += mlen; 2520 len -= mlen; 2521 } 2522 2523 /* Disable FW download. */ 2524 rtwn_write_1(sc, R92C_MCUFWDL, 2525 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2526 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2527 2528 /* Wait for checksum report. */ 2529 for (ntries = 0; ntries < 1000; ntries++) { 2530 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2531 break; 2532 DELAY(5); 2533 } 2534 if (ntries == 1000) { 2535 aprint_error_dev(sc->sc_dev, 2536 "timeout waiting for checksum report\n"); 2537 error = ETIMEDOUT; 2538 goto fail; 2539 } 2540 2541 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2542 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2543 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2544 2545 /* Wait for firmware readiness. */ 2546 for (ntries = 0; ntries < 1000; ntries++) { 2547 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2548 break; 2549 DELAY(5); 2550 } 2551 if (ntries == 1000) { 2552 aprint_error_dev(sc->sc_dev, 2553 "timeout waiting for firmware readiness\n"); 2554 error = ETIMEDOUT; 2555 goto fail; 2556 } 2557 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2558 2559 fail: 2560 firmware_free(fw, fwlen); 2561 return error; 2562 } 2563 2564 static int 2565 rtwn_dma_init(struct rtwn_softc *sc) 2566 { 2567 uint32_t reg; 2568 int error; 2569 2570 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2571 2572 /* Initialize LLT table. */ 2573 error = rtwn_llt_init(sc); 2574 if (error != 0) 2575 return error; 2576 2577 /* Set number of pages for normal priority queue. */ 2578 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2579 rtwn_write_4(sc, R92C_RQPN, 2580 /* Set number of pages for public queue. */ 2581 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2582 /* Set number of pages for high priority queue. */ 2583 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2584 /* Set number of pages for low priority queue. */ 2585 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2586 /* Load values. */ 2587 R92C_RQPN_LD); 2588 2589 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2590 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2591 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2592 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2593 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2594 2595 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2596 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2597 reg |= 0xF771; 2598 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2599 2600 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2601 2602 /* Configure Tx DMA. */ 2603 rtwn_write_4(sc, R92C_BKQ_DESA, 2604 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2605 rtwn_write_4(sc, R92C_BEQ_DESA, 2606 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2607 rtwn_write_4(sc, R92C_VIQ_DESA, 2608 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2609 rtwn_write_4(sc, R92C_VOQ_DESA, 2610 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2611 rtwn_write_4(sc, R92C_BCNQ_DESA, 2612 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2613 rtwn_write_4(sc, R92C_MGQ_DESA, 2614 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2615 rtwn_write_4(sc, R92C_HQ_DESA, 2616 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2617 2618 /* Configure Rx DMA. */ 2619 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2620 2621 /* Set Tx/Rx transfer page boundary. */ 2622 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2623 2624 /* Set Tx/Rx transfer page size. */ 2625 rtwn_write_1(sc, R92C_PBP, 2626 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2627 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2628 return 0; 2629 } 2630 2631 static void 2632 rtwn_mac_init(struct rtwn_softc *sc) 2633 { 2634 int i; 2635 2636 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2637 2638 /* Write MAC initialization values. */ 2639 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2640 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2641 } 2642 2643 static void 2644 rtwn_bb_init(struct rtwn_softc *sc) 2645 { 2646 const struct rtwn_bb_prog *prog; 2647 uint32_t reg; 2648 int i; 2649 2650 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2651 2652 /* Enable BB and RF. */ 2653 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2654 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2655 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2656 R92C_SYS_FUNC_EN_DIO_RF); 2657 2658 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2659 2660 rtwn_write_1(sc, R92C_RF_CTRL, 2661 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2662 2663 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2664 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2665 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2666 R92C_SYS_FUNC_EN_BBRSTB); 2667 2668 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2669 2670 rtwn_write_4(sc, R92C_LEDCFG0, 2671 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2672 2673 /* Select BB programming. */ 2674 prog = (sc->chip & RTWN_CHIP_92C) ? 2675 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2676 2677 /* Write BB initialization values. */ 2678 for (i = 0; i < prog->count; i++) { 2679 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2680 DELAY(1); 2681 } 2682 2683 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2684 /* 8192C 1T only configuration. */ 2685 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2686 reg = (reg & ~0x00000003) | 0x2; 2687 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2688 2689 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2690 reg = (reg & ~0x00300033) | 0x00200022; 2691 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2692 2693 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2694 reg = (reg & ~0xff000000) | 0x45 << 24; 2695 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2696 2697 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2698 reg = (reg & ~0x000000ff) | 0x23; 2699 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2700 2701 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2702 reg = (reg & ~0x00000030) | 1 << 4; 2703 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2704 2705 reg = rtwn_bb_read(sc, 0xe74); 2706 reg = (reg & ~0x0c000000) | 2 << 26; 2707 rtwn_bb_write(sc, 0xe74, reg); 2708 reg = rtwn_bb_read(sc, 0xe78); 2709 reg = (reg & ~0x0c000000) | 2 << 26; 2710 rtwn_bb_write(sc, 0xe78, reg); 2711 reg = rtwn_bb_read(sc, 0xe7c); 2712 reg = (reg & ~0x0c000000) | 2 << 26; 2713 rtwn_bb_write(sc, 0xe7c, reg); 2714 reg = rtwn_bb_read(sc, 0xe80); 2715 reg = (reg & ~0x0c000000) | 2 << 26; 2716 rtwn_bb_write(sc, 0xe80, reg); 2717 reg = rtwn_bb_read(sc, 0xe88); 2718 reg = (reg & ~0x0c000000) | 2 << 26; 2719 rtwn_bb_write(sc, 0xe88, reg); 2720 } 2721 2722 /* Write AGC values. */ 2723 for (i = 0; i < prog->agccount; i++) { 2724 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2725 prog->agcvals[i]); 2726 DELAY(1); 2727 } 2728 2729 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2730 R92C_HSSI_PARAM2_CCK_HIPWR) 2731 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2732 } 2733 2734 static void 2735 rtwn_rf_init(struct rtwn_softc *sc) 2736 { 2737 const struct rtwn_rf_prog *prog; 2738 uint32_t reg, type; 2739 int i, j, idx, off; 2740 2741 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2742 2743 /* Select RF programming based on board type. */ 2744 if (!(sc->chip & RTWN_CHIP_92C)) { 2745 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2746 prog = rtl8188ce_rf_prog; 2747 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2748 prog = rtl8188ru_rf_prog; 2749 else 2750 prog = rtl8188cu_rf_prog; 2751 } else 2752 prog = rtl8192ce_rf_prog; 2753 2754 for (i = 0; i < sc->nrxchains; i++) { 2755 /* Save RF_ENV control type. */ 2756 idx = i / 2; 2757 off = (i % 2) * 16; 2758 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2759 type = (reg >> off) & 0x10; 2760 2761 /* Set RF_ENV enable. */ 2762 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2763 reg |= 0x100000; 2764 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2765 DELAY(1); 2766 /* Set RF_ENV output high. */ 2767 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2768 reg |= 0x10; 2769 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2770 DELAY(1); 2771 /* Set address and data lengths of RF registers. */ 2772 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2773 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2774 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2775 DELAY(1); 2776 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2777 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2778 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2779 DELAY(1); 2780 2781 /* Write RF initialization values for this chain. */ 2782 for (j = 0; j < prog[i].count; j++) { 2783 if (prog[i].regs[j] >= 0xf9 && 2784 prog[i].regs[j] <= 0xfe) { 2785 /* 2786 * These are fake RF registers offsets that 2787 * indicate a delay is required. 2788 */ 2789 DELAY(50); 2790 continue; 2791 } 2792 rtwn_rf_write(sc, i, prog[i].regs[j], 2793 prog[i].vals[j]); 2794 DELAY(1); 2795 } 2796 2797 /* Restore RF_ENV control type. */ 2798 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2799 reg &= ~(0x10 << off) | (type << off); 2800 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2801 2802 /* Cache RF register CHNLBW. */ 2803 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2804 } 2805 2806 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2807 RTWN_CHIP_UMC_A_CUT) { 2808 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2809 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2810 } 2811 } 2812 2813 static void 2814 rtwn_cam_init(struct rtwn_softc *sc) 2815 { 2816 2817 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2818 2819 /* Invalidate all CAM entries. */ 2820 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2821 } 2822 2823 static void 2824 rtwn_pa_bias_init(struct rtwn_softc *sc) 2825 { 2826 uint8_t reg; 2827 int i; 2828 2829 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2830 2831 for (i = 0; i < sc->nrxchains; i++) { 2832 if (sc->pa_setting & (1 << i)) 2833 continue; 2834 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2835 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2836 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2837 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2838 } 2839 if (!(sc->pa_setting & 0x10)) { 2840 reg = rtwn_read_1(sc, 0x16); 2841 reg = (reg & ~0xf0) | 0x90; 2842 rtwn_write_1(sc, 0x16, reg); 2843 } 2844 } 2845 2846 static void 2847 rtwn_rxfilter_init(struct rtwn_softc *sc) 2848 { 2849 2850 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2851 2852 /* Initialize Rx filter. */ 2853 /* TODO: use better filter for monitor mode. */ 2854 rtwn_write_4(sc, R92C_RCR, 2855 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2856 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2857 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2858 /* Accept all multicast frames. */ 2859 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2860 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2861 /* Accept all management frames. */ 2862 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2863 /* Reject all control frames. */ 2864 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2865 /* Accept all data frames. */ 2866 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2867 } 2868 2869 static void 2870 rtwn_edca_init(struct rtwn_softc *sc) 2871 { 2872 2873 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2874 2875 /* set spec SIFS (used in NAV) */ 2876 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2877 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2878 2879 /* set SIFS CCK/OFDM */ 2880 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2881 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2882 2883 /* TXOP */ 2884 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2885 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2886 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2887 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2888 } 2889 2890 static void 2891 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2892 uint16_t power[RTWN_RIDX_COUNT]) 2893 { 2894 uint32_t reg; 2895 2896 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2897 2898 /* Write per-CCK rate Tx power. */ 2899 if (chain == 0) { 2900 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2901 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2902 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2903 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2904 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2905 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2906 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2907 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2908 } else { 2909 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2910 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2911 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2912 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2913 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2914 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2915 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2916 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2917 } 2918 /* Write per-OFDM rate Tx power. */ 2919 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2920 SM(R92C_TXAGC_RATE06, power[ 4]) | 2921 SM(R92C_TXAGC_RATE09, power[ 5]) | 2922 SM(R92C_TXAGC_RATE12, power[ 6]) | 2923 SM(R92C_TXAGC_RATE18, power[ 7])); 2924 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2925 SM(R92C_TXAGC_RATE24, power[ 8]) | 2926 SM(R92C_TXAGC_RATE36, power[ 9]) | 2927 SM(R92C_TXAGC_RATE48, power[10]) | 2928 SM(R92C_TXAGC_RATE54, power[11])); 2929 /* Write per-MCS Tx power. */ 2930 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2931 SM(R92C_TXAGC_MCS00, power[12]) | 2932 SM(R92C_TXAGC_MCS01, power[13]) | 2933 SM(R92C_TXAGC_MCS02, power[14]) | 2934 SM(R92C_TXAGC_MCS03, power[15])); 2935 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2936 SM(R92C_TXAGC_MCS04, power[16]) | 2937 SM(R92C_TXAGC_MCS05, power[17]) | 2938 SM(R92C_TXAGC_MCS06, power[18]) | 2939 SM(R92C_TXAGC_MCS07, power[19])); 2940 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2941 SM(R92C_TXAGC_MCS08, power[20]) | 2942 SM(R92C_TXAGC_MCS09, power[21]) | 2943 SM(R92C_TXAGC_MCS10, power[22]) | 2944 SM(R92C_TXAGC_MCS11, power[23])); 2945 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2946 SM(R92C_TXAGC_MCS12, power[24]) | 2947 SM(R92C_TXAGC_MCS13, power[25]) | 2948 SM(R92C_TXAGC_MCS14, power[26]) | 2949 SM(R92C_TXAGC_MCS15, power[27])); 2950 } 2951 2952 static void 2953 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2954 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2955 uint16_t power[RTWN_RIDX_COUNT]) 2956 { 2957 struct ieee80211com *ic = &sc->sc_ic; 2958 struct r92c_rom *rom = &sc->rom; 2959 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2960 const struct rtwn_txpwr *base; 2961 int ridx, chan, group; 2962 2963 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2964 2965 /* Determine channel group. */ 2966 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2967 if (chan <= 3) 2968 group = 0; 2969 else if (chan <= 9) 2970 group = 1; 2971 else 2972 group = 2; 2973 2974 /* Get original Tx power based on board type and RF chain. */ 2975 if (!(sc->chip & RTWN_CHIP_92C)) { 2976 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2977 base = &rtl8188ru_txagc[chain]; 2978 else 2979 base = &rtl8192cu_txagc[chain]; 2980 } else 2981 base = &rtl8192cu_txagc[chain]; 2982 2983 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2984 if (sc->regulatory == 0) { 2985 for (ridx = 0; ridx <= 3; ridx++) 2986 power[ridx] = base->pwr[0][ridx]; 2987 } 2988 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 2989 if (sc->regulatory == 3) { 2990 power[ridx] = base->pwr[0][ridx]; 2991 /* Apply vendor limits. */ 2992 if (extc != NULL) 2993 maxpwr = rom->ht40_max_pwr[group]; 2994 else 2995 maxpwr = rom->ht20_max_pwr[group]; 2996 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 2997 if (power[ridx] > maxpwr) 2998 power[ridx] = maxpwr; 2999 } else if (sc->regulatory == 1) { 3000 if (extc == NULL) 3001 power[ridx] = base->pwr[group][ridx]; 3002 } else if (sc->regulatory != 2) 3003 power[ridx] = base->pwr[0][ridx]; 3004 } 3005 3006 /* Compute per-CCK rate Tx power. */ 3007 cckpow = rom->cck_tx_pwr[chain][group]; 3008 for (ridx = 0; ridx <= 3; ridx++) { 3009 power[ridx] += cckpow; 3010 if (power[ridx] > R92C_MAX_TX_PWR) 3011 power[ridx] = R92C_MAX_TX_PWR; 3012 } 3013 3014 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3015 if (sc->ntxchains > 1) { 3016 /* Apply reduction for 2 spatial streams. */ 3017 diff = rom->ht40_2s_tx_pwr_diff[group]; 3018 diff = (diff >> (chain * 4)) & 0xf; 3019 htpow = (htpow > diff) ? htpow - diff : 0; 3020 } 3021 3022 /* Compute per-OFDM rate Tx power. */ 3023 diff = rom->ofdm_tx_pwr_diff[group]; 3024 diff = (diff >> (chain * 4)) & 0xf; 3025 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3026 for (ridx = 4; ridx <= 11; ridx++) { 3027 power[ridx] += ofdmpow; 3028 if (power[ridx] > R92C_MAX_TX_PWR) 3029 power[ridx] = R92C_MAX_TX_PWR; 3030 } 3031 3032 /* Compute per-MCS Tx power. */ 3033 if (extc == NULL) { 3034 diff = rom->ht20_tx_pwr_diff[group]; 3035 diff = (diff >> (chain * 4)) & 0xf; 3036 htpow += diff; /* HT40->HT20 correction. */ 3037 } 3038 for (ridx = 12; ridx <= 27; ridx++) { 3039 power[ridx] += htpow; 3040 if (power[ridx] > R92C_MAX_TX_PWR) 3041 power[ridx] = R92C_MAX_TX_PWR; 3042 } 3043 #ifdef RTWN_DEBUG 3044 if (rtwn_debug >= 4) { 3045 /* Dump per-rate Tx power values. */ 3046 printf("Tx power for chain %d:\n", chain); 3047 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3048 printf("Rate %d = %u\n", ridx, power[ridx]); 3049 } 3050 #endif 3051 } 3052 3053 static void 3054 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3055 struct ieee80211_channel *extc) 3056 { 3057 uint16_t power[RTWN_RIDX_COUNT]; 3058 int i; 3059 3060 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3061 3062 for (i = 0; i < sc->ntxchains; i++) { 3063 /* Compute per-rate Tx power values. */ 3064 rtwn_get_txpower(sc, i, c, extc, power); 3065 /* Write per-rate Tx power values to hardware. */ 3066 rtwn_write_txpower(sc, i, power); 3067 } 3068 } 3069 3070 static void 3071 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3072 struct ieee80211_channel *extc) 3073 { 3074 struct ieee80211com *ic = &sc->sc_ic; 3075 u_int chan; 3076 int i; 3077 3078 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3079 3080 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3081 3082 /* Set Tx power for this new channel. */ 3083 rtwn_set_txpower(sc, c, extc); 3084 3085 for (i = 0; i < sc->nrxchains; i++) { 3086 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3087 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3088 } 3089 #ifndef IEEE80211_NO_HT 3090 if (extc != NULL) { 3091 uint32_t reg; 3092 3093 /* Is secondary channel below or above primary? */ 3094 int prichlo = c->ic_freq < extc->ic_freq; 3095 3096 rtwn_write_1(sc, R92C_BWOPMODE, 3097 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3098 3099 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3100 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3101 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3102 3103 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3104 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3105 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3106 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3107 3108 /* Set CCK side band. */ 3109 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3110 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3111 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3112 3113 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3114 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3115 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3116 3117 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3118 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3119 ~R92C_FPGA0_ANAPARAM2_CBW20); 3120 3121 reg = rtwn_bb_read(sc, 0x818); 3122 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3123 rtwn_bb_write(sc, 0x818, reg); 3124 3125 /* Select 40MHz bandwidth. */ 3126 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3127 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3128 } else 3129 #endif 3130 { 3131 rtwn_write_1(sc, R92C_BWOPMODE, 3132 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3133 3134 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3135 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3136 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3137 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3138 3139 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3140 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3141 R92C_FPGA0_ANAPARAM2_CBW20); 3142 3143 /* Select 20MHz bandwidth. */ 3144 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3145 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3146 } 3147 } 3148 3149 static void 3150 rtwn_iq_calib(struct rtwn_softc *sc) 3151 { 3152 3153 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3154 3155 /* XXX */ 3156 } 3157 3158 static void 3159 rtwn_lc_calib(struct rtwn_softc *sc) 3160 { 3161 uint32_t rf_ac[2]; 3162 uint8_t txmode; 3163 int i; 3164 3165 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3166 3167 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3168 if ((txmode & 0x70) != 0) { 3169 /* Disable all continuous Tx. */ 3170 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3171 3172 /* Set RF mode to standby mode. */ 3173 for (i = 0; i < sc->nrxchains; i++) { 3174 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3175 rtwn_rf_write(sc, i, R92C_RF_AC, 3176 RW(rf_ac[i], R92C_RF_AC_MODE, 3177 R92C_RF_AC_MODE_STANDBY)); 3178 } 3179 } else { 3180 /* Block all Tx queues. */ 3181 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3182 } 3183 /* Start calibration. */ 3184 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3185 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3186 3187 /* Give calibration the time to complete. */ 3188 DELAY(100); 3189 3190 /* Restore configuration. */ 3191 if ((txmode & 0x70) != 0) { 3192 /* Restore Tx mode. */ 3193 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3194 /* Restore RF mode. */ 3195 for (i = 0; i < sc->nrxchains; i++) 3196 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3197 } else { 3198 /* Unblock all Tx queues. */ 3199 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3200 } 3201 } 3202 3203 static void 3204 rtwn_temp_calib(struct rtwn_softc *sc) 3205 { 3206 int temp; 3207 3208 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3209 3210 if (sc->thcal_state == 0) { 3211 /* Start measuring temperature. */ 3212 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3213 sc->thcal_state = 1; 3214 return; 3215 } 3216 sc->thcal_state = 0; 3217 3218 /* Read measured temperature. */ 3219 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3220 if (temp == 0) /* Read failed, skip. */ 3221 return; 3222 DPRINTFN(2, ("temperature=%d\n", temp)); 3223 3224 /* 3225 * Redo IQ and LC calibration if temperature changed significantly 3226 * since last calibration. 3227 */ 3228 if (sc->thcal_lctemp == 0) { 3229 /* First calibration is performed in rtwn_init(). */ 3230 sc->thcal_lctemp = temp; 3231 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3232 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3233 sc->thcal_lctemp, temp)); 3234 rtwn_iq_calib(sc); 3235 rtwn_lc_calib(sc); 3236 /* Record temperature of last calibration. */ 3237 sc->thcal_lctemp = temp; 3238 } 3239 } 3240 3241 static int 3242 rtwn_init(struct ifnet *ifp) 3243 { 3244 struct rtwn_softc *sc = ifp->if_softc; 3245 struct ieee80211com *ic = &sc->sc_ic; 3246 uint32_t reg; 3247 int i, error; 3248 3249 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3250 3251 /* Init firmware commands ring. */ 3252 sc->fwcur = 0; 3253 3254 /* Power on adapter. */ 3255 error = rtwn_power_on(sc); 3256 if (error != 0) { 3257 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3258 goto fail; 3259 } 3260 3261 /* Initialize DMA. */ 3262 error = rtwn_dma_init(sc); 3263 if (error != 0) { 3264 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3265 goto fail; 3266 } 3267 3268 /* Set info size in Rx descriptors (in 64-bit words). */ 3269 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3270 3271 /* Disable interrupts. */ 3272 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3273 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3274 3275 /* Set MAC address. */ 3276 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3277 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3278 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3279 3280 /* Set initial network type. */ 3281 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3282 3283 rtwn_rxfilter_init(sc); 3284 3285 reg = rtwn_read_4(sc, R92C_RRSR); 3286 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3287 rtwn_write_4(sc, R92C_RRSR, reg); 3288 3289 /* Set short/long retry limits. */ 3290 rtwn_write_2(sc, R92C_RL, 3291 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3292 3293 /* Initialize EDCA parameters. */ 3294 rtwn_edca_init(sc); 3295 3296 /* Set data and response automatic rate fallback retry counts. */ 3297 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3298 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3299 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3300 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3301 3302 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3303 3304 /* Set ACK timeout. */ 3305 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3306 3307 /* Initialize beacon parameters. */ 3308 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3309 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3310 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3311 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3312 3313 /* Setup AMPDU aggregation. */ 3314 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3315 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3316 3317 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3318 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3319 3320 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3321 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3322 3323 /* Load 8051 microcode. */ 3324 error = rtwn_load_firmware(sc); 3325 if (error != 0) 3326 goto fail; 3327 3328 /* Initialize MAC/BB/RF blocks. */ 3329 rtwn_mac_init(sc); 3330 rtwn_bb_init(sc); 3331 rtwn_rf_init(sc); 3332 3333 /* Turn CCK and OFDM blocks on. */ 3334 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3335 reg |= R92C_RFMOD_CCK_EN; 3336 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3337 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3338 reg |= R92C_RFMOD_OFDM_EN; 3339 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3340 3341 /* Clear per-station keys table. */ 3342 rtwn_cam_init(sc); 3343 3344 /* Enable hardware sequence numbering. */ 3345 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3346 3347 /* Perform LO and IQ calibrations. */ 3348 rtwn_iq_calib(sc); 3349 /* Perform LC calibration. */ 3350 rtwn_lc_calib(sc); 3351 3352 rtwn_pa_bias_init(sc); 3353 3354 /* Initialize GPIO setting. */ 3355 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3356 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3357 3358 /* Fix for lower temperature. */ 3359 rtwn_write_1(sc, 0x15, 0xe9); 3360 3361 /* Set default channel. */ 3362 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3363 3364 /* Clear pending interrupts. */ 3365 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3366 3367 /* Enable interrupts. */ 3368 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3369 3370 /* We're ready to go. */ 3371 ifp->if_flags &= ~IFF_OACTIVE; 3372 ifp->if_flags |= IFF_RUNNING; 3373 3374 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3375 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3376 else 3377 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3378 3379 return 0; 3380 3381 fail: 3382 rtwn_stop(ifp, 1); 3383 return error; 3384 } 3385 3386 static void 3387 rtwn_init_task(void *arg) 3388 { 3389 struct rtwn_softc *sc = arg; 3390 struct ifnet *ifp = GET_IFP(sc); 3391 int s; 3392 3393 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3394 3395 s = splnet(); 3396 3397 rtwn_stop(ifp, 0); 3398 3399 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3400 rtwn_init(ifp); 3401 3402 splx(s); 3403 } 3404 3405 static void 3406 rtwn_stop(struct ifnet *ifp, int disable) 3407 { 3408 struct rtwn_softc *sc = ifp->if_softc; 3409 struct ieee80211com *ic = &sc->sc_ic; 3410 uint16_t reg; 3411 int s, i; 3412 3413 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3414 3415 sc->sc_tx_timer = 0; 3416 ifp->if_timer = 0; 3417 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3418 3419 callout_stop(&sc->scan_to); 3420 callout_stop(&sc->calib_to); 3421 3422 s = splnet(); 3423 3424 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3425 3426 /* Disable interrupts. */ 3427 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3428 3429 /* Pause MAC TX queue */ 3430 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3431 3432 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3433 3434 /* Reset BB state machine */ 3435 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3436 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3437 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3438 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3439 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3440 3441 reg = rtwn_read_2(sc, R92C_CR); 3442 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3443 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3444 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3445 R92C_CR_ENSEC); 3446 rtwn_write_2(sc, R92C_CR, reg); 3447 3448 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3449 rtwn_fw_reset(sc); 3450 3451 /* Reset MAC and Enable 8051 */ 3452 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3453 3454 /* TODO: linux does additional btcoex stuff here */ 3455 3456 /* Disable AFE PLL */ 3457 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3458 /* Enter PFM mode */ 3459 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3460 /* Gated AFE DIG_CLOCK */ 3461 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3462 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3463 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3464 3465 for (i = 0; i < RTWN_NTXQUEUES; i++) 3466 rtwn_reset_tx_list(sc, i); 3467 rtwn_reset_rx_list(sc); 3468 3469 splx(s); 3470 } 3471 3472 static int 3473 rtwn_intr(void *xsc) 3474 { 3475 struct rtwn_softc *sc = xsc; 3476 uint32_t status; 3477 int i; 3478 3479 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3480 return 0; 3481 3482 status = rtwn_read_4(sc, R92C_HISR); 3483 if (status == 0 || status == 0xffffffff) 3484 return 0; 3485 3486 /* Disable interrupts. */ 3487 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3488 3489 /* Ack interrupts. */ 3490 rtwn_write_4(sc, R92C_HISR, status); 3491 3492 /* Vendor driver treats RX errors like ROK... */ 3493 if (status & RTWN_INT_ENABLE_RX) { 3494 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3495 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3496 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3497 3498 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3499 continue; 3500 3501 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3502 } 3503 } 3504 3505 if (status & R92C_IMR_BDOK) 3506 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3507 if (status & R92C_IMR_HIGHDOK) 3508 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3509 if (status & R92C_IMR_MGNTDOK) 3510 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3511 if (status & R92C_IMR_BKDOK) 3512 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3513 if (status & R92C_IMR_BEDOK) 3514 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3515 if (status & R92C_IMR_VIDOK) 3516 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3517 if (status & R92C_IMR_VODOK) 3518 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3519 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3520 struct ifnet *ifp = GET_IFP(sc); 3521 ifp->if_flags &= ~IFF_OACTIVE; 3522 rtwn_start(ifp); 3523 } 3524 3525 /* Enable interrupts. */ 3526 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3527 3528 return 1; 3529 } 3530
Indexes created Thu Oct 02 01:09:59 GMT 2025