if_rtwn.c revision 1.8.2.1
1 /* $NetBSD: if_rtwn.c,v 1.8.2.1 2017/01/07 08:56:33 pgoyette Exp $ */ 2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */ 3 #define IEEE80211_NO_HT 4 /*- 5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.8.2.1 2017/01/07 08:56:33 pgoyette Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/callout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 #include <sys/mutex.h> 39 40 #include <sys/bus.h> 41 #include <sys/intr.h> 42 43 #include <net/bpf.h> 44 #include <net/if.h> 45 #include <net/if_arp.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 51 #include <netinet/in.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/firmload.h> 57 58 #include <dev/pci/pcireg.h> 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcidevs.h> 61 62 #include <dev/pci/if_rtwnreg.h> 63 64 #ifdef RTWN_DEBUG 65 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 66 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 67 int rtwn_debug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n, x) 71 #endif 72 73 /* 74 * PCI configuration space registers. 75 */ 76 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 77 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 78 79 #define RTWN_INT_ENABLE_TX \ 80 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \ 81 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 82 R92C_IMR_HIGHDOK | R92C_IMR_BDOK) 83 #define RTWN_INT_ENABLE_RX \ 84 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW) 85 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX) 86 87 static const struct rtwn_device { 88 pci_vendor_id_t rd_vendor; 89 pci_product_id_t rd_product; 90 } rtwn_devices[] = { 91 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE }, 92 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE } 93 }; 94 95 static int rtwn_match(device_t, cfdata_t, void *); 96 static void rtwn_attach(device_t, device_t, void *); 97 static int rtwn_detach(device_t, int); 98 static int rtwn_activate(device_t, enum devact); 99 100 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match, 101 rtwn_attach, rtwn_detach, rtwn_activate); 102 103 static int rtwn_alloc_rx_list(struct rtwn_softc *); 104 static void rtwn_reset_rx_list(struct rtwn_softc *); 105 static void rtwn_free_rx_list(struct rtwn_softc *); 106 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 107 bus_addr_t, size_t, int); 108 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 109 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 110 static void rtwn_free_tx_list(struct rtwn_softc *, int); 111 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 119 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 121 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 static void rtwn_efuse_read(struct rtwn_softc *); 123 static int rtwn_read_chipid(struct rtwn_softc *); 124 static void rtwn_efuse_switch_power(struct rtwn_softc *); 125 static void rtwn_read_rom(struct rtwn_softc *); 126 static int rtwn_media_change(struct ifnet *); 127 static int rtwn_ra_init(struct rtwn_softc *); 128 static int rtwn_get_nettype(struct rtwn_softc *); 129 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t); 130 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 131 static void rtwn_set_led(struct rtwn_softc *, int, int); 132 static void rtwn_calib_to(void *); 133 static void rtwn_next_scan(void *); 134 static void rtwn_newassoc(struct ieee80211_node *, int); 135 static int rtwn_reset(struct ifnet *); 136 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state, 137 int); 138 static int rtwn_wme_update(struct ieee80211com *); 139 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 140 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 141 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 142 struct rtwn_rx_data *, int); 143 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 144 struct ieee80211_node *); 145 static void rtwn_tx_done(struct rtwn_softc *, int); 146 static void rtwn_start(struct ifnet *); 147 static void rtwn_watchdog(struct ifnet *); 148 static int rtwn_ioctl(struct ifnet *, u_long, void *); 149 static int rtwn_power_on(struct rtwn_softc *); 150 static int rtwn_llt_init(struct rtwn_softc *); 151 static void rtwn_fw_reset(struct rtwn_softc *); 152 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int); 153 static int rtwn_load_firmware(struct rtwn_softc *); 154 static int rtwn_dma_init(struct rtwn_softc *); 155 static void rtwn_mac_init(struct rtwn_softc *); 156 static void rtwn_bb_init(struct rtwn_softc *); 157 static void rtwn_rf_init(struct rtwn_softc *); 158 static void rtwn_cam_init(struct rtwn_softc *); 159 static void rtwn_pa_bias_init(struct rtwn_softc *); 160 static void rtwn_rxfilter_init(struct rtwn_softc *); 161 static void rtwn_edca_init(struct rtwn_softc *); 162 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 163 static void rtwn_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, struct ieee80211_channel *, 165 uint16_t[]); 166 static void rtwn_set_txpower(struct rtwn_softc *, 167 struct ieee80211_channel *, struct ieee80211_channel *); 168 static void rtwn_set_chan(struct rtwn_softc *, 169 struct ieee80211_channel *, struct ieee80211_channel *); 170 static void rtwn_iq_calib(struct rtwn_softc *); 171 static void rtwn_lc_calib(struct rtwn_softc *); 172 static void rtwn_temp_calib(struct rtwn_softc *); 173 static int rtwn_init(struct ifnet *); 174 static void rtwn_init_task(void *); 175 static void rtwn_stop(struct ifnet *, int); 176 static int rtwn_intr(void *); 177 178 /* Aliases. */ 179 #define rtwn_bb_write rtwn_write_4 180 #define rtwn_bb_read rtwn_read_4 181 182 static const struct rtwn_device * 183 rtwn_lookup(const struct pci_attach_args *pa) 184 { 185 const struct rtwn_device *rd; 186 int i; 187 188 for (i = 0; i < __arraycount(rtwn_devices); i++) { 189 rd = &rtwn_devices[i]; 190 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor && 191 PCI_PRODUCT(pa->pa_id) == rd->rd_product) 192 return rd; 193 } 194 return NULL; 195 } 196 197 static int 198 rtwn_match(device_t parent, cfdata_t match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 202 if (rtwn_lookup(pa) != NULL) 203 return 1; 204 return 0; 205 } 206 207 static void 208 rtwn_attach(device_t parent, device_t self, void *aux) 209 { 210 struct rtwn_softc *sc = device_private(self); 211 struct pci_attach_args *pa = aux; 212 struct ieee80211com *ic = &sc->sc_ic; 213 struct ifnet *ifp = GET_IFP(sc); 214 int i, error; 215 pcireg_t memtype; 216 const char *intrstr; 217 char intrbuf[PCI_INTRSTR_LEN]; 218 219 sc->sc_dev = self; 220 sc->sc_dmat = pa->pa_dmat; 221 sc->sc_pc = pa->pa_pc; 222 sc->sc_tag = pa->pa_tag; 223 224 pci_aprint_devinfo(pa, NULL); 225 226 callout_init(&sc->scan_to, 0); 227 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc); 228 callout_init(&sc->calib_to, 0); 229 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc); 230 231 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc); 232 233 /* Power up the device */ 234 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 235 236 /* Map control/status registers. */ 237 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA); 238 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st, 239 &sc->sc_sh, NULL, &sc->sc_mapsize); 240 if (error != 0) { 241 aprint_error_dev(self, "can't map mem space\n"); 242 return; 243 } 244 245 /* Install interrupt handler. */ 246 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) { 247 aprint_error_dev(self, "can't map interrupt\n"); 248 return; 249 } 250 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf, 251 sizeof(intrbuf)); 252 sc->sc_ih = pci_intr_establish(sc->sc_pc, sc->sc_pihp[0], IPL_NET, 253 rtwn_intr, sc); 254 if (sc->sc_ih == NULL) { 255 aprint_error_dev(self, "can't establish interrupt"); 256 if (intrstr != NULL) 257 aprint_error(" at %s", intrstr); 258 aprint_error("\n"); 259 return; 260 } 261 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 262 263 error = rtwn_read_chipid(sc); 264 if (error != 0) { 265 aprint_error_dev(self, "unsupported test or unknown chip\n"); 266 return; 267 } 268 269 /* Disable PCIe Active State Power Management (ASPM). */ 270 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS, 271 &sc->sc_cap_off, NULL)) { 272 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag, 273 sc->sc_cap_off + PCIE_LCSR); 274 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1); 275 pci_conf_write(sc->sc_pc, sc->sc_tag, 276 sc->sc_cap_off + PCIE_LCSR, lcsr); 277 } 278 279 /* Allocate Tx/Rx buffers. */ 280 error = rtwn_alloc_rx_list(sc); 281 if (error != 0) { 282 aprint_error_dev(self, "could not allocate Rx buffers\n"); 283 return; 284 } 285 for (i = 0; i < RTWN_NTXQUEUES; i++) { 286 error = rtwn_alloc_tx_list(sc, i); 287 if (error != 0) { 288 aprint_error_dev(self, 289 "could not allocate Tx buffers\n"); 290 return; 291 } 292 } 293 294 /* Determine number of Tx/Rx chains. */ 295 if (sc->chip & RTWN_CHIP_92C) { 296 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 297 sc->nrxchains = 2; 298 } else { 299 sc->ntxchains = 1; 300 sc->nrxchains = 1; 301 } 302 rtwn_read_rom(sc); 303 304 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 305 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 306 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 307 308 /* 309 * Setup the 802.11 device. 310 */ 311 ic->ic_ifp = ifp; 312 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 313 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 314 ic->ic_state = IEEE80211_S_INIT; 315 316 /* Set device capabilities. */ 317 ic->ic_caps = 318 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 319 IEEE80211_C_IBSS | /* IBSS mode supported */ 320 IEEE80211_C_HOSTAP | /* HostAp mode supported */ 321 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 322 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 323 IEEE80211_C_WME | /* 802.11e */ 324 IEEE80211_C_WPA; /* WPA/RSN. */ 325 326 #ifndef IEEE80211_NO_HT 327 /* Set HT capabilities. */ 328 ic->ic_htcaps = 329 IEEE80211_HTCAP_CBW20_40 | 330 IEEE80211_HTCAP_DSSSCCK40; 331 /* Set supported HT rates. */ 332 for (i = 0; i < sc->nrxchains; i++) 333 ic->ic_sup_mcs[i] = 0xff; 334 #endif 335 336 /* Set supported .11b and .11g rates. */ 337 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 338 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 339 340 /* Set supported .11b and .11g channels (1 through 14). */ 341 for (i = 1; i <= 14; i++) { 342 ic->ic_channels[i].ic_freq = 343 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 344 ic->ic_channels[i].ic_flags = 345 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 346 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 347 } 348 349 ifp->if_softc = sc; 350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 351 ifp->if_init = rtwn_init; 352 ifp->if_ioctl = rtwn_ioctl; 353 ifp->if_start = rtwn_start; 354 ifp->if_watchdog = rtwn_watchdog; 355 IFQ_SET_READY(&ifp->if_snd); 356 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 357 358 if_initialize(ifp); 359 ieee80211_ifattach(ic); 360 /* Use common softint-based if_input */ 361 ifp->if_percpuq = if_percpuq_create(ifp); 362 if_deferred_start_init(ifp, NULL); 363 if_register(ifp); 364 365 /* override default methods */ 366 ic->ic_newassoc = rtwn_newassoc; 367 ic->ic_reset = rtwn_reset; 368 ic->ic_wme.wme_update = rtwn_wme_update; 369 370 /* Override state transition machine. */ 371 sc->sc_newstate = ic->ic_newstate; 372 ic->ic_newstate = rtwn_newstate; 373 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status); 374 375 bpf_attach2(ifp, DLT_IEEE802_11_RADIO, 376 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN, 377 &sc->sc_drvbpf); 378 379 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 380 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 381 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT); 382 383 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 384 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 385 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT); 386 387 ieee80211_announce(ic); 388 389 if (!pmf_device_register(self, NULL, NULL)) 390 aprint_error_dev(self, "couldn't establish power handler\n"); 391 } 392 393 static int 394 rtwn_detach(device_t self, int flags) 395 { 396 struct rtwn_softc *sc = device_private(self); 397 struct ieee80211com *ic = &sc->sc_ic; 398 struct ifnet *ifp = GET_IFP(sc); 399 int s, i; 400 401 callout_stop(&sc->scan_to); 402 callout_stop(&sc->calib_to); 403 404 s = splnet(); 405 406 if (ifp->if_softc != NULL) { 407 rtwn_stop(ifp, 0); 408 409 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 410 bpf_detach(ifp); 411 ieee80211_ifdetach(ic); 412 if_detach(ifp); 413 } 414 415 /* Free Tx/Rx buffers. */ 416 for (i = 0; i < RTWN_NTXQUEUES; i++) 417 rtwn_free_tx_list(sc, i); 418 rtwn_free_rx_list(sc); 419 420 splx(s); 421 422 callout_destroy(&sc->scan_to); 423 callout_destroy(&sc->calib_to); 424 425 if (sc->init_task != NULL) 426 softint_disestablish(sc->init_task); 427 428 if (sc->sc_ih != NULL) { 429 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 430 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 431 } 432 433 pmf_device_deregister(self); 434 435 return 0; 436 } 437 438 static int 439 rtwn_activate(device_t self, enum devact act) 440 { 441 struct rtwn_softc *sc = device_private(self); 442 struct ifnet *ifp = GET_IFP(sc); 443 444 switch (act) { 445 case DVACT_DEACTIVATE: 446 if (ifp->if_flags & IFF_RUNNING) 447 rtwn_stop(ifp, 0); 448 return 0; 449 default: 450 return EOPNOTSUPP; 451 } 452 } 453 454 static void 455 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 456 bus_addr_t addr, size_t len, int idx) 457 { 458 459 memset(desc, 0, sizeof(*desc)); 460 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 461 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 462 desc->rxbufaddr = htole32(addr); 463 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 464 BUS_SPACE_BARRIER_WRITE); 465 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 466 } 467 468 static int 469 rtwn_alloc_rx_list(struct rtwn_softc *sc) 470 { 471 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 472 struct rtwn_rx_data *rx_data; 473 const size_t size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 474 int i, error = 0; 475 476 /* Allocate Rx descriptors. */ 477 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 478 &rx_ring->map); 479 if (error != 0) { 480 aprint_error_dev(sc->sc_dev, 481 "could not create rx desc DMA map\n"); 482 rx_ring->map = NULL; 483 goto fail; 484 } 485 486 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1, 487 &rx_ring->nsegs, BUS_DMA_NOWAIT); 488 if (error != 0) { 489 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n"); 490 goto fail; 491 } 492 493 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, 494 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 495 if (error != 0) { 496 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); 497 rx_ring->desc = NULL; 498 aprint_error_dev(sc->sc_dev, "could not map rx desc\n"); 499 goto fail; 500 } 501 memset(rx_ring->desc, 0, size); 502 503 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg, 504 1, size, BUS_DMA_NOWAIT); 505 if (error != 0) { 506 aprint_error_dev(sc->sc_dev, "could not load rx desc\n"); 507 goto fail; 508 } 509 510 /* Allocate Rx buffers. */ 511 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 512 rx_data = &rx_ring->rx_data[i]; 513 514 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 515 0, BUS_DMA_NOWAIT, &rx_data->map); 516 if (error != 0) { 517 aprint_error_dev(sc->sc_dev, 518 "could not create rx buf DMA map\n"); 519 goto fail; 520 } 521 522 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA); 523 if (__predict_false(rx_data->m == NULL)) { 524 aprint_error_dev(sc->sc_dev, 525 "couldn't allocate rx mbuf\n"); 526 error = ENOMEM; 527 goto fail; 528 } 529 MCLGET(rx_data->m, M_DONTWAIT); 530 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) { 531 aprint_error_dev(sc->sc_dev, 532 "couldn't allocate rx mbuf cluster\n"); 533 m_free(rx_data->m); 534 rx_data->m = NULL; 535 error = ENOMEM; 536 goto fail; 537 } 538 539 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, 540 mtod(rx_data->m, void *), MCLBYTES, NULL, 541 BUS_DMA_NOWAIT | BUS_DMA_READ); 542 if (error != 0) { 543 aprint_error_dev(sc->sc_dev, 544 "could not load rx buf DMA map\n"); 545 goto fail; 546 } 547 548 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 549 BUS_DMASYNC_PREREAD); 550 551 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 552 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 553 } 554 fail: if (error != 0) 555 rtwn_free_rx_list(sc); 556 return error; 557 } 558 559 static void 560 rtwn_reset_rx_list(struct rtwn_softc *sc) 561 { 562 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 563 struct rtwn_rx_data *rx_data; 564 int i; 565 566 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 567 rx_data = &rx_ring->rx_data[i]; 568 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], 569 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i); 570 } 571 } 572 573 static void 574 rtwn_free_rx_list(struct rtwn_softc *sc) 575 { 576 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 577 struct rtwn_rx_data *rx_data; 578 int i, s; 579 580 s = splnet(); 581 582 if (rx_ring->map) { 583 if (rx_ring->desc) { 584 bus_dmamap_unload(sc->sc_dmat, rx_ring->map); 585 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc, 586 sizeof (struct r92c_rx_desc) * RTWN_RX_LIST_COUNT); 587 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, 588 rx_ring->nsegs); 589 rx_ring->desc = NULL; 590 } 591 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map); 592 rx_ring->map = NULL; 593 } 594 595 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 596 rx_data = &rx_ring->rx_data[i]; 597 598 if (rx_data->m != NULL) { 599 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 600 m_freem(rx_data->m); 601 rx_data->m = NULL; 602 } 603 bus_dmamap_destroy(sc->sc_dmat, rx_data->map); 604 rx_data->map = NULL; 605 } 606 607 splx(s); 608 } 609 610 static int 611 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 612 { 613 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 614 struct rtwn_tx_data *tx_data; 615 const size_t size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 616 int i = 0, error = 0; 617 618 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, 619 &tx_ring->map); 620 if (error != 0) { 621 aprint_error_dev(sc->sc_dev, 622 "could not create tx ring DMA map\n"); 623 goto fail; 624 } 625 626 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 627 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT); 628 if (error != 0) { 629 aprint_error_dev(sc->sc_dev, 630 "could not allocate tx ring DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs, 635 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT); 636 if (error != 0) { 637 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs); 638 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n"); 639 goto fail; 640 } 641 memset(tx_ring->desc, 0, size); 642 643 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc, 644 size, NULL, BUS_DMA_NOWAIT); 645 if (error != 0) { 646 aprint_error_dev(sc->sc_dev, 647 "could not load tx ring DMA map\n"); 648 goto fail; 649 } 650 651 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 652 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 653 654 /* setup tx desc */ 655 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr 656 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT)); 657 658 tx_data = &tx_ring->tx_data[i]; 659 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 660 0, BUS_DMA_NOWAIT, &tx_data->map); 661 if (error != 0) { 662 aprint_error_dev(sc->sc_dev, 663 "could not create tx buf DMA map\n"); 664 goto fail; 665 } 666 tx_data->m = NULL; 667 tx_data->ni = NULL; 668 } 669 670 fail: 671 if (error != 0) 672 rtwn_free_tx_list(sc, qid); 673 return error; 674 } 675 676 static void 677 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 678 { 679 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 680 int i; 681 682 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 683 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 684 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 685 686 memset(desc, 0, sizeof(*desc) - 687 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 688 sizeof(desc->nextdescaddr))); 689 690 if (tx_data->m != NULL) { 691 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 692 m_freem(tx_data->m); 693 tx_data->m = NULL; 694 ieee80211_free_node(tx_data->ni); 695 tx_data->ni = NULL; 696 } 697 } 698 699 sc->qfullmsk &= ~(1 << qid); 700 tx_ring->queued = 0; 701 tx_ring->cur = 0; 702 } 703 704 static void 705 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 706 { 707 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 708 struct rtwn_tx_data *tx_data; 709 int i; 710 711 if (tx_ring->map != NULL) { 712 if (tx_ring->desc != NULL) { 713 bus_dmamap_unload(sc->sc_dmat, tx_ring->map); 714 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc, 715 sizeof (struct r92c_tx_desc) * RTWN_TX_LIST_COUNT); 716 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, 717 tx_ring->nsegs); 718 } 719 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map); 720 } 721 722 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 723 tx_data = &tx_ring->tx_data[i]; 724 725 if (tx_data->m != NULL) { 726 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 727 m_freem(tx_data->m); 728 tx_data->m = NULL; 729 } 730 bus_dmamap_destroy(sc->sc_dmat, tx_data->map); 731 } 732 733 sc->qfullmsk &= ~(1 << qid); 734 tx_ring->queued = 0; 735 tx_ring->cur = 0; 736 } 737 738 static void 739 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 740 { 741 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 742 } 743 744 static void 745 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 746 { 747 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val)); 748 } 749 750 static void 751 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 752 { 753 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val)); 754 } 755 756 static uint8_t 757 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 758 { 759 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr); 760 } 761 762 static uint16_t 763 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 764 { 765 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 766 } 767 768 static uint32_t 769 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 770 { 771 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 772 } 773 774 static int 775 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 776 { 777 struct r92c_fw_cmd cmd; 778 uint8_t *cp; 779 int fwcur; 780 int ntries; 781 782 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n", 783 device_xname(sc->sc_dev), __func__, id, buf, len)); 784 785 fwcur = sc->fwcur; 786 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 787 788 /* Wait for current FW box to be empty. */ 789 for (ntries = 0; ntries < 100; ntries++) { 790 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 791 break; 792 DELAY(1); 793 } 794 if (ntries == 100) { 795 aprint_error_dev(sc->sc_dev, 796 "could not send firmware command %d\n", id); 797 return ETIMEDOUT; 798 } 799 800 memset(&cmd, 0, sizeof(cmd)); 801 KASSERT(len <= sizeof(cmd.msg)); 802 memcpy(cmd.msg, buf, len); 803 804 /* Write the first word last since that will trigger the FW. */ 805 cp = (uint8_t *)&cmd; 806 if (len >= 4) { 807 cmd.id = id | R92C_CMD_FLAG_EXT; 808 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8)); 809 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 810 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24)); 811 } else { 812 cmd.id = id; 813 rtwn_write_4(sc, R92C_HMEBOX(fwcur), 814 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24)); 815 } 816 817 /* Give firmware some time for processing. */ 818 DELAY(2000); 819 820 return 0; 821 } 822 823 static void 824 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 825 { 826 827 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 828 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val)); 829 } 830 831 static uint32_t 832 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 833 { 834 uint32_t reg[R92C_MAX_CHAINS], val; 835 836 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 837 if (chain != 0) 838 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 839 840 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 841 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 842 DELAY(1000); 843 844 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 845 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 846 R92C_HSSI_PARAM2_READ_EDGE); 847 DELAY(1000); 848 849 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 850 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 851 DELAY(1000); 852 853 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 854 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 855 else 856 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 857 return MS(val, R92C_LSSI_READBACK_DATA); 858 } 859 860 static int 861 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 862 { 863 int ntries; 864 865 rtwn_write_4(sc, R92C_LLT_INIT, 866 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 867 SM(R92C_LLT_INIT_ADDR, addr) | 868 SM(R92C_LLT_INIT_DATA, data)); 869 /* Wait for write operation to complete. */ 870 for (ntries = 0; ntries < 20; ntries++) { 871 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 872 R92C_LLT_INIT_OP_NO_ACTIVE) 873 return 0; 874 DELAY(5); 875 } 876 return ETIMEDOUT; 877 } 878 879 static uint8_t 880 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 881 { 882 uint32_t reg; 883 int ntries; 884 885 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 886 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 887 reg &= ~R92C_EFUSE_CTRL_VALID; 888 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 889 /* Wait for read operation to complete. */ 890 for (ntries = 0; ntries < 100; ntries++) { 891 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 892 if (reg & R92C_EFUSE_CTRL_VALID) 893 return MS(reg, R92C_EFUSE_CTRL_DATA); 894 DELAY(5); 895 } 896 aprint_error_dev(sc->sc_dev, 897 "could not read efuse byte at address 0x%x\n", addr); 898 return 0xff; 899 } 900 901 static void 902 rtwn_efuse_read(struct rtwn_softc *sc) 903 { 904 uint8_t *rom = (uint8_t *)&sc->rom; 905 uint32_t reg; 906 uint16_t addr = 0; 907 uint8_t off, msk; 908 int i; 909 910 rtwn_efuse_switch_power(sc); 911 912 memset(&sc->rom, 0xff, sizeof(sc->rom)); 913 while (addr < 512) { 914 reg = rtwn_efuse_read_1(sc, addr); 915 if (reg == 0xff) 916 break; 917 addr++; 918 off = reg >> 4; 919 msk = reg & 0xf; 920 for (i = 0; i < 4; i++) { 921 if (msk & (1 << i)) 922 continue; 923 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 924 addr++; 925 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 926 addr++; 927 } 928 } 929 #ifdef RTWN_DEBUG 930 if (rtwn_debug >= 2) { 931 /* Dump ROM content. */ 932 printf("\n"); 933 for (i = 0; i < sizeof(sc->rom); i++) 934 printf("%02x:", rom[i]); 935 printf("\n"); 936 } 937 #endif 938 } 939 940 static void 941 rtwn_efuse_switch_power(struct rtwn_softc *sc) 942 { 943 uint32_t reg; 944 945 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 946 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 947 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 948 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 949 } 950 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 951 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 952 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 953 reg | R92C_SYS_FUNC_EN_ELDR); 954 } 955 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 956 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 957 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 958 rtwn_write_2(sc, R92C_SYS_CLKR, 959 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 960 } 961 } 962 963 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */ 964 static int 965 rtwn_read_chipid(struct rtwn_softc *sc) 966 { 967 uint32_t reg; 968 969 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 970 971 reg = rtwn_read_4(sc, R92C_SYS_CFG); 972 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg)); 973 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 974 /* Unsupported test chip. */ 975 return EIO; 976 977 if (reg & R92C_SYS_CFG_TYPE_92C) { 978 sc->chip |= RTWN_CHIP_92C; 979 /* Check if it is a castrated 8192C. */ 980 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 981 R92C_HPON_FSM_CHIP_BONDING_ID) == 982 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 983 sc->chip |= RTWN_CHIP_92C_1T2R; 984 } 985 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 986 sc->chip |= RTWN_CHIP_UMC; 987 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 988 sc->chip |= RTWN_CHIP_UMC_A_CUT; 989 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) { 990 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1) 991 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT; 992 else 993 /* Unsupported unknown chip. */ 994 return EIO; 995 } 996 return 0; 997 } 998 999 static void 1000 rtwn_read_rom(struct rtwn_softc *sc) 1001 { 1002 struct ieee80211com *ic = &sc->sc_ic; 1003 struct r92c_rom *rom = &sc->rom; 1004 1005 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1006 1007 /* Read full ROM image. */ 1008 rtwn_efuse_read(sc); 1009 1010 if (rom->id != 0x8129) { 1011 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n", 1012 rom->id); 1013 } 1014 1015 /* XXX Weird but this is what the vendor driver does. */ 1016 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1017 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1018 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1019 1020 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n", 1021 sc->pa_setting, sc->board_type, sc->regulatory)); 1022 1023 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 1024 } 1025 1026 static int 1027 rtwn_media_change(struct ifnet *ifp) 1028 { 1029 int error; 1030 1031 error = ieee80211_media_change(ifp); 1032 if (error != ENETRESET) 1033 return error; 1034 1035 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1036 (IFF_UP | IFF_RUNNING)) { 1037 rtwn_stop(ifp, 0); 1038 error = rtwn_init(ifp); 1039 } 1040 return error; 1041 } 1042 1043 /* 1044 * Initialize rate adaptation in firmware. 1045 */ 1046 static int 1047 rtwn_ra_init(struct rtwn_softc *sc) 1048 { 1049 static const uint8_t map[] = { 1050 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 1051 }; 1052 struct ieee80211com *ic = &sc->sc_ic; 1053 struct ieee80211_node *ni = ic->ic_bss; 1054 struct ieee80211_rateset *rs = &ni->ni_rates; 1055 struct r92c_fw_cmd_macid_cfg cmd; 1056 uint32_t rates, basicrates; 1057 uint8_t mode; 1058 int maxrate, maxbasicrate, error, i, j; 1059 1060 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1061 1062 /* Get normal and basic rates mask. */ 1063 rates = basicrates = 0; 1064 maxrate = maxbasicrate = 0; 1065 for (i = 0; i < rs->rs_nrates; i++) { 1066 /* Convert 802.11 rate to HW rate index. */ 1067 for (j = 0; j < __arraycount(map); j++) 1068 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1069 break; 1070 if (j == __arraycount(map)) /* Unknown rate, skip. */ 1071 continue; 1072 rates |= 1 << j; 1073 if (j > maxrate) 1074 maxrate = j; 1075 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1076 basicrates |= 1 << j; 1077 if (j > maxbasicrate) 1078 maxbasicrate = j; 1079 } 1080 } 1081 if (ic->ic_curmode == IEEE80211_MODE_11B) 1082 mode = R92C_RAID_11B; 1083 else 1084 mode = R92C_RAID_11BG; 1085 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1086 device_xname(sc->sc_dev), mode, rates, basicrates)); 1087 if (basicrates == 0) 1088 basicrates |= 1; /* add 1Mbps */ 1089 1090 /* Set rates mask for group addressed frames. */ 1091 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1092 cmd.mask = htole32((mode << 28) | basicrates); 1093 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1094 if (error != 0) { 1095 aprint_error_dev(sc->sc_dev, 1096 "could not add broadcast station\n"); 1097 return error; 1098 } 1099 /* Set initial MRR rate. */ 1100 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev), 1101 maxbasicrate)); 1102 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate); 1103 1104 /* Set rates mask for unicast frames. */ 1105 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1106 cmd.mask = htole32((mode << 28) | rates); 1107 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1108 if (error != 0) { 1109 aprint_error_dev(sc->sc_dev, "could not add BSS station\n"); 1110 return error; 1111 } 1112 /* Set initial MRR rate. */ 1113 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate)); 1114 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate); 1115 1116 /* Configure Automatic Rate Fallback Register. */ 1117 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1118 if (rates & 0x0c) 1119 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1120 else 1121 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1122 } else 1123 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1124 1125 /* Indicate highest supported rate. */ 1126 ni->ni_txrate = rs->rs_nrates - 1; 1127 return 0; 1128 } 1129 1130 static int 1131 rtwn_get_nettype(struct rtwn_softc *sc) 1132 { 1133 struct ieee80211com *ic = &sc->sc_ic; 1134 int type; 1135 1136 switch (ic->ic_opmode) { 1137 case IEEE80211_M_STA: 1138 type = R92C_CR_NETTYPE_INFRA; 1139 break; 1140 1141 case IEEE80211_M_HOSTAP: 1142 type = R92C_CR_NETTYPE_AP; 1143 break; 1144 1145 case IEEE80211_M_IBSS: 1146 type = R92C_CR_NETTYPE_ADHOC; 1147 break; 1148 1149 default: 1150 type = R92C_CR_NETTYPE_NOLINK; 1151 break; 1152 } 1153 1154 return type; 1155 } 1156 1157 static void 1158 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type) 1159 { 1160 uint32_t reg; 1161 1162 reg = rtwn_read_4(sc, R92C_CR); 1163 reg = RW(reg, R92C_CR_NETTYPE, type); 1164 rtwn_write_4(sc, R92C_CR, reg); 1165 } 1166 1167 static void 1168 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1169 { 1170 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 1171 uint64_t tsf; 1172 1173 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1174 1175 /* Enable TSF synchronization. */ 1176 rtwn_write_1(sc, R92C_BCN_CTRL, 1177 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1178 1179 rtwn_write_1(sc, R92C_BCN_CTRL, 1180 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1181 1182 /* Set initial TSF. */ 1183 tsf = ni->ni_tstamp.tsf; 1184 tsf = le64toh(tsf); 1185 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 1186 tsf -= IEEE80211_DUR_TU; 1187 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf); 1188 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32)); 1189 1190 rtwn_write_1(sc, R92C_BCN_CTRL, 1191 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1192 } 1193 1194 static void 1195 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1196 { 1197 uint8_t reg; 1198 1199 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1200 1201 if (led == RTWN_LED_LINK) { 1202 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1203 if (!on) 1204 reg |= R92C_LEDCFG2_DIS; 1205 else 1206 reg |= R92C_LEDCFG2_EN; 1207 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1208 sc->ledlink = on; /* Save LED state. */ 1209 } 1210 } 1211 1212 static void 1213 rtwn_calib_to(void *arg) 1214 { 1215 struct rtwn_softc *sc = arg; 1216 struct r92c_fw_cmd_rssi cmd; 1217 1218 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1219 1220 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) 1221 goto restart_timer; 1222 1223 if (sc->avg_pwdb != -1) { 1224 /* Indicate Rx signal strength to FW for rate adaptation. */ 1225 memset(&cmd, 0, sizeof(cmd)); 1226 cmd.macid = 0; /* BSS. */ 1227 cmd.pwdb = sc->avg_pwdb; 1228 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1229 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1230 } 1231 1232 /* Do temperature compensation. */ 1233 rtwn_temp_calib(sc); 1234 1235 restart_timer: 1236 callout_schedule(&sc->calib_to, mstohz(2000)); 1237 } 1238 1239 static void 1240 rtwn_next_scan(void *arg) 1241 { 1242 struct rtwn_softc *sc = arg; 1243 struct ieee80211com *ic = &sc->sc_ic; 1244 int s; 1245 1246 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1247 1248 s = splnet(); 1249 if (ic->ic_state == IEEE80211_S_SCAN) 1250 ieee80211_next_scan(ic); 1251 splx(s); 1252 } 1253 1254 static void 1255 rtwn_newassoc(struct ieee80211_node *ni, int isnew) 1256 { 1257 1258 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr))); 1259 1260 /* start with lowest Tx rate */ 1261 ni->ni_txrate = 0; 1262 } 1263 1264 static int 1265 rtwn_reset(struct ifnet *ifp) 1266 { 1267 struct rtwn_softc *sc = ifp->if_softc; 1268 struct ieee80211com *ic = &sc->sc_ic; 1269 1270 if (ic->ic_opmode != IEEE80211_M_MONITOR) 1271 return ENETRESET; 1272 1273 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1274 1275 return 0; 1276 } 1277 1278 static int 1279 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1280 { 1281 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1282 struct ieee80211_node *ni; 1283 enum ieee80211_state ostate = ic->ic_state; 1284 uint32_t reg; 1285 int s; 1286 1287 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1288 1289 s = splnet(); 1290 1291 callout_stop(&sc->scan_to); 1292 callout_stop(&sc->calib_to); 1293 1294 if (ostate != nstate) { 1295 DPRINTF(("%s: %s -> %s\n", __func__, 1296 ieee80211_state_name[ostate], 1297 ieee80211_state_name[nstate])); 1298 } 1299 1300 switch (ostate) { 1301 case IEEE80211_S_INIT: 1302 break; 1303 1304 case IEEE80211_S_SCAN: 1305 if (nstate != IEEE80211_S_SCAN) { 1306 /* 1307 * End of scanning 1308 */ 1309 /* flush 4-AC Queue after site_survey */ 1310 rtwn_write_1(sc, R92C_TXPAUSE, 0x0); 1311 1312 /* Allow Rx from our BSSID only. */ 1313 rtwn_write_4(sc, R92C_RCR, 1314 rtwn_read_4(sc, R92C_RCR) | 1315 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1316 } 1317 break; 1318 1319 case IEEE80211_S_AUTH: 1320 case IEEE80211_S_ASSOC: 1321 break; 1322 1323 case IEEE80211_S_RUN: 1324 /* Turn link LED off. */ 1325 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1326 1327 /* Set media status to 'No Link'. */ 1328 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1329 1330 /* Stop Rx of data frames. */ 1331 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1332 1333 /* Rest TSF. */ 1334 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1335 1336 /* Disable TSF synchronization. */ 1337 rtwn_write_1(sc, R92C_BCN_CTRL, 1338 rtwn_read_1(sc, R92C_BCN_CTRL) | 1339 R92C_BCN_CTRL_DIS_TSF_UDT0); 1340 1341 /* Back to 20MHz mode */ 1342 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1343 1344 /* Reset EDCA parameters. */ 1345 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1346 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1347 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1348 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1349 1350 /* flush all cam entries */ 1351 rtwn_cam_init(sc); 1352 break; 1353 } 1354 1355 switch (nstate) { 1356 case IEEE80211_S_INIT: 1357 /* Turn link LED off. */ 1358 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1359 break; 1360 1361 case IEEE80211_S_SCAN: 1362 if (ostate != IEEE80211_S_SCAN) { 1363 /* 1364 * Begin of scanning 1365 */ 1366 1367 /* Set gain for scanning. */ 1368 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1369 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1370 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1371 1372 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1373 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1374 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1375 1376 /* Allow Rx from any BSSID. */ 1377 rtwn_write_4(sc, R92C_RCR, 1378 rtwn_read_4(sc, R92C_RCR) & 1379 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1380 1381 /* Stop Rx of data frames. */ 1382 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1383 1384 /* Disable update TSF */ 1385 rtwn_write_1(sc, R92C_BCN_CTRL, 1386 rtwn_read_1(sc, R92C_BCN_CTRL) | 1387 R92C_BCN_CTRL_DIS_TSF_UDT0); 1388 } 1389 1390 /* Make link LED blink during scan. */ 1391 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1392 1393 /* Pause AC Tx queues. */ 1394 rtwn_write_1(sc, R92C_TXPAUSE, 1395 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1396 1397 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1398 1399 /* Start periodic scan. */ 1400 callout_schedule(&sc->scan_to, mstohz(200)); 1401 break; 1402 1403 case IEEE80211_S_AUTH: 1404 /* Set initial gain under link. */ 1405 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1406 #ifdef doaslinux 1407 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1408 #else 1409 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1410 #endif 1411 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1412 1413 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1414 #ifdef doaslinux 1415 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1416 #else 1417 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1418 #endif 1419 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1420 1421 /* Set media status to 'No Link'. */ 1422 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1423 1424 /* Allow Rx from any BSSID. */ 1425 rtwn_write_4(sc, R92C_RCR, 1426 rtwn_read_4(sc, R92C_RCR) & 1427 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1428 1429 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1430 break; 1431 1432 case IEEE80211_S_ASSOC: 1433 break; 1434 1435 case IEEE80211_S_RUN: 1436 ni = ic->ic_bss; 1437 1438 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1439 1440 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1441 /* Back to 20Mhz mode */ 1442 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1443 1444 /* Set media status to 'No Link'. */ 1445 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK); 1446 1447 /* Enable Rx of data frames. */ 1448 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1449 1450 /* Allow Rx from any BSSID. */ 1451 rtwn_write_4(sc, R92C_RCR, 1452 rtwn_read_4(sc, R92C_RCR) & 1453 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1454 1455 /* Accept Rx data/control/management frames */ 1456 rtwn_write_4(sc, R92C_RCR, 1457 rtwn_read_4(sc, R92C_RCR) | 1458 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF); 1459 1460 /* Turn link LED on. */ 1461 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1462 break; 1463 } 1464 1465 /* Set media status to 'Associated'. */ 1466 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 1467 1468 /* Set BSSID. */ 1469 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1470 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1471 1472 if (ic->ic_curmode == IEEE80211_MODE_11B) 1473 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1474 else /* 802.11b/g */ 1475 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1476 1477 /* Enable Rx of data frames. */ 1478 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1479 1480 /* Flush all AC queues. */ 1481 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1482 1483 /* Set beacon interval. */ 1484 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1485 1486 switch (ic->ic_opmode) { 1487 case IEEE80211_M_STA: 1488 /* Allow Rx from our BSSID only. */ 1489 rtwn_write_4(sc, R92C_RCR, 1490 rtwn_read_4(sc, R92C_RCR) | 1491 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1492 1493 /* Enable TSF synchronization. */ 1494 rtwn_tsf_sync_enable(sc); 1495 break; 1496 1497 case IEEE80211_M_HOSTAP: 1498 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f); 1499 1500 /* Allow Rx from any BSSID. */ 1501 rtwn_write_4(sc, R92C_RCR, 1502 rtwn_read_4(sc, R92C_RCR) & 1503 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1504 1505 /* Reset TSF timer to zero. */ 1506 reg = rtwn_read_4(sc, R92C_TCR); 1507 reg &= ~0x01; 1508 rtwn_write_4(sc, R92C_TCR, reg); 1509 reg |= 0x01; 1510 rtwn_write_4(sc, R92C_TCR, reg); 1511 break; 1512 1513 case IEEE80211_M_MONITOR: 1514 default: 1515 break; 1516 } 1517 1518 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1519 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1520 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1521 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1522 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1523 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1524 1525 /* Intialize rate adaptation. */ 1526 rtwn_ra_init(sc); 1527 1528 /* Turn link LED on. */ 1529 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1530 1531 /* Reset average RSSI. */ 1532 sc->avg_pwdb = -1; 1533 1534 /* Reset temperature calibration state machine. */ 1535 sc->thcal_state = 0; 1536 sc->thcal_lctemp = 0; 1537 1538 /* Start periodic calibration. */ 1539 callout_schedule(&sc->calib_to, mstohz(2000)); 1540 break; 1541 } 1542 1543 (void)sc->sc_newstate(ic, nstate, arg); 1544 1545 splx(s); 1546 1547 return 0; 1548 } 1549 1550 static int 1551 rtwn_wme_update(struct ieee80211com *ic) 1552 { 1553 static const uint16_t aci2reg[WME_NUM_AC] = { 1554 R92C_EDCA_BE_PARAM, 1555 R92C_EDCA_BK_PARAM, 1556 R92C_EDCA_VI_PARAM, 1557 R92C_EDCA_VO_PARAM 1558 }; 1559 struct rtwn_softc *sc = IC2IFP(ic)->if_softc; 1560 const struct wmeParams *wmep; 1561 int s, aci, aifs, slottime; 1562 1563 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1564 1565 s = splnet(); 1566 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1567 for (aci = 0; aci < WME_NUM_AC; aci++) { 1568 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1569 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1570 aifs = wmep->wmep_aifsn * slottime + 10; 1571 rtwn_write_4(sc, aci2reg[aci], 1572 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) | 1573 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) | 1574 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) | 1575 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1576 } 1577 splx(s); 1578 1579 return 0; 1580 } 1581 1582 static void 1583 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1584 { 1585 int pwdb; 1586 1587 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1588 1589 /* Convert antenna signal to percentage. */ 1590 if (rssi <= -100 || rssi >= 20) 1591 pwdb = 0; 1592 else if (rssi >= 0) 1593 pwdb = 100; 1594 else 1595 pwdb = 100 + rssi; 1596 if (rate <= 3) { 1597 /* CCK gain is smaller than OFDM/MCS gain. */ 1598 pwdb += 6; 1599 if (pwdb > 100) 1600 pwdb = 100; 1601 if (pwdb <= 14) 1602 pwdb -= 4; 1603 else if (pwdb <= 26) 1604 pwdb -= 8; 1605 else if (pwdb <= 34) 1606 pwdb -= 6; 1607 else if (pwdb <= 42) 1608 pwdb -= 2; 1609 } 1610 if (sc->avg_pwdb == -1) /* Init. */ 1611 sc->avg_pwdb = pwdb; 1612 else if (sc->avg_pwdb < pwdb) 1613 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1614 else 1615 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1616 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1617 } 1618 1619 static int8_t 1620 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1621 { 1622 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1623 struct r92c_rx_phystat *phy; 1624 struct r92c_rx_cck *cck; 1625 uint8_t rpt; 1626 int8_t rssi; 1627 1628 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1629 1630 if (rate <= 3) { 1631 cck = (struct r92c_rx_cck *)physt; 1632 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1633 rpt = (cck->agc_rpt >> 5) & 0x3; 1634 rssi = (cck->agc_rpt & 0x1f) << 1; 1635 } else { 1636 rpt = (cck->agc_rpt >> 6) & 0x3; 1637 rssi = cck->agc_rpt & 0x3e; 1638 } 1639 rssi = cckoff[rpt] - rssi; 1640 } else { /* OFDM/HT. */ 1641 phy = (struct r92c_rx_phystat *)physt; 1642 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1643 } 1644 return rssi; 1645 } 1646 1647 static void 1648 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1649 struct rtwn_rx_data *rx_data, int desc_idx) 1650 { 1651 struct ieee80211com *ic = &sc->sc_ic; 1652 struct ifnet *ifp = IC2IFP(ic); 1653 struct ieee80211_frame *wh; 1654 struct ieee80211_node *ni; 1655 struct r92c_rx_phystat *phy = NULL; 1656 uint32_t rxdw0, rxdw3; 1657 struct mbuf *m, *m1; 1658 uint8_t rate; 1659 int8_t rssi = 0; 1660 int infosz, pktlen, shift, totlen, error; 1661 1662 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1663 1664 rxdw0 = le32toh(rx_desc->rxdw0); 1665 rxdw3 = le32toh(rx_desc->rxdw3); 1666 1667 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1668 /* 1669 * This should not happen since we setup our Rx filter 1670 * to not receive these frames. 1671 */ 1672 ifp->if_ierrors++; 1673 return; 1674 } 1675 1676 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1677 /* 1678 * XXX: This will drop most control packets. Do we really 1679 * want this in IEEE80211_M_MONITOR mode? 1680 */ 1681 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) { 1682 ic->ic_stats.is_rx_tooshort++; 1683 ifp->if_ierrors++; 1684 return; 1685 } 1686 if (__predict_false(pktlen > MCLBYTES)) { 1687 ifp->if_ierrors++; 1688 return; 1689 } 1690 1691 rate = MS(rxdw3, R92C_RXDW3_RATE); 1692 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1693 if (infosz > sizeof(struct r92c_rx_phystat)) 1694 infosz = sizeof(struct r92c_rx_phystat); 1695 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1696 totlen = pktlen + infosz + shift; 1697 1698 /* Get RSSI from PHY status descriptor if present. */ 1699 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1700 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1701 rssi = rtwn_get_rssi(sc, rate, phy); 1702 /* Update our average RSSI. */ 1703 rtwn_update_avgrssi(sc, rate, rssi); 1704 } 1705 1706 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1707 pktlen, rate, infosz, shift, rssi)); 1708 1709 MGETHDR(m1, M_DONTWAIT, MT_DATA); 1710 if (__predict_false(m1 == NULL)) { 1711 ic->ic_stats.is_rx_nobuf++; 1712 ifp->if_ierrors++; 1713 return; 1714 } 1715 MCLGET(m1, M_DONTWAIT); 1716 if (__predict_false(!(m1->m_flags & M_EXT))) { 1717 m_freem(m1); 1718 ic->ic_stats.is_rx_nobuf++; 1719 ifp->if_ierrors++; 1720 return; 1721 } 1722 1723 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen, 1724 BUS_DMASYNC_POSTREAD); 1725 1726 bus_dmamap_unload(sc->sc_dmat, rx_data->map); 1727 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *), 1728 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 1729 if (error != 0) { 1730 m_freem(m1); 1731 1732 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map, 1733 rx_data->m, BUS_DMA_NOWAIT)) 1734 panic("%s: could not load old RX mbuf", 1735 device_xname(sc->sc_dev)); 1736 1737 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1738 BUS_DMASYNC_PREREAD); 1739 1740 /* Physical address may have changed. */ 1741 rtwn_setup_rx_desc(sc, rx_desc, 1742 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx); 1743 1744 ifp->if_ierrors++; 1745 return; 1746 } 1747 1748 /* Finalize mbuf. */ 1749 m = rx_data->m; 1750 rx_data->m = m1; 1751 m->m_pkthdr.len = m->m_len = totlen; 1752 m_set_rcvif(m, ifp); 1753 1754 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES, 1755 BUS_DMASYNC_PREREAD); 1756 1757 /* Update RX descriptor. */ 1758 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr, 1759 MCLBYTES, desc_idx); 1760 1761 /* Get ieee80211 frame header. */ 1762 if (rxdw0 & R92C_RXDW0_PHYST) 1763 m_adj(m, infosz + shift); 1764 else 1765 m_adj(m, shift); 1766 wh = mtod(m, struct ieee80211_frame *); 1767 1768 if (__predict_false(sc->sc_drvbpf != NULL)) { 1769 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1770 1771 tap->wr_flags = 0; 1772 /* Map HW rate index to 802.11 rate. */ 1773 tap->wr_flags = 2; 1774 if (!(rxdw3 & R92C_RXDW3_HT)) { 1775 switch (rate) { 1776 /* CCK. */ 1777 case 0: tap->wr_rate = 2; break; 1778 case 1: tap->wr_rate = 4; break; 1779 case 2: tap->wr_rate = 11; break; 1780 case 3: tap->wr_rate = 22; break; 1781 /* OFDM. */ 1782 case 4: tap->wr_rate = 12; break; 1783 case 5: tap->wr_rate = 18; break; 1784 case 6: tap->wr_rate = 24; break; 1785 case 7: tap->wr_rate = 36; break; 1786 case 8: tap->wr_rate = 48; break; 1787 case 9: tap->wr_rate = 72; break; 1788 case 10: tap->wr_rate = 96; break; 1789 case 11: tap->wr_rate = 108; break; 1790 } 1791 } else if (rate >= 12) { /* MCS0~15. */ 1792 /* Bit 7 set means HT MCS instead of rate. */ 1793 tap->wr_rate = 0x80 | (rate - 12); 1794 } 1795 tap->wr_dbm_antsignal = rssi; 1796 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1797 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1798 1799 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); 1800 } 1801 1802 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 1803 1804 /* push the frame up to the 802.11 stack */ 1805 ieee80211_input(ic, m, ni, rssi, 0); 1806 1807 /* Node is no longer needed. */ 1808 ieee80211_free_node(ni); 1809 } 1810 1811 static int 1812 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1813 { 1814 struct ieee80211com *ic = &sc->sc_ic; 1815 struct ieee80211_frame *wh; 1816 struct ieee80211_key *k = NULL; 1817 struct rtwn_tx_ring *tx_ring; 1818 struct rtwn_tx_data *data; 1819 struct r92c_tx_desc *txd; 1820 uint16_t qos, seq; 1821 uint8_t raid, type, tid, qid; 1822 int hasqos, error; 1823 1824 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 1825 1826 wh = mtod(m, struct ieee80211_frame *); 1827 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1828 1829 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1830 k = ieee80211_crypto_encap(ic, ni, m); 1831 if (k == NULL) 1832 return ENOBUFS; 1833 1834 wh = mtod(m, struct ieee80211_frame *); 1835 } 1836 1837 if ((hasqos = ieee80211_has_qos(wh))) { 1838 /* data frames in 11n mode */ 1839 qos = ieee80211_get_qos(wh); 1840 tid = qos & IEEE80211_QOS_TID; 1841 qid = TID_TO_WME_AC(tid); 1842 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1843 /* Use AC_VO for management frames. */ 1844 tid = 0; /* compiler happy */ 1845 qid = RTWN_VO_QUEUE; 1846 } else { 1847 /* non-qos data frames */ 1848 tid = R92C_TXDW1_QSEL_BE; 1849 qid = RTWN_BE_QUEUE; 1850 } 1851 1852 /* Grab a Tx buffer from the ring. */ 1853 tx_ring = &sc->tx_ring[qid]; 1854 data = &tx_ring->tx_data[tx_ring->cur]; 1855 if (data->m != NULL) { 1856 m_freem(m); 1857 return ENOBUFS; 1858 } 1859 1860 /* Fill Tx descriptor. */ 1861 txd = &tx_ring->desc[tx_ring->cur]; 1862 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1863 m_freem(m); 1864 return ENOBUFS; 1865 } 1866 1867 txd->txdw0 = htole32( 1868 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1869 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1870 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1871 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1872 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1873 1874 txd->txdw1 = 0; 1875 txd->txdw4 = 0; 1876 txd->txdw5 = 0; 1877 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1878 type == IEEE80211_FC0_TYPE_DATA) { 1879 if (ic->ic_curmode == IEEE80211_MODE_11B) 1880 raid = R92C_RAID_11B; 1881 else 1882 raid = R92C_RAID_11BG; 1883 1884 txd->txdw1 |= htole32( 1885 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1886 SM(R92C_TXDW1_QSEL, tid) | 1887 SM(R92C_TXDW1_RAID, raid) | 1888 R92C_TXDW1_AGGBK); 1889 1890 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1891 /* for 11g */ 1892 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1893 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1894 R92C_TXDW4_HWRTSEN); 1895 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1896 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1897 R92C_TXDW4_HWRTSEN); 1898 } 1899 } 1900 /* Send RTS at OFDM24. */ 1901 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1902 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1903 /* Send data at OFDM54. */ 1904 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1905 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1906 } else if (type == IEEE80211_FC0_TYPE_MGT) { 1907 txd->txdw1 |= htole32( 1908 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1909 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1910 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1911 1912 /* Force CCK1. */ 1913 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1914 /* Use 1Mbps */ 1915 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1916 } else { 1917 txd->txdw1 |= htole32( 1918 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) | 1919 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1920 1921 /* Force CCK1. */ 1922 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1923 /* Use 1Mbps */ 1924 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1925 } 1926 1927 /* Set sequence number (already little endian). */ 1928 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT; 1929 txd->txdseq = htole16(seq); 1930 1931 if (!hasqos) { 1932 /* Use HW sequence numbering for non-QoS frames. */ 1933 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1934 txd->txdseq |= htole16(0x8000); /* WTF? */ 1935 } else 1936 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1937 1938 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1939 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1940 if (error && error != EFBIG) { 1941 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n", 1942 error); 1943 m_freem(m); 1944 return error; 1945 } 1946 if (error != 0) { 1947 /* Too many DMA segments, linearize mbuf. */ 1948 if ((m = m_defrag(m, M_DONTWAIT)) == NULL) { 1949 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n"); 1950 return ENOBUFS; 1951 } 1952 1953 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 1954 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 1955 if (error != 0) { 1956 aprint_error_dev(sc->sc_dev, 1957 "can't map mbuf (error %d)\n", error); 1958 m_freem(m); 1959 return error; 1960 } 1961 } 1962 1963 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr); 1964 txd->txbufsize = htole16(m->m_pkthdr.len); 1965 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1966 BUS_SPACE_BARRIER_WRITE); 1967 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1968 1969 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0, 1970 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE); 1971 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len, 1972 BUS_DMASYNC_PREWRITE); 1973 1974 data->m = m; 1975 data->ni = ni; 1976 1977 if (__predict_false(sc->sc_drvbpf != NULL)) { 1978 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1979 1980 tap->wt_flags = 0; 1981 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1982 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1983 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1984 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1985 1986 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m); 1987 } 1988 1989 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1990 tx_ring->queued++; 1991 1992 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1993 sc->qfullmsk |= (1 << qid); 1994 1995 /* Kick TX. */ 1996 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1997 1998 return 0; 1999 } 2000 2001 static void 2002 rtwn_tx_done(struct rtwn_softc *sc, int qid) 2003 { 2004 struct ieee80211com *ic = &sc->sc_ic; 2005 struct ifnet *ifp = IC2IFP(ic); 2006 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 2007 struct rtwn_tx_data *tx_data; 2008 struct r92c_tx_desc *tx_desc; 2009 int i; 2010 2011 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__, 2012 qid)); 2013 2014 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 2015 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT, 2016 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2017 2018 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 2019 tx_data = &tx_ring->tx_data[i]; 2020 if (tx_data->m == NULL) 2021 continue; 2022 2023 tx_desc = &tx_ring->desc[i]; 2024 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 2025 continue; 2026 2027 bus_dmamap_unload(sc->sc_dmat, tx_data->map); 2028 m_freem(tx_data->m); 2029 tx_data->m = NULL; 2030 ieee80211_free_node(tx_data->ni); 2031 tx_data->ni = NULL; 2032 2033 ifp->if_opackets++; 2034 sc->sc_tx_timer = 0; 2035 tx_ring->queued--; 2036 } 2037 2038 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 2039 sc->qfullmsk &= ~(1 << qid); 2040 } 2041 2042 static void 2043 rtwn_start(struct ifnet *ifp) 2044 { 2045 struct rtwn_softc *sc = ifp->if_softc; 2046 struct ieee80211com *ic = &sc->sc_ic; 2047 struct ether_header *eh; 2048 struct ieee80211_node *ni; 2049 struct mbuf *m; 2050 2051 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 2052 return; 2053 2054 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2055 2056 for (;;) { 2057 if (sc->qfullmsk != 0) { 2058 ifp->if_flags |= IFF_OACTIVE; 2059 break; 2060 } 2061 /* Send pending management frames first. */ 2062 IF_DEQUEUE(&ic->ic_mgtq, m); 2063 if (m != NULL) { 2064 ni = M_GETCTX(m, struct ieee80211_node *); 2065 M_CLEARCTX(m); 2066 goto sendit; 2067 } 2068 if (ic->ic_state != IEEE80211_S_RUN) 2069 break; 2070 2071 /* Encapsulate and send data frames. */ 2072 IFQ_DEQUEUE(&ifp->if_snd, m); 2073 if (m == NULL) 2074 break; 2075 2076 if (m->m_len < (int)sizeof(*eh) && 2077 (m = m_pullup(m, sizeof(*eh))) == NULL) { 2078 ifp->if_oerrors++; 2079 continue; 2080 } 2081 eh = mtod(m, struct ether_header *); 2082 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 2083 if (ni == NULL) { 2084 m_freem(m); 2085 ifp->if_oerrors++; 2086 continue; 2087 } 2088 2089 bpf_mtap(ifp, m); 2090 2091 if ((m = ieee80211_encap(ic, m, ni)) == NULL) { 2092 ieee80211_free_node(ni); 2093 ifp->if_oerrors++; 2094 continue; 2095 } 2096 sendit: 2097 bpf_mtap3(ic->ic_rawbpf, m); 2098 2099 if (rtwn_tx(sc, m, ni) != 0) { 2100 ieee80211_free_node(ni); 2101 ifp->if_oerrors++; 2102 continue; 2103 } 2104 2105 sc->sc_tx_timer = 5; 2106 ifp->if_timer = 1; 2107 } 2108 2109 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__)); 2110 } 2111 2112 static void 2113 rtwn_watchdog(struct ifnet *ifp) 2114 { 2115 struct rtwn_softc *sc = ifp->if_softc; 2116 struct ieee80211com *ic = &sc->sc_ic; 2117 2118 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2119 2120 ifp->if_timer = 0; 2121 2122 if (sc->sc_tx_timer > 0) { 2123 if (--sc->sc_tx_timer == 0) { 2124 aprint_error_dev(sc->sc_dev, "device timeout\n"); 2125 softint_schedule(sc->init_task); 2126 ifp->if_oerrors++; 2127 return; 2128 } 2129 ifp->if_timer = 1; 2130 } 2131 ieee80211_watchdog(ic); 2132 } 2133 2134 static int 2135 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2136 { 2137 struct rtwn_softc *sc = ifp->if_softc; 2138 struct ieee80211com *ic = &sc->sc_ic; 2139 int s, error = 0; 2140 2141 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev), 2142 __func__, cmd, data)); 2143 2144 s = splnet(); 2145 2146 switch (cmd) { 2147 case SIOCSIFFLAGS: 2148 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 2149 break; 2150 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 2151 case IFF_UP | IFF_RUNNING: 2152 break; 2153 case IFF_UP: 2154 error = rtwn_init(ifp); 2155 if (error != 0) 2156 ifp->if_flags &= ~IFF_UP; 2157 break; 2158 case IFF_RUNNING: 2159 rtwn_stop(ifp, 1); 2160 break; 2161 case 0: 2162 break; 2163 } 2164 break; 2165 2166 case SIOCADDMULTI: 2167 case SIOCDELMULTI: 2168 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2169 /* setup multicast filter, etc */ 2170 error = 0; 2171 } 2172 break; 2173 2174 case SIOCS80211CHANNEL: 2175 error = ieee80211_ioctl(ic, cmd, data); 2176 if (error == ENETRESET && 2177 ic->ic_opmode == IEEE80211_M_MONITOR) { 2178 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2179 (IFF_UP | IFF_RUNNING)) { 2180 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2181 } 2182 error = 0; 2183 } 2184 break; 2185 2186 default: 2187 error = ieee80211_ioctl(ic, cmd, data); 2188 break; 2189 } 2190 2191 if (error == ENETRESET) { 2192 error = 0; 2193 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2194 (IFF_UP | IFF_RUNNING)) { 2195 rtwn_stop(ifp, 0); 2196 error = rtwn_init(ifp); 2197 } 2198 } 2199 2200 splx(s); 2201 2202 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__, 2203 error)); 2204 2205 return error; 2206 } 2207 2208 static int 2209 rtwn_power_on(struct rtwn_softc *sc) 2210 { 2211 uint32_t reg; 2212 int ntries; 2213 2214 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2215 2216 /* Wait for autoload done bit. */ 2217 for (ntries = 0; ntries < 1000; ntries++) { 2218 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2219 break; 2220 DELAY(5); 2221 } 2222 if (ntries == 1000) { 2223 aprint_error_dev(sc->sc_dev, 2224 "timeout waiting for chip autoload\n"); 2225 return ETIMEDOUT; 2226 } 2227 2228 /* Unlock ISO/CLK/Power control register. */ 2229 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 2230 2231 /* TODO: check if we need this for 8188CE */ 2232 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2233 /* bt coex */ 2234 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 2235 reg |= (R92C_APS_FSMCO_SOP_ABG | 2236 R92C_APS_FSMCO_SOP_AMB | 2237 R92C_APS_FSMCO_XOP_BTCK); 2238 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 2239 } 2240 2241 /* Move SPS into PWM mode. */ 2242 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2243 DELAY(100); 2244 2245 /* Set low byte to 0x0f, leave others unchanged. */ 2246 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 2247 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 2248 2249 /* TODO: check if we need this for 8188CE */ 2250 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2251 /* bt coex */ 2252 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 2253 reg &= ~0x00024800; /* XXX magic from linux */ 2254 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 2255 } 2256 2257 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2258 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 2259 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 2260 DELAY(200); 2261 2262 /* TODO: linux does additional btcoex stuff here */ 2263 2264 /* Auto enable WLAN. */ 2265 rtwn_write_2(sc, R92C_APS_FSMCO, 2266 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2267 for (ntries = 0; ntries < 1000; ntries++) { 2268 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 2269 R92C_APS_FSMCO_APFM_ONMAC)) 2270 break; 2271 DELAY(5); 2272 } 2273 if (ntries == 1000) { 2274 aprint_error_dev(sc->sc_dev, 2275 "timeout waiting for MAC auto ON\n"); 2276 return ETIMEDOUT; 2277 } 2278 2279 /* Enable radio, GPIO and LED functions. */ 2280 rtwn_write_2(sc, R92C_APS_FSMCO, 2281 R92C_APS_FSMCO_AFSM_PCIE | 2282 R92C_APS_FSMCO_PDN_EN | 2283 R92C_APS_FSMCO_PFM_ALDN); 2284 2285 /* Release RF digital isolation. */ 2286 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2287 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2288 2289 if (sc->chip & RTWN_CHIP_92C) 2290 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 2291 else 2292 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 2293 2294 rtwn_write_4(sc, R92C_INT_MIG, 0); 2295 2296 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 2297 /* bt coex */ 2298 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 2299 reg &= 0xfd; /* XXX magic from linux */ 2300 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 2301 } 2302 2303 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2304 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2305 2306 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2307 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2308 aprint_error_dev(sc->sc_dev, 2309 "radio is disabled by hardware switch\n"); 2310 return EPERM; /* :-) */ 2311 } 2312 2313 /* Initialize MAC. */ 2314 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2315 rtwn_write_1(sc, R92C_APSD_CTRL, 2316 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2317 for (ntries = 0; ntries < 200; ntries++) { 2318 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2319 R92C_APSD_CTRL_OFF_STATUS)) 2320 break; 2321 DELAY(500); 2322 } 2323 if (ntries == 200) { 2324 aprint_error_dev(sc->sc_dev, 2325 "timeout waiting for MAC initialization\n"); 2326 return ETIMEDOUT; 2327 } 2328 2329 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2330 reg = rtwn_read_2(sc, R92C_CR); 2331 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2332 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2333 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2334 R92C_CR_ENSEC; 2335 rtwn_write_2(sc, R92C_CR, reg); 2336 2337 rtwn_write_1(sc, 0xfe10, 0x19); 2338 2339 return 0; 2340 } 2341 2342 static int 2343 rtwn_llt_init(struct rtwn_softc *sc) 2344 { 2345 int i, error; 2346 2347 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2348 2349 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2350 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2351 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2352 return error; 2353 } 2354 /* NB: 0xff indicates end-of-list. */ 2355 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2356 return error; 2357 /* 2358 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2359 * as ring buffer. 2360 */ 2361 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2362 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2363 return error; 2364 } 2365 /* Make the last page point to the beginning of the ring buffer. */ 2366 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2367 return error; 2368 } 2369 2370 static void 2371 rtwn_fw_reset(struct rtwn_softc *sc) 2372 { 2373 uint16_t reg; 2374 int ntries; 2375 2376 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2377 2378 /* Tell 8051 to reset itself. */ 2379 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2380 2381 /* Wait until 8051 resets by itself. */ 2382 for (ntries = 0; ntries < 100; ntries++) { 2383 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2384 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2385 goto sleep; 2386 DELAY(50); 2387 } 2388 /* Force 8051 reset. */ 2389 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2390 sleep: 2391 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2392 #if 0 2393 /* 2394 * We must sleep for one second to let the firmware settle. 2395 * Accessing registers too early will hang the whole system. 2396 */ 2397 tsleep(®, 0, "rtwnrst", hz); 2398 #else 2399 DELAY(1000 * 1000); 2400 #endif 2401 } 2402 2403 static int 2404 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len) 2405 { 2406 uint32_t reg; 2407 int off, mlen, error = 0, i; 2408 2409 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2410 2411 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2412 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2413 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2414 2415 DELAY(5); 2416 2417 off = R92C_FW_START_ADDR; 2418 while (len > 0) { 2419 if (len > 196) 2420 mlen = 196; 2421 else if (len > 4) 2422 mlen = 4; 2423 else 2424 mlen = 1; 2425 for (i = 0; i < mlen; i++) 2426 rtwn_write_1(sc, off++, buf[i]); 2427 buf += mlen; 2428 len -= mlen; 2429 } 2430 2431 return error; 2432 } 2433 2434 static int 2435 rtwn_load_firmware(struct rtwn_softc *sc) 2436 { 2437 firmware_handle_t fwh; 2438 const struct r92c_fw_hdr *hdr; 2439 const char *name; 2440 u_char *fw, *ptr; 2441 size_t len; 2442 uint32_t reg; 2443 int mlen, ntries, page, error; 2444 2445 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2446 2447 /* Read firmware image from the filesystem. */ 2448 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2449 RTWN_CHIP_UMC_A_CUT) 2450 name = "rtl8192cfwU.bin"; 2451 else if (sc->chip & RTWN_CHIP_UMC_B_CUT) 2452 name = "rtl8192cfwU_B.bin"; 2453 else 2454 name = "rtl8192cfw.bin"; 2455 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name)); 2456 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) { 2457 aprint_error_dev(sc->sc_dev, 2458 "could not read firmware %s (error %d)\n", name, error); 2459 return error; 2460 } 2461 const size_t fwlen = len = firmware_get_size(fwh); 2462 fw = firmware_malloc(len); 2463 if (fw == NULL) { 2464 aprint_error_dev(sc->sc_dev, 2465 "failed to allocate firmware memory (size=%zu)\n", len); 2466 firmware_close(fwh); 2467 return ENOMEM; 2468 } 2469 error = firmware_read(fwh, 0, fw, len); 2470 firmware_close(fwh); 2471 if (error != 0) { 2472 aprint_error_dev(sc->sc_dev, 2473 "failed to read firmware (error %d)\n", error); 2474 firmware_free(fw, fwlen); 2475 return error; 2476 } 2477 2478 if (len < sizeof(*hdr)) { 2479 aprint_error_dev(sc->sc_dev, "firmware too short\n"); 2480 error = EINVAL; 2481 goto fail; 2482 } 2483 ptr = fw; 2484 hdr = (const struct r92c_fw_hdr *)ptr; 2485 /* Check if there is a valid FW header and skip it. */ 2486 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2487 (le16toh(hdr->signature) >> 4) == 0x92c) { 2488 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2489 le16toh(hdr->version), le16toh(hdr->subversion), 2490 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2491 ptr += sizeof(*hdr); 2492 len -= sizeof(*hdr); 2493 } 2494 2495 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2496 rtwn_fw_reset(sc); 2497 2498 /* Enable FW download. */ 2499 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2500 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2501 R92C_SYS_FUNC_EN_CPUEN); 2502 rtwn_write_1(sc, R92C_MCUFWDL, 2503 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2504 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2505 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2506 2507 /* Reset the FWDL checksum. */ 2508 rtwn_write_1(sc, R92C_MCUFWDL, 2509 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2510 2511 /* download firmware */ 2512 for (page = 0; len > 0; page++) { 2513 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2514 error = rtwn_fw_loadpage(sc, page, ptr, mlen); 2515 if (error != 0) { 2516 aprint_error_dev(sc->sc_dev, 2517 "could not load firmware page %d\n", page); 2518 goto fail; 2519 } 2520 ptr += mlen; 2521 len -= mlen; 2522 } 2523 2524 /* Disable FW download. */ 2525 rtwn_write_1(sc, R92C_MCUFWDL, 2526 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2527 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2528 2529 /* Wait for checksum report. */ 2530 for (ntries = 0; ntries < 1000; ntries++) { 2531 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2532 break; 2533 DELAY(5); 2534 } 2535 if (ntries == 1000) { 2536 aprint_error_dev(sc->sc_dev, 2537 "timeout waiting for checksum report\n"); 2538 error = ETIMEDOUT; 2539 goto fail; 2540 } 2541 2542 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2543 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2544 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2545 2546 /* Wait for firmware readiness. */ 2547 for (ntries = 0; ntries < 1000; ntries++) { 2548 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2549 break; 2550 DELAY(5); 2551 } 2552 if (ntries == 1000) { 2553 aprint_error_dev(sc->sc_dev, 2554 "timeout waiting for firmware readiness\n"); 2555 error = ETIMEDOUT; 2556 goto fail; 2557 } 2558 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED); 2559 2560 fail: 2561 firmware_free(fw, fwlen); 2562 return error; 2563 } 2564 2565 static int 2566 rtwn_dma_init(struct rtwn_softc *sc) 2567 { 2568 uint32_t reg; 2569 int error; 2570 2571 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2572 2573 /* Initialize LLT table. */ 2574 error = rtwn_llt_init(sc); 2575 if (error != 0) 2576 return error; 2577 2578 /* Set number of pages for normal priority queue. */ 2579 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2580 rtwn_write_4(sc, R92C_RQPN, 2581 /* Set number of pages for public queue. */ 2582 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2583 /* Set number of pages for high priority queue. */ 2584 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2585 /* Set number of pages for low priority queue. */ 2586 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2587 /* Load values. */ 2588 R92C_RQPN_LD); 2589 2590 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2591 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2592 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2593 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2594 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2595 2596 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2597 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2598 reg |= 0xF771; 2599 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2600 2601 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2602 2603 /* Configure Tx DMA. */ 2604 rtwn_write_4(sc, R92C_BKQ_DESA, 2605 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr); 2606 rtwn_write_4(sc, R92C_BEQ_DESA, 2607 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr); 2608 rtwn_write_4(sc, R92C_VIQ_DESA, 2609 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr); 2610 rtwn_write_4(sc, R92C_VOQ_DESA, 2611 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr); 2612 rtwn_write_4(sc, R92C_BCNQ_DESA, 2613 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr); 2614 rtwn_write_4(sc, R92C_MGQ_DESA, 2615 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr); 2616 rtwn_write_4(sc, R92C_HQ_DESA, 2617 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr); 2618 2619 /* Configure Rx DMA. */ 2620 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr); 2621 2622 /* Set Tx/Rx transfer page boundary. */ 2623 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2624 2625 /* Set Tx/Rx transfer page size. */ 2626 rtwn_write_1(sc, R92C_PBP, 2627 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2628 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2629 return 0; 2630 } 2631 2632 static void 2633 rtwn_mac_init(struct rtwn_softc *sc) 2634 { 2635 int i; 2636 2637 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2638 2639 /* Write MAC initialization values. */ 2640 for (i = 0; i < __arraycount(rtl8192ce_mac); i++) 2641 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2642 } 2643 2644 static void 2645 rtwn_bb_init(struct rtwn_softc *sc) 2646 { 2647 const struct rtwn_bb_prog *prog; 2648 uint32_t reg; 2649 int i; 2650 2651 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2652 2653 /* Enable BB and RF. */ 2654 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2655 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2656 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2657 R92C_SYS_FUNC_EN_DIO_RF); 2658 2659 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2660 2661 rtwn_write_1(sc, R92C_RF_CTRL, 2662 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2663 2664 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2665 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2666 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2667 R92C_SYS_FUNC_EN_BBRSTB); 2668 2669 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2670 2671 rtwn_write_4(sc, R92C_LEDCFG0, 2672 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2673 2674 /* Select BB programming. */ 2675 prog = (sc->chip & RTWN_CHIP_92C) ? 2676 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2677 2678 /* Write BB initialization values. */ 2679 for (i = 0; i < prog->count; i++) { 2680 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2681 DELAY(1); 2682 } 2683 2684 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2685 /* 8192C 1T only configuration. */ 2686 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2687 reg = (reg & ~0x00000003) | 0x2; 2688 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2689 2690 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2691 reg = (reg & ~0x00300033) | 0x00200022; 2692 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2693 2694 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2695 reg = (reg & ~0xff000000) | 0x45 << 24; 2696 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2697 2698 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2699 reg = (reg & ~0x000000ff) | 0x23; 2700 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2701 2702 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2703 reg = (reg & ~0x00000030) | 1 << 4; 2704 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2705 2706 reg = rtwn_bb_read(sc, 0xe74); 2707 reg = (reg & ~0x0c000000) | 2 << 26; 2708 rtwn_bb_write(sc, 0xe74, reg); 2709 reg = rtwn_bb_read(sc, 0xe78); 2710 reg = (reg & ~0x0c000000) | 2 << 26; 2711 rtwn_bb_write(sc, 0xe78, reg); 2712 reg = rtwn_bb_read(sc, 0xe7c); 2713 reg = (reg & ~0x0c000000) | 2 << 26; 2714 rtwn_bb_write(sc, 0xe7c, reg); 2715 reg = rtwn_bb_read(sc, 0xe80); 2716 reg = (reg & ~0x0c000000) | 2 << 26; 2717 rtwn_bb_write(sc, 0xe80, reg); 2718 reg = rtwn_bb_read(sc, 0xe88); 2719 reg = (reg & ~0x0c000000) | 2 << 26; 2720 rtwn_bb_write(sc, 0xe88, reg); 2721 } 2722 2723 /* Write AGC values. */ 2724 for (i = 0; i < prog->agccount; i++) { 2725 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2726 prog->agcvals[i]); 2727 DELAY(1); 2728 } 2729 2730 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2731 R92C_HSSI_PARAM2_CCK_HIPWR) 2732 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2733 } 2734 2735 static void 2736 rtwn_rf_init(struct rtwn_softc *sc) 2737 { 2738 const struct rtwn_rf_prog *prog; 2739 uint32_t reg, type; 2740 int i, j, idx, off; 2741 2742 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2743 2744 /* Select RF programming based on board type. */ 2745 if (!(sc->chip & RTWN_CHIP_92C)) { 2746 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2747 prog = rtl8188ce_rf_prog; 2748 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2749 prog = rtl8188ru_rf_prog; 2750 else 2751 prog = rtl8188cu_rf_prog; 2752 } else 2753 prog = rtl8192ce_rf_prog; 2754 2755 for (i = 0; i < sc->nrxchains; i++) { 2756 /* Save RF_ENV control type. */ 2757 idx = i / 2; 2758 off = (i % 2) * 16; 2759 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2760 type = (reg >> off) & 0x10; 2761 2762 /* Set RF_ENV enable. */ 2763 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2764 reg |= 0x100000; 2765 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2766 DELAY(1); 2767 /* Set RF_ENV output high. */ 2768 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2769 reg |= 0x10; 2770 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2771 DELAY(1); 2772 /* Set address and data lengths of RF registers. */ 2773 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2774 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2775 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2776 DELAY(1); 2777 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2778 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2779 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2780 DELAY(1); 2781 2782 /* Write RF initialization values for this chain. */ 2783 for (j = 0; j < prog[i].count; j++) { 2784 if (prog[i].regs[j] >= 0xf9 && 2785 prog[i].regs[j] <= 0xfe) { 2786 /* 2787 * These are fake RF registers offsets that 2788 * indicate a delay is required. 2789 */ 2790 DELAY(50); 2791 continue; 2792 } 2793 rtwn_rf_write(sc, i, prog[i].regs[j], 2794 prog[i].vals[j]); 2795 DELAY(1); 2796 } 2797 2798 /* Restore RF_ENV control type. */ 2799 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2800 reg &= ~(0x10 << off) | (type << off); 2801 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2802 2803 /* Cache RF register CHNLBW. */ 2804 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2805 } 2806 2807 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2808 RTWN_CHIP_UMC_A_CUT) { 2809 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2810 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2811 } 2812 } 2813 2814 static void 2815 rtwn_cam_init(struct rtwn_softc *sc) 2816 { 2817 2818 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2819 2820 /* Invalidate all CAM entries. */ 2821 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2822 } 2823 2824 static void 2825 rtwn_pa_bias_init(struct rtwn_softc *sc) 2826 { 2827 uint8_t reg; 2828 int i; 2829 2830 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2831 2832 for (i = 0; i < sc->nrxchains; i++) { 2833 if (sc->pa_setting & (1 << i)) 2834 continue; 2835 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2836 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2837 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2838 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2839 } 2840 if (!(sc->pa_setting & 0x10)) { 2841 reg = rtwn_read_1(sc, 0x16); 2842 reg = (reg & ~0xf0) | 0x90; 2843 rtwn_write_1(sc, 0x16, reg); 2844 } 2845 } 2846 2847 static void 2848 rtwn_rxfilter_init(struct rtwn_softc *sc) 2849 { 2850 2851 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2852 2853 /* Initialize Rx filter. */ 2854 /* TODO: use better filter for monitor mode. */ 2855 rtwn_write_4(sc, R92C_RCR, 2856 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2857 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2858 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2859 /* Accept all multicast frames. */ 2860 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2861 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2862 /* Accept all management frames. */ 2863 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2864 /* Reject all control frames. */ 2865 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2866 /* Accept all data frames. */ 2867 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2868 } 2869 2870 static void 2871 rtwn_edca_init(struct rtwn_softc *sc) 2872 { 2873 2874 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2875 2876 /* set spec SIFS (used in NAV) */ 2877 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2878 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2879 2880 /* set SIFS CCK/OFDM */ 2881 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2882 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2883 2884 /* TXOP */ 2885 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2886 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2887 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2888 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2889 } 2890 2891 static void 2892 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2893 uint16_t power[RTWN_RIDX_COUNT]) 2894 { 2895 uint32_t reg; 2896 2897 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2898 2899 /* Write per-CCK rate Tx power. */ 2900 if (chain == 0) { 2901 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2902 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2903 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2904 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2905 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2906 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2907 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2908 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2909 } else { 2910 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2911 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2912 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2913 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2914 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2915 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2916 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2917 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2918 } 2919 /* Write per-OFDM rate Tx power. */ 2920 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2921 SM(R92C_TXAGC_RATE06, power[ 4]) | 2922 SM(R92C_TXAGC_RATE09, power[ 5]) | 2923 SM(R92C_TXAGC_RATE12, power[ 6]) | 2924 SM(R92C_TXAGC_RATE18, power[ 7])); 2925 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2926 SM(R92C_TXAGC_RATE24, power[ 8]) | 2927 SM(R92C_TXAGC_RATE36, power[ 9]) | 2928 SM(R92C_TXAGC_RATE48, power[10]) | 2929 SM(R92C_TXAGC_RATE54, power[11])); 2930 /* Write per-MCS Tx power. */ 2931 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2932 SM(R92C_TXAGC_MCS00, power[12]) | 2933 SM(R92C_TXAGC_MCS01, power[13]) | 2934 SM(R92C_TXAGC_MCS02, power[14]) | 2935 SM(R92C_TXAGC_MCS03, power[15])); 2936 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2937 SM(R92C_TXAGC_MCS04, power[16]) | 2938 SM(R92C_TXAGC_MCS05, power[17]) | 2939 SM(R92C_TXAGC_MCS06, power[18]) | 2940 SM(R92C_TXAGC_MCS07, power[19])); 2941 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2942 SM(R92C_TXAGC_MCS08, power[20]) | 2943 SM(R92C_TXAGC_MCS09, power[21]) | 2944 SM(R92C_TXAGC_MCS10, power[22]) | 2945 SM(R92C_TXAGC_MCS11, power[23])); 2946 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2947 SM(R92C_TXAGC_MCS12, power[24]) | 2948 SM(R92C_TXAGC_MCS13, power[25]) | 2949 SM(R92C_TXAGC_MCS14, power[26]) | 2950 SM(R92C_TXAGC_MCS15, power[27])); 2951 } 2952 2953 static void 2954 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2955 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2956 uint16_t power[RTWN_RIDX_COUNT]) 2957 { 2958 struct ieee80211com *ic = &sc->sc_ic; 2959 struct r92c_rom *rom = &sc->rom; 2960 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr; 2961 const struct rtwn_txpwr *base; 2962 int ridx, chan, group; 2963 2964 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 2965 2966 /* Determine channel group. */ 2967 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2968 if (chan <= 3) 2969 group = 0; 2970 else if (chan <= 9) 2971 group = 1; 2972 else 2973 group = 2; 2974 2975 /* Get original Tx power based on board type and RF chain. */ 2976 if (!(sc->chip & RTWN_CHIP_92C)) { 2977 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2978 base = &rtl8188ru_txagc[chain]; 2979 else 2980 base = &rtl8192cu_txagc[chain]; 2981 } else 2982 base = &rtl8192cu_txagc[chain]; 2983 2984 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2985 if (sc->regulatory == 0) { 2986 for (ridx = 0; ridx <= 3; ridx++) 2987 power[ridx] = base->pwr[0][ridx]; 2988 } 2989 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 2990 if (sc->regulatory == 3) { 2991 power[ridx] = base->pwr[0][ridx]; 2992 /* Apply vendor limits. */ 2993 if (extc != NULL) 2994 maxpwr = rom->ht40_max_pwr[group]; 2995 else 2996 maxpwr = rom->ht20_max_pwr[group]; 2997 maxpwr = (maxpwr >> (chain * 4)) & 0xf; 2998 if (power[ridx] > maxpwr) 2999 power[ridx] = maxpwr; 3000 } else if (sc->regulatory == 1) { 3001 if (extc == NULL) 3002 power[ridx] = base->pwr[group][ridx]; 3003 } else if (sc->regulatory != 2) 3004 power[ridx] = base->pwr[0][ridx]; 3005 } 3006 3007 /* Compute per-CCK rate Tx power. */ 3008 cckpow = rom->cck_tx_pwr[chain][group]; 3009 for (ridx = 0; ridx <= 3; ridx++) { 3010 power[ridx] += cckpow; 3011 if (power[ridx] > R92C_MAX_TX_PWR) 3012 power[ridx] = R92C_MAX_TX_PWR; 3013 } 3014 3015 htpow = rom->ht40_1s_tx_pwr[chain][group]; 3016 if (sc->ntxchains > 1) { 3017 /* Apply reduction for 2 spatial streams. */ 3018 diff = rom->ht40_2s_tx_pwr_diff[group]; 3019 diff = (diff >> (chain * 4)) & 0xf; 3020 htpow = (htpow > diff) ? htpow - diff : 0; 3021 } 3022 3023 /* Compute per-OFDM rate Tx power. */ 3024 diff = rom->ofdm_tx_pwr_diff[group]; 3025 diff = (diff >> (chain * 4)) & 0xf; 3026 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3027 for (ridx = 4; ridx <= 11; ridx++) { 3028 power[ridx] += ofdmpow; 3029 if (power[ridx] > R92C_MAX_TX_PWR) 3030 power[ridx] = R92C_MAX_TX_PWR; 3031 } 3032 3033 /* Compute per-MCS Tx power. */ 3034 if (extc == NULL) { 3035 diff = rom->ht20_tx_pwr_diff[group]; 3036 diff = (diff >> (chain * 4)) & 0xf; 3037 htpow += diff; /* HT40->HT20 correction. */ 3038 } 3039 for (ridx = 12; ridx <= 27; ridx++) { 3040 power[ridx] += htpow; 3041 if (power[ridx] > R92C_MAX_TX_PWR) 3042 power[ridx] = R92C_MAX_TX_PWR; 3043 } 3044 #ifdef RTWN_DEBUG 3045 if (rtwn_debug >= 4) { 3046 /* Dump per-rate Tx power values. */ 3047 printf("Tx power for chain %d:\n", chain); 3048 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 3049 printf("Rate %d = %u\n", ridx, power[ridx]); 3050 } 3051 #endif 3052 } 3053 3054 static void 3055 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 3056 struct ieee80211_channel *extc) 3057 { 3058 uint16_t power[RTWN_RIDX_COUNT]; 3059 int i; 3060 3061 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3062 3063 for (i = 0; i < sc->ntxchains; i++) { 3064 /* Compute per-rate Tx power values. */ 3065 rtwn_get_txpower(sc, i, c, extc, power); 3066 /* Write per-rate Tx power values to hardware. */ 3067 rtwn_write_txpower(sc, i, power); 3068 } 3069 } 3070 3071 static void 3072 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 3073 struct ieee80211_channel *extc) 3074 { 3075 struct ieee80211com *ic = &sc->sc_ic; 3076 u_int chan; 3077 int i; 3078 3079 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3080 3081 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3082 3083 /* Set Tx power for this new channel. */ 3084 rtwn_set_txpower(sc, c, extc); 3085 3086 for (i = 0; i < sc->nrxchains; i++) { 3087 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3088 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3089 } 3090 #ifndef IEEE80211_NO_HT 3091 if (extc != NULL) { 3092 uint32_t reg; 3093 3094 /* Is secondary channel below or above primary? */ 3095 int prichlo = c->ic_freq < extc->ic_freq; 3096 3097 rtwn_write_1(sc, R92C_BWOPMODE, 3098 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3099 3100 reg = rtwn_read_1(sc, R92C_RRSR + 2); 3101 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3102 rtwn_write_1(sc, R92C_RRSR + 2, reg); 3103 3104 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3105 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3106 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3107 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3108 3109 /* Set CCK side band. */ 3110 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3111 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3112 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3113 3114 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 3115 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3116 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3117 3118 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3119 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3120 ~R92C_FPGA0_ANAPARAM2_CBW20); 3121 3122 reg = rtwn_bb_read(sc, 0x818); 3123 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3124 rtwn_bb_write(sc, 0x818, reg); 3125 3126 /* Select 40MHz bandwidth. */ 3127 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3128 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3129 } else 3130 #endif 3131 { 3132 rtwn_write_1(sc, R92C_BWOPMODE, 3133 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3134 3135 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3136 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3137 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3138 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3139 3140 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3141 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3142 R92C_FPGA0_ANAPARAM2_CBW20); 3143 3144 /* Select 20MHz bandwidth. */ 3145 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3146 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 3147 } 3148 } 3149 3150 static void 3151 rtwn_iq_calib(struct rtwn_softc *sc) 3152 { 3153 3154 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3155 3156 /* XXX */ 3157 } 3158 3159 static void 3160 rtwn_lc_calib(struct rtwn_softc *sc) 3161 { 3162 uint32_t rf_ac[2]; 3163 uint8_t txmode; 3164 int i; 3165 3166 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3167 3168 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3169 if ((txmode & 0x70) != 0) { 3170 /* Disable all continuous Tx. */ 3171 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3172 3173 /* Set RF mode to standby mode. */ 3174 for (i = 0; i < sc->nrxchains; i++) { 3175 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3176 rtwn_rf_write(sc, i, R92C_RF_AC, 3177 RW(rf_ac[i], R92C_RF_AC_MODE, 3178 R92C_RF_AC_MODE_STANDBY)); 3179 } 3180 } else { 3181 /* Block all Tx queues. */ 3182 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3183 } 3184 /* Start calibration. */ 3185 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3186 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3187 3188 /* Give calibration the time to complete. */ 3189 DELAY(100); 3190 3191 /* Restore configuration. */ 3192 if ((txmode & 0x70) != 0) { 3193 /* Restore Tx mode. */ 3194 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3195 /* Restore RF mode. */ 3196 for (i = 0; i < sc->nrxchains; i++) 3197 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3198 } else { 3199 /* Unblock all Tx queues. */ 3200 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3201 } 3202 } 3203 3204 static void 3205 rtwn_temp_calib(struct rtwn_softc *sc) 3206 { 3207 int temp; 3208 3209 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3210 3211 if (sc->thcal_state == 0) { 3212 /* Start measuring temperature. */ 3213 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3214 sc->thcal_state = 1; 3215 return; 3216 } 3217 sc->thcal_state = 0; 3218 3219 /* Read measured temperature. */ 3220 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3221 if (temp == 0) /* Read failed, skip. */ 3222 return; 3223 DPRINTFN(2, ("temperature=%d\n", temp)); 3224 3225 /* 3226 * Redo IQ and LC calibration if temperature changed significantly 3227 * since last calibration. 3228 */ 3229 if (sc->thcal_lctemp == 0) { 3230 /* First calibration is performed in rtwn_init(). */ 3231 sc->thcal_lctemp = temp; 3232 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3233 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3234 sc->thcal_lctemp, temp)); 3235 rtwn_iq_calib(sc); 3236 rtwn_lc_calib(sc); 3237 /* Record temperature of last calibration. */ 3238 sc->thcal_lctemp = temp; 3239 } 3240 } 3241 3242 static int 3243 rtwn_init(struct ifnet *ifp) 3244 { 3245 struct rtwn_softc *sc = ifp->if_softc; 3246 struct ieee80211com *ic = &sc->sc_ic; 3247 uint32_t reg; 3248 int i, error; 3249 3250 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3251 3252 /* Init firmware commands ring. */ 3253 sc->fwcur = 0; 3254 3255 /* Power on adapter. */ 3256 error = rtwn_power_on(sc); 3257 if (error != 0) { 3258 aprint_error_dev(sc->sc_dev, "could not power on adapter\n"); 3259 goto fail; 3260 } 3261 3262 /* Initialize DMA. */ 3263 error = rtwn_dma_init(sc); 3264 if (error != 0) { 3265 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n"); 3266 goto fail; 3267 } 3268 3269 /* Set info size in Rx descriptors (in 64-bit words). */ 3270 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3271 3272 /* Disable interrupts. */ 3273 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3274 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3275 3276 /* Set MAC address. */ 3277 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl)); 3278 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3279 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3280 3281 /* Set initial network type. */ 3282 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc)); 3283 3284 rtwn_rxfilter_init(sc); 3285 3286 reg = rtwn_read_4(sc, R92C_RRSR); 3287 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3288 rtwn_write_4(sc, R92C_RRSR, reg); 3289 3290 /* Set short/long retry limits. */ 3291 rtwn_write_2(sc, R92C_RL, 3292 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3293 3294 /* Initialize EDCA parameters. */ 3295 rtwn_edca_init(sc); 3296 3297 /* Set data and response automatic rate fallback retry counts. */ 3298 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3299 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3300 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3301 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3302 3303 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3304 3305 /* Set ACK timeout. */ 3306 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3307 3308 /* Initialize beacon parameters. */ 3309 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3310 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3311 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3312 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3313 3314 /* Setup AMPDU aggregation. */ 3315 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3316 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3317 3318 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3319 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3320 3321 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3322 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3323 3324 /* Load 8051 microcode. */ 3325 error = rtwn_load_firmware(sc); 3326 if (error != 0) 3327 goto fail; 3328 3329 /* Initialize MAC/BB/RF blocks. */ 3330 rtwn_mac_init(sc); 3331 rtwn_bb_init(sc); 3332 rtwn_rf_init(sc); 3333 3334 /* Turn CCK and OFDM blocks on. */ 3335 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3336 reg |= R92C_RFMOD_CCK_EN; 3337 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3338 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3339 reg |= R92C_RFMOD_OFDM_EN; 3340 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3341 3342 /* Clear per-station keys table. */ 3343 rtwn_cam_init(sc); 3344 3345 /* Enable hardware sequence numbering. */ 3346 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3347 3348 /* Perform LO and IQ calibrations. */ 3349 rtwn_iq_calib(sc); 3350 /* Perform LC calibration. */ 3351 rtwn_lc_calib(sc); 3352 3353 rtwn_pa_bias_init(sc); 3354 3355 /* Initialize GPIO setting. */ 3356 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3357 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3358 3359 /* Fix for lower temperature. */ 3360 rtwn_write_1(sc, 0x15, 0xe9); 3361 3362 /* Set default channel. */ 3363 rtwn_set_chan(sc, ic->ic_curchan, NULL); 3364 3365 /* Clear pending interrupts. */ 3366 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3367 3368 /* Enable interrupts. */ 3369 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3370 3371 /* We're ready to go. */ 3372 ifp->if_flags &= ~IFF_OACTIVE; 3373 ifp->if_flags |= IFF_RUNNING; 3374 3375 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3376 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3377 else 3378 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3379 3380 return 0; 3381 3382 fail: 3383 rtwn_stop(ifp, 1); 3384 return error; 3385 } 3386 3387 static void 3388 rtwn_init_task(void *arg) 3389 { 3390 struct rtwn_softc *sc = arg; 3391 struct ifnet *ifp = GET_IFP(sc); 3392 int s; 3393 3394 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3395 3396 s = splnet(); 3397 3398 rtwn_stop(ifp, 0); 3399 3400 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3401 rtwn_init(ifp); 3402 3403 splx(s); 3404 } 3405 3406 static void 3407 rtwn_stop(struct ifnet *ifp, int disable) 3408 { 3409 struct rtwn_softc *sc = ifp->if_softc; 3410 struct ieee80211com *ic = &sc->sc_ic; 3411 uint16_t reg; 3412 int s, i; 3413 3414 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__)); 3415 3416 sc->sc_tx_timer = 0; 3417 ifp->if_timer = 0; 3418 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3419 3420 callout_stop(&sc->scan_to); 3421 callout_stop(&sc->calib_to); 3422 3423 s = splnet(); 3424 3425 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3426 3427 /* Disable interrupts. */ 3428 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3429 3430 /* Pause MAC TX queue */ 3431 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3432 3433 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3434 3435 /* Reset BB state machine */ 3436 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3437 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3438 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3439 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3440 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3441 3442 reg = rtwn_read_2(sc, R92C_CR); 3443 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3444 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3445 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3446 R92C_CR_ENSEC); 3447 rtwn_write_2(sc, R92C_CR, reg); 3448 3449 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3450 rtwn_fw_reset(sc); 3451 3452 /* Reset MAC and Enable 8051 */ 3453 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54); 3454 3455 /* TODO: linux does additional btcoex stuff here */ 3456 3457 /* Disable AFE PLL */ 3458 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3459 /* Enter PFM mode */ 3460 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3461 /* Gated AFE DIG_CLOCK */ 3462 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3463 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3464 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3465 3466 for (i = 0; i < RTWN_NTXQUEUES; i++) 3467 rtwn_reset_tx_list(sc, i); 3468 rtwn_reset_rx_list(sc); 3469 3470 splx(s); 3471 } 3472 3473 static int 3474 rtwn_intr(void *xsc) 3475 { 3476 struct rtwn_softc *sc = xsc; 3477 uint32_t status; 3478 int i; 3479 3480 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED)) 3481 return 0; 3482 3483 status = rtwn_read_4(sc, R92C_HISR); 3484 if (status == 0 || status == 0xffffffff) 3485 return 0; 3486 3487 /* Disable interrupts. */ 3488 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3489 3490 /* Ack interrupts. */ 3491 rtwn_write_4(sc, R92C_HISR, status); 3492 3493 /* Vendor driver treats RX errors like ROK... */ 3494 if (status & RTWN_INT_ENABLE_RX) { 3495 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3496 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3497 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3498 3499 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3500 continue; 3501 3502 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3503 } 3504 } 3505 3506 if (status & R92C_IMR_BDOK) 3507 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3508 if (status & R92C_IMR_HIGHDOK) 3509 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3510 if (status & R92C_IMR_MGNTDOK) 3511 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3512 if (status & R92C_IMR_BKDOK) 3513 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3514 if (status & R92C_IMR_BEDOK) 3515 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3516 if (status & R92C_IMR_VIDOK) 3517 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3518 if (status & R92C_IMR_VODOK) 3519 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3520 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) { 3521 struct ifnet *ifp = GET_IFP(sc); 3522 ifp->if_flags &= ~IFF_OACTIVE; 3523 if_schedule_deferred_start(ifp); 3524 } 3525 3526 /* Enable interrupts. */ 3527 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3528 3529 return 1; 3530 } 3531
Indexes created Thu Oct 02 01:09:59 GMT 2025