if_rtwnreg.h revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: if_rtwnreg.h,v 1.1.2.2 2015/09/22 12:05:59 skrll Exp $ */ 2 1.1.2.2 skrll /* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ 3 1.1.2.2 skrll 4 1.1.2.2 skrll /*- 5 1.1.2.2 skrll * Copyright (c) 2010 Damien Bergamini <damien.bergamini (at) free.fr> 6 1.1.2.2 skrll * Copyright (c) 2015 Stefan Sperling <stsp (at) openbsd.org> 7 1.1.2.2 skrll * 8 1.1.2.2 skrll * Permission to use, copy, modify, and distribute this software for any 9 1.1.2.2 skrll * purpose with or without fee is hereby granted, provided that the above 10 1.1.2.2 skrll * copyright notice and this permission notice appear in all copies. 11 1.1.2.2 skrll * 12 1.1.2.2 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 1.1.2.2 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 1.1.2.2 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 1.1.2.2 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 1.1.2.2 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 1.1.2.2 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 1.1.2.2 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 1.1.2.2 skrll */ 20 1.1.2.2 skrll 21 1.1.2.2 skrll #define R92C_MAX_CHAINS 2 22 1.1.2.2 skrll 23 1.1.2.2 skrll /* Maximum number of output pipes is 3. */ 24 1.1.2.2 skrll #define R92C_MAX_EPOUT 3 25 1.1.2.2 skrll 26 1.1.2.2 skrll #define R92C_MAX_TX_PWR 0x3f 27 1.1.2.2 skrll 28 1.1.2.2 skrll #define R92C_PUBQ_NPAGES 176 29 1.1.2.2 skrll #define R92C_HPQ_NPAGES 41 30 1.1.2.2 skrll #define R92C_LPQ_NPAGES 28 31 1.1.2.2 skrll #define R92C_TXPKTBUF_COUNT 256 32 1.1.2.2 skrll #define R92C_TX_PAGE_COUNT \ 33 1.1.2.2 skrll (R92C_PUBQ_NPAGES + R92C_HPQ_NPAGES + R92C_LPQ_NPAGES) 34 1.1.2.2 skrll #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 35 1.1.2.2 skrll 36 1.1.2.2 skrll #define R92C_H2C_NBOX 4 37 1.1.2.2 skrll 38 1.1.2.2 skrll /* USB Requests. */ 39 1.1.2.2 skrll #define R92C_REQ_REGS 0x05 40 1.1.2.2 skrll 41 1.1.2.2 skrll /* 42 1.1.2.2 skrll * MAC registers. 43 1.1.2.2 skrll */ 44 1.1.2.2 skrll /* System Configuration. */ 45 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL 0x000 46 1.1.2.2 skrll #define R92C_SYS_FUNC_EN 0x002 47 1.1.2.2 skrll #define R92C_APS_FSMCO 0x004 48 1.1.2.2 skrll #define R92C_SYS_CLKR 0x008 49 1.1.2.2 skrll #define R92C_AFE_MISC 0x010 50 1.1.2.2 skrll #define R92C_SPS0_CTRL 0x011 51 1.1.2.2 skrll #define R92C_SPS_OCP_CFG 0x018 52 1.1.2.2 skrll #define R92C_RSV_CTRL 0x01c 53 1.1.2.2 skrll #define R92C_RF_CTRL 0x01f 54 1.1.2.2 skrll #define R92C_LDOA15_CTRL 0x020 55 1.1.2.2 skrll #define R92C_LDOV12D_CTRL 0x021 56 1.1.2.2 skrll #define R92C_LDOHCI12_CTRL 0x022 57 1.1.2.2 skrll #define R92C_LPLDO_CTRL 0x023 58 1.1.2.2 skrll #define R92C_AFE_XTAL_CTRL 0x024 59 1.1.2.2 skrll #define R92C_AFE_PLL_CTRL 0x028 60 1.1.2.2 skrll #define R92C_EFUSE_CTRL 0x030 61 1.1.2.2 skrll #define R92C_EFUSE_TEST 0x034 62 1.1.2.2 skrll #define R92C_PWR_DATA 0x038 63 1.1.2.2 skrll #define R92C_CAL_TIMER 0x03c 64 1.1.2.2 skrll #define R92C_ACLK_MON 0x03e 65 1.1.2.2 skrll #define R92C_GPIO_MUXCFG 0x040 66 1.1.2.2 skrll #define R92C_GPIO_IO_SEL 0x042 67 1.1.2.2 skrll #define R92C_MAC_PINMUX_CFG 0x043 68 1.1.2.2 skrll #define R92C_GPIO_PIN_CTRL 0x044 69 1.1.2.2 skrll #define R92C_GPIO_INTM 0x048 70 1.1.2.2 skrll #define R92C_LEDCFG0 0x04c 71 1.1.2.2 skrll #define R92C_LEDCFG1 0x04d 72 1.1.2.2 skrll #define R92C_LEDCFG2 0x04e 73 1.1.2.2 skrll #define R92C_LEDCFG3 0x04f 74 1.1.2.2 skrll #define R92C_FSIMR 0x050 75 1.1.2.2 skrll #define R92C_FSISR 0x054 76 1.1.2.2 skrll #define R92C_HSIMR 0x058 77 1.1.2.2 skrll #define R92C_HSISR 0x05c 78 1.1.2.2 skrll #define R92C_MCUFWDL 0x080 79 1.1.2.2 skrll #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 80 1.1.2.2 skrll #define R92C_BIST_SCAN 0x0d0 81 1.1.2.2 skrll #define R92C_BIST_RPT 0x0d4 82 1.1.2.2 skrll #define R92C_BIST_ROM_RPT 0x0d8 83 1.1.2.2 skrll #define R92C_USB_SIE_INTF 0x0e0 84 1.1.2.2 skrll #define R92C_PCIE_MIO_INTF 0x0e4 85 1.1.2.2 skrll #define R92C_PCIE_MIO_INTD 0x0e8 86 1.1.2.2 skrll #define R92C_HPON_FSM 0x0ec 87 1.1.2.2 skrll #define R92C_SYS_CFG 0x0f0 88 1.1.2.2 skrll /* MAC General Configuration. */ 89 1.1.2.2 skrll #define R92C_CR 0x100 90 1.1.2.2 skrll #define R92C_PBP 0x104 91 1.1.2.2 skrll #define R92C_TRXDMA_CTRL 0x10c 92 1.1.2.2 skrll #define R92C_TRXFF_BNDY 0x114 93 1.1.2.2 skrll #define R92C_TRXFF_STATUS 0x118 94 1.1.2.2 skrll #define R92C_RXFF_PTR 0x11c 95 1.1.2.2 skrll #define R92C_HIMR 0x120 96 1.1.2.2 skrll #define R92C_HISR 0x124 97 1.1.2.2 skrll #define R92C_HIMRE 0x128 98 1.1.2.2 skrll #define R92C_HISRE 0x12c 99 1.1.2.2 skrll #define R92C_CPWM 0x12f 100 1.1.2.2 skrll #define R92C_FWIMR 0x130 101 1.1.2.2 skrll #define R92C_FWISR 0x134 102 1.1.2.2 skrll #define R92C_PKTBUF_DBG_CTRL 0x140 103 1.1.2.2 skrll #define R92C_PKTBUF_DBG_DATA_L 0x144 104 1.1.2.2 skrll #define R92C_PKTBUF_DBG_DATA_H 0x148 105 1.1.2.2 skrll #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 106 1.1.2.2 skrll #define R92C_TCUNIT_BASE 0x164 107 1.1.2.2 skrll #define R92C_MBIST_START 0x174 108 1.1.2.2 skrll #define R92C_MBIST_DONE 0x178 109 1.1.2.2 skrll #define R92C_MBIST_FAIL 0x17c 110 1.1.2.2 skrll #define R92C_C2HEVT_MSG_NORMAL 0x1a0 111 1.1.2.2 skrll #define R92C_C2HEVT_MSG_TEST 0x1b8 112 1.1.2.2 skrll #define R92C_C2HEVT_CLEAR 0x1bf 113 1.1.2.2 skrll #define R92C_MCUTST_1 0x1c0 114 1.1.2.2 skrll #define R92C_FMETHR 0x1c8 115 1.1.2.2 skrll #define R92C_HMETFR 0x1cc 116 1.1.2.2 skrll #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 117 1.1.2.2 skrll #define R92C_LLT_INIT 0x1e0 118 1.1.2.2 skrll #define R92C_BB_ACCESS_CTRL 0x1e8 119 1.1.2.2 skrll #define R92C_BB_ACCESS_DATA 0x1ec 120 1.1.2.2 skrll /* Tx DMA Configuration. */ 121 1.1.2.2 skrll #define R92C_RQPN 0x200 122 1.1.2.2 skrll #define R92C_FIFOPAGE 0x204 123 1.1.2.2 skrll #define R92C_TDECTRL 0x208 124 1.1.2.2 skrll #define R92C_TXDMA_OFFSET_CHK 0x20c 125 1.1.2.2 skrll #define R92C_TXDMA_STATUS 0x210 126 1.1.2.2 skrll #define R92C_RQPN_NPQ 0x214 127 1.1.2.2 skrll /* Rx DMA Configuration. */ 128 1.1.2.2 skrll #define R92C_RXDMA_AGG_PG_TH 0x280 129 1.1.2.2 skrll #define R92C_RXPKT_NUM 0x284 130 1.1.2.2 skrll #define R92C_RXDMA_STATUS 0x288 131 1.1.2.2 skrll 132 1.1.2.2 skrll #define R92C_PCIE_CTRL_REG 0x300 133 1.1.2.2 skrll #define R92C_INT_MIG 0x304 134 1.1.2.2 skrll #define R92C_BCNQ_DESA 0x308 135 1.1.2.2 skrll #define R92C_HQ_DESA 0x310 136 1.1.2.2 skrll #define R92C_MGQ_DESA 0x318 137 1.1.2.2 skrll #define R92C_VOQ_DESA 0x320 138 1.1.2.2 skrll #define R92C_VIQ_DESA 0x328 139 1.1.2.2 skrll #define R92C_BEQ_DESA 0x330 140 1.1.2.2 skrll #define R92C_BKQ_DESA 0x338 141 1.1.2.2 skrll #define R92C_RX_DESA 0x340 142 1.1.2.2 skrll #define R92C_DBI 0x348 143 1.1.2.2 skrll #define R92C_MDIO 0x354 144 1.1.2.2 skrll #define R92C_DBG_SEL 0x360 145 1.1.2.2 skrll #define R92C_PCIE_HRPWM 0x361 146 1.1.2.2 skrll #define R92C_PCIE_HCPWM 0x363 147 1.1.2.2 skrll #define R92C_UART_CTRL 0x364 148 1.1.2.2 skrll #define R92C_UART_TX_DES 0x370 149 1.1.2.2 skrll #define R92C_UART_RX_DES 0x378 150 1.1.2.2 skrll 151 1.1.2.2 skrll #define R92C_VOQ_INFORMATION 0x0400 152 1.1.2.2 skrll #define R92C_VIQ_INFORMATION 0x0404 153 1.1.2.2 skrll #define R92C_BEQ_INFORMATION 0x0408 154 1.1.2.2 skrll #define R92C_BKQ_INFORMATION 0x040C 155 1.1.2.2 skrll #define R92C_MGQ_INFORMATION 0x0410 156 1.1.2.2 skrll #define R92C_HGQ_INFORMATION 0x0414 157 1.1.2.2 skrll #define R92C_BCNQ_INFORMATION 0x0418 158 1.1.2.2 skrll #define R92C_CPU_MGQ_INFORMATION 0x041C 159 1.1.2.2 skrll 160 1.1.2.2 skrll /* Protocol Configuration. */ 161 1.1.2.2 skrll #define R92C_FWHW_TXQ_CTRL 0x420 162 1.1.2.2 skrll #define R92C_HWSEQ_CTRL 0x423 163 1.1.2.2 skrll #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 164 1.1.2.2 skrll #define R92C_TXPKTBUF_MGQ_BDNY 0x425 165 1.1.2.2 skrll #define R92C_SPEC_SIFS 0x428 166 1.1.2.2 skrll #define R92C_RL 0x42a 167 1.1.2.2 skrll #define R92C_DARFRC 0x430 168 1.1.2.2 skrll #define R92C_RARFRC 0x438 169 1.1.2.2 skrll #define R92C_RRSR 0x440 170 1.1.2.2 skrll #define R92C_ARFR(i) (0x444 + (i) * 4) 171 1.1.2.2 skrll #define R92C_AGGLEN_LMT 0x458 172 1.1.2.2 skrll #define R92C_AMPDU_MIN_SPACE 0x45c 173 1.1.2.2 skrll #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 174 1.1.2.2 skrll #define R92C_FAST_EDCA_CTRL 0x460 175 1.1.2.2 skrll #define R92C_RD_RESP_PKT_TH 0x463 176 1.1.2.2 skrll #define R92C_INIRTS_RATE_SEL 0x480 177 1.1.2.2 skrll #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 178 1.1.2.2 skrll /* EDCA Configuration. */ 179 1.1.2.2 skrll #define R92C_EDCA_VO_PARAM 0x500 180 1.1.2.2 skrll #define R92C_EDCA_VI_PARAM 0x504 181 1.1.2.2 skrll #define R92C_EDCA_BE_PARAM 0x508 182 1.1.2.2 skrll #define R92C_EDCA_BK_PARAM 0x50c 183 1.1.2.2 skrll #define R92C_BCNTCFG 0x510 184 1.1.2.2 skrll #define R92C_PIFS 0x512 185 1.1.2.2 skrll #define R92C_RDG_PIFS 0x513 186 1.1.2.2 skrll #define R92C_SIFS_CCK 0x514 187 1.1.2.2 skrll #define R92C_SIFS_OFDM 0x516 188 1.1.2.2 skrll #define R92C_AGGR_BREAK_TIME 0x51a 189 1.1.2.2 skrll #define R92C_SLOT 0x51b 190 1.1.2.2 skrll #define R92C_TX_PTCL_CTRL 0x520 191 1.1.2.2 skrll #define R92C_TXPAUSE 0x522 192 1.1.2.2 skrll #define R92C_DIS_TXREQ_CLR 0x523 193 1.1.2.2 skrll #define R92C_RD_CTRL 0x524 194 1.1.2.2 skrll #define R92C_TBTT_PROHIBIT 0x540 195 1.1.2.2 skrll #define R92C_RD_NAV_NXT 0x544 196 1.1.2.2 skrll #define R92C_NAV_PROT_LEN 0x546 197 1.1.2.2 skrll #define R92C_BCN_CTRL 0x550 198 1.1.2.2 skrll #define R92C_USTIME_TSF 0x551 199 1.1.2.2 skrll #define R92C_MBID_NUM 0x552 200 1.1.2.2 skrll #define R92C_DUAL_TSF_RST 0x553 201 1.1.2.2 skrll #define R92C_BCN_INTERVAL 0x554 202 1.1.2.2 skrll #define R92C_DRVERLYINT 0x558 203 1.1.2.2 skrll #define R92C_BCNDMATIM 0x559 204 1.1.2.2 skrll #define R92C_ATIMWND 0x55a 205 1.1.2.2 skrll #define R92C_BCN_MAX_ERR 0x55d 206 1.1.2.2 skrll #define R92C_RXTSF_OFFSET_CCK 0x55e 207 1.1.2.2 skrll #define R92C_RXTSF_OFFSET_OFDM 0x55f 208 1.1.2.2 skrll #define R92C_TSFTR 0x560 209 1.1.2.2 skrll #define R92C_INIT_TSFTR 0x564 210 1.1.2.2 skrll #define R92C_PSTIMER 0x580 211 1.1.2.2 skrll #define R92C_TIMER0 0x584 212 1.1.2.2 skrll #define R92C_TIMER1 0x588 213 1.1.2.2 skrll #define R92C_ACMHWCTRL 0x5c0 214 1.1.2.2 skrll #define R92C_ACMRSTCTRL 0x5c1 215 1.1.2.2 skrll #define R92C_ACMAVG 0x5c2 216 1.1.2.2 skrll #define R92C_VO_ADMTIME 0x5c4 217 1.1.2.2 skrll #define R92C_VI_ADMTIME 0x5c6 218 1.1.2.2 skrll #define R92C_BE_ADMTIME 0x5c8 219 1.1.2.2 skrll #define R92C_EDCA_RANDOM_GEN 0x5cc 220 1.1.2.2 skrll #define R92C_SCH_TXCMD 0x5d0 221 1.1.2.2 skrll /* WMAC Configuration. */ 222 1.1.2.2 skrll #define R92C_APSD_CTRL 0x600 223 1.1.2.2 skrll #define R92C_BWOPMODE 0x603 224 1.1.2.2 skrll #define R92C_TCR 0x604 225 1.1.2.2 skrll #define R92C_RCR 0x608 226 1.1.2.2 skrll #define R92C_RX_DRVINFO_SZ 0x60f 227 1.1.2.2 skrll #define R92C_MACID 0x610 228 1.1.2.2 skrll #define R92C_BSSID 0x618 229 1.1.2.2 skrll #define R92C_MAR 0x620 230 1.1.2.2 skrll #define R92C_MAC_SPEC_SIFS 0x63a 231 1.1.2.2 skrll #define R92C_R2T_SIFS 0x63c 232 1.1.2.2 skrll #define R92C_T2T_SIFS 0x63e 233 1.1.2.2 skrll #define R92C_ACKTO 0x640 234 1.1.2.2 skrll #define R92C_CAMCMD 0x670 235 1.1.2.2 skrll #define R92C_CAMWRITE 0x674 236 1.1.2.2 skrll #define R92C_CAMREAD 0x678 237 1.1.2.2 skrll #define R92C_CAMDBG 0x67c 238 1.1.2.2 skrll #define R92C_SECCFG 0x680 239 1.1.2.2 skrll #define R92C_RXFLTMAP0 0x6a0 240 1.1.2.2 skrll #define R92C_RXFLTMAP1 0x6a2 241 1.1.2.2 skrll #define R92C_RXFLTMAP2 0x6a4 242 1.1.2.2 skrll 243 1.1.2.2 skrll /* Bits for R92C_SYS_ISO_CTRL. */ 244 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 245 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 246 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 247 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 248 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 249 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 250 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_DIOP 0x0040 251 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_DIOE 0x0080 252 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 253 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_DIOR 0x0200 254 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 255 1.1.2.2 skrll #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 256 1.1.2.2 skrll 257 1.1.2.2 skrll /* Bits for R92C_SYS_FUNC_EN. */ 258 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 259 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 260 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_USBA 0x0004 261 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_UPLL 0x0008 262 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_USBD 0x0010 263 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 264 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_PCIEA 0x0040 265 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_PPLL 0x0080 266 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_PCIED 0x0100 267 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_DIOE 0x0200 268 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_CPUEN 0x0400 269 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_DCORE 0x0800 270 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_ELDR 0x1000 271 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 272 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_HWPDN 0x4000 273 1.1.2.2 skrll #define R92C_SYS_FUNC_EN_MREGEN 0x8000 274 1.1.2.2 skrll 275 1.1.2.2 skrll /* Bits for R92C_APS_FSMCO. */ 276 1.1.2.2 skrll #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 277 1.1.2.2 skrll #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 278 1.1.2.2 skrll #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 279 1.1.2.2 skrll #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 280 1.1.2.2 skrll #define R92C_APS_FSMCO_PDN_EN 0x00000010 281 1.1.2.2 skrll #define R92C_APS_FSMCO_PDN_PL 0x00000020 282 1.1.2.2 skrll #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 283 1.1.2.2 skrll #define R92C_APS_FSMCO_APFM_OFF 0x00000200 284 1.1.2.2 skrll #define R92C_APS_FSMCO_APFM_RSM 0x00000400 285 1.1.2.2 skrll #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 286 1.1.2.2 skrll #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 287 1.1.2.2 skrll #define R92C_APS_FSMCO_APDM_MAC 0x00002000 288 1.1.2.2 skrll #define R92C_APS_FSMCO_APDM_HOST 0x00004000 289 1.1.2.2 skrll #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 290 1.1.2.2 skrll #define R92C_APS_FSMCO_RDY_MACON 0x00010000 291 1.1.2.2 skrll #define R92C_APS_FSMCO_SUS_HOST 0x00020000 292 1.1.2.2 skrll #define R92C_APS_FSMCO_ROP_ALD 0x00100000 293 1.1.2.2 skrll #define R92C_APS_FSMCO_ROP_PWR 0x00200000 294 1.1.2.2 skrll #define R92C_APS_FSMCO_ROP_SPS 0x00400000 295 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_MRST 0x02000000 296 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 297 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_ABG 0x08000000 298 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_AMB 0x10000000 299 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_RCK 0x20000000 300 1.1.2.2 skrll #define R92C_APS_FSMCO_SOP_A8M 0x40000000 301 1.1.2.2 skrll #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 302 1.1.2.2 skrll 303 1.1.2.2 skrll /* Bits for R92C_SYS_CLKR. */ 304 1.1.2.2 skrll #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 305 1.1.2.2 skrll #define R92C_SYS_CLKR_ANA8M 0x00000002 306 1.1.2.2 skrll #define R92C_SYS_CLKR_MACSLP 0x00000010 307 1.1.2.2 skrll #define R92C_SYS_CLKR_LOADER_EN 0x00000020 308 1.1.2.2 skrll #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 309 1.1.2.2 skrll #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 310 1.1.2.2 skrll #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 311 1.1.2.2 skrll #define R92C_SYS_CLKR_SEC_EN 0x00000400 312 1.1.2.2 skrll #define R92C_SYS_CLKR_MAC_EN 0x00000800 313 1.1.2.2 skrll #define R92C_SYS_CLKR_SYS_EN 0x00001000 314 1.1.2.2 skrll #define R92C_SYS_CLKR_RING_EN 0x00002000 315 1.1.2.2 skrll 316 1.1.2.2 skrll /* Bits for R92C_RF_CTRL. */ 317 1.1.2.2 skrll #define R92C_RF_CTRL_EN 0x01 318 1.1.2.2 skrll #define R92C_RF_CTRL_RSTB 0x02 319 1.1.2.2 skrll #define R92C_RF_CTRL_SDMRSTB 0x04 320 1.1.2.2 skrll 321 1.1.2.2 skrll /* Bits for R92C_LDOV12D_CTRL. */ 322 1.1.2.2 skrll #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 323 1.1.2.2 skrll 324 1.1.2.2 skrll /* Bits for R92C_EFUSE_CTRL. */ 325 1.1.2.2 skrll #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 326 1.1.2.2 skrll #define R92C_EFUSE_CTRL_DATA_S 0 327 1.1.2.2 skrll #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 328 1.1.2.2 skrll #define R92C_EFUSE_CTRL_ADDR_S 8 329 1.1.2.2 skrll #define R92C_EFUSE_CTRL_VALID 0x80000000 330 1.1.2.2 skrll 331 1.1.2.2 skrll /* Bits for R92C_GPIO_MUXCFG. */ 332 1.1.2.2 skrll #define R92C_GPIO_MUXCFG_RFKILL 0x0008 333 1.1.2.2 skrll #define R92C_GPIO_MUXCFG_ENBT 0x0020 334 1.1.2.2 skrll 335 1.1.2.2 skrll /* Bits for R92C_GPIO_IO_SEL. */ 336 1.1.2.2 skrll #define R92C_GPIO_IO_SEL_RFKILL 0x0008 337 1.1.2.2 skrll 338 1.1.2.2 skrll /* Bits for R92C_LEDCFG0. */ 339 1.1.2.2 skrll #define R92C_LEDCFG0_DIS 0x08 340 1.1.2.2 skrll 341 1.1.2.2 skrll /* Bits for R92C_LEDCFG2. */ 342 1.1.2.2 skrll #define R92C_LEDCFG2_EN 0x60 343 1.1.2.2 skrll #define R92C_LEDCFG2_DIS 0x68 344 1.1.2.2 skrll 345 1.1.2.2 skrll /* Bits for R92C_MCUFWDL. */ 346 1.1.2.2 skrll #define R92C_MCUFWDL_EN 0x00000001 347 1.1.2.2 skrll #define R92C_MCUFWDL_RDY 0x00000002 348 1.1.2.2 skrll #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 349 1.1.2.2 skrll #define R92C_MCUFWDL_MACINI_RDY 0x00000008 350 1.1.2.2 skrll #define R92C_MCUFWDL_BBINI_RDY 0x00000010 351 1.1.2.2 skrll #define R92C_MCUFWDL_RFINI_RDY 0x00000020 352 1.1.2.2 skrll #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 353 1.1.2.2 skrll #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 354 1.1.2.2 skrll #define R92C_MCUFWDL_PAGE_M 0x00070000 355 1.1.2.2 skrll #define R92C_MCUFWDL_PAGE_S 16 356 1.1.2.2 skrll #define R92C_MCUFWDL_CPRST 0x00800000 357 1.1.2.2 skrll 358 1.1.2.2 skrll /* Bits for R92C_HPON_FSM. */ 359 1.1.2.2 skrll #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 360 1.1.2.2 skrll #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 361 1.1.2.2 skrll #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 362 1.1.2.2 skrll 363 1.1.2.2 skrll /* Bits for R92C_SYS_CFG. */ 364 1.1.2.2 skrll #define R92C_SYS_CFG_XCLK_VLD 0x00000001 365 1.1.2.2 skrll #define R92C_SYS_CFG_ACLK_VLD 0x00000002 366 1.1.2.2 skrll #define R92C_SYS_CFG_UCLK_VLD 0x00000004 367 1.1.2.2 skrll #define R92C_SYS_CFG_PCLK_VLD 0x00000008 368 1.1.2.2 skrll #define R92C_SYS_CFG_PCIRSTB 0x00000010 369 1.1.2.2 skrll #define R92C_SYS_CFG_V15_VLD 0x00000020 370 1.1.2.2 skrll #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 371 1.1.2.2 skrll #define R92C_SYS_CFG_SIC_IDLE 0x00000100 372 1.1.2.2 skrll #define R92C_SYS_CFG_BD_MAC2 0x00000200 373 1.1.2.2 skrll #define R92C_SYS_CFG_BD_MAC1 0x00000400 374 1.1.2.2 skrll #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 375 1.1.2.2 skrll #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 376 1.1.2.2 skrll #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 377 1.1.2.2 skrll #define R92C_SYS_CFG_BT_FUNC 0x00010000 378 1.1.2.2 skrll #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 379 1.1.2.2 skrll #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 380 1.1.2.2 skrll #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 381 1.1.2.2 skrll #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 382 1.1.2.2 skrll #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 383 1.1.2.2 skrll #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 384 1.1.2.2 skrll #define R92C_SYS_CFG_TYPE_92C 0x08000000 385 1.1.2.2 skrll 386 1.1.2.2 skrll /* Bits for R92C_CR. */ 387 1.1.2.2 skrll #define R92C_CR_HCI_TXDMA_EN 0x00000001 388 1.1.2.2 skrll #define R92C_CR_HCI_RXDMA_EN 0x00000002 389 1.1.2.2 skrll #define R92C_CR_TXDMA_EN 0x00000004 390 1.1.2.2 skrll #define R92C_CR_RXDMA_EN 0x00000008 391 1.1.2.2 skrll #define R92C_CR_PROTOCOL_EN 0x00000010 392 1.1.2.2 skrll #define R92C_CR_SCHEDULE_EN 0x00000020 393 1.1.2.2 skrll #define R92C_CR_MACTXEN 0x00000040 394 1.1.2.2 skrll #define R92C_CR_MACRXEN 0x00000080 395 1.1.2.2 skrll #define R92C_CR_ENSEC 0x00000200 396 1.1.2.2 skrll #define R92C_CR_NETTYPE_S 16 397 1.1.2.2 skrll #define R92C_CR_NETTYPE_M 0x00030000 398 1.1.2.2 skrll #define R92C_CR_NETTYPE_NOLINK 0 399 1.1.2.2 skrll #define R92C_CR_NETTYPE_ADHOC 1 400 1.1.2.2 skrll #define R92C_CR_NETTYPE_INFRA 2 401 1.1.2.2 skrll #define R92C_CR_NETTYPE_AP 3 402 1.1.2.2 skrll 403 1.1.2.2 skrll /* Bits for R92C_PBP. */ 404 1.1.2.2 skrll #define R92C_PBP_PSRX_M 0x0f 405 1.1.2.2 skrll #define R92C_PBP_PSRX_S 0 406 1.1.2.2 skrll #define R92C_PBP_PSTX_M 0xf0 407 1.1.2.2 skrll #define R92C_PBP_PSTX_S 4 408 1.1.2.2 skrll #define R92C_PBP_64 0 409 1.1.2.2 skrll #define R92C_PBP_128 1 410 1.1.2.2 skrll #define R92C_PBP_256 2 411 1.1.2.2 skrll #define R92C_PBP_512 3 412 1.1.2.2 skrll #define R92C_PBP_1024 4 413 1.1.2.2 skrll 414 1.1.2.2 skrll /* Bits for R92C_TRXDMA_CTRL. */ 415 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 416 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 417 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 418 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 419 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 420 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 421 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 422 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 423 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 424 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 425 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 426 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 427 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 428 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 429 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 430 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 431 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 432 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_S 4 433 1.1.2.2 skrll /* Shortcuts. */ 434 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 435 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 436 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 437 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 438 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 439 1.1.2.2 skrll #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 440 1.1.2.2 skrll 441 1.1.2.2 skrll /* Bits for R92C_LLT_INIT. */ 442 1.1.2.2 skrll #define R92C_LLT_INIT_DATA_M 0x000000ff 443 1.1.2.2 skrll #define R92C_LLT_INIT_DATA_S 0 444 1.1.2.2 skrll #define R92C_LLT_INIT_ADDR_M 0x0000ff00 445 1.1.2.2 skrll #define R92C_LLT_INIT_ADDR_S 8 446 1.1.2.2 skrll #define R92C_LLT_INIT_OP_M 0xc0000000 447 1.1.2.2 skrll #define R92C_LLT_INIT_OP_S 30 448 1.1.2.2 skrll #define R92C_LLT_INIT_OP_NO_ACTIVE 0 449 1.1.2.2 skrll #define R92C_LLT_INIT_OP_WRITE 1 450 1.1.2.2 skrll 451 1.1.2.2 skrll /* Bits for R92C_RQPN. */ 452 1.1.2.2 skrll #define R92C_RQPN_HPQ_M 0x000000ff 453 1.1.2.2 skrll #define R92C_RQPN_HPQ_S 0 454 1.1.2.2 skrll #define R92C_RQPN_LPQ_M 0x0000ff00 455 1.1.2.2 skrll #define R92C_RQPN_LPQ_S 8 456 1.1.2.2 skrll #define R92C_RQPN_PUBQ_M 0x00ff0000 457 1.1.2.2 skrll #define R92C_RQPN_PUBQ_S 16 458 1.1.2.2 skrll #define R92C_RQPN_LD 0x80000000 459 1.1.2.2 skrll 460 1.1.2.2 skrll /* Bits for R92C_TDECTRL. */ 461 1.1.2.2 skrll #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 462 1.1.2.2 skrll #define R92C_TDECTRL_BLK_DESC_NUM_S 4 463 1.1.2.2 skrll 464 1.1.2.2 skrll /* Bits for R92C_FWHW_TXQ_CTRL. */ 465 1.1.2.2 skrll #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 466 1.1.2.2 skrll 467 1.1.2.2 skrll /* Bits for R92C_SPEC_SIFS. */ 468 1.1.2.2 skrll #define R92C_SPEC_SIFS_CCK_M 0x00ff 469 1.1.2.2 skrll #define R92C_SPEC_SIFS_CCK_S 0 470 1.1.2.2 skrll #define R92C_SPEC_SIFS_OFDM_M 0xff00 471 1.1.2.2 skrll #define R92C_SPEC_SIFS_OFDM_S 8 472 1.1.2.2 skrll 473 1.1.2.2 skrll /* Bits for R92C_RL. */ 474 1.1.2.2 skrll #define R92C_RL_LRL_M 0x003f 475 1.1.2.2 skrll #define R92C_RL_LRL_S 0 476 1.1.2.2 skrll #define R92C_RL_SRL_M 0x3f00 477 1.1.2.2 skrll #define R92C_RL_SRL_S 8 478 1.1.2.2 skrll 479 1.1.2.2 skrll /* Bits for R92C_RRSR. */ 480 1.1.2.2 skrll #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 481 1.1.2.2 skrll #define R92C_RRSR_RATE_BITMAP_S 0 482 1.1.2.2 skrll #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 483 1.1.2.2 skrll #define R92C_RRSR_RATE_ALL 0xfffff 484 1.1.2.2 skrll #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 485 1.1.2.2 skrll #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 486 1.1.2.2 skrll #define R92C_RRSR_SHORT 0x00800000 487 1.1.2.2 skrll 488 1.1.2.2 skrll /* Bits for R92C_EDCA_XX_PARAM. */ 489 1.1.2.2 skrll #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 490 1.1.2.2 skrll #define R92C_EDCA_PARAM_AIFS_S 0 491 1.1.2.2 skrll #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 492 1.1.2.2 skrll #define R92C_EDCA_PARAM_ECWMIN_S 8 493 1.1.2.2 skrll #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 494 1.1.2.2 skrll #define R92C_EDCA_PARAM_ECWMAX_S 12 495 1.1.2.2 skrll #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 496 1.1.2.2 skrll #define R92C_EDCA_PARAM_TXOP_S 16 497 1.1.2.2 skrll 498 1.1.2.2 skrll /* Bits for R92C_TXPAUSE. */ 499 1.1.2.2 skrll #define R92C_TXPAUSE_AC_VO 0x01 500 1.1.2.2 skrll #define R92C_TXPAUSE_AC_VI 0x02 501 1.1.2.2 skrll #define R92C_TXPAUSE_AC_BE 0x04 502 1.1.2.2 skrll #define R92C_TXPAUSE_AC_BK 0x08 503 1.1.2.2 skrll 504 1.1.2.2 skrll /* Bits for R92C_BCN_CTRL. */ 505 1.1.2.2 skrll #define R92C_BCN_CTRL_EN_MBSSID 0x02 506 1.1.2.2 skrll #define R92C_BCN_CTRL_TXBCN_RPT 0x04 507 1.1.2.2 skrll #define R92C_BCN_CTRL_EN_BCN 0x08 508 1.1.2.2 skrll #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 509 1.1.2.2 skrll 510 1.1.2.2 skrll /* Bits for R92C_APSD_CTRL. */ 511 1.1.2.2 skrll #define R92C_APSD_CTRL_OFF 0x40 512 1.1.2.2 skrll #define R92C_APSD_CTRL_OFF_STATUS 0x80 513 1.1.2.2 skrll 514 1.1.2.2 skrll /* Bits for R92C_BWOPMODE. */ 515 1.1.2.2 skrll #define R92C_BWOPMODE_11J 0x01 516 1.1.2.2 skrll #define R92C_BWOPMODE_5G 0x02 517 1.1.2.2 skrll #define R92C_BWOPMODE_20MHZ 0x04 518 1.1.2.2 skrll 519 1.1.2.2 skrll /* Bits for R92C_TCR. */ 520 1.1.2.2 skrll #define R92C_TCR_TSFRST 0x00000001 521 1.1.2.2 skrll #define R92C_TCR_DIS_GCLK 0x00000002 522 1.1.2.2 skrll #define R92C_TCR_PAD_SEL 0x00000004 523 1.1.2.2 skrll #define R92C_TCR_PWR_ST 0x00000040 524 1.1.2.2 skrll #define R92C_TCR_PWRBIT_OW_EN 0x00000080 525 1.1.2.2 skrll #define R92C_TCR_ACRC 0x00000100 526 1.1.2.2 skrll #define R92C_TCR_CFENDFORM 0x00000200 527 1.1.2.2 skrll #define R92C_TCR_ICV 0x00000400 528 1.1.2.2 skrll 529 1.1.2.2 skrll /* Bits for R92C_RCR. */ 530 1.1.2.2 skrll #define R92C_RCR_AAP 0x00000001 531 1.1.2.2 skrll #define R92C_RCR_APM 0x00000002 532 1.1.2.2 skrll #define R92C_RCR_AM 0x00000004 533 1.1.2.2 skrll #define R92C_RCR_AB 0x00000008 534 1.1.2.2 skrll #define R92C_RCR_ADD3 0x00000010 535 1.1.2.2 skrll #define R92C_RCR_APWRMGT 0x00000020 536 1.1.2.2 skrll #define R92C_RCR_CBSSID_DATA 0x00000040 537 1.1.2.2 skrll #define R92C_RCR_CBSSID_BCN 0x00000080 538 1.1.2.2 skrll #define R92C_RCR_ACRC32 0x00000100 539 1.1.2.2 skrll #define R92C_RCR_AICV 0x00000200 540 1.1.2.2 skrll #define R92C_RCR_ADF 0x00000800 541 1.1.2.2 skrll #define R92C_RCR_ACF 0x00001000 542 1.1.2.2 skrll #define R92C_RCR_AMF 0x00002000 543 1.1.2.2 skrll #define R92C_RCR_HTC_LOC_CTRL 0x00004000 544 1.1.2.2 skrll #define R92C_RCR_MFBEN 0x00400000 545 1.1.2.2 skrll #define R92C_RCR_LSIGEN 0x00800000 546 1.1.2.2 skrll #define R92C_RCR_ENMBID 0x01000000 547 1.1.2.2 skrll #define R92C_RCR_APP_BA_SSN 0x08000000 548 1.1.2.2 skrll #define R92C_RCR_APP_PHYSTS 0x10000000 549 1.1.2.2 skrll #define R92C_RCR_APP_ICV 0x20000000 550 1.1.2.2 skrll #define R92C_RCR_APP_MIC 0x40000000 551 1.1.2.2 skrll #define R92C_RCR_APPFCS 0x80000000 552 1.1.2.2 skrll 553 1.1.2.2 skrll /* Bits for R92C_CAMCMD. */ 554 1.1.2.2 skrll #define R92C_CAMCMD_ADDR_M 0x0000ffff 555 1.1.2.2 skrll #define R92C_CAMCMD_ADDR_S 0 556 1.1.2.2 skrll #define R92C_CAMCMD_WRITE 0x00010000 557 1.1.2.2 skrll #define R92C_CAMCMD_CLR 0x40000000 558 1.1.2.2 skrll #define R92C_CAMCMD_POLLING 0x80000000 559 1.1.2.2 skrll 560 1.1.2.2 skrll /* IMR */ 561 1.1.2.2 skrll 562 1.1.2.2 skrll /*Beacon DMA interrupt 6 */ 563 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT6 0x80000000 564 1.1.2.2 skrll /*Beacon DMA interrupt 5 */ 565 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT5 0x40000000 566 1.1.2.2 skrll /*Beacon DMA interrupt 4 */ 567 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT4 0x20000000 568 1.1.2.2 skrll /*Beacon DMA interrupt 3 */ 569 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT3 0x10000000 570 1.1.2.2 skrll /*Beacon DMA interrupt 2 */ 571 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT2 0x08000000 572 1.1.2.2 skrll /*Beacon DMA interrupt 1 */ 573 1.1.2.2 skrll #define R92C_IMR_BCNDMAINT1 0x04000000 574 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 8 */ 575 1.1.2.2 skrll #define R92C_IMR_BCNDOK8 0x02000000 576 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 7 */ 577 1.1.2.2 skrll #define R92C_IMR_BCNDOK7 0x01000000 578 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 6 */ 579 1.1.2.2 skrll #define R92C_IMR_BCNDOK6 0x00800000 580 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 5 */ 581 1.1.2.2 skrll #define R92C_IMR_BCNDOK5 0x00400000 582 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 4 */ 583 1.1.2.2 skrll #define R92C_IMR_BCNDOK4 0x00200000 584 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 3 */ 585 1.1.2.2 skrll #define R92C_IMR_BCNDOK3 0x00100000 586 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 2 */ 587 1.1.2.2 skrll #define R92C_IMR_BCNDOK2 0x00080000 588 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt 1 */ 589 1.1.2.2 skrll #define R92C_IMR_BCNDOK1 0x00040000 590 1.1.2.2 skrll /*Timeout interrupt 2 */ 591 1.1.2.2 skrll #define R92C_IMR_TIMEOUT2 0x00020000 592 1.1.2.2 skrll /*Timeout interrupt 1 */ 593 1.1.2.2 skrll #define R92C_IMR_TIMEOUT1 0x00010000 594 1.1.2.2 skrll /*Transmit FIFO Overflow */ 595 1.1.2.2 skrll #define R92C_IMR_TXFOVW 0x00008000 596 1.1.2.2 skrll /*Power save time out interrupt */ 597 1.1.2.2 skrll #define R92C_IMR_PSTIMEOUT 0x00004000 598 1.1.2.2 skrll /*Beacon DMA interrupt 0 */ 599 1.1.2.2 skrll #define R92C_IMR_BCNINT 0x00002000 600 1.1.2.2 skrll /*Receive FIFO Overflow */ 601 1.1.2.2 skrll #define R92C_IMR_RXFOVW 0x00001000 602 1.1.2.2 skrll /*Receive Descriptor Unavailable */ 603 1.1.2.2 skrll #define R92C_IMR_RDU 0x00000800 604 1.1.2.2 skrll /*For 92C,ATIM Window End interrupt */ 605 1.1.2.2 skrll #define R92C_IMR_ATIMEND 0x00000400 606 1.1.2.2 skrll /*Beacon Queue DMA OK interrupt */ 607 1.1.2.2 skrll #define R92C_IMR_BDOK 0x00000200 608 1.1.2.2 skrll /*High Queue DMA OK interrupt */ 609 1.1.2.2 skrll #define R92C_IMR_HIGHDOK 0x00000100 610 1.1.2.2 skrll /*Transmit Beacon OK interrupt */ 611 1.1.2.2 skrll #define R92C_IMR_TBDOK 0x00000080 612 1.1.2.2 skrll /*Management Queue DMA OK interrupt */ 613 1.1.2.2 skrll #define R92C_IMR_MGNTDOK 0x00000040 614 1.1.2.2 skrll /*For 92C,Transmit Beacon Error interrupt */ 615 1.1.2.2 skrll #define R92C_IMR_TBDER 0x00000020 616 1.1.2.2 skrll /*AC_BK DMA OK interrupt */ 617 1.1.2.2 skrll #define R92C_IMR_BKDOK 0x00000010 618 1.1.2.2 skrll /*AC_BE DMA OK interrupt */ 619 1.1.2.2 skrll #define R92C_IMR_BEDOK 0x00000008 620 1.1.2.2 skrll /*AC_VI DMA OK interrupt */ 621 1.1.2.2 skrll #define R92C_IMR_VIDOK 0x00000004 622 1.1.2.2 skrll /*AC_VO DMA interrupt */ 623 1.1.2.2 skrll #define R92C_IMR_VODOK 0x00000002 624 1.1.2.2 skrll /*Receive DMA OK interrupt */ 625 1.1.2.2 skrll #define R92C_IMR_ROK 0x00000001 626 1.1.2.2 skrll 627 1.1.2.2 skrll #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 628 1.1.2.2 skrll 629 1.1.2.2 skrll /* 630 1.1.2.2 skrll * Baseband registers. 631 1.1.2.2 skrll */ 632 1.1.2.2 skrll #define R92C_FPGA0_RFMOD 0x800 633 1.1.2.2 skrll #define R92C_FPGA0_TXINFO 0x804 634 1.1.2.2 skrll #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 635 1.1.2.2 skrll #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 636 1.1.2.2 skrll #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 637 1.1.2.2 skrll #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 638 1.1.2.2 skrll #define R92C_TXAGC_A_CCK1_MCS32 0xe08 639 1.1.2.2 skrll #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 640 1.1.2.2 skrll #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 641 1.1.2.2 skrll #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 642 1.1.2.2 skrll #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 643 1.1.2.2 skrll #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 644 1.1.2.2 skrll #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 645 1.1.2.2 skrll #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 646 1.1.2.2 skrll #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 647 1.1.2.2 skrll #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 648 1.1.2.2 skrll #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 649 1.1.2.2 skrll #define R92C_FPGA0_ANAPARAM2 0x884 650 1.1.2.2 skrll #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 651 1.1.2.2 skrll #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 652 1.1.2.2 skrll #define R92C_FPGA1_RFMOD 0x900 653 1.1.2.2 skrll #define R92C_FPGA1_TXINFO 0x90c 654 1.1.2.2 skrll #define R92C_CCK0_SYSTEM 0xa00 655 1.1.2.2 skrll #define R92C_CCK0_AFESETTING 0xa04 656 1.1.2.2 skrll #define R92C_OFDM0_TRXPATHENA 0xc04 657 1.1.2.2 skrll #define R92C_OFDM0_TRMUXPAR 0xc08 658 1.1.2.2 skrll #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 659 1.1.2.2 skrll #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 660 1.1.2.2 skrll #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 661 1.1.2.2 skrll #define R92C_OFDM0_AGCPARAM1 0xc70 662 1.1.2.2 skrll #define R92C_OFDM0_AGCRSSITABLE 0xc78 663 1.1.2.2 skrll #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 664 1.1.2.2 skrll #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 665 1.1.2.2 skrll #define R92C_OFDM0_RXIQEXTANTA 0xca0 666 1.1.2.2 skrll #define R92C_OFDM1_LSTF 0xd00 667 1.1.2.2 skrll 668 1.1.2.2 skrll /* Bits for R92C_FPGA[01]_RFMOD. */ 669 1.1.2.2 skrll #define R92C_RFMOD_40MHZ 0x00000001 670 1.1.2.2 skrll #define R92C_RFMOD_JAPAN 0x00000002 671 1.1.2.2 skrll #define R92C_RFMOD_CCK_TXSC 0x00000030 672 1.1.2.2 skrll #define R92C_RFMOD_CCK_EN 0x01000000 673 1.1.2.2 skrll #define R92C_RFMOD_OFDM_EN 0x02000000 674 1.1.2.2 skrll 675 1.1.2.2 skrll /* Bits for R92C_HSSI_PARAM1(i). */ 676 1.1.2.2 skrll #define R92C_HSSI_PARAM1_PI 0x00000100 677 1.1.2.2 skrll 678 1.1.2.2 skrll /* Bits for R92C_HSSI_PARAM2(i). */ 679 1.1.2.2 skrll #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 680 1.1.2.2 skrll #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 681 1.1.2.2 skrll #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 682 1.1.2.2 skrll #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 683 1.1.2.2 skrll #define R92C_HSSI_PARAM2_READ_ADDR_S 23 684 1.1.2.2 skrll #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 685 1.1.2.2 skrll 686 1.1.2.2 skrll /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 687 1.1.2.2 skrll #define R92C_TXAGC_A_CCK1_M 0x0000ff00 688 1.1.2.2 skrll #define R92C_TXAGC_A_CCK1_S 8 689 1.1.2.2 skrll 690 1.1.2.2 skrll /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 691 1.1.2.2 skrll #define R92C_TXAGC_B_CCK11_M 0x000000ff 692 1.1.2.2 skrll #define R92C_TXAGC_B_CCK11_S 0 693 1.1.2.2 skrll #define R92C_TXAGC_A_CCK2_M 0x0000ff00 694 1.1.2.2 skrll #define R92C_TXAGC_A_CCK2_S 8 695 1.1.2.2 skrll #define R92C_TXAGC_A_CCK55_M 0x00ff0000 696 1.1.2.2 skrll #define R92C_TXAGC_A_CCK55_S 16 697 1.1.2.2 skrll #define R92C_TXAGC_A_CCK11_M 0xff000000 698 1.1.2.2 skrll #define R92C_TXAGC_A_CCK11_S 24 699 1.1.2.2 skrll 700 1.1.2.2 skrll /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 701 1.1.2.2 skrll #define R92C_TXAGC_B_CCK1_M 0x0000ff00 702 1.1.2.2 skrll #define R92C_TXAGC_B_CCK1_S 8 703 1.1.2.2 skrll #define R92C_TXAGC_B_CCK2_M 0x00ff0000 704 1.1.2.2 skrll #define R92C_TXAGC_B_CCK2_S 16 705 1.1.2.2 skrll #define R92C_TXAGC_B_CCK55_M 0xff000000 706 1.1.2.2 skrll #define R92C_TXAGC_B_CCK55_S 24 707 1.1.2.2 skrll 708 1.1.2.2 skrll /* Bits for R92C_TXAGC_RATE18_06(x). */ 709 1.1.2.2 skrll #define R92C_TXAGC_RATE06_M 0x000000ff 710 1.1.2.2 skrll #define R92C_TXAGC_RATE06_S 0 711 1.1.2.2 skrll #define R92C_TXAGC_RATE09_M 0x0000ff00 712 1.1.2.2 skrll #define R92C_TXAGC_RATE09_S 8 713 1.1.2.2 skrll #define R92C_TXAGC_RATE12_M 0x00ff0000 714 1.1.2.2 skrll #define R92C_TXAGC_RATE12_S 16 715 1.1.2.2 skrll #define R92C_TXAGC_RATE18_M 0xff000000 716 1.1.2.2 skrll #define R92C_TXAGC_RATE18_S 24 717 1.1.2.2 skrll 718 1.1.2.2 skrll /* Bits for R92C_TXAGC_RATE54_24(x). */ 719 1.1.2.2 skrll #define R92C_TXAGC_RATE24_M 0x000000ff 720 1.1.2.2 skrll #define R92C_TXAGC_RATE24_S 0 721 1.1.2.2 skrll #define R92C_TXAGC_RATE36_M 0x0000ff00 722 1.1.2.2 skrll #define R92C_TXAGC_RATE36_S 8 723 1.1.2.2 skrll #define R92C_TXAGC_RATE48_M 0x00ff0000 724 1.1.2.2 skrll #define R92C_TXAGC_RATE48_S 16 725 1.1.2.2 skrll #define R92C_TXAGC_RATE54_M 0xff000000 726 1.1.2.2 skrll #define R92C_TXAGC_RATE54_S 24 727 1.1.2.2 skrll 728 1.1.2.2 skrll /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 729 1.1.2.2 skrll #define R92C_TXAGC_MCS00_M 0x000000ff 730 1.1.2.2 skrll #define R92C_TXAGC_MCS00_S 0 731 1.1.2.2 skrll #define R92C_TXAGC_MCS01_M 0x0000ff00 732 1.1.2.2 skrll #define R92C_TXAGC_MCS01_S 8 733 1.1.2.2 skrll #define R92C_TXAGC_MCS02_M 0x00ff0000 734 1.1.2.2 skrll #define R92C_TXAGC_MCS02_S 16 735 1.1.2.2 skrll #define R92C_TXAGC_MCS03_M 0xff000000 736 1.1.2.2 skrll #define R92C_TXAGC_MCS03_S 24 737 1.1.2.2 skrll 738 1.1.2.2 skrll /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 739 1.1.2.2 skrll #define R92C_TXAGC_MCS04_M 0x000000ff 740 1.1.2.2 skrll #define R92C_TXAGC_MCS04_S 0 741 1.1.2.2 skrll #define R92C_TXAGC_MCS05_M 0x0000ff00 742 1.1.2.2 skrll #define R92C_TXAGC_MCS05_S 8 743 1.1.2.2 skrll #define R92C_TXAGC_MCS06_M 0x00ff0000 744 1.1.2.2 skrll #define R92C_TXAGC_MCS06_S 16 745 1.1.2.2 skrll #define R92C_TXAGC_MCS07_M 0xff000000 746 1.1.2.2 skrll #define R92C_TXAGC_MCS07_S 24 747 1.1.2.2 skrll 748 1.1.2.2 skrll /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 749 1.1.2.2 skrll #define R92C_TXAGC_MCS08_M 0x000000ff 750 1.1.2.2 skrll #define R92C_TXAGC_MCS08_S 0 751 1.1.2.2 skrll #define R92C_TXAGC_MCS09_M 0x0000ff00 752 1.1.2.2 skrll #define R92C_TXAGC_MCS09_S 8 753 1.1.2.2 skrll #define R92C_TXAGC_MCS10_M 0x00ff0000 754 1.1.2.2 skrll #define R92C_TXAGC_MCS10_S 16 755 1.1.2.2 skrll #define R92C_TXAGC_MCS11_M 0xff000000 756 1.1.2.2 skrll #define R92C_TXAGC_MCS11_S 24 757 1.1.2.2 skrll 758 1.1.2.2 skrll /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 759 1.1.2.2 skrll #define R92C_TXAGC_MCS12_M 0x000000ff 760 1.1.2.2 skrll #define R92C_TXAGC_MCS12_S 0 761 1.1.2.2 skrll #define R92C_TXAGC_MCS13_M 0x0000ff00 762 1.1.2.2 skrll #define R92C_TXAGC_MCS13_S 8 763 1.1.2.2 skrll #define R92C_TXAGC_MCS14_M 0x00ff0000 764 1.1.2.2 skrll #define R92C_TXAGC_MCS14_S 16 765 1.1.2.2 skrll #define R92C_TXAGC_MCS15_M 0xff000000 766 1.1.2.2 skrll #define R92C_TXAGC_MCS15_S 24 767 1.1.2.2 skrll 768 1.1.2.2 skrll /* Bits for R92C_LSSI_PARAM(i). */ 769 1.1.2.2 skrll #define R92C_LSSI_PARAM_DATA_M 0x000fffff 770 1.1.2.2 skrll #define R92C_LSSI_PARAM_DATA_S 0 771 1.1.2.2 skrll #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 772 1.1.2.2 skrll #define R92C_LSSI_PARAM_ADDR_S 20 773 1.1.2.2 skrll 774 1.1.2.2 skrll /* Bits for R92C_FPGA0_ANAPARAM2. */ 775 1.1.2.2 skrll #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 776 1.1.2.2 skrll 777 1.1.2.2 skrll /* Bits for R92C_LSSI_READBACK(i). */ 778 1.1.2.2 skrll #define R92C_LSSI_READBACK_DATA_M 0x000fffff 779 1.1.2.2 skrll #define R92C_LSSI_READBACK_DATA_S 0 780 1.1.2.2 skrll 781 1.1.2.2 skrll /* Bits for R92C_OFDM0_AGCCORE1(i). */ 782 1.1.2.2 skrll #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 783 1.1.2.2 skrll #define R92C_OFDM0_AGCCORE1_GAIN_S 0 784 1.1.2.2 skrll 785 1.1.2.2 skrll 786 1.1.2.2 skrll /* 787 1.1.2.2 skrll * USB registers. 788 1.1.2.2 skrll */ 789 1.1.2.2 skrll #define R92C_USB_INFO 0xfe17 790 1.1.2.2 skrll #define R92C_USB_SPECIAL_OPTION 0xfe55 791 1.1.2.2 skrll #define R92C_USB_HCPWM 0xfe57 792 1.1.2.2 skrll #define R92C_USB_HRPWM 0xfe58 793 1.1.2.2 skrll #define R92C_USB_DMA_AGG_TO 0xfe5b 794 1.1.2.2 skrll #define R92C_USB_AGG_TO 0xfe5c 795 1.1.2.2 skrll #define R92C_USB_AGG_TH 0xfe5d 796 1.1.2.2 skrll #define R92C_USB_VID 0xfe60 797 1.1.2.2 skrll #define R92C_USB_PID 0xfe62 798 1.1.2.2 skrll #define R92C_USB_OPTIONAL 0xfe64 799 1.1.2.2 skrll #define R92C_USB_EP 0xfe65 800 1.1.2.2 skrll #define R92C_USB_PHY 0xfe68 801 1.1.2.2 skrll #define R92C_USB_MAC_ADDR 0xfe70 802 1.1.2.2 skrll #define R92C_USB_STRING 0xfe80 803 1.1.2.2 skrll 804 1.1.2.2 skrll /* Bits for R92C_USB_SPECIAL_OPTION. */ 805 1.1.2.2 skrll #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 806 1.1.2.2 skrll 807 1.1.2.2 skrll /* Bits for R92C_USB_EP. */ 808 1.1.2.2 skrll #define R92C_USB_EP_HQ_M 0x000f 809 1.1.2.2 skrll #define R92C_USB_EP_HQ_S 0 810 1.1.2.2 skrll #define R92C_USB_EP_NQ_M 0x00f0 811 1.1.2.2 skrll #define R92C_USB_EP_NQ_S 4 812 1.1.2.2 skrll #define R92C_USB_EP_LQ_M 0x0f00 813 1.1.2.2 skrll #define R92C_USB_EP_LQ_S 8 814 1.1.2.2 skrll 815 1.1.2.2 skrll 816 1.1.2.2 skrll /* 817 1.1.2.2 skrll * Firmware base address. 818 1.1.2.2 skrll */ 819 1.1.2.2 skrll #define R92C_FW_START_ADDR 0x1000 820 1.1.2.2 skrll #define R92C_FW_PAGE_SIZE 4096 821 1.1.2.2 skrll 822 1.1.2.2 skrll 823 1.1.2.2 skrll /* 824 1.1.2.2 skrll * RF (6052) registers. 825 1.1.2.2 skrll */ 826 1.1.2.2 skrll #define R92C_RF_AC 0x00 827 1.1.2.2 skrll #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 828 1.1.2.2 skrll #define R92C_RF_POW_TRSW 0x05 829 1.1.2.2 skrll #define R92C_RF_GAIN_RX 0x06 830 1.1.2.2 skrll #define R92C_RF_GAIN_TX 0x07 831 1.1.2.2 skrll #define R92C_RF_TXM_IDAC 0x08 832 1.1.2.2 skrll #define R92C_RF_BS_IQGEN 0x0f 833 1.1.2.2 skrll #define R92C_RF_MODE1 0x10 834 1.1.2.2 skrll #define R92C_RF_MODE2 0x11 835 1.1.2.2 skrll #define R92C_RF_RX_AGC_HP 0x12 836 1.1.2.2 skrll #define R92C_RF_TX_AGC 0x13 837 1.1.2.2 skrll #define R92C_RF_BIAS 0x14 838 1.1.2.2 skrll #define R92C_RF_IPA 0x15 839 1.1.2.2 skrll #define R92C_RF_POW_ABILITY 0x17 840 1.1.2.2 skrll #define R92C_RF_CHNLBW 0x18 841 1.1.2.2 skrll #define R92C_RF_RX_G1 0x1a 842 1.1.2.2 skrll #define R92C_RF_RX_G2 0x1b 843 1.1.2.2 skrll #define R92C_RF_RX_BB2 0x1c 844 1.1.2.2 skrll #define R92C_RF_RX_BB1 0x1d 845 1.1.2.2 skrll #define R92C_RF_RCK1 0x1e 846 1.1.2.2 skrll #define R92C_RF_RCK2 0x1f 847 1.1.2.2 skrll #define R92C_RF_TX_G(i) (0x20 + (i)) 848 1.1.2.2 skrll #define R92C_RF_TX_BB1 0x23 849 1.1.2.2 skrll #define R92C_RF_T_METER 0x24 850 1.1.2.2 skrll #define R92C_RF_SYN_G(i) (0x25 + (i)) 851 1.1.2.2 skrll #define R92C_RF_RCK_OS 0x30 852 1.1.2.2 skrll #define R92C_RF_TXPA_G(i) (0x31 + (i)) 853 1.1.2.2 skrll 854 1.1.2.2 skrll /* Bits for R92C_RF_AC. */ 855 1.1.2.2 skrll #define R92C_RF_AC_MODE_M 0x70000 856 1.1.2.2 skrll #define R92C_RF_AC_MODE_S 16 857 1.1.2.2 skrll #define R92C_RF_AC_MODE_STANDBY 1 858 1.1.2.2 skrll 859 1.1.2.2 skrll /* Bits for R92C_RF_CHNLBW. */ 860 1.1.2.2 skrll #define R92C_RF_CHNLBW_CHNL_M 0x003ff 861 1.1.2.2 skrll #define R92C_RF_CHNLBW_CHNL_S 0 862 1.1.2.2 skrll #define R92C_RF_CHNLBW_BW20 0x00400 863 1.1.2.2 skrll #define R92C_RF_CHNLBW_LCSTART 0x08000 864 1.1.2.2 skrll 865 1.1.2.2 skrll 866 1.1.2.2 skrll /* 867 1.1.2.2 skrll * CAM entries. 868 1.1.2.2 skrll */ 869 1.1.2.2 skrll #define R92C_CAM_ENTRY_COUNT 32 870 1.1.2.2 skrll 871 1.1.2.2 skrll #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 872 1.1.2.2 skrll #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 873 1.1.2.2 skrll #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 874 1.1.2.2 skrll 875 1.1.2.2 skrll /* Bits for R92C_CAM_CTL0(i). */ 876 1.1.2.2 skrll #define R92C_CAM_KEYID_M 0x00000003 877 1.1.2.2 skrll #define R92C_CAM_KEYID_S 0 878 1.1.2.2 skrll #define R92C_CAM_ALGO_M 0x0000001c 879 1.1.2.2 skrll #define R92C_CAM_ALGO_S 2 880 1.1.2.2 skrll #define R92C_CAM_ALGO_NONE 0 881 1.1.2.2 skrll #define R92C_CAM_ALGO_WEP40 1 882 1.1.2.2 skrll #define R92C_CAM_ALGO_TKIP 2 883 1.1.2.2 skrll #define R92C_CAM_ALGO_AES 4 884 1.1.2.2 skrll #define R92C_CAM_ALGO_WEP104 5 885 1.1.2.2 skrll #define R92C_CAM_VALID 0x00008000 886 1.1.2.2 skrll #define R92C_CAM_MACLO_M 0xffff0000 887 1.1.2.2 skrll #define R92C_CAM_MACLO_S 16 888 1.1.2.2 skrll 889 1.1.2.2 skrll /* Rate adaptation modes. */ 890 1.1.2.2 skrll #define R92C_RAID_11GN 1 891 1.1.2.2 skrll #define R92C_RAID_11N 3 892 1.1.2.2 skrll #define R92C_RAID_11BG 4 893 1.1.2.2 skrll #define R92C_RAID_11G 5 /* "pure" 11g */ 894 1.1.2.2 skrll #define R92C_RAID_11B 6 895 1.1.2.2 skrll 896 1.1.2.2 skrll 897 1.1.2.2 skrll /* Macros to access unaligned little-endian memory. */ 898 1.1.2.2 skrll #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 899 1.1.2.2 skrll #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 900 1.1.2.2 skrll 901 1.1.2.2 skrll /* 902 1.1.2.2 skrll * Macros to access subfields in registers. 903 1.1.2.2 skrll */ 904 1.1.2.2 skrll /* Mask and Shift (getter). */ 905 1.1.2.2 skrll #define MS(val, field) \ 906 1.1.2.2 skrll (((val) & field##_M) >> field##_S) 907 1.1.2.2 skrll 908 1.1.2.2 skrll /* Shift and Mask (setter). */ 909 1.1.2.2 skrll #define SM(field, val) \ 910 1.1.2.2 skrll (((val) << field##_S) & field##_M) 911 1.1.2.2 skrll 912 1.1.2.2 skrll /* Rewrite. */ 913 1.1.2.2 skrll #define RW(var, field, val) \ 914 1.1.2.2 skrll (((var) & ~field##_M) | SM(field, val)) 915 1.1.2.2 skrll 916 1.1.2.2 skrll /* 917 1.1.2.2 skrll * Firmware image header. 918 1.1.2.2 skrll */ 919 1.1.2.2 skrll struct r92c_fw_hdr { 920 1.1.2.2 skrll /* QWORD0 */ 921 1.1.2.2 skrll uint16_t signature; 922 1.1.2.2 skrll uint8_t category; 923 1.1.2.2 skrll uint8_t function; 924 1.1.2.2 skrll uint16_t version; 925 1.1.2.2 skrll uint16_t subversion; 926 1.1.2.2 skrll /* QWORD1 */ 927 1.1.2.2 skrll uint8_t month; 928 1.1.2.2 skrll uint8_t date; 929 1.1.2.2 skrll uint8_t hour; 930 1.1.2.2 skrll uint8_t minute; 931 1.1.2.2 skrll uint16_t ramcodesize; 932 1.1.2.2 skrll uint16_t reserved2; 933 1.1.2.2 skrll /* QWORD2 */ 934 1.1.2.2 skrll uint32_t svnidx; 935 1.1.2.2 skrll uint32_t reserved3; 936 1.1.2.2 skrll /* QWORD3 */ 937 1.1.2.2 skrll uint32_t reserved4; 938 1.1.2.2 skrll uint32_t reserved5; 939 1.1.2.2 skrll } __packed; 940 1.1.2.2 skrll 941 1.1.2.2 skrll /* 942 1.1.2.2 skrll * Host to firmware commands. 943 1.1.2.2 skrll */ 944 1.1.2.2 skrll struct r92c_fw_cmd { 945 1.1.2.2 skrll uint8_t id; 946 1.1.2.2 skrll #define R92C_CMD_AP_OFFLOAD 0 947 1.1.2.2 skrll #define R92C_CMD_SET_PWRMODE 1 948 1.1.2.2 skrll #define R92C_CMD_JOINBSS_RPT 2 949 1.1.2.2 skrll #define R92C_CMD_RSVD_PAGE 3 950 1.1.2.2 skrll #define R92C_CMD_RSSI 4 951 1.1.2.2 skrll #define R92C_CMD_RSSI_SETTING 5 952 1.1.2.2 skrll #define R92C_CMD_MACID_CONFIG 6 953 1.1.2.2 skrll #define R92C_CMD_MACID_PS_MODE 7 954 1.1.2.2 skrll #define R92C_CMD_P2P_PS_OFFLOAD 8 955 1.1.2.2 skrll #define R92C_CMD_SELECTIVE_SUSPEND 9 956 1.1.2.2 skrll #define R92C_CMD_FLAG_EXT 0x80 957 1.1.2.2 skrll 958 1.1.2.2 skrll uint8_t msg[5]; 959 1.1.2.2 skrll } __packed; 960 1.1.2.2 skrll 961 1.1.2.2 skrll /* Structure for R92C_CMD_RSSI_SETTING. */ 962 1.1.2.2 skrll struct r92c_fw_cmd_rssi { 963 1.1.2.2 skrll uint8_t macid; 964 1.1.2.2 skrll uint8_t reserved; 965 1.1.2.2 skrll uint8_t pwdb; 966 1.1.2.2 skrll } __packed; 967 1.1.2.2 skrll 968 1.1.2.2 skrll /* Structure for R92C_CMD_MACID_CONFIG. */ 969 1.1.2.2 skrll struct r92c_fw_cmd_macid_cfg { 970 1.1.2.2 skrll uint32_t mask; 971 1.1.2.2 skrll uint8_t macid; 972 1.1.2.2 skrll #define RTWN_MACID_BSS 0 973 1.1.2.2 skrll #define RTWN_MACID_BC 4 /* Broadcast. */ 974 1.1.2.2 skrll #define RTWN_MACID_VALID 0x80 975 1.1.2.2 skrll } __packed; 976 1.1.2.2 skrll 977 1.1.2.2 skrll /* 978 1.1.2.2 skrll * RTL8192CU ROM image. 979 1.1.2.2 skrll */ 980 1.1.2.2 skrll struct r92c_rom { 981 1.1.2.2 skrll uint16_t id; /* 0x8129 */ 982 1.1.2.2 skrll uint8_t reserved1[5]; 983 1.1.2.2 skrll uint8_t dbg_sel; 984 1.1.2.2 skrll uint16_t reserved2; 985 1.1.2.2 skrll uint16_t vid; 986 1.1.2.2 skrll uint16_t pid; 987 1.1.2.2 skrll uint8_t usb_opt; 988 1.1.2.2 skrll uint8_t ep_setting; 989 1.1.2.2 skrll uint16_t reserved3; 990 1.1.2.2 skrll uint8_t usb_phy; 991 1.1.2.2 skrll uint8_t reserved4[3]; 992 1.1.2.2 skrll uint8_t macaddr[6]; 993 1.1.2.2 skrll uint8_t string[61]; /* "Realtek" */ 994 1.1.2.2 skrll uint8_t subcustomer_id; 995 1.1.2.2 skrll uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 996 1.1.2.2 skrll uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 997 1.1.2.2 skrll uint8_t ht40_2s_tx_pwr_diff[3]; 998 1.1.2.2 skrll uint8_t ht20_tx_pwr_diff[3]; 999 1.1.2.2 skrll uint8_t ofdm_tx_pwr_diff[3]; 1000 1.1.2.2 skrll uint8_t ht40_max_pwr[3]; 1001 1.1.2.2 skrll uint8_t ht20_max_pwr[3]; 1002 1.1.2.2 skrll uint8_t xtal_calib; 1003 1.1.2.2 skrll uint8_t tssi[R92C_MAX_CHAINS]; 1004 1.1.2.2 skrll uint8_t thermal_meter; 1005 1.1.2.2 skrll uint8_t rf_opt1; 1006 1.1.2.2 skrll #define R92C_ROM_RF1_REGULATORY_M 0x07 1007 1.1.2.2 skrll #define R92C_ROM_RF1_REGULATORY_S 0 1008 1.1.2.2 skrll #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1009 1.1.2.2 skrll #define R92C_ROM_RF1_BOARD_TYPE_S 5 1010 1.1.2.2 skrll #define R92C_BOARD_TYPE_DONGLE 0 1011 1.1.2.2 skrll #define R92C_BOARD_TYPE_HIGHPA 1 1012 1.1.2.2 skrll #define R92C_BOARD_TYPE_MINICARD 2 1013 1.1.2.2 skrll #define R92C_BOARD_TYPE_SOLO 3 1014 1.1.2.2 skrll #define R92C_BOARD_TYPE_COMBO 4 1015 1.1.2.2 skrll 1016 1.1.2.2 skrll uint8_t rf_opt2; 1017 1.1.2.2 skrll uint8_t rf_opt3; 1018 1.1.2.2 skrll uint8_t rf_opt4; 1019 1.1.2.2 skrll uint8_t channel_plan; 1020 1.1.2.2 skrll uint8_t version; 1021 1.1.2.2 skrll uint8_t curstomer_id; 1022 1.1.2.2 skrll } __packed; 1023 1.1.2.2 skrll 1024 1.1.2.2 skrll /* Rx MAC descriptor. */ 1025 1.1.2.2 skrll struct r92c_rx_desc { 1026 1.1.2.2 skrll uint32_t rxdw0; 1027 1.1.2.2 skrll #define R92C_RXDW0_PKTLEN_M 0x00003fff 1028 1.1.2.2 skrll #define R92C_RXDW0_PKTLEN_S 0 1029 1.1.2.2 skrll #define R92C_RXDW0_CRCERR 0x00004000 1030 1.1.2.2 skrll #define R92C_RXDW0_ICVERR 0x00008000 1031 1.1.2.2 skrll #define R92C_RXDW0_INFOSZ_M 0x000f0000 1032 1.1.2.2 skrll #define R92C_RXDW0_INFOSZ_S 16 1033 1.1.2.2 skrll #define R92C_RXDW0_QOS 0x00800000 1034 1.1.2.2 skrll #define R92C_RXDW0_SHIFT_M 0x03000000 1035 1.1.2.2 skrll #define R92C_RXDW0_SHIFT_S 24 1036 1.1.2.2 skrll #define R92C_RXDW0_PHYST 0x04000000 1037 1.1.2.2 skrll #define R92C_RXDW0_DECRYPTED 0x08000000 1038 1.1.2.2 skrll #define R92C_RXDW0_LS 0x10000000 1039 1.1.2.2 skrll #define R92C_RXDW0_FS 0x20000000 1040 1.1.2.2 skrll #define R92C_RXDW0_EOR 0x40000000 1041 1.1.2.2 skrll #define R92C_RXDW0_OWN 0x80000000 1042 1.1.2.2 skrll 1043 1.1.2.2 skrll uint32_t rxdw1; 1044 1.1.2.2 skrll uint32_t rxdw2; 1045 1.1.2.2 skrll #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1046 1.1.2.2 skrll #define R92C_RXDW2_PKTCNT_S 16 1047 1.1.2.2 skrll 1048 1.1.2.2 skrll uint32_t rxdw3; 1049 1.1.2.2 skrll #define R92C_RXDW3_RATE_M 0x0000003f 1050 1.1.2.2 skrll #define R92C_RXDW3_RATE_S 0 1051 1.1.2.2 skrll #define R92C_RXDW3_HT 0x00000040 1052 1.1.2.2 skrll #define R92C_RXDW3_HTC 0x00000400 1053 1.1.2.2 skrll 1054 1.1.2.2 skrll uint32_t rxdw4; 1055 1.1.2.2 skrll uint32_t rxdw5; 1056 1.1.2.2 skrll 1057 1.1.2.2 skrll uint32_t rxbufaddr; 1058 1.1.2.2 skrll uint32_t rxbufaddr64; 1059 1.1.2.2 skrll } __packed __attribute__((aligned(4))); 1060 1.1.2.2 skrll 1061 1.1.2.2 skrll /* Rx PHY descriptor. */ 1062 1.1.2.2 skrll struct r92c_rx_phystat { 1063 1.1.2.2 skrll uint32_t phydw0; 1064 1.1.2.2 skrll uint32_t phydw1; 1065 1.1.2.2 skrll uint32_t phydw2; 1066 1.1.2.2 skrll uint32_t phydw3; 1067 1.1.2.2 skrll uint32_t phydw4; 1068 1.1.2.2 skrll uint32_t phydw5; 1069 1.1.2.2 skrll uint32_t phydw6; 1070 1.1.2.2 skrll uint32_t phydw7; 1071 1.1.2.2 skrll } __packed __attribute__((aligned(4))); 1072 1.1.2.2 skrll 1073 1.1.2.2 skrll /* Rx PHY CCK descriptor. */ 1074 1.1.2.2 skrll struct r92c_rx_cck { 1075 1.1.2.2 skrll uint8_t adc_pwdb[4]; 1076 1.1.2.2 skrll uint8_t sq_rpt; 1077 1.1.2.2 skrll uint8_t agc_rpt; 1078 1.1.2.2 skrll } __packed; 1079 1.1.2.2 skrll 1080 1.1.2.2 skrll /* Tx MAC descriptor. */ 1081 1.1.2.2 skrll struct r92c_tx_desc { 1082 1.1.2.2 skrll uint32_t txdw0; 1083 1.1.2.2 skrll #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1084 1.1.2.2 skrll #define R92C_TXDW0_PKTLEN_S 0 1085 1.1.2.2 skrll #define R92C_TXDW0_OFFSET_M 0x00ff0000 1086 1.1.2.2 skrll #define R92C_TXDW0_OFFSET_S 16 1087 1.1.2.2 skrll #define R92C_TXDW0_BMCAST 0x01000000 1088 1.1.2.2 skrll #define R92C_TXDW0_LSG 0x04000000 1089 1.1.2.2 skrll #define R92C_TXDW0_FSG 0x08000000 1090 1.1.2.2 skrll #define R92C_TXDW0_OWN 0x80000000 1091 1.1.2.2 skrll 1092 1.1.2.2 skrll uint32_t txdw1; 1093 1.1.2.2 skrll #define R92C_TXDW1_MACID_M 0x0000001f 1094 1.1.2.2 skrll #define R92C_TXDW1_MACID_S 0 1095 1.1.2.2 skrll #define R92C_TXDW1_AGGEN 0x00000020 1096 1.1.2.2 skrll #define R92C_TXDW1_AGGBK 0x00000040 1097 1.1.2.2 skrll #define R92C_TXDW1_QSEL_M 0x00001f00 1098 1.1.2.2 skrll #define R92C_TXDW1_QSEL_S 8 1099 1.1.2.2 skrll #define R92C_TXDW1_QSEL_BE 0x00 1100 1.1.2.2 skrll #define R92C_TXDW1_QSEL_BK 0x02 1101 1.1.2.2 skrll #define R92C_TXDW1_QSEL_VI 0x05 1102 1.1.2.2 skrll #define R92C_TXDW1_QSEL_VO 0x07 1103 1.1.2.2 skrll #define R92C_TXDW1_QSEL_BEACON 0x10 1104 1.1.2.2 skrll #define R92C_TXDW1_QSEL_HIGH 0x11 1105 1.1.2.2 skrll #define R92C_TXDW1_QSEL_MGNT 0x12 1106 1.1.2.2 skrll #define R92C_TXDW1_QSEL_CMD 0x13 1107 1.1.2.2 skrll #define R92C_TXDW1_RAID_M 0x000f0000 1108 1.1.2.2 skrll #define R92C_TXDW1_RAID_S 16 1109 1.1.2.2 skrll #define R92C_TXDW1_CIPHER_M 0x00c00000 1110 1.1.2.2 skrll #define R92C_TXDW1_CIPHER_S 22 1111 1.1.2.2 skrll #define R92C_TXDW1_CIPHER_NONE 0 1112 1.1.2.2 skrll #define R92C_TXDW1_CIPHER_RC4 1 1113 1.1.2.2 skrll #define R92C_TXDW1_CIPHER_AES 3 1114 1.1.2.2 skrll #define R92C_TXDW1_PKTOFF_M 0x7c000000 1115 1.1.2.2 skrll #define R92C_TXDW1_PKTOFF_S 26 1116 1.1.2.2 skrll 1117 1.1.2.2 skrll uint32_t txdw2; 1118 1.1.2.2 skrll uint16_t txdw3; 1119 1.1.2.2 skrll uint16_t txdseq; 1120 1.1.2.2 skrll 1121 1.1.2.2 skrll uint32_t txdw4; 1122 1.1.2.2 skrll #define R92C_TXDW4_RTSRATE_M 0x0000003f 1123 1.1.2.2 skrll #define R92C_TXDW4_RTSRATE_S 0 1124 1.1.2.2 skrll #define R92C_TXDW4_QOS 0x00000040 1125 1.1.2.2 skrll #define R92C_TXDW4_HWSEQ 0x00000080 1126 1.1.2.2 skrll #define R92C_TXDW4_DRVRATE 0x00000100 1127 1.1.2.2 skrll #define R92C_TXDW4_CTS2SELF 0x00000800 1128 1.1.2.2 skrll #define R92C_TXDW4_RTSEN 0x00001000 1129 1.1.2.2 skrll #define R92C_TXDW4_HWRTSEN 0x00002000 1130 1.1.2.2 skrll #define R92C_TXDW4_SCO_M 0x003f0000 1131 1.1.2.2 skrll #define R92C_TXDW4_SCO_S 20 1132 1.1.2.2 skrll #define R92C_TXDW4_SCO_SCA 1 1133 1.1.2.2 skrll #define R92C_TXDW4_SCO_SCB 2 1134 1.1.2.2 skrll #define R92C_TXDW4_40MHZ 0x02000000 1135 1.1.2.2 skrll 1136 1.1.2.2 skrll uint32_t txdw5; 1137 1.1.2.2 skrll #define R92C_TXDW5_DATARATE_M 0x0000003f 1138 1.1.2.2 skrll #define R92C_TXDW5_DATARATE_S 0 1139 1.1.2.2 skrll #define R92C_TXDW5_SGI 0x00000040 1140 1.1.2.2 skrll #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1141 1.1.2.2 skrll #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1142 1.1.2.2 skrll #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1143 1.1.2.2 skrll #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1144 1.1.2.2 skrll #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1145 1.1.2.2 skrll #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1146 1.1.2.2 skrll #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1147 1.1.2.2 skrll #define R92C_TXDW5_AGGNUM_M 0xff000000 1148 1.1.2.2 skrll #define R92C_TXDW5_AGGNUM_S 24 1149 1.1.2.2 skrll 1150 1.1.2.2 skrll uint32_t txdw6; 1151 1.1.2.2 skrll 1152 1.1.2.2 skrll uint16_t txbufsize; 1153 1.1.2.2 skrll uint16_t pad; 1154 1.1.2.2 skrll 1155 1.1.2.2 skrll uint32_t txbufaddr; 1156 1.1.2.2 skrll uint32_t txbufaddr64; 1157 1.1.2.2 skrll 1158 1.1.2.2 skrll uint32_t nextdescaddr; 1159 1.1.2.2 skrll uint32_t nextdescaddr64; 1160 1.1.2.2 skrll 1161 1.1.2.2 skrll uint32_t reserved[4]; 1162 1.1.2.2 skrll } __packed __attribute__((aligned(4))); 1163 1.1.2.2 skrll 1164 1.1.2.2 skrll 1165 1.1.2.2 skrll /* 1166 1.1.2.2 skrll * Driver definitions. 1167 1.1.2.2 skrll */ 1168 1.1.2.2 skrll #define RTWN_NTXQUEUES 9 1169 1.1.2.2 skrll #define RTWN_RX_LIST_COUNT 256 1170 1.1.2.2 skrll #define RTWN_TX_LIST_COUNT 256 1171 1.1.2.2 skrll #define RTWN_HOST_CMD_RING_COUNT 32 1172 1.1.2.2 skrll 1173 1.1.2.2 skrll /* TX queue indices. */ 1174 1.1.2.2 skrll #define RTWN_BK_QUEUE 0 1175 1.1.2.2 skrll #define RTWN_BE_QUEUE 1 1176 1.1.2.2 skrll #define RTWN_VI_QUEUE 2 1177 1.1.2.2 skrll #define RTWN_VO_QUEUE 3 1178 1.1.2.2 skrll #define RTWN_BEACON_QUEUE 4 1179 1.1.2.2 skrll #define RTWN_TXCMD_QUEUE 5 1180 1.1.2.2 skrll #define RTWN_MGNT_QUEUE 6 1181 1.1.2.2 skrll #define RTWN_HIGH_QUEUE 7 1182 1.1.2.2 skrll #define RTWN_HCCA_QUEUE 8 1183 1.1.2.2 skrll 1184 1.1.2.2 skrll /* RX queue indices. */ 1185 1.1.2.2 skrll #define RTWN_RX_QUEUE 0 1186 1.1.2.2 skrll 1187 1.1.2.2 skrll #define RTWN_RXBUFSZ (16 * 1024) 1188 1.1.2.2 skrll #define RTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) 1189 1.1.2.2 skrll 1190 1.1.2.2 skrll #define RTWN_RIDX_COUNT 28 1191 1.1.2.2 skrll 1192 1.1.2.2 skrll #define RTWN_TX_TIMEOUT 5000 /* ms */ 1193 1.1.2.2 skrll 1194 1.1.2.2 skrll #define RTWN_LED_LINK 0 1195 1.1.2.2 skrll #define RTWN_LED_DATA 1 1196 1.1.2.2 skrll 1197 1.1.2.2 skrll struct rtwn_rx_radiotap_header { 1198 1.1.2.2 skrll struct ieee80211_radiotap_header wr_ihdr; 1199 1.1.2.2 skrll uint8_t wr_flags; 1200 1.1.2.2 skrll uint8_t wr_rate; 1201 1.1.2.2 skrll uint16_t wr_chan_freq; 1202 1.1.2.2 skrll uint16_t wr_chan_flags; 1203 1.1.2.2 skrll uint8_t wr_dbm_antsignal; 1204 1.1.2.2 skrll } __packed; 1205 1.1.2.2 skrll 1206 1.1.2.2 skrll #define RTWN_RX_RADIOTAP_PRESENT \ 1207 1.1.2.2 skrll (1 << IEEE80211_RADIOTAP_FLAGS | \ 1208 1.1.2.2 skrll 1 << IEEE80211_RADIOTAP_RATE | \ 1209 1.1.2.2 skrll 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1210 1.1.2.2 skrll 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 1211 1.1.2.2 skrll 1212 1.1.2.2 skrll struct rtwn_tx_radiotap_header { 1213 1.1.2.2 skrll struct ieee80211_radiotap_header wt_ihdr; 1214 1.1.2.2 skrll uint8_t wt_flags; 1215 1.1.2.2 skrll uint16_t wt_chan_freq; 1216 1.1.2.2 skrll uint16_t wt_chan_flags; 1217 1.1.2.2 skrll } __packed; 1218 1.1.2.2 skrll 1219 1.1.2.2 skrll #define RTWN_TX_RADIOTAP_PRESENT \ 1220 1.1.2.2 skrll (1 << IEEE80211_RADIOTAP_FLAGS | \ 1221 1.1.2.2 skrll 1 << IEEE80211_RADIOTAP_CHANNEL) 1222 1.1.2.2 skrll 1223 1.1.2.2 skrll struct rtwn_softc; 1224 1.1.2.2 skrll 1225 1.1.2.2 skrll struct rtwn_rx_data { 1226 1.1.2.2 skrll bus_dmamap_t map; 1227 1.1.2.2 skrll struct mbuf *m; 1228 1.1.2.2 skrll }; 1229 1.1.2.2 skrll 1230 1.1.2.2 skrll struct rtwn_rx_ring { 1231 1.1.2.2 skrll struct r92c_rx_desc *desc; 1232 1.1.2.2 skrll bus_dmamap_t map; 1233 1.1.2.2 skrll bus_dma_segment_t seg; 1234 1.1.2.2 skrll int nsegs; 1235 1.1.2.2 skrll struct rtwn_rx_data rx_data[RTWN_RX_LIST_COUNT]; 1236 1.1.2.2 skrll 1237 1.1.2.2 skrll }; 1238 1.1.2.2 skrll struct rtwn_tx_data { 1239 1.1.2.2 skrll bus_dmamap_t map; 1240 1.1.2.2 skrll struct mbuf *m; 1241 1.1.2.2 skrll struct ieee80211_node *ni; 1242 1.1.2.2 skrll }; 1243 1.1.2.2 skrll 1244 1.1.2.2 skrll struct rtwn_tx_ring { 1245 1.1.2.2 skrll bus_dmamap_t map; 1246 1.1.2.2 skrll bus_dma_segment_t seg; 1247 1.1.2.2 skrll int nsegs; 1248 1.1.2.2 skrll struct r92c_tx_desc *desc; 1249 1.1.2.2 skrll struct rtwn_tx_data tx_data[RTWN_TX_LIST_COUNT]; 1250 1.1.2.2 skrll int queued; 1251 1.1.2.2 skrll int cur; 1252 1.1.2.2 skrll }; 1253 1.1.2.2 skrll 1254 1.1.2.2 skrll struct rtwn_host_cmd { 1255 1.1.2.2 skrll void (*cb)(struct rtwn_softc *, void *); 1256 1.1.2.2 skrll uint8_t data[256]; 1257 1.1.2.2 skrll }; 1258 1.1.2.2 skrll 1259 1.1.2.2 skrll struct rtwn_cmd_key { 1260 1.1.2.2 skrll struct ieee80211_key key; 1261 1.1.2.2 skrll uint16_t associd; 1262 1.1.2.2 skrll }; 1263 1.1.2.2 skrll 1264 1.1.2.2 skrll struct rtwn_host_cmd_ring { 1265 1.1.2.2 skrll struct rtwn_host_cmd cmd[RTWN_HOST_CMD_RING_COUNT]; 1266 1.1.2.2 skrll int cur; 1267 1.1.2.2 skrll int next; 1268 1.1.2.2 skrll int queued; 1269 1.1.2.2 skrll }; 1270 1.1.2.2 skrll 1271 1.1.2.2 skrll struct rtwn_softc { 1272 1.1.2.2 skrll device_t sc_dev; 1273 1.1.2.2 skrll struct ethercom sc_ec; 1274 1.1.2.2 skrll struct ieee80211com sc_ic; 1275 1.1.2.2 skrll int (*sc_newstate)(struct ieee80211com *, 1276 1.1.2.2 skrll enum ieee80211_state, int); 1277 1.1.2.2 skrll 1278 1.1.2.2 skrll /* PCI specific goo. */ 1279 1.1.2.2 skrll bus_dma_tag_t sc_dmat; 1280 1.1.2.2 skrll pci_chipset_tag_t sc_pc; 1281 1.1.2.2 skrll pcitag_t sc_tag; 1282 1.1.2.2 skrll void *sc_ih; 1283 1.1.2.2 skrll #ifdef __HAVE_PCI_MSI_MSIX 1284 1.1.2.2 skrll pci_intr_handle_t *sc_pihp; 1285 1.1.2.2 skrll #endif 1286 1.1.2.2 skrll bus_space_tag_t sc_st; 1287 1.1.2.2 skrll bus_space_handle_t sc_sh; 1288 1.1.2.2 skrll bus_size_t sc_mapsize; 1289 1.1.2.2 skrll int sc_cap_off; 1290 1.1.2.2 skrll 1291 1.1.2.2 skrll 1292 1.1.2.2 skrll struct callout scan_to; 1293 1.1.2.2 skrll struct callout calib_to; 1294 1.1.2.2 skrll void *init_task; 1295 1.1.2.2 skrll int ac2idx[WME_NUM_AC]; 1296 1.1.2.2 skrll uint32_t sc_flags; 1297 1.1.2.2 skrll #define RTWN_FLAG_FW_LOADED __BIT(0) 1298 1.1.2.2 skrll #define RTWN_FLAG_CCK_HIPWR __BIT(1) 1299 1.1.2.2 skrll 1300 1.1.2.2 skrll uint32_t chip; 1301 1.1.2.2 skrll #define RTWN_CHIP_88C __BIT(0) 1302 1.1.2.2 skrll #define RTWN_CHIP_92C __BIT(1) 1303 1.1.2.2 skrll #define RTWN_CHIP_92C_1T2R __BIT(2) 1304 1.1.2.2 skrll #define RTWN_CHIP_UMC __BIT(3) 1305 1.1.2.2 skrll #define RTWN_CHIP_UMC_A_CUT __BIT(4) 1306 1.1.2.2 skrll #define RTWN_CHIP_UMC_B_CUT __BIT(5) 1307 1.1.2.2 skrll 1308 1.1.2.2 skrll uint8_t board_type; 1309 1.1.2.2 skrll uint8_t regulatory; 1310 1.1.2.2 skrll uint8_t pa_setting; 1311 1.1.2.2 skrll int avg_pwdb; 1312 1.1.2.2 skrll int thcal_state; 1313 1.1.2.2 skrll int thcal_lctemp; 1314 1.1.2.2 skrll int ntxchains; 1315 1.1.2.2 skrll int nrxchains; 1316 1.1.2.2 skrll int ledlink; 1317 1.1.2.2 skrll 1318 1.1.2.2 skrll int sc_tx_timer; 1319 1.1.2.2 skrll int fwcur; 1320 1.1.2.2 skrll struct rtwn_rx_ring rx_ring; 1321 1.1.2.2 skrll struct rtwn_tx_ring tx_ring[RTWN_NTXQUEUES]; 1322 1.1.2.2 skrll uint32_t qfullmsk; 1323 1.1.2.2 skrll struct r92c_rom rom; 1324 1.1.2.2 skrll 1325 1.1.2.2 skrll uint32_t rf_chnlbw[R92C_MAX_CHAINS]; 1326 1.1.2.2 skrll struct bpf_if *sc_drvbpf; 1327 1.1.2.2 skrll 1328 1.1.2.2 skrll union { 1329 1.1.2.2 skrll struct rtwn_rx_radiotap_header th; 1330 1.1.2.2 skrll uint8_t pad[64]; 1331 1.1.2.2 skrll } sc_rxtapu; 1332 1.1.2.2 skrll #define sc_rxtap sc_rxtapu.th 1333 1.1.2.2 skrll int sc_rxtap_len; 1334 1.1.2.2 skrll 1335 1.1.2.2 skrll union { 1336 1.1.2.2 skrll struct rtwn_tx_radiotap_header th; 1337 1.1.2.2 skrll uint8_t pad[64]; 1338 1.1.2.2 skrll } sc_txtapu; 1339 1.1.2.2 skrll #define sc_txtap sc_txtapu.th 1340 1.1.2.2 skrll int sc_txtap_len; 1341 1.1.2.2 skrll }; 1342 1.1.2.2 skrll 1343 1.1.2.2 skrll #define sc_if sc_ec.ec_if 1344 1.1.2.2 skrll #define GET_IFP(sc) (&(sc)->sc_if) 1345 1.1.2.2 skrll #define IC2IFP(ic) ((ic)->ic_ifp) 1346 1.1.2.2 skrll 1347 1.1.2.2 skrll 1348 1.1.2.2 skrll /* 1349 1.1.2.2 skrll * MAC initialization values. 1350 1.1.2.2 skrll */ 1351 1.1.2.2 skrll static const struct { 1352 1.1.2.2 skrll uint16_t reg; 1353 1.1.2.2 skrll uint8_t val; 1354 1.1.2.2 skrll } rtl8192ce_mac[] = { 1355 1.1.2.2 skrll { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1356 1.1.2.2 skrll { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1357 1.1.2.2 skrll { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1358 1.1.2.2 skrll { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1359 1.1.2.2 skrll { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1360 1.1.2.2 skrll { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1361 1.1.2.2 skrll { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1362 1.1.2.2 skrll { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1363 1.1.2.2 skrll { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1364 1.1.2.2 skrll { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1365 1.1.2.2 skrll { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1366 1.1.2.2 skrll { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1367 1.1.2.2 skrll { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1368 1.1.2.2 skrll { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1369 1.1.2.2 skrll { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1370 1.1.2.2 skrll { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1371 1.1.2.2 skrll { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1372 1.1.2.2 skrll { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1373 1.1.2.2 skrll { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1374 1.1.2.2 skrll { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1375 1.1.2.2 skrll { 0x70b, 0x87 } 1376 1.1.2.2 skrll }; 1377 1.1.2.2 skrll 1378 1.1.2.2 skrll /* 1379 1.1.2.2 skrll * Baseband initialization values. 1380 1.1.2.2 skrll */ 1381 1.1.2.2 skrll struct rtwn_bb_prog { 1382 1.1.2.2 skrll int count; 1383 1.1.2.2 skrll const uint16_t *regs; 1384 1.1.2.2 skrll const uint32_t *vals; 1385 1.1.2.2 skrll int agccount; 1386 1.1.2.2 skrll const uint32_t *agcvals; 1387 1.1.2.2 skrll }; 1388 1.1.2.2 skrll 1389 1.1.2.2 skrll /* 1390 1.1.2.2 skrll * RTL8192CU and RTL8192CE-VAU. 1391 1.1.2.2 skrll */ 1392 1.1.2.2 skrll static const uint16_t rtl8192ce_bb_regs[] = { 1393 1.1.2.2 skrll 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1394 1.1.2.2 skrll 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1395 1.1.2.2 skrll 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1396 1.1.2.2 skrll 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1397 1.1.2.2 skrll 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1398 1.1.2.2 skrll 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1399 1.1.2.2 skrll 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1400 1.1.2.2 skrll 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1401 1.1.2.2 skrll 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1402 1.1.2.2 skrll 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1403 1.1.2.2 skrll 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1404 1.1.2.2 skrll 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1405 1.1.2.2 skrll 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1406 1.1.2.2 skrll 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1407 1.1.2.2 skrll 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1408 1.1.2.2 skrll 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1409 1.1.2.2 skrll 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1410 1.1.2.2 skrll 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1411 1.1.2.2 skrll 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1412 1.1.2.2 skrll 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1413 1.1.2.2 skrll 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1414 1.1.2.2 skrll }; 1415 1.1.2.2 skrll 1416 1.1.2.2 skrll static const uint32_t rtl8192ce_bb_vals_2t[] = { 1417 1.1.2.2 skrll 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1418 1.1.2.2 skrll 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1419 1.1.2.2 skrll 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1420 1.1.2.2 skrll 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1421 1.1.2.2 skrll 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1422 1.1.2.2 skrll 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1423 1.1.2.2 skrll 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1424 1.1.2.2 skrll 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1425 1.1.2.2 skrll 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1426 1.1.2.2 skrll 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1427 1.1.2.2 skrll 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1428 1.1.2.2 skrll 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1429 1.1.2.2 skrll 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1430 1.1.2.2 skrll 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1431 1.1.2.2 skrll 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1432 1.1.2.2 skrll 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1433 1.1.2.2 skrll 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1434 1.1.2.2 skrll 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1435 1.1.2.2 skrll 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1436 1.1.2.2 skrll 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1437 1.1.2.2 skrll 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1438 1.1.2.2 skrll 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1439 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1440 1.1.2.2 skrll 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1441 1.1.2.2 skrll 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1442 1.1.2.2 skrll 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1443 1.1.2.2 skrll 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1444 1.1.2.2 skrll 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1445 1.1.2.2 skrll 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1446 1.1.2.2 skrll 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1447 1.1.2.2 skrll 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1448 1.1.2.2 skrll 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1449 1.1.2.2 skrll 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1450 1.1.2.2 skrll 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1451 1.1.2.2 skrll 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1452 1.1.2.2 skrll 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1453 1.1.2.2 skrll 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1454 1.1.2.2 skrll 0x00000000, 0x00000300 1455 1.1.2.2 skrll }; 1456 1.1.2.2 skrll 1457 1.1.2.2 skrll static const uint32_t rtl8192ce_bb_vals_1t[] = { 1458 1.1.2.2 skrll 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1459 1.1.2.2 skrll 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1460 1.1.2.2 skrll 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1461 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1462 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1463 1.1.2.2 skrll 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1464 1.1.2.2 skrll 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1465 1.1.2.2 skrll 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1466 1.1.2.2 skrll 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1467 1.1.2.2 skrll 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1468 1.1.2.2 skrll 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1469 1.1.2.2 skrll 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1470 1.1.2.2 skrll 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1471 1.1.2.2 skrll 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1472 1.1.2.2 skrll 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1473 1.1.2.2 skrll 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1474 1.1.2.2 skrll 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1475 1.1.2.2 skrll 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1476 1.1.2.2 skrll 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1477 1.1.2.2 skrll 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1478 1.1.2.2 skrll 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1479 1.1.2.2 skrll 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1480 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1481 1.1.2.2 skrll 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1482 1.1.2.2 skrll 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1483 1.1.2.2 skrll 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1484 1.1.2.2 skrll 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1485 1.1.2.2 skrll 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1486 1.1.2.2 skrll 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1487 1.1.2.2 skrll 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1488 1.1.2.2 skrll 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1489 1.1.2.2 skrll 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1490 1.1.2.2 skrll 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1491 1.1.2.2 skrll 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1492 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1493 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1494 1.1.2.2 skrll 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1495 1.1.2.2 skrll 0x00000000, 0x00000300, 1496 1.1.2.2 skrll }; 1497 1.1.2.2 skrll 1498 1.1.2.2 skrll static const uint32_t rtl8192ce_agc_vals[] = { 1499 1.1.2.2 skrll 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1500 1.1.2.2 skrll 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1501 1.1.2.2 skrll 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1502 1.1.2.2 skrll 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1503 1.1.2.2 skrll 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1504 1.1.2.2 skrll 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1505 1.1.2.2 skrll 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1506 1.1.2.2 skrll 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1507 1.1.2.2 skrll 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1508 1.1.2.2 skrll 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1509 1.1.2.2 skrll 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1510 1.1.2.2 skrll 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1511 1.1.2.2 skrll 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1512 1.1.2.2 skrll 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1513 1.1.2.2 skrll 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1514 1.1.2.2 skrll 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1515 1.1.2.2 skrll 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1516 1.1.2.2 skrll 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1517 1.1.2.2 skrll 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1518 1.1.2.2 skrll 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1519 1.1.2.2 skrll 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1520 1.1.2.2 skrll 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1521 1.1.2.2 skrll 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1522 1.1.2.2 skrll 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1523 1.1.2.2 skrll 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1524 1.1.2.2 skrll 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1525 1.1.2.2 skrll 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1526 1.1.2.2 skrll 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1527 1.1.2.2 skrll 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1528 1.1.2.2 skrll 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1529 1.1.2.2 skrll 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1530 1.1.2.2 skrll 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1531 1.1.2.2 skrll }; 1532 1.1.2.2 skrll 1533 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8192ce_bb_prog_2t = { 1534 1.1.2.2 skrll __arraycount(rtl8192ce_bb_regs), 1535 1.1.2.2 skrll rtl8192ce_bb_regs, 1536 1.1.2.2 skrll rtl8192ce_bb_vals_2t, 1537 1.1.2.2 skrll __arraycount(rtl8192ce_agc_vals), 1538 1.1.2.2 skrll rtl8192ce_agc_vals 1539 1.1.2.2 skrll }; 1540 1.1.2.2 skrll 1541 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8192ce_bb_prog_1t = { 1542 1.1.2.2 skrll __arraycount(rtl8192ce_bb_regs), 1543 1.1.2.2 skrll rtl8192ce_bb_regs, 1544 1.1.2.2 skrll rtl8192ce_bb_vals_1t, 1545 1.1.2.2 skrll __arraycount(rtl8192ce_agc_vals), 1546 1.1.2.2 skrll rtl8192ce_agc_vals 1547 1.1.2.2 skrll }; 1548 1.1.2.2 skrll 1549 1.1.2.2 skrll /* 1550 1.1.2.2 skrll * RTL8188CU. 1551 1.1.2.2 skrll */ 1552 1.1.2.2 skrll static const uint32_t rtl8192cu_bb_vals[] = { 1553 1.1.2.2 skrll 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1554 1.1.2.2 skrll 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1555 1.1.2.2 skrll 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1556 1.1.2.2 skrll 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1557 1.1.2.2 skrll 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1558 1.1.2.2 skrll 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1559 1.1.2.2 skrll 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1560 1.1.2.2 skrll 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1561 1.1.2.2 skrll 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1562 1.1.2.2 skrll 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1563 1.1.2.2 skrll 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1564 1.1.2.2 skrll 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1565 1.1.2.2 skrll 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1566 1.1.2.2 skrll 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1567 1.1.2.2 skrll 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1568 1.1.2.2 skrll 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1569 1.1.2.2 skrll 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1570 1.1.2.2 skrll 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1571 1.1.2.2 skrll 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1572 1.1.2.2 skrll 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1573 1.1.2.2 skrll 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1574 1.1.2.2 skrll 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1575 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1576 1.1.2.2 skrll 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1577 1.1.2.2 skrll 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1578 1.1.2.2 skrll 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1579 1.1.2.2 skrll 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1580 1.1.2.2 skrll 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1581 1.1.2.2 skrll 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1582 1.1.2.2 skrll 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1583 1.1.2.2 skrll 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1584 1.1.2.2 skrll 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1585 1.1.2.2 skrll 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1586 1.1.2.2 skrll 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1587 1.1.2.2 skrll 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1588 1.1.2.2 skrll 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1589 1.1.2.2 skrll 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1590 1.1.2.2 skrll 0x00000000, 0x00000300 1591 1.1.2.2 skrll }; 1592 1.1.2.2 skrll 1593 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8192cu_bb_prog = { 1594 1.1.2.2 skrll __arraycount(rtl8192ce_bb_regs), 1595 1.1.2.2 skrll rtl8192ce_bb_regs, 1596 1.1.2.2 skrll rtl8192cu_bb_vals, 1597 1.1.2.2 skrll __arraycount(rtl8192ce_agc_vals), 1598 1.1.2.2 skrll rtl8192ce_agc_vals 1599 1.1.2.2 skrll }; 1600 1.1.2.2 skrll 1601 1.1.2.2 skrll /* 1602 1.1.2.2 skrll * RTL8188CE-VAU. 1603 1.1.2.2 skrll */ 1604 1.1.2.2 skrll static const uint32_t rtl8188ce_bb_vals[] = { 1605 1.1.2.2 skrll 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1606 1.1.2.2 skrll 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1607 1.1.2.2 skrll 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1608 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1609 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1610 1.1.2.2 skrll 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1611 1.1.2.2 skrll 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1612 1.1.2.2 skrll 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1613 1.1.2.2 skrll 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1614 1.1.2.2 skrll 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1615 1.1.2.2 skrll 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1616 1.1.2.2 skrll 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1617 1.1.2.2 skrll 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1618 1.1.2.2 skrll 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1619 1.1.2.2 skrll 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1620 1.1.2.2 skrll 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1621 1.1.2.2 skrll 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1622 1.1.2.2 skrll 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1623 1.1.2.2 skrll 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1624 1.1.2.2 skrll 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1625 1.1.2.2 skrll 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1626 1.1.2.2 skrll 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1627 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1628 1.1.2.2 skrll 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1629 1.1.2.2 skrll 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1630 1.1.2.2 skrll 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1631 1.1.2.2 skrll 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1632 1.1.2.2 skrll 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1633 1.1.2.2 skrll 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1634 1.1.2.2 skrll 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1635 1.1.2.2 skrll 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1636 1.1.2.2 skrll 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1637 1.1.2.2 skrll 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1638 1.1.2.2 skrll 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1639 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1640 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1641 1.1.2.2 skrll 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1642 1.1.2.2 skrll 0x00000000, 0x00000300 1643 1.1.2.2 skrll }; 1644 1.1.2.2 skrll 1645 1.1.2.2 skrll static const uint32_t rtl8188ce_agc_vals[] = { 1646 1.1.2.2 skrll 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1647 1.1.2.2 skrll 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1648 1.1.2.2 skrll 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1649 1.1.2.2 skrll 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1650 1.1.2.2 skrll 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1651 1.1.2.2 skrll 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1652 1.1.2.2 skrll 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1653 1.1.2.2 skrll 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1654 1.1.2.2 skrll 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1655 1.1.2.2 skrll 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1656 1.1.2.2 skrll 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1657 1.1.2.2 skrll 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1658 1.1.2.2 skrll 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1659 1.1.2.2 skrll 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1660 1.1.2.2 skrll 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1661 1.1.2.2 skrll 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1662 1.1.2.2 skrll 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1663 1.1.2.2 skrll 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1664 1.1.2.2 skrll 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1665 1.1.2.2 skrll 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1666 1.1.2.2 skrll 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1667 1.1.2.2 skrll 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1668 1.1.2.2 skrll 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1669 1.1.2.2 skrll 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1670 1.1.2.2 skrll 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1671 1.1.2.2 skrll 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1672 1.1.2.2 skrll 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1673 1.1.2.2 skrll 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1674 1.1.2.2 skrll 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1675 1.1.2.2 skrll 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1676 1.1.2.2 skrll 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1677 1.1.2.2 skrll 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1678 1.1.2.2 skrll }; 1679 1.1.2.2 skrll 1680 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8188ce_bb_prog = { 1681 1.1.2.2 skrll __arraycount(rtl8192ce_bb_regs), 1682 1.1.2.2 skrll rtl8192ce_bb_regs, 1683 1.1.2.2 skrll rtl8188ce_bb_vals, 1684 1.1.2.2 skrll __arraycount(rtl8188ce_agc_vals), 1685 1.1.2.2 skrll rtl8188ce_agc_vals 1686 1.1.2.2 skrll }; 1687 1.1.2.2 skrll 1688 1.1.2.2 skrll static const uint32_t rtl8188cu_bb_vals[] = { 1689 1.1.2.2 skrll 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1690 1.1.2.2 skrll 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1691 1.1.2.2 skrll 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1692 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1693 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1694 1.1.2.2 skrll 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1695 1.1.2.2 skrll 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1696 1.1.2.2 skrll 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1697 1.1.2.2 skrll 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1698 1.1.2.2 skrll 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1699 1.1.2.2 skrll 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1700 1.1.2.2 skrll 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1701 1.1.2.2 skrll 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1702 1.1.2.2 skrll 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1703 1.1.2.2 skrll 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1704 1.1.2.2 skrll 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1705 1.1.2.2 skrll 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1706 1.1.2.2 skrll 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1707 1.1.2.2 skrll 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1708 1.1.2.2 skrll 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1709 1.1.2.2 skrll 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1710 1.1.2.2 skrll 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1711 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1712 1.1.2.2 skrll 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1713 1.1.2.2 skrll 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1714 1.1.2.2 skrll 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1715 1.1.2.2 skrll 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1716 1.1.2.2 skrll 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1717 1.1.2.2 skrll 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1718 1.1.2.2 skrll 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1719 1.1.2.2 skrll 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1720 1.1.2.2 skrll 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1721 1.1.2.2 skrll 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1722 1.1.2.2 skrll 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1723 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1724 1.1.2.2 skrll 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1725 1.1.2.2 skrll 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1726 1.1.2.2 skrll 0x00000000, 0x00000300 1727 1.1.2.2 skrll }; 1728 1.1.2.2 skrll 1729 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8188cu_bb_prog = { 1730 1.1.2.2 skrll __arraycount(rtl8192ce_bb_regs), 1731 1.1.2.2 skrll rtl8192ce_bb_regs, 1732 1.1.2.2 skrll rtl8188cu_bb_vals, 1733 1.1.2.2 skrll __arraycount(rtl8188ce_agc_vals), 1734 1.1.2.2 skrll rtl8188ce_agc_vals 1735 1.1.2.2 skrll }; 1736 1.1.2.2 skrll 1737 1.1.2.2 skrll /* 1738 1.1.2.2 skrll * RTL8188RU. 1739 1.1.2.2 skrll */ 1740 1.1.2.2 skrll static const uint16_t rtl8188ru_bb_regs[] = { 1741 1.1.2.2 skrll 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1742 1.1.2.2 skrll 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1743 1.1.2.2 skrll 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1744 1.1.2.2 skrll 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1745 1.1.2.2 skrll 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1746 1.1.2.2 skrll 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1747 1.1.2.2 skrll 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1748 1.1.2.2 skrll 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1749 1.1.2.2 skrll 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1750 1.1.2.2 skrll 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1751 1.1.2.2 skrll 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1752 1.1.2.2 skrll 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1753 1.1.2.2 skrll 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1754 1.1.2.2 skrll 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1755 1.1.2.2 skrll 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1756 1.1.2.2 skrll 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1757 1.1.2.2 skrll 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1758 1.1.2.2 skrll 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1759 1.1.2.2 skrll 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1760 1.1.2.2 skrll 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1761 1.1.2.2 skrll 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1762 1.1.2.2 skrll }; 1763 1.1.2.2 skrll 1764 1.1.2.2 skrll static const uint32_t rtl8188ru_bb_vals[] = { 1765 1.1.2.2 skrll 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1766 1.1.2.2 skrll 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1767 1.1.2.2 skrll 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1768 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1769 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1770 1.1.2.2 skrll 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1771 1.1.2.2 skrll 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1772 1.1.2.2 skrll 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1773 1.1.2.2 skrll 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1774 1.1.2.2 skrll 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1775 1.1.2.2 skrll 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1776 1.1.2.2 skrll 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1777 1.1.2.2 skrll 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1778 1.1.2.2 skrll 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1779 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1780 1.1.2.2 skrll 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1781 1.1.2.2 skrll 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1782 1.1.2.2 skrll 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1783 1.1.2.2 skrll 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1784 1.1.2.2 skrll 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1785 1.1.2.2 skrll 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1786 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1787 1.1.2.2 skrll 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1788 1.1.2.2 skrll 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1789 1.1.2.2 skrll 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1790 1.1.2.2 skrll 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1791 1.1.2.2 skrll 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1792 1.1.2.2 skrll 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1793 1.1.2.2 skrll 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1794 1.1.2.2 skrll 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1795 1.1.2.2 skrll 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1796 1.1.2.2 skrll 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1797 1.1.2.2 skrll 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1798 1.1.2.2 skrll 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1799 1.1.2.2 skrll 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1800 1.1.2.2 skrll 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1801 1.1.2.2 skrll 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1802 1.1.2.2 skrll 0x31555448, 0x00000003, 0x00000000, 0x00000300 1803 1.1.2.2 skrll }; 1804 1.1.2.2 skrll 1805 1.1.2.2 skrll static const uint32_t rtl8188ru_agc_vals[] = { 1806 1.1.2.2 skrll 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1807 1.1.2.2 skrll 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1808 1.1.2.2 skrll 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1809 1.1.2.2 skrll 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1810 1.1.2.2 skrll 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1811 1.1.2.2 skrll 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1812 1.1.2.2 skrll 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1813 1.1.2.2 skrll 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1814 1.1.2.2 skrll 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1815 1.1.2.2 skrll 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1816 1.1.2.2 skrll 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1817 1.1.2.2 skrll 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1818 1.1.2.2 skrll 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1819 1.1.2.2 skrll 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1820 1.1.2.2 skrll 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1821 1.1.2.2 skrll 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1822 1.1.2.2 skrll 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1823 1.1.2.2 skrll 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1824 1.1.2.2 skrll 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1825 1.1.2.2 skrll 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1826 1.1.2.2 skrll 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1827 1.1.2.2 skrll 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1828 1.1.2.2 skrll 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1829 1.1.2.2 skrll 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1830 1.1.2.2 skrll 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1831 1.1.2.2 skrll 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1832 1.1.2.2 skrll 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1833 1.1.2.2 skrll 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1834 1.1.2.2 skrll 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1835 1.1.2.2 skrll 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1836 1.1.2.2 skrll 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1837 1.1.2.2 skrll 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1838 1.1.2.2 skrll }; 1839 1.1.2.2 skrll 1840 1.1.2.2 skrll static const struct rtwn_bb_prog rtl8188ru_bb_prog = { 1841 1.1.2.2 skrll __arraycount(rtl8188ru_bb_regs), 1842 1.1.2.2 skrll rtl8188ru_bb_regs, 1843 1.1.2.2 skrll rtl8188ru_bb_vals, 1844 1.1.2.2 skrll __arraycount(rtl8188ru_agc_vals), 1845 1.1.2.2 skrll rtl8188ru_agc_vals 1846 1.1.2.2 skrll }; 1847 1.1.2.2 skrll 1848 1.1.2.2 skrll /* 1849 1.1.2.2 skrll * RF initialization values. 1850 1.1.2.2 skrll */ 1851 1.1.2.2 skrll struct rtwn_rf_prog { 1852 1.1.2.2 skrll int count; 1853 1.1.2.2 skrll const uint8_t *regs; 1854 1.1.2.2 skrll const uint32_t *vals; 1855 1.1.2.2 skrll }; 1856 1.1.2.2 skrll 1857 1.1.2.2 skrll /* 1858 1.1.2.2 skrll * RTL8192CU and RTL8192CE-VAU. 1859 1.1.2.2 skrll */ 1860 1.1.2.2 skrll static const uint8_t rtl8192ce_rf1_regs[] = { 1861 1.1.2.2 skrll 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1862 1.1.2.2 skrll 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1863 1.1.2.2 skrll 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1864 1.1.2.2 skrll 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1865 1.1.2.2 skrll 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1866 1.1.2.2 skrll 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1867 1.1.2.2 skrll 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1868 1.1.2.2 skrll 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1869 1.1.2.2 skrll 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1870 1.1.2.2 skrll 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1871 1.1.2.2 skrll 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1872 1.1.2.2 skrll 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1873 1.1.2.2 skrll 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1874 1.1.2.2 skrll }; 1875 1.1.2.2 skrll 1876 1.1.2.2 skrll static const uint32_t rtl8192ce_rf1_vals[] = { 1877 1.1.2.2 skrll 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1878 1.1.2.2 skrll 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1879 1.1.2.2 skrll 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1880 1.1.2.2 skrll 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1881 1.1.2.2 skrll 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1882 1.1.2.2 skrll 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1883 1.1.2.2 skrll 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1884 1.1.2.2 skrll 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1885 1.1.2.2 skrll 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1886 1.1.2.2 skrll 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1887 1.1.2.2 skrll 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1888 1.1.2.2 skrll 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1889 1.1.2.2 skrll 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1890 1.1.2.2 skrll 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1891 1.1.2.2 skrll 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1892 1.1.2.2 skrll 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1893 1.1.2.2 skrll 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1894 1.1.2.2 skrll 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1895 1.1.2.2 skrll 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1896 1.1.2.2 skrll 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1897 1.1.2.2 skrll 0x30159 1898 1.1.2.2 skrll }; 1899 1.1.2.2 skrll 1900 1.1.2.2 skrll static const uint8_t rtl8192ce_rf2_regs[] = { 1901 1.1.2.2 skrll 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1902 1.1.2.2 skrll 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1903 1.1.2.2 skrll 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1904 1.1.2.2 skrll 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1905 1.1.2.2 skrll }; 1906 1.1.2.2 skrll 1907 1.1.2.2 skrll static const uint32_t rtl8192ce_rf2_vals[] = { 1908 1.1.2.2 skrll 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1909 1.1.2.2 skrll 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1910 1.1.2.2 skrll 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1911 1.1.2.2 skrll 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1912 1.1.2.2 skrll 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1913 1.1.2.2 skrll 0xe0330, 0xa0330, 0x60330, 0x20330 1914 1.1.2.2 skrll }; 1915 1.1.2.2 skrll 1916 1.1.2.2 skrll static const struct rtwn_rf_prog rtl8192ce_rf_prog[] = { 1917 1.1.2.2 skrll { 1918 1.1.2.2 skrll __arraycount(rtl8192ce_rf1_regs), 1919 1.1.2.2 skrll rtl8192ce_rf1_regs, 1920 1.1.2.2 skrll rtl8192ce_rf1_vals 1921 1.1.2.2 skrll }, 1922 1.1.2.2 skrll { 1923 1.1.2.2 skrll __arraycount(rtl8192ce_rf2_regs), 1924 1.1.2.2 skrll rtl8192ce_rf2_regs, 1925 1.1.2.2 skrll rtl8192ce_rf2_vals 1926 1.1.2.2 skrll } 1927 1.1.2.2 skrll }; 1928 1.1.2.2 skrll 1929 1.1.2.2 skrll /* 1930 1.1.2.2 skrll * RTL8188CE-VAU. 1931 1.1.2.2 skrll */ 1932 1.1.2.2 skrll static const uint32_t rtl8188ce_rf_vals[] = { 1933 1.1.2.2 skrll 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1934 1.1.2.2 skrll 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1935 1.1.2.2 skrll 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1936 1.1.2.2 skrll 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1937 1.1.2.2 skrll 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1938 1.1.2.2 skrll 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1939 1.1.2.2 skrll 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1940 1.1.2.2 skrll 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1941 1.1.2.2 skrll 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1942 1.1.2.2 skrll 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1943 1.1.2.2 skrll 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1944 1.1.2.2 skrll 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1945 1.1.2.2 skrll 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1946 1.1.2.2 skrll 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1947 1.1.2.2 skrll 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1948 1.1.2.2 skrll 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1949 1.1.2.2 skrll 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1950 1.1.2.2 skrll 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1951 1.1.2.2 skrll 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1952 1.1.2.2 skrll 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1953 1.1.2.2 skrll 0x30159 1954 1.1.2.2 skrll }; 1955 1.1.2.2 skrll 1956 1.1.2.2 skrll static const struct rtwn_rf_prog rtl8188ce_rf_prog[] = { 1957 1.1.2.2 skrll { 1958 1.1.2.2 skrll __arraycount(rtl8192ce_rf1_regs), 1959 1.1.2.2 skrll rtl8192ce_rf1_regs, 1960 1.1.2.2 skrll rtl8188ce_rf_vals 1961 1.1.2.2 skrll } 1962 1.1.2.2 skrll }; 1963 1.1.2.2 skrll 1964 1.1.2.2 skrll 1965 1.1.2.2 skrll /* 1966 1.1.2.2 skrll * RTL8188CU. 1967 1.1.2.2 skrll */ 1968 1.1.2.2 skrll static const uint32_t rtl8188cu_rf_vals[] = { 1969 1.1.2.2 skrll 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1970 1.1.2.2 skrll 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1971 1.1.2.2 skrll 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1972 1.1.2.2 skrll 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1973 1.1.2.2 skrll 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1974 1.1.2.2 skrll 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1975 1.1.2.2 skrll 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1976 1.1.2.2 skrll 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1977 1.1.2.2 skrll 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1978 1.1.2.2 skrll 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1979 1.1.2.2 skrll 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1980 1.1.2.2 skrll 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1981 1.1.2.2 skrll 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1982 1.1.2.2 skrll 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1983 1.1.2.2 skrll 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1984 1.1.2.2 skrll 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1985 1.1.2.2 skrll 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1986 1.1.2.2 skrll 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1987 1.1.2.2 skrll 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1988 1.1.2.2 skrll 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1989 1.1.2.2 skrll 0x30159 1990 1.1.2.2 skrll }; 1991 1.1.2.2 skrll 1992 1.1.2.2 skrll static const struct rtwn_rf_prog rtl8188cu_rf_prog[] = { 1993 1.1.2.2 skrll { 1994 1.1.2.2 skrll __arraycount(rtl8192ce_rf1_regs), 1995 1.1.2.2 skrll rtl8192ce_rf1_regs, 1996 1.1.2.2 skrll rtl8188cu_rf_vals 1997 1.1.2.2 skrll } 1998 1.1.2.2 skrll }; 1999 1.1.2.2 skrll 2000 1.1.2.2 skrll /* 2001 1.1.2.2 skrll * RTL8188RU. 2002 1.1.2.2 skrll */ 2003 1.1.2.2 skrll static const uint32_t rtl8188ru_rf_vals[] = { 2004 1.1.2.2 skrll 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 2005 1.1.2.2 skrll 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 2006 1.1.2.2 skrll 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 2007 1.1.2.2 skrll 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 2008 1.1.2.2 skrll 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 2009 1.1.2.2 skrll 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2010 1.1.2.2 skrll 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2011 1.1.2.2 skrll 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2012 1.1.2.2 skrll 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2013 1.1.2.2 skrll 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2014 1.1.2.2 skrll 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2015 1.1.2.2 skrll 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2016 1.1.2.2 skrll 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2017 1.1.2.2 skrll 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2018 1.1.2.2 skrll 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2019 1.1.2.2 skrll 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2020 1.1.2.2 skrll 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2021 1.1.2.2 skrll 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2022 1.1.2.2 skrll 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2023 1.1.2.2 skrll 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2024 1.1.2.2 skrll 0x30159 2025 1.1.2.2 skrll }; 2026 1.1.2.2 skrll 2027 1.1.2.2 skrll static const struct rtwn_rf_prog rtl8188ru_rf_prog[] = { 2028 1.1.2.2 skrll { 2029 1.1.2.2 skrll __arraycount(rtl8192ce_rf1_regs), 2030 1.1.2.2 skrll rtl8192ce_rf1_regs, 2031 1.1.2.2 skrll rtl8188ru_rf_vals 2032 1.1.2.2 skrll } 2033 1.1.2.2 skrll }; 2034 1.1.2.2 skrll 2035 1.1.2.2 skrll struct rtwn_txpwr { 2036 1.1.2.2 skrll uint8_t pwr[3][28]; 2037 1.1.2.2 skrll }; 2038 1.1.2.2 skrll 2039 1.1.2.2 skrll /* 2040 1.1.2.2 skrll * Per RF chain/group/rate Tx gain values. 2041 1.1.2.2 skrll */ 2042 1.1.2.2 skrll static const struct rtwn_txpwr rtl8192cu_txagc[] = { 2043 1.1.2.2 skrll { { /* Chain 0. */ 2044 1.1.2.2 skrll { /* Group 0. */ 2045 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2046 1.1.2.2 skrll 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2047 1.1.2.2 skrll 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2048 1.1.2.2 skrll 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2049 1.1.2.2 skrll }, 2050 1.1.2.2 skrll { /* Group 1. */ 2051 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2052 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2053 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2054 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2055 1.1.2.2 skrll }, 2056 1.1.2.2 skrll { /* Group 2. */ 2057 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2058 1.1.2.2 skrll 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2059 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2060 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2061 1.1.2.2 skrll } 2062 1.1.2.2 skrll } }, 2063 1.1.2.2 skrll { { /* Chain 1. */ 2064 1.1.2.2 skrll { /* Group 0. */ 2065 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2066 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2067 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2068 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2069 1.1.2.2 skrll }, 2070 1.1.2.2 skrll { /* Group 1. */ 2071 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2072 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2073 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2074 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2075 1.1.2.2 skrll }, 2076 1.1.2.2 skrll { /* Group 2. */ 2077 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2078 1.1.2.2 skrll 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2079 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2080 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2081 1.1.2.2 skrll } 2082 1.1.2.2 skrll } } 2083 1.1.2.2 skrll }; 2084 1.1.2.2 skrll 2085 1.1.2.2 skrll static const struct rtwn_txpwr rtl8188ru_txagc[] = { 2086 1.1.2.2 skrll { { /* Chain 0. */ 2087 1.1.2.2 skrll { /* Group 0. */ 2088 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2089 1.1.2.2 skrll 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2090 1.1.2.2 skrll 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2091 1.1.2.2 skrll 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2092 1.1.2.2 skrll }, 2093 1.1.2.2 skrll { /* Group 1. */ 2094 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2095 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2096 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2097 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2098 1.1.2.2 skrll }, 2099 1.1.2.2 skrll { /* Group 2. */ 2100 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2101 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2102 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2103 1.1.2.2 skrll 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2104 1.1.2.2 skrll } 2105 1.1.2.2 skrll } } 2106 1.1.2.2 skrll }; 2107
Indexes created Wed Oct 22 13:09:56 GMT 2025