if_sip.c revision 1.101.2.2
1 /* $NetBSD: if_sip.c,v 1.101.2.2 2006/04/21 11:57:35 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.101.2.2 2006/04/21 11:57:35 tron Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 short sc_if_flags; 313 314 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 315 #if defined(DP83820) 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 #endif /* DP83820 */ 322 323 #if NRND > 0 324 rndsource_element_t rnd_source; /* random source */ 325 #endif 326 }; 327 328 #ifdef DP83820 329 #define SIP_RXCHAIN_RESET(sc) \ 330 do { \ 331 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 332 *(sc)->sc_rxtailp = NULL; \ 333 (sc)->sc_rxlen = 0; \ 334 } while (/*CONSTCOND*/0) 335 336 #define SIP_RXCHAIN_LINK(sc, m) \ 337 do { \ 338 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 339 (sc)->sc_rxtailp = &(m)->m_next; \ 340 } while (/*CONSTCOND*/0) 341 #endif /* DP83820 */ 342 343 #ifdef SIP_EVENT_COUNTERS 344 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 345 #else 346 #define SIP_EVCNT_INCR(ev) /* nothing */ 347 #endif 348 349 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 350 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 351 352 #define SIP_CDTXSYNC(sc, x, n, ops) \ 353 do { \ 354 int __x, __n; \ 355 \ 356 __x = (x); \ 357 __n = (n); \ 358 \ 359 /* If it will wrap around, sync to the end of the ring. */ \ 360 if ((__x + __n) > SIP_NTXDESC) { \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 363 (SIP_NTXDESC - __x), (ops)); \ 364 __n -= (SIP_NTXDESC - __x); \ 365 __x = 0; \ 366 } \ 367 \ 368 /* Now sync whatever is left. */ \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 371 } while (0) 372 373 #define SIP_CDRXSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 376 377 #ifdef DP83820 378 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 379 #define SIP_RXBUF_LEN (MCLBYTES - 8) 380 #else 381 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 382 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 383 #endif 384 #define SIP_INIT_RXDESC(sc, x) \ 385 do { \ 386 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 387 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 388 \ 389 __sipd->sipd_link = \ 390 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 391 __sipd->sipd_bufptr = \ 392 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 393 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 394 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 395 SIP_INIT_RXDESC_EXTSTS \ 396 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 397 } while (0) 398 399 #define SIP_CHIP_VERS(sc, v, p, r) \ 400 ((sc)->sc_model->sip_vendor == (v) && \ 401 (sc)->sc_model->sip_product == (p) && \ 402 (sc)->sc_rev == (r)) 403 404 #define SIP_CHIP_MODEL(sc, v, p) \ 405 ((sc)->sc_model->sip_vendor == (v) && \ 406 (sc)->sc_model->sip_product == (p)) 407 408 #if !defined(DP83820) 409 #define SIP_SIS900_REV(sc, rev) \ 410 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 411 #endif 412 413 #define SIP_TIMEOUT 1000 414 415 static void SIP_DECL(start)(struct ifnet *); 416 static void SIP_DECL(watchdog)(struct ifnet *); 417 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 418 static int SIP_DECL(init)(struct ifnet *); 419 static void SIP_DECL(stop)(struct ifnet *, int); 420 421 static void SIP_DECL(shutdown)(void *); 422 423 static void SIP_DECL(reset)(struct sip_softc *); 424 static void SIP_DECL(rxdrain)(struct sip_softc *); 425 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 426 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 427 u_int16_t *); 428 static void SIP_DECL(tick)(void *); 429 430 #if !defined(DP83820) 431 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 432 #endif /* ! DP83820 */ 433 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 434 435 #if defined(DP83820) 436 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 437 const struct pci_attach_args *, u_int8_t *); 438 #else 439 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 440 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 #endif /* DP83820 */ 445 446 static int SIP_DECL(intr)(void *); 447 static void SIP_DECL(txintr)(struct sip_softc *); 448 static void SIP_DECL(rxintr)(struct sip_softc *); 449 450 #if defined(DP83820) 451 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 452 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 453 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 454 #else 455 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 456 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 457 static void SIP_DECL(sis900_mii_statchg)(struct device *); 458 459 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 460 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 461 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 462 #endif /* DP83820 */ 463 464 static int SIP_DECL(mediachange)(struct ifnet *); 465 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 466 467 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 468 static void SIP_DECL(attach)(struct device *, struct device *, void *); 469 470 int SIP_DECL(copy_small) = 0; 471 472 #ifdef DP83820 473 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 474 gsip_match, gsip_attach, NULL, NULL); 475 #else 476 CFATTACH_DECL(sip, sizeof(struct sip_softc), 477 sip_match, sip_attach, NULL, NULL); 478 #endif 479 480 /* 481 * Descriptions of the variants of the SiS900. 482 */ 483 struct sip_variant { 484 int (*sipv_mii_readreg)(struct device *, int, int); 485 void (*sipv_mii_writereg)(struct device *, int, int, int); 486 void (*sipv_mii_statchg)(struct device *); 487 void (*sipv_set_filter)(struct sip_softc *); 488 void (*sipv_read_macaddr)(struct sip_softc *, 489 const struct pci_attach_args *, u_int8_t *); 490 }; 491 492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 493 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 494 495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 496 SIP_DECL(mii_bitbang_read), 497 SIP_DECL(mii_bitbang_write), 498 { 499 EROMAR_MDIO, /* MII_BIT_MDO */ 500 EROMAR_MDIO, /* MII_BIT_MDI */ 501 EROMAR_MDC, /* MII_BIT_MDC */ 502 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 503 0, /* MII_BIT_DIR_PHY_HOST */ 504 } 505 }; 506 507 #if defined(DP83820) 508 static const struct sip_variant SIP_DECL(variant_dp83820) = { 509 SIP_DECL(dp83820_mii_readreg), 510 SIP_DECL(dp83820_mii_writereg), 511 SIP_DECL(dp83820_mii_statchg), 512 SIP_DECL(dp83815_set_filter), 513 SIP_DECL(dp83820_read_macaddr), 514 }; 515 #else 516 static const struct sip_variant SIP_DECL(variant_sis900) = { 517 SIP_DECL(sis900_mii_readreg), 518 SIP_DECL(sis900_mii_writereg), 519 SIP_DECL(sis900_mii_statchg), 520 SIP_DECL(sis900_set_filter), 521 SIP_DECL(sis900_read_macaddr), 522 }; 523 524 static const struct sip_variant SIP_DECL(variant_dp83815) = { 525 SIP_DECL(dp83815_mii_readreg), 526 SIP_DECL(dp83815_mii_writereg), 527 SIP_DECL(dp83815_mii_statchg), 528 SIP_DECL(dp83815_set_filter), 529 SIP_DECL(dp83815_read_macaddr), 530 }; 531 #endif /* DP83820 */ 532 533 /* 534 * Devices supported by this driver. 535 */ 536 static const struct sip_product { 537 pci_vendor_id_t sip_vendor; 538 pci_product_id_t sip_product; 539 const char *sip_name; 540 const struct sip_variant *sip_variant; 541 } SIP_DECL(products)[] = { 542 #if defined(DP83820) 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 544 "NatSemi DP83820 Gigabit Ethernet", 545 &SIP_DECL(variant_dp83820) }, 546 #else 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 548 "SiS 900 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 551 "SiS 7016 10/100 Ethernet", 552 &SIP_DECL(variant_sis900) }, 553 554 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 555 "NatSemi DP83815 10/100 Ethernet", 556 &SIP_DECL(variant_dp83815) }, 557 #endif /* DP83820 */ 558 559 { 0, 0, 560 NULL, 561 NULL }, 562 }; 563 564 static const struct sip_product * 565 SIP_DECL(lookup)(const struct pci_attach_args *pa) 566 { 567 const struct sip_product *sip; 568 569 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 570 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 571 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 572 return (sip); 573 } 574 return (NULL); 575 } 576 577 #ifdef DP83820 578 /* 579 * I really hate stupid hardware vendors. There's a bit in the EEPROM 580 * which indicates if the card can do 64-bit data transfers. Unfortunately, 581 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 582 * which means we try to use 64-bit data transfers on those cards if we 583 * happen to be plugged into a 32-bit slot. 584 * 585 * What we do is use this table of cards known to be 64-bit cards. If 586 * you have a 64-bit card who's subsystem ID is not listed in this table, 587 * send the output of "pcictl dump ..." of the device to me so that your 588 * card will use the 64-bit data path when plugged into a 64-bit slot. 589 * 590 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 591 * June 30, 2002 592 */ 593 static int 594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 595 { 596 static const struct { 597 pci_vendor_id_t c64_vendor; 598 pci_product_id_t c64_product; 599 } card64[] = { 600 /* Asante GigaNIX */ 601 { 0x128a, 0x0002 }, 602 603 /* Accton EN1407-T, Planex GN-1000TE */ 604 { 0x1113, 0x1407 }, 605 606 /* Netgear GA-621 */ 607 { 0x1385, 0x621a }, 608 609 /* SMC EZ Card */ 610 { 0x10b8, 0x9462 }, 611 612 { 0, 0} 613 }; 614 pcireg_t subsys; 615 int i; 616 617 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 618 619 for (i = 0; card64[i].c64_vendor != 0; i++) { 620 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 621 PCI_PRODUCT(subsys) == card64[i].c64_product) 622 return (1); 623 } 624 625 return (0); 626 } 627 #endif /* DP83820 */ 628 629 static int 630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 631 { 632 struct pci_attach_args *pa = aux; 633 634 if (SIP_DECL(lookup)(pa) != NULL) 635 return (1); 636 637 return (0); 638 } 639 640 static void 641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 642 { 643 struct sip_softc *sc = (struct sip_softc *) self; 644 struct pci_attach_args *pa = aux; 645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 646 pci_chipset_tag_t pc = pa->pa_pc; 647 pci_intr_handle_t ih; 648 const char *intrstr = NULL; 649 bus_space_tag_t iot, memt; 650 bus_space_handle_t ioh, memh; 651 bus_dma_segment_t seg; 652 int ioh_valid, memh_valid; 653 int i, rseg, error; 654 const struct sip_product *sip; 655 pcireg_t pmode; 656 u_int8_t enaddr[ETHER_ADDR_LEN]; 657 int pmreg; 658 #ifdef DP83820 659 pcireg_t memtype; 660 u_int32_t reg; 661 #endif /* DP83820 */ 662 663 callout_init(&sc->sc_tick_ch); 664 665 sip = SIP_DECL(lookup)(pa); 666 if (sip == NULL) { 667 printf("\n"); 668 panic(SIP_STR(attach) ": impossible"); 669 } 670 sc->sc_rev = PCI_REVISION(pa->pa_class); 671 672 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 673 674 sc->sc_model = sip; 675 676 /* 677 * XXX Work-around broken PXE firmware on some boards. 678 * 679 * The DP83815 shares an address decoder with the MEM BAR 680 * and the ROM BAR. Make sure the ROM BAR is disabled, 681 * so that memory mapped access works. 682 */ 683 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 684 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 685 ~PCI_MAPREG_ROM_ENABLE); 686 687 /* 688 * Map the device. 689 */ 690 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 691 PCI_MAPREG_TYPE_IO, 0, 692 &iot, &ioh, NULL, NULL) == 0); 693 #ifdef DP83820 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 695 switch (memtype) { 696 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 697 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 698 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 699 memtype, 0, &memt, &memh, NULL, NULL) == 0); 700 break; 701 default: 702 memh_valid = 0; 703 } 704 #else 705 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 706 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 707 &memt, &memh, NULL, NULL) == 0); 708 #endif /* DP83820 */ 709 710 if (memh_valid) { 711 sc->sc_st = memt; 712 sc->sc_sh = memh; 713 } else if (ioh_valid) { 714 sc->sc_st = iot; 715 sc->sc_sh = ioh; 716 } else { 717 printf("%s: unable to map device registers\n", 718 sc->sc_dev.dv_xname); 719 return; 720 } 721 722 sc->sc_dmat = pa->pa_dmat; 723 724 /* 725 * Make sure bus mastering is enabled. Also make sure 726 * Write/Invalidate is enabled if we're allowed to use it. 727 */ 728 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 729 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 730 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 732 pmreg | PCI_COMMAND_MASTER_ENABLE); 733 734 /* Get it out of power save mode if needed. */ 735 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 736 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 737 PCI_PMCSR_STATE_MASK; 738 if (pmode == PCI_PMCSR_STATE_D3) { 739 /* 740 * The card has lost all configuration data in 741 * this state, so punt. 742 */ 743 printf("%s: unable to wake up from power state D3\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (pmode != PCI_PMCSR_STATE_D0) { 748 printf("%s: waking up from power state D%d\n", 749 sc->sc_dev.dv_xname, pmode); 750 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 751 PCI_PMCSR_STATE_D0); 752 } 753 } 754 755 /* 756 * Map and establish our interrupt. 757 */ 758 if (pci_intr_map(pa, &ih)) { 759 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 764 if (sc->sc_ih == NULL) { 765 printf("%s: unable to establish interrupt", 766 sc->sc_dev.dv_xname); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 return; 771 } 772 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 773 774 SIMPLEQ_INIT(&sc->sc_txfreeq); 775 SIMPLEQ_INIT(&sc->sc_txdirtyq); 776 777 /* 778 * Allocate the control data structures, and create and load the 779 * DMA map for it. 780 */ 781 if ((error = bus_dmamem_alloc(sc->sc_dmat, 782 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 783 0)) != 0) { 784 printf("%s: unable to allocate control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_0; 787 } 788 789 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 790 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 791 BUS_DMA_COHERENT)) != 0) { 792 printf("%s: unable to map control data, error = %d\n", 793 sc->sc_dev.dv_xname, error); 794 goto fail_1; 795 } 796 797 if ((error = bus_dmamap_create(sc->sc_dmat, 798 sizeof(struct sip_control_data), 1, 799 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 800 printf("%s: unable to create control data DMA map, " 801 "error = %d\n", sc->sc_dev.dv_xname, error); 802 goto fail_2; 803 } 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 806 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 807 0)) != 0) { 808 printf("%s: unable to load control data DMA map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 goto fail_3; 811 } 812 813 /* 814 * Create the transmit buffer DMA maps. 815 */ 816 for (i = 0; i < SIP_TXQUEUELEN; i++) { 817 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 818 SIP_NTXSEGS, MCLBYTES, 0, 0, 819 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 820 printf("%s: unable to create tx DMA map %d, " 821 "error = %d\n", sc->sc_dev.dv_xname, i, error); 822 goto fail_4; 823 } 824 } 825 826 /* 827 * Create the receive buffer DMA maps. 828 */ 829 for (i = 0; i < SIP_NRXDESC; i++) { 830 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 831 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 832 printf("%s: unable to create rx DMA map %d, " 833 "error = %d\n", sc->sc_dev.dv_xname, i, error); 834 goto fail_5; 835 } 836 sc->sc_rxsoft[i].rxs_mbuf = NULL; 837 } 838 839 /* 840 * Reset the chip to a known state. 841 */ 842 SIP_DECL(reset)(sc); 843 844 /* 845 * Read the Ethernet address from the EEPROM. This might 846 * also fetch other stuff from the EEPROM and stash it 847 * in the softc. 848 */ 849 sc->sc_cfg = 0; 850 #if !defined(DP83820) 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 854 855 if (SIP_SIS900_REV(sc,SIS_REV_635) || 856 SIP_SIS900_REV(sc,SIS_REV_960) || 857 SIP_SIS900_REV(sc,SIS_REV_900B)) 858 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 859 SIP_CFG) & CFG_EDBMASTEN); 860 #endif 861 862 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 863 864 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 865 ether_sprintf(enaddr)); 866 867 /* 868 * Initialize the configuration register: aggressive PCI 869 * bus request algorithm, default backoff, default OW timer, 870 * default parity error detection. 871 * 872 * NOTE: "Big endian mode" is useless on the SiS900 and 873 * friends -- it affects packet data, not descriptors. 874 */ 875 #ifdef DP83820 876 /* 877 * Cause the chip to load configuration data from the EEPROM. 878 */ 879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 880 for (i = 0; i < 10000; i++) { 881 delay(10); 882 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) == 0) 884 break; 885 } 886 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 887 PTSCR_EELOAD_EN) { 888 printf("%s: timeout loading configuration from EEPROM\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 893 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 894 895 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 896 if (reg & CFG_PCI64_DET) { 897 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 898 /* 899 * Check to see if this card is 64-bit. If so, enable 64-bit 900 * data transfers. 901 * 902 * We can't use the DATA64_EN bit in the EEPROM, because 903 * vendors of 32-bit cards fail to clear that bit in many 904 * cases (yet the card still detects that it's in a 64-bit 905 * slot; go figure). 906 */ 907 if (SIP_DECL(check_64bit)(pa)) { 908 sc->sc_cfg |= CFG_DATA64_EN; 909 printf(", using 64-bit data transfers"); 910 } 911 printf("\n"); 912 } 913 914 /* 915 * XXX Need some PCI flags indicating support for 916 * XXX 64-bit addressing. 917 */ 918 #if 0 919 if (reg & CFG_M64ADDR) 920 sc->sc_cfg |= CFG_M64ADDR; 921 if (reg & CFG_T64ADDR) 922 sc->sc_cfg |= CFG_T64ADDR; 923 #endif 924 925 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 926 const char *sep = ""; 927 printf("%s: using ", sc->sc_dev.dv_xname); 928 if (reg & CFG_EXT_125) { 929 sc->sc_cfg |= CFG_EXT_125; 930 printf("%s125MHz clock", sep); 931 sep = ", "; 932 } 933 if (reg & CFG_TBI_EN) { 934 sc->sc_cfg |= CFG_TBI_EN; 935 printf("%sten-bit interface", sep); 936 sep = ", "; 937 } 938 printf("\n"); 939 } 940 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 941 (reg & CFG_MRM_DIS) != 0) 942 sc->sc_cfg |= CFG_MRM_DIS; 943 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 944 (reg & CFG_MWI_DIS) != 0) 945 sc->sc_cfg |= CFG_MWI_DIS; 946 947 /* 948 * Use the extended descriptor format on the DP83820. This 949 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 950 * checksumming. 951 */ 952 sc->sc_cfg |= CFG_EXTSTS_EN; 953 #endif /* DP83820 */ 954 955 /* 956 * Initialize our media structures and probe the MII. 957 */ 958 sc->sc_mii.mii_ifp = ifp; 959 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 960 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 961 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 962 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 963 SIP_DECL(mediastatus)); 964 965 /* 966 * XXX We cannot handle flow control on the DP83815. 967 */ 968 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, 0); 971 else 972 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, MIIF_DOPAUSE); 974 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 975 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 977 } else 978 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 979 980 ifp = &sc->sc_ethercom.ec_if; 981 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 982 ifp->if_softc = sc; 983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 984 sc->sc_if_flags = ifp->if_flags; 985 ifp->if_ioctl = SIP_DECL(ioctl); 986 ifp->if_start = SIP_DECL(start); 987 ifp->if_watchdog = SIP_DECL(watchdog); 988 ifp->if_init = SIP_DECL(init); 989 ifp->if_stop = SIP_DECL(stop); 990 IFQ_SET_READY(&ifp->if_snd); 991 992 /* 993 * We can support 802.1Q VLAN-sized frames. 994 */ 995 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 996 997 #ifdef DP83820 998 /* 999 * And the DP83820 can do VLAN tagging in hardware, and 1000 * support the jumbo Ethernet MTU. 1001 */ 1002 sc->sc_ethercom.ec_capabilities |= 1003 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1004 1005 /* 1006 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1007 * in hardware. 1008 */ 1009 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1010 IFCAP_CSUM_UDPv4; 1011 #endif /* DP83820 */ 1012 1013 /* 1014 * Attach the interface. 1015 */ 1016 if_attach(ifp); 1017 ether_ifattach(ifp, enaddr); 1018 #if NRND > 0 1019 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1020 RND_TYPE_NET, 0); 1021 #endif 1022 1023 /* 1024 * The number of bytes that must be available in 1025 * the Tx FIFO before the bus master can DMA more 1026 * data into the FIFO. 1027 */ 1028 sc->sc_tx_fill_thresh = 64 / 32; 1029 1030 /* 1031 * Start at a drain threshold of 512 bytes. We will 1032 * increase it if a DMA underrun occurs. 1033 * 1034 * XXX The minimum value of this variable should be 1035 * tuned. We may be able to improve performance 1036 * by starting with a lower value. That, however, 1037 * may trash the first few outgoing packets if the 1038 * PCI bus is saturated. 1039 */ 1040 #ifdef DP83820 1041 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1042 #else 1043 sc->sc_tx_drain_thresh = 1504 / 32; 1044 #endif 1045 1046 /* 1047 * Initialize the Rx FIFO drain threshold. 1048 * 1049 * This is in units of 8 bytes. 1050 * 1051 * We should never set this value lower than 2; 14 bytes are 1052 * required to filter the packet. 1053 */ 1054 sc->sc_rx_drain_thresh = 128 / 8; 1055 1056 #ifdef SIP_EVENT_COUNTERS 1057 /* 1058 * Attach event counters. 1059 */ 1060 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1061 NULL, sc->sc_dev.dv_xname, "txsstall"); 1062 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txdstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1065 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txdintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txiintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "rxintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "hiberr"); 1074 #ifndef DP83820 1075 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1076 NULL, sc->sc_dev.dv_xname, "rxpause"); 1077 #endif /* !DP83820 */ 1078 #ifdef DP83820 1079 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1080 NULL, sc->sc_dev.dv_xname, "rxpause"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "txpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "txipsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1095 #endif /* DP83820 */ 1096 #endif /* SIP_EVENT_COUNTERS */ 1097 1098 /* 1099 * Make sure the interface is shutdown during reboot. 1100 */ 1101 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1102 if (sc->sc_sdhook == NULL) 1103 printf("%s: WARNING: unable to establish shutdown hook\n", 1104 sc->sc_dev.dv_xname); 1105 return; 1106 1107 /* 1108 * Free any resources we've allocated during the failed attach 1109 * attempt. Do this in reverse order and fall through. 1110 */ 1111 fail_5: 1112 for (i = 0; i < SIP_NRXDESC; i++) { 1113 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1114 bus_dmamap_destroy(sc->sc_dmat, 1115 sc->sc_rxsoft[i].rxs_dmamap); 1116 } 1117 fail_4: 1118 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1119 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1120 bus_dmamap_destroy(sc->sc_dmat, 1121 sc->sc_txsoft[i].txs_dmamap); 1122 } 1123 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1124 fail_3: 1125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_2: 1127 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1128 sizeof(struct sip_control_data)); 1129 fail_1: 1130 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1131 fail_0: 1132 return; 1133 } 1134 1135 /* 1136 * sip_shutdown: 1137 * 1138 * Make sure the interface is stopped at reboot time. 1139 */ 1140 static void 1141 SIP_DECL(shutdown)(void *arg) 1142 { 1143 struct sip_softc *sc = arg; 1144 1145 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1146 } 1147 1148 /* 1149 * sip_start: [ifnet interface function] 1150 * 1151 * Start packet transmission on the interface. 1152 */ 1153 static void 1154 SIP_DECL(start)(struct ifnet *ifp) 1155 { 1156 struct sip_softc *sc = ifp->if_softc; 1157 struct mbuf *m0; 1158 #ifndef DP83820 1159 struct mbuf *m; 1160 #endif 1161 struct sip_txsoft *txs; 1162 bus_dmamap_t dmamap; 1163 int error, nexttx, lasttx, seg; 1164 int ofree = sc->sc_txfree; 1165 #if 0 1166 int firsttx = sc->sc_txnext; 1167 #endif 1168 #ifdef DP83820 1169 struct m_tag *mtag; 1170 u_int32_t extsts; 1171 #endif 1172 1173 #ifndef DP83820 1174 /* 1175 * If we've been told to pause, don't transmit any more packets. 1176 */ 1177 if (sc->sc_paused) 1178 ifp->if_flags |= IFF_OACTIVE; 1179 #endif 1180 1181 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1182 return; 1183 1184 /* 1185 * Loop through the send queue, setting up transmit descriptors 1186 * until we drain the queue, or use up all available transmit 1187 * descriptors. 1188 */ 1189 for (;;) { 1190 /* Get a work queue entry. */ 1191 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1192 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1193 break; 1194 } 1195 1196 /* 1197 * Grab a packet off the queue. 1198 */ 1199 IFQ_POLL(&ifp->if_snd, m0); 1200 if (m0 == NULL) 1201 break; 1202 #ifndef DP83820 1203 m = NULL; 1204 #endif 1205 1206 dmamap = txs->txs_dmamap; 1207 1208 #ifdef DP83820 1209 /* 1210 * Load the DMA map. If this fails, the packet either 1211 * didn't fit in the allotted number of segments, or we 1212 * were short on resources. For the too-many-segments 1213 * case, we simply report an error and drop the packet, 1214 * since we can't sanely copy a jumbo packet to a single 1215 * buffer. 1216 */ 1217 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1218 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1219 if (error) { 1220 if (error == EFBIG) { 1221 printf("%s: Tx packet consumes too many " 1222 "DMA segments, dropping...\n", 1223 sc->sc_dev.dv_xname); 1224 IFQ_DEQUEUE(&ifp->if_snd, m0); 1225 m_freem(m0); 1226 continue; 1227 } 1228 /* 1229 * Short on resources, just stop for now. 1230 */ 1231 break; 1232 } 1233 #else /* DP83820 */ 1234 /* 1235 * Load the DMA map. If this fails, the packet either 1236 * didn't fit in the alloted number of segments, or we 1237 * were short on resources. In this case, we'll copy 1238 * and try again. 1239 */ 1240 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1241 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1242 MGETHDR(m, M_DONTWAIT, MT_DATA); 1243 if (m == NULL) { 1244 printf("%s: unable to allocate Tx mbuf\n", 1245 sc->sc_dev.dv_xname); 1246 break; 1247 } 1248 if (m0->m_pkthdr.len > MHLEN) { 1249 MCLGET(m, M_DONTWAIT); 1250 if ((m->m_flags & M_EXT) == 0) { 1251 printf("%s: unable to allocate Tx " 1252 "cluster\n", sc->sc_dev.dv_xname); 1253 m_freem(m); 1254 break; 1255 } 1256 } 1257 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1258 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1259 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1260 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1261 if (error) { 1262 printf("%s: unable to load Tx buffer, " 1263 "error = %d\n", sc->sc_dev.dv_xname, error); 1264 break; 1265 } 1266 } 1267 #endif /* DP83820 */ 1268 1269 /* 1270 * Ensure we have enough descriptors free to describe 1271 * the packet. Note, we always reserve one descriptor 1272 * at the end of the ring as a termination point, to 1273 * prevent wrap-around. 1274 */ 1275 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1276 /* 1277 * Not enough free descriptors to transmit this 1278 * packet. We haven't committed anything yet, 1279 * so just unload the DMA map, put the packet 1280 * back on the queue, and punt. Notify the upper 1281 * layer that there are not more slots left. 1282 * 1283 * XXX We could allocate an mbuf and copy, but 1284 * XXX is it worth it? 1285 */ 1286 ifp->if_flags |= IFF_OACTIVE; 1287 bus_dmamap_unload(sc->sc_dmat, dmamap); 1288 #ifndef DP83820 1289 if (m != NULL) 1290 m_freem(m); 1291 #endif 1292 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1293 break; 1294 } 1295 1296 IFQ_DEQUEUE(&ifp->if_snd, m0); 1297 #ifndef DP83820 1298 if (m != NULL) { 1299 m_freem(m0); 1300 m0 = m; 1301 } 1302 #endif 1303 1304 /* 1305 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1306 */ 1307 1308 /* Sync the DMA map. */ 1309 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 /* 1313 * Initialize the transmit descriptors. 1314 */ 1315 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1316 seg < dmamap->dm_nsegs; 1317 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1318 /* 1319 * If this is the first descriptor we're 1320 * enqueueing, don't set the OWN bit just 1321 * yet. That could cause a race condition. 1322 * We'll do it below. 1323 */ 1324 sc->sc_txdescs[nexttx].sipd_bufptr = 1325 htole32(dmamap->dm_segs[seg].ds_addr); 1326 sc->sc_txdescs[nexttx].sipd_cmdsts = 1327 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1328 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1329 #ifdef DP83820 1330 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1331 #endif /* DP83820 */ 1332 lasttx = nexttx; 1333 } 1334 1335 /* Clear the MORE bit on the last segment. */ 1336 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1337 1338 /* 1339 * If we're in the interrupt delay window, delay the 1340 * interrupt. 1341 */ 1342 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1343 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1344 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1345 htole32(CMDSTS_INTR); 1346 sc->sc_txwin = 0; 1347 } 1348 1349 #ifdef DP83820 1350 /* 1351 * If VLANs are enabled and the packet has a VLAN tag, set 1352 * up the descriptor to encapsulate the packet for us. 1353 * 1354 * This apparently has to be on the last descriptor of 1355 * the packet. 1356 */ 1357 1358 /* 1359 * Byte swapping is tricky. We need to provide the tag 1360 * in a network byte order. On a big-endian machine, 1361 * the byteorder is correct, but we need to swap it 1362 * anyway, because this will be undone by the outside 1363 * htole32(). That's why there must be an 1364 * unconditional swap instead of htons() inside. 1365 */ 1366 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1367 sc->sc_txdescs[lasttx].sipd_extsts |= 1368 htole32(EXTSTS_VPKT | 1369 (bswap16(VLAN_TAG_VALUE(mtag)) & 1370 EXTSTS_VTCI)); 1371 } 1372 1373 /* 1374 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1375 * checksumming, set up the descriptor to do this work 1376 * for us. 1377 * 1378 * This apparently has to be on the first descriptor of 1379 * the packet. 1380 * 1381 * Byte-swap constants so the compiler can optimize. 1382 */ 1383 extsts = 0; 1384 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1385 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1386 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1387 extsts |= htole32(EXTSTS_IPPKT); 1388 } 1389 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1390 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1391 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1392 extsts |= htole32(EXTSTS_TCPPKT); 1393 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1394 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1395 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1396 extsts |= htole32(EXTSTS_UDPPKT); 1397 } 1398 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1399 #endif /* DP83820 */ 1400 1401 /* Sync the descriptors we're using. */ 1402 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1403 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1404 1405 /* 1406 * The entire packet is set up. Give the first descrptor 1407 * to the chip now. 1408 */ 1409 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1410 htole32(CMDSTS_OWN); 1411 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1412 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1413 1414 /* 1415 * Store a pointer to the packet so we can free it later, 1416 * and remember what txdirty will be once the packet is 1417 * done. 1418 */ 1419 txs->txs_mbuf = m0; 1420 txs->txs_firstdesc = sc->sc_txnext; 1421 txs->txs_lastdesc = lasttx; 1422 1423 /* Advance the tx pointer. */ 1424 sc->sc_txfree -= dmamap->dm_nsegs; 1425 sc->sc_txnext = nexttx; 1426 1427 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1428 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1429 1430 #if NBPFILTER > 0 1431 /* 1432 * Pass the packet to any BPF listeners. 1433 */ 1434 if (ifp->if_bpf) 1435 bpf_mtap(ifp->if_bpf, m0); 1436 #endif /* NBPFILTER > 0 */ 1437 } 1438 1439 if (txs == NULL || sc->sc_txfree == 0) { 1440 /* No more slots left; notify upper layer. */ 1441 ifp->if_flags |= IFF_OACTIVE; 1442 } 1443 1444 if (sc->sc_txfree != ofree) { 1445 /* 1446 * Start the transmit process. Note, the manual says 1447 * that if there are no pending transmissions in the 1448 * chip's internal queue (indicated by TXE being clear), 1449 * then the driver software must set the TXDP to the 1450 * first descriptor to be transmitted. However, if we 1451 * do this, it causes serious performance degredation on 1452 * the DP83820 under load, not setting TXDP doesn't seem 1453 * to adversely affect the SiS 900 or DP83815. 1454 * 1455 * Well, I guess it wouldn't be the first time a manual 1456 * has lied -- and they could be speaking of the NULL- 1457 * terminated descriptor list case, rather than OWN- 1458 * terminated rings. 1459 */ 1460 #if 0 1461 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1462 CR_TXE) == 0) { 1463 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1464 SIP_CDTXADDR(sc, firsttx)); 1465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1466 } 1467 #else 1468 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1469 #endif 1470 1471 /* Set a watchdog timer in case the chip flakes out. */ 1472 #ifdef DP83820 1473 /* Gigabit autonegotiation takes 5 seconds. */ 1474 ifp->if_timer = 10; 1475 #else 1476 ifp->if_timer = 5; 1477 #endif 1478 } 1479 } 1480 1481 /* 1482 * sip_watchdog: [ifnet interface function] 1483 * 1484 * Watchdog timer handler. 1485 */ 1486 static void 1487 SIP_DECL(watchdog)(struct ifnet *ifp) 1488 { 1489 struct sip_softc *sc = ifp->if_softc; 1490 1491 /* 1492 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1493 * If we get a timeout, try and sweep up transmit descriptors. 1494 * If we manage to sweep them all up, ignore the lack of 1495 * interrupt. 1496 */ 1497 SIP_DECL(txintr)(sc); 1498 1499 if (sc->sc_txfree != SIP_NTXDESC) { 1500 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1501 ifp->if_oerrors++; 1502 1503 /* Reset the interface. */ 1504 (void) SIP_DECL(init)(ifp); 1505 } else if (ifp->if_flags & IFF_DEBUG) 1506 printf("%s: recovered from device timeout\n", 1507 sc->sc_dev.dv_xname); 1508 1509 /* Try to get more packets going. */ 1510 SIP_DECL(start)(ifp); 1511 } 1512 1513 /* 1514 * sip_ioctl: [ifnet interface function] 1515 * 1516 * Handle control requests from the operator. 1517 */ 1518 static int 1519 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1520 { 1521 struct sip_softc *sc = ifp->if_softc; 1522 struct ifreq *ifr = (struct ifreq *)data; 1523 int s, error; 1524 1525 s = splnet(); 1526 1527 switch (cmd) { 1528 case SIOCSIFMEDIA: 1529 /* Flow control requires full-duplex mode. */ 1530 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1531 (ifr->ifr_media & IFM_FDX) == 0) 1532 ifr->ifr_media &= ~IFM_ETH_FMASK; 1533 #ifdef DP83820 1534 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1535 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1536 /* We can do both TXPAUSE and RXPAUSE. */ 1537 ifr->ifr_media |= 1538 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1539 } 1540 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1541 } 1542 #else 1543 /* XXX */ 1544 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1545 ifr->ifr_media &= ~IFM_ETH_FMASK; 1546 1547 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1548 if (ifr->ifr_media & IFM_FLOW) { 1549 /* 1550 * Both TXPAUSE and RXPAUSE must be set. 1551 * (SiS900 and DP83815 don't have PAUSE_ASYM 1552 * feature.) 1553 * 1554 * XXX Can SiS900 and DP83815 send PAUSE? 1555 */ 1556 ifr->ifr_media |= 1557 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1558 } 1559 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1560 } 1561 #endif 1562 /* FALLTHROUGH */ 1563 case SIOCGIFMEDIA: 1564 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1565 break; 1566 case SIOCSIFFLAGS: 1567 /* If the interface is up and running, only modify the receive 1568 * filter when setting promiscuous or debug mode. Otherwise 1569 * fall through to ether_ioctl, which will reset the chip. 1570 */ 1571 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1572 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1573 == (IFF_UP|IFF_RUNNING)) 1574 && ((ifp->if_flags & (~RESETIGN)) 1575 == (sc->sc_if_flags & (~RESETIGN)))) { 1576 /* Set up the receive filter. */ 1577 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1578 error = 0; 1579 break; 1580 #undef RESETIGN 1581 } 1582 /* FALLTHROUGH */ 1583 default: 1584 error = ether_ioctl(ifp, cmd, data); 1585 if (error == ENETRESET) { 1586 /* 1587 * Multicast list has changed; set the hardware filter 1588 * accordingly. 1589 */ 1590 if (ifp->if_flags & IFF_RUNNING) 1591 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1592 error = 0; 1593 } 1594 break; 1595 } 1596 1597 /* Try to get more packets going. */ 1598 SIP_DECL(start)(ifp); 1599 1600 sc->sc_if_flags = ifp->if_flags; 1601 splx(s); 1602 return (error); 1603 } 1604 1605 /* 1606 * sip_intr: 1607 * 1608 * Interrupt service routine. 1609 */ 1610 static int 1611 SIP_DECL(intr)(void *arg) 1612 { 1613 struct sip_softc *sc = arg; 1614 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1615 u_int32_t isr; 1616 int handled = 0; 1617 1618 /* Disable interrupts. */ 1619 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1620 1621 for (;;) { 1622 /* Reading clears interrupt. */ 1623 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1624 if ((isr & sc->sc_imr) == 0) 1625 break; 1626 1627 #if NRND > 0 1628 if (RND_ENABLED(&sc->rnd_source)) 1629 rnd_add_uint32(&sc->rnd_source, isr); 1630 #endif 1631 1632 handled = 1; 1633 1634 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1635 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1636 1637 /* Grab any new packets. */ 1638 SIP_DECL(rxintr)(sc); 1639 1640 if (isr & ISR_RXORN) { 1641 printf("%s: receive FIFO overrun\n", 1642 sc->sc_dev.dv_xname); 1643 1644 /* XXX adjust rx_drain_thresh? */ 1645 } 1646 1647 if (isr & ISR_RXIDLE) { 1648 printf("%s: receive ring overrun\n", 1649 sc->sc_dev.dv_xname); 1650 1651 /* Get the receive process going again. */ 1652 bus_space_write_4(sc->sc_st, sc->sc_sh, 1653 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1654 bus_space_write_4(sc->sc_st, sc->sc_sh, 1655 SIP_CR, CR_RXE); 1656 } 1657 } 1658 1659 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1660 #ifdef SIP_EVENT_COUNTERS 1661 if (isr & ISR_TXDESC) 1662 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1663 else if (isr & ISR_TXIDLE) 1664 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1665 #endif 1666 1667 /* Sweep up transmit descriptors. */ 1668 SIP_DECL(txintr)(sc); 1669 1670 if (isr & ISR_TXURN) { 1671 u_int32_t thresh; 1672 1673 printf("%s: transmit FIFO underrun", 1674 sc->sc_dev.dv_xname); 1675 1676 thresh = sc->sc_tx_drain_thresh + 1; 1677 if (thresh <= TXCFG_DRTH && 1678 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1679 (sc->sc_tx_fill_thresh * 32))) { 1680 printf("; increasing Tx drain " 1681 "threshold to %u bytes\n", 1682 thresh * 32); 1683 sc->sc_tx_drain_thresh = thresh; 1684 (void) SIP_DECL(init)(ifp); 1685 } else { 1686 (void) SIP_DECL(init)(ifp); 1687 printf("\n"); 1688 } 1689 } 1690 } 1691 1692 #if !defined(DP83820) 1693 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1694 if (isr & ISR_PAUSE_ST) { 1695 sc->sc_paused = 1; 1696 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1697 ifp->if_flags |= IFF_OACTIVE; 1698 } 1699 if (isr & ISR_PAUSE_END) { 1700 sc->sc_paused = 0; 1701 ifp->if_flags &= ~IFF_OACTIVE; 1702 } 1703 } 1704 #endif /* ! DP83820 */ 1705 1706 if (isr & ISR_HIBERR) { 1707 int want_init = 0; 1708 1709 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1710 1711 #define PRINTERR(bit, str) \ 1712 do { \ 1713 if ((isr & (bit)) != 0) { \ 1714 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1715 printf("%s: %s\n", \ 1716 sc->sc_dev.dv_xname, str); \ 1717 want_init = 1; \ 1718 } \ 1719 } while (/*CONSTCOND*/0) 1720 1721 PRINTERR(ISR_DPERR, "parity error"); 1722 PRINTERR(ISR_SSERR, "system error"); 1723 PRINTERR(ISR_RMABT, "master abort"); 1724 PRINTERR(ISR_RTABT, "target abort"); 1725 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1726 /* 1727 * Ignore: 1728 * Tx reset complete 1729 * Rx reset complete 1730 */ 1731 if (want_init) 1732 (void) SIP_DECL(init)(ifp); 1733 #undef PRINTERR 1734 } 1735 } 1736 1737 /* Re-enable interrupts. */ 1738 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1739 1740 /* Try to get more packets going. */ 1741 SIP_DECL(start)(ifp); 1742 1743 return (handled); 1744 } 1745 1746 /* 1747 * sip_txintr: 1748 * 1749 * Helper; handle transmit interrupts. 1750 */ 1751 static void 1752 SIP_DECL(txintr)(struct sip_softc *sc) 1753 { 1754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1755 struct sip_txsoft *txs; 1756 u_int32_t cmdsts; 1757 1758 #ifndef DP83820 1759 if (sc->sc_paused == 0) 1760 #endif 1761 ifp->if_flags &= ~IFF_OACTIVE; 1762 1763 /* 1764 * Go through our Tx list and free mbufs for those 1765 * frames which have been transmitted. 1766 */ 1767 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1768 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1769 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1770 1771 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1772 if (cmdsts & CMDSTS_OWN) 1773 break; 1774 1775 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1776 1777 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1778 1779 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1780 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1781 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1782 m_freem(txs->txs_mbuf); 1783 txs->txs_mbuf = NULL; 1784 1785 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1786 1787 /* 1788 * Check for errors and collisions. 1789 */ 1790 if (cmdsts & 1791 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1792 ifp->if_oerrors++; 1793 if (cmdsts & CMDSTS_Tx_EC) 1794 ifp->if_collisions += 16; 1795 if (ifp->if_flags & IFF_DEBUG) { 1796 if (cmdsts & CMDSTS_Tx_ED) 1797 printf("%s: excessive deferral\n", 1798 sc->sc_dev.dv_xname); 1799 if (cmdsts & CMDSTS_Tx_EC) 1800 printf("%s: excessive collisions\n", 1801 sc->sc_dev.dv_xname); 1802 } 1803 } else { 1804 /* Packet was transmitted successfully. */ 1805 ifp->if_opackets++; 1806 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1807 } 1808 } 1809 1810 /* 1811 * If there are no more pending transmissions, cancel the watchdog 1812 * timer. 1813 */ 1814 if (txs == NULL) { 1815 ifp->if_timer = 0; 1816 sc->sc_txwin = 0; 1817 } 1818 } 1819 1820 #if defined(DP83820) 1821 /* 1822 * sip_rxintr: 1823 * 1824 * Helper; handle receive interrupts. 1825 */ 1826 static void 1827 SIP_DECL(rxintr)(struct sip_softc *sc) 1828 { 1829 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1830 struct sip_rxsoft *rxs; 1831 struct mbuf *m; 1832 u_int32_t cmdsts, extsts; 1833 int i, len; 1834 1835 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1836 rxs = &sc->sc_rxsoft[i]; 1837 1838 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1839 1840 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1841 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1842 len = CMDSTS_SIZE(cmdsts); 1843 1844 /* 1845 * NOTE: OWN is set if owned by _consumer_. We're the 1846 * consumer of the receive ring, so if the bit is clear, 1847 * we have processed all of the packets. 1848 */ 1849 if ((cmdsts & CMDSTS_OWN) == 0) { 1850 /* 1851 * We have processed all of the receive buffers. 1852 */ 1853 break; 1854 } 1855 1856 if (__predict_false(sc->sc_rxdiscard)) { 1857 SIP_INIT_RXDESC(sc, i); 1858 if ((cmdsts & CMDSTS_MORE) == 0) { 1859 /* Reset our state. */ 1860 sc->sc_rxdiscard = 0; 1861 } 1862 continue; 1863 } 1864 1865 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1866 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1867 1868 m = rxs->rxs_mbuf; 1869 1870 /* 1871 * Add a new receive buffer to the ring. 1872 */ 1873 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1874 /* 1875 * Failed, throw away what we've done so 1876 * far, and discard the rest of the packet. 1877 */ 1878 ifp->if_ierrors++; 1879 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1880 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1881 SIP_INIT_RXDESC(sc, i); 1882 if (cmdsts & CMDSTS_MORE) 1883 sc->sc_rxdiscard = 1; 1884 if (sc->sc_rxhead != NULL) 1885 m_freem(sc->sc_rxhead); 1886 SIP_RXCHAIN_RESET(sc); 1887 continue; 1888 } 1889 1890 SIP_RXCHAIN_LINK(sc, m); 1891 1892 m->m_len = len; 1893 1894 /* 1895 * If this is not the end of the packet, keep 1896 * looking. 1897 */ 1898 if (cmdsts & CMDSTS_MORE) { 1899 sc->sc_rxlen += len; 1900 continue; 1901 } 1902 1903 /* 1904 * Okay, we have the entire packet now. The chip includes 1905 * the FCS, so we need to trim it. 1906 */ 1907 m->m_len -= ETHER_CRC_LEN; 1908 1909 *sc->sc_rxtailp = NULL; 1910 len = m->m_len + sc->sc_rxlen; 1911 m = sc->sc_rxhead; 1912 1913 SIP_RXCHAIN_RESET(sc); 1914 1915 /* 1916 * If an error occurred, update stats and drop the packet. 1917 */ 1918 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1919 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1920 ifp->if_ierrors++; 1921 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1922 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1923 /* Receive overrun handled elsewhere. */ 1924 printf("%s: receive descriptor error\n", 1925 sc->sc_dev.dv_xname); 1926 } 1927 #define PRINTERR(bit, str) \ 1928 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1929 (cmdsts & (bit)) != 0) \ 1930 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1931 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1932 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1933 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1934 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1935 #undef PRINTERR 1936 m_freem(m); 1937 continue; 1938 } 1939 1940 /* 1941 * If the packet is small enough to fit in a 1942 * single header mbuf, allocate one and copy 1943 * the data into it. This greatly reduces 1944 * memory consumption when we receive lots 1945 * of small packets. 1946 */ 1947 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1948 struct mbuf *nm; 1949 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1950 if (nm == NULL) { 1951 ifp->if_ierrors++; 1952 m_freem(m); 1953 continue; 1954 } 1955 nm->m_data += 2; 1956 nm->m_pkthdr.len = nm->m_len = len; 1957 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1958 m_freem(m); 1959 m = nm; 1960 } 1961 #ifndef __NO_STRICT_ALIGNMENT 1962 else { 1963 /* 1964 * The DP83820's receive buffers must be 4-byte 1965 * aligned. But this means that the data after 1966 * the Ethernet header is misaligned. To compensate, 1967 * we have artificially shortened the buffer size 1968 * in the descriptor, and we do an overlapping copy 1969 * of the data two bytes further in (in the first 1970 * buffer of the chain only). 1971 */ 1972 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1973 m->m_len); 1974 m->m_data += 2; 1975 } 1976 #endif /* ! __NO_STRICT_ALIGNMENT */ 1977 1978 /* 1979 * If VLANs are enabled, VLAN packets have been unwrapped 1980 * for us. Associate the tag with the packet. 1981 */ 1982 1983 /* 1984 * Again, byte swapping is tricky. Hardware provided 1985 * the tag in the network byte order, but extsts was 1986 * passed through le32toh() in the meantime. On a 1987 * big-endian machine, we need to swap it again. On a 1988 * little-endian machine, we need to convert from the 1989 * network to host byte order. This means that we must 1990 * swap it in any case, so unconditional swap instead 1991 * of htons() is used. 1992 */ 1993 if ((extsts & EXTSTS_VPKT) != 0) { 1994 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 1995 continue); 1996 } 1997 1998 /* 1999 * Set the incoming checksum information for the 2000 * packet. 2001 */ 2002 if ((extsts & EXTSTS_IPPKT) != 0) { 2003 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2004 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2005 if (extsts & EXTSTS_Rx_IPERR) 2006 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2007 if (extsts & EXTSTS_TCPPKT) { 2008 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2009 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2010 if (extsts & EXTSTS_Rx_TCPERR) 2011 m->m_pkthdr.csum_flags |= 2012 M_CSUM_TCP_UDP_BAD; 2013 } else if (extsts & EXTSTS_UDPPKT) { 2014 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2015 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2016 if (extsts & EXTSTS_Rx_UDPERR) 2017 m->m_pkthdr.csum_flags |= 2018 M_CSUM_TCP_UDP_BAD; 2019 } 2020 } 2021 2022 ifp->if_ipackets++; 2023 m->m_pkthdr.rcvif = ifp; 2024 m->m_pkthdr.len = len; 2025 2026 #if NBPFILTER > 0 2027 /* 2028 * Pass this up to any BPF listeners, but only 2029 * pass if up the stack if it's for us. 2030 */ 2031 if (ifp->if_bpf) 2032 bpf_mtap(ifp->if_bpf, m); 2033 #endif /* NBPFILTER > 0 */ 2034 2035 /* Pass it on. */ 2036 (*ifp->if_input)(ifp, m); 2037 } 2038 2039 /* Update the receive pointer. */ 2040 sc->sc_rxptr = i; 2041 } 2042 #else /* ! DP83820 */ 2043 /* 2044 * sip_rxintr: 2045 * 2046 * Helper; handle receive interrupts. 2047 */ 2048 static void 2049 SIP_DECL(rxintr)(struct sip_softc *sc) 2050 { 2051 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2052 struct sip_rxsoft *rxs; 2053 struct mbuf *m; 2054 u_int32_t cmdsts; 2055 int i, len; 2056 2057 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2058 rxs = &sc->sc_rxsoft[i]; 2059 2060 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2061 2062 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2063 2064 /* 2065 * NOTE: OWN is set if owned by _consumer_. We're the 2066 * consumer of the receive ring, so if the bit is clear, 2067 * we have processed all of the packets. 2068 */ 2069 if ((cmdsts & CMDSTS_OWN) == 0) { 2070 /* 2071 * We have processed all of the receive buffers. 2072 */ 2073 break; 2074 } 2075 2076 /* 2077 * If any collisions were seen on the wire, count one. 2078 */ 2079 if (cmdsts & CMDSTS_Rx_COL) 2080 ifp->if_collisions++; 2081 2082 /* 2083 * If an error occurred, update stats, clear the status 2084 * word, and leave the packet buffer in place. It will 2085 * simply be reused the next time the ring comes around. 2086 */ 2087 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2088 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2089 ifp->if_ierrors++; 2090 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2091 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2092 /* Receive overrun handled elsewhere. */ 2093 printf("%s: receive descriptor error\n", 2094 sc->sc_dev.dv_xname); 2095 } 2096 #define PRINTERR(bit, str) \ 2097 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2098 (cmdsts & (bit)) != 0) \ 2099 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2100 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2101 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2102 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2103 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2104 #undef PRINTERR 2105 SIP_INIT_RXDESC(sc, i); 2106 continue; 2107 } 2108 2109 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2110 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2111 2112 /* 2113 * No errors; receive the packet. Note, the SiS 900 2114 * includes the CRC with every packet. 2115 */ 2116 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2117 2118 #ifdef __NO_STRICT_ALIGNMENT 2119 /* 2120 * If the packet is small enough to fit in a 2121 * single header mbuf, allocate one and copy 2122 * the data into it. This greatly reduces 2123 * memory consumption when we receive lots 2124 * of small packets. 2125 * 2126 * Otherwise, we add a new buffer to the receive 2127 * chain. If this fails, we drop the packet and 2128 * recycle the old buffer. 2129 */ 2130 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2131 MGETHDR(m, M_DONTWAIT, MT_DATA); 2132 if (m == NULL) 2133 goto dropit; 2134 memcpy(mtod(m, caddr_t), 2135 mtod(rxs->rxs_mbuf, caddr_t), len); 2136 SIP_INIT_RXDESC(sc, i); 2137 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2138 rxs->rxs_dmamap->dm_mapsize, 2139 BUS_DMASYNC_PREREAD); 2140 } else { 2141 m = rxs->rxs_mbuf; 2142 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2143 dropit: 2144 ifp->if_ierrors++; 2145 SIP_INIT_RXDESC(sc, i); 2146 bus_dmamap_sync(sc->sc_dmat, 2147 rxs->rxs_dmamap, 0, 2148 rxs->rxs_dmamap->dm_mapsize, 2149 BUS_DMASYNC_PREREAD); 2150 continue; 2151 } 2152 } 2153 #else 2154 /* 2155 * The SiS 900's receive buffers must be 4-byte aligned. 2156 * But this means that the data after the Ethernet header 2157 * is misaligned. We must allocate a new buffer and 2158 * copy the data, shifted forward 2 bytes. 2159 */ 2160 MGETHDR(m, M_DONTWAIT, MT_DATA); 2161 if (m == NULL) { 2162 dropit: 2163 ifp->if_ierrors++; 2164 SIP_INIT_RXDESC(sc, i); 2165 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2166 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2167 continue; 2168 } 2169 if (len > (MHLEN - 2)) { 2170 MCLGET(m, M_DONTWAIT); 2171 if ((m->m_flags & M_EXT) == 0) { 2172 m_freem(m); 2173 goto dropit; 2174 } 2175 } 2176 m->m_data += 2; 2177 2178 /* 2179 * Note that we use clusters for incoming frames, so the 2180 * buffer is virtually contiguous. 2181 */ 2182 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2183 2184 /* Allow the receive descriptor to continue using its mbuf. */ 2185 SIP_INIT_RXDESC(sc, i); 2186 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2187 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2188 #endif /* __NO_STRICT_ALIGNMENT */ 2189 2190 ifp->if_ipackets++; 2191 m->m_pkthdr.rcvif = ifp; 2192 m->m_pkthdr.len = m->m_len = len; 2193 2194 #if NBPFILTER > 0 2195 /* 2196 * Pass this up to any BPF listeners, but only 2197 * pass if up the stack if it's for us. 2198 */ 2199 if (ifp->if_bpf) 2200 bpf_mtap(ifp->if_bpf, m); 2201 #endif /* NBPFILTER > 0 */ 2202 2203 /* Pass it on. */ 2204 (*ifp->if_input)(ifp, m); 2205 } 2206 2207 /* Update the receive pointer. */ 2208 sc->sc_rxptr = i; 2209 } 2210 #endif /* DP83820 */ 2211 2212 /* 2213 * sip_tick: 2214 * 2215 * One second timer, used to tick the MII. 2216 */ 2217 static void 2218 SIP_DECL(tick)(void *arg) 2219 { 2220 struct sip_softc *sc = arg; 2221 int s; 2222 2223 s = splnet(); 2224 #ifdef DP83820 2225 #ifdef SIP_EVENT_COUNTERS 2226 /* Read PAUSE related counts from MIB registers. */ 2227 sc->sc_ev_rxpause.ev_count += 2228 bus_space_read_4(sc->sc_st, sc->sc_sh, 2229 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2230 sc->sc_ev_txpause.ev_count += 2231 bus_space_read_4(sc->sc_st, sc->sc_sh, 2232 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2233 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2234 #endif /* SIP_EVENT_COUNTERS */ 2235 #endif /* DP83820 */ 2236 mii_tick(&sc->sc_mii); 2237 splx(s); 2238 2239 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2240 } 2241 2242 /* 2243 * sip_reset: 2244 * 2245 * Perform a soft reset on the SiS 900. 2246 */ 2247 static void 2248 SIP_DECL(reset)(struct sip_softc *sc) 2249 { 2250 bus_space_tag_t st = sc->sc_st; 2251 bus_space_handle_t sh = sc->sc_sh; 2252 int i; 2253 2254 bus_space_write_4(st, sh, SIP_IER, 0); 2255 bus_space_write_4(st, sh, SIP_IMR, 0); 2256 bus_space_write_4(st, sh, SIP_RFCR, 0); 2257 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2258 2259 for (i = 0; i < SIP_TIMEOUT; i++) { 2260 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2261 break; 2262 delay(2); 2263 } 2264 2265 if (i == SIP_TIMEOUT) 2266 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2267 2268 delay(1000); 2269 2270 #ifdef DP83820 2271 /* 2272 * Set the general purpose I/O bits. Do it here in case we 2273 * need to have GPIO set up to talk to the media interface. 2274 */ 2275 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2276 delay(1000); 2277 #endif /* DP83820 */ 2278 } 2279 2280 /* 2281 * sip_init: [ ifnet interface function ] 2282 * 2283 * Initialize the interface. Must be called at splnet(). 2284 */ 2285 static int 2286 SIP_DECL(init)(struct ifnet *ifp) 2287 { 2288 struct sip_softc *sc = ifp->if_softc; 2289 bus_space_tag_t st = sc->sc_st; 2290 bus_space_handle_t sh = sc->sc_sh; 2291 struct sip_txsoft *txs; 2292 struct sip_rxsoft *rxs; 2293 struct sip_desc *sipd; 2294 #if defined(DP83820) 2295 u_int32_t reg; 2296 #endif 2297 int i, error = 0; 2298 2299 /* 2300 * Cancel any pending I/O. 2301 */ 2302 SIP_DECL(stop)(ifp, 0); 2303 2304 /* 2305 * Reset the chip to a known state. 2306 */ 2307 SIP_DECL(reset)(sc); 2308 2309 #if !defined(DP83820) 2310 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2311 /* 2312 * DP83815 manual, page 78: 2313 * 4.4 Recommended Registers Configuration 2314 * For optimum performance of the DP83815, version noted 2315 * as DP83815CVNG (SRR = 203h), the listed register 2316 * modifications must be followed in sequence... 2317 * 2318 * It's not clear if this should be 302h or 203h because that 2319 * chip name is listed as SRR 302h in the description of the 2320 * SRR register. However, my revision 302h DP83815 on the 2321 * Netgear FA311 purchased in 02/2001 needs these settings 2322 * to avoid tons of errors in AcceptPerfectMatch (non- 2323 * IFF_PROMISC) mode. I do not know if other revisions need 2324 * this set or not. [briggs -- 09 March 2001] 2325 * 2326 * Note that only the low-order 12 bits of 0xe4 are documented 2327 * and that this sets reserved bits in that register. 2328 */ 2329 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2330 2331 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2332 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2333 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2334 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2335 2336 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2337 } 2338 #endif /* ! DP83820 */ 2339 2340 /* 2341 * Initialize the transmit descriptor ring. 2342 */ 2343 for (i = 0; i < SIP_NTXDESC; i++) { 2344 sipd = &sc->sc_txdescs[i]; 2345 memset(sipd, 0, sizeof(struct sip_desc)); 2346 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2347 } 2348 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2349 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2350 sc->sc_txfree = SIP_NTXDESC; 2351 sc->sc_txnext = 0; 2352 sc->sc_txwin = 0; 2353 2354 /* 2355 * Initialize the transmit job descriptors. 2356 */ 2357 SIMPLEQ_INIT(&sc->sc_txfreeq); 2358 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2359 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2360 txs = &sc->sc_txsoft[i]; 2361 txs->txs_mbuf = NULL; 2362 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2363 } 2364 2365 /* 2366 * Initialize the receive descriptor and receive job 2367 * descriptor rings. 2368 */ 2369 for (i = 0; i < SIP_NRXDESC; i++) { 2370 rxs = &sc->sc_rxsoft[i]; 2371 if (rxs->rxs_mbuf == NULL) { 2372 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2373 printf("%s: unable to allocate or map rx " 2374 "buffer %d, error = %d\n", 2375 sc->sc_dev.dv_xname, i, error); 2376 /* 2377 * XXX Should attempt to run with fewer receive 2378 * XXX buffers instead of just failing. 2379 */ 2380 SIP_DECL(rxdrain)(sc); 2381 goto out; 2382 } 2383 } else 2384 SIP_INIT_RXDESC(sc, i); 2385 } 2386 sc->sc_rxptr = 0; 2387 #ifdef DP83820 2388 sc->sc_rxdiscard = 0; 2389 SIP_RXCHAIN_RESET(sc); 2390 #endif /* DP83820 */ 2391 2392 /* 2393 * Set the configuration register; it's already initialized 2394 * in sip_attach(). 2395 */ 2396 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2397 2398 /* 2399 * Initialize the prototype TXCFG register. 2400 */ 2401 #if defined(DP83820) 2402 sc->sc_txcfg = TXCFG_MXDMA_512; 2403 sc->sc_rxcfg = RXCFG_MXDMA_512; 2404 #else 2405 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2406 SIP_SIS900_REV(sc, SIS_REV_960) || 2407 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2408 (sc->sc_cfg & CFG_EDBMASTEN)) { 2409 sc->sc_txcfg = TXCFG_MXDMA_64; 2410 sc->sc_rxcfg = RXCFG_MXDMA_64; 2411 } else { 2412 sc->sc_txcfg = TXCFG_MXDMA_512; 2413 sc->sc_rxcfg = RXCFG_MXDMA_512; 2414 } 2415 #endif /* DP83820 */ 2416 2417 sc->sc_txcfg |= TXCFG_ATP | 2418 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2419 sc->sc_tx_drain_thresh; 2420 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2421 2422 /* 2423 * Initialize the receive drain threshold if we have never 2424 * done so. 2425 */ 2426 if (sc->sc_rx_drain_thresh == 0) { 2427 /* 2428 * XXX This value should be tuned. This is set to the 2429 * maximum of 248 bytes, and we may be able to improve 2430 * performance by decreasing it (although we should never 2431 * set this value lower than 2; 14 bytes are required to 2432 * filter the packet). 2433 */ 2434 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2435 } 2436 2437 /* 2438 * Initialize the prototype RXCFG register. 2439 */ 2440 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2441 #ifdef DP83820 2442 /* 2443 * Accept long packets (including FCS) so we can handle 2444 * 802.1q-tagged frames and jumbo frames properly. 2445 */ 2446 if (ifp->if_mtu > ETHERMTU || 2447 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2448 sc->sc_rxcfg |= RXCFG_ALP; 2449 2450 /* 2451 * Checksum offloading is disabled if the user selects an MTU 2452 * larger than 8109. (FreeBSD says 8152, but there is emperical 2453 * evidence that >8109 does not work on some boards, such as the 2454 * Planex GN-1000TE). 2455 */ 2456 if (ifp->if_mtu > 8109 && 2457 (ifp->if_capenable & 2458 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2459 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2460 "disabled.\n", sc->sc_dev.dv_xname); 2461 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2462 IFCAP_CSUM_UDPv4); 2463 ifp->if_csum_flags_tx = 0; 2464 ifp->if_csum_flags_rx = 0; 2465 } 2466 #else 2467 /* 2468 * Accept packets >1518 bytes (including FCS) so we can handle 2469 * 802.1q-tagged frames properly. 2470 */ 2471 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2472 sc->sc_rxcfg |= RXCFG_ALP; 2473 #endif 2474 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2475 2476 #ifdef DP83820 2477 /* 2478 * Initialize the VLAN/IP receive control register. 2479 * We enable checksum computation on all incoming 2480 * packets, and do not reject packets w/ bad checksums. 2481 */ 2482 reg = 0; 2483 if (ifp->if_capenable & 2484 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2485 reg |= VRCR_IPEN; 2486 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2487 reg |= VRCR_VTDEN|VRCR_VTREN; 2488 bus_space_write_4(st, sh, SIP_VRCR, reg); 2489 2490 /* 2491 * Initialize the VLAN/IP transmit control register. 2492 * We enable outgoing checksum computation on a 2493 * per-packet basis. 2494 */ 2495 reg = 0; 2496 if (ifp->if_capenable & 2497 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2498 reg |= VTCR_PPCHK; 2499 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2500 reg |= VTCR_VPPTI; 2501 bus_space_write_4(st, sh, SIP_VTCR, reg); 2502 2503 /* 2504 * If we're using VLANs, initialize the VLAN data register. 2505 * To understand why we bswap the VLAN Ethertype, see section 2506 * 4.2.36 of the DP83820 manual. 2507 */ 2508 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2509 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2510 #endif /* DP83820 */ 2511 2512 /* 2513 * Give the transmit and receive rings to the chip. 2514 */ 2515 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2516 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2517 2518 /* 2519 * Initialize the interrupt mask. 2520 */ 2521 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2522 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2523 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2524 2525 /* Set up the receive filter. */ 2526 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2527 2528 #ifdef DP83820 2529 /* 2530 * Tune sc_rx_flow_thresh. 2531 * XXX "More than 8KB" is too short for jumbo frames. 2532 * XXX TODO: Threshold value should be user-settable. 2533 */ 2534 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2535 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2536 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2537 #endif 2538 2539 /* 2540 * Set the current media. Do this after initializing the prototype 2541 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2542 * control. 2543 */ 2544 mii_mediachg(&sc->sc_mii); 2545 2546 #ifdef DP83820 2547 /* 2548 * Set the interrupt hold-off timer to 100us. 2549 */ 2550 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2551 #endif 2552 2553 /* 2554 * Enable interrupts. 2555 */ 2556 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2557 2558 /* 2559 * Start the transmit and receive processes. 2560 */ 2561 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2562 2563 /* 2564 * Start the one second MII clock. 2565 */ 2566 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2567 2568 /* 2569 * ...all done! 2570 */ 2571 ifp->if_flags |= IFF_RUNNING; 2572 ifp->if_flags &= ~IFF_OACTIVE; 2573 sc->sc_if_flags = ifp->if_flags; 2574 2575 out: 2576 if (error) 2577 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2578 return (error); 2579 } 2580 2581 /* 2582 * sip_drain: 2583 * 2584 * Drain the receive queue. 2585 */ 2586 static void 2587 SIP_DECL(rxdrain)(struct sip_softc *sc) 2588 { 2589 struct sip_rxsoft *rxs; 2590 int i; 2591 2592 for (i = 0; i < SIP_NRXDESC; i++) { 2593 rxs = &sc->sc_rxsoft[i]; 2594 if (rxs->rxs_mbuf != NULL) { 2595 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2596 m_freem(rxs->rxs_mbuf); 2597 rxs->rxs_mbuf = NULL; 2598 } 2599 } 2600 } 2601 2602 /* 2603 * sip_stop: [ ifnet interface function ] 2604 * 2605 * Stop transmission on the interface. 2606 */ 2607 static void 2608 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2609 { 2610 struct sip_softc *sc = ifp->if_softc; 2611 bus_space_tag_t st = sc->sc_st; 2612 bus_space_handle_t sh = sc->sc_sh; 2613 struct sip_txsoft *txs; 2614 u_int32_t cmdsts = 0; /* DEBUG */ 2615 2616 /* 2617 * Stop the one second clock. 2618 */ 2619 callout_stop(&sc->sc_tick_ch); 2620 2621 /* Down the MII. */ 2622 mii_down(&sc->sc_mii); 2623 2624 /* 2625 * Disable interrupts. 2626 */ 2627 bus_space_write_4(st, sh, SIP_IER, 0); 2628 2629 /* 2630 * Stop receiver and transmitter. 2631 */ 2632 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2633 2634 /* 2635 * Release any queued transmit buffers. 2636 */ 2637 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2638 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2639 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2640 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2641 CMDSTS_INTR) == 0) 2642 printf("%s: sip_stop: last descriptor does not " 2643 "have INTR bit set\n", sc->sc_dev.dv_xname); 2644 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2645 #ifdef DIAGNOSTIC 2646 if (txs->txs_mbuf == NULL) { 2647 printf("%s: dirty txsoft with no mbuf chain\n", 2648 sc->sc_dev.dv_xname); 2649 panic("sip_stop"); 2650 } 2651 #endif 2652 cmdsts |= /* DEBUG */ 2653 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2654 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2655 m_freem(txs->txs_mbuf); 2656 txs->txs_mbuf = NULL; 2657 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2658 } 2659 2660 if (disable) 2661 SIP_DECL(rxdrain)(sc); 2662 2663 /* 2664 * Mark the interface down and cancel the watchdog timer. 2665 */ 2666 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2667 ifp->if_timer = 0; 2668 2669 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2670 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2671 printf("%s: sip_stop: no INTR bits set in dirty tx " 2672 "descriptors\n", sc->sc_dev.dv_xname); 2673 } 2674 2675 /* 2676 * sip_read_eeprom: 2677 * 2678 * Read data from the serial EEPROM. 2679 */ 2680 static void 2681 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2682 u_int16_t *data) 2683 { 2684 bus_space_tag_t st = sc->sc_st; 2685 bus_space_handle_t sh = sc->sc_sh; 2686 u_int16_t reg; 2687 int i, x; 2688 2689 for (i = 0; i < wordcnt; i++) { 2690 /* Send CHIP SELECT. */ 2691 reg = EROMAR_EECS; 2692 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2693 2694 /* Shift in the READ opcode. */ 2695 for (x = 3; x > 0; x--) { 2696 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2697 reg |= EROMAR_EEDI; 2698 else 2699 reg &= ~EROMAR_EEDI; 2700 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2701 bus_space_write_4(st, sh, SIP_EROMAR, 2702 reg | EROMAR_EESK); 2703 delay(4); 2704 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2705 delay(4); 2706 } 2707 2708 /* Shift in address. */ 2709 for (x = 6; x > 0; x--) { 2710 if ((word + i) & (1 << (x - 1))) 2711 reg |= EROMAR_EEDI; 2712 else 2713 reg &= ~EROMAR_EEDI; 2714 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2715 bus_space_write_4(st, sh, SIP_EROMAR, 2716 reg | EROMAR_EESK); 2717 delay(4); 2718 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2719 delay(4); 2720 } 2721 2722 /* Shift out data. */ 2723 reg = EROMAR_EECS; 2724 data[i] = 0; 2725 for (x = 16; x > 0; x--) { 2726 bus_space_write_4(st, sh, SIP_EROMAR, 2727 reg | EROMAR_EESK); 2728 delay(4); 2729 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2730 data[i] |= (1 << (x - 1)); 2731 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2732 delay(4); 2733 } 2734 2735 /* Clear CHIP SELECT. */ 2736 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2737 delay(4); 2738 } 2739 } 2740 2741 /* 2742 * sip_add_rxbuf: 2743 * 2744 * Add a receive buffer to the indicated descriptor. 2745 */ 2746 static int 2747 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2748 { 2749 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2750 struct mbuf *m; 2751 int error; 2752 2753 MGETHDR(m, M_DONTWAIT, MT_DATA); 2754 if (m == NULL) 2755 return (ENOBUFS); 2756 2757 MCLGET(m, M_DONTWAIT); 2758 if ((m->m_flags & M_EXT) == 0) { 2759 m_freem(m); 2760 return (ENOBUFS); 2761 } 2762 2763 #if defined(DP83820) 2764 m->m_len = SIP_RXBUF_LEN; 2765 #endif /* DP83820 */ 2766 2767 if (rxs->rxs_mbuf != NULL) 2768 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2769 2770 rxs->rxs_mbuf = m; 2771 2772 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2773 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2774 BUS_DMA_READ|BUS_DMA_NOWAIT); 2775 if (error) { 2776 printf("%s: can't load rx DMA map %d, error = %d\n", 2777 sc->sc_dev.dv_xname, idx, error); 2778 panic("sip_add_rxbuf"); /* XXX */ 2779 } 2780 2781 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2782 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2783 2784 SIP_INIT_RXDESC(sc, idx); 2785 2786 return (0); 2787 } 2788 2789 #if !defined(DP83820) 2790 /* 2791 * sip_sis900_set_filter: 2792 * 2793 * Set up the receive filter. 2794 */ 2795 static void 2796 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2797 { 2798 bus_space_tag_t st = sc->sc_st; 2799 bus_space_handle_t sh = sc->sc_sh; 2800 struct ethercom *ec = &sc->sc_ethercom; 2801 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2802 struct ether_multi *enm; 2803 u_int8_t *cp; 2804 struct ether_multistep step; 2805 u_int32_t crc, mchash[16]; 2806 2807 /* 2808 * Initialize the prototype RFCR. 2809 */ 2810 sc->sc_rfcr = RFCR_RFEN; 2811 if (ifp->if_flags & IFF_BROADCAST) 2812 sc->sc_rfcr |= RFCR_AAB; 2813 if (ifp->if_flags & IFF_PROMISC) { 2814 sc->sc_rfcr |= RFCR_AAP; 2815 goto allmulti; 2816 } 2817 2818 /* 2819 * Set up the multicast address filter by passing all multicast 2820 * addresses through a CRC generator, and then using the high-order 2821 * 6 bits as an index into the 128 bit multicast hash table (only 2822 * the lower 16 bits of each 32 bit multicast hash register are 2823 * valid). The high order bits select the register, while the 2824 * rest of the bits select the bit within the register. 2825 */ 2826 2827 memset(mchash, 0, sizeof(mchash)); 2828 2829 /* 2830 * SiS900 (at least SiS963) requires us to register the address of 2831 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2832 */ 2833 crc = 0x0ed423f9; 2834 2835 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2836 SIP_SIS900_REV(sc, SIS_REV_960) || 2837 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2838 /* Just want the 8 most significant bits. */ 2839 crc >>= 24; 2840 } else { 2841 /* Just want the 7 most significant bits. */ 2842 crc >>= 25; 2843 } 2844 2845 /* Set the corresponding bit in the hash table. */ 2846 mchash[crc >> 4] |= 1 << (crc & 0xf); 2847 2848 ETHER_FIRST_MULTI(step, ec, enm); 2849 while (enm != NULL) { 2850 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2851 /* 2852 * We must listen to a range of multicast addresses. 2853 * For now, just accept all multicasts, rather than 2854 * trying to set only those filter bits needed to match 2855 * the range. (At this time, the only use of address 2856 * ranges is for IP multicast routing, for which the 2857 * range is big enough to require all bits set.) 2858 */ 2859 goto allmulti; 2860 } 2861 2862 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2863 2864 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2865 SIP_SIS900_REV(sc, SIS_REV_960) || 2866 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2867 /* Just want the 8 most significant bits. */ 2868 crc >>= 24; 2869 } else { 2870 /* Just want the 7 most significant bits. */ 2871 crc >>= 25; 2872 } 2873 2874 /* Set the corresponding bit in the hash table. */ 2875 mchash[crc >> 4] |= 1 << (crc & 0xf); 2876 2877 ETHER_NEXT_MULTI(step, enm); 2878 } 2879 2880 ifp->if_flags &= ~IFF_ALLMULTI; 2881 goto setit; 2882 2883 allmulti: 2884 ifp->if_flags |= IFF_ALLMULTI; 2885 sc->sc_rfcr |= RFCR_AAM; 2886 2887 setit: 2888 #define FILTER_EMIT(addr, data) \ 2889 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2890 delay(1); \ 2891 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2892 delay(1) 2893 2894 /* 2895 * Disable receive filter, and program the node address. 2896 */ 2897 cp = LLADDR(ifp->if_sadl); 2898 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2899 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2900 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2901 2902 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2903 /* 2904 * Program the multicast hash table. 2905 */ 2906 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2907 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2908 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2909 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2910 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2911 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2912 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2913 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2914 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2915 SIP_SIS900_REV(sc, SIS_REV_960) || 2916 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2917 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2918 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2919 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2920 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2921 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2922 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2923 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2924 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2925 } 2926 } 2927 #undef FILTER_EMIT 2928 2929 /* 2930 * Re-enable the receiver filter. 2931 */ 2932 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2933 } 2934 #endif /* ! DP83820 */ 2935 2936 /* 2937 * sip_dp83815_set_filter: 2938 * 2939 * Set up the receive filter. 2940 */ 2941 static void 2942 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2943 { 2944 bus_space_tag_t st = sc->sc_st; 2945 bus_space_handle_t sh = sc->sc_sh; 2946 struct ethercom *ec = &sc->sc_ethercom; 2947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2948 struct ether_multi *enm; 2949 u_int8_t *cp; 2950 struct ether_multistep step; 2951 u_int32_t crc, hash, slot, bit; 2952 #ifdef DP83820 2953 #define MCHASH_NWORDS 128 2954 #else 2955 #define MCHASH_NWORDS 32 2956 #endif /* DP83820 */ 2957 u_int16_t mchash[MCHASH_NWORDS]; 2958 int i; 2959 2960 /* 2961 * Initialize the prototype RFCR. 2962 * Enable the receive filter, and accept on 2963 * Perfect (destination address) Match 2964 * If IFF_BROADCAST, also accept all broadcast packets. 2965 * If IFF_PROMISC, accept all unicast packets (and later, set 2966 * IFF_ALLMULTI and accept all multicast, too). 2967 */ 2968 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2969 if (ifp->if_flags & IFF_BROADCAST) 2970 sc->sc_rfcr |= RFCR_AAB; 2971 if (ifp->if_flags & IFF_PROMISC) { 2972 sc->sc_rfcr |= RFCR_AAP; 2973 goto allmulti; 2974 } 2975 2976 #ifdef DP83820 2977 /* 2978 * Set up the DP83820 multicast address filter by passing all multicast 2979 * addresses through a CRC generator, and then using the high-order 2980 * 11 bits as an index into the 2048 bit multicast hash table. The 2981 * high-order 7 bits select the slot, while the low-order 4 bits 2982 * select the bit within the slot. Note that only the low 16-bits 2983 * of each filter word are used, and there are 128 filter words. 2984 */ 2985 #else 2986 /* 2987 * Set up the DP83815 multicast address filter by passing all multicast 2988 * addresses through a CRC generator, and then using the high-order 2989 * 9 bits as an index into the 512 bit multicast hash table. The 2990 * high-order 5 bits select the slot, while the low-order 4 bits 2991 * select the bit within the slot. Note that only the low 16-bits 2992 * of each filter word are used, and there are 32 filter words. 2993 */ 2994 #endif /* DP83820 */ 2995 2996 memset(mchash, 0, sizeof(mchash)); 2997 2998 ifp->if_flags &= ~IFF_ALLMULTI; 2999 ETHER_FIRST_MULTI(step, ec, enm); 3000 if (enm == NULL) 3001 goto setit; 3002 while (enm != NULL) { 3003 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3004 /* 3005 * We must listen to a range of multicast addresses. 3006 * For now, just accept all multicasts, rather than 3007 * trying to set only those filter bits needed to match 3008 * the range. (At this time, the only use of address 3009 * ranges is for IP multicast routing, for which the 3010 * range is big enough to require all bits set.) 3011 */ 3012 goto allmulti; 3013 } 3014 3015 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3016 3017 #ifdef DP83820 3018 /* Just want the 11 most significant bits. */ 3019 hash = crc >> 21; 3020 #else 3021 /* Just want the 9 most significant bits. */ 3022 hash = crc >> 23; 3023 #endif /* DP83820 */ 3024 3025 slot = hash >> 4; 3026 bit = hash & 0xf; 3027 3028 /* Set the corresponding bit in the hash table. */ 3029 mchash[slot] |= 1 << bit; 3030 3031 ETHER_NEXT_MULTI(step, enm); 3032 } 3033 sc->sc_rfcr |= RFCR_MHEN; 3034 goto setit; 3035 3036 allmulti: 3037 ifp->if_flags |= IFF_ALLMULTI; 3038 sc->sc_rfcr |= RFCR_AAM; 3039 3040 setit: 3041 #define FILTER_EMIT(addr, data) \ 3042 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3043 delay(1); \ 3044 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3045 delay(1) 3046 3047 /* 3048 * Disable receive filter, and program the node address. 3049 */ 3050 cp = LLADDR(ifp->if_sadl); 3051 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3052 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3053 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3054 3055 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3056 /* 3057 * Program the multicast hash table. 3058 */ 3059 for (i = 0; i < MCHASH_NWORDS; i++) { 3060 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3061 mchash[i]); 3062 } 3063 } 3064 #undef FILTER_EMIT 3065 #undef MCHASH_NWORDS 3066 3067 /* 3068 * Re-enable the receiver filter. 3069 */ 3070 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3071 } 3072 3073 #if defined(DP83820) 3074 /* 3075 * sip_dp83820_mii_readreg: [mii interface function] 3076 * 3077 * Read a PHY register on the MII of the DP83820. 3078 */ 3079 static int 3080 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3081 { 3082 struct sip_softc *sc = (void *) self; 3083 3084 if (sc->sc_cfg & CFG_TBI_EN) { 3085 bus_addr_t tbireg; 3086 int rv; 3087 3088 if (phy != 0) 3089 return (0); 3090 3091 switch (reg) { 3092 case MII_BMCR: tbireg = SIP_TBICR; break; 3093 case MII_BMSR: tbireg = SIP_TBISR; break; 3094 case MII_ANAR: tbireg = SIP_TANAR; break; 3095 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3096 case MII_ANER: tbireg = SIP_TANER; break; 3097 case MII_EXTSR: 3098 /* 3099 * Don't even bother reading the TESR register. 3100 * The manual documents that the device has 3101 * 1000baseX full/half capability, but the 3102 * register itself seems read back 0 on some 3103 * boards. Just hard-code the result. 3104 */ 3105 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3106 3107 default: 3108 return (0); 3109 } 3110 3111 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3112 if (tbireg == SIP_TBISR) { 3113 /* LINK and ACOMP are switched! */ 3114 int val = rv; 3115 3116 rv = 0; 3117 if (val & TBISR_MR_LINK_STATUS) 3118 rv |= BMSR_LINK; 3119 if (val & TBISR_MR_AN_COMPLETE) 3120 rv |= BMSR_ACOMP; 3121 3122 /* 3123 * The manual claims this register reads back 0 3124 * on hard and soft reset. But we want to let 3125 * the gentbi driver know that we support auto- 3126 * negotiation, so hard-code this bit in the 3127 * result. 3128 */ 3129 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3130 } 3131 3132 return (rv); 3133 } 3134 3135 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3136 phy, reg)); 3137 } 3138 3139 /* 3140 * sip_dp83820_mii_writereg: [mii interface function] 3141 * 3142 * Write a PHY register on the MII of the DP83820. 3143 */ 3144 static void 3145 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3146 { 3147 struct sip_softc *sc = (void *) self; 3148 3149 if (sc->sc_cfg & CFG_TBI_EN) { 3150 bus_addr_t tbireg; 3151 3152 if (phy != 0) 3153 return; 3154 3155 switch (reg) { 3156 case MII_BMCR: tbireg = SIP_TBICR; break; 3157 case MII_ANAR: tbireg = SIP_TANAR; break; 3158 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3159 default: 3160 return; 3161 } 3162 3163 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3164 return; 3165 } 3166 3167 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3168 phy, reg, val); 3169 } 3170 3171 /* 3172 * sip_dp83820_mii_statchg: [mii interface function] 3173 * 3174 * Callback from MII layer when media changes. 3175 */ 3176 static void 3177 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3178 { 3179 struct sip_softc *sc = (struct sip_softc *) self; 3180 struct mii_data *mii = &sc->sc_mii; 3181 u_int32_t cfg, pcr; 3182 3183 /* 3184 * Get flow control negotiation result. 3185 */ 3186 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3187 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3188 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3189 mii->mii_media_active &= ~IFM_ETH_FMASK; 3190 } 3191 3192 /* 3193 * Update TXCFG for full-duplex operation. 3194 */ 3195 if ((mii->mii_media_active & IFM_FDX) != 0) 3196 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3197 else 3198 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3199 3200 /* 3201 * Update RXCFG for full-duplex or loopback. 3202 */ 3203 if ((mii->mii_media_active & IFM_FDX) != 0 || 3204 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3205 sc->sc_rxcfg |= RXCFG_ATX; 3206 else 3207 sc->sc_rxcfg &= ~RXCFG_ATX; 3208 3209 /* 3210 * Update CFG for MII/GMII. 3211 */ 3212 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3213 cfg = sc->sc_cfg | CFG_MODE_1000; 3214 else 3215 cfg = sc->sc_cfg; 3216 3217 /* 3218 * 802.3x flow control. 3219 */ 3220 pcr = 0; 3221 if (sc->sc_flowflags & IFM_FLOW) { 3222 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3223 pcr |= sc->sc_rx_flow_thresh; 3224 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3225 pcr |= PCR_PSEN | PCR_PS_MCAST; 3226 } 3227 3228 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3229 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3230 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3231 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3232 } 3233 #endif /* ! DP83820 */ 3234 3235 /* 3236 * sip_mii_bitbang_read: [mii bit-bang interface function] 3237 * 3238 * Read the MII serial port for the MII bit-bang module. 3239 */ 3240 static u_int32_t 3241 SIP_DECL(mii_bitbang_read)(struct device *self) 3242 { 3243 struct sip_softc *sc = (void *) self; 3244 3245 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3246 } 3247 3248 /* 3249 * sip_mii_bitbang_write: [mii big-bang interface function] 3250 * 3251 * Write the MII serial port for the MII bit-bang module. 3252 */ 3253 static void 3254 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3255 { 3256 struct sip_softc *sc = (void *) self; 3257 3258 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3259 } 3260 3261 #ifndef DP83820 3262 /* 3263 * sip_sis900_mii_readreg: [mii interface function] 3264 * 3265 * Read a PHY register on the MII. 3266 */ 3267 static int 3268 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3269 { 3270 struct sip_softc *sc = (struct sip_softc *) self; 3271 u_int32_t enphy; 3272 3273 /* 3274 * The PHY of recent SiS chipsets is accessed through bitbang 3275 * operations. 3276 */ 3277 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3278 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3279 phy, reg)); 3280 3281 #ifndef SIS900_MII_RESTRICT 3282 /* 3283 * The SiS 900 has only an internal PHY on the MII. Only allow 3284 * MII address 0. 3285 */ 3286 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3287 return (0); 3288 #endif 3289 3290 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3291 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3292 ENPHY_RWCMD | ENPHY_ACCESS); 3293 do { 3294 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3295 } while (enphy & ENPHY_ACCESS); 3296 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3297 } 3298 3299 /* 3300 * sip_sis900_mii_writereg: [mii interface function] 3301 * 3302 * Write a PHY register on the MII. 3303 */ 3304 static void 3305 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3306 { 3307 struct sip_softc *sc = (struct sip_softc *) self; 3308 u_int32_t enphy; 3309 3310 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3311 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3312 phy, reg, val); 3313 return; 3314 } 3315 3316 #ifndef SIS900_MII_RESTRICT 3317 /* 3318 * The SiS 900 has only an internal PHY on the MII. Only allow 3319 * MII address 0. 3320 */ 3321 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3322 return; 3323 #endif 3324 3325 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3326 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3327 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3328 do { 3329 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3330 } while (enphy & ENPHY_ACCESS); 3331 } 3332 3333 /* 3334 * sip_sis900_mii_statchg: [mii interface function] 3335 * 3336 * Callback from MII layer when media changes. 3337 */ 3338 static void 3339 SIP_DECL(sis900_mii_statchg)(struct device *self) 3340 { 3341 struct sip_softc *sc = (struct sip_softc *) self; 3342 struct mii_data *mii = &sc->sc_mii; 3343 u_int32_t flowctl; 3344 3345 /* 3346 * Get flow control negotiation result. 3347 */ 3348 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3349 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3350 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3351 mii->mii_media_active &= ~IFM_ETH_FMASK; 3352 } 3353 3354 /* 3355 * Update TXCFG for full-duplex operation. 3356 */ 3357 if ((mii->mii_media_active & IFM_FDX) != 0) 3358 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3359 else 3360 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3361 3362 /* 3363 * Update RXCFG for full-duplex or loopback. 3364 */ 3365 if ((mii->mii_media_active & IFM_FDX) != 0 || 3366 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3367 sc->sc_rxcfg |= RXCFG_ATX; 3368 else 3369 sc->sc_rxcfg &= ~RXCFG_ATX; 3370 3371 /* 3372 * Update IMR for use of 802.3x flow control. 3373 */ 3374 if (sc->sc_flowflags & IFM_FLOW) { 3375 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3376 flowctl = FLOWCTL_FLOWEN; 3377 } else { 3378 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3379 flowctl = 0; 3380 } 3381 3382 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3383 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3384 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3385 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3386 } 3387 3388 /* 3389 * sip_dp83815_mii_readreg: [mii interface function] 3390 * 3391 * Read a PHY register on the MII. 3392 */ 3393 static int 3394 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3395 { 3396 struct sip_softc *sc = (struct sip_softc *) self; 3397 u_int32_t val; 3398 3399 /* 3400 * The DP83815 only has an internal PHY. Only allow 3401 * MII address 0. 3402 */ 3403 if (phy != 0) 3404 return (0); 3405 3406 /* 3407 * Apparently, after a reset, the DP83815 can take a while 3408 * to respond. During this recovery period, the BMSR returns 3409 * a value of 0. Catch this -- it's not supposed to happen 3410 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3411 * PHY to come back to life. 3412 * 3413 * This works out because the BMSR is the first register 3414 * read during the PHY probe process. 3415 */ 3416 do { 3417 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3418 } while (reg == MII_BMSR && val == 0); 3419 3420 return (val & 0xffff); 3421 } 3422 3423 /* 3424 * sip_dp83815_mii_writereg: [mii interface function] 3425 * 3426 * Write a PHY register to the MII. 3427 */ 3428 static void 3429 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3430 { 3431 struct sip_softc *sc = (struct sip_softc *) self; 3432 3433 /* 3434 * The DP83815 only has an internal PHY. Only allow 3435 * MII address 0. 3436 */ 3437 if (phy != 0) 3438 return; 3439 3440 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3441 } 3442 3443 /* 3444 * sip_dp83815_mii_statchg: [mii interface function] 3445 * 3446 * Callback from MII layer when media changes. 3447 */ 3448 static void 3449 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3450 { 3451 struct sip_softc *sc = (struct sip_softc *) self; 3452 3453 /* 3454 * Update TXCFG for full-duplex operation. 3455 */ 3456 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3457 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3458 else 3459 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3460 3461 /* 3462 * Update RXCFG for full-duplex or loopback. 3463 */ 3464 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3465 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3466 sc->sc_rxcfg |= RXCFG_ATX; 3467 else 3468 sc->sc_rxcfg &= ~RXCFG_ATX; 3469 3470 /* 3471 * XXX 802.3x flow control. 3472 */ 3473 3474 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3475 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3476 3477 /* 3478 * Some DP83815s experience problems when used with short 3479 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3480 * sequence adjusts the DSP's signal attenuation to fix the 3481 * problem. 3482 */ 3483 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3484 uint32_t reg; 3485 3486 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3487 3488 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3489 reg &= 0x0fff; 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3491 delay(100); 3492 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3493 reg &= 0x00ff; 3494 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3495 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3496 0x00e8); 3497 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3498 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3499 reg | 0x20); 3500 } 3501 3502 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3503 } 3504 } 3505 #endif /* DP83820 */ 3506 3507 #if defined(DP83820) 3508 static void 3509 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3510 const struct pci_attach_args *pa, u_int8_t *enaddr) 3511 { 3512 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3513 u_int8_t cksum, *e, match; 3514 int i; 3515 3516 /* 3517 * EEPROM data format for the DP83820 can be found in 3518 * the DP83820 manual, section 4.2.4. 3519 */ 3520 3521 SIP_DECL(read_eeprom)(sc, 0, 3522 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3523 3524 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3525 match = ~(match - 1); 3526 3527 cksum = 0x55; 3528 e = (u_int8_t *) eeprom_data; 3529 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3530 cksum += *e++; 3531 3532 if (cksum != match) 3533 printf("%s: Checksum (%x) mismatch (%x)", 3534 sc->sc_dev.dv_xname, cksum, match); 3535 3536 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3537 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3538 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3539 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3540 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3541 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3542 } 3543 #else /* ! DP83820 */ 3544 static void 3545 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3546 { 3547 int i; 3548 3549 /* 3550 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3551 * a reason, but I don't know it. 3552 */ 3553 for (i = 0; i < 10; i++) 3554 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3555 } 3556 3557 static void 3558 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3559 const struct pci_attach_args *pa, u_int8_t *enaddr) 3560 { 3561 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3562 3563 switch (sc->sc_rev) { 3564 case SIS_REV_630S: 3565 case SIS_REV_630E: 3566 case SIS_REV_630EA1: 3567 case SIS_REV_630ET: 3568 case SIS_REV_635: 3569 /* 3570 * The MAC address for the on-board Ethernet of 3571 * the SiS 630 chipset is in the NVRAM. Kick 3572 * the chip into re-loading it from NVRAM, and 3573 * read the MAC address out of the filter registers. 3574 */ 3575 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3576 3577 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3578 RFCR_RFADDR_NODE0); 3579 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3580 0xffff; 3581 3582 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3583 RFCR_RFADDR_NODE2); 3584 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3585 0xffff; 3586 3587 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3588 RFCR_RFADDR_NODE4); 3589 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3590 0xffff; 3591 break; 3592 3593 case SIS_REV_960: 3594 { 3595 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3596 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3597 3598 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3599 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3600 3601 int waittime, i; 3602 3603 /* Allow to read EEPROM from LAN. It is shared 3604 * between a 1394 controller and the NIC and each 3605 * time we access it, we need to set SIS_EECMD_REQ. 3606 */ 3607 SIS_SET_EROMAR(sc, EROMAR_REQ); 3608 3609 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3610 /* Force EEPROM to idle state. */ 3611 3612 /* 3613 * XXX-cube This is ugly. I'll look for docs about it. 3614 */ 3615 SIS_SET_EROMAR(sc, EROMAR_EECS); 3616 SIP_DECL(sis900_eeprom_delay)(sc); 3617 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3618 SIS_SET_EROMAR(sc, EROMAR_EESK); 3619 SIP_DECL(sis900_eeprom_delay)(sc); 3620 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3621 SIP_DECL(sis900_eeprom_delay)(sc); 3622 } 3623 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3624 SIP_DECL(sis900_eeprom_delay)(sc); 3625 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3626 3627 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3628 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3629 sizeof(myea) / sizeof(myea[0]), myea); 3630 break; 3631 } 3632 DELAY(1); 3633 } 3634 3635 /* 3636 * Set SIS_EECTL_CLK to high, so a other master 3637 * can operate on the i2c bus. 3638 */ 3639 SIS_SET_EROMAR(sc, EROMAR_EESK); 3640 3641 /* Refuse EEPROM access by LAN */ 3642 SIS_SET_EROMAR(sc, EROMAR_DONE); 3643 } break; 3644 3645 default: 3646 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3647 sizeof(myea) / sizeof(myea[0]), myea); 3648 } 3649 3650 enaddr[0] = myea[0] & 0xff; 3651 enaddr[1] = myea[0] >> 8; 3652 enaddr[2] = myea[1] & 0xff; 3653 enaddr[3] = myea[1] >> 8; 3654 enaddr[4] = myea[2] & 0xff; 3655 enaddr[5] = myea[2] >> 8; 3656 } 3657 3658 /* Table and macro to bit-reverse an octet. */ 3659 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3660 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3661 3662 static void 3663 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3664 const struct pci_attach_args *pa, u_int8_t *enaddr) 3665 { 3666 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3667 u_int8_t cksum, *e, match; 3668 int i; 3669 3670 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3671 sizeof(eeprom_data[0]), eeprom_data); 3672 3673 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3674 match = ~(match - 1); 3675 3676 cksum = 0x55; 3677 e = (u_int8_t *) eeprom_data; 3678 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3679 cksum += *e++; 3680 } 3681 if (cksum != match) { 3682 printf("%s: Checksum (%x) mismatch (%x)", 3683 sc->sc_dev.dv_xname, cksum, match); 3684 } 3685 3686 /* 3687 * Unrolled because it makes slightly more sense this way. 3688 * The DP83815 stores the MAC address in bit 0 of word 6 3689 * through bit 15 of word 8. 3690 */ 3691 ea = &eeprom_data[6]; 3692 enaddr[0] = ((*ea & 0x1) << 7); 3693 ea++; 3694 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3695 enaddr[1] = ((*ea & 0x1FE) >> 1); 3696 enaddr[2] = ((*ea & 0x1) << 7); 3697 ea++; 3698 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3699 enaddr[3] = ((*ea & 0x1FE) >> 1); 3700 enaddr[4] = ((*ea & 0x1) << 7); 3701 ea++; 3702 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3703 enaddr[5] = ((*ea & 0x1FE) >> 1); 3704 3705 /* 3706 * In case that's not weird enough, we also need to reverse 3707 * the bits in each byte. This all actually makes more sense 3708 * if you think about the EEPROM storage as an array of bits 3709 * being shifted into bytes, but that's not how we're looking 3710 * at it here... 3711 */ 3712 for (i = 0; i < 6 ;i++) 3713 enaddr[i] = bbr(enaddr[i]); 3714 } 3715 #endif /* DP83820 */ 3716 3717 /* 3718 * sip_mediastatus: [ifmedia interface function] 3719 * 3720 * Get the current interface media status. 3721 */ 3722 static void 3723 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3724 { 3725 struct sip_softc *sc = ifp->if_softc; 3726 3727 mii_pollstat(&sc->sc_mii); 3728 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3729 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3730 sc->sc_flowflags; 3731 } 3732 3733 /* 3734 * sip_mediachange: [ifmedia interface function] 3735 * 3736 * Set hardware to newly-selected media. 3737 */ 3738 static int 3739 SIP_DECL(mediachange)(struct ifnet *ifp) 3740 { 3741 struct sip_softc *sc = ifp->if_softc; 3742 3743 if (ifp->if_flags & IFF_UP) 3744 mii_mediachg(&sc->sc_mii); 3745 return (0); 3746 } 3747
Indexes created Tue Sep 30 11:09:46 GMT 2025