if_sip.c revision 1.101.2.3
1 /* $NetBSD: if_sip.c,v 1.101.2.3 2006/04/21 12:03:38 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.101.2.3 2006/04/21 12:03:38 tron Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 /* values of interface state at last init */ 313 struct { 314 /* if_capenable */ 315 uint64_t if_capenable; 316 /* ec_capenable */ 317 int ec_capenable; 318 /* VLAN_ATTACHED */ 319 int is_vlan; 320 } sc_prev; 321 322 short sc_if_flags; 323 324 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 325 #if defined(DP83820) 326 int sc_rxdiscard; 327 int sc_rxlen; 328 struct mbuf *sc_rxhead; 329 struct mbuf *sc_rxtail; 330 struct mbuf **sc_rxtailp; 331 #endif /* DP83820 */ 332 333 #if NRND > 0 334 rndsource_element_t rnd_source; /* random source */ 335 #endif 336 }; 337 338 #ifdef DP83820 339 #define SIP_RXCHAIN_RESET(sc) \ 340 do { \ 341 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 342 *(sc)->sc_rxtailp = NULL; \ 343 (sc)->sc_rxlen = 0; \ 344 } while (/*CONSTCOND*/0) 345 346 #define SIP_RXCHAIN_LINK(sc, m) \ 347 do { \ 348 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 349 (sc)->sc_rxtailp = &(m)->m_next; \ 350 } while (/*CONSTCOND*/0) 351 #endif /* DP83820 */ 352 353 #ifdef SIP_EVENT_COUNTERS 354 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 355 #else 356 #define SIP_EVCNT_INCR(ev) /* nothing */ 357 #endif 358 359 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 360 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 361 362 #define SIP_CDTXSYNC(sc, x, n, ops) \ 363 do { \ 364 int __x, __n; \ 365 \ 366 __x = (x); \ 367 __n = (n); \ 368 \ 369 /* If it will wrap around, sync to the end of the ring. */ \ 370 if ((__x + __n) > SIP_NTXDESC) { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 373 (SIP_NTXDESC - __x), (ops)); \ 374 __n -= (SIP_NTXDESC - __x); \ 375 __x = 0; \ 376 } \ 377 \ 378 /* Now sync whatever is left. */ \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 381 } while (0) 382 383 #define SIP_CDRXSYNC(sc, x, ops) \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 386 387 #ifdef DP83820 388 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 389 #define SIP_RXBUF_LEN (MCLBYTES - 8) 390 #else 391 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 392 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 393 #endif 394 #define SIP_INIT_RXDESC(sc, x) \ 395 do { \ 396 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 397 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 398 \ 399 __sipd->sipd_link = \ 400 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 401 __sipd->sipd_bufptr = \ 402 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 403 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 404 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 405 SIP_INIT_RXDESC_EXTSTS \ 406 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 407 } while (0) 408 409 #define SIP_CHIP_VERS(sc, v, p, r) \ 410 ((sc)->sc_model->sip_vendor == (v) && \ 411 (sc)->sc_model->sip_product == (p) && \ 412 (sc)->sc_rev == (r)) 413 414 #define SIP_CHIP_MODEL(sc, v, p) \ 415 ((sc)->sc_model->sip_vendor == (v) && \ 416 (sc)->sc_model->sip_product == (p)) 417 418 #if !defined(DP83820) 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 #endif 422 423 #define SIP_TIMEOUT 1000 424 425 static void SIP_DECL(start)(struct ifnet *); 426 static void SIP_DECL(watchdog)(struct ifnet *); 427 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 428 static int SIP_DECL(init)(struct ifnet *); 429 static void SIP_DECL(stop)(struct ifnet *, int); 430 431 static void SIP_DECL(shutdown)(void *); 432 433 static void SIP_DECL(reset)(struct sip_softc *); 434 static void SIP_DECL(rxdrain)(struct sip_softc *); 435 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 436 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 437 u_int16_t *); 438 static void SIP_DECL(tick)(void *); 439 440 #if !defined(DP83820) 441 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 442 #endif /* ! DP83820 */ 443 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 444 445 #if defined(DP83820) 446 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 447 const struct pci_attach_args *, u_int8_t *); 448 #else 449 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 450 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 451 const struct pci_attach_args *, u_int8_t *); 452 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 453 const struct pci_attach_args *, u_int8_t *); 454 #endif /* DP83820 */ 455 456 static int SIP_DECL(intr)(void *); 457 static void SIP_DECL(txintr)(struct sip_softc *); 458 static void SIP_DECL(rxintr)(struct sip_softc *); 459 460 #if defined(DP83820) 461 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 462 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 463 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 464 #else 465 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 466 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 467 static void SIP_DECL(sis900_mii_statchg)(struct device *); 468 469 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 470 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 471 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 472 #endif /* DP83820 */ 473 474 static int SIP_DECL(mediachange)(struct ifnet *); 475 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 476 477 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 478 static void SIP_DECL(attach)(struct device *, struct device *, void *); 479 480 int SIP_DECL(copy_small) = 0; 481 482 #ifdef DP83820 483 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 484 gsip_match, gsip_attach, NULL, NULL); 485 #else 486 CFATTACH_DECL(sip, sizeof(struct sip_softc), 487 sip_match, sip_attach, NULL, NULL); 488 #endif 489 490 /* 491 * Descriptions of the variants of the SiS900. 492 */ 493 struct sip_variant { 494 int (*sipv_mii_readreg)(struct device *, int, int); 495 void (*sipv_mii_writereg)(struct device *, int, int, int); 496 void (*sipv_mii_statchg)(struct device *); 497 void (*sipv_set_filter)(struct sip_softc *); 498 void (*sipv_read_macaddr)(struct sip_softc *, 499 const struct pci_attach_args *, u_int8_t *); 500 }; 501 502 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 503 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 504 505 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 506 SIP_DECL(mii_bitbang_read), 507 SIP_DECL(mii_bitbang_write), 508 { 509 EROMAR_MDIO, /* MII_BIT_MDO */ 510 EROMAR_MDIO, /* MII_BIT_MDI */ 511 EROMAR_MDC, /* MII_BIT_MDC */ 512 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 513 0, /* MII_BIT_DIR_PHY_HOST */ 514 } 515 }; 516 517 #if defined(DP83820) 518 static const struct sip_variant SIP_DECL(variant_dp83820) = { 519 SIP_DECL(dp83820_mii_readreg), 520 SIP_DECL(dp83820_mii_writereg), 521 SIP_DECL(dp83820_mii_statchg), 522 SIP_DECL(dp83815_set_filter), 523 SIP_DECL(dp83820_read_macaddr), 524 }; 525 #else 526 static const struct sip_variant SIP_DECL(variant_sis900) = { 527 SIP_DECL(sis900_mii_readreg), 528 SIP_DECL(sis900_mii_writereg), 529 SIP_DECL(sis900_mii_statchg), 530 SIP_DECL(sis900_set_filter), 531 SIP_DECL(sis900_read_macaddr), 532 }; 533 534 static const struct sip_variant SIP_DECL(variant_dp83815) = { 535 SIP_DECL(dp83815_mii_readreg), 536 SIP_DECL(dp83815_mii_writereg), 537 SIP_DECL(dp83815_mii_statchg), 538 SIP_DECL(dp83815_set_filter), 539 SIP_DECL(dp83815_read_macaddr), 540 }; 541 #endif /* DP83820 */ 542 543 /* 544 * Devices supported by this driver. 545 */ 546 static const struct sip_product { 547 pci_vendor_id_t sip_vendor; 548 pci_product_id_t sip_product; 549 const char *sip_name; 550 const struct sip_variant *sip_variant; 551 } SIP_DECL(products)[] = { 552 #if defined(DP83820) 553 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 554 "NatSemi DP83820 Gigabit Ethernet", 555 &SIP_DECL(variant_dp83820) }, 556 #else 557 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 558 "SiS 900 10/100 Ethernet", 559 &SIP_DECL(variant_sis900) }, 560 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 561 "SiS 7016 10/100 Ethernet", 562 &SIP_DECL(variant_sis900) }, 563 564 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 565 "NatSemi DP83815 10/100 Ethernet", 566 &SIP_DECL(variant_dp83815) }, 567 #endif /* DP83820 */ 568 569 { 0, 0, 570 NULL, 571 NULL }, 572 }; 573 574 static const struct sip_product * 575 SIP_DECL(lookup)(const struct pci_attach_args *pa) 576 { 577 const struct sip_product *sip; 578 579 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 580 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 581 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 582 return (sip); 583 } 584 return (NULL); 585 } 586 587 #ifdef DP83820 588 /* 589 * I really hate stupid hardware vendors. There's a bit in the EEPROM 590 * which indicates if the card can do 64-bit data transfers. Unfortunately, 591 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 592 * which means we try to use 64-bit data transfers on those cards if we 593 * happen to be plugged into a 32-bit slot. 594 * 595 * What we do is use this table of cards known to be 64-bit cards. If 596 * you have a 64-bit card who's subsystem ID is not listed in this table, 597 * send the output of "pcictl dump ..." of the device to me so that your 598 * card will use the 64-bit data path when plugged into a 64-bit slot. 599 * 600 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 601 * June 30, 2002 602 */ 603 static int 604 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 605 { 606 static const struct { 607 pci_vendor_id_t c64_vendor; 608 pci_product_id_t c64_product; 609 } card64[] = { 610 /* Asante GigaNIX */ 611 { 0x128a, 0x0002 }, 612 613 /* Accton EN1407-T, Planex GN-1000TE */ 614 { 0x1113, 0x1407 }, 615 616 /* Netgear GA-621 */ 617 { 0x1385, 0x621a }, 618 619 /* SMC EZ Card */ 620 { 0x10b8, 0x9462 }, 621 622 { 0, 0} 623 }; 624 pcireg_t subsys; 625 int i; 626 627 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 628 629 for (i = 0; card64[i].c64_vendor != 0; i++) { 630 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 631 PCI_PRODUCT(subsys) == card64[i].c64_product) 632 return (1); 633 } 634 635 return (0); 636 } 637 #endif /* DP83820 */ 638 639 static int 640 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 641 { 642 struct pci_attach_args *pa = aux; 643 644 if (SIP_DECL(lookup)(pa) != NULL) 645 return (1); 646 647 return (0); 648 } 649 650 static void 651 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 652 { 653 struct sip_softc *sc = (struct sip_softc *) self; 654 struct pci_attach_args *pa = aux; 655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 656 pci_chipset_tag_t pc = pa->pa_pc; 657 pci_intr_handle_t ih; 658 const char *intrstr = NULL; 659 bus_space_tag_t iot, memt; 660 bus_space_handle_t ioh, memh; 661 bus_dma_segment_t seg; 662 int ioh_valid, memh_valid; 663 int i, rseg, error; 664 const struct sip_product *sip; 665 pcireg_t pmode; 666 u_int8_t enaddr[ETHER_ADDR_LEN]; 667 int pmreg; 668 #ifdef DP83820 669 pcireg_t memtype; 670 u_int32_t reg; 671 #endif /* DP83820 */ 672 673 callout_init(&sc->sc_tick_ch); 674 675 sip = SIP_DECL(lookup)(pa); 676 if (sip == NULL) { 677 printf("\n"); 678 panic(SIP_STR(attach) ": impossible"); 679 } 680 sc->sc_rev = PCI_REVISION(pa->pa_class); 681 682 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 683 684 sc->sc_model = sip; 685 686 /* 687 * XXX Work-around broken PXE firmware on some boards. 688 * 689 * The DP83815 shares an address decoder with the MEM BAR 690 * and the ROM BAR. Make sure the ROM BAR is disabled, 691 * so that memory mapped access works. 692 */ 693 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 694 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 695 ~PCI_MAPREG_ROM_ENABLE); 696 697 /* 698 * Map the device. 699 */ 700 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 701 PCI_MAPREG_TYPE_IO, 0, 702 &iot, &ioh, NULL, NULL) == 0); 703 #ifdef DP83820 704 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 705 switch (memtype) { 706 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 707 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 708 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 709 memtype, 0, &memt, &memh, NULL, NULL) == 0); 710 break; 711 default: 712 memh_valid = 0; 713 } 714 #else 715 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 716 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 717 &memt, &memh, NULL, NULL) == 0); 718 #endif /* DP83820 */ 719 720 if (memh_valid) { 721 sc->sc_st = memt; 722 sc->sc_sh = memh; 723 } else if (ioh_valid) { 724 sc->sc_st = iot; 725 sc->sc_sh = ioh; 726 } else { 727 printf("%s: unable to map device registers\n", 728 sc->sc_dev.dv_xname); 729 return; 730 } 731 732 sc->sc_dmat = pa->pa_dmat; 733 734 /* 735 * Make sure bus mastering is enabled. Also make sure 736 * Write/Invalidate is enabled if we're allowed to use it. 737 */ 738 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 739 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 740 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 741 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 742 pmreg | PCI_COMMAND_MASTER_ENABLE); 743 744 /* Get it out of power save mode if needed. */ 745 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 746 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 747 PCI_PMCSR_STATE_MASK; 748 if (pmode == PCI_PMCSR_STATE_D3) { 749 /* 750 * The card has lost all configuration data in 751 * this state, so punt. 752 */ 753 printf("%s: unable to wake up from power state D3\n", 754 sc->sc_dev.dv_xname); 755 return; 756 } 757 if (pmode != PCI_PMCSR_STATE_D0) { 758 printf("%s: waking up from power state D%d\n", 759 sc->sc_dev.dv_xname, pmode); 760 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 761 PCI_PMCSR_STATE_D0); 762 } 763 } 764 765 /* 766 * Map and establish our interrupt. 767 */ 768 if (pci_intr_map(pa, &ih)) { 769 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 770 return; 771 } 772 intrstr = pci_intr_string(pc, ih); 773 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 774 if (sc->sc_ih == NULL) { 775 printf("%s: unable to establish interrupt", 776 sc->sc_dev.dv_xname); 777 if (intrstr != NULL) 778 printf(" at %s", intrstr); 779 printf("\n"); 780 return; 781 } 782 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 783 784 SIMPLEQ_INIT(&sc->sc_txfreeq); 785 SIMPLEQ_INIT(&sc->sc_txdirtyq); 786 787 /* 788 * Allocate the control data structures, and create and load the 789 * DMA map for it. 790 */ 791 if ((error = bus_dmamem_alloc(sc->sc_dmat, 792 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 793 0)) != 0) { 794 printf("%s: unable to allocate control data, error = %d\n", 795 sc->sc_dev.dv_xname, error); 796 goto fail_0; 797 } 798 799 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 800 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 801 BUS_DMA_COHERENT)) != 0) { 802 printf("%s: unable to map control data, error = %d\n", 803 sc->sc_dev.dv_xname, error); 804 goto fail_1; 805 } 806 807 if ((error = bus_dmamap_create(sc->sc_dmat, 808 sizeof(struct sip_control_data), 1, 809 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 810 printf("%s: unable to create control data DMA map, " 811 "error = %d\n", sc->sc_dev.dv_xname, error); 812 goto fail_2; 813 } 814 815 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 816 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 817 0)) != 0) { 818 printf("%s: unable to load control data DMA map, error = %d\n", 819 sc->sc_dev.dv_xname, error); 820 goto fail_3; 821 } 822 823 /* 824 * Create the transmit buffer DMA maps. 825 */ 826 for (i = 0; i < SIP_TXQUEUELEN; i++) { 827 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 828 SIP_NTXSEGS, MCLBYTES, 0, 0, 829 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 830 printf("%s: unable to create tx DMA map %d, " 831 "error = %d\n", sc->sc_dev.dv_xname, i, error); 832 goto fail_4; 833 } 834 } 835 836 /* 837 * Create the receive buffer DMA maps. 838 */ 839 for (i = 0; i < SIP_NRXDESC; i++) { 840 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 841 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 842 printf("%s: unable to create rx DMA map %d, " 843 "error = %d\n", sc->sc_dev.dv_xname, i, error); 844 goto fail_5; 845 } 846 sc->sc_rxsoft[i].rxs_mbuf = NULL; 847 } 848 849 /* 850 * Reset the chip to a known state. 851 */ 852 SIP_DECL(reset)(sc); 853 854 /* 855 * Read the Ethernet address from the EEPROM. This might 856 * also fetch other stuff from the EEPROM and stash it 857 * in the softc. 858 */ 859 sc->sc_cfg = 0; 860 #if !defined(DP83820) 861 if (SIP_SIS900_REV(sc,SIS_REV_635) || 862 SIP_SIS900_REV(sc,SIS_REV_900B)) 863 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 864 865 if (SIP_SIS900_REV(sc,SIS_REV_635) || 866 SIP_SIS900_REV(sc,SIS_REV_960) || 867 SIP_SIS900_REV(sc,SIS_REV_900B)) 868 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 869 SIP_CFG) & CFG_EDBMASTEN); 870 #endif 871 872 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 873 874 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 875 ether_sprintf(enaddr)); 876 877 /* 878 * Initialize the configuration register: aggressive PCI 879 * bus request algorithm, default backoff, default OW timer, 880 * default parity error detection. 881 * 882 * NOTE: "Big endian mode" is useless on the SiS900 and 883 * friends -- it affects packet data, not descriptors. 884 */ 885 #ifdef DP83820 886 /* 887 * Cause the chip to load configuration data from the EEPROM. 888 */ 889 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 890 for (i = 0; i < 10000; i++) { 891 delay(10); 892 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 893 PTSCR_EELOAD_EN) == 0) 894 break; 895 } 896 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 897 PTSCR_EELOAD_EN) { 898 printf("%s: timeout loading configuration from EEPROM\n", 899 sc->sc_dev.dv_xname); 900 return; 901 } 902 903 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 904 905 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 906 if (reg & CFG_PCI64_DET) { 907 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 908 /* 909 * Check to see if this card is 64-bit. If so, enable 64-bit 910 * data transfers. 911 * 912 * We can't use the DATA64_EN bit in the EEPROM, because 913 * vendors of 32-bit cards fail to clear that bit in many 914 * cases (yet the card still detects that it's in a 64-bit 915 * slot; go figure). 916 */ 917 if (SIP_DECL(check_64bit)(pa)) { 918 sc->sc_cfg |= CFG_DATA64_EN; 919 printf(", using 64-bit data transfers"); 920 } 921 printf("\n"); 922 } 923 924 /* 925 * XXX Need some PCI flags indicating support for 926 * XXX 64-bit addressing. 927 */ 928 #if 0 929 if (reg & CFG_M64ADDR) 930 sc->sc_cfg |= CFG_M64ADDR; 931 if (reg & CFG_T64ADDR) 932 sc->sc_cfg |= CFG_T64ADDR; 933 #endif 934 935 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 936 const char *sep = ""; 937 printf("%s: using ", sc->sc_dev.dv_xname); 938 if (reg & CFG_EXT_125) { 939 sc->sc_cfg |= CFG_EXT_125; 940 printf("%s125MHz clock", sep); 941 sep = ", "; 942 } 943 if (reg & CFG_TBI_EN) { 944 sc->sc_cfg |= CFG_TBI_EN; 945 printf("%sten-bit interface", sep); 946 sep = ", "; 947 } 948 printf("\n"); 949 } 950 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 951 (reg & CFG_MRM_DIS) != 0) 952 sc->sc_cfg |= CFG_MRM_DIS; 953 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 954 (reg & CFG_MWI_DIS) != 0) 955 sc->sc_cfg |= CFG_MWI_DIS; 956 957 /* 958 * Use the extended descriptor format on the DP83820. This 959 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 960 * checksumming. 961 */ 962 sc->sc_cfg |= CFG_EXTSTS_EN; 963 #endif /* DP83820 */ 964 965 /* 966 * Initialize our media structures and probe the MII. 967 */ 968 sc->sc_mii.mii_ifp = ifp; 969 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 970 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 971 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 972 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 973 SIP_DECL(mediastatus)); 974 975 /* 976 * XXX We cannot handle flow control on the DP83815. 977 */ 978 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 979 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 980 MII_OFFSET_ANY, 0); 981 else 982 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 983 MII_OFFSET_ANY, MIIF_DOPAUSE); 984 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 985 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 986 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 987 } else 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 989 990 ifp = &sc->sc_ethercom.ec_if; 991 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 992 ifp->if_softc = sc; 993 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 994 sc->sc_if_flags = ifp->if_flags; 995 ifp->if_ioctl = SIP_DECL(ioctl); 996 ifp->if_start = SIP_DECL(start); 997 ifp->if_watchdog = SIP_DECL(watchdog); 998 ifp->if_init = SIP_DECL(init); 999 ifp->if_stop = SIP_DECL(stop); 1000 IFQ_SET_READY(&ifp->if_snd); 1001 1002 /* 1003 * We can support 802.1Q VLAN-sized frames. 1004 */ 1005 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1006 1007 #ifdef DP83820 1008 /* 1009 * And the DP83820 can do VLAN tagging in hardware, and 1010 * support the jumbo Ethernet MTU. 1011 */ 1012 sc->sc_ethercom.ec_capabilities |= 1013 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1014 1015 /* 1016 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1017 * in hardware. 1018 */ 1019 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1020 IFCAP_CSUM_UDPv4; 1021 #endif /* DP83820 */ 1022 1023 /* 1024 * Attach the interface. 1025 */ 1026 if_attach(ifp); 1027 ether_ifattach(ifp, enaddr); 1028 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1029 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1030 sc->sc_prev.if_capenable = ifp->if_capenable; 1031 #if NRND > 0 1032 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1033 RND_TYPE_NET, 0); 1034 #endif 1035 1036 /* 1037 * The number of bytes that must be available in 1038 * the Tx FIFO before the bus master can DMA more 1039 * data into the FIFO. 1040 */ 1041 sc->sc_tx_fill_thresh = 64 / 32; 1042 1043 /* 1044 * Start at a drain threshold of 512 bytes. We will 1045 * increase it if a DMA underrun occurs. 1046 * 1047 * XXX The minimum value of this variable should be 1048 * tuned. We may be able to improve performance 1049 * by starting with a lower value. That, however, 1050 * may trash the first few outgoing packets if the 1051 * PCI bus is saturated. 1052 */ 1053 #ifdef DP83820 1054 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1055 #else 1056 sc->sc_tx_drain_thresh = 1504 / 32; 1057 #endif 1058 1059 /* 1060 * Initialize the Rx FIFO drain threshold. 1061 * 1062 * This is in units of 8 bytes. 1063 * 1064 * We should never set this value lower than 2; 14 bytes are 1065 * required to filter the packet. 1066 */ 1067 sc->sc_rx_drain_thresh = 128 / 8; 1068 1069 #ifdef SIP_EVENT_COUNTERS 1070 /* 1071 * Attach event counters. 1072 */ 1073 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1074 NULL, sc->sc_dev.dv_xname, "txsstall"); 1075 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1076 NULL, sc->sc_dev.dv_xname, "txdstall"); 1077 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1078 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1079 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1080 NULL, sc->sc_dev.dv_xname, "txdintr"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1082 NULL, sc->sc_dev.dv_xname, "txiintr"); 1083 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1084 NULL, sc->sc_dev.dv_xname, "rxintr"); 1085 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1086 NULL, sc->sc_dev.dv_xname, "hiberr"); 1087 #ifndef DP83820 1088 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1089 NULL, sc->sc_dev.dv_xname, "rxpause"); 1090 #endif /* !DP83820 */ 1091 #ifdef DP83820 1092 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1093 NULL, sc->sc_dev.dv_xname, "rxpause"); 1094 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1095 NULL, sc->sc_dev.dv_xname, "txpause"); 1096 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1097 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1098 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1099 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1100 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1101 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1102 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1103 NULL, sc->sc_dev.dv_xname, "txipsum"); 1104 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1105 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1106 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1107 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1108 #endif /* DP83820 */ 1109 #endif /* SIP_EVENT_COUNTERS */ 1110 1111 /* 1112 * Make sure the interface is shutdown during reboot. 1113 */ 1114 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1115 if (sc->sc_sdhook == NULL) 1116 printf("%s: WARNING: unable to establish shutdown hook\n", 1117 sc->sc_dev.dv_xname); 1118 return; 1119 1120 /* 1121 * Free any resources we've allocated during the failed attach 1122 * attempt. Do this in reverse order and fall through. 1123 */ 1124 fail_5: 1125 for (i = 0; i < SIP_NRXDESC; i++) { 1126 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1127 bus_dmamap_destroy(sc->sc_dmat, 1128 sc->sc_rxsoft[i].rxs_dmamap); 1129 } 1130 fail_4: 1131 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1132 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1133 bus_dmamap_destroy(sc->sc_dmat, 1134 sc->sc_txsoft[i].txs_dmamap); 1135 } 1136 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1137 fail_3: 1138 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1139 fail_2: 1140 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1141 sizeof(struct sip_control_data)); 1142 fail_1: 1143 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1144 fail_0: 1145 return; 1146 } 1147 1148 /* 1149 * sip_shutdown: 1150 * 1151 * Make sure the interface is stopped at reboot time. 1152 */ 1153 static void 1154 SIP_DECL(shutdown)(void *arg) 1155 { 1156 struct sip_softc *sc = arg; 1157 1158 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1159 } 1160 1161 /* 1162 * sip_start: [ifnet interface function] 1163 * 1164 * Start packet transmission on the interface. 1165 */ 1166 static void 1167 SIP_DECL(start)(struct ifnet *ifp) 1168 { 1169 struct sip_softc *sc = ifp->if_softc; 1170 struct mbuf *m0; 1171 #ifndef DP83820 1172 struct mbuf *m; 1173 #endif 1174 struct sip_txsoft *txs; 1175 bus_dmamap_t dmamap; 1176 int error, nexttx, lasttx, seg; 1177 int ofree = sc->sc_txfree; 1178 #if 0 1179 int firsttx = sc->sc_txnext; 1180 #endif 1181 #ifdef DP83820 1182 struct m_tag *mtag; 1183 u_int32_t extsts; 1184 #endif 1185 1186 #ifndef DP83820 1187 /* 1188 * If we've been told to pause, don't transmit any more packets. 1189 */ 1190 if (sc->sc_paused) 1191 ifp->if_flags |= IFF_OACTIVE; 1192 #endif 1193 1194 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1195 return; 1196 1197 /* 1198 * Loop through the send queue, setting up transmit descriptors 1199 * until we drain the queue, or use up all available transmit 1200 * descriptors. 1201 */ 1202 for (;;) { 1203 /* Get a work queue entry. */ 1204 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1205 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1206 break; 1207 } 1208 1209 /* 1210 * Grab a packet off the queue. 1211 */ 1212 IFQ_POLL(&ifp->if_snd, m0); 1213 if (m0 == NULL) 1214 break; 1215 #ifndef DP83820 1216 m = NULL; 1217 #endif 1218 1219 dmamap = txs->txs_dmamap; 1220 1221 #ifdef DP83820 1222 /* 1223 * Load the DMA map. If this fails, the packet either 1224 * didn't fit in the allotted number of segments, or we 1225 * were short on resources. For the too-many-segments 1226 * case, we simply report an error and drop the packet, 1227 * since we can't sanely copy a jumbo packet to a single 1228 * buffer. 1229 */ 1230 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1231 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1232 if (error) { 1233 if (error == EFBIG) { 1234 printf("%s: Tx packet consumes too many " 1235 "DMA segments, dropping...\n", 1236 sc->sc_dev.dv_xname); 1237 IFQ_DEQUEUE(&ifp->if_snd, m0); 1238 m_freem(m0); 1239 continue; 1240 } 1241 /* 1242 * Short on resources, just stop for now. 1243 */ 1244 break; 1245 } 1246 #else /* DP83820 */ 1247 /* 1248 * Load the DMA map. If this fails, the packet either 1249 * didn't fit in the alloted number of segments, or we 1250 * were short on resources. In this case, we'll copy 1251 * and try again. 1252 */ 1253 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1254 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1255 MGETHDR(m, M_DONTWAIT, MT_DATA); 1256 if (m == NULL) { 1257 printf("%s: unable to allocate Tx mbuf\n", 1258 sc->sc_dev.dv_xname); 1259 break; 1260 } 1261 if (m0->m_pkthdr.len > MHLEN) { 1262 MCLGET(m, M_DONTWAIT); 1263 if ((m->m_flags & M_EXT) == 0) { 1264 printf("%s: unable to allocate Tx " 1265 "cluster\n", sc->sc_dev.dv_xname); 1266 m_freem(m); 1267 break; 1268 } 1269 } 1270 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1271 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1272 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1273 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1274 if (error) { 1275 printf("%s: unable to load Tx buffer, " 1276 "error = %d\n", sc->sc_dev.dv_xname, error); 1277 break; 1278 } 1279 } 1280 #endif /* DP83820 */ 1281 1282 /* 1283 * Ensure we have enough descriptors free to describe 1284 * the packet. Note, we always reserve one descriptor 1285 * at the end of the ring as a termination point, to 1286 * prevent wrap-around. 1287 */ 1288 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1289 /* 1290 * Not enough free descriptors to transmit this 1291 * packet. We haven't committed anything yet, 1292 * so just unload the DMA map, put the packet 1293 * back on the queue, and punt. Notify the upper 1294 * layer that there are not more slots left. 1295 * 1296 * XXX We could allocate an mbuf and copy, but 1297 * XXX is it worth it? 1298 */ 1299 ifp->if_flags |= IFF_OACTIVE; 1300 bus_dmamap_unload(sc->sc_dmat, dmamap); 1301 #ifndef DP83820 1302 if (m != NULL) 1303 m_freem(m); 1304 #endif 1305 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1306 break; 1307 } 1308 1309 IFQ_DEQUEUE(&ifp->if_snd, m0); 1310 #ifndef DP83820 1311 if (m != NULL) { 1312 m_freem(m0); 1313 m0 = m; 1314 } 1315 #endif 1316 1317 /* 1318 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1319 */ 1320 1321 /* Sync the DMA map. */ 1322 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1323 BUS_DMASYNC_PREWRITE); 1324 1325 /* 1326 * Initialize the transmit descriptors. 1327 */ 1328 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1329 seg < dmamap->dm_nsegs; 1330 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1331 /* 1332 * If this is the first descriptor we're 1333 * enqueueing, don't set the OWN bit just 1334 * yet. That could cause a race condition. 1335 * We'll do it below. 1336 */ 1337 sc->sc_txdescs[nexttx].sipd_bufptr = 1338 htole32(dmamap->dm_segs[seg].ds_addr); 1339 sc->sc_txdescs[nexttx].sipd_cmdsts = 1340 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1341 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1342 #ifdef DP83820 1343 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1344 #endif /* DP83820 */ 1345 lasttx = nexttx; 1346 } 1347 1348 /* Clear the MORE bit on the last segment. */ 1349 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1350 1351 /* 1352 * If we're in the interrupt delay window, delay the 1353 * interrupt. 1354 */ 1355 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1356 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1357 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1358 htole32(CMDSTS_INTR); 1359 sc->sc_txwin = 0; 1360 } 1361 1362 #ifdef DP83820 1363 /* 1364 * If VLANs are enabled and the packet has a VLAN tag, set 1365 * up the descriptor to encapsulate the packet for us. 1366 * 1367 * This apparently has to be on the last descriptor of 1368 * the packet. 1369 */ 1370 1371 /* 1372 * Byte swapping is tricky. We need to provide the tag 1373 * in a network byte order. On a big-endian machine, 1374 * the byteorder is correct, but we need to swap it 1375 * anyway, because this will be undone by the outside 1376 * htole32(). That's why there must be an 1377 * unconditional swap instead of htons() inside. 1378 */ 1379 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1380 sc->sc_txdescs[lasttx].sipd_extsts |= 1381 htole32(EXTSTS_VPKT | 1382 (bswap16(VLAN_TAG_VALUE(mtag)) & 1383 EXTSTS_VTCI)); 1384 } 1385 1386 /* 1387 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1388 * checksumming, set up the descriptor to do this work 1389 * for us. 1390 * 1391 * This apparently has to be on the first descriptor of 1392 * the packet. 1393 * 1394 * Byte-swap constants so the compiler can optimize. 1395 */ 1396 extsts = 0; 1397 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1398 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4); 1399 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1400 extsts |= htole32(EXTSTS_IPPKT); 1401 } 1402 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1403 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4); 1404 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1405 extsts |= htole32(EXTSTS_TCPPKT); 1406 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1407 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4); 1408 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1409 extsts |= htole32(EXTSTS_UDPPKT); 1410 } 1411 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1412 #endif /* DP83820 */ 1413 1414 /* Sync the descriptors we're using. */ 1415 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1416 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1417 1418 /* 1419 * The entire packet is set up. Give the first descrptor 1420 * to the chip now. 1421 */ 1422 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1423 htole32(CMDSTS_OWN); 1424 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1425 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1426 1427 /* 1428 * Store a pointer to the packet so we can free it later, 1429 * and remember what txdirty will be once the packet is 1430 * done. 1431 */ 1432 txs->txs_mbuf = m0; 1433 txs->txs_firstdesc = sc->sc_txnext; 1434 txs->txs_lastdesc = lasttx; 1435 1436 /* Advance the tx pointer. */ 1437 sc->sc_txfree -= dmamap->dm_nsegs; 1438 sc->sc_txnext = nexttx; 1439 1440 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1441 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1442 1443 #if NBPFILTER > 0 1444 /* 1445 * Pass the packet to any BPF listeners. 1446 */ 1447 if (ifp->if_bpf) 1448 bpf_mtap(ifp->if_bpf, m0); 1449 #endif /* NBPFILTER > 0 */ 1450 } 1451 1452 if (txs == NULL || sc->sc_txfree == 0) { 1453 /* No more slots left; notify upper layer. */ 1454 ifp->if_flags |= IFF_OACTIVE; 1455 } 1456 1457 if (sc->sc_txfree != ofree) { 1458 /* 1459 * Start the transmit process. Note, the manual says 1460 * that if there are no pending transmissions in the 1461 * chip's internal queue (indicated by TXE being clear), 1462 * then the driver software must set the TXDP to the 1463 * first descriptor to be transmitted. However, if we 1464 * do this, it causes serious performance degredation on 1465 * the DP83820 under load, not setting TXDP doesn't seem 1466 * to adversely affect the SiS 900 or DP83815. 1467 * 1468 * Well, I guess it wouldn't be the first time a manual 1469 * has lied -- and they could be speaking of the NULL- 1470 * terminated descriptor list case, rather than OWN- 1471 * terminated rings. 1472 */ 1473 #if 0 1474 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1475 CR_TXE) == 0) { 1476 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1477 SIP_CDTXADDR(sc, firsttx)); 1478 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1479 } 1480 #else 1481 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1482 #endif 1483 1484 /* Set a watchdog timer in case the chip flakes out. */ 1485 #ifdef DP83820 1486 /* Gigabit autonegotiation takes 5 seconds. */ 1487 ifp->if_timer = 10; 1488 #else 1489 ifp->if_timer = 5; 1490 #endif 1491 } 1492 } 1493 1494 /* 1495 * sip_watchdog: [ifnet interface function] 1496 * 1497 * Watchdog timer handler. 1498 */ 1499 static void 1500 SIP_DECL(watchdog)(struct ifnet *ifp) 1501 { 1502 struct sip_softc *sc = ifp->if_softc; 1503 1504 /* 1505 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1506 * If we get a timeout, try and sweep up transmit descriptors. 1507 * If we manage to sweep them all up, ignore the lack of 1508 * interrupt. 1509 */ 1510 SIP_DECL(txintr)(sc); 1511 1512 if (sc->sc_txfree != SIP_NTXDESC) { 1513 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1514 ifp->if_oerrors++; 1515 1516 /* Reset the interface. */ 1517 (void) SIP_DECL(init)(ifp); 1518 } else if (ifp->if_flags & IFF_DEBUG) 1519 printf("%s: recovered from device timeout\n", 1520 sc->sc_dev.dv_xname); 1521 1522 /* Try to get more packets going. */ 1523 SIP_DECL(start)(ifp); 1524 } 1525 1526 /* 1527 * sip_ioctl: [ifnet interface function] 1528 * 1529 * Handle control requests from the operator. 1530 */ 1531 static int 1532 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1533 { 1534 struct sip_softc *sc = ifp->if_softc; 1535 struct ifreq *ifr = (struct ifreq *)data; 1536 int s, error; 1537 1538 s = splnet(); 1539 1540 switch (cmd) { 1541 case SIOCSIFMEDIA: 1542 /* Flow control requires full-duplex mode. */ 1543 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1544 (ifr->ifr_media & IFM_FDX) == 0) 1545 ifr->ifr_media &= ~IFM_ETH_FMASK; 1546 #ifdef DP83820 1547 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1548 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1549 /* We can do both TXPAUSE and RXPAUSE. */ 1550 ifr->ifr_media |= 1551 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1552 } 1553 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1554 } 1555 #else 1556 /* XXX */ 1557 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1558 ifr->ifr_media &= ~IFM_ETH_FMASK; 1559 1560 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1561 if (ifr->ifr_media & IFM_FLOW) { 1562 /* 1563 * Both TXPAUSE and RXPAUSE must be set. 1564 * (SiS900 and DP83815 don't have PAUSE_ASYM 1565 * feature.) 1566 * 1567 * XXX Can SiS900 and DP83815 send PAUSE? 1568 */ 1569 ifr->ifr_media |= 1570 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1571 } 1572 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1573 } 1574 #endif 1575 /* FALLTHROUGH */ 1576 case SIOCGIFMEDIA: 1577 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1578 break; 1579 case SIOCSIFFLAGS: 1580 /* If the interface is up and running, only modify the receive 1581 * filter when setting promiscuous or debug mode. Otherwise 1582 * fall through to ether_ioctl, which will reset the chip. 1583 */ 1584 1585 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1586 == (sc)->sc_ethercom.ec_capenable) \ 1587 && ((sc)->sc_prev.is_vlan == \ 1588 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1589 1590 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1591 1592 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1593 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1594 == (IFF_UP|IFF_RUNNING)) 1595 && ((ifp->if_flags & (~RESETIGN)) 1596 == (sc->sc_if_flags & (~RESETIGN))) 1597 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1598 /* Set up the receive filter. */ 1599 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1600 error = 0; 1601 break; 1602 #undef RESETIGN 1603 } 1604 /* FALLTHROUGH */ 1605 default: 1606 error = ether_ioctl(ifp, cmd, data); 1607 if (error == ENETRESET) { 1608 /* 1609 * Multicast list has changed; set the hardware filter 1610 * accordingly. 1611 */ 1612 if (ifp->if_flags & IFF_RUNNING) 1613 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1614 error = 0; 1615 } 1616 break; 1617 } 1618 1619 /* Try to get more packets going. */ 1620 SIP_DECL(start)(ifp); 1621 1622 sc->sc_if_flags = ifp->if_flags; 1623 splx(s); 1624 return (error); 1625 } 1626 1627 /* 1628 * sip_intr: 1629 * 1630 * Interrupt service routine. 1631 */ 1632 static int 1633 SIP_DECL(intr)(void *arg) 1634 { 1635 struct sip_softc *sc = arg; 1636 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1637 u_int32_t isr; 1638 int handled = 0; 1639 1640 /* Disable interrupts. */ 1641 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1642 1643 for (;;) { 1644 /* Reading clears interrupt. */ 1645 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1646 if ((isr & sc->sc_imr) == 0) 1647 break; 1648 1649 #if NRND > 0 1650 if (RND_ENABLED(&sc->rnd_source)) 1651 rnd_add_uint32(&sc->rnd_source, isr); 1652 #endif 1653 1654 handled = 1; 1655 1656 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1657 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1658 1659 /* Grab any new packets. */ 1660 SIP_DECL(rxintr)(sc); 1661 1662 if (isr & ISR_RXORN) { 1663 printf("%s: receive FIFO overrun\n", 1664 sc->sc_dev.dv_xname); 1665 1666 /* XXX adjust rx_drain_thresh? */ 1667 } 1668 1669 if (isr & ISR_RXIDLE) { 1670 printf("%s: receive ring overrun\n", 1671 sc->sc_dev.dv_xname); 1672 1673 /* Get the receive process going again. */ 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, 1675 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, 1677 SIP_CR, CR_RXE); 1678 } 1679 } 1680 1681 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1682 #ifdef SIP_EVENT_COUNTERS 1683 if (isr & ISR_TXDESC) 1684 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1685 else if (isr & ISR_TXIDLE) 1686 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1687 #endif 1688 1689 /* Sweep up transmit descriptors. */ 1690 SIP_DECL(txintr)(sc); 1691 1692 if (isr & ISR_TXURN) { 1693 u_int32_t thresh; 1694 1695 printf("%s: transmit FIFO underrun", 1696 sc->sc_dev.dv_xname); 1697 1698 thresh = sc->sc_tx_drain_thresh + 1; 1699 if (thresh <= TXCFG_DRTH && 1700 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1701 (sc->sc_tx_fill_thresh * 32))) { 1702 printf("; increasing Tx drain " 1703 "threshold to %u bytes\n", 1704 thresh * 32); 1705 sc->sc_tx_drain_thresh = thresh; 1706 (void) SIP_DECL(init)(ifp); 1707 } else { 1708 (void) SIP_DECL(init)(ifp); 1709 printf("\n"); 1710 } 1711 } 1712 } 1713 1714 #if !defined(DP83820) 1715 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1716 if (isr & ISR_PAUSE_ST) { 1717 sc->sc_paused = 1; 1718 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1719 ifp->if_flags |= IFF_OACTIVE; 1720 } 1721 if (isr & ISR_PAUSE_END) { 1722 sc->sc_paused = 0; 1723 ifp->if_flags &= ~IFF_OACTIVE; 1724 } 1725 } 1726 #endif /* ! DP83820 */ 1727 1728 if (isr & ISR_HIBERR) { 1729 int want_init = 0; 1730 1731 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1732 1733 #define PRINTERR(bit, str) \ 1734 do { \ 1735 if ((isr & (bit)) != 0) { \ 1736 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1737 printf("%s: %s\n", \ 1738 sc->sc_dev.dv_xname, str); \ 1739 want_init = 1; \ 1740 } \ 1741 } while (/*CONSTCOND*/0) 1742 1743 PRINTERR(ISR_DPERR, "parity error"); 1744 PRINTERR(ISR_SSERR, "system error"); 1745 PRINTERR(ISR_RMABT, "master abort"); 1746 PRINTERR(ISR_RTABT, "target abort"); 1747 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1748 /* 1749 * Ignore: 1750 * Tx reset complete 1751 * Rx reset complete 1752 */ 1753 if (want_init) 1754 (void) SIP_DECL(init)(ifp); 1755 #undef PRINTERR 1756 } 1757 } 1758 1759 /* Re-enable interrupts. */ 1760 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1761 1762 /* Try to get more packets going. */ 1763 SIP_DECL(start)(ifp); 1764 1765 return (handled); 1766 } 1767 1768 /* 1769 * sip_txintr: 1770 * 1771 * Helper; handle transmit interrupts. 1772 */ 1773 static void 1774 SIP_DECL(txintr)(struct sip_softc *sc) 1775 { 1776 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1777 struct sip_txsoft *txs; 1778 u_int32_t cmdsts; 1779 1780 #ifndef DP83820 1781 if (sc->sc_paused == 0) 1782 #endif 1783 ifp->if_flags &= ~IFF_OACTIVE; 1784 1785 /* 1786 * Go through our Tx list and free mbufs for those 1787 * frames which have been transmitted. 1788 */ 1789 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1790 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1791 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1792 1793 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1794 if (cmdsts & CMDSTS_OWN) 1795 break; 1796 1797 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1798 1799 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1800 1801 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1802 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1803 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1804 m_freem(txs->txs_mbuf); 1805 txs->txs_mbuf = NULL; 1806 1807 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1808 1809 /* 1810 * Check for errors and collisions. 1811 */ 1812 if (cmdsts & 1813 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1814 ifp->if_oerrors++; 1815 if (cmdsts & CMDSTS_Tx_EC) 1816 ifp->if_collisions += 16; 1817 if (ifp->if_flags & IFF_DEBUG) { 1818 if (cmdsts & CMDSTS_Tx_ED) 1819 printf("%s: excessive deferral\n", 1820 sc->sc_dev.dv_xname); 1821 if (cmdsts & CMDSTS_Tx_EC) 1822 printf("%s: excessive collisions\n", 1823 sc->sc_dev.dv_xname); 1824 } 1825 } else { 1826 /* Packet was transmitted successfully. */ 1827 ifp->if_opackets++; 1828 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1829 } 1830 } 1831 1832 /* 1833 * If there are no more pending transmissions, cancel the watchdog 1834 * timer. 1835 */ 1836 if (txs == NULL) { 1837 ifp->if_timer = 0; 1838 sc->sc_txwin = 0; 1839 } 1840 } 1841 1842 #if defined(DP83820) 1843 /* 1844 * sip_rxintr: 1845 * 1846 * Helper; handle receive interrupts. 1847 */ 1848 static void 1849 SIP_DECL(rxintr)(struct sip_softc *sc) 1850 { 1851 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1852 struct sip_rxsoft *rxs; 1853 struct mbuf *m; 1854 u_int32_t cmdsts, extsts; 1855 int i, len; 1856 1857 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1858 rxs = &sc->sc_rxsoft[i]; 1859 1860 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1861 1862 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1863 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1864 len = CMDSTS_SIZE(cmdsts); 1865 1866 /* 1867 * NOTE: OWN is set if owned by _consumer_. We're the 1868 * consumer of the receive ring, so if the bit is clear, 1869 * we have processed all of the packets. 1870 */ 1871 if ((cmdsts & CMDSTS_OWN) == 0) { 1872 /* 1873 * We have processed all of the receive buffers. 1874 */ 1875 break; 1876 } 1877 1878 if (__predict_false(sc->sc_rxdiscard)) { 1879 SIP_INIT_RXDESC(sc, i); 1880 if ((cmdsts & CMDSTS_MORE) == 0) { 1881 /* Reset our state. */ 1882 sc->sc_rxdiscard = 0; 1883 } 1884 continue; 1885 } 1886 1887 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1888 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1889 1890 m = rxs->rxs_mbuf; 1891 1892 /* 1893 * Add a new receive buffer to the ring. 1894 */ 1895 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1896 /* 1897 * Failed, throw away what we've done so 1898 * far, and discard the rest of the packet. 1899 */ 1900 ifp->if_ierrors++; 1901 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1902 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1903 SIP_INIT_RXDESC(sc, i); 1904 if (cmdsts & CMDSTS_MORE) 1905 sc->sc_rxdiscard = 1; 1906 if (sc->sc_rxhead != NULL) 1907 m_freem(sc->sc_rxhead); 1908 SIP_RXCHAIN_RESET(sc); 1909 continue; 1910 } 1911 1912 SIP_RXCHAIN_LINK(sc, m); 1913 1914 m->m_len = len; 1915 1916 /* 1917 * If this is not the end of the packet, keep 1918 * looking. 1919 */ 1920 if (cmdsts & CMDSTS_MORE) { 1921 sc->sc_rxlen += len; 1922 continue; 1923 } 1924 1925 /* 1926 * Okay, we have the entire packet now. The chip includes 1927 * the FCS, so we need to trim it. 1928 */ 1929 m->m_len -= ETHER_CRC_LEN; 1930 1931 *sc->sc_rxtailp = NULL; 1932 len = m->m_len + sc->sc_rxlen; 1933 m = sc->sc_rxhead; 1934 1935 SIP_RXCHAIN_RESET(sc); 1936 1937 /* 1938 * If an error occurred, update stats and drop the packet. 1939 */ 1940 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1941 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1942 ifp->if_ierrors++; 1943 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1944 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1945 /* Receive overrun handled elsewhere. */ 1946 printf("%s: receive descriptor error\n", 1947 sc->sc_dev.dv_xname); 1948 } 1949 #define PRINTERR(bit, str) \ 1950 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1951 (cmdsts & (bit)) != 0) \ 1952 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1953 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1954 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1955 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1956 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1957 #undef PRINTERR 1958 m_freem(m); 1959 continue; 1960 } 1961 1962 /* 1963 * If the packet is small enough to fit in a 1964 * single header mbuf, allocate one and copy 1965 * the data into it. This greatly reduces 1966 * memory consumption when we receive lots 1967 * of small packets. 1968 */ 1969 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1970 struct mbuf *nm; 1971 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1972 if (nm == NULL) { 1973 ifp->if_ierrors++; 1974 m_freem(m); 1975 continue; 1976 } 1977 nm->m_data += 2; 1978 nm->m_pkthdr.len = nm->m_len = len; 1979 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1980 m_freem(m); 1981 m = nm; 1982 } 1983 #ifndef __NO_STRICT_ALIGNMENT 1984 else { 1985 /* 1986 * The DP83820's receive buffers must be 4-byte 1987 * aligned. But this means that the data after 1988 * the Ethernet header is misaligned. To compensate, 1989 * we have artificially shortened the buffer size 1990 * in the descriptor, and we do an overlapping copy 1991 * of the data two bytes further in (in the first 1992 * buffer of the chain only). 1993 */ 1994 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1995 m->m_len); 1996 m->m_data += 2; 1997 } 1998 #endif /* ! __NO_STRICT_ALIGNMENT */ 1999 2000 /* 2001 * If VLANs are enabled, VLAN packets have been unwrapped 2002 * for us. Associate the tag with the packet. 2003 */ 2004 2005 /* 2006 * Again, byte swapping is tricky. Hardware provided 2007 * the tag in the network byte order, but extsts was 2008 * passed through le32toh() in the meantime. On a 2009 * big-endian machine, we need to swap it again. On a 2010 * little-endian machine, we need to convert from the 2011 * network to host byte order. This means that we must 2012 * swap it in any case, so unconditional swap instead 2013 * of htons() is used. 2014 */ 2015 if ((extsts & EXTSTS_VPKT) != 0) { 2016 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2017 continue); 2018 } 2019 2020 /* 2021 * Set the incoming checksum information for the 2022 * packet. 2023 */ 2024 if ((extsts & EXTSTS_IPPKT) != 0) { 2025 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2026 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2027 if (extsts & EXTSTS_Rx_IPERR) 2028 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2029 if (extsts & EXTSTS_TCPPKT) { 2030 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2031 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2032 if (extsts & EXTSTS_Rx_TCPERR) 2033 m->m_pkthdr.csum_flags |= 2034 M_CSUM_TCP_UDP_BAD; 2035 } else if (extsts & EXTSTS_UDPPKT) { 2036 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2037 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2038 if (extsts & EXTSTS_Rx_UDPERR) 2039 m->m_pkthdr.csum_flags |= 2040 M_CSUM_TCP_UDP_BAD; 2041 } 2042 } 2043 2044 ifp->if_ipackets++; 2045 m->m_pkthdr.rcvif = ifp; 2046 m->m_pkthdr.len = len; 2047 2048 #if NBPFILTER > 0 2049 /* 2050 * Pass this up to any BPF listeners, but only 2051 * pass if up the stack if it's for us. 2052 */ 2053 if (ifp->if_bpf) 2054 bpf_mtap(ifp->if_bpf, m); 2055 #endif /* NBPFILTER > 0 */ 2056 2057 /* Pass it on. */ 2058 (*ifp->if_input)(ifp, m); 2059 } 2060 2061 /* Update the receive pointer. */ 2062 sc->sc_rxptr = i; 2063 } 2064 #else /* ! DP83820 */ 2065 /* 2066 * sip_rxintr: 2067 * 2068 * Helper; handle receive interrupts. 2069 */ 2070 static void 2071 SIP_DECL(rxintr)(struct sip_softc *sc) 2072 { 2073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2074 struct sip_rxsoft *rxs; 2075 struct mbuf *m; 2076 u_int32_t cmdsts; 2077 int i, len; 2078 2079 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2080 rxs = &sc->sc_rxsoft[i]; 2081 2082 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2083 2084 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2085 2086 /* 2087 * NOTE: OWN is set if owned by _consumer_. We're the 2088 * consumer of the receive ring, so if the bit is clear, 2089 * we have processed all of the packets. 2090 */ 2091 if ((cmdsts & CMDSTS_OWN) == 0) { 2092 /* 2093 * We have processed all of the receive buffers. 2094 */ 2095 break; 2096 } 2097 2098 /* 2099 * If any collisions were seen on the wire, count one. 2100 */ 2101 if (cmdsts & CMDSTS_Rx_COL) 2102 ifp->if_collisions++; 2103 2104 /* 2105 * If an error occurred, update stats, clear the status 2106 * word, and leave the packet buffer in place. It will 2107 * simply be reused the next time the ring comes around. 2108 */ 2109 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2110 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2111 ifp->if_ierrors++; 2112 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2113 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2114 /* Receive overrun handled elsewhere. */ 2115 printf("%s: receive descriptor error\n", 2116 sc->sc_dev.dv_xname); 2117 } 2118 #define PRINTERR(bit, str) \ 2119 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2120 (cmdsts & (bit)) != 0) \ 2121 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2122 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2123 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2124 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2125 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2126 #undef PRINTERR 2127 SIP_INIT_RXDESC(sc, i); 2128 continue; 2129 } 2130 2131 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2132 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2133 2134 /* 2135 * No errors; receive the packet. Note, the SiS 900 2136 * includes the CRC with every packet. 2137 */ 2138 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2139 2140 #ifdef __NO_STRICT_ALIGNMENT 2141 /* 2142 * If the packet is small enough to fit in a 2143 * single header mbuf, allocate one and copy 2144 * the data into it. This greatly reduces 2145 * memory consumption when we receive lots 2146 * of small packets. 2147 * 2148 * Otherwise, we add a new buffer to the receive 2149 * chain. If this fails, we drop the packet and 2150 * recycle the old buffer. 2151 */ 2152 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2153 MGETHDR(m, M_DONTWAIT, MT_DATA); 2154 if (m == NULL) 2155 goto dropit; 2156 memcpy(mtod(m, caddr_t), 2157 mtod(rxs->rxs_mbuf, caddr_t), len); 2158 SIP_INIT_RXDESC(sc, i); 2159 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2160 rxs->rxs_dmamap->dm_mapsize, 2161 BUS_DMASYNC_PREREAD); 2162 } else { 2163 m = rxs->rxs_mbuf; 2164 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2165 dropit: 2166 ifp->if_ierrors++; 2167 SIP_INIT_RXDESC(sc, i); 2168 bus_dmamap_sync(sc->sc_dmat, 2169 rxs->rxs_dmamap, 0, 2170 rxs->rxs_dmamap->dm_mapsize, 2171 BUS_DMASYNC_PREREAD); 2172 continue; 2173 } 2174 } 2175 #else 2176 /* 2177 * The SiS 900's receive buffers must be 4-byte aligned. 2178 * But this means that the data after the Ethernet header 2179 * is misaligned. We must allocate a new buffer and 2180 * copy the data, shifted forward 2 bytes. 2181 */ 2182 MGETHDR(m, M_DONTWAIT, MT_DATA); 2183 if (m == NULL) { 2184 dropit: 2185 ifp->if_ierrors++; 2186 SIP_INIT_RXDESC(sc, i); 2187 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2188 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2189 continue; 2190 } 2191 if (len > (MHLEN - 2)) { 2192 MCLGET(m, M_DONTWAIT); 2193 if ((m->m_flags & M_EXT) == 0) { 2194 m_freem(m); 2195 goto dropit; 2196 } 2197 } 2198 m->m_data += 2; 2199 2200 /* 2201 * Note that we use clusters for incoming frames, so the 2202 * buffer is virtually contiguous. 2203 */ 2204 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2205 2206 /* Allow the receive descriptor to continue using its mbuf. */ 2207 SIP_INIT_RXDESC(sc, i); 2208 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2209 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2210 #endif /* __NO_STRICT_ALIGNMENT */ 2211 2212 ifp->if_ipackets++; 2213 m->m_pkthdr.rcvif = ifp; 2214 m->m_pkthdr.len = m->m_len = len; 2215 2216 #if NBPFILTER > 0 2217 /* 2218 * Pass this up to any BPF listeners, but only 2219 * pass if up the stack if it's for us. 2220 */ 2221 if (ifp->if_bpf) 2222 bpf_mtap(ifp->if_bpf, m); 2223 #endif /* NBPFILTER > 0 */ 2224 2225 /* Pass it on. */ 2226 (*ifp->if_input)(ifp, m); 2227 } 2228 2229 /* Update the receive pointer. */ 2230 sc->sc_rxptr = i; 2231 } 2232 #endif /* DP83820 */ 2233 2234 /* 2235 * sip_tick: 2236 * 2237 * One second timer, used to tick the MII. 2238 */ 2239 static void 2240 SIP_DECL(tick)(void *arg) 2241 { 2242 struct sip_softc *sc = arg; 2243 int s; 2244 2245 s = splnet(); 2246 #ifdef DP83820 2247 #ifdef SIP_EVENT_COUNTERS 2248 /* Read PAUSE related counts from MIB registers. */ 2249 sc->sc_ev_rxpause.ev_count += 2250 bus_space_read_4(sc->sc_st, sc->sc_sh, 2251 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2252 sc->sc_ev_txpause.ev_count += 2253 bus_space_read_4(sc->sc_st, sc->sc_sh, 2254 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2255 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2256 #endif /* SIP_EVENT_COUNTERS */ 2257 #endif /* DP83820 */ 2258 mii_tick(&sc->sc_mii); 2259 splx(s); 2260 2261 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2262 } 2263 2264 /* 2265 * sip_reset: 2266 * 2267 * Perform a soft reset on the SiS 900. 2268 */ 2269 static void 2270 SIP_DECL(reset)(struct sip_softc *sc) 2271 { 2272 bus_space_tag_t st = sc->sc_st; 2273 bus_space_handle_t sh = sc->sc_sh; 2274 int i; 2275 2276 bus_space_write_4(st, sh, SIP_IER, 0); 2277 bus_space_write_4(st, sh, SIP_IMR, 0); 2278 bus_space_write_4(st, sh, SIP_RFCR, 0); 2279 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2280 2281 for (i = 0; i < SIP_TIMEOUT; i++) { 2282 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2283 break; 2284 delay(2); 2285 } 2286 2287 if (i == SIP_TIMEOUT) 2288 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2289 2290 delay(1000); 2291 2292 #ifdef DP83820 2293 /* 2294 * Set the general purpose I/O bits. Do it here in case we 2295 * need to have GPIO set up to talk to the media interface. 2296 */ 2297 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2298 delay(1000); 2299 #endif /* DP83820 */ 2300 } 2301 2302 /* 2303 * sip_init: [ ifnet interface function ] 2304 * 2305 * Initialize the interface. Must be called at splnet(). 2306 */ 2307 static int 2308 SIP_DECL(init)(struct ifnet *ifp) 2309 { 2310 struct sip_softc *sc = ifp->if_softc; 2311 bus_space_tag_t st = sc->sc_st; 2312 bus_space_handle_t sh = sc->sc_sh; 2313 struct sip_txsoft *txs; 2314 struct sip_rxsoft *rxs; 2315 struct sip_desc *sipd; 2316 #if defined(DP83820) 2317 u_int32_t reg; 2318 #endif 2319 int i, error = 0; 2320 2321 /* 2322 * Cancel any pending I/O. 2323 */ 2324 SIP_DECL(stop)(ifp, 0); 2325 2326 /* 2327 * Reset the chip to a known state. 2328 */ 2329 SIP_DECL(reset)(sc); 2330 2331 #if !defined(DP83820) 2332 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2333 /* 2334 * DP83815 manual, page 78: 2335 * 4.4 Recommended Registers Configuration 2336 * For optimum performance of the DP83815, version noted 2337 * as DP83815CVNG (SRR = 203h), the listed register 2338 * modifications must be followed in sequence... 2339 * 2340 * It's not clear if this should be 302h or 203h because that 2341 * chip name is listed as SRR 302h in the description of the 2342 * SRR register. However, my revision 302h DP83815 on the 2343 * Netgear FA311 purchased in 02/2001 needs these settings 2344 * to avoid tons of errors in AcceptPerfectMatch (non- 2345 * IFF_PROMISC) mode. I do not know if other revisions need 2346 * this set or not. [briggs -- 09 March 2001] 2347 * 2348 * Note that only the low-order 12 bits of 0xe4 are documented 2349 * and that this sets reserved bits in that register. 2350 */ 2351 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2352 2353 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2354 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2355 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2356 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2357 2358 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2359 } 2360 #endif /* ! DP83820 */ 2361 2362 /* 2363 * Initialize the transmit descriptor ring. 2364 */ 2365 for (i = 0; i < SIP_NTXDESC; i++) { 2366 sipd = &sc->sc_txdescs[i]; 2367 memset(sipd, 0, sizeof(struct sip_desc)); 2368 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2369 } 2370 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2371 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2372 sc->sc_txfree = SIP_NTXDESC; 2373 sc->sc_txnext = 0; 2374 sc->sc_txwin = 0; 2375 2376 /* 2377 * Initialize the transmit job descriptors. 2378 */ 2379 SIMPLEQ_INIT(&sc->sc_txfreeq); 2380 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2381 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2382 txs = &sc->sc_txsoft[i]; 2383 txs->txs_mbuf = NULL; 2384 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2385 } 2386 2387 /* 2388 * Initialize the receive descriptor and receive job 2389 * descriptor rings. 2390 */ 2391 for (i = 0; i < SIP_NRXDESC; i++) { 2392 rxs = &sc->sc_rxsoft[i]; 2393 if (rxs->rxs_mbuf == NULL) { 2394 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2395 printf("%s: unable to allocate or map rx " 2396 "buffer %d, error = %d\n", 2397 sc->sc_dev.dv_xname, i, error); 2398 /* 2399 * XXX Should attempt to run with fewer receive 2400 * XXX buffers instead of just failing. 2401 */ 2402 SIP_DECL(rxdrain)(sc); 2403 goto out; 2404 } 2405 } else 2406 SIP_INIT_RXDESC(sc, i); 2407 } 2408 sc->sc_rxptr = 0; 2409 #ifdef DP83820 2410 sc->sc_rxdiscard = 0; 2411 SIP_RXCHAIN_RESET(sc); 2412 #endif /* DP83820 */ 2413 2414 /* 2415 * Set the configuration register; it's already initialized 2416 * in sip_attach(). 2417 */ 2418 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2419 2420 /* 2421 * Initialize the prototype TXCFG register. 2422 */ 2423 #if defined(DP83820) 2424 sc->sc_txcfg = TXCFG_MXDMA_512; 2425 sc->sc_rxcfg = RXCFG_MXDMA_512; 2426 #else 2427 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2428 SIP_SIS900_REV(sc, SIS_REV_960) || 2429 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2430 (sc->sc_cfg & CFG_EDBMASTEN)) { 2431 sc->sc_txcfg = TXCFG_MXDMA_64; 2432 sc->sc_rxcfg = RXCFG_MXDMA_64; 2433 } else { 2434 sc->sc_txcfg = TXCFG_MXDMA_512; 2435 sc->sc_rxcfg = RXCFG_MXDMA_512; 2436 } 2437 #endif /* DP83820 */ 2438 2439 sc->sc_txcfg |= TXCFG_ATP | 2440 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2441 sc->sc_tx_drain_thresh; 2442 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2443 2444 /* 2445 * Initialize the receive drain threshold if we have never 2446 * done so. 2447 */ 2448 if (sc->sc_rx_drain_thresh == 0) { 2449 /* 2450 * XXX This value should be tuned. This is set to the 2451 * maximum of 248 bytes, and we may be able to improve 2452 * performance by decreasing it (although we should never 2453 * set this value lower than 2; 14 bytes are required to 2454 * filter the packet). 2455 */ 2456 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2457 } 2458 2459 /* 2460 * Initialize the prototype RXCFG register. 2461 */ 2462 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2463 #ifdef DP83820 2464 /* 2465 * Accept long packets (including FCS) so we can handle 2466 * 802.1q-tagged frames and jumbo frames properly. 2467 */ 2468 if (ifp->if_mtu > ETHERMTU || 2469 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2470 sc->sc_rxcfg |= RXCFG_ALP; 2471 2472 /* 2473 * Checksum offloading is disabled if the user selects an MTU 2474 * larger than 8109. (FreeBSD says 8152, but there is emperical 2475 * evidence that >8109 does not work on some boards, such as the 2476 * Planex GN-1000TE). 2477 */ 2478 if (ifp->if_mtu > 8109 && 2479 (ifp->if_capenable & 2480 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4))) { 2481 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2482 "disabled.\n", sc->sc_dev.dv_xname); 2483 ifp->if_capenable &= ~(IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 2484 IFCAP_CSUM_UDPv4); 2485 ifp->if_csum_flags_tx = 0; 2486 ifp->if_csum_flags_rx = 0; 2487 } 2488 #else 2489 /* 2490 * Accept packets >1518 bytes (including FCS) so we can handle 2491 * 802.1q-tagged frames properly. 2492 */ 2493 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2494 sc->sc_rxcfg |= RXCFG_ALP; 2495 #endif 2496 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2497 2498 #ifdef DP83820 2499 /* 2500 * Initialize the VLAN/IP receive control register. 2501 * We enable checksum computation on all incoming 2502 * packets, and do not reject packets w/ bad checksums. 2503 */ 2504 reg = 0; 2505 if (ifp->if_capenable & 2506 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2507 reg |= VRCR_IPEN; 2508 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2509 reg |= VRCR_VTDEN|VRCR_VTREN; 2510 bus_space_write_4(st, sh, SIP_VRCR, reg); 2511 2512 /* 2513 * Initialize the VLAN/IP transmit control register. 2514 * We enable outgoing checksum computation on a 2515 * per-packet basis. 2516 */ 2517 reg = 0; 2518 if (ifp->if_capenable & 2519 (IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 2520 reg |= VTCR_PPCHK; 2521 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2522 reg |= VTCR_VPPTI; 2523 bus_space_write_4(st, sh, SIP_VTCR, reg); 2524 2525 /* 2526 * If we're using VLANs, initialize the VLAN data register. 2527 * To understand why we bswap the VLAN Ethertype, see section 2528 * 4.2.36 of the DP83820 manual. 2529 */ 2530 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2531 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2532 #endif /* DP83820 */ 2533 2534 /* 2535 * Give the transmit and receive rings to the chip. 2536 */ 2537 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2538 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2539 2540 /* 2541 * Initialize the interrupt mask. 2542 */ 2543 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2544 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2545 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2546 2547 /* Set up the receive filter. */ 2548 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2549 2550 #ifdef DP83820 2551 /* 2552 * Tune sc_rx_flow_thresh. 2553 * XXX "More than 8KB" is too short for jumbo frames. 2554 * XXX TODO: Threshold value should be user-settable. 2555 */ 2556 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2557 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2558 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2559 #endif 2560 2561 /* 2562 * Set the current media. Do this after initializing the prototype 2563 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2564 * control. 2565 */ 2566 mii_mediachg(&sc->sc_mii); 2567 2568 #ifdef DP83820 2569 /* 2570 * Set the interrupt hold-off timer to 100us. 2571 */ 2572 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2573 #endif 2574 2575 /* 2576 * Enable interrupts. 2577 */ 2578 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2579 2580 /* 2581 * Start the transmit and receive processes. 2582 */ 2583 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2584 2585 /* 2586 * Start the one second MII clock. 2587 */ 2588 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2589 2590 /* 2591 * ...all done! 2592 */ 2593 ifp->if_flags |= IFF_RUNNING; 2594 ifp->if_flags &= ~IFF_OACTIVE; 2595 sc->sc_if_flags = ifp->if_flags; 2596 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2597 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2598 sc->sc_prev.if_capenable = ifp->if_capenable; 2599 2600 out: 2601 if (error) 2602 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2603 return (error); 2604 } 2605 2606 /* 2607 * sip_drain: 2608 * 2609 * Drain the receive queue. 2610 */ 2611 static void 2612 SIP_DECL(rxdrain)(struct sip_softc *sc) 2613 { 2614 struct sip_rxsoft *rxs; 2615 int i; 2616 2617 for (i = 0; i < SIP_NRXDESC; i++) { 2618 rxs = &sc->sc_rxsoft[i]; 2619 if (rxs->rxs_mbuf != NULL) { 2620 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2621 m_freem(rxs->rxs_mbuf); 2622 rxs->rxs_mbuf = NULL; 2623 } 2624 } 2625 } 2626 2627 /* 2628 * sip_stop: [ ifnet interface function ] 2629 * 2630 * Stop transmission on the interface. 2631 */ 2632 static void 2633 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2634 { 2635 struct sip_softc *sc = ifp->if_softc; 2636 bus_space_tag_t st = sc->sc_st; 2637 bus_space_handle_t sh = sc->sc_sh; 2638 struct sip_txsoft *txs; 2639 u_int32_t cmdsts = 0; /* DEBUG */ 2640 2641 /* 2642 * Stop the one second clock. 2643 */ 2644 callout_stop(&sc->sc_tick_ch); 2645 2646 /* Down the MII. */ 2647 mii_down(&sc->sc_mii); 2648 2649 /* 2650 * Disable interrupts. 2651 */ 2652 bus_space_write_4(st, sh, SIP_IER, 0); 2653 2654 /* 2655 * Stop receiver and transmitter. 2656 */ 2657 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2658 2659 /* 2660 * Release any queued transmit buffers. 2661 */ 2662 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2663 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2664 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2665 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2666 CMDSTS_INTR) == 0) 2667 printf("%s: sip_stop: last descriptor does not " 2668 "have INTR bit set\n", sc->sc_dev.dv_xname); 2669 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2670 #ifdef DIAGNOSTIC 2671 if (txs->txs_mbuf == NULL) { 2672 printf("%s: dirty txsoft with no mbuf chain\n", 2673 sc->sc_dev.dv_xname); 2674 panic("sip_stop"); 2675 } 2676 #endif 2677 cmdsts |= /* DEBUG */ 2678 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2679 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2680 m_freem(txs->txs_mbuf); 2681 txs->txs_mbuf = NULL; 2682 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2683 } 2684 2685 if (disable) 2686 SIP_DECL(rxdrain)(sc); 2687 2688 /* 2689 * Mark the interface down and cancel the watchdog timer. 2690 */ 2691 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2692 ifp->if_timer = 0; 2693 2694 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2695 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2696 printf("%s: sip_stop: no INTR bits set in dirty tx " 2697 "descriptors\n", sc->sc_dev.dv_xname); 2698 } 2699 2700 /* 2701 * sip_read_eeprom: 2702 * 2703 * Read data from the serial EEPROM. 2704 */ 2705 static void 2706 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2707 u_int16_t *data) 2708 { 2709 bus_space_tag_t st = sc->sc_st; 2710 bus_space_handle_t sh = sc->sc_sh; 2711 u_int16_t reg; 2712 int i, x; 2713 2714 for (i = 0; i < wordcnt; i++) { 2715 /* Send CHIP SELECT. */ 2716 reg = EROMAR_EECS; 2717 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2718 2719 /* Shift in the READ opcode. */ 2720 for (x = 3; x > 0; x--) { 2721 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2722 reg |= EROMAR_EEDI; 2723 else 2724 reg &= ~EROMAR_EEDI; 2725 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2726 bus_space_write_4(st, sh, SIP_EROMAR, 2727 reg | EROMAR_EESK); 2728 delay(4); 2729 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2730 delay(4); 2731 } 2732 2733 /* Shift in address. */ 2734 for (x = 6; x > 0; x--) { 2735 if ((word + i) & (1 << (x - 1))) 2736 reg |= EROMAR_EEDI; 2737 else 2738 reg &= ~EROMAR_EEDI; 2739 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2740 bus_space_write_4(st, sh, SIP_EROMAR, 2741 reg | EROMAR_EESK); 2742 delay(4); 2743 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2744 delay(4); 2745 } 2746 2747 /* Shift out data. */ 2748 reg = EROMAR_EECS; 2749 data[i] = 0; 2750 for (x = 16; x > 0; x--) { 2751 bus_space_write_4(st, sh, SIP_EROMAR, 2752 reg | EROMAR_EESK); 2753 delay(4); 2754 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2755 data[i] |= (1 << (x - 1)); 2756 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2757 delay(4); 2758 } 2759 2760 /* Clear CHIP SELECT. */ 2761 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2762 delay(4); 2763 } 2764 } 2765 2766 /* 2767 * sip_add_rxbuf: 2768 * 2769 * Add a receive buffer to the indicated descriptor. 2770 */ 2771 static int 2772 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2773 { 2774 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2775 struct mbuf *m; 2776 int error; 2777 2778 MGETHDR(m, M_DONTWAIT, MT_DATA); 2779 if (m == NULL) 2780 return (ENOBUFS); 2781 2782 MCLGET(m, M_DONTWAIT); 2783 if ((m->m_flags & M_EXT) == 0) { 2784 m_freem(m); 2785 return (ENOBUFS); 2786 } 2787 2788 #if defined(DP83820) 2789 m->m_len = SIP_RXBUF_LEN; 2790 #endif /* DP83820 */ 2791 2792 if (rxs->rxs_mbuf != NULL) 2793 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2794 2795 rxs->rxs_mbuf = m; 2796 2797 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2798 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2799 BUS_DMA_READ|BUS_DMA_NOWAIT); 2800 if (error) { 2801 printf("%s: can't load rx DMA map %d, error = %d\n", 2802 sc->sc_dev.dv_xname, idx, error); 2803 panic("sip_add_rxbuf"); /* XXX */ 2804 } 2805 2806 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2807 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2808 2809 SIP_INIT_RXDESC(sc, idx); 2810 2811 return (0); 2812 } 2813 2814 #if !defined(DP83820) 2815 /* 2816 * sip_sis900_set_filter: 2817 * 2818 * Set up the receive filter. 2819 */ 2820 static void 2821 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2822 { 2823 bus_space_tag_t st = sc->sc_st; 2824 bus_space_handle_t sh = sc->sc_sh; 2825 struct ethercom *ec = &sc->sc_ethercom; 2826 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2827 struct ether_multi *enm; 2828 u_int8_t *cp; 2829 struct ether_multistep step; 2830 u_int32_t crc, mchash[16]; 2831 2832 /* 2833 * Initialize the prototype RFCR. 2834 */ 2835 sc->sc_rfcr = RFCR_RFEN; 2836 if (ifp->if_flags & IFF_BROADCAST) 2837 sc->sc_rfcr |= RFCR_AAB; 2838 if (ifp->if_flags & IFF_PROMISC) { 2839 sc->sc_rfcr |= RFCR_AAP; 2840 goto allmulti; 2841 } 2842 2843 /* 2844 * Set up the multicast address filter by passing all multicast 2845 * addresses through a CRC generator, and then using the high-order 2846 * 6 bits as an index into the 128 bit multicast hash table (only 2847 * the lower 16 bits of each 32 bit multicast hash register are 2848 * valid). The high order bits select the register, while the 2849 * rest of the bits select the bit within the register. 2850 */ 2851 2852 memset(mchash, 0, sizeof(mchash)); 2853 2854 /* 2855 * SiS900 (at least SiS963) requires us to register the address of 2856 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2857 */ 2858 crc = 0x0ed423f9; 2859 2860 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2861 SIP_SIS900_REV(sc, SIS_REV_960) || 2862 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2863 /* Just want the 8 most significant bits. */ 2864 crc >>= 24; 2865 } else { 2866 /* Just want the 7 most significant bits. */ 2867 crc >>= 25; 2868 } 2869 2870 /* Set the corresponding bit in the hash table. */ 2871 mchash[crc >> 4] |= 1 << (crc & 0xf); 2872 2873 ETHER_FIRST_MULTI(step, ec, enm); 2874 while (enm != NULL) { 2875 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2876 /* 2877 * We must listen to a range of multicast addresses. 2878 * For now, just accept all multicasts, rather than 2879 * trying to set only those filter bits needed to match 2880 * the range. (At this time, the only use of address 2881 * ranges is for IP multicast routing, for which the 2882 * range is big enough to require all bits set.) 2883 */ 2884 goto allmulti; 2885 } 2886 2887 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2888 2889 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2890 SIP_SIS900_REV(sc, SIS_REV_960) || 2891 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2892 /* Just want the 8 most significant bits. */ 2893 crc >>= 24; 2894 } else { 2895 /* Just want the 7 most significant bits. */ 2896 crc >>= 25; 2897 } 2898 2899 /* Set the corresponding bit in the hash table. */ 2900 mchash[crc >> 4] |= 1 << (crc & 0xf); 2901 2902 ETHER_NEXT_MULTI(step, enm); 2903 } 2904 2905 ifp->if_flags &= ~IFF_ALLMULTI; 2906 goto setit; 2907 2908 allmulti: 2909 ifp->if_flags |= IFF_ALLMULTI; 2910 sc->sc_rfcr |= RFCR_AAM; 2911 2912 setit: 2913 #define FILTER_EMIT(addr, data) \ 2914 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2915 delay(1); \ 2916 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2917 delay(1) 2918 2919 /* 2920 * Disable receive filter, and program the node address. 2921 */ 2922 cp = LLADDR(ifp->if_sadl); 2923 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2924 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2925 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2926 2927 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2928 /* 2929 * Program the multicast hash table. 2930 */ 2931 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2932 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2933 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2934 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2935 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2936 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2937 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2938 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2939 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2940 SIP_SIS900_REV(sc, SIS_REV_960) || 2941 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2942 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2943 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2944 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2945 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2946 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2947 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2948 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2949 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2950 } 2951 } 2952 #undef FILTER_EMIT 2953 2954 /* 2955 * Re-enable the receiver filter. 2956 */ 2957 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2958 } 2959 #endif /* ! DP83820 */ 2960 2961 /* 2962 * sip_dp83815_set_filter: 2963 * 2964 * Set up the receive filter. 2965 */ 2966 static void 2967 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2968 { 2969 bus_space_tag_t st = sc->sc_st; 2970 bus_space_handle_t sh = sc->sc_sh; 2971 struct ethercom *ec = &sc->sc_ethercom; 2972 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2973 struct ether_multi *enm; 2974 u_int8_t *cp; 2975 struct ether_multistep step; 2976 u_int32_t crc, hash, slot, bit; 2977 #ifdef DP83820 2978 #define MCHASH_NWORDS 128 2979 #else 2980 #define MCHASH_NWORDS 32 2981 #endif /* DP83820 */ 2982 u_int16_t mchash[MCHASH_NWORDS]; 2983 int i; 2984 2985 /* 2986 * Initialize the prototype RFCR. 2987 * Enable the receive filter, and accept on 2988 * Perfect (destination address) Match 2989 * If IFF_BROADCAST, also accept all broadcast packets. 2990 * If IFF_PROMISC, accept all unicast packets (and later, set 2991 * IFF_ALLMULTI and accept all multicast, too). 2992 */ 2993 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2994 if (ifp->if_flags & IFF_BROADCAST) 2995 sc->sc_rfcr |= RFCR_AAB; 2996 if (ifp->if_flags & IFF_PROMISC) { 2997 sc->sc_rfcr |= RFCR_AAP; 2998 goto allmulti; 2999 } 3000 3001 #ifdef DP83820 3002 /* 3003 * Set up the DP83820 multicast address filter by passing all multicast 3004 * addresses through a CRC generator, and then using the high-order 3005 * 11 bits as an index into the 2048 bit multicast hash table. The 3006 * high-order 7 bits select the slot, while the low-order 4 bits 3007 * select the bit within the slot. Note that only the low 16-bits 3008 * of each filter word are used, and there are 128 filter words. 3009 */ 3010 #else 3011 /* 3012 * Set up the DP83815 multicast address filter by passing all multicast 3013 * addresses through a CRC generator, and then using the high-order 3014 * 9 bits as an index into the 512 bit multicast hash table. The 3015 * high-order 5 bits select the slot, while the low-order 4 bits 3016 * select the bit within the slot. Note that only the low 16-bits 3017 * of each filter word are used, and there are 32 filter words. 3018 */ 3019 #endif /* DP83820 */ 3020 3021 memset(mchash, 0, sizeof(mchash)); 3022 3023 ifp->if_flags &= ~IFF_ALLMULTI; 3024 ETHER_FIRST_MULTI(step, ec, enm); 3025 if (enm == NULL) 3026 goto setit; 3027 while (enm != NULL) { 3028 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3029 /* 3030 * We must listen to a range of multicast addresses. 3031 * For now, just accept all multicasts, rather than 3032 * trying to set only those filter bits needed to match 3033 * the range. (At this time, the only use of address 3034 * ranges is for IP multicast routing, for which the 3035 * range is big enough to require all bits set.) 3036 */ 3037 goto allmulti; 3038 } 3039 3040 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3041 3042 #ifdef DP83820 3043 /* Just want the 11 most significant bits. */ 3044 hash = crc >> 21; 3045 #else 3046 /* Just want the 9 most significant bits. */ 3047 hash = crc >> 23; 3048 #endif /* DP83820 */ 3049 3050 slot = hash >> 4; 3051 bit = hash & 0xf; 3052 3053 /* Set the corresponding bit in the hash table. */ 3054 mchash[slot] |= 1 << bit; 3055 3056 ETHER_NEXT_MULTI(step, enm); 3057 } 3058 sc->sc_rfcr |= RFCR_MHEN; 3059 goto setit; 3060 3061 allmulti: 3062 ifp->if_flags |= IFF_ALLMULTI; 3063 sc->sc_rfcr |= RFCR_AAM; 3064 3065 setit: 3066 #define FILTER_EMIT(addr, data) \ 3067 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3068 delay(1); \ 3069 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3070 delay(1) 3071 3072 /* 3073 * Disable receive filter, and program the node address. 3074 */ 3075 cp = LLADDR(ifp->if_sadl); 3076 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3077 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3078 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3079 3080 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3081 /* 3082 * Program the multicast hash table. 3083 */ 3084 for (i = 0; i < MCHASH_NWORDS; i++) { 3085 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3086 mchash[i]); 3087 } 3088 } 3089 #undef FILTER_EMIT 3090 #undef MCHASH_NWORDS 3091 3092 /* 3093 * Re-enable the receiver filter. 3094 */ 3095 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3096 } 3097 3098 #if defined(DP83820) 3099 /* 3100 * sip_dp83820_mii_readreg: [mii interface function] 3101 * 3102 * Read a PHY register on the MII of the DP83820. 3103 */ 3104 static int 3105 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3106 { 3107 struct sip_softc *sc = (void *) self; 3108 3109 if (sc->sc_cfg & CFG_TBI_EN) { 3110 bus_addr_t tbireg; 3111 int rv; 3112 3113 if (phy != 0) 3114 return (0); 3115 3116 switch (reg) { 3117 case MII_BMCR: tbireg = SIP_TBICR; break; 3118 case MII_BMSR: tbireg = SIP_TBISR; break; 3119 case MII_ANAR: tbireg = SIP_TANAR; break; 3120 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3121 case MII_ANER: tbireg = SIP_TANER; break; 3122 case MII_EXTSR: 3123 /* 3124 * Don't even bother reading the TESR register. 3125 * The manual documents that the device has 3126 * 1000baseX full/half capability, but the 3127 * register itself seems read back 0 on some 3128 * boards. Just hard-code the result. 3129 */ 3130 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3131 3132 default: 3133 return (0); 3134 } 3135 3136 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3137 if (tbireg == SIP_TBISR) { 3138 /* LINK and ACOMP are switched! */ 3139 int val = rv; 3140 3141 rv = 0; 3142 if (val & TBISR_MR_LINK_STATUS) 3143 rv |= BMSR_LINK; 3144 if (val & TBISR_MR_AN_COMPLETE) 3145 rv |= BMSR_ACOMP; 3146 3147 /* 3148 * The manual claims this register reads back 0 3149 * on hard and soft reset. But we want to let 3150 * the gentbi driver know that we support auto- 3151 * negotiation, so hard-code this bit in the 3152 * result. 3153 */ 3154 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3155 } 3156 3157 return (rv); 3158 } 3159 3160 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3161 phy, reg)); 3162 } 3163 3164 /* 3165 * sip_dp83820_mii_writereg: [mii interface function] 3166 * 3167 * Write a PHY register on the MII of the DP83820. 3168 */ 3169 static void 3170 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3171 { 3172 struct sip_softc *sc = (void *) self; 3173 3174 if (sc->sc_cfg & CFG_TBI_EN) { 3175 bus_addr_t tbireg; 3176 3177 if (phy != 0) 3178 return; 3179 3180 switch (reg) { 3181 case MII_BMCR: tbireg = SIP_TBICR; break; 3182 case MII_ANAR: tbireg = SIP_TANAR; break; 3183 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3184 default: 3185 return; 3186 } 3187 3188 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3189 return; 3190 } 3191 3192 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3193 phy, reg, val); 3194 } 3195 3196 /* 3197 * sip_dp83820_mii_statchg: [mii interface function] 3198 * 3199 * Callback from MII layer when media changes. 3200 */ 3201 static void 3202 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3203 { 3204 struct sip_softc *sc = (struct sip_softc *) self; 3205 struct mii_data *mii = &sc->sc_mii; 3206 u_int32_t cfg, pcr; 3207 3208 /* 3209 * Get flow control negotiation result. 3210 */ 3211 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3212 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3213 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3214 mii->mii_media_active &= ~IFM_ETH_FMASK; 3215 } 3216 3217 /* 3218 * Update TXCFG for full-duplex operation. 3219 */ 3220 if ((mii->mii_media_active & IFM_FDX) != 0) 3221 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3222 else 3223 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3224 3225 /* 3226 * Update RXCFG for full-duplex or loopback. 3227 */ 3228 if ((mii->mii_media_active & IFM_FDX) != 0 || 3229 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3230 sc->sc_rxcfg |= RXCFG_ATX; 3231 else 3232 sc->sc_rxcfg &= ~RXCFG_ATX; 3233 3234 /* 3235 * Update CFG for MII/GMII. 3236 */ 3237 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3238 cfg = sc->sc_cfg | CFG_MODE_1000; 3239 else 3240 cfg = sc->sc_cfg; 3241 3242 /* 3243 * 802.3x flow control. 3244 */ 3245 pcr = 0; 3246 if (sc->sc_flowflags & IFM_FLOW) { 3247 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3248 pcr |= sc->sc_rx_flow_thresh; 3249 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3250 pcr |= PCR_PSEN | PCR_PS_MCAST; 3251 } 3252 3253 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3254 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3255 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3256 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3257 } 3258 #endif /* ! DP83820 */ 3259 3260 /* 3261 * sip_mii_bitbang_read: [mii bit-bang interface function] 3262 * 3263 * Read the MII serial port for the MII bit-bang module. 3264 */ 3265 static u_int32_t 3266 SIP_DECL(mii_bitbang_read)(struct device *self) 3267 { 3268 struct sip_softc *sc = (void *) self; 3269 3270 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3271 } 3272 3273 /* 3274 * sip_mii_bitbang_write: [mii big-bang interface function] 3275 * 3276 * Write the MII serial port for the MII bit-bang module. 3277 */ 3278 static void 3279 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3280 { 3281 struct sip_softc *sc = (void *) self; 3282 3283 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3284 } 3285 3286 #ifndef DP83820 3287 /* 3288 * sip_sis900_mii_readreg: [mii interface function] 3289 * 3290 * Read a PHY register on the MII. 3291 */ 3292 static int 3293 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3294 { 3295 struct sip_softc *sc = (struct sip_softc *) self; 3296 u_int32_t enphy; 3297 3298 /* 3299 * The PHY of recent SiS chipsets is accessed through bitbang 3300 * operations. 3301 */ 3302 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3303 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3304 phy, reg)); 3305 3306 #ifndef SIS900_MII_RESTRICT 3307 /* 3308 * The SiS 900 has only an internal PHY on the MII. Only allow 3309 * MII address 0. 3310 */ 3311 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3312 return (0); 3313 #endif 3314 3315 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3316 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3317 ENPHY_RWCMD | ENPHY_ACCESS); 3318 do { 3319 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3320 } while (enphy & ENPHY_ACCESS); 3321 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3322 } 3323 3324 /* 3325 * sip_sis900_mii_writereg: [mii interface function] 3326 * 3327 * Write a PHY register on the MII. 3328 */ 3329 static void 3330 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3331 { 3332 struct sip_softc *sc = (struct sip_softc *) self; 3333 u_int32_t enphy; 3334 3335 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3336 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3337 phy, reg, val); 3338 return; 3339 } 3340 3341 #ifndef SIS900_MII_RESTRICT 3342 /* 3343 * The SiS 900 has only an internal PHY on the MII. Only allow 3344 * MII address 0. 3345 */ 3346 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3347 return; 3348 #endif 3349 3350 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3351 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3352 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3353 do { 3354 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3355 } while (enphy & ENPHY_ACCESS); 3356 } 3357 3358 /* 3359 * sip_sis900_mii_statchg: [mii interface function] 3360 * 3361 * Callback from MII layer when media changes. 3362 */ 3363 static void 3364 SIP_DECL(sis900_mii_statchg)(struct device *self) 3365 { 3366 struct sip_softc *sc = (struct sip_softc *) self; 3367 struct mii_data *mii = &sc->sc_mii; 3368 u_int32_t flowctl; 3369 3370 /* 3371 * Get flow control negotiation result. 3372 */ 3373 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3374 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3375 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3376 mii->mii_media_active &= ~IFM_ETH_FMASK; 3377 } 3378 3379 /* 3380 * Update TXCFG for full-duplex operation. 3381 */ 3382 if ((mii->mii_media_active & IFM_FDX) != 0) 3383 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3384 else 3385 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3386 3387 /* 3388 * Update RXCFG for full-duplex or loopback. 3389 */ 3390 if ((mii->mii_media_active & IFM_FDX) != 0 || 3391 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3392 sc->sc_rxcfg |= RXCFG_ATX; 3393 else 3394 sc->sc_rxcfg &= ~RXCFG_ATX; 3395 3396 /* 3397 * Update IMR for use of 802.3x flow control. 3398 */ 3399 if (sc->sc_flowflags & IFM_FLOW) { 3400 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3401 flowctl = FLOWCTL_FLOWEN; 3402 } else { 3403 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3404 flowctl = 0; 3405 } 3406 3407 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3408 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3409 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3410 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3411 } 3412 3413 /* 3414 * sip_dp83815_mii_readreg: [mii interface function] 3415 * 3416 * Read a PHY register on the MII. 3417 */ 3418 static int 3419 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3420 { 3421 struct sip_softc *sc = (struct sip_softc *) self; 3422 u_int32_t val; 3423 3424 /* 3425 * The DP83815 only has an internal PHY. Only allow 3426 * MII address 0. 3427 */ 3428 if (phy != 0) 3429 return (0); 3430 3431 /* 3432 * Apparently, after a reset, the DP83815 can take a while 3433 * to respond. During this recovery period, the BMSR returns 3434 * a value of 0. Catch this -- it's not supposed to happen 3435 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3436 * PHY to come back to life. 3437 * 3438 * This works out because the BMSR is the first register 3439 * read during the PHY probe process. 3440 */ 3441 do { 3442 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3443 } while (reg == MII_BMSR && val == 0); 3444 3445 return (val & 0xffff); 3446 } 3447 3448 /* 3449 * sip_dp83815_mii_writereg: [mii interface function] 3450 * 3451 * Write a PHY register to the MII. 3452 */ 3453 static void 3454 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3455 { 3456 struct sip_softc *sc = (struct sip_softc *) self; 3457 3458 /* 3459 * The DP83815 only has an internal PHY. Only allow 3460 * MII address 0. 3461 */ 3462 if (phy != 0) 3463 return; 3464 3465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3466 } 3467 3468 /* 3469 * sip_dp83815_mii_statchg: [mii interface function] 3470 * 3471 * Callback from MII layer when media changes. 3472 */ 3473 static void 3474 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3475 { 3476 struct sip_softc *sc = (struct sip_softc *) self; 3477 3478 /* 3479 * Update TXCFG for full-duplex operation. 3480 */ 3481 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3482 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3483 else 3484 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3485 3486 /* 3487 * Update RXCFG for full-duplex or loopback. 3488 */ 3489 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3490 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3491 sc->sc_rxcfg |= RXCFG_ATX; 3492 else 3493 sc->sc_rxcfg &= ~RXCFG_ATX; 3494 3495 /* 3496 * XXX 802.3x flow control. 3497 */ 3498 3499 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3500 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3501 3502 /* 3503 * Some DP83815s experience problems when used with short 3504 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3505 * sequence adjusts the DSP's signal attenuation to fix the 3506 * problem. 3507 */ 3508 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3509 uint32_t reg; 3510 3511 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3512 3513 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3514 reg &= 0x0fff; 3515 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3516 delay(100); 3517 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3518 reg &= 0x00ff; 3519 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3520 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3521 0x00e8); 3522 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3523 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3524 reg | 0x20); 3525 } 3526 3527 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3528 } 3529 } 3530 #endif /* DP83820 */ 3531 3532 #if defined(DP83820) 3533 static void 3534 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3535 const struct pci_attach_args *pa, u_int8_t *enaddr) 3536 { 3537 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3538 u_int8_t cksum, *e, match; 3539 int i; 3540 3541 /* 3542 * EEPROM data format for the DP83820 can be found in 3543 * the DP83820 manual, section 4.2.4. 3544 */ 3545 3546 SIP_DECL(read_eeprom)(sc, 0, 3547 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3548 3549 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3550 match = ~(match - 1); 3551 3552 cksum = 0x55; 3553 e = (u_int8_t *) eeprom_data; 3554 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3555 cksum += *e++; 3556 3557 if (cksum != match) 3558 printf("%s: Checksum (%x) mismatch (%x)", 3559 sc->sc_dev.dv_xname, cksum, match); 3560 3561 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3562 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3563 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3564 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3565 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3566 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3567 } 3568 #else /* ! DP83820 */ 3569 static void 3570 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3571 { 3572 int i; 3573 3574 /* 3575 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3576 * a reason, but I don't know it. 3577 */ 3578 for (i = 0; i < 10; i++) 3579 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3580 } 3581 3582 static void 3583 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3584 const struct pci_attach_args *pa, u_int8_t *enaddr) 3585 { 3586 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3587 3588 switch (sc->sc_rev) { 3589 case SIS_REV_630S: 3590 case SIS_REV_630E: 3591 case SIS_REV_630EA1: 3592 case SIS_REV_630ET: 3593 case SIS_REV_635: 3594 /* 3595 * The MAC address for the on-board Ethernet of 3596 * the SiS 630 chipset is in the NVRAM. Kick 3597 * the chip into re-loading it from NVRAM, and 3598 * read the MAC address out of the filter registers. 3599 */ 3600 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3601 3602 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3603 RFCR_RFADDR_NODE0); 3604 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3605 0xffff; 3606 3607 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3608 RFCR_RFADDR_NODE2); 3609 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3610 0xffff; 3611 3612 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3613 RFCR_RFADDR_NODE4); 3614 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3615 0xffff; 3616 break; 3617 3618 case SIS_REV_960: 3619 { 3620 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3621 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3622 3623 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3624 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3625 3626 int waittime, i; 3627 3628 /* Allow to read EEPROM from LAN. It is shared 3629 * between a 1394 controller and the NIC and each 3630 * time we access it, we need to set SIS_EECMD_REQ. 3631 */ 3632 SIS_SET_EROMAR(sc, EROMAR_REQ); 3633 3634 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3635 /* Force EEPROM to idle state. */ 3636 3637 /* 3638 * XXX-cube This is ugly. I'll look for docs about it. 3639 */ 3640 SIS_SET_EROMAR(sc, EROMAR_EECS); 3641 SIP_DECL(sis900_eeprom_delay)(sc); 3642 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3643 SIS_SET_EROMAR(sc, EROMAR_EESK); 3644 SIP_DECL(sis900_eeprom_delay)(sc); 3645 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3646 SIP_DECL(sis900_eeprom_delay)(sc); 3647 } 3648 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3649 SIP_DECL(sis900_eeprom_delay)(sc); 3650 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3651 3652 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3653 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3654 sizeof(myea) / sizeof(myea[0]), myea); 3655 break; 3656 } 3657 DELAY(1); 3658 } 3659 3660 /* 3661 * Set SIS_EECTL_CLK to high, so a other master 3662 * can operate on the i2c bus. 3663 */ 3664 SIS_SET_EROMAR(sc, EROMAR_EESK); 3665 3666 /* Refuse EEPROM access by LAN */ 3667 SIS_SET_EROMAR(sc, EROMAR_DONE); 3668 } break; 3669 3670 default: 3671 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3672 sizeof(myea) / sizeof(myea[0]), myea); 3673 } 3674 3675 enaddr[0] = myea[0] & 0xff; 3676 enaddr[1] = myea[0] >> 8; 3677 enaddr[2] = myea[1] & 0xff; 3678 enaddr[3] = myea[1] >> 8; 3679 enaddr[4] = myea[2] & 0xff; 3680 enaddr[5] = myea[2] >> 8; 3681 } 3682 3683 /* Table and macro to bit-reverse an octet. */ 3684 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3685 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3686 3687 static void 3688 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3689 const struct pci_attach_args *pa, u_int8_t *enaddr) 3690 { 3691 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3692 u_int8_t cksum, *e, match; 3693 int i; 3694 3695 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3696 sizeof(eeprom_data[0]), eeprom_data); 3697 3698 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3699 match = ~(match - 1); 3700 3701 cksum = 0x55; 3702 e = (u_int8_t *) eeprom_data; 3703 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3704 cksum += *e++; 3705 } 3706 if (cksum != match) { 3707 printf("%s: Checksum (%x) mismatch (%x)", 3708 sc->sc_dev.dv_xname, cksum, match); 3709 } 3710 3711 /* 3712 * Unrolled because it makes slightly more sense this way. 3713 * The DP83815 stores the MAC address in bit 0 of word 6 3714 * through bit 15 of word 8. 3715 */ 3716 ea = &eeprom_data[6]; 3717 enaddr[0] = ((*ea & 0x1) << 7); 3718 ea++; 3719 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3720 enaddr[1] = ((*ea & 0x1FE) >> 1); 3721 enaddr[2] = ((*ea & 0x1) << 7); 3722 ea++; 3723 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3724 enaddr[3] = ((*ea & 0x1FE) >> 1); 3725 enaddr[4] = ((*ea & 0x1) << 7); 3726 ea++; 3727 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3728 enaddr[5] = ((*ea & 0x1FE) >> 1); 3729 3730 /* 3731 * In case that's not weird enough, we also need to reverse 3732 * the bits in each byte. This all actually makes more sense 3733 * if you think about the EEPROM storage as an array of bits 3734 * being shifted into bytes, but that's not how we're looking 3735 * at it here... 3736 */ 3737 for (i = 0; i < 6 ;i++) 3738 enaddr[i] = bbr(enaddr[i]); 3739 } 3740 #endif /* DP83820 */ 3741 3742 /* 3743 * sip_mediastatus: [ifmedia interface function] 3744 * 3745 * Get the current interface media status. 3746 */ 3747 static void 3748 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3749 { 3750 struct sip_softc *sc = ifp->if_softc; 3751 3752 mii_pollstat(&sc->sc_mii); 3753 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3754 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3755 sc->sc_flowflags; 3756 } 3757 3758 /* 3759 * sip_mediachange: [ifmedia interface function] 3760 * 3761 * Set hardware to newly-selected media. 3762 */ 3763 static int 3764 SIP_DECL(mediachange)(struct ifnet *ifp) 3765 { 3766 struct sip_softc *sc = ifp->if_softc; 3767 3768 if (ifp->if_flags & IFF_UP) 3769 mii_mediachg(&sc->sc_mii); 3770 return (0); 3771 } 3772
Indexes created Tue Sep 30 11:09:46 GMT 2025