if_sip.c revision 1.102.2.1
1 /* $NetBSD: if_sip.c,v 1.102.2.1 2006/06/21 15:05:05 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.102.2.1 2006/06/21 15:05:05 yamt Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 /* values of interface state at last init */ 313 struct { 314 /* if_capenable */ 315 uint64_t if_capenable; 316 /* ec_capenable */ 317 int ec_capenable; 318 /* VLAN_ATTACHED */ 319 int is_vlan; 320 } sc_prev; 321 322 short sc_if_flags; 323 324 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 325 #if defined(DP83820) 326 int sc_rxdiscard; 327 int sc_rxlen; 328 struct mbuf *sc_rxhead; 329 struct mbuf *sc_rxtail; 330 struct mbuf **sc_rxtailp; 331 #endif /* DP83820 */ 332 333 #if NRND > 0 334 rndsource_element_t rnd_source; /* random source */ 335 #endif 336 }; 337 338 #ifdef DP83820 339 #define SIP_RXCHAIN_RESET(sc) \ 340 do { \ 341 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 342 *(sc)->sc_rxtailp = NULL; \ 343 (sc)->sc_rxlen = 0; \ 344 } while (/*CONSTCOND*/0) 345 346 #define SIP_RXCHAIN_LINK(sc, m) \ 347 do { \ 348 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 349 (sc)->sc_rxtailp = &(m)->m_next; \ 350 } while (/*CONSTCOND*/0) 351 #endif /* DP83820 */ 352 353 #ifdef SIP_EVENT_COUNTERS 354 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 355 #else 356 #define SIP_EVCNT_INCR(ev) /* nothing */ 357 #endif 358 359 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 360 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 361 362 #define SIP_CDTXSYNC(sc, x, n, ops) \ 363 do { \ 364 int __x, __n; \ 365 \ 366 __x = (x); \ 367 __n = (n); \ 368 \ 369 /* If it will wrap around, sync to the end of the ring. */ \ 370 if ((__x + __n) > SIP_NTXDESC) { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 373 (SIP_NTXDESC - __x), (ops)); \ 374 __n -= (SIP_NTXDESC - __x); \ 375 __x = 0; \ 376 } \ 377 \ 378 /* Now sync whatever is left. */ \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 381 } while (0) 382 383 #define SIP_CDRXSYNC(sc, x, ops) \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 386 387 #ifdef DP83820 388 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 389 #define SIP_RXBUF_LEN (MCLBYTES - 8) 390 #else 391 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 392 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 393 #endif 394 #define SIP_INIT_RXDESC(sc, x) \ 395 do { \ 396 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 397 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 398 \ 399 __sipd->sipd_link = \ 400 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 401 __sipd->sipd_bufptr = \ 402 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 403 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 404 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 405 SIP_INIT_RXDESC_EXTSTS \ 406 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 407 } while (0) 408 409 #define SIP_CHIP_VERS(sc, v, p, r) \ 410 ((sc)->sc_model->sip_vendor == (v) && \ 411 (sc)->sc_model->sip_product == (p) && \ 412 (sc)->sc_rev == (r)) 413 414 #define SIP_CHIP_MODEL(sc, v, p) \ 415 ((sc)->sc_model->sip_vendor == (v) && \ 416 (sc)->sc_model->sip_product == (p)) 417 418 #if !defined(DP83820) 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 #endif 422 423 #define SIP_TIMEOUT 1000 424 425 static void SIP_DECL(start)(struct ifnet *); 426 static void SIP_DECL(watchdog)(struct ifnet *); 427 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 428 static int SIP_DECL(init)(struct ifnet *); 429 static void SIP_DECL(stop)(struct ifnet *, int); 430 431 static void SIP_DECL(shutdown)(void *); 432 433 static void SIP_DECL(reset)(struct sip_softc *); 434 static void SIP_DECL(rxdrain)(struct sip_softc *); 435 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 436 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 437 u_int16_t *); 438 static void SIP_DECL(tick)(void *); 439 440 #if !defined(DP83820) 441 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 442 #endif /* ! DP83820 */ 443 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 444 445 #if defined(DP83820) 446 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 447 const struct pci_attach_args *, u_int8_t *); 448 #else 449 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 450 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 451 const struct pci_attach_args *, u_int8_t *); 452 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 453 const struct pci_attach_args *, u_int8_t *); 454 #endif /* DP83820 */ 455 456 static int SIP_DECL(intr)(void *); 457 static void SIP_DECL(txintr)(struct sip_softc *); 458 static void SIP_DECL(rxintr)(struct sip_softc *); 459 460 #if defined(DP83820) 461 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 462 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 463 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 464 #else 465 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 466 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 467 static void SIP_DECL(sis900_mii_statchg)(struct device *); 468 469 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 470 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 471 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 472 #endif /* DP83820 */ 473 474 static int SIP_DECL(mediachange)(struct ifnet *); 475 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 476 477 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 478 static void SIP_DECL(attach)(struct device *, struct device *, void *); 479 480 int SIP_DECL(copy_small) = 0; 481 482 #ifdef DP83820 483 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 484 gsip_match, gsip_attach, NULL, NULL); 485 #else 486 CFATTACH_DECL(sip, sizeof(struct sip_softc), 487 sip_match, sip_attach, NULL, NULL); 488 #endif 489 490 /* 491 * Descriptions of the variants of the SiS900. 492 */ 493 struct sip_variant { 494 int (*sipv_mii_readreg)(struct device *, int, int); 495 void (*sipv_mii_writereg)(struct device *, int, int, int); 496 void (*sipv_mii_statchg)(struct device *); 497 void (*sipv_set_filter)(struct sip_softc *); 498 void (*sipv_read_macaddr)(struct sip_softc *, 499 const struct pci_attach_args *, u_int8_t *); 500 }; 501 502 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 503 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 504 505 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 506 SIP_DECL(mii_bitbang_read), 507 SIP_DECL(mii_bitbang_write), 508 { 509 EROMAR_MDIO, /* MII_BIT_MDO */ 510 EROMAR_MDIO, /* MII_BIT_MDI */ 511 EROMAR_MDC, /* MII_BIT_MDC */ 512 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 513 0, /* MII_BIT_DIR_PHY_HOST */ 514 } 515 }; 516 517 #if defined(DP83820) 518 static const struct sip_variant SIP_DECL(variant_dp83820) = { 519 SIP_DECL(dp83820_mii_readreg), 520 SIP_DECL(dp83820_mii_writereg), 521 SIP_DECL(dp83820_mii_statchg), 522 SIP_DECL(dp83815_set_filter), 523 SIP_DECL(dp83820_read_macaddr), 524 }; 525 #else 526 static const struct sip_variant SIP_DECL(variant_sis900) = { 527 SIP_DECL(sis900_mii_readreg), 528 SIP_DECL(sis900_mii_writereg), 529 SIP_DECL(sis900_mii_statchg), 530 SIP_DECL(sis900_set_filter), 531 SIP_DECL(sis900_read_macaddr), 532 }; 533 534 static const struct sip_variant SIP_DECL(variant_dp83815) = { 535 SIP_DECL(dp83815_mii_readreg), 536 SIP_DECL(dp83815_mii_writereg), 537 SIP_DECL(dp83815_mii_statchg), 538 SIP_DECL(dp83815_set_filter), 539 SIP_DECL(dp83815_read_macaddr), 540 }; 541 #endif /* DP83820 */ 542 543 /* 544 * Devices supported by this driver. 545 */ 546 static const struct sip_product { 547 pci_vendor_id_t sip_vendor; 548 pci_product_id_t sip_product; 549 const char *sip_name; 550 const struct sip_variant *sip_variant; 551 } SIP_DECL(products)[] = { 552 #if defined(DP83820) 553 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 554 "NatSemi DP83820 Gigabit Ethernet", 555 &SIP_DECL(variant_dp83820) }, 556 #else 557 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 558 "SiS 900 10/100 Ethernet", 559 &SIP_DECL(variant_sis900) }, 560 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 561 "SiS 7016 10/100 Ethernet", 562 &SIP_DECL(variant_sis900) }, 563 564 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 565 "NatSemi DP83815 10/100 Ethernet", 566 &SIP_DECL(variant_dp83815) }, 567 #endif /* DP83820 */ 568 569 { 0, 0, 570 NULL, 571 NULL }, 572 }; 573 574 static const struct sip_product * 575 SIP_DECL(lookup)(const struct pci_attach_args *pa) 576 { 577 const struct sip_product *sip; 578 579 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 580 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 581 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 582 return (sip); 583 } 584 return (NULL); 585 } 586 587 #ifdef DP83820 588 /* 589 * I really hate stupid hardware vendors. There's a bit in the EEPROM 590 * which indicates if the card can do 64-bit data transfers. Unfortunately, 591 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 592 * which means we try to use 64-bit data transfers on those cards if we 593 * happen to be plugged into a 32-bit slot. 594 * 595 * What we do is use this table of cards known to be 64-bit cards. If 596 * you have a 64-bit card who's subsystem ID is not listed in this table, 597 * send the output of "pcictl dump ..." of the device to me so that your 598 * card will use the 64-bit data path when plugged into a 64-bit slot. 599 * 600 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 601 * June 30, 2002 602 */ 603 static int 604 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 605 { 606 static const struct { 607 pci_vendor_id_t c64_vendor; 608 pci_product_id_t c64_product; 609 } card64[] = { 610 /* Asante GigaNIX */ 611 { 0x128a, 0x0002 }, 612 613 /* Accton EN1407-T, Planex GN-1000TE */ 614 { 0x1113, 0x1407 }, 615 616 /* Netgear GA-621 */ 617 { 0x1385, 0x621a }, 618 619 /* SMC EZ Card */ 620 { 0x10b8, 0x9462 }, 621 622 { 0, 0} 623 }; 624 pcireg_t subsys; 625 int i; 626 627 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 628 629 for (i = 0; card64[i].c64_vendor != 0; i++) { 630 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 631 PCI_PRODUCT(subsys) == card64[i].c64_product) 632 return (1); 633 } 634 635 return (0); 636 } 637 #endif /* DP83820 */ 638 639 static int 640 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 641 { 642 struct pci_attach_args *pa = aux; 643 644 if (SIP_DECL(lookup)(pa) != NULL) 645 return (1); 646 647 return (0); 648 } 649 650 static void 651 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 652 { 653 struct sip_softc *sc = (struct sip_softc *) self; 654 struct pci_attach_args *pa = aux; 655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 656 pci_chipset_tag_t pc = pa->pa_pc; 657 pci_intr_handle_t ih; 658 const char *intrstr = NULL; 659 bus_space_tag_t iot, memt; 660 bus_space_handle_t ioh, memh; 661 bus_dma_segment_t seg; 662 int ioh_valid, memh_valid; 663 int i, rseg, error; 664 const struct sip_product *sip; 665 u_int8_t enaddr[ETHER_ADDR_LEN]; 666 pcireg_t pmreg; 667 #ifdef DP83820 668 pcireg_t memtype; 669 u_int32_t reg; 670 #endif /* DP83820 */ 671 672 callout_init(&sc->sc_tick_ch); 673 674 sip = SIP_DECL(lookup)(pa); 675 if (sip == NULL) { 676 printf("\n"); 677 panic(SIP_STR(attach) ": impossible"); 678 } 679 sc->sc_rev = PCI_REVISION(pa->pa_class); 680 681 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 682 683 sc->sc_model = sip; 684 685 /* 686 * XXX Work-around broken PXE firmware on some boards. 687 * 688 * The DP83815 shares an address decoder with the MEM BAR 689 * and the ROM BAR. Make sure the ROM BAR is disabled, 690 * so that memory mapped access works. 691 */ 692 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 693 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 694 ~PCI_MAPREG_ROM_ENABLE); 695 696 /* 697 * Map the device. 698 */ 699 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 700 PCI_MAPREG_TYPE_IO, 0, 701 &iot, &ioh, NULL, NULL) == 0); 702 #ifdef DP83820 703 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 704 switch (memtype) { 705 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 706 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 707 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 708 memtype, 0, &memt, &memh, NULL, NULL) == 0); 709 break; 710 default: 711 memh_valid = 0; 712 } 713 #else 714 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 715 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 716 &memt, &memh, NULL, NULL) == 0); 717 #endif /* DP83820 */ 718 719 if (memh_valid) { 720 sc->sc_st = memt; 721 sc->sc_sh = memh; 722 } else if (ioh_valid) { 723 sc->sc_st = iot; 724 sc->sc_sh = ioh; 725 } else { 726 printf("%s: unable to map device registers\n", 727 sc->sc_dev.dv_xname); 728 return; 729 } 730 731 sc->sc_dmat = pa->pa_dmat; 732 733 /* 734 * Make sure bus mastering is enabled. Also make sure 735 * Write/Invalidate is enabled if we're allowed to use it. 736 */ 737 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 738 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 739 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 740 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 741 pmreg | PCI_COMMAND_MASTER_ENABLE); 742 743 /* power up chip */ 744 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 745 NULL)) && error != EOPNOTSUPP) { 746 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 747 error); 748 return; 749 } 750 751 /* 752 * Map and establish our interrupt. 753 */ 754 if (pci_intr_map(pa, &ih)) { 755 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 756 return; 757 } 758 intrstr = pci_intr_string(pc, ih); 759 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 760 if (sc->sc_ih == NULL) { 761 printf("%s: unable to establish interrupt", 762 sc->sc_dev.dv_xname); 763 if (intrstr != NULL) 764 printf(" at %s", intrstr); 765 printf("\n"); 766 return; 767 } 768 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 769 770 SIMPLEQ_INIT(&sc->sc_txfreeq); 771 SIMPLEQ_INIT(&sc->sc_txdirtyq); 772 773 /* 774 * Allocate the control data structures, and create and load the 775 * DMA map for it. 776 */ 777 if ((error = bus_dmamem_alloc(sc->sc_dmat, 778 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 779 0)) != 0) { 780 printf("%s: unable to allocate control data, error = %d\n", 781 sc->sc_dev.dv_xname, error); 782 goto fail_0; 783 } 784 785 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 786 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 787 BUS_DMA_COHERENT)) != 0) { 788 printf("%s: unable to map control data, error = %d\n", 789 sc->sc_dev.dv_xname, error); 790 goto fail_1; 791 } 792 793 if ((error = bus_dmamap_create(sc->sc_dmat, 794 sizeof(struct sip_control_data), 1, 795 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 796 printf("%s: unable to create control data DMA map, " 797 "error = %d\n", sc->sc_dev.dv_xname, error); 798 goto fail_2; 799 } 800 801 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 802 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 803 0)) != 0) { 804 printf("%s: unable to load control data DMA map, error = %d\n", 805 sc->sc_dev.dv_xname, error); 806 goto fail_3; 807 } 808 809 /* 810 * Create the transmit buffer DMA maps. 811 */ 812 for (i = 0; i < SIP_TXQUEUELEN; i++) { 813 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 814 SIP_NTXSEGS, MCLBYTES, 0, 0, 815 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 816 printf("%s: unable to create tx DMA map %d, " 817 "error = %d\n", sc->sc_dev.dv_xname, i, error); 818 goto fail_4; 819 } 820 } 821 822 /* 823 * Create the receive buffer DMA maps. 824 */ 825 for (i = 0; i < SIP_NRXDESC; i++) { 826 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 827 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 828 printf("%s: unable to create rx DMA map %d, " 829 "error = %d\n", sc->sc_dev.dv_xname, i, error); 830 goto fail_5; 831 } 832 sc->sc_rxsoft[i].rxs_mbuf = NULL; 833 } 834 835 /* 836 * Reset the chip to a known state. 837 */ 838 SIP_DECL(reset)(sc); 839 840 /* 841 * Read the Ethernet address from the EEPROM. This might 842 * also fetch other stuff from the EEPROM and stash it 843 * in the softc. 844 */ 845 sc->sc_cfg = 0; 846 #if !defined(DP83820) 847 if (SIP_SIS900_REV(sc,SIS_REV_635) || 848 SIP_SIS900_REV(sc,SIS_REV_900B)) 849 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 850 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_960) || 853 SIP_SIS900_REV(sc,SIS_REV_900B)) 854 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 855 SIP_CFG) & CFG_EDBMASTEN); 856 #endif 857 858 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 859 860 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 861 ether_sprintf(enaddr)); 862 863 /* 864 * Initialize the configuration register: aggressive PCI 865 * bus request algorithm, default backoff, default OW timer, 866 * default parity error detection. 867 * 868 * NOTE: "Big endian mode" is useless on the SiS900 and 869 * friends -- it affects packet data, not descriptors. 870 */ 871 #ifdef DP83820 872 /* 873 * Cause the chip to load configuration data from the EEPROM. 874 */ 875 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 876 for (i = 0; i < 10000; i++) { 877 delay(10); 878 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 879 PTSCR_EELOAD_EN) == 0) 880 break; 881 } 882 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) { 884 printf("%s: timeout loading configuration from EEPROM\n", 885 sc->sc_dev.dv_xname); 886 return; 887 } 888 889 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 890 891 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 892 if (reg & CFG_PCI64_DET) { 893 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 894 /* 895 * Check to see if this card is 64-bit. If so, enable 64-bit 896 * data transfers. 897 * 898 * We can't use the DATA64_EN bit in the EEPROM, because 899 * vendors of 32-bit cards fail to clear that bit in many 900 * cases (yet the card still detects that it's in a 64-bit 901 * slot; go figure). 902 */ 903 if (SIP_DECL(check_64bit)(pa)) { 904 sc->sc_cfg |= CFG_DATA64_EN; 905 printf(", using 64-bit data transfers"); 906 } 907 printf("\n"); 908 } 909 910 /* 911 * XXX Need some PCI flags indicating support for 912 * XXX 64-bit addressing. 913 */ 914 #if 0 915 if (reg & CFG_M64ADDR) 916 sc->sc_cfg |= CFG_M64ADDR; 917 if (reg & CFG_T64ADDR) 918 sc->sc_cfg |= CFG_T64ADDR; 919 #endif 920 921 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 922 const char *sep = ""; 923 printf("%s: using ", sc->sc_dev.dv_xname); 924 if (reg & CFG_EXT_125) { 925 sc->sc_cfg |= CFG_EXT_125; 926 printf("%s125MHz clock", sep); 927 sep = ", "; 928 } 929 if (reg & CFG_TBI_EN) { 930 sc->sc_cfg |= CFG_TBI_EN; 931 printf("%sten-bit interface", sep); 932 sep = ", "; 933 } 934 printf("\n"); 935 } 936 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 937 (reg & CFG_MRM_DIS) != 0) 938 sc->sc_cfg |= CFG_MRM_DIS; 939 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 940 (reg & CFG_MWI_DIS) != 0) 941 sc->sc_cfg |= CFG_MWI_DIS; 942 943 /* 944 * Use the extended descriptor format on the DP83820. This 945 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 946 * checksumming. 947 */ 948 sc->sc_cfg |= CFG_EXTSTS_EN; 949 #endif /* DP83820 */ 950 951 /* 952 * Initialize our media structures and probe the MII. 953 */ 954 sc->sc_mii.mii_ifp = ifp; 955 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 956 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 957 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 958 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 959 SIP_DECL(mediastatus)); 960 961 /* 962 * XXX We cannot handle flow control on the DP83815. 963 */ 964 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 965 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 966 MII_OFFSET_ANY, 0); 967 else 968 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 969 MII_OFFSET_ANY, MIIF_DOPAUSE); 970 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 971 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 972 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 973 } else 974 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 975 976 ifp = &sc->sc_ethercom.ec_if; 977 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 978 ifp->if_softc = sc; 979 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 980 sc->sc_if_flags = ifp->if_flags; 981 ifp->if_ioctl = SIP_DECL(ioctl); 982 ifp->if_start = SIP_DECL(start); 983 ifp->if_watchdog = SIP_DECL(watchdog); 984 ifp->if_init = SIP_DECL(init); 985 ifp->if_stop = SIP_DECL(stop); 986 IFQ_SET_READY(&ifp->if_snd); 987 988 /* 989 * We can support 802.1Q VLAN-sized frames. 990 */ 991 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 992 993 #ifdef DP83820 994 /* 995 * And the DP83820 can do VLAN tagging in hardware, and 996 * support the jumbo Ethernet MTU. 997 */ 998 sc->sc_ethercom.ec_capabilities |= 999 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1000 1001 /* 1002 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1003 * in hardware. 1004 */ 1005 ifp->if_capabilities |= 1006 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1007 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1008 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1009 #endif /* DP83820 */ 1010 1011 /* 1012 * Attach the interface. 1013 */ 1014 if_attach(ifp); 1015 ether_ifattach(ifp, enaddr); 1016 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1017 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1018 sc->sc_prev.if_capenable = ifp->if_capenable; 1019 #if NRND > 0 1020 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1021 RND_TYPE_NET, 0); 1022 #endif 1023 1024 /* 1025 * The number of bytes that must be available in 1026 * the Tx FIFO before the bus master can DMA more 1027 * data into the FIFO. 1028 */ 1029 sc->sc_tx_fill_thresh = 64 / 32; 1030 1031 /* 1032 * Start at a drain threshold of 512 bytes. We will 1033 * increase it if a DMA underrun occurs. 1034 * 1035 * XXX The minimum value of this variable should be 1036 * tuned. We may be able to improve performance 1037 * by starting with a lower value. That, however, 1038 * may trash the first few outgoing packets if the 1039 * PCI bus is saturated. 1040 */ 1041 #ifdef DP83820 1042 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1043 #else 1044 sc->sc_tx_drain_thresh = 1504 / 32; 1045 #endif 1046 1047 /* 1048 * Initialize the Rx FIFO drain threshold. 1049 * 1050 * This is in units of 8 bytes. 1051 * 1052 * We should never set this value lower than 2; 14 bytes are 1053 * required to filter the packet. 1054 */ 1055 sc->sc_rx_drain_thresh = 128 / 8; 1056 1057 #ifdef SIP_EVENT_COUNTERS 1058 /* 1059 * Attach event counters. 1060 */ 1061 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1062 NULL, sc->sc_dev.dv_xname, "txsstall"); 1063 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1064 NULL, sc->sc_dev.dv_xname, "txdstall"); 1065 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1066 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1067 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1068 NULL, sc->sc_dev.dv_xname, "txdintr"); 1069 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1070 NULL, sc->sc_dev.dv_xname, "txiintr"); 1071 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1072 NULL, sc->sc_dev.dv_xname, "rxintr"); 1073 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1074 NULL, sc->sc_dev.dv_xname, "hiberr"); 1075 #ifndef DP83820 1076 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1077 NULL, sc->sc_dev.dv_xname, "rxpause"); 1078 #endif /* !DP83820 */ 1079 #ifdef DP83820 1080 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1081 NULL, sc->sc_dev.dv_xname, "rxpause"); 1082 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1083 NULL, sc->sc_dev.dv_xname, "txpause"); 1084 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1085 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1086 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1087 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1088 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1089 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1090 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1091 NULL, sc->sc_dev.dv_xname, "txipsum"); 1092 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1093 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1094 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1095 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1096 #endif /* DP83820 */ 1097 #endif /* SIP_EVENT_COUNTERS */ 1098 1099 /* 1100 * Make sure the interface is shutdown during reboot. 1101 */ 1102 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1103 if (sc->sc_sdhook == NULL) 1104 printf("%s: WARNING: unable to establish shutdown hook\n", 1105 sc->sc_dev.dv_xname); 1106 return; 1107 1108 /* 1109 * Free any resources we've allocated during the failed attach 1110 * attempt. Do this in reverse order and fall through. 1111 */ 1112 fail_5: 1113 for (i = 0; i < SIP_NRXDESC; i++) { 1114 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1115 bus_dmamap_destroy(sc->sc_dmat, 1116 sc->sc_rxsoft[i].rxs_dmamap); 1117 } 1118 fail_4: 1119 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1120 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1121 bus_dmamap_destroy(sc->sc_dmat, 1122 sc->sc_txsoft[i].txs_dmamap); 1123 } 1124 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1125 fail_3: 1126 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1127 fail_2: 1128 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1129 sizeof(struct sip_control_data)); 1130 fail_1: 1131 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1132 fail_0: 1133 return; 1134 } 1135 1136 /* 1137 * sip_shutdown: 1138 * 1139 * Make sure the interface is stopped at reboot time. 1140 */ 1141 static void 1142 SIP_DECL(shutdown)(void *arg) 1143 { 1144 struct sip_softc *sc = arg; 1145 1146 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1147 } 1148 1149 /* 1150 * sip_start: [ifnet interface function] 1151 * 1152 * Start packet transmission on the interface. 1153 */ 1154 static void 1155 SIP_DECL(start)(struct ifnet *ifp) 1156 { 1157 struct sip_softc *sc = ifp->if_softc; 1158 struct mbuf *m0; 1159 #ifndef DP83820 1160 struct mbuf *m; 1161 #endif 1162 struct sip_txsoft *txs; 1163 bus_dmamap_t dmamap; 1164 int error, nexttx, lasttx, seg; 1165 int ofree = sc->sc_txfree; 1166 #if 0 1167 int firsttx = sc->sc_txnext; 1168 #endif 1169 #ifdef DP83820 1170 struct m_tag *mtag; 1171 u_int32_t extsts; 1172 #endif 1173 1174 #ifndef DP83820 1175 /* 1176 * If we've been told to pause, don't transmit any more packets. 1177 */ 1178 if (sc->sc_paused) 1179 ifp->if_flags |= IFF_OACTIVE; 1180 #endif 1181 1182 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1183 return; 1184 1185 /* 1186 * Loop through the send queue, setting up transmit descriptors 1187 * until we drain the queue, or use up all available transmit 1188 * descriptors. 1189 */ 1190 for (;;) { 1191 /* Get a work queue entry. */ 1192 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1193 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1194 break; 1195 } 1196 1197 /* 1198 * Grab a packet off the queue. 1199 */ 1200 IFQ_POLL(&ifp->if_snd, m0); 1201 if (m0 == NULL) 1202 break; 1203 #ifndef DP83820 1204 m = NULL; 1205 #endif 1206 1207 dmamap = txs->txs_dmamap; 1208 1209 #ifdef DP83820 1210 /* 1211 * Load the DMA map. If this fails, the packet either 1212 * didn't fit in the allotted number of segments, or we 1213 * were short on resources. For the too-many-segments 1214 * case, we simply report an error and drop the packet, 1215 * since we can't sanely copy a jumbo packet to a single 1216 * buffer. 1217 */ 1218 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1219 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1220 if (error) { 1221 if (error == EFBIG) { 1222 printf("%s: Tx packet consumes too many " 1223 "DMA segments, dropping...\n", 1224 sc->sc_dev.dv_xname); 1225 IFQ_DEQUEUE(&ifp->if_snd, m0); 1226 m_freem(m0); 1227 continue; 1228 } 1229 /* 1230 * Short on resources, just stop for now. 1231 */ 1232 break; 1233 } 1234 #else /* DP83820 */ 1235 /* 1236 * Load the DMA map. If this fails, the packet either 1237 * didn't fit in the alloted number of segments, or we 1238 * were short on resources. In this case, we'll copy 1239 * and try again. 1240 */ 1241 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1242 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1243 MGETHDR(m, M_DONTWAIT, MT_DATA); 1244 if (m == NULL) { 1245 printf("%s: unable to allocate Tx mbuf\n", 1246 sc->sc_dev.dv_xname); 1247 break; 1248 } 1249 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1250 if (m0->m_pkthdr.len > MHLEN) { 1251 MCLGET(m, M_DONTWAIT); 1252 if ((m->m_flags & M_EXT) == 0) { 1253 printf("%s: unable to allocate Tx " 1254 "cluster\n", sc->sc_dev.dv_xname); 1255 m_freem(m); 1256 break; 1257 } 1258 } 1259 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1260 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1261 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1262 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1263 if (error) { 1264 printf("%s: unable to load Tx buffer, " 1265 "error = %d\n", sc->sc_dev.dv_xname, error); 1266 break; 1267 } 1268 } 1269 #endif /* DP83820 */ 1270 1271 /* 1272 * Ensure we have enough descriptors free to describe 1273 * the packet. Note, we always reserve one descriptor 1274 * at the end of the ring as a termination point, to 1275 * prevent wrap-around. 1276 */ 1277 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1278 /* 1279 * Not enough free descriptors to transmit this 1280 * packet. We haven't committed anything yet, 1281 * so just unload the DMA map, put the packet 1282 * back on the queue, and punt. Notify the upper 1283 * layer that there are not more slots left. 1284 * 1285 * XXX We could allocate an mbuf and copy, but 1286 * XXX is it worth it? 1287 */ 1288 ifp->if_flags |= IFF_OACTIVE; 1289 bus_dmamap_unload(sc->sc_dmat, dmamap); 1290 #ifndef DP83820 1291 if (m != NULL) 1292 m_freem(m); 1293 #endif 1294 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1295 break; 1296 } 1297 1298 IFQ_DEQUEUE(&ifp->if_snd, m0); 1299 #ifndef DP83820 1300 if (m != NULL) { 1301 m_freem(m0); 1302 m0 = m; 1303 } 1304 #endif 1305 1306 /* 1307 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1308 */ 1309 1310 /* Sync the DMA map. */ 1311 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 1314 /* 1315 * Initialize the transmit descriptors. 1316 */ 1317 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1318 seg < dmamap->dm_nsegs; 1319 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1320 /* 1321 * If this is the first descriptor we're 1322 * enqueueing, don't set the OWN bit just 1323 * yet. That could cause a race condition. 1324 * We'll do it below. 1325 */ 1326 sc->sc_txdescs[nexttx].sipd_bufptr = 1327 htole32(dmamap->dm_segs[seg].ds_addr); 1328 sc->sc_txdescs[nexttx].sipd_cmdsts = 1329 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1330 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1331 #ifdef DP83820 1332 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1333 #endif /* DP83820 */ 1334 lasttx = nexttx; 1335 } 1336 1337 /* Clear the MORE bit on the last segment. */ 1338 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1339 1340 /* 1341 * If we're in the interrupt delay window, delay the 1342 * interrupt. 1343 */ 1344 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1345 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1346 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1347 htole32(CMDSTS_INTR); 1348 sc->sc_txwin = 0; 1349 } 1350 1351 #ifdef DP83820 1352 /* 1353 * If VLANs are enabled and the packet has a VLAN tag, set 1354 * up the descriptor to encapsulate the packet for us. 1355 * 1356 * This apparently has to be on the last descriptor of 1357 * the packet. 1358 */ 1359 1360 /* 1361 * Byte swapping is tricky. We need to provide the tag 1362 * in a network byte order. On a big-endian machine, 1363 * the byteorder is correct, but we need to swap it 1364 * anyway, because this will be undone by the outside 1365 * htole32(). That's why there must be an 1366 * unconditional swap instead of htons() inside. 1367 */ 1368 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1369 sc->sc_txdescs[lasttx].sipd_extsts |= 1370 htole32(EXTSTS_VPKT | 1371 (bswap16(VLAN_TAG_VALUE(mtag)) & 1372 EXTSTS_VTCI)); 1373 } 1374 1375 /* 1376 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1377 * checksumming, set up the descriptor to do this work 1378 * for us. 1379 * 1380 * This apparently has to be on the first descriptor of 1381 * the packet. 1382 * 1383 * Byte-swap constants so the compiler can optimize. 1384 */ 1385 extsts = 0; 1386 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1387 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1388 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1389 extsts |= htole32(EXTSTS_IPPKT); 1390 } 1391 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1392 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1393 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1394 extsts |= htole32(EXTSTS_TCPPKT); 1395 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1396 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1397 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1398 extsts |= htole32(EXTSTS_UDPPKT); 1399 } 1400 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1401 #endif /* DP83820 */ 1402 1403 /* Sync the descriptors we're using. */ 1404 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1405 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1406 1407 /* 1408 * The entire packet is set up. Give the first descrptor 1409 * to the chip now. 1410 */ 1411 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1412 htole32(CMDSTS_OWN); 1413 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1414 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1415 1416 /* 1417 * Store a pointer to the packet so we can free it later, 1418 * and remember what txdirty will be once the packet is 1419 * done. 1420 */ 1421 txs->txs_mbuf = m0; 1422 txs->txs_firstdesc = sc->sc_txnext; 1423 txs->txs_lastdesc = lasttx; 1424 1425 /* Advance the tx pointer. */ 1426 sc->sc_txfree -= dmamap->dm_nsegs; 1427 sc->sc_txnext = nexttx; 1428 1429 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1430 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1431 1432 #if NBPFILTER > 0 1433 /* 1434 * Pass the packet to any BPF listeners. 1435 */ 1436 if (ifp->if_bpf) 1437 bpf_mtap(ifp->if_bpf, m0); 1438 #endif /* NBPFILTER > 0 */ 1439 } 1440 1441 if (txs == NULL || sc->sc_txfree == 0) { 1442 /* No more slots left; notify upper layer. */ 1443 ifp->if_flags |= IFF_OACTIVE; 1444 } 1445 1446 if (sc->sc_txfree != ofree) { 1447 /* 1448 * Start the transmit process. Note, the manual says 1449 * that if there are no pending transmissions in the 1450 * chip's internal queue (indicated by TXE being clear), 1451 * then the driver software must set the TXDP to the 1452 * first descriptor to be transmitted. However, if we 1453 * do this, it causes serious performance degredation on 1454 * the DP83820 under load, not setting TXDP doesn't seem 1455 * to adversely affect the SiS 900 or DP83815. 1456 * 1457 * Well, I guess it wouldn't be the first time a manual 1458 * has lied -- and they could be speaking of the NULL- 1459 * terminated descriptor list case, rather than OWN- 1460 * terminated rings. 1461 */ 1462 #if 0 1463 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1464 CR_TXE) == 0) { 1465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1466 SIP_CDTXADDR(sc, firsttx)); 1467 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1468 } 1469 #else 1470 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1471 #endif 1472 1473 /* Set a watchdog timer in case the chip flakes out. */ 1474 #ifdef DP83820 1475 /* Gigabit autonegotiation takes 5 seconds. */ 1476 ifp->if_timer = 10; 1477 #else 1478 ifp->if_timer = 5; 1479 #endif 1480 } 1481 } 1482 1483 /* 1484 * sip_watchdog: [ifnet interface function] 1485 * 1486 * Watchdog timer handler. 1487 */ 1488 static void 1489 SIP_DECL(watchdog)(struct ifnet *ifp) 1490 { 1491 struct sip_softc *sc = ifp->if_softc; 1492 1493 /* 1494 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1495 * If we get a timeout, try and sweep up transmit descriptors. 1496 * If we manage to sweep them all up, ignore the lack of 1497 * interrupt. 1498 */ 1499 SIP_DECL(txintr)(sc); 1500 1501 if (sc->sc_txfree != SIP_NTXDESC) { 1502 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1503 ifp->if_oerrors++; 1504 1505 /* Reset the interface. */ 1506 (void) SIP_DECL(init)(ifp); 1507 } else if (ifp->if_flags & IFF_DEBUG) 1508 printf("%s: recovered from device timeout\n", 1509 sc->sc_dev.dv_xname); 1510 1511 /* Try to get more packets going. */ 1512 SIP_DECL(start)(ifp); 1513 } 1514 1515 /* 1516 * sip_ioctl: [ifnet interface function] 1517 * 1518 * Handle control requests from the operator. 1519 */ 1520 static int 1521 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1522 { 1523 struct sip_softc *sc = ifp->if_softc; 1524 struct ifreq *ifr = (struct ifreq *)data; 1525 int s, error; 1526 1527 s = splnet(); 1528 1529 switch (cmd) { 1530 case SIOCSIFMEDIA: 1531 /* Flow control requires full-duplex mode. */ 1532 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1533 (ifr->ifr_media & IFM_FDX) == 0) 1534 ifr->ifr_media &= ~IFM_ETH_FMASK; 1535 #ifdef DP83820 1536 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1537 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1538 /* We can do both TXPAUSE and RXPAUSE. */ 1539 ifr->ifr_media |= 1540 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1541 } 1542 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1543 } 1544 #else 1545 /* XXX */ 1546 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1547 ifr->ifr_media &= ~IFM_ETH_FMASK; 1548 1549 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1550 if (ifr->ifr_media & IFM_FLOW) { 1551 /* 1552 * Both TXPAUSE and RXPAUSE must be set. 1553 * (SiS900 and DP83815 don't have PAUSE_ASYM 1554 * feature.) 1555 * 1556 * XXX Can SiS900 and DP83815 send PAUSE? 1557 */ 1558 ifr->ifr_media |= 1559 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1560 } 1561 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1562 } 1563 #endif 1564 /* FALLTHROUGH */ 1565 case SIOCGIFMEDIA: 1566 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1567 break; 1568 case SIOCSIFFLAGS: 1569 /* If the interface is up and running, only modify the receive 1570 * filter when setting promiscuous or debug mode. Otherwise 1571 * fall through to ether_ioctl, which will reset the chip. 1572 */ 1573 1574 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1575 == (sc)->sc_ethercom.ec_capenable) \ 1576 && ((sc)->sc_prev.is_vlan == \ 1577 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1578 1579 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1580 1581 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1582 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1583 == (IFF_UP|IFF_RUNNING)) 1584 && ((ifp->if_flags & (~RESETIGN)) 1585 == (sc->sc_if_flags & (~RESETIGN))) 1586 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1587 /* Set up the receive filter. */ 1588 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1589 error = 0; 1590 break; 1591 #undef RESETIGN 1592 } 1593 /* FALLTHROUGH */ 1594 default: 1595 error = ether_ioctl(ifp, cmd, data); 1596 if (error == ENETRESET) { 1597 /* 1598 * Multicast list has changed; set the hardware filter 1599 * accordingly. 1600 */ 1601 if (ifp->if_flags & IFF_RUNNING) 1602 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1603 error = 0; 1604 } 1605 break; 1606 } 1607 1608 /* Try to get more packets going. */ 1609 SIP_DECL(start)(ifp); 1610 1611 sc->sc_if_flags = ifp->if_flags; 1612 splx(s); 1613 return (error); 1614 } 1615 1616 /* 1617 * sip_intr: 1618 * 1619 * Interrupt service routine. 1620 */ 1621 static int 1622 SIP_DECL(intr)(void *arg) 1623 { 1624 struct sip_softc *sc = arg; 1625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1626 u_int32_t isr; 1627 int handled = 0; 1628 1629 /* Disable interrupts. */ 1630 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1631 1632 for (;;) { 1633 /* Reading clears interrupt. */ 1634 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1635 if ((isr & sc->sc_imr) == 0) 1636 break; 1637 1638 #if NRND > 0 1639 if (RND_ENABLED(&sc->rnd_source)) 1640 rnd_add_uint32(&sc->rnd_source, isr); 1641 #endif 1642 1643 handled = 1; 1644 1645 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1646 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1647 1648 /* Grab any new packets. */ 1649 SIP_DECL(rxintr)(sc); 1650 1651 if (isr & ISR_RXORN) { 1652 printf("%s: receive FIFO overrun\n", 1653 sc->sc_dev.dv_xname); 1654 1655 /* XXX adjust rx_drain_thresh? */ 1656 } 1657 1658 if (isr & ISR_RXIDLE) { 1659 printf("%s: receive ring overrun\n", 1660 sc->sc_dev.dv_xname); 1661 1662 /* Get the receive process going again. */ 1663 bus_space_write_4(sc->sc_st, sc->sc_sh, 1664 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1665 bus_space_write_4(sc->sc_st, sc->sc_sh, 1666 SIP_CR, CR_RXE); 1667 } 1668 } 1669 1670 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1671 #ifdef SIP_EVENT_COUNTERS 1672 if (isr & ISR_TXDESC) 1673 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1674 else if (isr & ISR_TXIDLE) 1675 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1676 #endif 1677 1678 /* Sweep up transmit descriptors. */ 1679 SIP_DECL(txintr)(sc); 1680 1681 if (isr & ISR_TXURN) { 1682 u_int32_t thresh; 1683 1684 printf("%s: transmit FIFO underrun", 1685 sc->sc_dev.dv_xname); 1686 1687 thresh = sc->sc_tx_drain_thresh + 1; 1688 if (thresh <= TXCFG_DRTH && 1689 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1690 (sc->sc_tx_fill_thresh * 32))) { 1691 printf("; increasing Tx drain " 1692 "threshold to %u bytes\n", 1693 thresh * 32); 1694 sc->sc_tx_drain_thresh = thresh; 1695 (void) SIP_DECL(init)(ifp); 1696 } else { 1697 (void) SIP_DECL(init)(ifp); 1698 printf("\n"); 1699 } 1700 } 1701 } 1702 1703 #if !defined(DP83820) 1704 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1705 if (isr & ISR_PAUSE_ST) { 1706 sc->sc_paused = 1; 1707 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1708 ifp->if_flags |= IFF_OACTIVE; 1709 } 1710 if (isr & ISR_PAUSE_END) { 1711 sc->sc_paused = 0; 1712 ifp->if_flags &= ~IFF_OACTIVE; 1713 } 1714 } 1715 #endif /* ! DP83820 */ 1716 1717 if (isr & ISR_HIBERR) { 1718 int want_init = 0; 1719 1720 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1721 1722 #define PRINTERR(bit, str) \ 1723 do { \ 1724 if ((isr & (bit)) != 0) { \ 1725 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1726 printf("%s: %s\n", \ 1727 sc->sc_dev.dv_xname, str); \ 1728 want_init = 1; \ 1729 } \ 1730 } while (/*CONSTCOND*/0) 1731 1732 PRINTERR(ISR_DPERR, "parity error"); 1733 PRINTERR(ISR_SSERR, "system error"); 1734 PRINTERR(ISR_RMABT, "master abort"); 1735 PRINTERR(ISR_RTABT, "target abort"); 1736 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1737 /* 1738 * Ignore: 1739 * Tx reset complete 1740 * Rx reset complete 1741 */ 1742 if (want_init) 1743 (void) SIP_DECL(init)(ifp); 1744 #undef PRINTERR 1745 } 1746 } 1747 1748 /* Re-enable interrupts. */ 1749 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1750 1751 /* Try to get more packets going. */ 1752 SIP_DECL(start)(ifp); 1753 1754 return (handled); 1755 } 1756 1757 /* 1758 * sip_txintr: 1759 * 1760 * Helper; handle transmit interrupts. 1761 */ 1762 static void 1763 SIP_DECL(txintr)(struct sip_softc *sc) 1764 { 1765 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1766 struct sip_txsoft *txs; 1767 u_int32_t cmdsts; 1768 1769 #ifndef DP83820 1770 if (sc->sc_paused == 0) 1771 #endif 1772 ifp->if_flags &= ~IFF_OACTIVE; 1773 1774 /* 1775 * Go through our Tx list and free mbufs for those 1776 * frames which have been transmitted. 1777 */ 1778 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1779 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1781 1782 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1783 if (cmdsts & CMDSTS_OWN) 1784 break; 1785 1786 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1787 1788 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1789 1790 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1791 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1792 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1793 m_freem(txs->txs_mbuf); 1794 txs->txs_mbuf = NULL; 1795 1796 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1797 1798 /* 1799 * Check for errors and collisions. 1800 */ 1801 if (cmdsts & 1802 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1803 ifp->if_oerrors++; 1804 if (cmdsts & CMDSTS_Tx_EC) 1805 ifp->if_collisions += 16; 1806 if (ifp->if_flags & IFF_DEBUG) { 1807 if (cmdsts & CMDSTS_Tx_ED) 1808 printf("%s: excessive deferral\n", 1809 sc->sc_dev.dv_xname); 1810 if (cmdsts & CMDSTS_Tx_EC) 1811 printf("%s: excessive collisions\n", 1812 sc->sc_dev.dv_xname); 1813 } 1814 } else { 1815 /* Packet was transmitted successfully. */ 1816 ifp->if_opackets++; 1817 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1818 } 1819 } 1820 1821 /* 1822 * If there are no more pending transmissions, cancel the watchdog 1823 * timer. 1824 */ 1825 if (txs == NULL) { 1826 ifp->if_timer = 0; 1827 sc->sc_txwin = 0; 1828 } 1829 } 1830 1831 #if defined(DP83820) 1832 /* 1833 * sip_rxintr: 1834 * 1835 * Helper; handle receive interrupts. 1836 */ 1837 static void 1838 SIP_DECL(rxintr)(struct sip_softc *sc) 1839 { 1840 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1841 struct sip_rxsoft *rxs; 1842 struct mbuf *m; 1843 u_int32_t cmdsts, extsts; 1844 int i, len; 1845 1846 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1847 rxs = &sc->sc_rxsoft[i]; 1848 1849 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1850 1851 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1852 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1853 len = CMDSTS_SIZE(cmdsts); 1854 1855 /* 1856 * NOTE: OWN is set if owned by _consumer_. We're the 1857 * consumer of the receive ring, so if the bit is clear, 1858 * we have processed all of the packets. 1859 */ 1860 if ((cmdsts & CMDSTS_OWN) == 0) { 1861 /* 1862 * We have processed all of the receive buffers. 1863 */ 1864 break; 1865 } 1866 1867 if (__predict_false(sc->sc_rxdiscard)) { 1868 SIP_INIT_RXDESC(sc, i); 1869 if ((cmdsts & CMDSTS_MORE) == 0) { 1870 /* Reset our state. */ 1871 sc->sc_rxdiscard = 0; 1872 } 1873 continue; 1874 } 1875 1876 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1877 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1878 1879 m = rxs->rxs_mbuf; 1880 1881 /* 1882 * Add a new receive buffer to the ring. 1883 */ 1884 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1885 /* 1886 * Failed, throw away what we've done so 1887 * far, and discard the rest of the packet. 1888 */ 1889 ifp->if_ierrors++; 1890 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1891 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1892 SIP_INIT_RXDESC(sc, i); 1893 if (cmdsts & CMDSTS_MORE) 1894 sc->sc_rxdiscard = 1; 1895 if (sc->sc_rxhead != NULL) 1896 m_freem(sc->sc_rxhead); 1897 SIP_RXCHAIN_RESET(sc); 1898 continue; 1899 } 1900 1901 SIP_RXCHAIN_LINK(sc, m); 1902 1903 m->m_len = len; 1904 1905 /* 1906 * If this is not the end of the packet, keep 1907 * looking. 1908 */ 1909 if (cmdsts & CMDSTS_MORE) { 1910 sc->sc_rxlen += len; 1911 continue; 1912 } 1913 1914 /* 1915 * Okay, we have the entire packet now. The chip includes 1916 * the FCS, so we need to trim it. 1917 */ 1918 m->m_len -= ETHER_CRC_LEN; 1919 1920 *sc->sc_rxtailp = NULL; 1921 len = m->m_len + sc->sc_rxlen; 1922 m = sc->sc_rxhead; 1923 1924 SIP_RXCHAIN_RESET(sc); 1925 1926 /* 1927 * If an error occurred, update stats and drop the packet. 1928 */ 1929 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1930 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1931 ifp->if_ierrors++; 1932 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1933 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1934 /* Receive overrun handled elsewhere. */ 1935 printf("%s: receive descriptor error\n", 1936 sc->sc_dev.dv_xname); 1937 } 1938 #define PRINTERR(bit, str) \ 1939 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1940 (cmdsts & (bit)) != 0) \ 1941 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1942 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1943 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1944 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1945 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1946 #undef PRINTERR 1947 m_freem(m); 1948 continue; 1949 } 1950 1951 /* 1952 * If the packet is small enough to fit in a 1953 * single header mbuf, allocate one and copy 1954 * the data into it. This greatly reduces 1955 * memory consumption when we receive lots 1956 * of small packets. 1957 */ 1958 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1959 struct mbuf *nm; 1960 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1961 if (nm == NULL) { 1962 ifp->if_ierrors++; 1963 m_freem(m); 1964 continue; 1965 } 1966 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1967 nm->m_data += 2; 1968 nm->m_pkthdr.len = nm->m_len = len; 1969 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1970 m_freem(m); 1971 m = nm; 1972 } 1973 #ifndef __NO_STRICT_ALIGNMENT 1974 else { 1975 /* 1976 * The DP83820's receive buffers must be 4-byte 1977 * aligned. But this means that the data after 1978 * the Ethernet header is misaligned. To compensate, 1979 * we have artificially shortened the buffer size 1980 * in the descriptor, and we do an overlapping copy 1981 * of the data two bytes further in (in the first 1982 * buffer of the chain only). 1983 */ 1984 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1985 m->m_len); 1986 m->m_data += 2; 1987 } 1988 #endif /* ! __NO_STRICT_ALIGNMENT */ 1989 1990 /* 1991 * If VLANs are enabled, VLAN packets have been unwrapped 1992 * for us. Associate the tag with the packet. 1993 */ 1994 1995 /* 1996 * Again, byte swapping is tricky. Hardware provided 1997 * the tag in the network byte order, but extsts was 1998 * passed through le32toh() in the meantime. On a 1999 * big-endian machine, we need to swap it again. On a 2000 * little-endian machine, we need to convert from the 2001 * network to host byte order. This means that we must 2002 * swap it in any case, so unconditional swap instead 2003 * of htons() is used. 2004 */ 2005 if ((extsts & EXTSTS_VPKT) != 0) { 2006 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2007 continue); 2008 } 2009 2010 /* 2011 * Set the incoming checksum information for the 2012 * packet. 2013 */ 2014 if ((extsts & EXTSTS_IPPKT) != 0) { 2015 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2016 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2017 if (extsts & EXTSTS_Rx_IPERR) 2018 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2019 if (extsts & EXTSTS_TCPPKT) { 2020 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2021 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2022 if (extsts & EXTSTS_Rx_TCPERR) 2023 m->m_pkthdr.csum_flags |= 2024 M_CSUM_TCP_UDP_BAD; 2025 } else if (extsts & EXTSTS_UDPPKT) { 2026 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2027 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2028 if (extsts & EXTSTS_Rx_UDPERR) 2029 m->m_pkthdr.csum_flags |= 2030 M_CSUM_TCP_UDP_BAD; 2031 } 2032 } 2033 2034 ifp->if_ipackets++; 2035 m->m_pkthdr.rcvif = ifp; 2036 m->m_pkthdr.len = len; 2037 2038 #if NBPFILTER > 0 2039 /* 2040 * Pass this up to any BPF listeners, but only 2041 * pass if up the stack if it's for us. 2042 */ 2043 if (ifp->if_bpf) 2044 bpf_mtap(ifp->if_bpf, m); 2045 #endif /* NBPFILTER > 0 */ 2046 2047 /* Pass it on. */ 2048 (*ifp->if_input)(ifp, m); 2049 } 2050 2051 /* Update the receive pointer. */ 2052 sc->sc_rxptr = i; 2053 } 2054 #else /* ! DP83820 */ 2055 /* 2056 * sip_rxintr: 2057 * 2058 * Helper; handle receive interrupts. 2059 */ 2060 static void 2061 SIP_DECL(rxintr)(struct sip_softc *sc) 2062 { 2063 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2064 struct sip_rxsoft *rxs; 2065 struct mbuf *m; 2066 u_int32_t cmdsts; 2067 int i, len; 2068 2069 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2070 rxs = &sc->sc_rxsoft[i]; 2071 2072 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2073 2074 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2075 2076 /* 2077 * NOTE: OWN is set if owned by _consumer_. We're the 2078 * consumer of the receive ring, so if the bit is clear, 2079 * we have processed all of the packets. 2080 */ 2081 if ((cmdsts & CMDSTS_OWN) == 0) { 2082 /* 2083 * We have processed all of the receive buffers. 2084 */ 2085 break; 2086 } 2087 2088 /* 2089 * If any collisions were seen on the wire, count one. 2090 */ 2091 if (cmdsts & CMDSTS_Rx_COL) 2092 ifp->if_collisions++; 2093 2094 /* 2095 * If an error occurred, update stats, clear the status 2096 * word, and leave the packet buffer in place. It will 2097 * simply be reused the next time the ring comes around. 2098 */ 2099 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2100 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2101 ifp->if_ierrors++; 2102 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2103 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2104 /* Receive overrun handled elsewhere. */ 2105 printf("%s: receive descriptor error\n", 2106 sc->sc_dev.dv_xname); 2107 } 2108 #define PRINTERR(bit, str) \ 2109 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2110 (cmdsts & (bit)) != 0) \ 2111 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2112 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2113 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2114 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2115 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2116 #undef PRINTERR 2117 SIP_INIT_RXDESC(sc, i); 2118 continue; 2119 } 2120 2121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2122 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2123 2124 /* 2125 * No errors; receive the packet. Note, the SiS 900 2126 * includes the CRC with every packet. 2127 */ 2128 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2129 2130 #ifdef __NO_STRICT_ALIGNMENT 2131 /* 2132 * If the packet is small enough to fit in a 2133 * single header mbuf, allocate one and copy 2134 * the data into it. This greatly reduces 2135 * memory consumption when we receive lots 2136 * of small packets. 2137 * 2138 * Otherwise, we add a new buffer to the receive 2139 * chain. If this fails, we drop the packet and 2140 * recycle the old buffer. 2141 */ 2142 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2143 MGETHDR(m, M_DONTWAIT, MT_DATA); 2144 if (m == NULL) 2145 goto dropit; 2146 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2147 memcpy(mtod(m, caddr_t), 2148 mtod(rxs->rxs_mbuf, caddr_t), len); 2149 SIP_INIT_RXDESC(sc, i); 2150 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2151 rxs->rxs_dmamap->dm_mapsize, 2152 BUS_DMASYNC_PREREAD); 2153 } else { 2154 m = rxs->rxs_mbuf; 2155 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2156 dropit: 2157 ifp->if_ierrors++; 2158 SIP_INIT_RXDESC(sc, i); 2159 bus_dmamap_sync(sc->sc_dmat, 2160 rxs->rxs_dmamap, 0, 2161 rxs->rxs_dmamap->dm_mapsize, 2162 BUS_DMASYNC_PREREAD); 2163 continue; 2164 } 2165 } 2166 #else 2167 /* 2168 * The SiS 900's receive buffers must be 4-byte aligned. 2169 * But this means that the data after the Ethernet header 2170 * is misaligned. We must allocate a new buffer and 2171 * copy the data, shifted forward 2 bytes. 2172 */ 2173 MGETHDR(m, M_DONTWAIT, MT_DATA); 2174 if (m == NULL) { 2175 dropit: 2176 ifp->if_ierrors++; 2177 SIP_INIT_RXDESC(sc, i); 2178 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2179 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2180 continue; 2181 } 2182 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2183 if (len > (MHLEN - 2)) { 2184 MCLGET(m, M_DONTWAIT); 2185 if ((m->m_flags & M_EXT) == 0) { 2186 m_freem(m); 2187 goto dropit; 2188 } 2189 } 2190 m->m_data += 2; 2191 2192 /* 2193 * Note that we use clusters for incoming frames, so the 2194 * buffer is virtually contiguous. 2195 */ 2196 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2197 2198 /* Allow the receive descriptor to continue using its mbuf. */ 2199 SIP_INIT_RXDESC(sc, i); 2200 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2201 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2202 #endif /* __NO_STRICT_ALIGNMENT */ 2203 2204 ifp->if_ipackets++; 2205 m->m_pkthdr.rcvif = ifp; 2206 m->m_pkthdr.len = m->m_len = len; 2207 2208 #if NBPFILTER > 0 2209 /* 2210 * Pass this up to any BPF listeners, but only 2211 * pass if up the stack if it's for us. 2212 */ 2213 if (ifp->if_bpf) 2214 bpf_mtap(ifp->if_bpf, m); 2215 #endif /* NBPFILTER > 0 */ 2216 2217 /* Pass it on. */ 2218 (*ifp->if_input)(ifp, m); 2219 } 2220 2221 /* Update the receive pointer. */ 2222 sc->sc_rxptr = i; 2223 } 2224 #endif /* DP83820 */ 2225 2226 /* 2227 * sip_tick: 2228 * 2229 * One second timer, used to tick the MII. 2230 */ 2231 static void 2232 SIP_DECL(tick)(void *arg) 2233 { 2234 struct sip_softc *sc = arg; 2235 int s; 2236 2237 s = splnet(); 2238 #ifdef DP83820 2239 #ifdef SIP_EVENT_COUNTERS 2240 /* Read PAUSE related counts from MIB registers. */ 2241 sc->sc_ev_rxpause.ev_count += 2242 bus_space_read_4(sc->sc_st, sc->sc_sh, 2243 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2244 sc->sc_ev_txpause.ev_count += 2245 bus_space_read_4(sc->sc_st, sc->sc_sh, 2246 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2247 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2248 #endif /* SIP_EVENT_COUNTERS */ 2249 #endif /* DP83820 */ 2250 mii_tick(&sc->sc_mii); 2251 splx(s); 2252 2253 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2254 } 2255 2256 /* 2257 * sip_reset: 2258 * 2259 * Perform a soft reset on the SiS 900. 2260 */ 2261 static void 2262 SIP_DECL(reset)(struct sip_softc *sc) 2263 { 2264 bus_space_tag_t st = sc->sc_st; 2265 bus_space_handle_t sh = sc->sc_sh; 2266 int i; 2267 2268 bus_space_write_4(st, sh, SIP_IER, 0); 2269 bus_space_write_4(st, sh, SIP_IMR, 0); 2270 bus_space_write_4(st, sh, SIP_RFCR, 0); 2271 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2272 2273 for (i = 0; i < SIP_TIMEOUT; i++) { 2274 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2275 break; 2276 delay(2); 2277 } 2278 2279 if (i == SIP_TIMEOUT) 2280 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2281 2282 delay(1000); 2283 2284 #ifdef DP83820 2285 /* 2286 * Set the general purpose I/O bits. Do it here in case we 2287 * need to have GPIO set up to talk to the media interface. 2288 */ 2289 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2290 delay(1000); 2291 #endif /* DP83820 */ 2292 } 2293 2294 /* 2295 * sip_init: [ ifnet interface function ] 2296 * 2297 * Initialize the interface. Must be called at splnet(). 2298 */ 2299 static int 2300 SIP_DECL(init)(struct ifnet *ifp) 2301 { 2302 struct sip_softc *sc = ifp->if_softc; 2303 bus_space_tag_t st = sc->sc_st; 2304 bus_space_handle_t sh = sc->sc_sh; 2305 struct sip_txsoft *txs; 2306 struct sip_rxsoft *rxs; 2307 struct sip_desc *sipd; 2308 #if defined(DP83820) 2309 u_int32_t reg; 2310 #endif 2311 int i, error = 0; 2312 2313 /* 2314 * Cancel any pending I/O. 2315 */ 2316 SIP_DECL(stop)(ifp, 0); 2317 2318 /* 2319 * Reset the chip to a known state. 2320 */ 2321 SIP_DECL(reset)(sc); 2322 2323 #if !defined(DP83820) 2324 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2325 /* 2326 * DP83815 manual, page 78: 2327 * 4.4 Recommended Registers Configuration 2328 * For optimum performance of the DP83815, version noted 2329 * as DP83815CVNG (SRR = 203h), the listed register 2330 * modifications must be followed in sequence... 2331 * 2332 * It's not clear if this should be 302h or 203h because that 2333 * chip name is listed as SRR 302h in the description of the 2334 * SRR register. However, my revision 302h DP83815 on the 2335 * Netgear FA311 purchased in 02/2001 needs these settings 2336 * to avoid tons of errors in AcceptPerfectMatch (non- 2337 * IFF_PROMISC) mode. I do not know if other revisions need 2338 * this set or not. [briggs -- 09 March 2001] 2339 * 2340 * Note that only the low-order 12 bits of 0xe4 are documented 2341 * and that this sets reserved bits in that register. 2342 */ 2343 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2344 2345 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2346 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2347 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2348 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2349 2350 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2351 } 2352 #endif /* ! DP83820 */ 2353 2354 /* 2355 * Initialize the transmit descriptor ring. 2356 */ 2357 for (i = 0; i < SIP_NTXDESC; i++) { 2358 sipd = &sc->sc_txdescs[i]; 2359 memset(sipd, 0, sizeof(struct sip_desc)); 2360 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2361 } 2362 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2363 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2364 sc->sc_txfree = SIP_NTXDESC; 2365 sc->sc_txnext = 0; 2366 sc->sc_txwin = 0; 2367 2368 /* 2369 * Initialize the transmit job descriptors. 2370 */ 2371 SIMPLEQ_INIT(&sc->sc_txfreeq); 2372 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2373 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2374 txs = &sc->sc_txsoft[i]; 2375 txs->txs_mbuf = NULL; 2376 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2377 } 2378 2379 /* 2380 * Initialize the receive descriptor and receive job 2381 * descriptor rings. 2382 */ 2383 for (i = 0; i < SIP_NRXDESC; i++) { 2384 rxs = &sc->sc_rxsoft[i]; 2385 if (rxs->rxs_mbuf == NULL) { 2386 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2387 printf("%s: unable to allocate or map rx " 2388 "buffer %d, error = %d\n", 2389 sc->sc_dev.dv_xname, i, error); 2390 /* 2391 * XXX Should attempt to run with fewer receive 2392 * XXX buffers instead of just failing. 2393 */ 2394 SIP_DECL(rxdrain)(sc); 2395 goto out; 2396 } 2397 } else 2398 SIP_INIT_RXDESC(sc, i); 2399 } 2400 sc->sc_rxptr = 0; 2401 #ifdef DP83820 2402 sc->sc_rxdiscard = 0; 2403 SIP_RXCHAIN_RESET(sc); 2404 #endif /* DP83820 */ 2405 2406 /* 2407 * Set the configuration register; it's already initialized 2408 * in sip_attach(). 2409 */ 2410 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2411 2412 /* 2413 * Initialize the prototype TXCFG register. 2414 */ 2415 #if defined(DP83820) 2416 sc->sc_txcfg = TXCFG_MXDMA_512; 2417 sc->sc_rxcfg = RXCFG_MXDMA_512; 2418 #else 2419 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2420 SIP_SIS900_REV(sc, SIS_REV_960) || 2421 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2422 (sc->sc_cfg & CFG_EDBMASTEN)) { 2423 sc->sc_txcfg = TXCFG_MXDMA_64; 2424 sc->sc_rxcfg = RXCFG_MXDMA_64; 2425 } else { 2426 sc->sc_txcfg = TXCFG_MXDMA_512; 2427 sc->sc_rxcfg = RXCFG_MXDMA_512; 2428 } 2429 #endif /* DP83820 */ 2430 2431 sc->sc_txcfg |= TXCFG_ATP | 2432 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2433 sc->sc_tx_drain_thresh; 2434 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2435 2436 /* 2437 * Initialize the receive drain threshold if we have never 2438 * done so. 2439 */ 2440 if (sc->sc_rx_drain_thresh == 0) { 2441 /* 2442 * XXX This value should be tuned. This is set to the 2443 * maximum of 248 bytes, and we may be able to improve 2444 * performance by decreasing it (although we should never 2445 * set this value lower than 2; 14 bytes are required to 2446 * filter the packet). 2447 */ 2448 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2449 } 2450 2451 /* 2452 * Initialize the prototype RXCFG register. 2453 */ 2454 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2455 #ifdef DP83820 2456 /* 2457 * Accept long packets (including FCS) so we can handle 2458 * 802.1q-tagged frames and jumbo frames properly. 2459 */ 2460 if (ifp->if_mtu > ETHERMTU || 2461 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2462 sc->sc_rxcfg |= RXCFG_ALP; 2463 2464 /* 2465 * Checksum offloading is disabled if the user selects an MTU 2466 * larger than 8109. (FreeBSD says 8152, but there is emperical 2467 * evidence that >8109 does not work on some boards, such as the 2468 * Planex GN-1000TE). 2469 */ 2470 if (ifp->if_mtu > 8109 && 2471 (ifp->if_capenable & 2472 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2473 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2474 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2475 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2476 "disabled.\n", sc->sc_dev.dv_xname); 2477 ifp->if_capenable &= 2478 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2479 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2480 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2481 ifp->if_csum_flags_tx = 0; 2482 ifp->if_csum_flags_rx = 0; 2483 } 2484 #else 2485 /* 2486 * Accept packets >1518 bytes (including FCS) so we can handle 2487 * 802.1q-tagged frames properly. 2488 */ 2489 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2490 sc->sc_rxcfg |= RXCFG_ALP; 2491 #endif 2492 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2493 2494 #ifdef DP83820 2495 /* 2496 * Initialize the VLAN/IP receive control register. 2497 * We enable checksum computation on all incoming 2498 * packets, and do not reject packets w/ bad checksums. 2499 */ 2500 reg = 0; 2501 if (ifp->if_capenable & 2502 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2503 reg |= VRCR_IPEN; 2504 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2505 reg |= VRCR_VTDEN|VRCR_VTREN; 2506 bus_space_write_4(st, sh, SIP_VRCR, reg); 2507 2508 /* 2509 * Initialize the VLAN/IP transmit control register. 2510 * We enable outgoing checksum computation on a 2511 * per-packet basis. 2512 */ 2513 reg = 0; 2514 if (ifp->if_capenable & 2515 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2516 reg |= VTCR_PPCHK; 2517 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2518 reg |= VTCR_VPPTI; 2519 bus_space_write_4(st, sh, SIP_VTCR, reg); 2520 2521 /* 2522 * If we're using VLANs, initialize the VLAN data register. 2523 * To understand why we bswap the VLAN Ethertype, see section 2524 * 4.2.36 of the DP83820 manual. 2525 */ 2526 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2527 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2528 #endif /* DP83820 */ 2529 2530 /* 2531 * Give the transmit and receive rings to the chip. 2532 */ 2533 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2534 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2535 2536 /* 2537 * Initialize the interrupt mask. 2538 */ 2539 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2540 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2541 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2542 2543 /* Set up the receive filter. */ 2544 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2545 2546 #ifdef DP83820 2547 /* 2548 * Tune sc_rx_flow_thresh. 2549 * XXX "More than 8KB" is too short for jumbo frames. 2550 * XXX TODO: Threshold value should be user-settable. 2551 */ 2552 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2553 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2554 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2555 #endif 2556 2557 /* 2558 * Set the current media. Do this after initializing the prototype 2559 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2560 * control. 2561 */ 2562 mii_mediachg(&sc->sc_mii); 2563 2564 #ifdef DP83820 2565 /* 2566 * Set the interrupt hold-off timer to 100us. 2567 */ 2568 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2569 #endif 2570 2571 /* 2572 * Enable interrupts. 2573 */ 2574 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2575 2576 /* 2577 * Start the transmit and receive processes. 2578 */ 2579 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2580 2581 /* 2582 * Start the one second MII clock. 2583 */ 2584 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2585 2586 /* 2587 * ...all done! 2588 */ 2589 ifp->if_flags |= IFF_RUNNING; 2590 ifp->if_flags &= ~IFF_OACTIVE; 2591 sc->sc_if_flags = ifp->if_flags; 2592 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2593 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2594 sc->sc_prev.if_capenable = ifp->if_capenable; 2595 2596 out: 2597 if (error) 2598 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2599 return (error); 2600 } 2601 2602 /* 2603 * sip_drain: 2604 * 2605 * Drain the receive queue. 2606 */ 2607 static void 2608 SIP_DECL(rxdrain)(struct sip_softc *sc) 2609 { 2610 struct sip_rxsoft *rxs; 2611 int i; 2612 2613 for (i = 0; i < SIP_NRXDESC; i++) { 2614 rxs = &sc->sc_rxsoft[i]; 2615 if (rxs->rxs_mbuf != NULL) { 2616 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2617 m_freem(rxs->rxs_mbuf); 2618 rxs->rxs_mbuf = NULL; 2619 } 2620 } 2621 } 2622 2623 /* 2624 * sip_stop: [ ifnet interface function ] 2625 * 2626 * Stop transmission on the interface. 2627 */ 2628 static void 2629 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2630 { 2631 struct sip_softc *sc = ifp->if_softc; 2632 bus_space_tag_t st = sc->sc_st; 2633 bus_space_handle_t sh = sc->sc_sh; 2634 struct sip_txsoft *txs; 2635 u_int32_t cmdsts = 0; /* DEBUG */ 2636 2637 /* 2638 * Stop the one second clock. 2639 */ 2640 callout_stop(&sc->sc_tick_ch); 2641 2642 /* Down the MII. */ 2643 mii_down(&sc->sc_mii); 2644 2645 /* 2646 * Disable interrupts. 2647 */ 2648 bus_space_write_4(st, sh, SIP_IER, 0); 2649 2650 /* 2651 * Stop receiver and transmitter. 2652 */ 2653 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2654 2655 /* 2656 * Release any queued transmit buffers. 2657 */ 2658 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2659 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2660 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2661 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2662 CMDSTS_INTR) == 0) 2663 printf("%s: sip_stop: last descriptor does not " 2664 "have INTR bit set\n", sc->sc_dev.dv_xname); 2665 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2666 #ifdef DIAGNOSTIC 2667 if (txs->txs_mbuf == NULL) { 2668 printf("%s: dirty txsoft with no mbuf chain\n", 2669 sc->sc_dev.dv_xname); 2670 panic("sip_stop"); 2671 } 2672 #endif 2673 cmdsts |= /* DEBUG */ 2674 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2675 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2676 m_freem(txs->txs_mbuf); 2677 txs->txs_mbuf = NULL; 2678 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2679 } 2680 2681 if (disable) 2682 SIP_DECL(rxdrain)(sc); 2683 2684 /* 2685 * Mark the interface down and cancel the watchdog timer. 2686 */ 2687 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2688 ifp->if_timer = 0; 2689 2690 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2691 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2692 printf("%s: sip_stop: no INTR bits set in dirty tx " 2693 "descriptors\n", sc->sc_dev.dv_xname); 2694 } 2695 2696 /* 2697 * sip_read_eeprom: 2698 * 2699 * Read data from the serial EEPROM. 2700 */ 2701 static void 2702 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2703 u_int16_t *data) 2704 { 2705 bus_space_tag_t st = sc->sc_st; 2706 bus_space_handle_t sh = sc->sc_sh; 2707 u_int16_t reg; 2708 int i, x; 2709 2710 for (i = 0; i < wordcnt; i++) { 2711 /* Send CHIP SELECT. */ 2712 reg = EROMAR_EECS; 2713 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2714 2715 /* Shift in the READ opcode. */ 2716 for (x = 3; x > 0; x--) { 2717 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2718 reg |= EROMAR_EEDI; 2719 else 2720 reg &= ~EROMAR_EEDI; 2721 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2722 bus_space_write_4(st, sh, SIP_EROMAR, 2723 reg | EROMAR_EESK); 2724 delay(4); 2725 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2726 delay(4); 2727 } 2728 2729 /* Shift in address. */ 2730 for (x = 6; x > 0; x--) { 2731 if ((word + i) & (1 << (x - 1))) 2732 reg |= EROMAR_EEDI; 2733 else 2734 reg &= ~EROMAR_EEDI; 2735 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2736 bus_space_write_4(st, sh, SIP_EROMAR, 2737 reg | EROMAR_EESK); 2738 delay(4); 2739 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2740 delay(4); 2741 } 2742 2743 /* Shift out data. */ 2744 reg = EROMAR_EECS; 2745 data[i] = 0; 2746 for (x = 16; x > 0; x--) { 2747 bus_space_write_4(st, sh, SIP_EROMAR, 2748 reg | EROMAR_EESK); 2749 delay(4); 2750 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2751 data[i] |= (1 << (x - 1)); 2752 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2753 delay(4); 2754 } 2755 2756 /* Clear CHIP SELECT. */ 2757 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2758 delay(4); 2759 } 2760 } 2761 2762 /* 2763 * sip_add_rxbuf: 2764 * 2765 * Add a receive buffer to the indicated descriptor. 2766 */ 2767 static int 2768 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2769 { 2770 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2771 struct mbuf *m; 2772 int error; 2773 2774 MGETHDR(m, M_DONTWAIT, MT_DATA); 2775 if (m == NULL) 2776 return (ENOBUFS); 2777 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2778 2779 MCLGET(m, M_DONTWAIT); 2780 if ((m->m_flags & M_EXT) == 0) { 2781 m_freem(m); 2782 return (ENOBUFS); 2783 } 2784 2785 #if defined(DP83820) 2786 m->m_len = SIP_RXBUF_LEN; 2787 #endif /* DP83820 */ 2788 2789 if (rxs->rxs_mbuf != NULL) 2790 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2791 2792 rxs->rxs_mbuf = m; 2793 2794 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2795 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2796 BUS_DMA_READ|BUS_DMA_NOWAIT); 2797 if (error) { 2798 printf("%s: can't load rx DMA map %d, error = %d\n", 2799 sc->sc_dev.dv_xname, idx, error); 2800 panic("sip_add_rxbuf"); /* XXX */ 2801 } 2802 2803 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2804 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2805 2806 SIP_INIT_RXDESC(sc, idx); 2807 2808 return (0); 2809 } 2810 2811 #if !defined(DP83820) 2812 /* 2813 * sip_sis900_set_filter: 2814 * 2815 * Set up the receive filter. 2816 */ 2817 static void 2818 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2819 { 2820 bus_space_tag_t st = sc->sc_st; 2821 bus_space_handle_t sh = sc->sc_sh; 2822 struct ethercom *ec = &sc->sc_ethercom; 2823 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2824 struct ether_multi *enm; 2825 u_int8_t *cp; 2826 struct ether_multistep step; 2827 u_int32_t crc, mchash[16]; 2828 2829 /* 2830 * Initialize the prototype RFCR. 2831 */ 2832 sc->sc_rfcr = RFCR_RFEN; 2833 if (ifp->if_flags & IFF_BROADCAST) 2834 sc->sc_rfcr |= RFCR_AAB; 2835 if (ifp->if_flags & IFF_PROMISC) { 2836 sc->sc_rfcr |= RFCR_AAP; 2837 goto allmulti; 2838 } 2839 2840 /* 2841 * Set up the multicast address filter by passing all multicast 2842 * addresses through a CRC generator, and then using the high-order 2843 * 6 bits as an index into the 128 bit multicast hash table (only 2844 * the lower 16 bits of each 32 bit multicast hash register are 2845 * valid). The high order bits select the register, while the 2846 * rest of the bits select the bit within the register. 2847 */ 2848 2849 memset(mchash, 0, sizeof(mchash)); 2850 2851 /* 2852 * SiS900 (at least SiS963) requires us to register the address of 2853 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2854 */ 2855 crc = 0x0ed423f9; 2856 2857 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2858 SIP_SIS900_REV(sc, SIS_REV_960) || 2859 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2860 /* Just want the 8 most significant bits. */ 2861 crc >>= 24; 2862 } else { 2863 /* Just want the 7 most significant bits. */ 2864 crc >>= 25; 2865 } 2866 2867 /* Set the corresponding bit in the hash table. */ 2868 mchash[crc >> 4] |= 1 << (crc & 0xf); 2869 2870 ETHER_FIRST_MULTI(step, ec, enm); 2871 while (enm != NULL) { 2872 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2873 /* 2874 * We must listen to a range of multicast addresses. 2875 * For now, just accept all multicasts, rather than 2876 * trying to set only those filter bits needed to match 2877 * the range. (At this time, the only use of address 2878 * ranges is for IP multicast routing, for which the 2879 * range is big enough to require all bits set.) 2880 */ 2881 goto allmulti; 2882 } 2883 2884 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2885 2886 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2887 SIP_SIS900_REV(sc, SIS_REV_960) || 2888 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2889 /* Just want the 8 most significant bits. */ 2890 crc >>= 24; 2891 } else { 2892 /* Just want the 7 most significant bits. */ 2893 crc >>= 25; 2894 } 2895 2896 /* Set the corresponding bit in the hash table. */ 2897 mchash[crc >> 4] |= 1 << (crc & 0xf); 2898 2899 ETHER_NEXT_MULTI(step, enm); 2900 } 2901 2902 ifp->if_flags &= ~IFF_ALLMULTI; 2903 goto setit; 2904 2905 allmulti: 2906 ifp->if_flags |= IFF_ALLMULTI; 2907 sc->sc_rfcr |= RFCR_AAM; 2908 2909 setit: 2910 #define FILTER_EMIT(addr, data) \ 2911 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2912 delay(1); \ 2913 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2914 delay(1) 2915 2916 /* 2917 * Disable receive filter, and program the node address. 2918 */ 2919 cp = LLADDR(ifp->if_sadl); 2920 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2921 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2922 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2923 2924 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2925 /* 2926 * Program the multicast hash table. 2927 */ 2928 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2929 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2930 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2931 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2932 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2933 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2934 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2935 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2936 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2937 SIP_SIS900_REV(sc, SIS_REV_960) || 2938 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2939 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2940 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2941 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2942 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2943 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2944 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2945 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2946 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2947 } 2948 } 2949 #undef FILTER_EMIT 2950 2951 /* 2952 * Re-enable the receiver filter. 2953 */ 2954 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2955 } 2956 #endif /* ! DP83820 */ 2957 2958 /* 2959 * sip_dp83815_set_filter: 2960 * 2961 * Set up the receive filter. 2962 */ 2963 static void 2964 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2965 { 2966 bus_space_tag_t st = sc->sc_st; 2967 bus_space_handle_t sh = sc->sc_sh; 2968 struct ethercom *ec = &sc->sc_ethercom; 2969 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2970 struct ether_multi *enm; 2971 u_int8_t *cp; 2972 struct ether_multistep step; 2973 u_int32_t crc, hash, slot, bit; 2974 #ifdef DP83820 2975 #define MCHASH_NWORDS 128 2976 #else 2977 #define MCHASH_NWORDS 32 2978 #endif /* DP83820 */ 2979 u_int16_t mchash[MCHASH_NWORDS]; 2980 int i; 2981 2982 /* 2983 * Initialize the prototype RFCR. 2984 * Enable the receive filter, and accept on 2985 * Perfect (destination address) Match 2986 * If IFF_BROADCAST, also accept all broadcast packets. 2987 * If IFF_PROMISC, accept all unicast packets (and later, set 2988 * IFF_ALLMULTI and accept all multicast, too). 2989 */ 2990 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2991 if (ifp->if_flags & IFF_BROADCAST) 2992 sc->sc_rfcr |= RFCR_AAB; 2993 if (ifp->if_flags & IFF_PROMISC) { 2994 sc->sc_rfcr |= RFCR_AAP; 2995 goto allmulti; 2996 } 2997 2998 #ifdef DP83820 2999 /* 3000 * Set up the DP83820 multicast address filter by passing all multicast 3001 * addresses through a CRC generator, and then using the high-order 3002 * 11 bits as an index into the 2048 bit multicast hash table. The 3003 * high-order 7 bits select the slot, while the low-order 4 bits 3004 * select the bit within the slot. Note that only the low 16-bits 3005 * of each filter word are used, and there are 128 filter words. 3006 */ 3007 #else 3008 /* 3009 * Set up the DP83815 multicast address filter by passing all multicast 3010 * addresses through a CRC generator, and then using the high-order 3011 * 9 bits as an index into the 512 bit multicast hash table. The 3012 * high-order 5 bits select the slot, while the low-order 4 bits 3013 * select the bit within the slot. Note that only the low 16-bits 3014 * of each filter word are used, and there are 32 filter words. 3015 */ 3016 #endif /* DP83820 */ 3017 3018 memset(mchash, 0, sizeof(mchash)); 3019 3020 ifp->if_flags &= ~IFF_ALLMULTI; 3021 ETHER_FIRST_MULTI(step, ec, enm); 3022 if (enm == NULL) 3023 goto setit; 3024 while (enm != NULL) { 3025 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3026 /* 3027 * We must listen to a range of multicast addresses. 3028 * For now, just accept all multicasts, rather than 3029 * trying to set only those filter bits needed to match 3030 * the range. (At this time, the only use of address 3031 * ranges is for IP multicast routing, for which the 3032 * range is big enough to require all bits set.) 3033 */ 3034 goto allmulti; 3035 } 3036 3037 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3038 3039 #ifdef DP83820 3040 /* Just want the 11 most significant bits. */ 3041 hash = crc >> 21; 3042 #else 3043 /* Just want the 9 most significant bits. */ 3044 hash = crc >> 23; 3045 #endif /* DP83820 */ 3046 3047 slot = hash >> 4; 3048 bit = hash & 0xf; 3049 3050 /* Set the corresponding bit in the hash table. */ 3051 mchash[slot] |= 1 << bit; 3052 3053 ETHER_NEXT_MULTI(step, enm); 3054 } 3055 sc->sc_rfcr |= RFCR_MHEN; 3056 goto setit; 3057 3058 allmulti: 3059 ifp->if_flags |= IFF_ALLMULTI; 3060 sc->sc_rfcr |= RFCR_AAM; 3061 3062 setit: 3063 #define FILTER_EMIT(addr, data) \ 3064 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3065 delay(1); \ 3066 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3067 delay(1) 3068 3069 /* 3070 * Disable receive filter, and program the node address. 3071 */ 3072 cp = LLADDR(ifp->if_sadl); 3073 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3074 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3075 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3076 3077 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3078 /* 3079 * Program the multicast hash table. 3080 */ 3081 for (i = 0; i < MCHASH_NWORDS; i++) { 3082 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3083 mchash[i]); 3084 } 3085 } 3086 #undef FILTER_EMIT 3087 #undef MCHASH_NWORDS 3088 3089 /* 3090 * Re-enable the receiver filter. 3091 */ 3092 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3093 } 3094 3095 #if defined(DP83820) 3096 /* 3097 * sip_dp83820_mii_readreg: [mii interface function] 3098 * 3099 * Read a PHY register on the MII of the DP83820. 3100 */ 3101 static int 3102 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3103 { 3104 struct sip_softc *sc = (void *) self; 3105 3106 if (sc->sc_cfg & CFG_TBI_EN) { 3107 bus_addr_t tbireg; 3108 int rv; 3109 3110 if (phy != 0) 3111 return (0); 3112 3113 switch (reg) { 3114 case MII_BMCR: tbireg = SIP_TBICR; break; 3115 case MII_BMSR: tbireg = SIP_TBISR; break; 3116 case MII_ANAR: tbireg = SIP_TANAR; break; 3117 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3118 case MII_ANER: tbireg = SIP_TANER; break; 3119 case MII_EXTSR: 3120 /* 3121 * Don't even bother reading the TESR register. 3122 * The manual documents that the device has 3123 * 1000baseX full/half capability, but the 3124 * register itself seems read back 0 on some 3125 * boards. Just hard-code the result. 3126 */ 3127 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3128 3129 default: 3130 return (0); 3131 } 3132 3133 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3134 if (tbireg == SIP_TBISR) { 3135 /* LINK and ACOMP are switched! */ 3136 int val = rv; 3137 3138 rv = 0; 3139 if (val & TBISR_MR_LINK_STATUS) 3140 rv |= BMSR_LINK; 3141 if (val & TBISR_MR_AN_COMPLETE) 3142 rv |= BMSR_ACOMP; 3143 3144 /* 3145 * The manual claims this register reads back 0 3146 * on hard and soft reset. But we want to let 3147 * the gentbi driver know that we support auto- 3148 * negotiation, so hard-code this bit in the 3149 * result. 3150 */ 3151 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3152 } 3153 3154 return (rv); 3155 } 3156 3157 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3158 phy, reg)); 3159 } 3160 3161 /* 3162 * sip_dp83820_mii_writereg: [mii interface function] 3163 * 3164 * Write a PHY register on the MII of the DP83820. 3165 */ 3166 static void 3167 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3168 { 3169 struct sip_softc *sc = (void *) self; 3170 3171 if (sc->sc_cfg & CFG_TBI_EN) { 3172 bus_addr_t tbireg; 3173 3174 if (phy != 0) 3175 return; 3176 3177 switch (reg) { 3178 case MII_BMCR: tbireg = SIP_TBICR; break; 3179 case MII_ANAR: tbireg = SIP_TANAR; break; 3180 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3181 default: 3182 return; 3183 } 3184 3185 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3186 return; 3187 } 3188 3189 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3190 phy, reg, val); 3191 } 3192 3193 /* 3194 * sip_dp83820_mii_statchg: [mii interface function] 3195 * 3196 * Callback from MII layer when media changes. 3197 */ 3198 static void 3199 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3200 { 3201 struct sip_softc *sc = (struct sip_softc *) self; 3202 struct mii_data *mii = &sc->sc_mii; 3203 u_int32_t cfg, pcr; 3204 3205 /* 3206 * Get flow control negotiation result. 3207 */ 3208 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3209 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3210 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3211 mii->mii_media_active &= ~IFM_ETH_FMASK; 3212 } 3213 3214 /* 3215 * Update TXCFG for full-duplex operation. 3216 */ 3217 if ((mii->mii_media_active & IFM_FDX) != 0) 3218 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3219 else 3220 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3221 3222 /* 3223 * Update RXCFG for full-duplex or loopback. 3224 */ 3225 if ((mii->mii_media_active & IFM_FDX) != 0 || 3226 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3227 sc->sc_rxcfg |= RXCFG_ATX; 3228 else 3229 sc->sc_rxcfg &= ~RXCFG_ATX; 3230 3231 /* 3232 * Update CFG for MII/GMII. 3233 */ 3234 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3235 cfg = sc->sc_cfg | CFG_MODE_1000; 3236 else 3237 cfg = sc->sc_cfg; 3238 3239 /* 3240 * 802.3x flow control. 3241 */ 3242 pcr = 0; 3243 if (sc->sc_flowflags & IFM_FLOW) { 3244 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3245 pcr |= sc->sc_rx_flow_thresh; 3246 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3247 pcr |= PCR_PSEN | PCR_PS_MCAST; 3248 } 3249 3250 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3251 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3252 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3253 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3254 } 3255 #endif /* ! DP83820 */ 3256 3257 /* 3258 * sip_mii_bitbang_read: [mii bit-bang interface function] 3259 * 3260 * Read the MII serial port for the MII bit-bang module. 3261 */ 3262 static u_int32_t 3263 SIP_DECL(mii_bitbang_read)(struct device *self) 3264 { 3265 struct sip_softc *sc = (void *) self; 3266 3267 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3268 } 3269 3270 /* 3271 * sip_mii_bitbang_write: [mii big-bang interface function] 3272 * 3273 * Write the MII serial port for the MII bit-bang module. 3274 */ 3275 static void 3276 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3277 { 3278 struct sip_softc *sc = (void *) self; 3279 3280 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3281 } 3282 3283 #ifndef DP83820 3284 /* 3285 * sip_sis900_mii_readreg: [mii interface function] 3286 * 3287 * Read a PHY register on the MII. 3288 */ 3289 static int 3290 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3291 { 3292 struct sip_softc *sc = (struct sip_softc *) self; 3293 u_int32_t enphy; 3294 3295 /* 3296 * The PHY of recent SiS chipsets is accessed through bitbang 3297 * operations. 3298 */ 3299 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3300 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3301 phy, reg)); 3302 3303 #ifndef SIS900_MII_RESTRICT 3304 /* 3305 * The SiS 900 has only an internal PHY on the MII. Only allow 3306 * MII address 0. 3307 */ 3308 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3309 return (0); 3310 #endif 3311 3312 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3313 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3314 ENPHY_RWCMD | ENPHY_ACCESS); 3315 do { 3316 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3317 } while (enphy & ENPHY_ACCESS); 3318 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3319 } 3320 3321 /* 3322 * sip_sis900_mii_writereg: [mii interface function] 3323 * 3324 * Write a PHY register on the MII. 3325 */ 3326 static void 3327 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3328 { 3329 struct sip_softc *sc = (struct sip_softc *) self; 3330 u_int32_t enphy; 3331 3332 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3333 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3334 phy, reg, val); 3335 return; 3336 } 3337 3338 #ifndef SIS900_MII_RESTRICT 3339 /* 3340 * The SiS 900 has only an internal PHY on the MII. Only allow 3341 * MII address 0. 3342 */ 3343 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3344 return; 3345 #endif 3346 3347 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3348 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3349 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3350 do { 3351 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3352 } while (enphy & ENPHY_ACCESS); 3353 } 3354 3355 /* 3356 * sip_sis900_mii_statchg: [mii interface function] 3357 * 3358 * Callback from MII layer when media changes. 3359 */ 3360 static void 3361 SIP_DECL(sis900_mii_statchg)(struct device *self) 3362 { 3363 struct sip_softc *sc = (struct sip_softc *) self; 3364 struct mii_data *mii = &sc->sc_mii; 3365 u_int32_t flowctl; 3366 3367 /* 3368 * Get flow control negotiation result. 3369 */ 3370 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3371 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3372 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3373 mii->mii_media_active &= ~IFM_ETH_FMASK; 3374 } 3375 3376 /* 3377 * Update TXCFG for full-duplex operation. 3378 */ 3379 if ((mii->mii_media_active & IFM_FDX) != 0) 3380 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3381 else 3382 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3383 3384 /* 3385 * Update RXCFG for full-duplex or loopback. 3386 */ 3387 if ((mii->mii_media_active & IFM_FDX) != 0 || 3388 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3389 sc->sc_rxcfg |= RXCFG_ATX; 3390 else 3391 sc->sc_rxcfg &= ~RXCFG_ATX; 3392 3393 /* 3394 * Update IMR for use of 802.3x flow control. 3395 */ 3396 if (sc->sc_flowflags & IFM_FLOW) { 3397 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3398 flowctl = FLOWCTL_FLOWEN; 3399 } else { 3400 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3401 flowctl = 0; 3402 } 3403 3404 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3405 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3406 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3407 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3408 } 3409 3410 /* 3411 * sip_dp83815_mii_readreg: [mii interface function] 3412 * 3413 * Read a PHY register on the MII. 3414 */ 3415 static int 3416 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3417 { 3418 struct sip_softc *sc = (struct sip_softc *) self; 3419 u_int32_t val; 3420 3421 /* 3422 * The DP83815 only has an internal PHY. Only allow 3423 * MII address 0. 3424 */ 3425 if (phy != 0) 3426 return (0); 3427 3428 /* 3429 * Apparently, after a reset, the DP83815 can take a while 3430 * to respond. During this recovery period, the BMSR returns 3431 * a value of 0. Catch this -- it's not supposed to happen 3432 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3433 * PHY to come back to life. 3434 * 3435 * This works out because the BMSR is the first register 3436 * read during the PHY probe process. 3437 */ 3438 do { 3439 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3440 } while (reg == MII_BMSR && val == 0); 3441 3442 return (val & 0xffff); 3443 } 3444 3445 /* 3446 * sip_dp83815_mii_writereg: [mii interface function] 3447 * 3448 * Write a PHY register to the MII. 3449 */ 3450 static void 3451 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3452 { 3453 struct sip_softc *sc = (struct sip_softc *) self; 3454 3455 /* 3456 * The DP83815 only has an internal PHY. Only allow 3457 * MII address 0. 3458 */ 3459 if (phy != 0) 3460 return; 3461 3462 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3463 } 3464 3465 /* 3466 * sip_dp83815_mii_statchg: [mii interface function] 3467 * 3468 * Callback from MII layer when media changes. 3469 */ 3470 static void 3471 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3472 { 3473 struct sip_softc *sc = (struct sip_softc *) self; 3474 3475 /* 3476 * Update TXCFG for full-duplex operation. 3477 */ 3478 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3479 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3480 else 3481 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3482 3483 /* 3484 * Update RXCFG for full-duplex or loopback. 3485 */ 3486 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3487 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3488 sc->sc_rxcfg |= RXCFG_ATX; 3489 else 3490 sc->sc_rxcfg &= ~RXCFG_ATX; 3491 3492 /* 3493 * XXX 802.3x flow control. 3494 */ 3495 3496 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3497 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3498 3499 /* 3500 * Some DP83815s experience problems when used with short 3501 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3502 * sequence adjusts the DSP's signal attenuation to fix the 3503 * problem. 3504 */ 3505 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3506 uint32_t reg; 3507 3508 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3509 3510 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3511 reg &= 0x0fff; 3512 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3513 delay(100); 3514 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3515 reg &= 0x00ff; 3516 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3517 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3518 0x00e8); 3519 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3520 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3521 reg | 0x20); 3522 } 3523 3524 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3525 } 3526 } 3527 #endif /* DP83820 */ 3528 3529 #if defined(DP83820) 3530 static void 3531 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3532 const struct pci_attach_args *pa, u_int8_t *enaddr) 3533 { 3534 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3535 u_int8_t cksum, *e, match; 3536 int i; 3537 3538 /* 3539 * EEPROM data format for the DP83820 can be found in 3540 * the DP83820 manual, section 4.2.4. 3541 */ 3542 3543 SIP_DECL(read_eeprom)(sc, 0, 3544 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3545 3546 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3547 match = ~(match - 1); 3548 3549 cksum = 0x55; 3550 e = (u_int8_t *) eeprom_data; 3551 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3552 cksum += *e++; 3553 3554 if (cksum != match) 3555 printf("%s: Checksum (%x) mismatch (%x)", 3556 sc->sc_dev.dv_xname, cksum, match); 3557 3558 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3559 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3560 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3561 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3562 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3563 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3564 } 3565 #else /* ! DP83820 */ 3566 static void 3567 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3568 { 3569 int i; 3570 3571 /* 3572 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3573 * a reason, but I don't know it. 3574 */ 3575 for (i = 0; i < 10; i++) 3576 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3577 } 3578 3579 static void 3580 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3581 const struct pci_attach_args *pa, u_int8_t *enaddr) 3582 { 3583 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3584 3585 switch (sc->sc_rev) { 3586 case SIS_REV_630S: 3587 case SIS_REV_630E: 3588 case SIS_REV_630EA1: 3589 case SIS_REV_630ET: 3590 case SIS_REV_635: 3591 /* 3592 * The MAC address for the on-board Ethernet of 3593 * the SiS 630 chipset is in the NVRAM. Kick 3594 * the chip into re-loading it from NVRAM, and 3595 * read the MAC address out of the filter registers. 3596 */ 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3598 3599 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3600 RFCR_RFADDR_NODE0); 3601 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3602 0xffff; 3603 3604 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3605 RFCR_RFADDR_NODE2); 3606 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3607 0xffff; 3608 3609 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3610 RFCR_RFADDR_NODE4); 3611 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3612 0xffff; 3613 break; 3614 3615 case SIS_REV_960: 3616 { 3617 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3618 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3619 3620 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3621 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3622 3623 int waittime, i; 3624 3625 /* Allow to read EEPROM from LAN. It is shared 3626 * between a 1394 controller and the NIC and each 3627 * time we access it, we need to set SIS_EECMD_REQ. 3628 */ 3629 SIS_SET_EROMAR(sc, EROMAR_REQ); 3630 3631 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3632 /* Force EEPROM to idle state. */ 3633 3634 /* 3635 * XXX-cube This is ugly. I'll look for docs about it. 3636 */ 3637 SIS_SET_EROMAR(sc, EROMAR_EECS); 3638 SIP_DECL(sis900_eeprom_delay)(sc); 3639 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3640 SIS_SET_EROMAR(sc, EROMAR_EESK); 3641 SIP_DECL(sis900_eeprom_delay)(sc); 3642 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3643 SIP_DECL(sis900_eeprom_delay)(sc); 3644 } 3645 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3646 SIP_DECL(sis900_eeprom_delay)(sc); 3647 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3648 3649 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3650 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3651 sizeof(myea) / sizeof(myea[0]), myea); 3652 break; 3653 } 3654 DELAY(1); 3655 } 3656 3657 /* 3658 * Set SIS_EECTL_CLK to high, so a other master 3659 * can operate on the i2c bus. 3660 */ 3661 SIS_SET_EROMAR(sc, EROMAR_EESK); 3662 3663 /* Refuse EEPROM access by LAN */ 3664 SIS_SET_EROMAR(sc, EROMAR_DONE); 3665 } break; 3666 3667 default: 3668 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3669 sizeof(myea) / sizeof(myea[0]), myea); 3670 } 3671 3672 enaddr[0] = myea[0] & 0xff; 3673 enaddr[1] = myea[0] >> 8; 3674 enaddr[2] = myea[1] & 0xff; 3675 enaddr[3] = myea[1] >> 8; 3676 enaddr[4] = myea[2] & 0xff; 3677 enaddr[5] = myea[2] >> 8; 3678 } 3679 3680 /* Table and macro to bit-reverse an octet. */ 3681 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3682 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3683 3684 static void 3685 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3686 const struct pci_attach_args *pa, u_int8_t *enaddr) 3687 { 3688 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3689 u_int8_t cksum, *e, match; 3690 int i; 3691 3692 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3693 sizeof(eeprom_data[0]), eeprom_data); 3694 3695 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3696 match = ~(match - 1); 3697 3698 cksum = 0x55; 3699 e = (u_int8_t *) eeprom_data; 3700 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3701 cksum += *e++; 3702 } 3703 if (cksum != match) { 3704 printf("%s: Checksum (%x) mismatch (%x)", 3705 sc->sc_dev.dv_xname, cksum, match); 3706 } 3707 3708 /* 3709 * Unrolled because it makes slightly more sense this way. 3710 * The DP83815 stores the MAC address in bit 0 of word 6 3711 * through bit 15 of word 8. 3712 */ 3713 ea = &eeprom_data[6]; 3714 enaddr[0] = ((*ea & 0x1) << 7); 3715 ea++; 3716 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3717 enaddr[1] = ((*ea & 0x1FE) >> 1); 3718 enaddr[2] = ((*ea & 0x1) << 7); 3719 ea++; 3720 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3721 enaddr[3] = ((*ea & 0x1FE) >> 1); 3722 enaddr[4] = ((*ea & 0x1) << 7); 3723 ea++; 3724 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3725 enaddr[5] = ((*ea & 0x1FE) >> 1); 3726 3727 /* 3728 * In case that's not weird enough, we also need to reverse 3729 * the bits in each byte. This all actually makes more sense 3730 * if you think about the EEPROM storage as an array of bits 3731 * being shifted into bytes, but that's not how we're looking 3732 * at it here... 3733 */ 3734 for (i = 0; i < 6 ;i++) 3735 enaddr[i] = bbr(enaddr[i]); 3736 } 3737 #endif /* DP83820 */ 3738 3739 /* 3740 * sip_mediastatus: [ifmedia interface function] 3741 * 3742 * Get the current interface media status. 3743 */ 3744 static void 3745 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3746 { 3747 struct sip_softc *sc = ifp->if_softc; 3748 3749 mii_pollstat(&sc->sc_mii); 3750 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3751 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3752 sc->sc_flowflags; 3753 } 3754 3755 /* 3756 * sip_mediachange: [ifmedia interface function] 3757 * 3758 * Set hardware to newly-selected media. 3759 */ 3760 static int 3761 SIP_DECL(mediachange)(struct ifnet *ifp) 3762 { 3763 struct sip_softc *sc = ifp->if_softc; 3764 3765 if (ifp->if_flags & IFF_UP) 3766 mii_mediachg(&sc->sc_mii); 3767 return (0); 3768 } 3769
Indexes created Tue Sep 30 11:09:46 GMT 2025