if_sip.c revision 1.103.6.1
1 /* $NetBSD: if_sip.c,v 1.103.6.1 2006/04/22 11:39:14 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.103.6.1 2006/04/22 11:39:14 simonb Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 /* values of interface state at last init */ 313 struct { 314 /* if_capenable */ 315 uint64_t if_capenable; 316 /* ec_capenable */ 317 int ec_capenable; 318 /* VLAN_ATTACHED */ 319 int is_vlan; 320 } sc_prev; 321 322 short sc_if_flags; 323 324 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 325 #if defined(DP83820) 326 int sc_rxdiscard; 327 int sc_rxlen; 328 struct mbuf *sc_rxhead; 329 struct mbuf *sc_rxtail; 330 struct mbuf **sc_rxtailp; 331 #endif /* DP83820 */ 332 333 #if NRND > 0 334 rndsource_element_t rnd_source; /* random source */ 335 #endif 336 }; 337 338 #ifdef DP83820 339 #define SIP_RXCHAIN_RESET(sc) \ 340 do { \ 341 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 342 *(sc)->sc_rxtailp = NULL; \ 343 (sc)->sc_rxlen = 0; \ 344 } while (/*CONSTCOND*/0) 345 346 #define SIP_RXCHAIN_LINK(sc, m) \ 347 do { \ 348 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 349 (sc)->sc_rxtailp = &(m)->m_next; \ 350 } while (/*CONSTCOND*/0) 351 #endif /* DP83820 */ 352 353 #ifdef SIP_EVENT_COUNTERS 354 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 355 #else 356 #define SIP_EVCNT_INCR(ev) /* nothing */ 357 #endif 358 359 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 360 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 361 362 #define SIP_CDTXSYNC(sc, x, n, ops) \ 363 do { \ 364 int __x, __n; \ 365 \ 366 __x = (x); \ 367 __n = (n); \ 368 \ 369 /* If it will wrap around, sync to the end of the ring. */ \ 370 if ((__x + __n) > SIP_NTXDESC) { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 373 (SIP_NTXDESC - __x), (ops)); \ 374 __n -= (SIP_NTXDESC - __x); \ 375 __x = 0; \ 376 } \ 377 \ 378 /* Now sync whatever is left. */ \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 381 } while (0) 382 383 #define SIP_CDRXSYNC(sc, x, ops) \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 386 387 #ifdef DP83820 388 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 389 #define SIP_RXBUF_LEN (MCLBYTES - 8) 390 #else 391 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 392 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 393 #endif 394 #define SIP_INIT_RXDESC(sc, x) \ 395 do { \ 396 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 397 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 398 \ 399 __sipd->sipd_link = \ 400 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 401 __sipd->sipd_bufptr = \ 402 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 403 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 404 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 405 SIP_INIT_RXDESC_EXTSTS \ 406 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 407 } while (0) 408 409 #define SIP_CHIP_VERS(sc, v, p, r) \ 410 ((sc)->sc_model->sip_vendor == (v) && \ 411 (sc)->sc_model->sip_product == (p) && \ 412 (sc)->sc_rev == (r)) 413 414 #define SIP_CHIP_MODEL(sc, v, p) \ 415 ((sc)->sc_model->sip_vendor == (v) && \ 416 (sc)->sc_model->sip_product == (p)) 417 418 #if !defined(DP83820) 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 #endif 422 423 #define SIP_TIMEOUT 1000 424 425 static void SIP_DECL(start)(struct ifnet *); 426 static void SIP_DECL(watchdog)(struct ifnet *); 427 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 428 static int SIP_DECL(init)(struct ifnet *); 429 static void SIP_DECL(stop)(struct ifnet *, int); 430 431 static void SIP_DECL(shutdown)(void *); 432 433 static void SIP_DECL(reset)(struct sip_softc *); 434 static void SIP_DECL(rxdrain)(struct sip_softc *); 435 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 436 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 437 u_int16_t *); 438 static void SIP_DECL(tick)(void *); 439 440 #if !defined(DP83820) 441 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 442 #endif /* ! DP83820 */ 443 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 444 445 #if defined(DP83820) 446 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 447 const struct pci_attach_args *, u_int8_t *); 448 #else 449 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 450 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 451 const struct pci_attach_args *, u_int8_t *); 452 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 453 const struct pci_attach_args *, u_int8_t *); 454 #endif /* DP83820 */ 455 456 static int SIP_DECL(intr)(void *); 457 static void SIP_DECL(txintr)(struct sip_softc *); 458 static void SIP_DECL(rxintr)(struct sip_softc *); 459 460 #if defined(DP83820) 461 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 462 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 463 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 464 #else 465 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 466 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 467 static void SIP_DECL(sis900_mii_statchg)(struct device *); 468 469 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 470 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 471 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 472 #endif /* DP83820 */ 473 474 static int SIP_DECL(mediachange)(struct ifnet *); 475 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 476 477 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 478 static void SIP_DECL(attach)(struct device *, struct device *, void *); 479 480 int SIP_DECL(copy_small) = 0; 481 482 #ifdef DP83820 483 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 484 gsip_match, gsip_attach, NULL, NULL); 485 #else 486 CFATTACH_DECL(sip, sizeof(struct sip_softc), 487 sip_match, sip_attach, NULL, NULL); 488 #endif 489 490 /* 491 * Descriptions of the variants of the SiS900. 492 */ 493 struct sip_variant { 494 int (*sipv_mii_readreg)(struct device *, int, int); 495 void (*sipv_mii_writereg)(struct device *, int, int, int); 496 void (*sipv_mii_statchg)(struct device *); 497 void (*sipv_set_filter)(struct sip_softc *); 498 void (*sipv_read_macaddr)(struct sip_softc *, 499 const struct pci_attach_args *, u_int8_t *); 500 }; 501 502 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 503 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 504 505 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 506 SIP_DECL(mii_bitbang_read), 507 SIP_DECL(mii_bitbang_write), 508 { 509 EROMAR_MDIO, /* MII_BIT_MDO */ 510 EROMAR_MDIO, /* MII_BIT_MDI */ 511 EROMAR_MDC, /* MII_BIT_MDC */ 512 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 513 0, /* MII_BIT_DIR_PHY_HOST */ 514 } 515 }; 516 517 #if defined(DP83820) 518 static const struct sip_variant SIP_DECL(variant_dp83820) = { 519 SIP_DECL(dp83820_mii_readreg), 520 SIP_DECL(dp83820_mii_writereg), 521 SIP_DECL(dp83820_mii_statchg), 522 SIP_DECL(dp83815_set_filter), 523 SIP_DECL(dp83820_read_macaddr), 524 }; 525 #else 526 static const struct sip_variant SIP_DECL(variant_sis900) = { 527 SIP_DECL(sis900_mii_readreg), 528 SIP_DECL(sis900_mii_writereg), 529 SIP_DECL(sis900_mii_statchg), 530 SIP_DECL(sis900_set_filter), 531 SIP_DECL(sis900_read_macaddr), 532 }; 533 534 static const struct sip_variant SIP_DECL(variant_dp83815) = { 535 SIP_DECL(dp83815_mii_readreg), 536 SIP_DECL(dp83815_mii_writereg), 537 SIP_DECL(dp83815_mii_statchg), 538 SIP_DECL(dp83815_set_filter), 539 SIP_DECL(dp83815_read_macaddr), 540 }; 541 #endif /* DP83820 */ 542 543 /* 544 * Devices supported by this driver. 545 */ 546 static const struct sip_product { 547 pci_vendor_id_t sip_vendor; 548 pci_product_id_t sip_product; 549 const char *sip_name; 550 const struct sip_variant *sip_variant; 551 } SIP_DECL(products)[] = { 552 #if defined(DP83820) 553 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 554 "NatSemi DP83820 Gigabit Ethernet", 555 &SIP_DECL(variant_dp83820) }, 556 #else 557 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 558 "SiS 900 10/100 Ethernet", 559 &SIP_DECL(variant_sis900) }, 560 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 561 "SiS 7016 10/100 Ethernet", 562 &SIP_DECL(variant_sis900) }, 563 564 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 565 "NatSemi DP83815 10/100 Ethernet", 566 &SIP_DECL(variant_dp83815) }, 567 #endif /* DP83820 */ 568 569 { 0, 0, 570 NULL, 571 NULL }, 572 }; 573 574 static const struct sip_product * 575 SIP_DECL(lookup)(const struct pci_attach_args *pa) 576 { 577 const struct sip_product *sip; 578 579 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 580 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 581 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 582 return (sip); 583 } 584 return (NULL); 585 } 586 587 #ifdef DP83820 588 /* 589 * I really hate stupid hardware vendors. There's a bit in the EEPROM 590 * which indicates if the card can do 64-bit data transfers. Unfortunately, 591 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 592 * which means we try to use 64-bit data transfers on those cards if we 593 * happen to be plugged into a 32-bit slot. 594 * 595 * What we do is use this table of cards known to be 64-bit cards. If 596 * you have a 64-bit card who's subsystem ID is not listed in this table, 597 * send the output of "pcictl dump ..." of the device to me so that your 598 * card will use the 64-bit data path when plugged into a 64-bit slot. 599 * 600 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 601 * June 30, 2002 602 */ 603 static int 604 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 605 { 606 static const struct { 607 pci_vendor_id_t c64_vendor; 608 pci_product_id_t c64_product; 609 } card64[] = { 610 /* Asante GigaNIX */ 611 { 0x128a, 0x0002 }, 612 613 /* Accton EN1407-T, Planex GN-1000TE */ 614 { 0x1113, 0x1407 }, 615 616 /* Netgear GA-621 */ 617 { 0x1385, 0x621a }, 618 619 /* SMC EZ Card */ 620 { 0x10b8, 0x9462 }, 621 622 { 0, 0} 623 }; 624 pcireg_t subsys; 625 int i; 626 627 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 628 629 for (i = 0; card64[i].c64_vendor != 0; i++) { 630 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 631 PCI_PRODUCT(subsys) == card64[i].c64_product) 632 return (1); 633 } 634 635 return (0); 636 } 637 #endif /* DP83820 */ 638 639 static int 640 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 641 { 642 struct pci_attach_args *pa = aux; 643 644 if (SIP_DECL(lookup)(pa) != NULL) 645 return (1); 646 647 return (0); 648 } 649 650 static void 651 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 652 { 653 struct sip_softc *sc = (struct sip_softc *) self; 654 struct pci_attach_args *pa = aux; 655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 656 pci_chipset_tag_t pc = pa->pa_pc; 657 pci_intr_handle_t ih; 658 const char *intrstr = NULL; 659 bus_space_tag_t iot, memt; 660 bus_space_handle_t ioh, memh; 661 bus_dma_segment_t seg; 662 int ioh_valid, memh_valid; 663 int i, rseg, error; 664 const struct sip_product *sip; 665 pcireg_t pmode; 666 u_int8_t enaddr[ETHER_ADDR_LEN]; 667 int pmreg; 668 #ifdef DP83820 669 pcireg_t memtype; 670 u_int32_t reg; 671 #endif /* DP83820 */ 672 673 callout_init(&sc->sc_tick_ch); 674 675 sip = SIP_DECL(lookup)(pa); 676 if (sip == NULL) { 677 printf("\n"); 678 panic(SIP_STR(attach) ": impossible"); 679 } 680 sc->sc_rev = PCI_REVISION(pa->pa_class); 681 682 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 683 684 sc->sc_model = sip; 685 686 /* 687 * XXX Work-around broken PXE firmware on some boards. 688 * 689 * The DP83815 shares an address decoder with the MEM BAR 690 * and the ROM BAR. Make sure the ROM BAR is disabled, 691 * so that memory mapped access works. 692 */ 693 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 694 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 695 ~PCI_MAPREG_ROM_ENABLE); 696 697 /* 698 * Map the device. 699 */ 700 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 701 PCI_MAPREG_TYPE_IO, 0, 702 &iot, &ioh, NULL, NULL) == 0); 703 #ifdef DP83820 704 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 705 switch (memtype) { 706 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 707 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 708 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 709 memtype, 0, &memt, &memh, NULL, NULL) == 0); 710 break; 711 default: 712 memh_valid = 0; 713 } 714 #else 715 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 716 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 717 &memt, &memh, NULL, NULL) == 0); 718 #endif /* DP83820 */ 719 720 if (memh_valid) { 721 sc->sc_st = memt; 722 sc->sc_sh = memh; 723 } else if (ioh_valid) { 724 sc->sc_st = iot; 725 sc->sc_sh = ioh; 726 } else { 727 printf("%s: unable to map device registers\n", 728 sc->sc_dev.dv_xname); 729 return; 730 } 731 732 sc->sc_dmat = pa->pa_dmat; 733 734 /* 735 * Make sure bus mastering is enabled. Also make sure 736 * Write/Invalidate is enabled if we're allowed to use it. 737 */ 738 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 739 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 740 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 741 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 742 pmreg | PCI_COMMAND_MASTER_ENABLE); 743 744 /* Get it out of power save mode if needed. */ 745 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 746 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 747 PCI_PMCSR_STATE_MASK; 748 if (pmode == PCI_PMCSR_STATE_D3) { 749 /* 750 * The card has lost all configuration data in 751 * this state, so punt. 752 */ 753 printf("%s: unable to wake up from power state D3\n", 754 sc->sc_dev.dv_xname); 755 return; 756 } 757 if (pmode != PCI_PMCSR_STATE_D0) { 758 printf("%s: waking up from power state D%d\n", 759 sc->sc_dev.dv_xname, pmode); 760 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 761 PCI_PMCSR_STATE_D0); 762 } 763 } 764 765 /* 766 * Map and establish our interrupt. 767 */ 768 if (pci_intr_map(pa, &ih)) { 769 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 770 return; 771 } 772 intrstr = pci_intr_string(pc, ih); 773 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 774 if (sc->sc_ih == NULL) { 775 printf("%s: unable to establish interrupt", 776 sc->sc_dev.dv_xname); 777 if (intrstr != NULL) 778 printf(" at %s", intrstr); 779 printf("\n"); 780 return; 781 } 782 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 783 784 SIMPLEQ_INIT(&sc->sc_txfreeq); 785 SIMPLEQ_INIT(&sc->sc_txdirtyq); 786 787 /* 788 * Allocate the control data structures, and create and load the 789 * DMA map for it. 790 */ 791 if ((error = bus_dmamem_alloc(sc->sc_dmat, 792 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 793 0)) != 0) { 794 printf("%s: unable to allocate control data, error = %d\n", 795 sc->sc_dev.dv_xname, error); 796 goto fail_0; 797 } 798 799 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 800 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 801 BUS_DMA_COHERENT)) != 0) { 802 printf("%s: unable to map control data, error = %d\n", 803 sc->sc_dev.dv_xname, error); 804 goto fail_1; 805 } 806 807 if ((error = bus_dmamap_create(sc->sc_dmat, 808 sizeof(struct sip_control_data), 1, 809 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 810 printf("%s: unable to create control data DMA map, " 811 "error = %d\n", sc->sc_dev.dv_xname, error); 812 goto fail_2; 813 } 814 815 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 816 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 817 0)) != 0) { 818 printf("%s: unable to load control data DMA map, error = %d\n", 819 sc->sc_dev.dv_xname, error); 820 goto fail_3; 821 } 822 823 /* 824 * Create the transmit buffer DMA maps. 825 */ 826 for (i = 0; i < SIP_TXQUEUELEN; i++) { 827 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 828 SIP_NTXSEGS, MCLBYTES, 0, 0, 829 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 830 printf("%s: unable to create tx DMA map %d, " 831 "error = %d\n", sc->sc_dev.dv_xname, i, error); 832 goto fail_4; 833 } 834 } 835 836 /* 837 * Create the receive buffer DMA maps. 838 */ 839 for (i = 0; i < SIP_NRXDESC; i++) { 840 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 841 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 842 printf("%s: unable to create rx DMA map %d, " 843 "error = %d\n", sc->sc_dev.dv_xname, i, error); 844 goto fail_5; 845 } 846 sc->sc_rxsoft[i].rxs_mbuf = NULL; 847 } 848 849 /* 850 * Reset the chip to a known state. 851 */ 852 SIP_DECL(reset)(sc); 853 854 /* 855 * Read the Ethernet address from the EEPROM. This might 856 * also fetch other stuff from the EEPROM and stash it 857 * in the softc. 858 */ 859 sc->sc_cfg = 0; 860 #if !defined(DP83820) 861 if (SIP_SIS900_REV(sc,SIS_REV_635) || 862 SIP_SIS900_REV(sc,SIS_REV_900B)) 863 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 864 865 if (SIP_SIS900_REV(sc,SIS_REV_635) || 866 SIP_SIS900_REV(sc,SIS_REV_960) || 867 SIP_SIS900_REV(sc,SIS_REV_900B)) 868 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 869 SIP_CFG) & CFG_EDBMASTEN); 870 #endif 871 872 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 873 874 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 875 ether_sprintf(enaddr)); 876 877 /* 878 * Initialize the configuration register: aggressive PCI 879 * bus request algorithm, default backoff, default OW timer, 880 * default parity error detection. 881 * 882 * NOTE: "Big endian mode" is useless on the SiS900 and 883 * friends -- it affects packet data, not descriptors. 884 */ 885 #ifdef DP83820 886 /* 887 * Cause the chip to load configuration data from the EEPROM. 888 */ 889 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 890 for (i = 0; i < 10000; i++) { 891 delay(10); 892 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 893 PTSCR_EELOAD_EN) == 0) 894 break; 895 } 896 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 897 PTSCR_EELOAD_EN) { 898 printf("%s: timeout loading configuration from EEPROM\n", 899 sc->sc_dev.dv_xname); 900 return; 901 } 902 903 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 904 905 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 906 if (reg & CFG_PCI64_DET) { 907 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 908 /* 909 * Check to see if this card is 64-bit. If so, enable 64-bit 910 * data transfers. 911 * 912 * We can't use the DATA64_EN bit in the EEPROM, because 913 * vendors of 32-bit cards fail to clear that bit in many 914 * cases (yet the card still detects that it's in a 64-bit 915 * slot; go figure). 916 */ 917 if (SIP_DECL(check_64bit)(pa)) { 918 sc->sc_cfg |= CFG_DATA64_EN; 919 printf(", using 64-bit data transfers"); 920 } 921 printf("\n"); 922 } 923 924 /* 925 * XXX Need some PCI flags indicating support for 926 * XXX 64-bit addressing. 927 */ 928 #if 0 929 if (reg & CFG_M64ADDR) 930 sc->sc_cfg |= CFG_M64ADDR; 931 if (reg & CFG_T64ADDR) 932 sc->sc_cfg |= CFG_T64ADDR; 933 #endif 934 935 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 936 const char *sep = ""; 937 printf("%s: using ", sc->sc_dev.dv_xname); 938 if (reg & CFG_EXT_125) { 939 sc->sc_cfg |= CFG_EXT_125; 940 printf("%s125MHz clock", sep); 941 sep = ", "; 942 } 943 if (reg & CFG_TBI_EN) { 944 sc->sc_cfg |= CFG_TBI_EN; 945 printf("%sten-bit interface", sep); 946 sep = ", "; 947 } 948 printf("\n"); 949 } 950 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 951 (reg & CFG_MRM_DIS) != 0) 952 sc->sc_cfg |= CFG_MRM_DIS; 953 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 954 (reg & CFG_MWI_DIS) != 0) 955 sc->sc_cfg |= CFG_MWI_DIS; 956 957 /* 958 * Use the extended descriptor format on the DP83820. This 959 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 960 * checksumming. 961 */ 962 sc->sc_cfg |= CFG_EXTSTS_EN; 963 #endif /* DP83820 */ 964 965 /* 966 * Initialize our media structures and probe the MII. 967 */ 968 sc->sc_mii.mii_ifp = ifp; 969 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 970 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 971 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 972 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 973 SIP_DECL(mediastatus)); 974 975 /* 976 * XXX We cannot handle flow control on the DP83815. 977 */ 978 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 979 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 980 MII_OFFSET_ANY, 0); 981 else 982 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 983 MII_OFFSET_ANY, MIIF_DOPAUSE); 984 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 985 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 986 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 987 } else 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 989 990 ifp = &sc->sc_ethercom.ec_if; 991 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 992 ifp->if_softc = sc; 993 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 994 sc->sc_if_flags = ifp->if_flags; 995 ifp->if_ioctl = SIP_DECL(ioctl); 996 ifp->if_start = SIP_DECL(start); 997 ifp->if_watchdog = SIP_DECL(watchdog); 998 ifp->if_init = SIP_DECL(init); 999 ifp->if_stop = SIP_DECL(stop); 1000 IFQ_SET_READY(&ifp->if_snd); 1001 1002 /* 1003 * We can support 802.1Q VLAN-sized frames. 1004 */ 1005 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1006 1007 #ifdef DP83820 1008 /* 1009 * And the DP83820 can do VLAN tagging in hardware, and 1010 * support the jumbo Ethernet MTU. 1011 */ 1012 sc->sc_ethercom.ec_capabilities |= 1013 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1014 1015 /* 1016 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1017 * in hardware. 1018 */ 1019 ifp->if_capabilities |= 1020 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1021 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1022 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1023 #endif /* DP83820 */ 1024 1025 /* 1026 * Attach the interface. 1027 */ 1028 if_attach(ifp); 1029 ether_ifattach(ifp, enaddr); 1030 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1031 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1032 sc->sc_prev.if_capenable = ifp->if_capenable; 1033 #if NRND > 0 1034 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1035 RND_TYPE_NET, 0); 1036 #endif 1037 1038 /* 1039 * The number of bytes that must be available in 1040 * the Tx FIFO before the bus master can DMA more 1041 * data into the FIFO. 1042 */ 1043 sc->sc_tx_fill_thresh = 64 / 32; 1044 1045 /* 1046 * Start at a drain threshold of 512 bytes. We will 1047 * increase it if a DMA underrun occurs. 1048 * 1049 * XXX The minimum value of this variable should be 1050 * tuned. We may be able to improve performance 1051 * by starting with a lower value. That, however, 1052 * may trash the first few outgoing packets if the 1053 * PCI bus is saturated. 1054 */ 1055 #ifdef DP83820 1056 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1057 #else 1058 sc->sc_tx_drain_thresh = 1504 / 32; 1059 #endif 1060 1061 /* 1062 * Initialize the Rx FIFO drain threshold. 1063 * 1064 * This is in units of 8 bytes. 1065 * 1066 * We should never set this value lower than 2; 14 bytes are 1067 * required to filter the packet. 1068 */ 1069 sc->sc_rx_drain_thresh = 128 / 8; 1070 1071 #ifdef SIP_EVENT_COUNTERS 1072 /* 1073 * Attach event counters. 1074 */ 1075 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1076 NULL, sc->sc_dev.dv_xname, "txsstall"); 1077 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1078 NULL, sc->sc_dev.dv_xname, "txdstall"); 1079 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1080 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1082 NULL, sc->sc_dev.dv_xname, "txdintr"); 1083 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1084 NULL, sc->sc_dev.dv_xname, "txiintr"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1086 NULL, sc->sc_dev.dv_xname, "rxintr"); 1087 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1088 NULL, sc->sc_dev.dv_xname, "hiberr"); 1089 #ifndef DP83820 1090 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1091 NULL, sc->sc_dev.dv_xname, "rxpause"); 1092 #endif /* !DP83820 */ 1093 #ifdef DP83820 1094 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1095 NULL, sc->sc_dev.dv_xname, "rxpause"); 1096 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1097 NULL, sc->sc_dev.dv_xname, "txpause"); 1098 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1099 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1100 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1101 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1102 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1103 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1104 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1105 NULL, sc->sc_dev.dv_xname, "txipsum"); 1106 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1107 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1108 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1109 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1110 #endif /* DP83820 */ 1111 #endif /* SIP_EVENT_COUNTERS */ 1112 1113 /* 1114 * Make sure the interface is shutdown during reboot. 1115 */ 1116 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1117 if (sc->sc_sdhook == NULL) 1118 printf("%s: WARNING: unable to establish shutdown hook\n", 1119 sc->sc_dev.dv_xname); 1120 return; 1121 1122 /* 1123 * Free any resources we've allocated during the failed attach 1124 * attempt. Do this in reverse order and fall through. 1125 */ 1126 fail_5: 1127 for (i = 0; i < SIP_NRXDESC; i++) { 1128 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1129 bus_dmamap_destroy(sc->sc_dmat, 1130 sc->sc_rxsoft[i].rxs_dmamap); 1131 } 1132 fail_4: 1133 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1134 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1135 bus_dmamap_destroy(sc->sc_dmat, 1136 sc->sc_txsoft[i].txs_dmamap); 1137 } 1138 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1139 fail_3: 1140 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1141 fail_2: 1142 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1143 sizeof(struct sip_control_data)); 1144 fail_1: 1145 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1146 fail_0: 1147 return; 1148 } 1149 1150 /* 1151 * sip_shutdown: 1152 * 1153 * Make sure the interface is stopped at reboot time. 1154 */ 1155 static void 1156 SIP_DECL(shutdown)(void *arg) 1157 { 1158 struct sip_softc *sc = arg; 1159 1160 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1161 } 1162 1163 /* 1164 * sip_start: [ifnet interface function] 1165 * 1166 * Start packet transmission on the interface. 1167 */ 1168 static void 1169 SIP_DECL(start)(struct ifnet *ifp) 1170 { 1171 struct sip_softc *sc = ifp->if_softc; 1172 struct mbuf *m0; 1173 #ifndef DP83820 1174 struct mbuf *m; 1175 #endif 1176 struct sip_txsoft *txs; 1177 bus_dmamap_t dmamap; 1178 int error, nexttx, lasttx, seg; 1179 int ofree = sc->sc_txfree; 1180 #if 0 1181 int firsttx = sc->sc_txnext; 1182 #endif 1183 #ifdef DP83820 1184 struct m_tag *mtag; 1185 u_int32_t extsts; 1186 #endif 1187 1188 #ifndef DP83820 1189 /* 1190 * If we've been told to pause, don't transmit any more packets. 1191 */ 1192 if (sc->sc_paused) 1193 ifp->if_flags |= IFF_OACTIVE; 1194 #endif 1195 1196 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1197 return; 1198 1199 /* 1200 * Loop through the send queue, setting up transmit descriptors 1201 * until we drain the queue, or use up all available transmit 1202 * descriptors. 1203 */ 1204 for (;;) { 1205 /* Get a work queue entry. */ 1206 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1207 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1208 break; 1209 } 1210 1211 /* 1212 * Grab a packet off the queue. 1213 */ 1214 IFQ_POLL(&ifp->if_snd, m0); 1215 if (m0 == NULL) 1216 break; 1217 #ifndef DP83820 1218 m = NULL; 1219 #endif 1220 1221 dmamap = txs->txs_dmamap; 1222 1223 #ifdef DP83820 1224 /* 1225 * Load the DMA map. If this fails, the packet either 1226 * didn't fit in the allotted number of segments, or we 1227 * were short on resources. For the too-many-segments 1228 * case, we simply report an error and drop the packet, 1229 * since we can't sanely copy a jumbo packet to a single 1230 * buffer. 1231 */ 1232 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1233 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1234 if (error) { 1235 if (error == EFBIG) { 1236 printf("%s: Tx packet consumes too many " 1237 "DMA segments, dropping...\n", 1238 sc->sc_dev.dv_xname); 1239 IFQ_DEQUEUE(&ifp->if_snd, m0); 1240 m_freem(m0); 1241 continue; 1242 } 1243 /* 1244 * Short on resources, just stop for now. 1245 */ 1246 break; 1247 } 1248 #else /* DP83820 */ 1249 /* 1250 * Load the DMA map. If this fails, the packet either 1251 * didn't fit in the alloted number of segments, or we 1252 * were short on resources. In this case, we'll copy 1253 * and try again. 1254 */ 1255 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1256 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1257 MGETHDR(m, M_DONTWAIT, MT_DATA); 1258 if (m == NULL) { 1259 printf("%s: unable to allocate Tx mbuf\n", 1260 sc->sc_dev.dv_xname); 1261 break; 1262 } 1263 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1264 if (m0->m_pkthdr.len > MHLEN) { 1265 MCLGET(m, M_DONTWAIT); 1266 if ((m->m_flags & M_EXT) == 0) { 1267 printf("%s: unable to allocate Tx " 1268 "cluster\n", sc->sc_dev.dv_xname); 1269 m_freem(m); 1270 break; 1271 } 1272 } 1273 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1274 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1275 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1276 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1277 if (error) { 1278 printf("%s: unable to load Tx buffer, " 1279 "error = %d\n", sc->sc_dev.dv_xname, error); 1280 break; 1281 } 1282 } 1283 #endif /* DP83820 */ 1284 1285 /* 1286 * Ensure we have enough descriptors free to describe 1287 * the packet. Note, we always reserve one descriptor 1288 * at the end of the ring as a termination point, to 1289 * prevent wrap-around. 1290 */ 1291 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1292 /* 1293 * Not enough free descriptors to transmit this 1294 * packet. We haven't committed anything yet, 1295 * so just unload the DMA map, put the packet 1296 * back on the queue, and punt. Notify the upper 1297 * layer that there are not more slots left. 1298 * 1299 * XXX We could allocate an mbuf and copy, but 1300 * XXX is it worth it? 1301 */ 1302 ifp->if_flags |= IFF_OACTIVE; 1303 bus_dmamap_unload(sc->sc_dmat, dmamap); 1304 #ifndef DP83820 1305 if (m != NULL) 1306 m_freem(m); 1307 #endif 1308 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1309 break; 1310 } 1311 1312 IFQ_DEQUEUE(&ifp->if_snd, m0); 1313 #ifndef DP83820 1314 if (m != NULL) { 1315 m_freem(m0); 1316 m0 = m; 1317 } 1318 #endif 1319 1320 /* 1321 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1322 */ 1323 1324 /* Sync the DMA map. */ 1325 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1326 BUS_DMASYNC_PREWRITE); 1327 1328 /* 1329 * Initialize the transmit descriptors. 1330 */ 1331 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1332 seg < dmamap->dm_nsegs; 1333 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1334 /* 1335 * If this is the first descriptor we're 1336 * enqueueing, don't set the OWN bit just 1337 * yet. That could cause a race condition. 1338 * We'll do it below. 1339 */ 1340 sc->sc_txdescs[nexttx].sipd_bufptr = 1341 htole32(dmamap->dm_segs[seg].ds_addr); 1342 sc->sc_txdescs[nexttx].sipd_cmdsts = 1343 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1344 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1345 #ifdef DP83820 1346 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1347 #endif /* DP83820 */ 1348 lasttx = nexttx; 1349 } 1350 1351 /* Clear the MORE bit on the last segment. */ 1352 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1353 1354 /* 1355 * If we're in the interrupt delay window, delay the 1356 * interrupt. 1357 */ 1358 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1359 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1360 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1361 htole32(CMDSTS_INTR); 1362 sc->sc_txwin = 0; 1363 } 1364 1365 #ifdef DP83820 1366 /* 1367 * If VLANs are enabled and the packet has a VLAN tag, set 1368 * up the descriptor to encapsulate the packet for us. 1369 * 1370 * This apparently has to be on the last descriptor of 1371 * the packet. 1372 */ 1373 1374 /* 1375 * Byte swapping is tricky. We need to provide the tag 1376 * in a network byte order. On a big-endian machine, 1377 * the byteorder is correct, but we need to swap it 1378 * anyway, because this will be undone by the outside 1379 * htole32(). That's why there must be an 1380 * unconditional swap instead of htons() inside. 1381 */ 1382 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1383 sc->sc_txdescs[lasttx].sipd_extsts |= 1384 htole32(EXTSTS_VPKT | 1385 (bswap16(VLAN_TAG_VALUE(mtag)) & 1386 EXTSTS_VTCI)); 1387 } 1388 1389 /* 1390 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1391 * checksumming, set up the descriptor to do this work 1392 * for us. 1393 * 1394 * This apparently has to be on the first descriptor of 1395 * the packet. 1396 * 1397 * Byte-swap constants so the compiler can optimize. 1398 */ 1399 extsts = 0; 1400 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1401 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1402 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1403 extsts |= htole32(EXTSTS_IPPKT); 1404 } 1405 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1406 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1407 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1408 extsts |= htole32(EXTSTS_TCPPKT); 1409 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1410 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1411 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1412 extsts |= htole32(EXTSTS_UDPPKT); 1413 } 1414 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1415 #endif /* DP83820 */ 1416 1417 /* Sync the descriptors we're using. */ 1418 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1419 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1420 1421 /* 1422 * The entire packet is set up. Give the first descrptor 1423 * to the chip now. 1424 */ 1425 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1426 htole32(CMDSTS_OWN); 1427 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1428 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1429 1430 /* 1431 * Store a pointer to the packet so we can free it later, 1432 * and remember what txdirty will be once the packet is 1433 * done. 1434 */ 1435 txs->txs_mbuf = m0; 1436 txs->txs_firstdesc = sc->sc_txnext; 1437 txs->txs_lastdesc = lasttx; 1438 1439 /* Advance the tx pointer. */ 1440 sc->sc_txfree -= dmamap->dm_nsegs; 1441 sc->sc_txnext = nexttx; 1442 1443 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1444 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1445 1446 #if NBPFILTER > 0 1447 /* 1448 * Pass the packet to any BPF listeners. 1449 */ 1450 if (ifp->if_bpf) 1451 bpf_mtap(ifp->if_bpf, m0); 1452 #endif /* NBPFILTER > 0 */ 1453 } 1454 1455 if (txs == NULL || sc->sc_txfree == 0) { 1456 /* No more slots left; notify upper layer. */ 1457 ifp->if_flags |= IFF_OACTIVE; 1458 } 1459 1460 if (sc->sc_txfree != ofree) { 1461 /* 1462 * Start the transmit process. Note, the manual says 1463 * that if there are no pending transmissions in the 1464 * chip's internal queue (indicated by TXE being clear), 1465 * then the driver software must set the TXDP to the 1466 * first descriptor to be transmitted. However, if we 1467 * do this, it causes serious performance degredation on 1468 * the DP83820 under load, not setting TXDP doesn't seem 1469 * to adversely affect the SiS 900 or DP83815. 1470 * 1471 * Well, I guess it wouldn't be the first time a manual 1472 * has lied -- and they could be speaking of the NULL- 1473 * terminated descriptor list case, rather than OWN- 1474 * terminated rings. 1475 */ 1476 #if 0 1477 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1478 CR_TXE) == 0) { 1479 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1480 SIP_CDTXADDR(sc, firsttx)); 1481 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1482 } 1483 #else 1484 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1485 #endif 1486 1487 /* Set a watchdog timer in case the chip flakes out. */ 1488 #ifdef DP83820 1489 /* Gigabit autonegotiation takes 5 seconds. */ 1490 ifp->if_timer = 10; 1491 #else 1492 ifp->if_timer = 5; 1493 #endif 1494 } 1495 } 1496 1497 /* 1498 * sip_watchdog: [ifnet interface function] 1499 * 1500 * Watchdog timer handler. 1501 */ 1502 static void 1503 SIP_DECL(watchdog)(struct ifnet *ifp) 1504 { 1505 struct sip_softc *sc = ifp->if_softc; 1506 1507 /* 1508 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1509 * If we get a timeout, try and sweep up transmit descriptors. 1510 * If we manage to sweep them all up, ignore the lack of 1511 * interrupt. 1512 */ 1513 SIP_DECL(txintr)(sc); 1514 1515 if (sc->sc_txfree != SIP_NTXDESC) { 1516 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1517 ifp->if_oerrors++; 1518 1519 /* Reset the interface. */ 1520 (void) SIP_DECL(init)(ifp); 1521 } else if (ifp->if_flags & IFF_DEBUG) 1522 printf("%s: recovered from device timeout\n", 1523 sc->sc_dev.dv_xname); 1524 1525 /* Try to get more packets going. */ 1526 SIP_DECL(start)(ifp); 1527 } 1528 1529 /* 1530 * sip_ioctl: [ifnet interface function] 1531 * 1532 * Handle control requests from the operator. 1533 */ 1534 static int 1535 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1536 { 1537 struct sip_softc *sc = ifp->if_softc; 1538 struct ifreq *ifr = (struct ifreq *)data; 1539 int s, error; 1540 1541 s = splnet(); 1542 1543 switch (cmd) { 1544 case SIOCSIFMEDIA: 1545 /* Flow control requires full-duplex mode. */ 1546 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1547 (ifr->ifr_media & IFM_FDX) == 0) 1548 ifr->ifr_media &= ~IFM_ETH_FMASK; 1549 #ifdef DP83820 1550 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1551 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1552 /* We can do both TXPAUSE and RXPAUSE. */ 1553 ifr->ifr_media |= 1554 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1555 } 1556 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1557 } 1558 #else 1559 /* XXX */ 1560 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1561 ifr->ifr_media &= ~IFM_ETH_FMASK; 1562 1563 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1564 if (ifr->ifr_media & IFM_FLOW) { 1565 /* 1566 * Both TXPAUSE and RXPAUSE must be set. 1567 * (SiS900 and DP83815 don't have PAUSE_ASYM 1568 * feature.) 1569 * 1570 * XXX Can SiS900 and DP83815 send PAUSE? 1571 */ 1572 ifr->ifr_media |= 1573 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1574 } 1575 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1576 } 1577 #endif 1578 /* FALLTHROUGH */ 1579 case SIOCGIFMEDIA: 1580 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1581 break; 1582 case SIOCSIFFLAGS: 1583 /* If the interface is up and running, only modify the receive 1584 * filter when setting promiscuous or debug mode. Otherwise 1585 * fall through to ether_ioctl, which will reset the chip. 1586 */ 1587 1588 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1589 == (sc)->sc_ethercom.ec_capenable) \ 1590 && ((sc)->sc_prev.is_vlan == \ 1591 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1592 1593 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1594 1595 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1596 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1597 == (IFF_UP|IFF_RUNNING)) 1598 && ((ifp->if_flags & (~RESETIGN)) 1599 == (sc->sc_if_flags & (~RESETIGN))) 1600 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1601 /* Set up the receive filter. */ 1602 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1603 error = 0; 1604 break; 1605 #undef RESETIGN 1606 } 1607 /* FALLTHROUGH */ 1608 default: 1609 error = ether_ioctl(ifp, cmd, data); 1610 if (error == ENETRESET) { 1611 /* 1612 * Multicast list has changed; set the hardware filter 1613 * accordingly. 1614 */ 1615 if (ifp->if_flags & IFF_RUNNING) 1616 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1617 error = 0; 1618 } 1619 break; 1620 } 1621 1622 /* Try to get more packets going. */ 1623 SIP_DECL(start)(ifp); 1624 1625 sc->sc_if_flags = ifp->if_flags; 1626 splx(s); 1627 return (error); 1628 } 1629 1630 /* 1631 * sip_intr: 1632 * 1633 * Interrupt service routine. 1634 */ 1635 static int 1636 SIP_DECL(intr)(void *arg) 1637 { 1638 struct sip_softc *sc = arg; 1639 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1640 u_int32_t isr; 1641 int handled = 0; 1642 1643 /* Disable interrupts. */ 1644 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1645 1646 for (;;) { 1647 /* Reading clears interrupt. */ 1648 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1649 if ((isr & sc->sc_imr) == 0) 1650 break; 1651 1652 #if NRND > 0 1653 if (RND_ENABLED(&sc->rnd_source)) 1654 rnd_add_uint32(&sc->rnd_source, isr); 1655 #endif 1656 1657 handled = 1; 1658 1659 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1660 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1661 1662 /* Grab any new packets. */ 1663 SIP_DECL(rxintr)(sc); 1664 1665 if (isr & ISR_RXORN) { 1666 printf("%s: receive FIFO overrun\n", 1667 sc->sc_dev.dv_xname); 1668 1669 /* XXX adjust rx_drain_thresh? */ 1670 } 1671 1672 if (isr & ISR_RXIDLE) { 1673 printf("%s: receive ring overrun\n", 1674 sc->sc_dev.dv_xname); 1675 1676 /* Get the receive process going again. */ 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, 1678 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, 1680 SIP_CR, CR_RXE); 1681 } 1682 } 1683 1684 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1685 #ifdef SIP_EVENT_COUNTERS 1686 if (isr & ISR_TXDESC) 1687 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1688 else if (isr & ISR_TXIDLE) 1689 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1690 #endif 1691 1692 /* Sweep up transmit descriptors. */ 1693 SIP_DECL(txintr)(sc); 1694 1695 if (isr & ISR_TXURN) { 1696 u_int32_t thresh; 1697 1698 printf("%s: transmit FIFO underrun", 1699 sc->sc_dev.dv_xname); 1700 1701 thresh = sc->sc_tx_drain_thresh + 1; 1702 if (thresh <= TXCFG_DRTH && 1703 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1704 (sc->sc_tx_fill_thresh * 32))) { 1705 printf("; increasing Tx drain " 1706 "threshold to %u bytes\n", 1707 thresh * 32); 1708 sc->sc_tx_drain_thresh = thresh; 1709 (void) SIP_DECL(init)(ifp); 1710 } else { 1711 (void) SIP_DECL(init)(ifp); 1712 printf("\n"); 1713 } 1714 } 1715 } 1716 1717 #if !defined(DP83820) 1718 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1719 if (isr & ISR_PAUSE_ST) { 1720 sc->sc_paused = 1; 1721 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1722 ifp->if_flags |= IFF_OACTIVE; 1723 } 1724 if (isr & ISR_PAUSE_END) { 1725 sc->sc_paused = 0; 1726 ifp->if_flags &= ~IFF_OACTIVE; 1727 } 1728 } 1729 #endif /* ! DP83820 */ 1730 1731 if (isr & ISR_HIBERR) { 1732 int want_init = 0; 1733 1734 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1735 1736 #define PRINTERR(bit, str) \ 1737 do { \ 1738 if ((isr & (bit)) != 0) { \ 1739 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1740 printf("%s: %s\n", \ 1741 sc->sc_dev.dv_xname, str); \ 1742 want_init = 1; \ 1743 } \ 1744 } while (/*CONSTCOND*/0) 1745 1746 PRINTERR(ISR_DPERR, "parity error"); 1747 PRINTERR(ISR_SSERR, "system error"); 1748 PRINTERR(ISR_RMABT, "master abort"); 1749 PRINTERR(ISR_RTABT, "target abort"); 1750 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1751 /* 1752 * Ignore: 1753 * Tx reset complete 1754 * Rx reset complete 1755 */ 1756 if (want_init) 1757 (void) SIP_DECL(init)(ifp); 1758 #undef PRINTERR 1759 } 1760 } 1761 1762 /* Re-enable interrupts. */ 1763 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1764 1765 /* Try to get more packets going. */ 1766 SIP_DECL(start)(ifp); 1767 1768 return (handled); 1769 } 1770 1771 /* 1772 * sip_txintr: 1773 * 1774 * Helper; handle transmit interrupts. 1775 */ 1776 static void 1777 SIP_DECL(txintr)(struct sip_softc *sc) 1778 { 1779 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1780 struct sip_txsoft *txs; 1781 u_int32_t cmdsts; 1782 1783 #ifndef DP83820 1784 if (sc->sc_paused == 0) 1785 #endif 1786 ifp->if_flags &= ~IFF_OACTIVE; 1787 1788 /* 1789 * Go through our Tx list and free mbufs for those 1790 * frames which have been transmitted. 1791 */ 1792 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1793 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1794 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1795 1796 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1797 if (cmdsts & CMDSTS_OWN) 1798 break; 1799 1800 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1801 1802 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1803 1804 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1805 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1806 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1807 m_freem(txs->txs_mbuf); 1808 txs->txs_mbuf = NULL; 1809 1810 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1811 1812 /* 1813 * Check for errors and collisions. 1814 */ 1815 if (cmdsts & 1816 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1817 ifp->if_oerrors++; 1818 if (cmdsts & CMDSTS_Tx_EC) 1819 ifp->if_collisions += 16; 1820 if (ifp->if_flags & IFF_DEBUG) { 1821 if (cmdsts & CMDSTS_Tx_ED) 1822 printf("%s: excessive deferral\n", 1823 sc->sc_dev.dv_xname); 1824 if (cmdsts & CMDSTS_Tx_EC) 1825 printf("%s: excessive collisions\n", 1826 sc->sc_dev.dv_xname); 1827 } 1828 } else { 1829 /* Packet was transmitted successfully. */ 1830 ifp->if_opackets++; 1831 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1832 } 1833 } 1834 1835 /* 1836 * If there are no more pending transmissions, cancel the watchdog 1837 * timer. 1838 */ 1839 if (txs == NULL) { 1840 ifp->if_timer = 0; 1841 sc->sc_txwin = 0; 1842 } 1843 } 1844 1845 #if defined(DP83820) 1846 /* 1847 * sip_rxintr: 1848 * 1849 * Helper; handle receive interrupts. 1850 */ 1851 static void 1852 SIP_DECL(rxintr)(struct sip_softc *sc) 1853 { 1854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1855 struct sip_rxsoft *rxs; 1856 struct mbuf *m; 1857 u_int32_t cmdsts, extsts; 1858 int i, len; 1859 1860 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1861 rxs = &sc->sc_rxsoft[i]; 1862 1863 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1864 1865 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1866 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1867 len = CMDSTS_SIZE(cmdsts); 1868 1869 /* 1870 * NOTE: OWN is set if owned by _consumer_. We're the 1871 * consumer of the receive ring, so if the bit is clear, 1872 * we have processed all of the packets. 1873 */ 1874 if ((cmdsts & CMDSTS_OWN) == 0) { 1875 /* 1876 * We have processed all of the receive buffers. 1877 */ 1878 break; 1879 } 1880 1881 if (__predict_false(sc->sc_rxdiscard)) { 1882 SIP_INIT_RXDESC(sc, i); 1883 if ((cmdsts & CMDSTS_MORE) == 0) { 1884 /* Reset our state. */ 1885 sc->sc_rxdiscard = 0; 1886 } 1887 continue; 1888 } 1889 1890 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1891 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1892 1893 m = rxs->rxs_mbuf; 1894 1895 /* 1896 * Add a new receive buffer to the ring. 1897 */ 1898 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1899 /* 1900 * Failed, throw away what we've done so 1901 * far, and discard the rest of the packet. 1902 */ 1903 ifp->if_ierrors++; 1904 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1905 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1906 SIP_INIT_RXDESC(sc, i); 1907 if (cmdsts & CMDSTS_MORE) 1908 sc->sc_rxdiscard = 1; 1909 if (sc->sc_rxhead != NULL) 1910 m_freem(sc->sc_rxhead); 1911 SIP_RXCHAIN_RESET(sc); 1912 continue; 1913 } 1914 1915 SIP_RXCHAIN_LINK(sc, m); 1916 1917 m->m_len = len; 1918 1919 /* 1920 * If this is not the end of the packet, keep 1921 * looking. 1922 */ 1923 if (cmdsts & CMDSTS_MORE) { 1924 sc->sc_rxlen += len; 1925 continue; 1926 } 1927 1928 /* 1929 * Okay, we have the entire packet now. The chip includes 1930 * the FCS, so we need to trim it. 1931 */ 1932 m->m_len -= ETHER_CRC_LEN; 1933 1934 *sc->sc_rxtailp = NULL; 1935 len = m->m_len + sc->sc_rxlen; 1936 m = sc->sc_rxhead; 1937 1938 SIP_RXCHAIN_RESET(sc); 1939 1940 /* 1941 * If an error occurred, update stats and drop the packet. 1942 */ 1943 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1944 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1945 ifp->if_ierrors++; 1946 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1947 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1948 /* Receive overrun handled elsewhere. */ 1949 printf("%s: receive descriptor error\n", 1950 sc->sc_dev.dv_xname); 1951 } 1952 #define PRINTERR(bit, str) \ 1953 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1954 (cmdsts & (bit)) != 0) \ 1955 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1956 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1957 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1958 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1959 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1960 #undef PRINTERR 1961 m_freem(m); 1962 continue; 1963 } 1964 1965 /* 1966 * If the packet is small enough to fit in a 1967 * single header mbuf, allocate one and copy 1968 * the data into it. This greatly reduces 1969 * memory consumption when we receive lots 1970 * of small packets. 1971 */ 1972 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1973 struct mbuf *nm; 1974 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1975 if (nm == NULL) { 1976 ifp->if_ierrors++; 1977 m_freem(m); 1978 continue; 1979 } 1980 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1981 nm->m_data += 2; 1982 nm->m_pkthdr.len = nm->m_len = len; 1983 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1984 m_freem(m); 1985 m = nm; 1986 } 1987 #ifndef __NO_STRICT_ALIGNMENT 1988 else { 1989 /* 1990 * The DP83820's receive buffers must be 4-byte 1991 * aligned. But this means that the data after 1992 * the Ethernet header is misaligned. To compensate, 1993 * we have artificially shortened the buffer size 1994 * in the descriptor, and we do an overlapping copy 1995 * of the data two bytes further in (in the first 1996 * buffer of the chain only). 1997 */ 1998 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1999 m->m_len); 2000 m->m_data += 2; 2001 } 2002 #endif /* ! __NO_STRICT_ALIGNMENT */ 2003 2004 /* 2005 * If VLANs are enabled, VLAN packets have been unwrapped 2006 * for us. Associate the tag with the packet. 2007 */ 2008 2009 /* 2010 * Again, byte swapping is tricky. Hardware provided 2011 * the tag in the network byte order, but extsts was 2012 * passed through le32toh() in the meantime. On a 2013 * big-endian machine, we need to swap it again. On a 2014 * little-endian machine, we need to convert from the 2015 * network to host byte order. This means that we must 2016 * swap it in any case, so unconditional swap instead 2017 * of htons() is used. 2018 */ 2019 if ((extsts & EXTSTS_VPKT) != 0) { 2020 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2021 continue); 2022 } 2023 2024 /* 2025 * Set the incoming checksum information for the 2026 * packet. 2027 */ 2028 if ((extsts & EXTSTS_IPPKT) != 0) { 2029 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2030 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2031 if (extsts & EXTSTS_Rx_IPERR) 2032 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2033 if (extsts & EXTSTS_TCPPKT) { 2034 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2035 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2036 if (extsts & EXTSTS_Rx_TCPERR) 2037 m->m_pkthdr.csum_flags |= 2038 M_CSUM_TCP_UDP_BAD; 2039 } else if (extsts & EXTSTS_UDPPKT) { 2040 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2041 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2042 if (extsts & EXTSTS_Rx_UDPERR) 2043 m->m_pkthdr.csum_flags |= 2044 M_CSUM_TCP_UDP_BAD; 2045 } 2046 } 2047 2048 ifp->if_ipackets++; 2049 m->m_pkthdr.rcvif = ifp; 2050 m->m_pkthdr.len = len; 2051 2052 #if NBPFILTER > 0 2053 /* 2054 * Pass this up to any BPF listeners, but only 2055 * pass if up the stack if it's for us. 2056 */ 2057 if (ifp->if_bpf) 2058 bpf_mtap(ifp->if_bpf, m); 2059 #endif /* NBPFILTER > 0 */ 2060 2061 /* Pass it on. */ 2062 (*ifp->if_input)(ifp, m); 2063 } 2064 2065 /* Update the receive pointer. */ 2066 sc->sc_rxptr = i; 2067 } 2068 #else /* ! DP83820 */ 2069 /* 2070 * sip_rxintr: 2071 * 2072 * Helper; handle receive interrupts. 2073 */ 2074 static void 2075 SIP_DECL(rxintr)(struct sip_softc *sc) 2076 { 2077 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2078 struct sip_rxsoft *rxs; 2079 struct mbuf *m; 2080 u_int32_t cmdsts; 2081 int i, len; 2082 2083 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2084 rxs = &sc->sc_rxsoft[i]; 2085 2086 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2087 2088 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2089 2090 /* 2091 * NOTE: OWN is set if owned by _consumer_. We're the 2092 * consumer of the receive ring, so if the bit is clear, 2093 * we have processed all of the packets. 2094 */ 2095 if ((cmdsts & CMDSTS_OWN) == 0) { 2096 /* 2097 * We have processed all of the receive buffers. 2098 */ 2099 break; 2100 } 2101 2102 /* 2103 * If any collisions were seen on the wire, count one. 2104 */ 2105 if (cmdsts & CMDSTS_Rx_COL) 2106 ifp->if_collisions++; 2107 2108 /* 2109 * If an error occurred, update stats, clear the status 2110 * word, and leave the packet buffer in place. It will 2111 * simply be reused the next time the ring comes around. 2112 */ 2113 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2114 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2115 ifp->if_ierrors++; 2116 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2117 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2118 /* Receive overrun handled elsewhere. */ 2119 printf("%s: receive descriptor error\n", 2120 sc->sc_dev.dv_xname); 2121 } 2122 #define PRINTERR(bit, str) \ 2123 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2124 (cmdsts & (bit)) != 0) \ 2125 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2126 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2127 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2128 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2129 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2130 #undef PRINTERR 2131 SIP_INIT_RXDESC(sc, i); 2132 continue; 2133 } 2134 2135 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2136 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2137 2138 /* 2139 * No errors; receive the packet. Note, the SiS 900 2140 * includes the CRC with every packet. 2141 */ 2142 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2143 2144 #ifdef __NO_STRICT_ALIGNMENT 2145 /* 2146 * If the packet is small enough to fit in a 2147 * single header mbuf, allocate one and copy 2148 * the data into it. This greatly reduces 2149 * memory consumption when we receive lots 2150 * of small packets. 2151 * 2152 * Otherwise, we add a new buffer to the receive 2153 * chain. If this fails, we drop the packet and 2154 * recycle the old buffer. 2155 */ 2156 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2157 MGETHDR(m, M_DONTWAIT, MT_DATA); 2158 if (m == NULL) 2159 goto dropit; 2160 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2161 memcpy(mtod(m, caddr_t), 2162 mtod(rxs->rxs_mbuf, caddr_t), len); 2163 SIP_INIT_RXDESC(sc, i); 2164 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2165 rxs->rxs_dmamap->dm_mapsize, 2166 BUS_DMASYNC_PREREAD); 2167 } else { 2168 m = rxs->rxs_mbuf; 2169 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2170 dropit: 2171 ifp->if_ierrors++; 2172 SIP_INIT_RXDESC(sc, i); 2173 bus_dmamap_sync(sc->sc_dmat, 2174 rxs->rxs_dmamap, 0, 2175 rxs->rxs_dmamap->dm_mapsize, 2176 BUS_DMASYNC_PREREAD); 2177 continue; 2178 } 2179 } 2180 #else 2181 /* 2182 * The SiS 900's receive buffers must be 4-byte aligned. 2183 * But this means that the data after the Ethernet header 2184 * is misaligned. We must allocate a new buffer and 2185 * copy the data, shifted forward 2 bytes. 2186 */ 2187 MGETHDR(m, M_DONTWAIT, MT_DATA); 2188 if (m == NULL) { 2189 dropit: 2190 ifp->if_ierrors++; 2191 SIP_INIT_RXDESC(sc, i); 2192 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2193 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2194 continue; 2195 } 2196 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2197 if (len > (MHLEN - 2)) { 2198 MCLGET(m, M_DONTWAIT); 2199 if ((m->m_flags & M_EXT) == 0) { 2200 m_freem(m); 2201 goto dropit; 2202 } 2203 } 2204 m->m_data += 2; 2205 2206 /* 2207 * Note that we use clusters for incoming frames, so the 2208 * buffer is virtually contiguous. 2209 */ 2210 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2211 2212 /* Allow the receive descriptor to continue using its mbuf. */ 2213 SIP_INIT_RXDESC(sc, i); 2214 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2215 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2216 #endif /* __NO_STRICT_ALIGNMENT */ 2217 2218 ifp->if_ipackets++; 2219 m->m_pkthdr.rcvif = ifp; 2220 m->m_pkthdr.len = m->m_len = len; 2221 2222 #if NBPFILTER > 0 2223 /* 2224 * Pass this up to any BPF listeners, but only 2225 * pass if up the stack if it's for us. 2226 */ 2227 if (ifp->if_bpf) 2228 bpf_mtap(ifp->if_bpf, m); 2229 #endif /* NBPFILTER > 0 */ 2230 2231 /* Pass it on. */ 2232 (*ifp->if_input)(ifp, m); 2233 } 2234 2235 /* Update the receive pointer. */ 2236 sc->sc_rxptr = i; 2237 } 2238 #endif /* DP83820 */ 2239 2240 /* 2241 * sip_tick: 2242 * 2243 * One second timer, used to tick the MII. 2244 */ 2245 static void 2246 SIP_DECL(tick)(void *arg) 2247 { 2248 struct sip_softc *sc = arg; 2249 int s; 2250 2251 s = splnet(); 2252 #ifdef DP83820 2253 #ifdef SIP_EVENT_COUNTERS 2254 /* Read PAUSE related counts from MIB registers. */ 2255 sc->sc_ev_rxpause.ev_count += 2256 bus_space_read_4(sc->sc_st, sc->sc_sh, 2257 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2258 sc->sc_ev_txpause.ev_count += 2259 bus_space_read_4(sc->sc_st, sc->sc_sh, 2260 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2261 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2262 #endif /* SIP_EVENT_COUNTERS */ 2263 #endif /* DP83820 */ 2264 mii_tick(&sc->sc_mii); 2265 splx(s); 2266 2267 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2268 } 2269 2270 /* 2271 * sip_reset: 2272 * 2273 * Perform a soft reset on the SiS 900. 2274 */ 2275 static void 2276 SIP_DECL(reset)(struct sip_softc *sc) 2277 { 2278 bus_space_tag_t st = sc->sc_st; 2279 bus_space_handle_t sh = sc->sc_sh; 2280 int i; 2281 2282 bus_space_write_4(st, sh, SIP_IER, 0); 2283 bus_space_write_4(st, sh, SIP_IMR, 0); 2284 bus_space_write_4(st, sh, SIP_RFCR, 0); 2285 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2286 2287 for (i = 0; i < SIP_TIMEOUT; i++) { 2288 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2289 break; 2290 delay(2); 2291 } 2292 2293 if (i == SIP_TIMEOUT) 2294 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2295 2296 delay(1000); 2297 2298 #ifdef DP83820 2299 /* 2300 * Set the general purpose I/O bits. Do it here in case we 2301 * need to have GPIO set up to talk to the media interface. 2302 */ 2303 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2304 delay(1000); 2305 #endif /* DP83820 */ 2306 } 2307 2308 /* 2309 * sip_init: [ ifnet interface function ] 2310 * 2311 * Initialize the interface. Must be called at splnet(). 2312 */ 2313 static int 2314 SIP_DECL(init)(struct ifnet *ifp) 2315 { 2316 struct sip_softc *sc = ifp->if_softc; 2317 bus_space_tag_t st = sc->sc_st; 2318 bus_space_handle_t sh = sc->sc_sh; 2319 struct sip_txsoft *txs; 2320 struct sip_rxsoft *rxs; 2321 struct sip_desc *sipd; 2322 #if defined(DP83820) 2323 u_int32_t reg; 2324 #endif 2325 int i, error = 0; 2326 2327 /* 2328 * Cancel any pending I/O. 2329 */ 2330 SIP_DECL(stop)(ifp, 0); 2331 2332 /* 2333 * Reset the chip to a known state. 2334 */ 2335 SIP_DECL(reset)(sc); 2336 2337 #if !defined(DP83820) 2338 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2339 /* 2340 * DP83815 manual, page 78: 2341 * 4.4 Recommended Registers Configuration 2342 * For optimum performance of the DP83815, version noted 2343 * as DP83815CVNG (SRR = 203h), the listed register 2344 * modifications must be followed in sequence... 2345 * 2346 * It's not clear if this should be 302h or 203h because that 2347 * chip name is listed as SRR 302h in the description of the 2348 * SRR register. However, my revision 302h DP83815 on the 2349 * Netgear FA311 purchased in 02/2001 needs these settings 2350 * to avoid tons of errors in AcceptPerfectMatch (non- 2351 * IFF_PROMISC) mode. I do not know if other revisions need 2352 * this set or not. [briggs -- 09 March 2001] 2353 * 2354 * Note that only the low-order 12 bits of 0xe4 are documented 2355 * and that this sets reserved bits in that register. 2356 */ 2357 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2358 2359 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2360 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2361 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2362 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2363 2364 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2365 } 2366 #endif /* ! DP83820 */ 2367 2368 /* 2369 * Initialize the transmit descriptor ring. 2370 */ 2371 for (i = 0; i < SIP_NTXDESC; i++) { 2372 sipd = &sc->sc_txdescs[i]; 2373 memset(sipd, 0, sizeof(struct sip_desc)); 2374 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2375 } 2376 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2378 sc->sc_txfree = SIP_NTXDESC; 2379 sc->sc_txnext = 0; 2380 sc->sc_txwin = 0; 2381 2382 /* 2383 * Initialize the transmit job descriptors. 2384 */ 2385 SIMPLEQ_INIT(&sc->sc_txfreeq); 2386 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2387 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2388 txs = &sc->sc_txsoft[i]; 2389 txs->txs_mbuf = NULL; 2390 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2391 } 2392 2393 /* 2394 * Initialize the receive descriptor and receive job 2395 * descriptor rings. 2396 */ 2397 for (i = 0; i < SIP_NRXDESC; i++) { 2398 rxs = &sc->sc_rxsoft[i]; 2399 if (rxs->rxs_mbuf == NULL) { 2400 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2401 printf("%s: unable to allocate or map rx " 2402 "buffer %d, error = %d\n", 2403 sc->sc_dev.dv_xname, i, error); 2404 /* 2405 * XXX Should attempt to run with fewer receive 2406 * XXX buffers instead of just failing. 2407 */ 2408 SIP_DECL(rxdrain)(sc); 2409 goto out; 2410 } 2411 } else 2412 SIP_INIT_RXDESC(sc, i); 2413 } 2414 sc->sc_rxptr = 0; 2415 #ifdef DP83820 2416 sc->sc_rxdiscard = 0; 2417 SIP_RXCHAIN_RESET(sc); 2418 #endif /* DP83820 */ 2419 2420 /* 2421 * Set the configuration register; it's already initialized 2422 * in sip_attach(). 2423 */ 2424 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2425 2426 /* 2427 * Initialize the prototype TXCFG register. 2428 */ 2429 #if defined(DP83820) 2430 sc->sc_txcfg = TXCFG_MXDMA_512; 2431 sc->sc_rxcfg = RXCFG_MXDMA_512; 2432 #else 2433 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2434 SIP_SIS900_REV(sc, SIS_REV_960) || 2435 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2436 (sc->sc_cfg & CFG_EDBMASTEN)) { 2437 sc->sc_txcfg = TXCFG_MXDMA_64; 2438 sc->sc_rxcfg = RXCFG_MXDMA_64; 2439 } else { 2440 sc->sc_txcfg = TXCFG_MXDMA_512; 2441 sc->sc_rxcfg = RXCFG_MXDMA_512; 2442 } 2443 #endif /* DP83820 */ 2444 2445 sc->sc_txcfg |= TXCFG_ATP | 2446 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2447 sc->sc_tx_drain_thresh; 2448 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2449 2450 /* 2451 * Initialize the receive drain threshold if we have never 2452 * done so. 2453 */ 2454 if (sc->sc_rx_drain_thresh == 0) { 2455 /* 2456 * XXX This value should be tuned. This is set to the 2457 * maximum of 248 bytes, and we may be able to improve 2458 * performance by decreasing it (although we should never 2459 * set this value lower than 2; 14 bytes are required to 2460 * filter the packet). 2461 */ 2462 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2463 } 2464 2465 /* 2466 * Initialize the prototype RXCFG register. 2467 */ 2468 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2469 #ifdef DP83820 2470 /* 2471 * Accept long packets (including FCS) so we can handle 2472 * 802.1q-tagged frames and jumbo frames properly. 2473 */ 2474 if (ifp->if_mtu > ETHERMTU || 2475 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2476 sc->sc_rxcfg |= RXCFG_ALP; 2477 2478 /* 2479 * Checksum offloading is disabled if the user selects an MTU 2480 * larger than 8109. (FreeBSD says 8152, but there is emperical 2481 * evidence that >8109 does not work on some boards, such as the 2482 * Planex GN-1000TE). 2483 */ 2484 if (ifp->if_mtu > 8109 && 2485 (ifp->if_capenable & 2486 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2487 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2488 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2489 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2490 "disabled.\n", sc->sc_dev.dv_xname); 2491 ifp->if_capenable &= 2492 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2493 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2494 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2495 ifp->if_csum_flags_tx = 0; 2496 ifp->if_csum_flags_rx = 0; 2497 } 2498 #else 2499 /* 2500 * Accept packets >1518 bytes (including FCS) so we can handle 2501 * 802.1q-tagged frames properly. 2502 */ 2503 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2504 sc->sc_rxcfg |= RXCFG_ALP; 2505 #endif 2506 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2507 2508 #ifdef DP83820 2509 /* 2510 * Initialize the VLAN/IP receive control register. 2511 * We enable checksum computation on all incoming 2512 * packets, and do not reject packets w/ bad checksums. 2513 */ 2514 reg = 0; 2515 if (ifp->if_capenable & 2516 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2517 reg |= VRCR_IPEN; 2518 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2519 reg |= VRCR_VTDEN|VRCR_VTREN; 2520 bus_space_write_4(st, sh, SIP_VRCR, reg); 2521 2522 /* 2523 * Initialize the VLAN/IP transmit control register. 2524 * We enable outgoing checksum computation on a 2525 * per-packet basis. 2526 */ 2527 reg = 0; 2528 if (ifp->if_capenable & 2529 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2530 reg |= VTCR_PPCHK; 2531 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2532 reg |= VTCR_VPPTI; 2533 bus_space_write_4(st, sh, SIP_VTCR, reg); 2534 2535 /* 2536 * If we're using VLANs, initialize the VLAN data register. 2537 * To understand why we bswap the VLAN Ethertype, see section 2538 * 4.2.36 of the DP83820 manual. 2539 */ 2540 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2541 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2542 #endif /* DP83820 */ 2543 2544 /* 2545 * Give the transmit and receive rings to the chip. 2546 */ 2547 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2548 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2549 2550 /* 2551 * Initialize the interrupt mask. 2552 */ 2553 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2554 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2555 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2556 2557 /* Set up the receive filter. */ 2558 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2559 2560 #ifdef DP83820 2561 /* 2562 * Tune sc_rx_flow_thresh. 2563 * XXX "More than 8KB" is too short for jumbo frames. 2564 * XXX TODO: Threshold value should be user-settable. 2565 */ 2566 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2567 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2568 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2569 #endif 2570 2571 /* 2572 * Set the current media. Do this after initializing the prototype 2573 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2574 * control. 2575 */ 2576 mii_mediachg(&sc->sc_mii); 2577 2578 #ifdef DP83820 2579 /* 2580 * Set the interrupt hold-off timer to 100us. 2581 */ 2582 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2583 #endif 2584 2585 /* 2586 * Enable interrupts. 2587 */ 2588 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2589 2590 /* 2591 * Start the transmit and receive processes. 2592 */ 2593 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2594 2595 /* 2596 * Start the one second MII clock. 2597 */ 2598 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2599 2600 /* 2601 * ...all done! 2602 */ 2603 ifp->if_flags |= IFF_RUNNING; 2604 ifp->if_flags &= ~IFF_OACTIVE; 2605 sc->sc_if_flags = ifp->if_flags; 2606 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2607 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2608 sc->sc_prev.if_capenable = ifp->if_capenable; 2609 2610 out: 2611 if (error) 2612 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2613 return (error); 2614 } 2615 2616 /* 2617 * sip_drain: 2618 * 2619 * Drain the receive queue. 2620 */ 2621 static void 2622 SIP_DECL(rxdrain)(struct sip_softc *sc) 2623 { 2624 struct sip_rxsoft *rxs; 2625 int i; 2626 2627 for (i = 0; i < SIP_NRXDESC; i++) { 2628 rxs = &sc->sc_rxsoft[i]; 2629 if (rxs->rxs_mbuf != NULL) { 2630 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2631 m_freem(rxs->rxs_mbuf); 2632 rxs->rxs_mbuf = NULL; 2633 } 2634 } 2635 } 2636 2637 /* 2638 * sip_stop: [ ifnet interface function ] 2639 * 2640 * Stop transmission on the interface. 2641 */ 2642 static void 2643 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2644 { 2645 struct sip_softc *sc = ifp->if_softc; 2646 bus_space_tag_t st = sc->sc_st; 2647 bus_space_handle_t sh = sc->sc_sh; 2648 struct sip_txsoft *txs; 2649 u_int32_t cmdsts = 0; /* DEBUG */ 2650 2651 /* 2652 * Stop the one second clock. 2653 */ 2654 callout_stop(&sc->sc_tick_ch); 2655 2656 /* Down the MII. */ 2657 mii_down(&sc->sc_mii); 2658 2659 /* 2660 * Disable interrupts. 2661 */ 2662 bus_space_write_4(st, sh, SIP_IER, 0); 2663 2664 /* 2665 * Stop receiver and transmitter. 2666 */ 2667 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2668 2669 /* 2670 * Release any queued transmit buffers. 2671 */ 2672 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2673 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2674 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2675 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2676 CMDSTS_INTR) == 0) 2677 printf("%s: sip_stop: last descriptor does not " 2678 "have INTR bit set\n", sc->sc_dev.dv_xname); 2679 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2680 #ifdef DIAGNOSTIC 2681 if (txs->txs_mbuf == NULL) { 2682 printf("%s: dirty txsoft with no mbuf chain\n", 2683 sc->sc_dev.dv_xname); 2684 panic("sip_stop"); 2685 } 2686 #endif 2687 cmdsts |= /* DEBUG */ 2688 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2689 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2690 m_freem(txs->txs_mbuf); 2691 txs->txs_mbuf = NULL; 2692 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2693 } 2694 2695 if (disable) 2696 SIP_DECL(rxdrain)(sc); 2697 2698 /* 2699 * Mark the interface down and cancel the watchdog timer. 2700 */ 2701 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2702 ifp->if_timer = 0; 2703 2704 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2705 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2706 printf("%s: sip_stop: no INTR bits set in dirty tx " 2707 "descriptors\n", sc->sc_dev.dv_xname); 2708 } 2709 2710 /* 2711 * sip_read_eeprom: 2712 * 2713 * Read data from the serial EEPROM. 2714 */ 2715 static void 2716 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2717 u_int16_t *data) 2718 { 2719 bus_space_tag_t st = sc->sc_st; 2720 bus_space_handle_t sh = sc->sc_sh; 2721 u_int16_t reg; 2722 int i, x; 2723 2724 for (i = 0; i < wordcnt; i++) { 2725 /* Send CHIP SELECT. */ 2726 reg = EROMAR_EECS; 2727 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2728 2729 /* Shift in the READ opcode. */ 2730 for (x = 3; x > 0; x--) { 2731 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2732 reg |= EROMAR_EEDI; 2733 else 2734 reg &= ~EROMAR_EEDI; 2735 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2736 bus_space_write_4(st, sh, SIP_EROMAR, 2737 reg | EROMAR_EESK); 2738 delay(4); 2739 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2740 delay(4); 2741 } 2742 2743 /* Shift in address. */ 2744 for (x = 6; x > 0; x--) { 2745 if ((word + i) & (1 << (x - 1))) 2746 reg |= EROMAR_EEDI; 2747 else 2748 reg &= ~EROMAR_EEDI; 2749 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2750 bus_space_write_4(st, sh, SIP_EROMAR, 2751 reg | EROMAR_EESK); 2752 delay(4); 2753 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2754 delay(4); 2755 } 2756 2757 /* Shift out data. */ 2758 reg = EROMAR_EECS; 2759 data[i] = 0; 2760 for (x = 16; x > 0; x--) { 2761 bus_space_write_4(st, sh, SIP_EROMAR, 2762 reg | EROMAR_EESK); 2763 delay(4); 2764 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2765 data[i] |= (1 << (x - 1)); 2766 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2767 delay(4); 2768 } 2769 2770 /* Clear CHIP SELECT. */ 2771 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2772 delay(4); 2773 } 2774 } 2775 2776 /* 2777 * sip_add_rxbuf: 2778 * 2779 * Add a receive buffer to the indicated descriptor. 2780 */ 2781 static int 2782 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2783 { 2784 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2785 struct mbuf *m; 2786 int error; 2787 2788 MGETHDR(m, M_DONTWAIT, MT_DATA); 2789 if (m == NULL) 2790 return (ENOBUFS); 2791 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2792 2793 MCLGET(m, M_DONTWAIT); 2794 if ((m->m_flags & M_EXT) == 0) { 2795 m_freem(m); 2796 return (ENOBUFS); 2797 } 2798 2799 #if defined(DP83820) 2800 m->m_len = SIP_RXBUF_LEN; 2801 #endif /* DP83820 */ 2802 2803 if (rxs->rxs_mbuf != NULL) 2804 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2805 2806 rxs->rxs_mbuf = m; 2807 2808 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2809 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2810 BUS_DMA_READ|BUS_DMA_NOWAIT); 2811 if (error) { 2812 printf("%s: can't load rx DMA map %d, error = %d\n", 2813 sc->sc_dev.dv_xname, idx, error); 2814 panic("sip_add_rxbuf"); /* XXX */ 2815 } 2816 2817 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2818 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2819 2820 SIP_INIT_RXDESC(sc, idx); 2821 2822 return (0); 2823 } 2824 2825 #if !defined(DP83820) 2826 /* 2827 * sip_sis900_set_filter: 2828 * 2829 * Set up the receive filter. 2830 */ 2831 static void 2832 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2833 { 2834 bus_space_tag_t st = sc->sc_st; 2835 bus_space_handle_t sh = sc->sc_sh; 2836 struct ethercom *ec = &sc->sc_ethercom; 2837 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2838 struct ether_multi *enm; 2839 u_int8_t *cp; 2840 struct ether_multistep step; 2841 u_int32_t crc, mchash[16]; 2842 2843 /* 2844 * Initialize the prototype RFCR. 2845 */ 2846 sc->sc_rfcr = RFCR_RFEN; 2847 if (ifp->if_flags & IFF_BROADCAST) 2848 sc->sc_rfcr |= RFCR_AAB; 2849 if (ifp->if_flags & IFF_PROMISC) { 2850 sc->sc_rfcr |= RFCR_AAP; 2851 goto allmulti; 2852 } 2853 2854 /* 2855 * Set up the multicast address filter by passing all multicast 2856 * addresses through a CRC generator, and then using the high-order 2857 * 6 bits as an index into the 128 bit multicast hash table (only 2858 * the lower 16 bits of each 32 bit multicast hash register are 2859 * valid). The high order bits select the register, while the 2860 * rest of the bits select the bit within the register. 2861 */ 2862 2863 memset(mchash, 0, sizeof(mchash)); 2864 2865 /* 2866 * SiS900 (at least SiS963) requires us to register the address of 2867 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2868 */ 2869 crc = 0x0ed423f9; 2870 2871 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2872 SIP_SIS900_REV(sc, SIS_REV_960) || 2873 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2874 /* Just want the 8 most significant bits. */ 2875 crc >>= 24; 2876 } else { 2877 /* Just want the 7 most significant bits. */ 2878 crc >>= 25; 2879 } 2880 2881 /* Set the corresponding bit in the hash table. */ 2882 mchash[crc >> 4] |= 1 << (crc & 0xf); 2883 2884 ETHER_FIRST_MULTI(step, ec, enm); 2885 while (enm != NULL) { 2886 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2887 /* 2888 * We must listen to a range of multicast addresses. 2889 * For now, just accept all multicasts, rather than 2890 * trying to set only those filter bits needed to match 2891 * the range. (At this time, the only use of address 2892 * ranges is for IP multicast routing, for which the 2893 * range is big enough to require all bits set.) 2894 */ 2895 goto allmulti; 2896 } 2897 2898 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2899 2900 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2901 SIP_SIS900_REV(sc, SIS_REV_960) || 2902 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2903 /* Just want the 8 most significant bits. */ 2904 crc >>= 24; 2905 } else { 2906 /* Just want the 7 most significant bits. */ 2907 crc >>= 25; 2908 } 2909 2910 /* Set the corresponding bit in the hash table. */ 2911 mchash[crc >> 4] |= 1 << (crc & 0xf); 2912 2913 ETHER_NEXT_MULTI(step, enm); 2914 } 2915 2916 ifp->if_flags &= ~IFF_ALLMULTI; 2917 goto setit; 2918 2919 allmulti: 2920 ifp->if_flags |= IFF_ALLMULTI; 2921 sc->sc_rfcr |= RFCR_AAM; 2922 2923 setit: 2924 #define FILTER_EMIT(addr, data) \ 2925 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2926 delay(1); \ 2927 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2928 delay(1) 2929 2930 /* 2931 * Disable receive filter, and program the node address. 2932 */ 2933 cp = LLADDR(ifp->if_sadl); 2934 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2935 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2936 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2937 2938 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2939 /* 2940 * Program the multicast hash table. 2941 */ 2942 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2943 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2944 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2945 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2946 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2947 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2948 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2949 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2950 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2951 SIP_SIS900_REV(sc, SIS_REV_960) || 2952 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2953 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2954 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2955 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2956 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2957 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2958 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2959 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2960 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2961 } 2962 } 2963 #undef FILTER_EMIT 2964 2965 /* 2966 * Re-enable the receiver filter. 2967 */ 2968 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2969 } 2970 #endif /* ! DP83820 */ 2971 2972 /* 2973 * sip_dp83815_set_filter: 2974 * 2975 * Set up the receive filter. 2976 */ 2977 static void 2978 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2979 { 2980 bus_space_tag_t st = sc->sc_st; 2981 bus_space_handle_t sh = sc->sc_sh; 2982 struct ethercom *ec = &sc->sc_ethercom; 2983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2984 struct ether_multi *enm; 2985 u_int8_t *cp; 2986 struct ether_multistep step; 2987 u_int32_t crc, hash, slot, bit; 2988 #ifdef DP83820 2989 #define MCHASH_NWORDS 128 2990 #else 2991 #define MCHASH_NWORDS 32 2992 #endif /* DP83820 */ 2993 u_int16_t mchash[MCHASH_NWORDS]; 2994 int i; 2995 2996 /* 2997 * Initialize the prototype RFCR. 2998 * Enable the receive filter, and accept on 2999 * Perfect (destination address) Match 3000 * If IFF_BROADCAST, also accept all broadcast packets. 3001 * If IFF_PROMISC, accept all unicast packets (and later, set 3002 * IFF_ALLMULTI and accept all multicast, too). 3003 */ 3004 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3005 if (ifp->if_flags & IFF_BROADCAST) 3006 sc->sc_rfcr |= RFCR_AAB; 3007 if (ifp->if_flags & IFF_PROMISC) { 3008 sc->sc_rfcr |= RFCR_AAP; 3009 goto allmulti; 3010 } 3011 3012 #ifdef DP83820 3013 /* 3014 * Set up the DP83820 multicast address filter by passing all multicast 3015 * addresses through a CRC generator, and then using the high-order 3016 * 11 bits as an index into the 2048 bit multicast hash table. The 3017 * high-order 7 bits select the slot, while the low-order 4 bits 3018 * select the bit within the slot. Note that only the low 16-bits 3019 * of each filter word are used, and there are 128 filter words. 3020 */ 3021 #else 3022 /* 3023 * Set up the DP83815 multicast address filter by passing all multicast 3024 * addresses through a CRC generator, and then using the high-order 3025 * 9 bits as an index into the 512 bit multicast hash table. The 3026 * high-order 5 bits select the slot, while the low-order 4 bits 3027 * select the bit within the slot. Note that only the low 16-bits 3028 * of each filter word are used, and there are 32 filter words. 3029 */ 3030 #endif /* DP83820 */ 3031 3032 memset(mchash, 0, sizeof(mchash)); 3033 3034 ifp->if_flags &= ~IFF_ALLMULTI; 3035 ETHER_FIRST_MULTI(step, ec, enm); 3036 if (enm == NULL) 3037 goto setit; 3038 while (enm != NULL) { 3039 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3040 /* 3041 * We must listen to a range of multicast addresses. 3042 * For now, just accept all multicasts, rather than 3043 * trying to set only those filter bits needed to match 3044 * the range. (At this time, the only use of address 3045 * ranges is for IP multicast routing, for which the 3046 * range is big enough to require all bits set.) 3047 */ 3048 goto allmulti; 3049 } 3050 3051 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3052 3053 #ifdef DP83820 3054 /* Just want the 11 most significant bits. */ 3055 hash = crc >> 21; 3056 #else 3057 /* Just want the 9 most significant bits. */ 3058 hash = crc >> 23; 3059 #endif /* DP83820 */ 3060 3061 slot = hash >> 4; 3062 bit = hash & 0xf; 3063 3064 /* Set the corresponding bit in the hash table. */ 3065 mchash[slot] |= 1 << bit; 3066 3067 ETHER_NEXT_MULTI(step, enm); 3068 } 3069 sc->sc_rfcr |= RFCR_MHEN; 3070 goto setit; 3071 3072 allmulti: 3073 ifp->if_flags |= IFF_ALLMULTI; 3074 sc->sc_rfcr |= RFCR_AAM; 3075 3076 setit: 3077 #define FILTER_EMIT(addr, data) \ 3078 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3079 delay(1); \ 3080 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3081 delay(1) 3082 3083 /* 3084 * Disable receive filter, and program the node address. 3085 */ 3086 cp = LLADDR(ifp->if_sadl); 3087 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3088 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3089 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3090 3091 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3092 /* 3093 * Program the multicast hash table. 3094 */ 3095 for (i = 0; i < MCHASH_NWORDS; i++) { 3096 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3097 mchash[i]); 3098 } 3099 } 3100 #undef FILTER_EMIT 3101 #undef MCHASH_NWORDS 3102 3103 /* 3104 * Re-enable the receiver filter. 3105 */ 3106 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3107 } 3108 3109 #if defined(DP83820) 3110 /* 3111 * sip_dp83820_mii_readreg: [mii interface function] 3112 * 3113 * Read a PHY register on the MII of the DP83820. 3114 */ 3115 static int 3116 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3117 { 3118 struct sip_softc *sc = (void *) self; 3119 3120 if (sc->sc_cfg & CFG_TBI_EN) { 3121 bus_addr_t tbireg; 3122 int rv; 3123 3124 if (phy != 0) 3125 return (0); 3126 3127 switch (reg) { 3128 case MII_BMCR: tbireg = SIP_TBICR; break; 3129 case MII_BMSR: tbireg = SIP_TBISR; break; 3130 case MII_ANAR: tbireg = SIP_TANAR; break; 3131 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3132 case MII_ANER: tbireg = SIP_TANER; break; 3133 case MII_EXTSR: 3134 /* 3135 * Don't even bother reading the TESR register. 3136 * The manual documents that the device has 3137 * 1000baseX full/half capability, but the 3138 * register itself seems read back 0 on some 3139 * boards. Just hard-code the result. 3140 */ 3141 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3142 3143 default: 3144 return (0); 3145 } 3146 3147 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3148 if (tbireg == SIP_TBISR) { 3149 /* LINK and ACOMP are switched! */ 3150 int val = rv; 3151 3152 rv = 0; 3153 if (val & TBISR_MR_LINK_STATUS) 3154 rv |= BMSR_LINK; 3155 if (val & TBISR_MR_AN_COMPLETE) 3156 rv |= BMSR_ACOMP; 3157 3158 /* 3159 * The manual claims this register reads back 0 3160 * on hard and soft reset. But we want to let 3161 * the gentbi driver know that we support auto- 3162 * negotiation, so hard-code this bit in the 3163 * result. 3164 */ 3165 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3166 } 3167 3168 return (rv); 3169 } 3170 3171 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3172 phy, reg)); 3173 } 3174 3175 /* 3176 * sip_dp83820_mii_writereg: [mii interface function] 3177 * 3178 * Write a PHY register on the MII of the DP83820. 3179 */ 3180 static void 3181 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3182 { 3183 struct sip_softc *sc = (void *) self; 3184 3185 if (sc->sc_cfg & CFG_TBI_EN) { 3186 bus_addr_t tbireg; 3187 3188 if (phy != 0) 3189 return; 3190 3191 switch (reg) { 3192 case MII_BMCR: tbireg = SIP_TBICR; break; 3193 case MII_ANAR: tbireg = SIP_TANAR; break; 3194 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3195 default: 3196 return; 3197 } 3198 3199 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3200 return; 3201 } 3202 3203 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3204 phy, reg, val); 3205 } 3206 3207 /* 3208 * sip_dp83820_mii_statchg: [mii interface function] 3209 * 3210 * Callback from MII layer when media changes. 3211 */ 3212 static void 3213 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3214 { 3215 struct sip_softc *sc = (struct sip_softc *) self; 3216 struct mii_data *mii = &sc->sc_mii; 3217 u_int32_t cfg, pcr; 3218 3219 /* 3220 * Get flow control negotiation result. 3221 */ 3222 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3223 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3224 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3225 mii->mii_media_active &= ~IFM_ETH_FMASK; 3226 } 3227 3228 /* 3229 * Update TXCFG for full-duplex operation. 3230 */ 3231 if ((mii->mii_media_active & IFM_FDX) != 0) 3232 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3233 else 3234 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3235 3236 /* 3237 * Update RXCFG for full-duplex or loopback. 3238 */ 3239 if ((mii->mii_media_active & IFM_FDX) != 0 || 3240 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3241 sc->sc_rxcfg |= RXCFG_ATX; 3242 else 3243 sc->sc_rxcfg &= ~RXCFG_ATX; 3244 3245 /* 3246 * Update CFG for MII/GMII. 3247 */ 3248 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3249 cfg = sc->sc_cfg | CFG_MODE_1000; 3250 else 3251 cfg = sc->sc_cfg; 3252 3253 /* 3254 * 802.3x flow control. 3255 */ 3256 pcr = 0; 3257 if (sc->sc_flowflags & IFM_FLOW) { 3258 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3259 pcr |= sc->sc_rx_flow_thresh; 3260 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3261 pcr |= PCR_PSEN | PCR_PS_MCAST; 3262 } 3263 3264 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3265 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3266 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3267 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3268 } 3269 #endif /* ! DP83820 */ 3270 3271 /* 3272 * sip_mii_bitbang_read: [mii bit-bang interface function] 3273 * 3274 * Read the MII serial port for the MII bit-bang module. 3275 */ 3276 static u_int32_t 3277 SIP_DECL(mii_bitbang_read)(struct device *self) 3278 { 3279 struct sip_softc *sc = (void *) self; 3280 3281 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3282 } 3283 3284 /* 3285 * sip_mii_bitbang_write: [mii big-bang interface function] 3286 * 3287 * Write the MII serial port for the MII bit-bang module. 3288 */ 3289 static void 3290 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3291 { 3292 struct sip_softc *sc = (void *) self; 3293 3294 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3295 } 3296 3297 #ifndef DP83820 3298 /* 3299 * sip_sis900_mii_readreg: [mii interface function] 3300 * 3301 * Read a PHY register on the MII. 3302 */ 3303 static int 3304 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3305 { 3306 struct sip_softc *sc = (struct sip_softc *) self; 3307 u_int32_t enphy; 3308 3309 /* 3310 * The PHY of recent SiS chipsets is accessed through bitbang 3311 * operations. 3312 */ 3313 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3314 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3315 phy, reg)); 3316 3317 #ifndef SIS900_MII_RESTRICT 3318 /* 3319 * The SiS 900 has only an internal PHY on the MII. Only allow 3320 * MII address 0. 3321 */ 3322 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3323 return (0); 3324 #endif 3325 3326 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3327 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3328 ENPHY_RWCMD | ENPHY_ACCESS); 3329 do { 3330 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3331 } while (enphy & ENPHY_ACCESS); 3332 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3333 } 3334 3335 /* 3336 * sip_sis900_mii_writereg: [mii interface function] 3337 * 3338 * Write a PHY register on the MII. 3339 */ 3340 static void 3341 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3342 { 3343 struct sip_softc *sc = (struct sip_softc *) self; 3344 u_int32_t enphy; 3345 3346 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3347 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3348 phy, reg, val); 3349 return; 3350 } 3351 3352 #ifndef SIS900_MII_RESTRICT 3353 /* 3354 * The SiS 900 has only an internal PHY on the MII. Only allow 3355 * MII address 0. 3356 */ 3357 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3358 return; 3359 #endif 3360 3361 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3362 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3363 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3364 do { 3365 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3366 } while (enphy & ENPHY_ACCESS); 3367 } 3368 3369 /* 3370 * sip_sis900_mii_statchg: [mii interface function] 3371 * 3372 * Callback from MII layer when media changes. 3373 */ 3374 static void 3375 SIP_DECL(sis900_mii_statchg)(struct device *self) 3376 { 3377 struct sip_softc *sc = (struct sip_softc *) self; 3378 struct mii_data *mii = &sc->sc_mii; 3379 u_int32_t flowctl; 3380 3381 /* 3382 * Get flow control negotiation result. 3383 */ 3384 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3385 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3386 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3387 mii->mii_media_active &= ~IFM_ETH_FMASK; 3388 } 3389 3390 /* 3391 * Update TXCFG for full-duplex operation. 3392 */ 3393 if ((mii->mii_media_active & IFM_FDX) != 0) 3394 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3395 else 3396 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3397 3398 /* 3399 * Update RXCFG for full-duplex or loopback. 3400 */ 3401 if ((mii->mii_media_active & IFM_FDX) != 0 || 3402 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3403 sc->sc_rxcfg |= RXCFG_ATX; 3404 else 3405 sc->sc_rxcfg &= ~RXCFG_ATX; 3406 3407 /* 3408 * Update IMR for use of 802.3x flow control. 3409 */ 3410 if (sc->sc_flowflags & IFM_FLOW) { 3411 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3412 flowctl = FLOWCTL_FLOWEN; 3413 } else { 3414 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3415 flowctl = 0; 3416 } 3417 3418 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3419 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3420 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3422 } 3423 3424 /* 3425 * sip_dp83815_mii_readreg: [mii interface function] 3426 * 3427 * Read a PHY register on the MII. 3428 */ 3429 static int 3430 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3431 { 3432 struct sip_softc *sc = (struct sip_softc *) self; 3433 u_int32_t val; 3434 3435 /* 3436 * The DP83815 only has an internal PHY. Only allow 3437 * MII address 0. 3438 */ 3439 if (phy != 0) 3440 return (0); 3441 3442 /* 3443 * Apparently, after a reset, the DP83815 can take a while 3444 * to respond. During this recovery period, the BMSR returns 3445 * a value of 0. Catch this -- it's not supposed to happen 3446 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3447 * PHY to come back to life. 3448 * 3449 * This works out because the BMSR is the first register 3450 * read during the PHY probe process. 3451 */ 3452 do { 3453 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3454 } while (reg == MII_BMSR && val == 0); 3455 3456 return (val & 0xffff); 3457 } 3458 3459 /* 3460 * sip_dp83815_mii_writereg: [mii interface function] 3461 * 3462 * Write a PHY register to the MII. 3463 */ 3464 static void 3465 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3466 { 3467 struct sip_softc *sc = (struct sip_softc *) self; 3468 3469 /* 3470 * The DP83815 only has an internal PHY. Only allow 3471 * MII address 0. 3472 */ 3473 if (phy != 0) 3474 return; 3475 3476 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3477 } 3478 3479 /* 3480 * sip_dp83815_mii_statchg: [mii interface function] 3481 * 3482 * Callback from MII layer when media changes. 3483 */ 3484 static void 3485 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3486 { 3487 struct sip_softc *sc = (struct sip_softc *) self; 3488 3489 /* 3490 * Update TXCFG for full-duplex operation. 3491 */ 3492 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3493 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3494 else 3495 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3496 3497 /* 3498 * Update RXCFG for full-duplex or loopback. 3499 */ 3500 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3501 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3502 sc->sc_rxcfg |= RXCFG_ATX; 3503 else 3504 sc->sc_rxcfg &= ~RXCFG_ATX; 3505 3506 /* 3507 * XXX 802.3x flow control. 3508 */ 3509 3510 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3511 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3512 3513 /* 3514 * Some DP83815s experience problems when used with short 3515 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3516 * sequence adjusts the DSP's signal attenuation to fix the 3517 * problem. 3518 */ 3519 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3520 uint32_t reg; 3521 3522 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3523 3524 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3525 reg &= 0x0fff; 3526 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3527 delay(100); 3528 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3529 reg &= 0x00ff; 3530 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3531 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3532 0x00e8); 3533 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3534 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3535 reg | 0x20); 3536 } 3537 3538 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3539 } 3540 } 3541 #endif /* DP83820 */ 3542 3543 #if defined(DP83820) 3544 static void 3545 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3546 const struct pci_attach_args *pa, u_int8_t *enaddr) 3547 { 3548 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3549 u_int8_t cksum, *e, match; 3550 int i; 3551 3552 /* 3553 * EEPROM data format for the DP83820 can be found in 3554 * the DP83820 manual, section 4.2.4. 3555 */ 3556 3557 SIP_DECL(read_eeprom)(sc, 0, 3558 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3559 3560 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3561 match = ~(match - 1); 3562 3563 cksum = 0x55; 3564 e = (u_int8_t *) eeprom_data; 3565 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3566 cksum += *e++; 3567 3568 if (cksum != match) 3569 printf("%s: Checksum (%x) mismatch (%x)", 3570 sc->sc_dev.dv_xname, cksum, match); 3571 3572 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3573 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3574 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3575 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3576 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3577 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3578 } 3579 #else /* ! DP83820 */ 3580 static void 3581 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3582 { 3583 int i; 3584 3585 /* 3586 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3587 * a reason, but I don't know it. 3588 */ 3589 for (i = 0; i < 10; i++) 3590 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3591 } 3592 3593 static void 3594 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3595 const struct pci_attach_args *pa, u_int8_t *enaddr) 3596 { 3597 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3598 3599 switch (sc->sc_rev) { 3600 case SIS_REV_630S: 3601 case SIS_REV_630E: 3602 case SIS_REV_630EA1: 3603 case SIS_REV_630ET: 3604 case SIS_REV_635: 3605 /* 3606 * The MAC address for the on-board Ethernet of 3607 * the SiS 630 chipset is in the NVRAM. Kick 3608 * the chip into re-loading it from NVRAM, and 3609 * read the MAC address out of the filter registers. 3610 */ 3611 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3612 3613 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3614 RFCR_RFADDR_NODE0); 3615 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3616 0xffff; 3617 3618 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3619 RFCR_RFADDR_NODE2); 3620 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3621 0xffff; 3622 3623 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3624 RFCR_RFADDR_NODE4); 3625 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3626 0xffff; 3627 break; 3628 3629 case SIS_REV_960: 3630 { 3631 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3632 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3633 3634 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3635 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3636 3637 int waittime, i; 3638 3639 /* Allow to read EEPROM from LAN. It is shared 3640 * between a 1394 controller and the NIC and each 3641 * time we access it, we need to set SIS_EECMD_REQ. 3642 */ 3643 SIS_SET_EROMAR(sc, EROMAR_REQ); 3644 3645 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3646 /* Force EEPROM to idle state. */ 3647 3648 /* 3649 * XXX-cube This is ugly. I'll look for docs about it. 3650 */ 3651 SIS_SET_EROMAR(sc, EROMAR_EECS); 3652 SIP_DECL(sis900_eeprom_delay)(sc); 3653 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3654 SIS_SET_EROMAR(sc, EROMAR_EESK); 3655 SIP_DECL(sis900_eeprom_delay)(sc); 3656 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3657 SIP_DECL(sis900_eeprom_delay)(sc); 3658 } 3659 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3660 SIP_DECL(sis900_eeprom_delay)(sc); 3661 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3662 3663 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3664 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3665 sizeof(myea) / sizeof(myea[0]), myea); 3666 break; 3667 } 3668 DELAY(1); 3669 } 3670 3671 /* 3672 * Set SIS_EECTL_CLK to high, so a other master 3673 * can operate on the i2c bus. 3674 */ 3675 SIS_SET_EROMAR(sc, EROMAR_EESK); 3676 3677 /* Refuse EEPROM access by LAN */ 3678 SIS_SET_EROMAR(sc, EROMAR_DONE); 3679 } break; 3680 3681 default: 3682 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3683 sizeof(myea) / sizeof(myea[0]), myea); 3684 } 3685 3686 enaddr[0] = myea[0] & 0xff; 3687 enaddr[1] = myea[0] >> 8; 3688 enaddr[2] = myea[1] & 0xff; 3689 enaddr[3] = myea[1] >> 8; 3690 enaddr[4] = myea[2] & 0xff; 3691 enaddr[5] = myea[2] >> 8; 3692 } 3693 3694 /* Table and macro to bit-reverse an octet. */ 3695 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3696 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3697 3698 static void 3699 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3700 const struct pci_attach_args *pa, u_int8_t *enaddr) 3701 { 3702 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3703 u_int8_t cksum, *e, match; 3704 int i; 3705 3706 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3707 sizeof(eeprom_data[0]), eeprom_data); 3708 3709 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3710 match = ~(match - 1); 3711 3712 cksum = 0x55; 3713 e = (u_int8_t *) eeprom_data; 3714 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3715 cksum += *e++; 3716 } 3717 if (cksum != match) { 3718 printf("%s: Checksum (%x) mismatch (%x)", 3719 sc->sc_dev.dv_xname, cksum, match); 3720 } 3721 3722 /* 3723 * Unrolled because it makes slightly more sense this way. 3724 * The DP83815 stores the MAC address in bit 0 of word 6 3725 * through bit 15 of word 8. 3726 */ 3727 ea = &eeprom_data[6]; 3728 enaddr[0] = ((*ea & 0x1) << 7); 3729 ea++; 3730 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3731 enaddr[1] = ((*ea & 0x1FE) >> 1); 3732 enaddr[2] = ((*ea & 0x1) << 7); 3733 ea++; 3734 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3735 enaddr[3] = ((*ea & 0x1FE) >> 1); 3736 enaddr[4] = ((*ea & 0x1) << 7); 3737 ea++; 3738 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3739 enaddr[5] = ((*ea & 0x1FE) >> 1); 3740 3741 /* 3742 * In case that's not weird enough, we also need to reverse 3743 * the bits in each byte. This all actually makes more sense 3744 * if you think about the EEPROM storage as an array of bits 3745 * being shifted into bytes, but that's not how we're looking 3746 * at it here... 3747 */ 3748 for (i = 0; i < 6 ;i++) 3749 enaddr[i] = bbr(enaddr[i]); 3750 } 3751 #endif /* DP83820 */ 3752 3753 /* 3754 * sip_mediastatus: [ifmedia interface function] 3755 * 3756 * Get the current interface media status. 3757 */ 3758 static void 3759 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3760 { 3761 struct sip_softc *sc = ifp->if_softc; 3762 3763 mii_pollstat(&sc->sc_mii); 3764 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3765 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3766 sc->sc_flowflags; 3767 } 3768 3769 /* 3770 * sip_mediachange: [ifmedia interface function] 3771 * 3772 * Set hardware to newly-selected media. 3773 */ 3774 static int 3775 SIP_DECL(mediachange)(struct ifnet *ifp) 3776 { 3777 struct sip_softc *sc = ifp->if_softc; 3778 3779 if (ifp->if_flags & IFF_UP) 3780 mii_mediachg(&sc->sc_mii); 3781 return (0); 3782 } 3783
Indexes created Tue Sep 30 11:09:46 GMT 2025