if_sip.c revision 1.104
1 /* $NetBSD: if_sip.c,v 1.104 2006/02/07 06:20:04 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.104 2006/02/07 06:20:04 thorpej Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 short sc_if_flags; 313 314 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 315 #if defined(DP83820) 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 #endif /* DP83820 */ 322 323 #if NRND > 0 324 rndsource_element_t rnd_source; /* random source */ 325 #endif 326 }; 327 328 #ifdef DP83820 329 #define SIP_RXCHAIN_RESET(sc) \ 330 do { \ 331 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 332 *(sc)->sc_rxtailp = NULL; \ 333 (sc)->sc_rxlen = 0; \ 334 } while (/*CONSTCOND*/0) 335 336 #define SIP_RXCHAIN_LINK(sc, m) \ 337 do { \ 338 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 339 (sc)->sc_rxtailp = &(m)->m_next; \ 340 } while (/*CONSTCOND*/0) 341 #endif /* DP83820 */ 342 343 #ifdef SIP_EVENT_COUNTERS 344 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 345 #else 346 #define SIP_EVCNT_INCR(ev) /* nothing */ 347 #endif 348 349 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 350 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 351 352 #define SIP_CDTXSYNC(sc, x, n, ops) \ 353 do { \ 354 int __x, __n; \ 355 \ 356 __x = (x); \ 357 __n = (n); \ 358 \ 359 /* If it will wrap around, sync to the end of the ring. */ \ 360 if ((__x + __n) > SIP_NTXDESC) { \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 363 (SIP_NTXDESC - __x), (ops)); \ 364 __n -= (SIP_NTXDESC - __x); \ 365 __x = 0; \ 366 } \ 367 \ 368 /* Now sync whatever is left. */ \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 371 } while (0) 372 373 #define SIP_CDRXSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 376 377 #ifdef DP83820 378 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 379 #define SIP_RXBUF_LEN (MCLBYTES - 8) 380 #else 381 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 382 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 383 #endif 384 #define SIP_INIT_RXDESC(sc, x) \ 385 do { \ 386 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 387 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 388 \ 389 __sipd->sipd_link = \ 390 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 391 __sipd->sipd_bufptr = \ 392 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 393 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 394 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 395 SIP_INIT_RXDESC_EXTSTS \ 396 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 397 } while (0) 398 399 #define SIP_CHIP_VERS(sc, v, p, r) \ 400 ((sc)->sc_model->sip_vendor == (v) && \ 401 (sc)->sc_model->sip_product == (p) && \ 402 (sc)->sc_rev == (r)) 403 404 #define SIP_CHIP_MODEL(sc, v, p) \ 405 ((sc)->sc_model->sip_vendor == (v) && \ 406 (sc)->sc_model->sip_product == (p)) 407 408 #if !defined(DP83820) 409 #define SIP_SIS900_REV(sc, rev) \ 410 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 411 #endif 412 413 #define SIP_TIMEOUT 1000 414 415 static void SIP_DECL(start)(struct ifnet *); 416 static void SIP_DECL(watchdog)(struct ifnet *); 417 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 418 static int SIP_DECL(init)(struct ifnet *); 419 static void SIP_DECL(stop)(struct ifnet *, int); 420 421 static void SIP_DECL(shutdown)(void *); 422 423 static void SIP_DECL(reset)(struct sip_softc *); 424 static void SIP_DECL(rxdrain)(struct sip_softc *); 425 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 426 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 427 u_int16_t *); 428 static void SIP_DECL(tick)(void *); 429 430 #if !defined(DP83820) 431 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 432 #endif /* ! DP83820 */ 433 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 434 435 #if defined(DP83820) 436 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 437 const struct pci_attach_args *, u_int8_t *); 438 #else 439 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 440 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 #endif /* DP83820 */ 445 446 static int SIP_DECL(intr)(void *); 447 static void SIP_DECL(txintr)(struct sip_softc *); 448 static void SIP_DECL(rxintr)(struct sip_softc *); 449 450 #if defined(DP83820) 451 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 452 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 453 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 454 #else 455 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 456 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 457 static void SIP_DECL(sis900_mii_statchg)(struct device *); 458 459 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 460 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 461 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 462 #endif /* DP83820 */ 463 464 static int SIP_DECL(mediachange)(struct ifnet *); 465 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 466 467 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 468 static void SIP_DECL(attach)(struct device *, struct device *, void *); 469 470 int SIP_DECL(copy_small) = 0; 471 472 #ifdef DP83820 473 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 474 gsip_match, gsip_attach, NULL, NULL); 475 #else 476 CFATTACH_DECL(sip, sizeof(struct sip_softc), 477 sip_match, sip_attach, NULL, NULL); 478 #endif 479 480 /* 481 * Descriptions of the variants of the SiS900. 482 */ 483 struct sip_variant { 484 int (*sipv_mii_readreg)(struct device *, int, int); 485 void (*sipv_mii_writereg)(struct device *, int, int, int); 486 void (*sipv_mii_statchg)(struct device *); 487 void (*sipv_set_filter)(struct sip_softc *); 488 void (*sipv_read_macaddr)(struct sip_softc *, 489 const struct pci_attach_args *, u_int8_t *); 490 }; 491 492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 493 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 494 495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 496 SIP_DECL(mii_bitbang_read), 497 SIP_DECL(mii_bitbang_write), 498 { 499 EROMAR_MDIO, /* MII_BIT_MDO */ 500 EROMAR_MDIO, /* MII_BIT_MDI */ 501 EROMAR_MDC, /* MII_BIT_MDC */ 502 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 503 0, /* MII_BIT_DIR_PHY_HOST */ 504 } 505 }; 506 507 #if defined(DP83820) 508 static const struct sip_variant SIP_DECL(variant_dp83820) = { 509 SIP_DECL(dp83820_mii_readreg), 510 SIP_DECL(dp83820_mii_writereg), 511 SIP_DECL(dp83820_mii_statchg), 512 SIP_DECL(dp83815_set_filter), 513 SIP_DECL(dp83820_read_macaddr), 514 }; 515 #else 516 static const struct sip_variant SIP_DECL(variant_sis900) = { 517 SIP_DECL(sis900_mii_readreg), 518 SIP_DECL(sis900_mii_writereg), 519 SIP_DECL(sis900_mii_statchg), 520 SIP_DECL(sis900_set_filter), 521 SIP_DECL(sis900_read_macaddr), 522 }; 523 524 static const struct sip_variant SIP_DECL(variant_dp83815) = { 525 SIP_DECL(dp83815_mii_readreg), 526 SIP_DECL(dp83815_mii_writereg), 527 SIP_DECL(dp83815_mii_statchg), 528 SIP_DECL(dp83815_set_filter), 529 SIP_DECL(dp83815_read_macaddr), 530 }; 531 #endif /* DP83820 */ 532 533 /* 534 * Devices supported by this driver. 535 */ 536 static const struct sip_product { 537 pci_vendor_id_t sip_vendor; 538 pci_product_id_t sip_product; 539 const char *sip_name; 540 const struct sip_variant *sip_variant; 541 } SIP_DECL(products)[] = { 542 #if defined(DP83820) 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 544 "NatSemi DP83820 Gigabit Ethernet", 545 &SIP_DECL(variant_dp83820) }, 546 #else 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 548 "SiS 900 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 551 "SiS 7016 10/100 Ethernet", 552 &SIP_DECL(variant_sis900) }, 553 554 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 555 "NatSemi DP83815 10/100 Ethernet", 556 &SIP_DECL(variant_dp83815) }, 557 #endif /* DP83820 */ 558 559 { 0, 0, 560 NULL, 561 NULL }, 562 }; 563 564 static const struct sip_product * 565 SIP_DECL(lookup)(const struct pci_attach_args *pa) 566 { 567 const struct sip_product *sip; 568 569 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 570 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 571 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 572 return (sip); 573 } 574 return (NULL); 575 } 576 577 #ifdef DP83820 578 /* 579 * I really hate stupid hardware vendors. There's a bit in the EEPROM 580 * which indicates if the card can do 64-bit data transfers. Unfortunately, 581 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 582 * which means we try to use 64-bit data transfers on those cards if we 583 * happen to be plugged into a 32-bit slot. 584 * 585 * What we do is use this table of cards known to be 64-bit cards. If 586 * you have a 64-bit card who's subsystem ID is not listed in this table, 587 * send the output of "pcictl dump ..." of the device to me so that your 588 * card will use the 64-bit data path when plugged into a 64-bit slot. 589 * 590 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 591 * June 30, 2002 592 */ 593 static int 594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 595 { 596 static const struct { 597 pci_vendor_id_t c64_vendor; 598 pci_product_id_t c64_product; 599 } card64[] = { 600 /* Asante GigaNIX */ 601 { 0x128a, 0x0002 }, 602 603 /* Accton EN1407-T, Planex GN-1000TE */ 604 { 0x1113, 0x1407 }, 605 606 /* Netgear GA-621 */ 607 { 0x1385, 0x621a }, 608 609 /* SMC EZ Card */ 610 { 0x10b8, 0x9462 }, 611 612 { 0, 0} 613 }; 614 pcireg_t subsys; 615 int i; 616 617 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 618 619 for (i = 0; card64[i].c64_vendor != 0; i++) { 620 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 621 PCI_PRODUCT(subsys) == card64[i].c64_product) 622 return (1); 623 } 624 625 return (0); 626 } 627 #endif /* DP83820 */ 628 629 static int 630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 631 { 632 struct pci_attach_args *pa = aux; 633 634 if (SIP_DECL(lookup)(pa) != NULL) 635 return (1); 636 637 return (0); 638 } 639 640 static void 641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 642 { 643 struct sip_softc *sc = (struct sip_softc *) self; 644 struct pci_attach_args *pa = aux; 645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 646 pci_chipset_tag_t pc = pa->pa_pc; 647 pci_intr_handle_t ih; 648 const char *intrstr = NULL; 649 bus_space_tag_t iot, memt; 650 bus_space_handle_t ioh, memh; 651 bus_dma_segment_t seg; 652 int ioh_valid, memh_valid; 653 int i, rseg, error; 654 const struct sip_product *sip; 655 pcireg_t pmode; 656 u_int8_t enaddr[ETHER_ADDR_LEN]; 657 int pmreg; 658 #ifdef DP83820 659 pcireg_t memtype; 660 u_int32_t reg; 661 #endif /* DP83820 */ 662 663 callout_init(&sc->sc_tick_ch); 664 665 sip = SIP_DECL(lookup)(pa); 666 if (sip == NULL) { 667 printf("\n"); 668 panic(SIP_STR(attach) ": impossible"); 669 } 670 sc->sc_rev = PCI_REVISION(pa->pa_class); 671 672 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 673 674 sc->sc_model = sip; 675 676 /* 677 * XXX Work-around broken PXE firmware on some boards. 678 * 679 * The DP83815 shares an address decoder with the MEM BAR 680 * and the ROM BAR. Make sure the ROM BAR is disabled, 681 * so that memory mapped access works. 682 */ 683 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 684 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 685 ~PCI_MAPREG_ROM_ENABLE); 686 687 /* 688 * Map the device. 689 */ 690 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 691 PCI_MAPREG_TYPE_IO, 0, 692 &iot, &ioh, NULL, NULL) == 0); 693 #ifdef DP83820 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 695 switch (memtype) { 696 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 697 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 698 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 699 memtype, 0, &memt, &memh, NULL, NULL) == 0); 700 break; 701 default: 702 memh_valid = 0; 703 } 704 #else 705 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 706 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 707 &memt, &memh, NULL, NULL) == 0); 708 #endif /* DP83820 */ 709 710 if (memh_valid) { 711 sc->sc_st = memt; 712 sc->sc_sh = memh; 713 } else if (ioh_valid) { 714 sc->sc_st = iot; 715 sc->sc_sh = ioh; 716 } else { 717 printf("%s: unable to map device registers\n", 718 sc->sc_dev.dv_xname); 719 return; 720 } 721 722 sc->sc_dmat = pa->pa_dmat; 723 724 /* 725 * Make sure bus mastering is enabled. Also make sure 726 * Write/Invalidate is enabled if we're allowed to use it. 727 */ 728 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 729 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 730 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 732 pmreg | PCI_COMMAND_MASTER_ENABLE); 733 734 /* Get it out of power save mode if needed. */ 735 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 736 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 737 PCI_PMCSR_STATE_MASK; 738 if (pmode == PCI_PMCSR_STATE_D3) { 739 /* 740 * The card has lost all configuration data in 741 * this state, so punt. 742 */ 743 printf("%s: unable to wake up from power state D3\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (pmode != PCI_PMCSR_STATE_D0) { 748 printf("%s: waking up from power state D%d\n", 749 sc->sc_dev.dv_xname, pmode); 750 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 751 PCI_PMCSR_STATE_D0); 752 } 753 } 754 755 /* 756 * Map and establish our interrupt. 757 */ 758 if (pci_intr_map(pa, &ih)) { 759 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 764 if (sc->sc_ih == NULL) { 765 printf("%s: unable to establish interrupt", 766 sc->sc_dev.dv_xname); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 return; 771 } 772 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 773 774 SIMPLEQ_INIT(&sc->sc_txfreeq); 775 SIMPLEQ_INIT(&sc->sc_txdirtyq); 776 777 /* 778 * Allocate the control data structures, and create and load the 779 * DMA map for it. 780 */ 781 if ((error = bus_dmamem_alloc(sc->sc_dmat, 782 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 783 0)) != 0) { 784 printf("%s: unable to allocate control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_0; 787 } 788 789 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 790 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 791 BUS_DMA_COHERENT)) != 0) { 792 printf("%s: unable to map control data, error = %d\n", 793 sc->sc_dev.dv_xname, error); 794 goto fail_1; 795 } 796 797 if ((error = bus_dmamap_create(sc->sc_dmat, 798 sizeof(struct sip_control_data), 1, 799 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 800 printf("%s: unable to create control data DMA map, " 801 "error = %d\n", sc->sc_dev.dv_xname, error); 802 goto fail_2; 803 } 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 806 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 807 0)) != 0) { 808 printf("%s: unable to load control data DMA map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 goto fail_3; 811 } 812 813 /* 814 * Create the transmit buffer DMA maps. 815 */ 816 for (i = 0; i < SIP_TXQUEUELEN; i++) { 817 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 818 SIP_NTXSEGS, MCLBYTES, 0, 0, 819 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 820 printf("%s: unable to create tx DMA map %d, " 821 "error = %d\n", sc->sc_dev.dv_xname, i, error); 822 goto fail_4; 823 } 824 } 825 826 /* 827 * Create the receive buffer DMA maps. 828 */ 829 for (i = 0; i < SIP_NRXDESC; i++) { 830 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 831 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 832 printf("%s: unable to create rx DMA map %d, " 833 "error = %d\n", sc->sc_dev.dv_xname, i, error); 834 goto fail_5; 835 } 836 sc->sc_rxsoft[i].rxs_mbuf = NULL; 837 } 838 839 /* 840 * Reset the chip to a known state. 841 */ 842 SIP_DECL(reset)(sc); 843 844 /* 845 * Read the Ethernet address from the EEPROM. This might 846 * also fetch other stuff from the EEPROM and stash it 847 * in the softc. 848 */ 849 sc->sc_cfg = 0; 850 #if !defined(DP83820) 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 854 855 if (SIP_SIS900_REV(sc,SIS_REV_635) || 856 SIP_SIS900_REV(sc,SIS_REV_960) || 857 SIP_SIS900_REV(sc,SIS_REV_900B)) 858 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 859 SIP_CFG) & CFG_EDBMASTEN); 860 #endif 861 862 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 863 864 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 865 ether_sprintf(enaddr)); 866 867 /* 868 * Initialize the configuration register: aggressive PCI 869 * bus request algorithm, default backoff, default OW timer, 870 * default parity error detection. 871 * 872 * NOTE: "Big endian mode" is useless on the SiS900 and 873 * friends -- it affects packet data, not descriptors. 874 */ 875 #ifdef DP83820 876 /* 877 * Cause the chip to load configuration data from the EEPROM. 878 */ 879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 880 for (i = 0; i < 10000; i++) { 881 delay(10); 882 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) == 0) 884 break; 885 } 886 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 887 PTSCR_EELOAD_EN) { 888 printf("%s: timeout loading configuration from EEPROM\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 893 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 894 895 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 896 if (reg & CFG_PCI64_DET) { 897 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 898 /* 899 * Check to see if this card is 64-bit. If so, enable 64-bit 900 * data transfers. 901 * 902 * We can't use the DATA64_EN bit in the EEPROM, because 903 * vendors of 32-bit cards fail to clear that bit in many 904 * cases (yet the card still detects that it's in a 64-bit 905 * slot; go figure). 906 */ 907 if (SIP_DECL(check_64bit)(pa)) { 908 sc->sc_cfg |= CFG_DATA64_EN; 909 printf(", using 64-bit data transfers"); 910 } 911 printf("\n"); 912 } 913 914 /* 915 * XXX Need some PCI flags indicating support for 916 * XXX 64-bit addressing. 917 */ 918 #if 0 919 if (reg & CFG_M64ADDR) 920 sc->sc_cfg |= CFG_M64ADDR; 921 if (reg & CFG_T64ADDR) 922 sc->sc_cfg |= CFG_T64ADDR; 923 #endif 924 925 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 926 const char *sep = ""; 927 printf("%s: using ", sc->sc_dev.dv_xname); 928 if (reg & CFG_EXT_125) { 929 sc->sc_cfg |= CFG_EXT_125; 930 printf("%s125MHz clock", sep); 931 sep = ", "; 932 } 933 if (reg & CFG_TBI_EN) { 934 sc->sc_cfg |= CFG_TBI_EN; 935 printf("%sten-bit interface", sep); 936 sep = ", "; 937 } 938 printf("\n"); 939 } 940 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 941 (reg & CFG_MRM_DIS) != 0) 942 sc->sc_cfg |= CFG_MRM_DIS; 943 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 944 (reg & CFG_MWI_DIS) != 0) 945 sc->sc_cfg |= CFG_MWI_DIS; 946 947 /* 948 * Use the extended descriptor format on the DP83820. This 949 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 950 * checksumming. 951 */ 952 sc->sc_cfg |= CFG_EXTSTS_EN; 953 #endif /* DP83820 */ 954 955 /* 956 * Initialize our media structures and probe the MII. 957 */ 958 sc->sc_mii.mii_ifp = ifp; 959 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 960 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 961 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 962 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 963 SIP_DECL(mediastatus)); 964 965 /* 966 * XXX We cannot handle flow control on the DP83815. 967 */ 968 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, 0); 971 else 972 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, MIIF_DOPAUSE); 974 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 975 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 977 } else 978 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 979 980 ifp = &sc->sc_ethercom.ec_if; 981 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 982 ifp->if_softc = sc; 983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 984 sc->sc_if_flags = ifp->if_flags; 985 ifp->if_ioctl = SIP_DECL(ioctl); 986 ifp->if_start = SIP_DECL(start); 987 ifp->if_watchdog = SIP_DECL(watchdog); 988 ifp->if_init = SIP_DECL(init); 989 ifp->if_stop = SIP_DECL(stop); 990 IFQ_SET_READY(&ifp->if_snd); 991 992 /* 993 * We can support 802.1Q VLAN-sized frames. 994 */ 995 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 996 997 #ifdef DP83820 998 /* 999 * And the DP83820 can do VLAN tagging in hardware, and 1000 * support the jumbo Ethernet MTU. 1001 */ 1002 sc->sc_ethercom.ec_capabilities |= 1003 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1004 1005 /* 1006 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1007 * in hardware. 1008 */ 1009 ifp->if_capabilities |= 1010 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1011 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1012 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1013 #endif /* DP83820 */ 1014 1015 /* 1016 * Attach the interface. 1017 */ 1018 if_attach(ifp); 1019 ether_ifattach(ifp, enaddr); 1020 #if NRND > 0 1021 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1022 RND_TYPE_NET, 0); 1023 #endif 1024 1025 /* 1026 * The number of bytes that must be available in 1027 * the Tx FIFO before the bus master can DMA more 1028 * data into the FIFO. 1029 */ 1030 sc->sc_tx_fill_thresh = 64 / 32; 1031 1032 /* 1033 * Start at a drain threshold of 512 bytes. We will 1034 * increase it if a DMA underrun occurs. 1035 * 1036 * XXX The minimum value of this variable should be 1037 * tuned. We may be able to improve performance 1038 * by starting with a lower value. That, however, 1039 * may trash the first few outgoing packets if the 1040 * PCI bus is saturated. 1041 */ 1042 #ifdef DP83820 1043 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1044 #else 1045 sc->sc_tx_drain_thresh = 1504 / 32; 1046 #endif 1047 1048 /* 1049 * Initialize the Rx FIFO drain threshold. 1050 * 1051 * This is in units of 8 bytes. 1052 * 1053 * We should never set this value lower than 2; 14 bytes are 1054 * required to filter the packet. 1055 */ 1056 sc->sc_rx_drain_thresh = 128 / 8; 1057 1058 #ifdef SIP_EVENT_COUNTERS 1059 /* 1060 * Attach event counters. 1061 */ 1062 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txsstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1065 NULL, sc->sc_dev.dv_xname, "txdstall"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txdintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "txiintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "rxintr"); 1074 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1075 NULL, sc->sc_dev.dv_xname, "hiberr"); 1076 #ifndef DP83820 1077 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1078 NULL, sc->sc_dev.dv_xname, "rxpause"); 1079 #endif /* !DP83820 */ 1080 #ifdef DP83820 1081 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "rxpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "txpause"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txipsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1095 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1096 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1097 #endif /* DP83820 */ 1098 #endif /* SIP_EVENT_COUNTERS */ 1099 1100 /* 1101 * Make sure the interface is shutdown during reboot. 1102 */ 1103 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1104 if (sc->sc_sdhook == NULL) 1105 printf("%s: WARNING: unable to establish shutdown hook\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 1109 /* 1110 * Free any resources we've allocated during the failed attach 1111 * attempt. Do this in reverse order and fall through. 1112 */ 1113 fail_5: 1114 for (i = 0; i < SIP_NRXDESC; i++) { 1115 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1116 bus_dmamap_destroy(sc->sc_dmat, 1117 sc->sc_rxsoft[i].rxs_dmamap); 1118 } 1119 fail_4: 1120 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1121 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1122 bus_dmamap_destroy(sc->sc_dmat, 1123 sc->sc_txsoft[i].txs_dmamap); 1124 } 1125 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_3: 1127 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1128 fail_2: 1129 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1130 sizeof(struct sip_control_data)); 1131 fail_1: 1132 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1133 fail_0: 1134 return; 1135 } 1136 1137 /* 1138 * sip_shutdown: 1139 * 1140 * Make sure the interface is stopped at reboot time. 1141 */ 1142 static void 1143 SIP_DECL(shutdown)(void *arg) 1144 { 1145 struct sip_softc *sc = arg; 1146 1147 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1148 } 1149 1150 /* 1151 * sip_start: [ifnet interface function] 1152 * 1153 * Start packet transmission on the interface. 1154 */ 1155 static void 1156 SIP_DECL(start)(struct ifnet *ifp) 1157 { 1158 struct sip_softc *sc = ifp->if_softc; 1159 struct mbuf *m0; 1160 #ifndef DP83820 1161 struct mbuf *m; 1162 #endif 1163 struct sip_txsoft *txs; 1164 bus_dmamap_t dmamap; 1165 int error, nexttx, lasttx, seg; 1166 int ofree = sc->sc_txfree; 1167 #if 0 1168 int firsttx = sc->sc_txnext; 1169 #endif 1170 #ifdef DP83820 1171 struct m_tag *mtag; 1172 u_int32_t extsts; 1173 #endif 1174 1175 #ifndef DP83820 1176 /* 1177 * If we've been told to pause, don't transmit any more packets. 1178 */ 1179 if (sc->sc_paused) 1180 ifp->if_flags |= IFF_OACTIVE; 1181 #endif 1182 1183 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1184 return; 1185 1186 /* 1187 * Loop through the send queue, setting up transmit descriptors 1188 * until we drain the queue, or use up all available transmit 1189 * descriptors. 1190 */ 1191 for (;;) { 1192 /* Get a work queue entry. */ 1193 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1194 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1195 break; 1196 } 1197 1198 /* 1199 * Grab a packet off the queue. 1200 */ 1201 IFQ_POLL(&ifp->if_snd, m0); 1202 if (m0 == NULL) 1203 break; 1204 #ifndef DP83820 1205 m = NULL; 1206 #endif 1207 1208 dmamap = txs->txs_dmamap; 1209 1210 #ifdef DP83820 1211 /* 1212 * Load the DMA map. If this fails, the packet either 1213 * didn't fit in the allotted number of segments, or we 1214 * were short on resources. For the too-many-segments 1215 * case, we simply report an error and drop the packet, 1216 * since we can't sanely copy a jumbo packet to a single 1217 * buffer. 1218 */ 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1220 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1221 if (error) { 1222 if (error == EFBIG) { 1223 printf("%s: Tx packet consumes too many " 1224 "DMA segments, dropping...\n", 1225 sc->sc_dev.dv_xname); 1226 IFQ_DEQUEUE(&ifp->if_snd, m0); 1227 m_freem(m0); 1228 continue; 1229 } 1230 /* 1231 * Short on resources, just stop for now. 1232 */ 1233 break; 1234 } 1235 #else /* DP83820 */ 1236 /* 1237 * Load the DMA map. If this fails, the packet either 1238 * didn't fit in the alloted number of segments, or we 1239 * were short on resources. In this case, we'll copy 1240 * and try again. 1241 */ 1242 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1243 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1244 MGETHDR(m, M_DONTWAIT, MT_DATA); 1245 if (m == NULL) { 1246 printf("%s: unable to allocate Tx mbuf\n", 1247 sc->sc_dev.dv_xname); 1248 break; 1249 } 1250 if (m0->m_pkthdr.len > MHLEN) { 1251 MCLGET(m, M_DONTWAIT); 1252 if ((m->m_flags & M_EXT) == 0) { 1253 printf("%s: unable to allocate Tx " 1254 "cluster\n", sc->sc_dev.dv_xname); 1255 m_freem(m); 1256 break; 1257 } 1258 } 1259 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1260 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1261 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1262 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1263 if (error) { 1264 printf("%s: unable to load Tx buffer, " 1265 "error = %d\n", sc->sc_dev.dv_xname, error); 1266 break; 1267 } 1268 } 1269 #endif /* DP83820 */ 1270 1271 /* 1272 * Ensure we have enough descriptors free to describe 1273 * the packet. Note, we always reserve one descriptor 1274 * at the end of the ring as a termination point, to 1275 * prevent wrap-around. 1276 */ 1277 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1278 /* 1279 * Not enough free descriptors to transmit this 1280 * packet. We haven't committed anything yet, 1281 * so just unload the DMA map, put the packet 1282 * back on the queue, and punt. Notify the upper 1283 * layer that there are not more slots left. 1284 * 1285 * XXX We could allocate an mbuf and copy, but 1286 * XXX is it worth it? 1287 */ 1288 ifp->if_flags |= IFF_OACTIVE; 1289 bus_dmamap_unload(sc->sc_dmat, dmamap); 1290 #ifndef DP83820 1291 if (m != NULL) 1292 m_freem(m); 1293 #endif 1294 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1295 break; 1296 } 1297 1298 IFQ_DEQUEUE(&ifp->if_snd, m0); 1299 #ifndef DP83820 1300 if (m != NULL) { 1301 m_freem(m0); 1302 m0 = m; 1303 } 1304 #endif 1305 1306 /* 1307 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1308 */ 1309 1310 /* Sync the DMA map. */ 1311 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1312 BUS_DMASYNC_PREWRITE); 1313 1314 /* 1315 * Initialize the transmit descriptors. 1316 */ 1317 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1318 seg < dmamap->dm_nsegs; 1319 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1320 /* 1321 * If this is the first descriptor we're 1322 * enqueueing, don't set the OWN bit just 1323 * yet. That could cause a race condition. 1324 * We'll do it below. 1325 */ 1326 sc->sc_txdescs[nexttx].sipd_bufptr = 1327 htole32(dmamap->dm_segs[seg].ds_addr); 1328 sc->sc_txdescs[nexttx].sipd_cmdsts = 1329 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1330 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1331 #ifdef DP83820 1332 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1333 #endif /* DP83820 */ 1334 lasttx = nexttx; 1335 } 1336 1337 /* Clear the MORE bit on the last segment. */ 1338 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1339 1340 /* 1341 * If we're in the interrupt delay window, delay the 1342 * interrupt. 1343 */ 1344 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1345 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1346 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1347 htole32(CMDSTS_INTR); 1348 sc->sc_txwin = 0; 1349 } 1350 1351 #ifdef DP83820 1352 /* 1353 * If VLANs are enabled and the packet has a VLAN tag, set 1354 * up the descriptor to encapsulate the packet for us. 1355 * 1356 * This apparently has to be on the last descriptor of 1357 * the packet. 1358 */ 1359 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1360 sc->sc_txdescs[lasttx].sipd_extsts |= 1361 htole32(EXTSTS_VPKT | 1362 (VLAN_TAG_VALUE(mtag) & EXTSTS_VTCI)); 1363 } 1364 1365 /* 1366 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1367 * checksumming, set up the descriptor to do this work 1368 * for us. 1369 * 1370 * This apparently has to be on the first descriptor of 1371 * the packet. 1372 * 1373 * Byte-swap constants so the compiler can optimize. 1374 */ 1375 extsts = 0; 1376 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1377 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1378 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1379 extsts |= htole32(EXTSTS_IPPKT); 1380 } 1381 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1382 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1383 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1384 extsts |= htole32(EXTSTS_TCPPKT); 1385 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1386 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1387 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1388 extsts |= htole32(EXTSTS_UDPPKT); 1389 } 1390 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1391 #endif /* DP83820 */ 1392 1393 /* Sync the descriptors we're using. */ 1394 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1395 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1396 1397 /* 1398 * The entire packet is set up. Give the first descrptor 1399 * to the chip now. 1400 */ 1401 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1402 htole32(CMDSTS_OWN); 1403 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1404 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1405 1406 /* 1407 * Store a pointer to the packet so we can free it later, 1408 * and remember what txdirty will be once the packet is 1409 * done. 1410 */ 1411 txs->txs_mbuf = m0; 1412 txs->txs_firstdesc = sc->sc_txnext; 1413 txs->txs_lastdesc = lasttx; 1414 1415 /* Advance the tx pointer. */ 1416 sc->sc_txfree -= dmamap->dm_nsegs; 1417 sc->sc_txnext = nexttx; 1418 1419 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1420 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1421 1422 #if NBPFILTER > 0 1423 /* 1424 * Pass the packet to any BPF listeners. 1425 */ 1426 if (ifp->if_bpf) 1427 bpf_mtap(ifp->if_bpf, m0); 1428 #endif /* NBPFILTER > 0 */ 1429 } 1430 1431 if (txs == NULL || sc->sc_txfree == 0) { 1432 /* No more slots left; notify upper layer. */ 1433 ifp->if_flags |= IFF_OACTIVE; 1434 } 1435 1436 if (sc->sc_txfree != ofree) { 1437 /* 1438 * Start the transmit process. Note, the manual says 1439 * that if there are no pending transmissions in the 1440 * chip's internal queue (indicated by TXE being clear), 1441 * then the driver software must set the TXDP to the 1442 * first descriptor to be transmitted. However, if we 1443 * do this, it causes serious performance degredation on 1444 * the DP83820 under load, not setting TXDP doesn't seem 1445 * to adversely affect the SiS 900 or DP83815. 1446 * 1447 * Well, I guess it wouldn't be the first time a manual 1448 * has lied -- and they could be speaking of the NULL- 1449 * terminated descriptor list case, rather than OWN- 1450 * terminated rings. 1451 */ 1452 #if 0 1453 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1454 CR_TXE) == 0) { 1455 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1456 SIP_CDTXADDR(sc, firsttx)); 1457 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1458 } 1459 #else 1460 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1461 #endif 1462 1463 /* Set a watchdog timer in case the chip flakes out. */ 1464 #ifdef DP83820 1465 /* Gigabit autonegotiation takes 5 seconds. */ 1466 ifp->if_timer = 10; 1467 #else 1468 ifp->if_timer = 5; 1469 #endif 1470 } 1471 } 1472 1473 /* 1474 * sip_watchdog: [ifnet interface function] 1475 * 1476 * Watchdog timer handler. 1477 */ 1478 static void 1479 SIP_DECL(watchdog)(struct ifnet *ifp) 1480 { 1481 struct sip_softc *sc = ifp->if_softc; 1482 1483 /* 1484 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1485 * If we get a timeout, try and sweep up transmit descriptors. 1486 * If we manage to sweep them all up, ignore the lack of 1487 * interrupt. 1488 */ 1489 SIP_DECL(txintr)(sc); 1490 1491 if (sc->sc_txfree != SIP_NTXDESC) { 1492 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1493 ifp->if_oerrors++; 1494 1495 /* Reset the interface. */ 1496 (void) SIP_DECL(init)(ifp); 1497 } else if (ifp->if_flags & IFF_DEBUG) 1498 printf("%s: recovered from device timeout\n", 1499 sc->sc_dev.dv_xname); 1500 1501 /* Try to get more packets going. */ 1502 SIP_DECL(start)(ifp); 1503 } 1504 1505 /* 1506 * sip_ioctl: [ifnet interface function] 1507 * 1508 * Handle control requests from the operator. 1509 */ 1510 static int 1511 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1512 { 1513 struct sip_softc *sc = ifp->if_softc; 1514 struct ifreq *ifr = (struct ifreq *)data; 1515 int s, error; 1516 1517 s = splnet(); 1518 1519 switch (cmd) { 1520 case SIOCSIFMEDIA: 1521 /* Flow control requires full-duplex mode. */ 1522 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1523 (ifr->ifr_media & IFM_FDX) == 0) 1524 ifr->ifr_media &= ~IFM_ETH_FMASK; 1525 #ifdef DP83820 1526 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1527 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1528 /* We can do both TXPAUSE and RXPAUSE. */ 1529 ifr->ifr_media |= 1530 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1531 } 1532 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1533 } 1534 #else 1535 /* XXX */ 1536 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1537 ifr->ifr_media &= ~IFM_ETH_FMASK; 1538 1539 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1540 if (ifr->ifr_media & IFM_FLOW) { 1541 /* 1542 * Both TXPAUSE and RXPAUSE must be set. 1543 * (SiS900 and DP83815 don't have PAUSE_ASYM 1544 * feature.) 1545 * 1546 * XXX Can SiS900 and DP83815 send PAUSE? 1547 */ 1548 ifr->ifr_media |= 1549 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1550 } 1551 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1552 } 1553 #endif 1554 /* FALLTHROUGH */ 1555 case SIOCGIFMEDIA: 1556 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1557 break; 1558 case SIOCSIFFLAGS: 1559 /* If the interface is up and running, only modify the receive 1560 * filter when setting promiscuous or debug mode. Otherwise 1561 * fall through to ether_ioctl, which will reset the chip. 1562 */ 1563 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1564 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1565 == (IFF_UP|IFF_RUNNING)) 1566 && ((ifp->if_flags & (~RESETIGN)) 1567 == (sc->sc_if_flags & (~RESETIGN)))) { 1568 /* Set up the receive filter. */ 1569 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1570 error = 0; 1571 break; 1572 #undef RESETIGN 1573 } 1574 /* FALLTHROUGH */ 1575 default: 1576 error = ether_ioctl(ifp, cmd, data); 1577 if (error == ENETRESET) { 1578 /* 1579 * Multicast list has changed; set the hardware filter 1580 * accordingly. 1581 */ 1582 if (ifp->if_flags & IFF_RUNNING) 1583 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1584 error = 0; 1585 } 1586 break; 1587 } 1588 1589 /* Try to get more packets going. */ 1590 SIP_DECL(start)(ifp); 1591 1592 sc->sc_if_flags = ifp->if_flags; 1593 splx(s); 1594 return (error); 1595 } 1596 1597 /* 1598 * sip_intr: 1599 * 1600 * Interrupt service routine. 1601 */ 1602 static int 1603 SIP_DECL(intr)(void *arg) 1604 { 1605 struct sip_softc *sc = arg; 1606 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1607 u_int32_t isr; 1608 int handled = 0; 1609 1610 /* Disable interrupts. */ 1611 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1612 1613 for (;;) { 1614 /* Reading clears interrupt. */ 1615 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1616 if ((isr & sc->sc_imr) == 0) 1617 break; 1618 1619 #if NRND > 0 1620 if (RND_ENABLED(&sc->rnd_source)) 1621 rnd_add_uint32(&sc->rnd_source, isr); 1622 #endif 1623 1624 handled = 1; 1625 1626 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1627 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1628 1629 /* Grab any new packets. */ 1630 SIP_DECL(rxintr)(sc); 1631 1632 if (isr & ISR_RXORN) { 1633 printf("%s: receive FIFO overrun\n", 1634 sc->sc_dev.dv_xname); 1635 1636 /* XXX adjust rx_drain_thresh? */ 1637 } 1638 1639 if (isr & ISR_RXIDLE) { 1640 printf("%s: receive ring overrun\n", 1641 sc->sc_dev.dv_xname); 1642 1643 /* Get the receive process going again. */ 1644 bus_space_write_4(sc->sc_st, sc->sc_sh, 1645 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1646 bus_space_write_4(sc->sc_st, sc->sc_sh, 1647 SIP_CR, CR_RXE); 1648 } 1649 } 1650 1651 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1652 #ifdef SIP_EVENT_COUNTERS 1653 if (isr & ISR_TXDESC) 1654 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1655 else if (isr & ISR_TXIDLE) 1656 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1657 #endif 1658 1659 /* Sweep up transmit descriptors. */ 1660 SIP_DECL(txintr)(sc); 1661 1662 if (isr & ISR_TXURN) { 1663 u_int32_t thresh; 1664 1665 printf("%s: transmit FIFO underrun", 1666 sc->sc_dev.dv_xname); 1667 1668 thresh = sc->sc_tx_drain_thresh + 1; 1669 if (thresh <= TXCFG_DRTH && 1670 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1671 (sc->sc_tx_fill_thresh * 32))) { 1672 printf("; increasing Tx drain " 1673 "threshold to %u bytes\n", 1674 thresh * 32); 1675 sc->sc_tx_drain_thresh = thresh; 1676 (void) SIP_DECL(init)(ifp); 1677 } else { 1678 (void) SIP_DECL(init)(ifp); 1679 printf("\n"); 1680 } 1681 } 1682 } 1683 1684 #if !defined(DP83820) 1685 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1686 if (isr & ISR_PAUSE_ST) { 1687 sc->sc_paused = 1; 1688 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1689 ifp->if_flags |= IFF_OACTIVE; 1690 } 1691 if (isr & ISR_PAUSE_END) { 1692 sc->sc_paused = 0; 1693 ifp->if_flags &= ~IFF_OACTIVE; 1694 } 1695 } 1696 #endif /* ! DP83820 */ 1697 1698 if (isr & ISR_HIBERR) { 1699 int want_init = 0; 1700 1701 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1702 1703 #define PRINTERR(bit, str) \ 1704 do { \ 1705 if ((isr & (bit)) != 0) { \ 1706 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1707 printf("%s: %s\n", \ 1708 sc->sc_dev.dv_xname, str); \ 1709 want_init = 1; \ 1710 } \ 1711 } while (/*CONSTCOND*/0) 1712 1713 PRINTERR(ISR_DPERR, "parity error"); 1714 PRINTERR(ISR_SSERR, "system error"); 1715 PRINTERR(ISR_RMABT, "master abort"); 1716 PRINTERR(ISR_RTABT, "target abort"); 1717 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1718 /* 1719 * Ignore: 1720 * Tx reset complete 1721 * Rx reset complete 1722 */ 1723 if (want_init) 1724 (void) SIP_DECL(init)(ifp); 1725 #undef PRINTERR 1726 } 1727 } 1728 1729 /* Re-enable interrupts. */ 1730 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1731 1732 /* Try to get more packets going. */ 1733 SIP_DECL(start)(ifp); 1734 1735 return (handled); 1736 } 1737 1738 /* 1739 * sip_txintr: 1740 * 1741 * Helper; handle transmit interrupts. 1742 */ 1743 static void 1744 SIP_DECL(txintr)(struct sip_softc *sc) 1745 { 1746 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1747 struct sip_txsoft *txs; 1748 u_int32_t cmdsts; 1749 1750 #ifndef DP83820 1751 if (sc->sc_paused == 0) 1752 #endif 1753 ifp->if_flags &= ~IFF_OACTIVE; 1754 1755 /* 1756 * Go through our Tx list and free mbufs for those 1757 * frames which have been transmitted. 1758 */ 1759 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1760 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1761 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1762 1763 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1764 if (cmdsts & CMDSTS_OWN) 1765 break; 1766 1767 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1768 1769 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1770 1771 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1772 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1773 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1774 m_freem(txs->txs_mbuf); 1775 txs->txs_mbuf = NULL; 1776 1777 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1778 1779 /* 1780 * Check for errors and collisions. 1781 */ 1782 if (cmdsts & 1783 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1784 ifp->if_oerrors++; 1785 if (cmdsts & CMDSTS_Tx_EC) 1786 ifp->if_collisions += 16; 1787 if (ifp->if_flags & IFF_DEBUG) { 1788 if (cmdsts & CMDSTS_Tx_ED) 1789 printf("%s: excessive deferral\n", 1790 sc->sc_dev.dv_xname); 1791 if (cmdsts & CMDSTS_Tx_EC) 1792 printf("%s: excessive collisions\n", 1793 sc->sc_dev.dv_xname); 1794 } 1795 } else { 1796 /* Packet was transmitted successfully. */ 1797 ifp->if_opackets++; 1798 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1799 } 1800 } 1801 1802 /* 1803 * If there are no more pending transmissions, cancel the watchdog 1804 * timer. 1805 */ 1806 if (txs == NULL) { 1807 ifp->if_timer = 0; 1808 sc->sc_txwin = 0; 1809 } 1810 } 1811 1812 #if defined(DP83820) 1813 /* 1814 * sip_rxintr: 1815 * 1816 * Helper; handle receive interrupts. 1817 */ 1818 static void 1819 SIP_DECL(rxintr)(struct sip_softc *sc) 1820 { 1821 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1822 struct sip_rxsoft *rxs; 1823 struct mbuf *m; 1824 u_int32_t cmdsts, extsts; 1825 int i, len; 1826 1827 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1828 rxs = &sc->sc_rxsoft[i]; 1829 1830 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1831 1832 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1833 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1834 len = CMDSTS_SIZE(cmdsts); 1835 1836 /* 1837 * NOTE: OWN is set if owned by _consumer_. We're the 1838 * consumer of the receive ring, so if the bit is clear, 1839 * we have processed all of the packets. 1840 */ 1841 if ((cmdsts & CMDSTS_OWN) == 0) { 1842 /* 1843 * We have processed all of the receive buffers. 1844 */ 1845 break; 1846 } 1847 1848 if (__predict_false(sc->sc_rxdiscard)) { 1849 SIP_INIT_RXDESC(sc, i); 1850 if ((cmdsts & CMDSTS_MORE) == 0) { 1851 /* Reset our state. */ 1852 sc->sc_rxdiscard = 0; 1853 } 1854 continue; 1855 } 1856 1857 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1858 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1859 1860 m = rxs->rxs_mbuf; 1861 1862 /* 1863 * Add a new receive buffer to the ring. 1864 */ 1865 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1866 /* 1867 * Failed, throw away what we've done so 1868 * far, and discard the rest of the packet. 1869 */ 1870 ifp->if_ierrors++; 1871 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1872 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1873 SIP_INIT_RXDESC(sc, i); 1874 if (cmdsts & CMDSTS_MORE) 1875 sc->sc_rxdiscard = 1; 1876 if (sc->sc_rxhead != NULL) 1877 m_freem(sc->sc_rxhead); 1878 SIP_RXCHAIN_RESET(sc); 1879 continue; 1880 } 1881 1882 SIP_RXCHAIN_LINK(sc, m); 1883 1884 m->m_len = len; 1885 1886 /* 1887 * If this is not the end of the packet, keep 1888 * looking. 1889 */ 1890 if (cmdsts & CMDSTS_MORE) { 1891 sc->sc_rxlen += len; 1892 continue; 1893 } 1894 1895 /* 1896 * Okay, we have the entire packet now. The chip includes 1897 * the FCS, so we need to trim it. 1898 */ 1899 m->m_len -= ETHER_CRC_LEN; 1900 1901 *sc->sc_rxtailp = NULL; 1902 len = m->m_len + sc->sc_rxlen; 1903 m = sc->sc_rxhead; 1904 1905 SIP_RXCHAIN_RESET(sc); 1906 1907 /* 1908 * If an error occurred, update stats and drop the packet. 1909 */ 1910 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1911 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1912 ifp->if_ierrors++; 1913 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1914 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1915 /* Receive overrun handled elsewhere. */ 1916 printf("%s: receive descriptor error\n", 1917 sc->sc_dev.dv_xname); 1918 } 1919 #define PRINTERR(bit, str) \ 1920 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1921 (cmdsts & (bit)) != 0) \ 1922 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1923 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1924 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1925 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1926 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1927 #undef PRINTERR 1928 m_freem(m); 1929 continue; 1930 } 1931 1932 /* 1933 * If the packet is small enough to fit in a 1934 * single header mbuf, allocate one and copy 1935 * the data into it. This greatly reduces 1936 * memory consumption when we receive lots 1937 * of small packets. 1938 */ 1939 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1940 struct mbuf *nm; 1941 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1942 if (nm == NULL) { 1943 ifp->if_ierrors++; 1944 m_freem(m); 1945 continue; 1946 } 1947 nm->m_data += 2; 1948 nm->m_pkthdr.len = nm->m_len = len; 1949 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1950 m_freem(m); 1951 m = nm; 1952 } 1953 #ifndef __NO_STRICT_ALIGNMENT 1954 else { 1955 /* 1956 * The DP83820's receive buffers must be 4-byte 1957 * aligned. But this means that the data after 1958 * the Ethernet header is misaligned. To compensate, 1959 * we have artificially shortened the buffer size 1960 * in the descriptor, and we do an overlapping copy 1961 * of the data two bytes further in (in the first 1962 * buffer of the chain only). 1963 */ 1964 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1965 m->m_len); 1966 m->m_data += 2; 1967 } 1968 #endif /* ! __NO_STRICT_ALIGNMENT */ 1969 1970 /* 1971 * If VLANs are enabled, VLAN packets have been unwrapped 1972 * for us. Associate the tag with the packet. 1973 */ 1974 if ((extsts & EXTSTS_VPKT) != 0) { 1975 VLAN_INPUT_TAG(ifp, m, ntohs(extsts & EXTSTS_VTCI), 1976 continue); 1977 } 1978 1979 /* 1980 * Set the incoming checksum information for the 1981 * packet. 1982 */ 1983 if ((extsts & EXTSTS_IPPKT) != 0) { 1984 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1985 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1986 if (extsts & EXTSTS_Rx_IPERR) 1987 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1988 if (extsts & EXTSTS_TCPPKT) { 1989 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1990 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1991 if (extsts & EXTSTS_Rx_TCPERR) 1992 m->m_pkthdr.csum_flags |= 1993 M_CSUM_TCP_UDP_BAD; 1994 } else if (extsts & EXTSTS_UDPPKT) { 1995 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1996 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1997 if (extsts & EXTSTS_Rx_UDPERR) 1998 m->m_pkthdr.csum_flags |= 1999 M_CSUM_TCP_UDP_BAD; 2000 } 2001 } 2002 2003 ifp->if_ipackets++; 2004 m->m_pkthdr.rcvif = ifp; 2005 m->m_pkthdr.len = len; 2006 2007 #if NBPFILTER > 0 2008 /* 2009 * Pass this up to any BPF listeners, but only 2010 * pass if up the stack if it's for us. 2011 */ 2012 if (ifp->if_bpf) 2013 bpf_mtap(ifp->if_bpf, m); 2014 #endif /* NBPFILTER > 0 */ 2015 2016 /* Pass it on. */ 2017 (*ifp->if_input)(ifp, m); 2018 } 2019 2020 /* Update the receive pointer. */ 2021 sc->sc_rxptr = i; 2022 } 2023 #else /* ! DP83820 */ 2024 /* 2025 * sip_rxintr: 2026 * 2027 * Helper; handle receive interrupts. 2028 */ 2029 static void 2030 SIP_DECL(rxintr)(struct sip_softc *sc) 2031 { 2032 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2033 struct sip_rxsoft *rxs; 2034 struct mbuf *m; 2035 u_int32_t cmdsts; 2036 int i, len; 2037 2038 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2039 rxs = &sc->sc_rxsoft[i]; 2040 2041 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2042 2043 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2044 2045 /* 2046 * NOTE: OWN is set if owned by _consumer_. We're the 2047 * consumer of the receive ring, so if the bit is clear, 2048 * we have processed all of the packets. 2049 */ 2050 if ((cmdsts & CMDSTS_OWN) == 0) { 2051 /* 2052 * We have processed all of the receive buffers. 2053 */ 2054 break; 2055 } 2056 2057 /* 2058 * If any collisions were seen on the wire, count one. 2059 */ 2060 if (cmdsts & CMDSTS_Rx_COL) 2061 ifp->if_collisions++; 2062 2063 /* 2064 * If an error occurred, update stats, clear the status 2065 * word, and leave the packet buffer in place. It will 2066 * simply be reused the next time the ring comes around. 2067 */ 2068 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2069 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2070 ifp->if_ierrors++; 2071 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2072 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2073 /* Receive overrun handled elsewhere. */ 2074 printf("%s: receive descriptor error\n", 2075 sc->sc_dev.dv_xname); 2076 } 2077 #define PRINTERR(bit, str) \ 2078 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2079 (cmdsts & (bit)) != 0) \ 2080 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2081 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2082 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2083 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2084 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2085 #undef PRINTERR 2086 SIP_INIT_RXDESC(sc, i); 2087 continue; 2088 } 2089 2090 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2091 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2092 2093 /* 2094 * No errors; receive the packet. Note, the SiS 900 2095 * includes the CRC with every packet. 2096 */ 2097 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2098 2099 #ifdef __NO_STRICT_ALIGNMENT 2100 /* 2101 * If the packet is small enough to fit in a 2102 * single header mbuf, allocate one and copy 2103 * the data into it. This greatly reduces 2104 * memory consumption when we receive lots 2105 * of small packets. 2106 * 2107 * Otherwise, we add a new buffer to the receive 2108 * chain. If this fails, we drop the packet and 2109 * recycle the old buffer. 2110 */ 2111 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2112 MGETHDR(m, M_DONTWAIT, MT_DATA); 2113 if (m == NULL) 2114 goto dropit; 2115 memcpy(mtod(m, caddr_t), 2116 mtod(rxs->rxs_mbuf, caddr_t), len); 2117 SIP_INIT_RXDESC(sc, i); 2118 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2119 rxs->rxs_dmamap->dm_mapsize, 2120 BUS_DMASYNC_PREREAD); 2121 } else { 2122 m = rxs->rxs_mbuf; 2123 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2124 dropit: 2125 ifp->if_ierrors++; 2126 SIP_INIT_RXDESC(sc, i); 2127 bus_dmamap_sync(sc->sc_dmat, 2128 rxs->rxs_dmamap, 0, 2129 rxs->rxs_dmamap->dm_mapsize, 2130 BUS_DMASYNC_PREREAD); 2131 continue; 2132 } 2133 } 2134 #else 2135 /* 2136 * The SiS 900's receive buffers must be 4-byte aligned. 2137 * But this means that the data after the Ethernet header 2138 * is misaligned. We must allocate a new buffer and 2139 * copy the data, shifted forward 2 bytes. 2140 */ 2141 MGETHDR(m, M_DONTWAIT, MT_DATA); 2142 if (m == NULL) { 2143 dropit: 2144 ifp->if_ierrors++; 2145 SIP_INIT_RXDESC(sc, i); 2146 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2147 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2148 continue; 2149 } 2150 if (len > (MHLEN - 2)) { 2151 MCLGET(m, M_DONTWAIT); 2152 if ((m->m_flags & M_EXT) == 0) { 2153 m_freem(m); 2154 goto dropit; 2155 } 2156 } 2157 m->m_data += 2; 2158 2159 /* 2160 * Note that we use clusters for incoming frames, so the 2161 * buffer is virtually contiguous. 2162 */ 2163 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2164 2165 /* Allow the receive descriptor to continue using its mbuf. */ 2166 SIP_INIT_RXDESC(sc, i); 2167 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2168 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2169 #endif /* __NO_STRICT_ALIGNMENT */ 2170 2171 ifp->if_ipackets++; 2172 m->m_pkthdr.rcvif = ifp; 2173 m->m_pkthdr.len = m->m_len = len; 2174 2175 #if NBPFILTER > 0 2176 /* 2177 * Pass this up to any BPF listeners, but only 2178 * pass if up the stack if it's for us. 2179 */ 2180 if (ifp->if_bpf) 2181 bpf_mtap(ifp->if_bpf, m); 2182 #endif /* NBPFILTER > 0 */ 2183 2184 /* Pass it on. */ 2185 (*ifp->if_input)(ifp, m); 2186 } 2187 2188 /* Update the receive pointer. */ 2189 sc->sc_rxptr = i; 2190 } 2191 #endif /* DP83820 */ 2192 2193 /* 2194 * sip_tick: 2195 * 2196 * One second timer, used to tick the MII. 2197 */ 2198 static void 2199 SIP_DECL(tick)(void *arg) 2200 { 2201 struct sip_softc *sc = arg; 2202 int s; 2203 2204 s = splnet(); 2205 #ifdef DP83820 2206 #ifdef SIP_EVENT_COUNTERS 2207 /* Read PAUSE related counts from MIB registers. */ 2208 sc->sc_ev_rxpause.ev_count += 2209 bus_space_read_4(sc->sc_st, sc->sc_sh, 2210 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2211 sc->sc_ev_txpause.ev_count += 2212 bus_space_read_4(sc->sc_st, sc->sc_sh, 2213 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2214 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2215 #endif /* SIP_EVENT_COUNTERS */ 2216 #endif /* DP83820 */ 2217 mii_tick(&sc->sc_mii); 2218 splx(s); 2219 2220 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2221 } 2222 2223 /* 2224 * sip_reset: 2225 * 2226 * Perform a soft reset on the SiS 900. 2227 */ 2228 static void 2229 SIP_DECL(reset)(struct sip_softc *sc) 2230 { 2231 bus_space_tag_t st = sc->sc_st; 2232 bus_space_handle_t sh = sc->sc_sh; 2233 int i; 2234 2235 bus_space_write_4(st, sh, SIP_IER, 0); 2236 bus_space_write_4(st, sh, SIP_IMR, 0); 2237 bus_space_write_4(st, sh, SIP_RFCR, 0); 2238 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2239 2240 for (i = 0; i < SIP_TIMEOUT; i++) { 2241 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2242 break; 2243 delay(2); 2244 } 2245 2246 if (i == SIP_TIMEOUT) 2247 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2248 2249 delay(1000); 2250 2251 #ifdef DP83820 2252 /* 2253 * Set the general purpose I/O bits. Do it here in case we 2254 * need to have GPIO set up to talk to the media interface. 2255 */ 2256 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2257 delay(1000); 2258 #endif /* DP83820 */ 2259 } 2260 2261 /* 2262 * sip_init: [ ifnet interface function ] 2263 * 2264 * Initialize the interface. Must be called at splnet(). 2265 */ 2266 static int 2267 SIP_DECL(init)(struct ifnet *ifp) 2268 { 2269 struct sip_softc *sc = ifp->if_softc; 2270 bus_space_tag_t st = sc->sc_st; 2271 bus_space_handle_t sh = sc->sc_sh; 2272 struct sip_txsoft *txs; 2273 struct sip_rxsoft *rxs; 2274 struct sip_desc *sipd; 2275 #if defined(DP83820) 2276 u_int32_t reg; 2277 #endif 2278 int i, error = 0; 2279 2280 /* 2281 * Cancel any pending I/O. 2282 */ 2283 SIP_DECL(stop)(ifp, 0); 2284 2285 /* 2286 * Reset the chip to a known state. 2287 */ 2288 SIP_DECL(reset)(sc); 2289 2290 #if !defined(DP83820) 2291 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2292 /* 2293 * DP83815 manual, page 78: 2294 * 4.4 Recommended Registers Configuration 2295 * For optimum performance of the DP83815, version noted 2296 * as DP83815CVNG (SRR = 203h), the listed register 2297 * modifications must be followed in sequence... 2298 * 2299 * It's not clear if this should be 302h or 203h because that 2300 * chip name is listed as SRR 302h in the description of the 2301 * SRR register. However, my revision 302h DP83815 on the 2302 * Netgear FA311 purchased in 02/2001 needs these settings 2303 * to avoid tons of errors in AcceptPerfectMatch (non- 2304 * IFF_PROMISC) mode. I do not know if other revisions need 2305 * this set or not. [briggs -- 09 March 2001] 2306 * 2307 * Note that only the low-order 12 bits of 0xe4 are documented 2308 * and that this sets reserved bits in that register. 2309 */ 2310 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2311 2312 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2313 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2314 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2315 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2316 2317 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2318 } 2319 #endif /* ! DP83820 */ 2320 2321 /* 2322 * Initialize the transmit descriptor ring. 2323 */ 2324 for (i = 0; i < SIP_NTXDESC; i++) { 2325 sipd = &sc->sc_txdescs[i]; 2326 memset(sipd, 0, sizeof(struct sip_desc)); 2327 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2328 } 2329 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2330 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2331 sc->sc_txfree = SIP_NTXDESC; 2332 sc->sc_txnext = 0; 2333 sc->sc_txwin = 0; 2334 2335 /* 2336 * Initialize the transmit job descriptors. 2337 */ 2338 SIMPLEQ_INIT(&sc->sc_txfreeq); 2339 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2340 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2341 txs = &sc->sc_txsoft[i]; 2342 txs->txs_mbuf = NULL; 2343 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2344 } 2345 2346 /* 2347 * Initialize the receive descriptor and receive job 2348 * descriptor rings. 2349 */ 2350 for (i = 0; i < SIP_NRXDESC; i++) { 2351 rxs = &sc->sc_rxsoft[i]; 2352 if (rxs->rxs_mbuf == NULL) { 2353 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2354 printf("%s: unable to allocate or map rx " 2355 "buffer %d, error = %d\n", 2356 sc->sc_dev.dv_xname, i, error); 2357 /* 2358 * XXX Should attempt to run with fewer receive 2359 * XXX buffers instead of just failing. 2360 */ 2361 SIP_DECL(rxdrain)(sc); 2362 goto out; 2363 } 2364 } else 2365 SIP_INIT_RXDESC(sc, i); 2366 } 2367 sc->sc_rxptr = 0; 2368 #ifdef DP83820 2369 sc->sc_rxdiscard = 0; 2370 SIP_RXCHAIN_RESET(sc); 2371 #endif /* DP83820 */ 2372 2373 /* 2374 * Set the configuration register; it's already initialized 2375 * in sip_attach(). 2376 */ 2377 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2378 2379 /* 2380 * Initialize the prototype TXCFG register. 2381 */ 2382 #if defined(DP83820) 2383 sc->sc_txcfg = TXCFG_MXDMA_512; 2384 sc->sc_rxcfg = RXCFG_MXDMA_512; 2385 #else 2386 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2387 SIP_SIS900_REV(sc, SIS_REV_960) || 2388 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2389 (sc->sc_cfg & CFG_EDBMASTEN)) { 2390 sc->sc_txcfg = TXCFG_MXDMA_64; 2391 sc->sc_rxcfg = RXCFG_MXDMA_64; 2392 } else { 2393 sc->sc_txcfg = TXCFG_MXDMA_512; 2394 sc->sc_rxcfg = RXCFG_MXDMA_512; 2395 } 2396 #endif /* DP83820 */ 2397 2398 sc->sc_txcfg |= TXCFG_ATP | 2399 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2400 sc->sc_tx_drain_thresh; 2401 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2402 2403 /* 2404 * Initialize the receive drain threshold if we have never 2405 * done so. 2406 */ 2407 if (sc->sc_rx_drain_thresh == 0) { 2408 /* 2409 * XXX This value should be tuned. This is set to the 2410 * maximum of 248 bytes, and we may be able to improve 2411 * performance by decreasing it (although we should never 2412 * set this value lower than 2; 14 bytes are required to 2413 * filter the packet). 2414 */ 2415 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2416 } 2417 2418 /* 2419 * Initialize the prototype RXCFG register. 2420 */ 2421 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2422 #ifdef DP83820 2423 /* 2424 * Accept long packets (including FCS) so we can handle 2425 * 802.1q-tagged frames and jumbo frames properly. 2426 */ 2427 if (ifp->if_mtu > ETHERMTU || 2428 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2429 sc->sc_rxcfg |= RXCFG_ALP; 2430 2431 /* 2432 * Checksum offloading is disabled if the user selects an MTU 2433 * larger than 8109. (FreeBSD says 8152, but there is emperical 2434 * evidence that >8109 does not work on some boards, such as the 2435 * Planex GN-1000TE). 2436 */ 2437 if (ifp->if_mtu > 8109 && 2438 (ifp->if_capenable & 2439 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2440 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2441 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2442 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2443 "disabled.\n", sc->sc_dev.dv_xname); 2444 ifp->if_capenable &= 2445 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2446 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2447 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2448 ifp->if_csum_flags_tx = 0; 2449 ifp->if_csum_flags_rx = 0; 2450 } 2451 #else 2452 /* 2453 * Accept packets >1518 bytes (including FCS) so we can handle 2454 * 802.1q-tagged frames properly. 2455 */ 2456 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2457 sc->sc_rxcfg |= RXCFG_ALP; 2458 #endif 2459 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2460 2461 #ifdef DP83820 2462 /* 2463 * Initialize the VLAN/IP receive control register. 2464 * We enable checksum computation on all incoming 2465 * packets, and do not reject packets w/ bad checksums. 2466 */ 2467 reg = 0; 2468 if (ifp->if_capenable & 2469 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2470 reg |= VRCR_IPEN; 2471 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2472 reg |= VRCR_VTDEN|VRCR_VTREN; 2473 bus_space_write_4(st, sh, SIP_VRCR, reg); 2474 2475 /* 2476 * Initialize the VLAN/IP transmit control register. 2477 * We enable outgoing checksum computation on a 2478 * per-packet basis. 2479 */ 2480 reg = 0; 2481 if (ifp->if_capenable & 2482 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2483 reg |= VTCR_PPCHK; 2484 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2485 reg |= VTCR_VPPTI; 2486 bus_space_write_4(st, sh, SIP_VTCR, reg); 2487 2488 /* 2489 * If we're using VLANs, initialize the VLAN data register. 2490 * To understand why we bswap the VLAN Ethertype, see section 2491 * 4.2.36 of the DP83820 manual. 2492 */ 2493 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2494 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2495 #endif /* DP83820 */ 2496 2497 /* 2498 * Give the transmit and receive rings to the chip. 2499 */ 2500 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2501 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2502 2503 /* 2504 * Initialize the interrupt mask. 2505 */ 2506 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2507 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2508 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2509 2510 /* Set up the receive filter. */ 2511 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2512 2513 #ifdef DP83820 2514 /* 2515 * Tune sc_rx_flow_thresh. 2516 * XXX "More than 8KB" is too short for jumbo frames. 2517 * XXX TODO: Threshold value should be user-settable. 2518 */ 2519 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2520 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2521 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2522 #endif 2523 2524 /* 2525 * Set the current media. Do this after initializing the prototype 2526 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2527 * control. 2528 */ 2529 mii_mediachg(&sc->sc_mii); 2530 2531 #ifdef DP83820 2532 /* 2533 * Set the interrupt hold-off timer to 100us. 2534 */ 2535 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2536 #endif 2537 2538 /* 2539 * Enable interrupts. 2540 */ 2541 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2542 2543 /* 2544 * Start the transmit and receive processes. 2545 */ 2546 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2547 2548 /* 2549 * Start the one second MII clock. 2550 */ 2551 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2552 2553 /* 2554 * ...all done! 2555 */ 2556 ifp->if_flags |= IFF_RUNNING; 2557 ifp->if_flags &= ~IFF_OACTIVE; 2558 sc->sc_if_flags = ifp->if_flags; 2559 2560 out: 2561 if (error) 2562 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2563 return (error); 2564 } 2565 2566 /* 2567 * sip_drain: 2568 * 2569 * Drain the receive queue. 2570 */ 2571 static void 2572 SIP_DECL(rxdrain)(struct sip_softc *sc) 2573 { 2574 struct sip_rxsoft *rxs; 2575 int i; 2576 2577 for (i = 0; i < SIP_NRXDESC; i++) { 2578 rxs = &sc->sc_rxsoft[i]; 2579 if (rxs->rxs_mbuf != NULL) { 2580 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2581 m_freem(rxs->rxs_mbuf); 2582 rxs->rxs_mbuf = NULL; 2583 } 2584 } 2585 } 2586 2587 /* 2588 * sip_stop: [ ifnet interface function ] 2589 * 2590 * Stop transmission on the interface. 2591 */ 2592 static void 2593 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2594 { 2595 struct sip_softc *sc = ifp->if_softc; 2596 bus_space_tag_t st = sc->sc_st; 2597 bus_space_handle_t sh = sc->sc_sh; 2598 struct sip_txsoft *txs; 2599 u_int32_t cmdsts = 0; /* DEBUG */ 2600 2601 /* 2602 * Stop the one second clock. 2603 */ 2604 callout_stop(&sc->sc_tick_ch); 2605 2606 /* Down the MII. */ 2607 mii_down(&sc->sc_mii); 2608 2609 /* 2610 * Disable interrupts. 2611 */ 2612 bus_space_write_4(st, sh, SIP_IER, 0); 2613 2614 /* 2615 * Stop receiver and transmitter. 2616 */ 2617 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2618 2619 /* 2620 * Release any queued transmit buffers. 2621 */ 2622 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2623 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2624 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2625 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2626 CMDSTS_INTR) == 0) 2627 printf("%s: sip_stop: last descriptor does not " 2628 "have INTR bit set\n", sc->sc_dev.dv_xname); 2629 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2630 #ifdef DIAGNOSTIC 2631 if (txs->txs_mbuf == NULL) { 2632 printf("%s: dirty txsoft with no mbuf chain\n", 2633 sc->sc_dev.dv_xname); 2634 panic("sip_stop"); 2635 } 2636 #endif 2637 cmdsts |= /* DEBUG */ 2638 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2639 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2640 m_freem(txs->txs_mbuf); 2641 txs->txs_mbuf = NULL; 2642 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2643 } 2644 2645 if (disable) 2646 SIP_DECL(rxdrain)(sc); 2647 2648 /* 2649 * Mark the interface down and cancel the watchdog timer. 2650 */ 2651 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2652 ifp->if_timer = 0; 2653 2654 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2655 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2656 printf("%s: sip_stop: no INTR bits set in dirty tx " 2657 "descriptors\n", sc->sc_dev.dv_xname); 2658 } 2659 2660 /* 2661 * sip_read_eeprom: 2662 * 2663 * Read data from the serial EEPROM. 2664 */ 2665 static void 2666 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2667 u_int16_t *data) 2668 { 2669 bus_space_tag_t st = sc->sc_st; 2670 bus_space_handle_t sh = sc->sc_sh; 2671 u_int16_t reg; 2672 int i, x; 2673 2674 for (i = 0; i < wordcnt; i++) { 2675 /* Send CHIP SELECT. */ 2676 reg = EROMAR_EECS; 2677 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2678 2679 /* Shift in the READ opcode. */ 2680 for (x = 3; x > 0; x--) { 2681 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2682 reg |= EROMAR_EEDI; 2683 else 2684 reg &= ~EROMAR_EEDI; 2685 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2686 bus_space_write_4(st, sh, SIP_EROMAR, 2687 reg | EROMAR_EESK); 2688 delay(4); 2689 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2690 delay(4); 2691 } 2692 2693 /* Shift in address. */ 2694 for (x = 6; x > 0; x--) { 2695 if ((word + i) & (1 << (x - 1))) 2696 reg |= EROMAR_EEDI; 2697 else 2698 reg &= ~EROMAR_EEDI; 2699 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2700 bus_space_write_4(st, sh, SIP_EROMAR, 2701 reg | EROMAR_EESK); 2702 delay(4); 2703 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2704 delay(4); 2705 } 2706 2707 /* Shift out data. */ 2708 reg = EROMAR_EECS; 2709 data[i] = 0; 2710 for (x = 16; x > 0; x--) { 2711 bus_space_write_4(st, sh, SIP_EROMAR, 2712 reg | EROMAR_EESK); 2713 delay(4); 2714 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2715 data[i] |= (1 << (x - 1)); 2716 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2717 delay(4); 2718 } 2719 2720 /* Clear CHIP SELECT. */ 2721 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2722 delay(4); 2723 } 2724 } 2725 2726 /* 2727 * sip_add_rxbuf: 2728 * 2729 * Add a receive buffer to the indicated descriptor. 2730 */ 2731 static int 2732 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2733 { 2734 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2735 struct mbuf *m; 2736 int error; 2737 2738 MGETHDR(m, M_DONTWAIT, MT_DATA); 2739 if (m == NULL) 2740 return (ENOBUFS); 2741 2742 MCLGET(m, M_DONTWAIT); 2743 if ((m->m_flags & M_EXT) == 0) { 2744 m_freem(m); 2745 return (ENOBUFS); 2746 } 2747 2748 #if defined(DP83820) 2749 m->m_len = SIP_RXBUF_LEN; 2750 #endif /* DP83820 */ 2751 2752 if (rxs->rxs_mbuf != NULL) 2753 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2754 2755 rxs->rxs_mbuf = m; 2756 2757 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2758 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2759 BUS_DMA_READ|BUS_DMA_NOWAIT); 2760 if (error) { 2761 printf("%s: can't load rx DMA map %d, error = %d\n", 2762 sc->sc_dev.dv_xname, idx, error); 2763 panic("sip_add_rxbuf"); /* XXX */ 2764 } 2765 2766 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2767 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2768 2769 SIP_INIT_RXDESC(sc, idx); 2770 2771 return (0); 2772 } 2773 2774 #if !defined(DP83820) 2775 /* 2776 * sip_sis900_set_filter: 2777 * 2778 * Set up the receive filter. 2779 */ 2780 static void 2781 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2782 { 2783 bus_space_tag_t st = sc->sc_st; 2784 bus_space_handle_t sh = sc->sc_sh; 2785 struct ethercom *ec = &sc->sc_ethercom; 2786 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2787 struct ether_multi *enm; 2788 u_int8_t *cp; 2789 struct ether_multistep step; 2790 u_int32_t crc, mchash[16]; 2791 2792 /* 2793 * Initialize the prototype RFCR. 2794 */ 2795 sc->sc_rfcr = RFCR_RFEN; 2796 if (ifp->if_flags & IFF_BROADCAST) 2797 sc->sc_rfcr |= RFCR_AAB; 2798 if (ifp->if_flags & IFF_PROMISC) { 2799 sc->sc_rfcr |= RFCR_AAP; 2800 goto allmulti; 2801 } 2802 2803 /* 2804 * Set up the multicast address filter by passing all multicast 2805 * addresses through a CRC generator, and then using the high-order 2806 * 6 bits as an index into the 128 bit multicast hash table (only 2807 * the lower 16 bits of each 32 bit multicast hash register are 2808 * valid). The high order bits select the register, while the 2809 * rest of the bits select the bit within the register. 2810 */ 2811 2812 memset(mchash, 0, sizeof(mchash)); 2813 2814 /* 2815 * SiS900 (at least SiS963) requires us to register the address of 2816 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2817 */ 2818 crc = 0x0ed423f9; 2819 2820 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2821 SIP_SIS900_REV(sc, SIS_REV_960) || 2822 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2823 /* Just want the 8 most significant bits. */ 2824 crc >>= 24; 2825 } else { 2826 /* Just want the 7 most significant bits. */ 2827 crc >>= 25; 2828 } 2829 2830 /* Set the corresponding bit in the hash table. */ 2831 mchash[crc >> 4] |= 1 << (crc & 0xf); 2832 2833 ETHER_FIRST_MULTI(step, ec, enm); 2834 while (enm != NULL) { 2835 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2836 /* 2837 * We must listen to a range of multicast addresses. 2838 * For now, just accept all multicasts, rather than 2839 * trying to set only those filter bits needed to match 2840 * the range. (At this time, the only use of address 2841 * ranges is for IP multicast routing, for which the 2842 * range is big enough to require all bits set.) 2843 */ 2844 goto allmulti; 2845 } 2846 2847 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2848 2849 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2850 SIP_SIS900_REV(sc, SIS_REV_960) || 2851 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2852 /* Just want the 8 most significant bits. */ 2853 crc >>= 24; 2854 } else { 2855 /* Just want the 7 most significant bits. */ 2856 crc >>= 25; 2857 } 2858 2859 /* Set the corresponding bit in the hash table. */ 2860 mchash[crc >> 4] |= 1 << (crc & 0xf); 2861 2862 ETHER_NEXT_MULTI(step, enm); 2863 } 2864 2865 ifp->if_flags &= ~IFF_ALLMULTI; 2866 goto setit; 2867 2868 allmulti: 2869 ifp->if_flags |= IFF_ALLMULTI; 2870 sc->sc_rfcr |= RFCR_AAM; 2871 2872 setit: 2873 #define FILTER_EMIT(addr, data) \ 2874 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2875 delay(1); \ 2876 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2877 delay(1) 2878 2879 /* 2880 * Disable receive filter, and program the node address. 2881 */ 2882 cp = LLADDR(ifp->if_sadl); 2883 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2884 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2885 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2886 2887 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2888 /* 2889 * Program the multicast hash table. 2890 */ 2891 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2892 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2893 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2894 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2895 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2896 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2897 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2898 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2899 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2900 SIP_SIS900_REV(sc, SIS_REV_960) || 2901 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2902 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2903 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2904 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2905 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2906 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2907 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2908 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2909 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2910 } 2911 } 2912 #undef FILTER_EMIT 2913 2914 /* 2915 * Re-enable the receiver filter. 2916 */ 2917 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2918 } 2919 #endif /* ! DP83820 */ 2920 2921 /* 2922 * sip_dp83815_set_filter: 2923 * 2924 * Set up the receive filter. 2925 */ 2926 static void 2927 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2928 { 2929 bus_space_tag_t st = sc->sc_st; 2930 bus_space_handle_t sh = sc->sc_sh; 2931 struct ethercom *ec = &sc->sc_ethercom; 2932 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2933 struct ether_multi *enm; 2934 u_int8_t *cp; 2935 struct ether_multistep step; 2936 u_int32_t crc, hash, slot, bit; 2937 #ifdef DP83820 2938 #define MCHASH_NWORDS 128 2939 #else 2940 #define MCHASH_NWORDS 32 2941 #endif /* DP83820 */ 2942 u_int16_t mchash[MCHASH_NWORDS]; 2943 int i; 2944 2945 /* 2946 * Initialize the prototype RFCR. 2947 * Enable the receive filter, and accept on 2948 * Perfect (destination address) Match 2949 * If IFF_BROADCAST, also accept all broadcast packets. 2950 * If IFF_PROMISC, accept all unicast packets (and later, set 2951 * IFF_ALLMULTI and accept all multicast, too). 2952 */ 2953 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2954 if (ifp->if_flags & IFF_BROADCAST) 2955 sc->sc_rfcr |= RFCR_AAB; 2956 if (ifp->if_flags & IFF_PROMISC) { 2957 sc->sc_rfcr |= RFCR_AAP; 2958 goto allmulti; 2959 } 2960 2961 #ifdef DP83820 2962 /* 2963 * Set up the DP83820 multicast address filter by passing all multicast 2964 * addresses through a CRC generator, and then using the high-order 2965 * 11 bits as an index into the 2048 bit multicast hash table. The 2966 * high-order 7 bits select the slot, while the low-order 4 bits 2967 * select the bit within the slot. Note that only the low 16-bits 2968 * of each filter word are used, and there are 128 filter words. 2969 */ 2970 #else 2971 /* 2972 * Set up the DP83815 multicast address filter by passing all multicast 2973 * addresses through a CRC generator, and then using the high-order 2974 * 9 bits as an index into the 512 bit multicast hash table. The 2975 * high-order 5 bits select the slot, while the low-order 4 bits 2976 * select the bit within the slot. Note that only the low 16-bits 2977 * of each filter word are used, and there are 32 filter words. 2978 */ 2979 #endif /* DP83820 */ 2980 2981 memset(mchash, 0, sizeof(mchash)); 2982 2983 ifp->if_flags &= ~IFF_ALLMULTI; 2984 ETHER_FIRST_MULTI(step, ec, enm); 2985 if (enm == NULL) 2986 goto setit; 2987 while (enm != NULL) { 2988 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2989 /* 2990 * We must listen to a range of multicast addresses. 2991 * For now, just accept all multicasts, rather than 2992 * trying to set only those filter bits needed to match 2993 * the range. (At this time, the only use of address 2994 * ranges is for IP multicast routing, for which the 2995 * range is big enough to require all bits set.) 2996 */ 2997 goto allmulti; 2998 } 2999 3000 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3001 3002 #ifdef DP83820 3003 /* Just want the 11 most significant bits. */ 3004 hash = crc >> 21; 3005 #else 3006 /* Just want the 9 most significant bits. */ 3007 hash = crc >> 23; 3008 #endif /* DP83820 */ 3009 3010 slot = hash >> 4; 3011 bit = hash & 0xf; 3012 3013 /* Set the corresponding bit in the hash table. */ 3014 mchash[slot] |= 1 << bit; 3015 3016 ETHER_NEXT_MULTI(step, enm); 3017 } 3018 sc->sc_rfcr |= RFCR_MHEN; 3019 goto setit; 3020 3021 allmulti: 3022 ifp->if_flags |= IFF_ALLMULTI; 3023 sc->sc_rfcr |= RFCR_AAM; 3024 3025 setit: 3026 #define FILTER_EMIT(addr, data) \ 3027 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3028 delay(1); \ 3029 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3030 delay(1) 3031 3032 /* 3033 * Disable receive filter, and program the node address. 3034 */ 3035 cp = LLADDR(ifp->if_sadl); 3036 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3037 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3038 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3039 3040 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3041 /* 3042 * Program the multicast hash table. 3043 */ 3044 for (i = 0; i < MCHASH_NWORDS; i++) { 3045 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3046 mchash[i]); 3047 } 3048 } 3049 #undef FILTER_EMIT 3050 #undef MCHASH_NWORDS 3051 3052 /* 3053 * Re-enable the receiver filter. 3054 */ 3055 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3056 } 3057 3058 #if defined(DP83820) 3059 /* 3060 * sip_dp83820_mii_readreg: [mii interface function] 3061 * 3062 * Read a PHY register on the MII of the DP83820. 3063 */ 3064 static int 3065 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3066 { 3067 struct sip_softc *sc = (void *) self; 3068 3069 if (sc->sc_cfg & CFG_TBI_EN) { 3070 bus_addr_t tbireg; 3071 int rv; 3072 3073 if (phy != 0) 3074 return (0); 3075 3076 switch (reg) { 3077 case MII_BMCR: tbireg = SIP_TBICR; break; 3078 case MII_BMSR: tbireg = SIP_TBISR; break; 3079 case MII_ANAR: tbireg = SIP_TANAR; break; 3080 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3081 case MII_ANER: tbireg = SIP_TANER; break; 3082 case MII_EXTSR: 3083 /* 3084 * Don't even bother reading the TESR register. 3085 * The manual documents that the device has 3086 * 1000baseX full/half capability, but the 3087 * register itself seems read back 0 on some 3088 * boards. Just hard-code the result. 3089 */ 3090 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3091 3092 default: 3093 return (0); 3094 } 3095 3096 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3097 if (tbireg == SIP_TBISR) { 3098 /* LINK and ACOMP are switched! */ 3099 int val = rv; 3100 3101 rv = 0; 3102 if (val & TBISR_MR_LINK_STATUS) 3103 rv |= BMSR_LINK; 3104 if (val & TBISR_MR_AN_COMPLETE) 3105 rv |= BMSR_ACOMP; 3106 3107 /* 3108 * The manual claims this register reads back 0 3109 * on hard and soft reset. But we want to let 3110 * the gentbi driver know that we support auto- 3111 * negotiation, so hard-code this bit in the 3112 * result. 3113 */ 3114 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3115 } 3116 3117 return (rv); 3118 } 3119 3120 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3121 phy, reg)); 3122 } 3123 3124 /* 3125 * sip_dp83820_mii_writereg: [mii interface function] 3126 * 3127 * Write a PHY register on the MII of the DP83820. 3128 */ 3129 static void 3130 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3131 { 3132 struct sip_softc *sc = (void *) self; 3133 3134 if (sc->sc_cfg & CFG_TBI_EN) { 3135 bus_addr_t tbireg; 3136 3137 if (phy != 0) 3138 return; 3139 3140 switch (reg) { 3141 case MII_BMCR: tbireg = SIP_TBICR; break; 3142 case MII_ANAR: tbireg = SIP_TANAR; break; 3143 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3144 default: 3145 return; 3146 } 3147 3148 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3149 return; 3150 } 3151 3152 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3153 phy, reg, val); 3154 } 3155 3156 /* 3157 * sip_dp83820_mii_statchg: [mii interface function] 3158 * 3159 * Callback from MII layer when media changes. 3160 */ 3161 static void 3162 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3163 { 3164 struct sip_softc *sc = (struct sip_softc *) self; 3165 struct mii_data *mii = &sc->sc_mii; 3166 u_int32_t cfg, pcr; 3167 3168 /* 3169 * Get flow control negotiation result. 3170 */ 3171 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3172 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3173 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3174 mii->mii_media_active &= ~IFM_ETH_FMASK; 3175 } 3176 3177 /* 3178 * Update TXCFG for full-duplex operation. 3179 */ 3180 if ((mii->mii_media_active & IFM_FDX) != 0) 3181 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3182 else 3183 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3184 3185 /* 3186 * Update RXCFG for full-duplex or loopback. 3187 */ 3188 if ((mii->mii_media_active & IFM_FDX) != 0 || 3189 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3190 sc->sc_rxcfg |= RXCFG_ATX; 3191 else 3192 sc->sc_rxcfg &= ~RXCFG_ATX; 3193 3194 /* 3195 * Update CFG for MII/GMII. 3196 */ 3197 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3198 cfg = sc->sc_cfg | CFG_MODE_1000; 3199 else 3200 cfg = sc->sc_cfg; 3201 3202 /* 3203 * 802.3x flow control. 3204 */ 3205 pcr = 0; 3206 if (sc->sc_flowflags & IFM_FLOW) { 3207 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3208 pcr |= sc->sc_rx_flow_thresh; 3209 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3210 pcr |= PCR_PSEN | PCR_PS_MCAST; 3211 } 3212 3213 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3214 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3215 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3216 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3217 } 3218 #endif /* ! DP83820 */ 3219 3220 /* 3221 * sip_mii_bitbang_read: [mii bit-bang interface function] 3222 * 3223 * Read the MII serial port for the MII bit-bang module. 3224 */ 3225 static u_int32_t 3226 SIP_DECL(mii_bitbang_read)(struct device *self) 3227 { 3228 struct sip_softc *sc = (void *) self; 3229 3230 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3231 } 3232 3233 /* 3234 * sip_mii_bitbang_write: [mii big-bang interface function] 3235 * 3236 * Write the MII serial port for the MII bit-bang module. 3237 */ 3238 static void 3239 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3240 { 3241 struct sip_softc *sc = (void *) self; 3242 3243 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3244 } 3245 3246 #ifndef DP83820 3247 /* 3248 * sip_sis900_mii_readreg: [mii interface function] 3249 * 3250 * Read a PHY register on the MII. 3251 */ 3252 static int 3253 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3254 { 3255 struct sip_softc *sc = (struct sip_softc *) self; 3256 u_int32_t enphy; 3257 3258 /* 3259 * The PHY of recent SiS chipsets is accessed through bitbang 3260 * operations. 3261 */ 3262 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3263 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3264 phy, reg)); 3265 3266 #ifndef SIS900_MII_RESTRICT 3267 /* 3268 * The SiS 900 has only an internal PHY on the MII. Only allow 3269 * MII address 0. 3270 */ 3271 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3272 return (0); 3273 #endif 3274 3275 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3276 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3277 ENPHY_RWCMD | ENPHY_ACCESS); 3278 do { 3279 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3280 } while (enphy & ENPHY_ACCESS); 3281 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3282 } 3283 3284 /* 3285 * sip_sis900_mii_writereg: [mii interface function] 3286 * 3287 * Write a PHY register on the MII. 3288 */ 3289 static void 3290 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3291 { 3292 struct sip_softc *sc = (struct sip_softc *) self; 3293 u_int32_t enphy; 3294 3295 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3296 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3297 phy, reg, val); 3298 return; 3299 } 3300 3301 #ifndef SIS900_MII_RESTRICT 3302 /* 3303 * The SiS 900 has only an internal PHY on the MII. Only allow 3304 * MII address 0. 3305 */ 3306 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3307 return; 3308 #endif 3309 3310 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3311 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3312 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3313 do { 3314 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3315 } while (enphy & ENPHY_ACCESS); 3316 } 3317 3318 /* 3319 * sip_sis900_mii_statchg: [mii interface function] 3320 * 3321 * Callback from MII layer when media changes. 3322 */ 3323 static void 3324 SIP_DECL(sis900_mii_statchg)(struct device *self) 3325 { 3326 struct sip_softc *sc = (struct sip_softc *) self; 3327 struct mii_data *mii = &sc->sc_mii; 3328 u_int32_t flowctl; 3329 3330 /* 3331 * Get flow control negotiation result. 3332 */ 3333 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3334 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3335 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3336 mii->mii_media_active &= ~IFM_ETH_FMASK; 3337 } 3338 3339 /* 3340 * Update TXCFG for full-duplex operation. 3341 */ 3342 if ((mii->mii_media_active & IFM_FDX) != 0) 3343 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3344 else 3345 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3346 3347 /* 3348 * Update RXCFG for full-duplex or loopback. 3349 */ 3350 if ((mii->mii_media_active & IFM_FDX) != 0 || 3351 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3352 sc->sc_rxcfg |= RXCFG_ATX; 3353 else 3354 sc->sc_rxcfg &= ~RXCFG_ATX; 3355 3356 /* 3357 * Update IMR for use of 802.3x flow control. 3358 */ 3359 if (sc->sc_flowflags & IFM_FLOW) { 3360 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3361 flowctl = FLOWCTL_FLOWEN; 3362 } else { 3363 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3364 flowctl = 0; 3365 } 3366 3367 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3368 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3369 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3370 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3371 } 3372 3373 /* 3374 * sip_dp83815_mii_readreg: [mii interface function] 3375 * 3376 * Read a PHY register on the MII. 3377 */ 3378 static int 3379 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3380 { 3381 struct sip_softc *sc = (struct sip_softc *) self; 3382 u_int32_t val; 3383 3384 /* 3385 * The DP83815 only has an internal PHY. Only allow 3386 * MII address 0. 3387 */ 3388 if (phy != 0) 3389 return (0); 3390 3391 /* 3392 * Apparently, after a reset, the DP83815 can take a while 3393 * to respond. During this recovery period, the BMSR returns 3394 * a value of 0. Catch this -- it's not supposed to happen 3395 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3396 * PHY to come back to life. 3397 * 3398 * This works out because the BMSR is the first register 3399 * read during the PHY probe process. 3400 */ 3401 do { 3402 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3403 } while (reg == MII_BMSR && val == 0); 3404 3405 return (val & 0xffff); 3406 } 3407 3408 /* 3409 * sip_dp83815_mii_writereg: [mii interface function] 3410 * 3411 * Write a PHY register to the MII. 3412 */ 3413 static void 3414 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3415 { 3416 struct sip_softc *sc = (struct sip_softc *) self; 3417 3418 /* 3419 * The DP83815 only has an internal PHY. Only allow 3420 * MII address 0. 3421 */ 3422 if (phy != 0) 3423 return; 3424 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3426 } 3427 3428 /* 3429 * sip_dp83815_mii_statchg: [mii interface function] 3430 * 3431 * Callback from MII layer when media changes. 3432 */ 3433 static void 3434 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3435 { 3436 struct sip_softc *sc = (struct sip_softc *) self; 3437 3438 /* 3439 * Update TXCFG for full-duplex operation. 3440 */ 3441 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3442 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3443 else 3444 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3445 3446 /* 3447 * Update RXCFG for full-duplex or loopback. 3448 */ 3449 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3450 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3451 sc->sc_rxcfg |= RXCFG_ATX; 3452 else 3453 sc->sc_rxcfg &= ~RXCFG_ATX; 3454 3455 /* 3456 * XXX 802.3x flow control. 3457 */ 3458 3459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3460 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3461 3462 /* 3463 * Some DP83815s experience problems when used with short 3464 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3465 * sequence adjusts the DSP's signal attenuation to fix the 3466 * problem. 3467 */ 3468 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3469 uint32_t reg; 3470 3471 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3472 3473 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3474 reg &= 0x0fff; 3475 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3476 delay(100); 3477 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3478 reg &= 0x00ff; 3479 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3480 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3481 0x00e8); 3482 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3483 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3484 reg | 0x20); 3485 } 3486 3487 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3488 } 3489 } 3490 #endif /* DP83820 */ 3491 3492 #if defined(DP83820) 3493 static void 3494 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3495 const struct pci_attach_args *pa, u_int8_t *enaddr) 3496 { 3497 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3498 u_int8_t cksum, *e, match; 3499 int i; 3500 3501 /* 3502 * EEPROM data format for the DP83820 can be found in 3503 * the DP83820 manual, section 4.2.4. 3504 */ 3505 3506 SIP_DECL(read_eeprom)(sc, 0, 3507 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3508 3509 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3510 match = ~(match - 1); 3511 3512 cksum = 0x55; 3513 e = (u_int8_t *) eeprom_data; 3514 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3515 cksum += *e++; 3516 3517 if (cksum != match) 3518 printf("%s: Checksum (%x) mismatch (%x)", 3519 sc->sc_dev.dv_xname, cksum, match); 3520 3521 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3522 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3523 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3524 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3525 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3526 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3527 } 3528 #else /* ! DP83820 */ 3529 static void 3530 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3531 { 3532 int i; 3533 3534 /* 3535 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3536 * a reason, but I don't know it. 3537 */ 3538 for (i = 0; i < 10; i++) 3539 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3540 } 3541 3542 static void 3543 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3544 const struct pci_attach_args *pa, u_int8_t *enaddr) 3545 { 3546 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3547 3548 switch (sc->sc_rev) { 3549 case SIS_REV_630S: 3550 case SIS_REV_630E: 3551 case SIS_REV_630EA1: 3552 case SIS_REV_630ET: 3553 case SIS_REV_635: 3554 /* 3555 * The MAC address for the on-board Ethernet of 3556 * the SiS 630 chipset is in the NVRAM. Kick 3557 * the chip into re-loading it from NVRAM, and 3558 * read the MAC address out of the filter registers. 3559 */ 3560 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3561 3562 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3563 RFCR_RFADDR_NODE0); 3564 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3565 0xffff; 3566 3567 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3568 RFCR_RFADDR_NODE2); 3569 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3570 0xffff; 3571 3572 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3573 RFCR_RFADDR_NODE4); 3574 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3575 0xffff; 3576 break; 3577 3578 case SIS_REV_960: 3579 { 3580 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3581 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3582 3583 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3584 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3585 3586 int waittime, i; 3587 3588 /* Allow to read EEPROM from LAN. It is shared 3589 * between a 1394 controller and the NIC and each 3590 * time we access it, we need to set SIS_EECMD_REQ. 3591 */ 3592 SIS_SET_EROMAR(sc, EROMAR_REQ); 3593 3594 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3595 /* Force EEPROM to idle state. */ 3596 3597 /* 3598 * XXX-cube This is ugly. I'll look for docs about it. 3599 */ 3600 SIS_SET_EROMAR(sc, EROMAR_EECS); 3601 SIP_DECL(sis900_eeprom_delay)(sc); 3602 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3603 SIS_SET_EROMAR(sc, EROMAR_EESK); 3604 SIP_DECL(sis900_eeprom_delay)(sc); 3605 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3606 SIP_DECL(sis900_eeprom_delay)(sc); 3607 } 3608 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3609 SIP_DECL(sis900_eeprom_delay)(sc); 3610 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3611 3612 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3613 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3614 sizeof(myea) / sizeof(myea[0]), myea); 3615 break; 3616 } 3617 DELAY(1); 3618 } 3619 3620 /* 3621 * Set SIS_EECTL_CLK to high, so a other master 3622 * can operate on the i2c bus. 3623 */ 3624 SIS_SET_EROMAR(sc, EROMAR_EESK); 3625 3626 /* Refuse EEPROM access by LAN */ 3627 SIS_SET_EROMAR(sc, EROMAR_DONE); 3628 } break; 3629 3630 default: 3631 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3632 sizeof(myea) / sizeof(myea[0]), myea); 3633 } 3634 3635 enaddr[0] = myea[0] & 0xff; 3636 enaddr[1] = myea[0] >> 8; 3637 enaddr[2] = myea[1] & 0xff; 3638 enaddr[3] = myea[1] >> 8; 3639 enaddr[4] = myea[2] & 0xff; 3640 enaddr[5] = myea[2] >> 8; 3641 } 3642 3643 /* Table and macro to bit-reverse an octet. */ 3644 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3645 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3646 3647 static void 3648 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3649 const struct pci_attach_args *pa, u_int8_t *enaddr) 3650 { 3651 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3652 u_int8_t cksum, *e, match; 3653 int i; 3654 3655 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3656 sizeof(eeprom_data[0]), eeprom_data); 3657 3658 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3659 match = ~(match - 1); 3660 3661 cksum = 0x55; 3662 e = (u_int8_t *) eeprom_data; 3663 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3664 cksum += *e++; 3665 } 3666 if (cksum != match) { 3667 printf("%s: Checksum (%x) mismatch (%x)", 3668 sc->sc_dev.dv_xname, cksum, match); 3669 } 3670 3671 /* 3672 * Unrolled because it makes slightly more sense this way. 3673 * The DP83815 stores the MAC address in bit 0 of word 6 3674 * through bit 15 of word 8. 3675 */ 3676 ea = &eeprom_data[6]; 3677 enaddr[0] = ((*ea & 0x1) << 7); 3678 ea++; 3679 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3680 enaddr[1] = ((*ea & 0x1FE) >> 1); 3681 enaddr[2] = ((*ea & 0x1) << 7); 3682 ea++; 3683 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3684 enaddr[3] = ((*ea & 0x1FE) >> 1); 3685 enaddr[4] = ((*ea & 0x1) << 7); 3686 ea++; 3687 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3688 enaddr[5] = ((*ea & 0x1FE) >> 1); 3689 3690 /* 3691 * In case that's not weird enough, we also need to reverse 3692 * the bits in each byte. This all actually makes more sense 3693 * if you think about the EEPROM storage as an array of bits 3694 * being shifted into bytes, but that's not how we're looking 3695 * at it here... 3696 */ 3697 for (i = 0; i < 6 ;i++) 3698 enaddr[i] = bbr(enaddr[i]); 3699 } 3700 #endif /* DP83820 */ 3701 3702 /* 3703 * sip_mediastatus: [ifmedia interface function] 3704 * 3705 * Get the current interface media status. 3706 */ 3707 static void 3708 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3709 { 3710 struct sip_softc *sc = ifp->if_softc; 3711 3712 mii_pollstat(&sc->sc_mii); 3713 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3714 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3715 sc->sc_flowflags; 3716 } 3717 3718 /* 3719 * sip_mediachange: [ifmedia interface function] 3720 * 3721 * Set hardware to newly-selected media. 3722 */ 3723 static int 3724 SIP_DECL(mediachange)(struct ifnet *ifp) 3725 { 3726 struct sip_softc *sc = ifp->if_softc; 3727 3728 if (ifp->if_flags & IFF_UP) 3729 mii_mediachg(&sc->sc_mii); 3730 return (0); 3731 } 3732
Indexes created Tue Sep 30 11:09:46 GMT 2025