if_sip.c revision 1.104.2.2
1 /* $NetBSD: if_sip.c,v 1.104.2.2 2006/04/11 11:55:17 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.104.2.2 2006/04/11 11:55:17 yamt Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 /* values of interface state at last init */ 313 struct { 314 /* if_capenable */ 315 uint64_t if_capenable; 316 /* ec_capenable */ 317 int ec_capenable; 318 /* VLAN_ATTACHED */ 319 int is_vlan; 320 } sc_prev; 321 322 short sc_if_flags; 323 324 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 325 #if defined(DP83820) 326 int sc_rxdiscard; 327 int sc_rxlen; 328 struct mbuf *sc_rxhead; 329 struct mbuf *sc_rxtail; 330 struct mbuf **sc_rxtailp; 331 #endif /* DP83820 */ 332 333 #if NRND > 0 334 rndsource_element_t rnd_source; /* random source */ 335 #endif 336 }; 337 338 #ifdef DP83820 339 #define SIP_RXCHAIN_RESET(sc) \ 340 do { \ 341 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 342 *(sc)->sc_rxtailp = NULL; \ 343 (sc)->sc_rxlen = 0; \ 344 } while (/*CONSTCOND*/0) 345 346 #define SIP_RXCHAIN_LINK(sc, m) \ 347 do { \ 348 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 349 (sc)->sc_rxtailp = &(m)->m_next; \ 350 } while (/*CONSTCOND*/0) 351 #endif /* DP83820 */ 352 353 #ifdef SIP_EVENT_COUNTERS 354 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 355 #else 356 #define SIP_EVCNT_INCR(ev) /* nothing */ 357 #endif 358 359 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 360 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 361 362 #define SIP_CDTXSYNC(sc, x, n, ops) \ 363 do { \ 364 int __x, __n; \ 365 \ 366 __x = (x); \ 367 __n = (n); \ 368 \ 369 /* If it will wrap around, sync to the end of the ring. */ \ 370 if ((__x + __n) > SIP_NTXDESC) { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 373 (SIP_NTXDESC - __x), (ops)); \ 374 __n -= (SIP_NTXDESC - __x); \ 375 __x = 0; \ 376 } \ 377 \ 378 /* Now sync whatever is left. */ \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 381 } while (0) 382 383 #define SIP_CDRXSYNC(sc, x, ops) \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 386 387 #ifdef DP83820 388 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 389 #define SIP_RXBUF_LEN (MCLBYTES - 8) 390 #else 391 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 392 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 393 #endif 394 #define SIP_INIT_RXDESC(sc, x) \ 395 do { \ 396 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 397 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 398 \ 399 __sipd->sipd_link = \ 400 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 401 __sipd->sipd_bufptr = \ 402 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 403 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 404 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 405 SIP_INIT_RXDESC_EXTSTS \ 406 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 407 } while (0) 408 409 #define SIP_CHIP_VERS(sc, v, p, r) \ 410 ((sc)->sc_model->sip_vendor == (v) && \ 411 (sc)->sc_model->sip_product == (p) && \ 412 (sc)->sc_rev == (r)) 413 414 #define SIP_CHIP_MODEL(sc, v, p) \ 415 ((sc)->sc_model->sip_vendor == (v) && \ 416 (sc)->sc_model->sip_product == (p)) 417 418 #if !defined(DP83820) 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 #endif 422 423 #define SIP_TIMEOUT 1000 424 425 static void SIP_DECL(start)(struct ifnet *); 426 static void SIP_DECL(watchdog)(struct ifnet *); 427 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 428 static int SIP_DECL(init)(struct ifnet *); 429 static void SIP_DECL(stop)(struct ifnet *, int); 430 431 static void SIP_DECL(shutdown)(void *); 432 433 static void SIP_DECL(reset)(struct sip_softc *); 434 static void SIP_DECL(rxdrain)(struct sip_softc *); 435 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 436 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 437 u_int16_t *); 438 static void SIP_DECL(tick)(void *); 439 440 #if !defined(DP83820) 441 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 442 #endif /* ! DP83820 */ 443 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 444 445 #if defined(DP83820) 446 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 447 const struct pci_attach_args *, u_int8_t *); 448 #else 449 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 450 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 451 const struct pci_attach_args *, u_int8_t *); 452 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 453 const struct pci_attach_args *, u_int8_t *); 454 #endif /* DP83820 */ 455 456 static int SIP_DECL(intr)(void *); 457 static void SIP_DECL(txintr)(struct sip_softc *); 458 static void SIP_DECL(rxintr)(struct sip_softc *); 459 460 #if defined(DP83820) 461 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 462 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 463 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 464 #else 465 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 466 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 467 static void SIP_DECL(sis900_mii_statchg)(struct device *); 468 469 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 470 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 471 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 472 #endif /* DP83820 */ 473 474 static int SIP_DECL(mediachange)(struct ifnet *); 475 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 476 477 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 478 static void SIP_DECL(attach)(struct device *, struct device *, void *); 479 480 int SIP_DECL(copy_small) = 0; 481 482 #ifdef DP83820 483 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 484 gsip_match, gsip_attach, NULL, NULL); 485 #else 486 CFATTACH_DECL(sip, sizeof(struct sip_softc), 487 sip_match, sip_attach, NULL, NULL); 488 #endif 489 490 /* 491 * Descriptions of the variants of the SiS900. 492 */ 493 struct sip_variant { 494 int (*sipv_mii_readreg)(struct device *, int, int); 495 void (*sipv_mii_writereg)(struct device *, int, int, int); 496 void (*sipv_mii_statchg)(struct device *); 497 void (*sipv_set_filter)(struct sip_softc *); 498 void (*sipv_read_macaddr)(struct sip_softc *, 499 const struct pci_attach_args *, u_int8_t *); 500 }; 501 502 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 503 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 504 505 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 506 SIP_DECL(mii_bitbang_read), 507 SIP_DECL(mii_bitbang_write), 508 { 509 EROMAR_MDIO, /* MII_BIT_MDO */ 510 EROMAR_MDIO, /* MII_BIT_MDI */ 511 EROMAR_MDC, /* MII_BIT_MDC */ 512 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 513 0, /* MII_BIT_DIR_PHY_HOST */ 514 } 515 }; 516 517 #if defined(DP83820) 518 static const struct sip_variant SIP_DECL(variant_dp83820) = { 519 SIP_DECL(dp83820_mii_readreg), 520 SIP_DECL(dp83820_mii_writereg), 521 SIP_DECL(dp83820_mii_statchg), 522 SIP_DECL(dp83815_set_filter), 523 SIP_DECL(dp83820_read_macaddr), 524 }; 525 #else 526 static const struct sip_variant SIP_DECL(variant_sis900) = { 527 SIP_DECL(sis900_mii_readreg), 528 SIP_DECL(sis900_mii_writereg), 529 SIP_DECL(sis900_mii_statchg), 530 SIP_DECL(sis900_set_filter), 531 SIP_DECL(sis900_read_macaddr), 532 }; 533 534 static const struct sip_variant SIP_DECL(variant_dp83815) = { 535 SIP_DECL(dp83815_mii_readreg), 536 SIP_DECL(dp83815_mii_writereg), 537 SIP_DECL(dp83815_mii_statchg), 538 SIP_DECL(dp83815_set_filter), 539 SIP_DECL(dp83815_read_macaddr), 540 }; 541 #endif /* DP83820 */ 542 543 /* 544 * Devices supported by this driver. 545 */ 546 static const struct sip_product { 547 pci_vendor_id_t sip_vendor; 548 pci_product_id_t sip_product; 549 const char *sip_name; 550 const struct sip_variant *sip_variant; 551 } SIP_DECL(products)[] = { 552 #if defined(DP83820) 553 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 554 "NatSemi DP83820 Gigabit Ethernet", 555 &SIP_DECL(variant_dp83820) }, 556 #else 557 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 558 "SiS 900 10/100 Ethernet", 559 &SIP_DECL(variant_sis900) }, 560 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 561 "SiS 7016 10/100 Ethernet", 562 &SIP_DECL(variant_sis900) }, 563 564 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 565 "NatSemi DP83815 10/100 Ethernet", 566 &SIP_DECL(variant_dp83815) }, 567 #endif /* DP83820 */ 568 569 { 0, 0, 570 NULL, 571 NULL }, 572 }; 573 574 static const struct sip_product * 575 SIP_DECL(lookup)(const struct pci_attach_args *pa) 576 { 577 const struct sip_product *sip; 578 579 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 580 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 581 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 582 return (sip); 583 } 584 return (NULL); 585 } 586 587 #ifdef DP83820 588 /* 589 * I really hate stupid hardware vendors. There's a bit in the EEPROM 590 * which indicates if the card can do 64-bit data transfers. Unfortunately, 591 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 592 * which means we try to use 64-bit data transfers on those cards if we 593 * happen to be plugged into a 32-bit slot. 594 * 595 * What we do is use this table of cards known to be 64-bit cards. If 596 * you have a 64-bit card who's subsystem ID is not listed in this table, 597 * send the output of "pcictl dump ..." of the device to me so that your 598 * card will use the 64-bit data path when plugged into a 64-bit slot. 599 * 600 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 601 * June 30, 2002 602 */ 603 static int 604 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 605 { 606 static const struct { 607 pci_vendor_id_t c64_vendor; 608 pci_product_id_t c64_product; 609 } card64[] = { 610 /* Asante GigaNIX */ 611 { 0x128a, 0x0002 }, 612 613 /* Accton EN1407-T, Planex GN-1000TE */ 614 { 0x1113, 0x1407 }, 615 616 /* Netgear GA-621 */ 617 { 0x1385, 0x621a }, 618 619 /* SMC EZ Card */ 620 { 0x10b8, 0x9462 }, 621 622 { 0, 0} 623 }; 624 pcireg_t subsys; 625 int i; 626 627 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 628 629 for (i = 0; card64[i].c64_vendor != 0; i++) { 630 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 631 PCI_PRODUCT(subsys) == card64[i].c64_product) 632 return (1); 633 } 634 635 return (0); 636 } 637 #endif /* DP83820 */ 638 639 static int 640 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 641 { 642 struct pci_attach_args *pa = aux; 643 644 if (SIP_DECL(lookup)(pa) != NULL) 645 return (1); 646 647 return (0); 648 } 649 650 static void 651 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 652 { 653 struct sip_softc *sc = (struct sip_softc *) self; 654 struct pci_attach_args *pa = aux; 655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 656 pci_chipset_tag_t pc = pa->pa_pc; 657 pci_intr_handle_t ih; 658 const char *intrstr = NULL; 659 bus_space_tag_t iot, memt; 660 bus_space_handle_t ioh, memh; 661 bus_dma_segment_t seg; 662 int ioh_valid, memh_valid; 663 int i, rseg, error; 664 const struct sip_product *sip; 665 pcireg_t pmode; 666 u_int8_t enaddr[ETHER_ADDR_LEN]; 667 int pmreg; 668 #ifdef DP83820 669 pcireg_t memtype; 670 u_int32_t reg; 671 #endif /* DP83820 */ 672 673 callout_init(&sc->sc_tick_ch); 674 675 sip = SIP_DECL(lookup)(pa); 676 if (sip == NULL) { 677 printf("\n"); 678 panic(SIP_STR(attach) ": impossible"); 679 } 680 sc->sc_rev = PCI_REVISION(pa->pa_class); 681 682 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 683 684 sc->sc_model = sip; 685 686 /* 687 * XXX Work-around broken PXE firmware on some boards. 688 * 689 * The DP83815 shares an address decoder with the MEM BAR 690 * and the ROM BAR. Make sure the ROM BAR is disabled, 691 * so that memory mapped access works. 692 */ 693 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 694 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 695 ~PCI_MAPREG_ROM_ENABLE); 696 697 /* 698 * Map the device. 699 */ 700 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 701 PCI_MAPREG_TYPE_IO, 0, 702 &iot, &ioh, NULL, NULL) == 0); 703 #ifdef DP83820 704 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 705 switch (memtype) { 706 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 707 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 708 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 709 memtype, 0, &memt, &memh, NULL, NULL) == 0); 710 break; 711 default: 712 memh_valid = 0; 713 } 714 #else 715 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 716 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 717 &memt, &memh, NULL, NULL) == 0); 718 #endif /* DP83820 */ 719 720 if (memh_valid) { 721 sc->sc_st = memt; 722 sc->sc_sh = memh; 723 } else if (ioh_valid) { 724 sc->sc_st = iot; 725 sc->sc_sh = ioh; 726 } else { 727 printf("%s: unable to map device registers\n", 728 sc->sc_dev.dv_xname); 729 return; 730 } 731 732 sc->sc_dmat = pa->pa_dmat; 733 734 /* 735 * Make sure bus mastering is enabled. Also make sure 736 * Write/Invalidate is enabled if we're allowed to use it. 737 */ 738 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 739 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 740 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 741 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 742 pmreg | PCI_COMMAND_MASTER_ENABLE); 743 744 /* Get it out of power save mode if needed. */ 745 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 746 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 747 PCI_PMCSR_STATE_MASK; 748 if (pmode == PCI_PMCSR_STATE_D3) { 749 /* 750 * The card has lost all configuration data in 751 * this state, so punt. 752 */ 753 printf("%s: unable to wake up from power state D3\n", 754 sc->sc_dev.dv_xname); 755 return; 756 } 757 if (pmode != PCI_PMCSR_STATE_D0) { 758 printf("%s: waking up from power state D%d\n", 759 sc->sc_dev.dv_xname, pmode); 760 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 761 PCI_PMCSR_STATE_D0); 762 } 763 } 764 765 /* 766 * Map and establish our interrupt. 767 */ 768 if (pci_intr_map(pa, &ih)) { 769 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 770 return; 771 } 772 intrstr = pci_intr_string(pc, ih); 773 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 774 if (sc->sc_ih == NULL) { 775 printf("%s: unable to establish interrupt", 776 sc->sc_dev.dv_xname); 777 if (intrstr != NULL) 778 printf(" at %s", intrstr); 779 printf("\n"); 780 return; 781 } 782 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 783 784 SIMPLEQ_INIT(&sc->sc_txfreeq); 785 SIMPLEQ_INIT(&sc->sc_txdirtyq); 786 787 /* 788 * Allocate the control data structures, and create and load the 789 * DMA map for it. 790 */ 791 if ((error = bus_dmamem_alloc(sc->sc_dmat, 792 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 793 0)) != 0) { 794 printf("%s: unable to allocate control data, error = %d\n", 795 sc->sc_dev.dv_xname, error); 796 goto fail_0; 797 } 798 799 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 800 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 801 BUS_DMA_COHERENT)) != 0) { 802 printf("%s: unable to map control data, error = %d\n", 803 sc->sc_dev.dv_xname, error); 804 goto fail_1; 805 } 806 807 if ((error = bus_dmamap_create(sc->sc_dmat, 808 sizeof(struct sip_control_data), 1, 809 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 810 printf("%s: unable to create control data DMA map, " 811 "error = %d\n", sc->sc_dev.dv_xname, error); 812 goto fail_2; 813 } 814 815 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 816 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 817 0)) != 0) { 818 printf("%s: unable to load control data DMA map, error = %d\n", 819 sc->sc_dev.dv_xname, error); 820 goto fail_3; 821 } 822 823 /* 824 * Create the transmit buffer DMA maps. 825 */ 826 for (i = 0; i < SIP_TXQUEUELEN; i++) { 827 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 828 SIP_NTXSEGS, MCLBYTES, 0, 0, 829 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 830 printf("%s: unable to create tx DMA map %d, " 831 "error = %d\n", sc->sc_dev.dv_xname, i, error); 832 goto fail_4; 833 } 834 } 835 836 /* 837 * Create the receive buffer DMA maps. 838 */ 839 for (i = 0; i < SIP_NRXDESC; i++) { 840 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 841 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 842 printf("%s: unable to create rx DMA map %d, " 843 "error = %d\n", sc->sc_dev.dv_xname, i, error); 844 goto fail_5; 845 } 846 sc->sc_rxsoft[i].rxs_mbuf = NULL; 847 } 848 849 /* 850 * Reset the chip to a known state. 851 */ 852 SIP_DECL(reset)(sc); 853 854 /* 855 * Read the Ethernet address from the EEPROM. This might 856 * also fetch other stuff from the EEPROM and stash it 857 * in the softc. 858 */ 859 sc->sc_cfg = 0; 860 #if !defined(DP83820) 861 if (SIP_SIS900_REV(sc,SIS_REV_635) || 862 SIP_SIS900_REV(sc,SIS_REV_900B)) 863 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 864 865 if (SIP_SIS900_REV(sc,SIS_REV_635) || 866 SIP_SIS900_REV(sc,SIS_REV_960) || 867 SIP_SIS900_REV(sc,SIS_REV_900B)) 868 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 869 SIP_CFG) & CFG_EDBMASTEN); 870 #endif 871 872 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 873 874 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 875 ether_sprintf(enaddr)); 876 877 /* 878 * Initialize the configuration register: aggressive PCI 879 * bus request algorithm, default backoff, default OW timer, 880 * default parity error detection. 881 * 882 * NOTE: "Big endian mode" is useless on the SiS900 and 883 * friends -- it affects packet data, not descriptors. 884 */ 885 #ifdef DP83820 886 /* 887 * Cause the chip to load configuration data from the EEPROM. 888 */ 889 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 890 for (i = 0; i < 10000; i++) { 891 delay(10); 892 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 893 PTSCR_EELOAD_EN) == 0) 894 break; 895 } 896 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 897 PTSCR_EELOAD_EN) { 898 printf("%s: timeout loading configuration from EEPROM\n", 899 sc->sc_dev.dv_xname); 900 return; 901 } 902 903 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 904 905 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 906 if (reg & CFG_PCI64_DET) { 907 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 908 /* 909 * Check to see if this card is 64-bit. If so, enable 64-bit 910 * data transfers. 911 * 912 * We can't use the DATA64_EN bit in the EEPROM, because 913 * vendors of 32-bit cards fail to clear that bit in many 914 * cases (yet the card still detects that it's in a 64-bit 915 * slot; go figure). 916 */ 917 if (SIP_DECL(check_64bit)(pa)) { 918 sc->sc_cfg |= CFG_DATA64_EN; 919 printf(", using 64-bit data transfers"); 920 } 921 printf("\n"); 922 } 923 924 /* 925 * XXX Need some PCI flags indicating support for 926 * XXX 64-bit addressing. 927 */ 928 #if 0 929 if (reg & CFG_M64ADDR) 930 sc->sc_cfg |= CFG_M64ADDR; 931 if (reg & CFG_T64ADDR) 932 sc->sc_cfg |= CFG_T64ADDR; 933 #endif 934 935 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 936 const char *sep = ""; 937 printf("%s: using ", sc->sc_dev.dv_xname); 938 if (reg & CFG_EXT_125) { 939 sc->sc_cfg |= CFG_EXT_125; 940 printf("%s125MHz clock", sep); 941 sep = ", "; 942 } 943 if (reg & CFG_TBI_EN) { 944 sc->sc_cfg |= CFG_TBI_EN; 945 printf("%sten-bit interface", sep); 946 sep = ", "; 947 } 948 printf("\n"); 949 } 950 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 951 (reg & CFG_MRM_DIS) != 0) 952 sc->sc_cfg |= CFG_MRM_DIS; 953 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 954 (reg & CFG_MWI_DIS) != 0) 955 sc->sc_cfg |= CFG_MWI_DIS; 956 957 /* 958 * Use the extended descriptor format on the DP83820. This 959 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 960 * checksumming. 961 */ 962 sc->sc_cfg |= CFG_EXTSTS_EN; 963 #endif /* DP83820 */ 964 965 /* 966 * Initialize our media structures and probe the MII. 967 */ 968 sc->sc_mii.mii_ifp = ifp; 969 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 970 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 971 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 972 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 973 SIP_DECL(mediastatus)); 974 975 /* 976 * XXX We cannot handle flow control on the DP83815. 977 */ 978 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 979 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 980 MII_OFFSET_ANY, 0); 981 else 982 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 983 MII_OFFSET_ANY, MIIF_DOPAUSE); 984 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 985 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 986 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 987 } else 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 989 990 ifp = &sc->sc_ethercom.ec_if; 991 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 992 ifp->if_softc = sc; 993 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 994 sc->sc_if_flags = ifp->if_flags; 995 ifp->if_ioctl = SIP_DECL(ioctl); 996 ifp->if_start = SIP_DECL(start); 997 ifp->if_watchdog = SIP_DECL(watchdog); 998 ifp->if_init = SIP_DECL(init); 999 ifp->if_stop = SIP_DECL(stop); 1000 IFQ_SET_READY(&ifp->if_snd); 1001 1002 /* 1003 * We can support 802.1Q VLAN-sized frames. 1004 */ 1005 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1006 1007 #ifdef DP83820 1008 /* 1009 * And the DP83820 can do VLAN tagging in hardware, and 1010 * support the jumbo Ethernet MTU. 1011 */ 1012 sc->sc_ethercom.ec_capabilities |= 1013 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1014 1015 /* 1016 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1017 * in hardware. 1018 */ 1019 ifp->if_capabilities |= 1020 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1021 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1022 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1023 #endif /* DP83820 */ 1024 1025 /* 1026 * Attach the interface. 1027 */ 1028 if_attach(ifp); 1029 ether_ifattach(ifp, enaddr); 1030 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1031 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1032 sc->sc_prev.if_capenable = ifp->if_capenable; 1033 #if NRND > 0 1034 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1035 RND_TYPE_NET, 0); 1036 #endif 1037 1038 /* 1039 * The number of bytes that must be available in 1040 * the Tx FIFO before the bus master can DMA more 1041 * data into the FIFO. 1042 */ 1043 sc->sc_tx_fill_thresh = 64 / 32; 1044 1045 /* 1046 * Start at a drain threshold of 512 bytes. We will 1047 * increase it if a DMA underrun occurs. 1048 * 1049 * XXX The minimum value of this variable should be 1050 * tuned. We may be able to improve performance 1051 * by starting with a lower value. That, however, 1052 * may trash the first few outgoing packets if the 1053 * PCI bus is saturated. 1054 */ 1055 #ifdef DP83820 1056 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1057 #else 1058 sc->sc_tx_drain_thresh = 1504 / 32; 1059 #endif 1060 1061 /* 1062 * Initialize the Rx FIFO drain threshold. 1063 * 1064 * This is in units of 8 bytes. 1065 * 1066 * We should never set this value lower than 2; 14 bytes are 1067 * required to filter the packet. 1068 */ 1069 sc->sc_rx_drain_thresh = 128 / 8; 1070 1071 #ifdef SIP_EVENT_COUNTERS 1072 /* 1073 * Attach event counters. 1074 */ 1075 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1076 NULL, sc->sc_dev.dv_xname, "txsstall"); 1077 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1078 NULL, sc->sc_dev.dv_xname, "txdstall"); 1079 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1080 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1081 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1082 NULL, sc->sc_dev.dv_xname, "txdintr"); 1083 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1084 NULL, sc->sc_dev.dv_xname, "txiintr"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1086 NULL, sc->sc_dev.dv_xname, "rxintr"); 1087 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1088 NULL, sc->sc_dev.dv_xname, "hiberr"); 1089 #ifndef DP83820 1090 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1091 NULL, sc->sc_dev.dv_xname, "rxpause"); 1092 #endif /* !DP83820 */ 1093 #ifdef DP83820 1094 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1095 NULL, sc->sc_dev.dv_xname, "rxpause"); 1096 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1097 NULL, sc->sc_dev.dv_xname, "txpause"); 1098 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1099 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1100 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1101 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1102 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1103 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1104 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1105 NULL, sc->sc_dev.dv_xname, "txipsum"); 1106 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1107 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1108 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1109 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1110 #endif /* DP83820 */ 1111 #endif /* SIP_EVENT_COUNTERS */ 1112 1113 /* 1114 * Make sure the interface is shutdown during reboot. 1115 */ 1116 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1117 if (sc->sc_sdhook == NULL) 1118 printf("%s: WARNING: unable to establish shutdown hook\n", 1119 sc->sc_dev.dv_xname); 1120 return; 1121 1122 /* 1123 * Free any resources we've allocated during the failed attach 1124 * attempt. Do this in reverse order and fall through. 1125 */ 1126 fail_5: 1127 for (i = 0; i < SIP_NRXDESC; i++) { 1128 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1129 bus_dmamap_destroy(sc->sc_dmat, 1130 sc->sc_rxsoft[i].rxs_dmamap); 1131 } 1132 fail_4: 1133 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1134 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1135 bus_dmamap_destroy(sc->sc_dmat, 1136 sc->sc_txsoft[i].txs_dmamap); 1137 } 1138 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1139 fail_3: 1140 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1141 fail_2: 1142 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1143 sizeof(struct sip_control_data)); 1144 fail_1: 1145 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1146 fail_0: 1147 return; 1148 } 1149 1150 /* 1151 * sip_shutdown: 1152 * 1153 * Make sure the interface is stopped at reboot time. 1154 */ 1155 static void 1156 SIP_DECL(shutdown)(void *arg) 1157 { 1158 struct sip_softc *sc = arg; 1159 1160 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1161 } 1162 1163 /* 1164 * sip_start: [ifnet interface function] 1165 * 1166 * Start packet transmission on the interface. 1167 */ 1168 static void 1169 SIP_DECL(start)(struct ifnet *ifp) 1170 { 1171 struct sip_softc *sc = ifp->if_softc; 1172 struct mbuf *m0; 1173 #ifndef DP83820 1174 struct mbuf *m; 1175 #endif 1176 struct sip_txsoft *txs; 1177 bus_dmamap_t dmamap; 1178 int error, nexttx, lasttx, seg; 1179 int ofree = sc->sc_txfree; 1180 #if 0 1181 int firsttx = sc->sc_txnext; 1182 #endif 1183 #ifdef DP83820 1184 struct m_tag *mtag; 1185 u_int32_t extsts; 1186 #endif 1187 1188 #ifndef DP83820 1189 /* 1190 * If we've been told to pause, don't transmit any more packets. 1191 */ 1192 if (sc->sc_paused) 1193 ifp->if_flags |= IFF_OACTIVE; 1194 #endif 1195 1196 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1197 return; 1198 1199 /* 1200 * Loop through the send queue, setting up transmit descriptors 1201 * until we drain the queue, or use up all available transmit 1202 * descriptors. 1203 */ 1204 for (;;) { 1205 /* Get a work queue entry. */ 1206 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1207 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1208 break; 1209 } 1210 1211 /* 1212 * Grab a packet off the queue. 1213 */ 1214 IFQ_POLL(&ifp->if_snd, m0); 1215 if (m0 == NULL) 1216 break; 1217 #ifndef DP83820 1218 m = NULL; 1219 #endif 1220 1221 dmamap = txs->txs_dmamap; 1222 1223 #ifdef DP83820 1224 /* 1225 * Load the DMA map. If this fails, the packet either 1226 * didn't fit in the allotted number of segments, or we 1227 * were short on resources. For the too-many-segments 1228 * case, we simply report an error and drop the packet, 1229 * since we can't sanely copy a jumbo packet to a single 1230 * buffer. 1231 */ 1232 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1233 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1234 if (error) { 1235 if (error == EFBIG) { 1236 printf("%s: Tx packet consumes too many " 1237 "DMA segments, dropping...\n", 1238 sc->sc_dev.dv_xname); 1239 IFQ_DEQUEUE(&ifp->if_snd, m0); 1240 m_freem(m0); 1241 continue; 1242 } 1243 /* 1244 * Short on resources, just stop for now. 1245 */ 1246 break; 1247 } 1248 #else /* DP83820 */ 1249 /* 1250 * Load the DMA map. If this fails, the packet either 1251 * didn't fit in the alloted number of segments, or we 1252 * were short on resources. In this case, we'll copy 1253 * and try again. 1254 */ 1255 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1256 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1257 MGETHDR(m, M_DONTWAIT, MT_DATA); 1258 if (m == NULL) { 1259 printf("%s: unable to allocate Tx mbuf\n", 1260 sc->sc_dev.dv_xname); 1261 break; 1262 } 1263 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1264 if (m0->m_pkthdr.len > MHLEN) { 1265 MCLGET(m, M_DONTWAIT); 1266 if ((m->m_flags & M_EXT) == 0) { 1267 printf("%s: unable to allocate Tx " 1268 "cluster\n", sc->sc_dev.dv_xname); 1269 m_freem(m); 1270 break; 1271 } 1272 } 1273 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1274 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1275 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1276 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1277 if (error) { 1278 printf("%s: unable to load Tx buffer, " 1279 "error = %d\n", sc->sc_dev.dv_xname, error); 1280 break; 1281 } 1282 } 1283 #endif /* DP83820 */ 1284 1285 /* 1286 * Ensure we have enough descriptors free to describe 1287 * the packet. Note, we always reserve one descriptor 1288 * at the end of the ring as a termination point, to 1289 * prevent wrap-around. 1290 */ 1291 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1292 /* 1293 * Not enough free descriptors to transmit this 1294 * packet. We haven't committed anything yet, 1295 * so just unload the DMA map, put the packet 1296 * back on the queue, and punt. Notify the upper 1297 * layer that there are not more slots left. 1298 * 1299 * XXX We could allocate an mbuf and copy, but 1300 * XXX is it worth it? 1301 */ 1302 ifp->if_flags |= IFF_OACTIVE; 1303 bus_dmamap_unload(sc->sc_dmat, dmamap); 1304 #ifndef DP83820 1305 if (m != NULL) 1306 m_freem(m); 1307 #endif 1308 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1309 break; 1310 } 1311 1312 IFQ_DEQUEUE(&ifp->if_snd, m0); 1313 #ifndef DP83820 1314 if (m != NULL) { 1315 m_freem(m0); 1316 m0 = m; 1317 } 1318 #endif 1319 1320 /* 1321 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1322 */ 1323 1324 /* Sync the DMA map. */ 1325 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1326 BUS_DMASYNC_PREWRITE); 1327 1328 /* 1329 * Initialize the transmit descriptors. 1330 */ 1331 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1332 seg < dmamap->dm_nsegs; 1333 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1334 /* 1335 * If this is the first descriptor we're 1336 * enqueueing, don't set the OWN bit just 1337 * yet. That could cause a race condition. 1338 * We'll do it below. 1339 */ 1340 sc->sc_txdescs[nexttx].sipd_bufptr = 1341 htole32(dmamap->dm_segs[seg].ds_addr); 1342 sc->sc_txdescs[nexttx].sipd_cmdsts = 1343 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1344 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1345 #ifdef DP83820 1346 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1347 #endif /* DP83820 */ 1348 lasttx = nexttx; 1349 } 1350 1351 /* Clear the MORE bit on the last segment. */ 1352 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1353 1354 /* 1355 * If we're in the interrupt delay window, delay the 1356 * interrupt. 1357 */ 1358 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1359 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1360 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1361 htole32(CMDSTS_INTR); 1362 sc->sc_txwin = 0; 1363 } 1364 1365 #ifdef DP83820 1366 /* 1367 * If VLANs are enabled and the packet has a VLAN tag, set 1368 * up the descriptor to encapsulate the packet for us. 1369 * 1370 * This apparently has to be on the last descriptor of 1371 * the packet. 1372 */ 1373 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1374 sc->sc_txdescs[lasttx].sipd_extsts |= 1375 htole32(EXTSTS_VPKT | 1376 (VLAN_TAG_VALUE(mtag) & EXTSTS_VTCI)); 1377 } 1378 1379 /* 1380 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1381 * checksumming, set up the descriptor to do this work 1382 * for us. 1383 * 1384 * This apparently has to be on the first descriptor of 1385 * the packet. 1386 * 1387 * Byte-swap constants so the compiler can optimize. 1388 */ 1389 extsts = 0; 1390 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1391 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1392 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1393 extsts |= htole32(EXTSTS_IPPKT); 1394 } 1395 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1396 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1397 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1398 extsts |= htole32(EXTSTS_TCPPKT); 1399 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1400 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1401 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1402 extsts |= htole32(EXTSTS_UDPPKT); 1403 } 1404 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1405 #endif /* DP83820 */ 1406 1407 /* Sync the descriptors we're using. */ 1408 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1409 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1410 1411 /* 1412 * The entire packet is set up. Give the first descrptor 1413 * to the chip now. 1414 */ 1415 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1416 htole32(CMDSTS_OWN); 1417 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1418 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1419 1420 /* 1421 * Store a pointer to the packet so we can free it later, 1422 * and remember what txdirty will be once the packet is 1423 * done. 1424 */ 1425 txs->txs_mbuf = m0; 1426 txs->txs_firstdesc = sc->sc_txnext; 1427 txs->txs_lastdesc = lasttx; 1428 1429 /* Advance the tx pointer. */ 1430 sc->sc_txfree -= dmamap->dm_nsegs; 1431 sc->sc_txnext = nexttx; 1432 1433 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1434 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1435 1436 #if NBPFILTER > 0 1437 /* 1438 * Pass the packet to any BPF listeners. 1439 */ 1440 if (ifp->if_bpf) 1441 bpf_mtap(ifp->if_bpf, m0); 1442 #endif /* NBPFILTER > 0 */ 1443 } 1444 1445 if (txs == NULL || sc->sc_txfree == 0) { 1446 /* No more slots left; notify upper layer. */ 1447 ifp->if_flags |= IFF_OACTIVE; 1448 } 1449 1450 if (sc->sc_txfree != ofree) { 1451 /* 1452 * Start the transmit process. Note, the manual says 1453 * that if there are no pending transmissions in the 1454 * chip's internal queue (indicated by TXE being clear), 1455 * then the driver software must set the TXDP to the 1456 * first descriptor to be transmitted. However, if we 1457 * do this, it causes serious performance degredation on 1458 * the DP83820 under load, not setting TXDP doesn't seem 1459 * to adversely affect the SiS 900 or DP83815. 1460 * 1461 * Well, I guess it wouldn't be the first time a manual 1462 * has lied -- and they could be speaking of the NULL- 1463 * terminated descriptor list case, rather than OWN- 1464 * terminated rings. 1465 */ 1466 #if 0 1467 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1468 CR_TXE) == 0) { 1469 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1470 SIP_CDTXADDR(sc, firsttx)); 1471 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1472 } 1473 #else 1474 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1475 #endif 1476 1477 /* Set a watchdog timer in case the chip flakes out. */ 1478 #ifdef DP83820 1479 /* Gigabit autonegotiation takes 5 seconds. */ 1480 ifp->if_timer = 10; 1481 #else 1482 ifp->if_timer = 5; 1483 #endif 1484 } 1485 } 1486 1487 /* 1488 * sip_watchdog: [ifnet interface function] 1489 * 1490 * Watchdog timer handler. 1491 */ 1492 static void 1493 SIP_DECL(watchdog)(struct ifnet *ifp) 1494 { 1495 struct sip_softc *sc = ifp->if_softc; 1496 1497 /* 1498 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1499 * If we get a timeout, try and sweep up transmit descriptors. 1500 * If we manage to sweep them all up, ignore the lack of 1501 * interrupt. 1502 */ 1503 SIP_DECL(txintr)(sc); 1504 1505 if (sc->sc_txfree != SIP_NTXDESC) { 1506 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1507 ifp->if_oerrors++; 1508 1509 /* Reset the interface. */ 1510 (void) SIP_DECL(init)(ifp); 1511 } else if (ifp->if_flags & IFF_DEBUG) 1512 printf("%s: recovered from device timeout\n", 1513 sc->sc_dev.dv_xname); 1514 1515 /* Try to get more packets going. */ 1516 SIP_DECL(start)(ifp); 1517 } 1518 1519 /* 1520 * sip_ioctl: [ifnet interface function] 1521 * 1522 * Handle control requests from the operator. 1523 */ 1524 static int 1525 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1526 { 1527 struct sip_softc *sc = ifp->if_softc; 1528 struct ifreq *ifr = (struct ifreq *)data; 1529 int s, error; 1530 1531 s = splnet(); 1532 1533 switch (cmd) { 1534 case SIOCSIFMEDIA: 1535 /* Flow control requires full-duplex mode. */ 1536 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1537 (ifr->ifr_media & IFM_FDX) == 0) 1538 ifr->ifr_media &= ~IFM_ETH_FMASK; 1539 #ifdef DP83820 1540 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1541 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1542 /* We can do both TXPAUSE and RXPAUSE. */ 1543 ifr->ifr_media |= 1544 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1545 } 1546 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1547 } 1548 #else 1549 /* XXX */ 1550 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1551 ifr->ifr_media &= ~IFM_ETH_FMASK; 1552 1553 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1554 if (ifr->ifr_media & IFM_FLOW) { 1555 /* 1556 * Both TXPAUSE and RXPAUSE must be set. 1557 * (SiS900 and DP83815 don't have PAUSE_ASYM 1558 * feature.) 1559 * 1560 * XXX Can SiS900 and DP83815 send PAUSE? 1561 */ 1562 ifr->ifr_media |= 1563 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1564 } 1565 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1566 } 1567 #endif 1568 /* FALLTHROUGH */ 1569 case SIOCGIFMEDIA: 1570 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1571 break; 1572 case SIOCSIFFLAGS: 1573 /* If the interface is up and running, only modify the receive 1574 * filter when setting promiscuous or debug mode. Otherwise 1575 * fall through to ether_ioctl, which will reset the chip. 1576 */ 1577 1578 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1579 == (sc)->sc_ethercom.ec_capenable) \ 1580 && ((sc)->sc_prev.is_vlan == \ 1581 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1582 1583 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1584 1585 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1586 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1587 == (IFF_UP|IFF_RUNNING)) 1588 && ((ifp->if_flags & (~RESETIGN)) 1589 == (sc->sc_if_flags & (~RESETIGN))) 1590 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1591 /* Set up the receive filter. */ 1592 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1593 error = 0; 1594 break; 1595 #undef RESETIGN 1596 } 1597 /* FALLTHROUGH */ 1598 default: 1599 error = ether_ioctl(ifp, cmd, data); 1600 if (error == ENETRESET) { 1601 /* 1602 * Multicast list has changed; set the hardware filter 1603 * accordingly. 1604 */ 1605 if (ifp->if_flags & IFF_RUNNING) 1606 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1607 error = 0; 1608 } 1609 break; 1610 } 1611 1612 /* Try to get more packets going. */ 1613 SIP_DECL(start)(ifp); 1614 1615 sc->sc_if_flags = ifp->if_flags; 1616 splx(s); 1617 return (error); 1618 } 1619 1620 /* 1621 * sip_intr: 1622 * 1623 * Interrupt service routine. 1624 */ 1625 static int 1626 SIP_DECL(intr)(void *arg) 1627 { 1628 struct sip_softc *sc = arg; 1629 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1630 u_int32_t isr; 1631 int handled = 0; 1632 1633 /* Disable interrupts. */ 1634 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1635 1636 for (;;) { 1637 /* Reading clears interrupt. */ 1638 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1639 if ((isr & sc->sc_imr) == 0) 1640 break; 1641 1642 #if NRND > 0 1643 if (RND_ENABLED(&sc->rnd_source)) 1644 rnd_add_uint32(&sc->rnd_source, isr); 1645 #endif 1646 1647 handled = 1; 1648 1649 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1650 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1651 1652 /* Grab any new packets. */ 1653 SIP_DECL(rxintr)(sc); 1654 1655 if (isr & ISR_RXORN) { 1656 printf("%s: receive FIFO overrun\n", 1657 sc->sc_dev.dv_xname); 1658 1659 /* XXX adjust rx_drain_thresh? */ 1660 } 1661 1662 if (isr & ISR_RXIDLE) { 1663 printf("%s: receive ring overrun\n", 1664 sc->sc_dev.dv_xname); 1665 1666 /* Get the receive process going again. */ 1667 bus_space_write_4(sc->sc_st, sc->sc_sh, 1668 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1669 bus_space_write_4(sc->sc_st, sc->sc_sh, 1670 SIP_CR, CR_RXE); 1671 } 1672 } 1673 1674 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1675 #ifdef SIP_EVENT_COUNTERS 1676 if (isr & ISR_TXDESC) 1677 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1678 else if (isr & ISR_TXIDLE) 1679 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1680 #endif 1681 1682 /* Sweep up transmit descriptors. */ 1683 SIP_DECL(txintr)(sc); 1684 1685 if (isr & ISR_TXURN) { 1686 u_int32_t thresh; 1687 1688 printf("%s: transmit FIFO underrun", 1689 sc->sc_dev.dv_xname); 1690 1691 thresh = sc->sc_tx_drain_thresh + 1; 1692 if (thresh <= TXCFG_DRTH && 1693 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1694 (sc->sc_tx_fill_thresh * 32))) { 1695 printf("; increasing Tx drain " 1696 "threshold to %u bytes\n", 1697 thresh * 32); 1698 sc->sc_tx_drain_thresh = thresh; 1699 (void) SIP_DECL(init)(ifp); 1700 } else { 1701 (void) SIP_DECL(init)(ifp); 1702 printf("\n"); 1703 } 1704 } 1705 } 1706 1707 #if !defined(DP83820) 1708 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1709 if (isr & ISR_PAUSE_ST) { 1710 sc->sc_paused = 1; 1711 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1712 ifp->if_flags |= IFF_OACTIVE; 1713 } 1714 if (isr & ISR_PAUSE_END) { 1715 sc->sc_paused = 0; 1716 ifp->if_flags &= ~IFF_OACTIVE; 1717 } 1718 } 1719 #endif /* ! DP83820 */ 1720 1721 if (isr & ISR_HIBERR) { 1722 int want_init = 0; 1723 1724 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1725 1726 #define PRINTERR(bit, str) \ 1727 do { \ 1728 if ((isr & (bit)) != 0) { \ 1729 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1730 printf("%s: %s\n", \ 1731 sc->sc_dev.dv_xname, str); \ 1732 want_init = 1; \ 1733 } \ 1734 } while (/*CONSTCOND*/0) 1735 1736 PRINTERR(ISR_DPERR, "parity error"); 1737 PRINTERR(ISR_SSERR, "system error"); 1738 PRINTERR(ISR_RMABT, "master abort"); 1739 PRINTERR(ISR_RTABT, "target abort"); 1740 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1741 /* 1742 * Ignore: 1743 * Tx reset complete 1744 * Rx reset complete 1745 */ 1746 if (want_init) 1747 (void) SIP_DECL(init)(ifp); 1748 #undef PRINTERR 1749 } 1750 } 1751 1752 /* Re-enable interrupts. */ 1753 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1754 1755 /* Try to get more packets going. */ 1756 SIP_DECL(start)(ifp); 1757 1758 return (handled); 1759 } 1760 1761 /* 1762 * sip_txintr: 1763 * 1764 * Helper; handle transmit interrupts. 1765 */ 1766 static void 1767 SIP_DECL(txintr)(struct sip_softc *sc) 1768 { 1769 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1770 struct sip_txsoft *txs; 1771 u_int32_t cmdsts; 1772 1773 #ifndef DP83820 1774 if (sc->sc_paused == 0) 1775 #endif 1776 ifp->if_flags &= ~IFF_OACTIVE; 1777 1778 /* 1779 * Go through our Tx list and free mbufs for those 1780 * frames which have been transmitted. 1781 */ 1782 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1783 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1784 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1785 1786 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1787 if (cmdsts & CMDSTS_OWN) 1788 break; 1789 1790 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1791 1792 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1793 1794 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1795 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1796 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1797 m_freem(txs->txs_mbuf); 1798 txs->txs_mbuf = NULL; 1799 1800 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1801 1802 /* 1803 * Check for errors and collisions. 1804 */ 1805 if (cmdsts & 1806 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1807 ifp->if_oerrors++; 1808 if (cmdsts & CMDSTS_Tx_EC) 1809 ifp->if_collisions += 16; 1810 if (ifp->if_flags & IFF_DEBUG) { 1811 if (cmdsts & CMDSTS_Tx_ED) 1812 printf("%s: excessive deferral\n", 1813 sc->sc_dev.dv_xname); 1814 if (cmdsts & CMDSTS_Tx_EC) 1815 printf("%s: excessive collisions\n", 1816 sc->sc_dev.dv_xname); 1817 } 1818 } else { 1819 /* Packet was transmitted successfully. */ 1820 ifp->if_opackets++; 1821 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1822 } 1823 } 1824 1825 /* 1826 * If there are no more pending transmissions, cancel the watchdog 1827 * timer. 1828 */ 1829 if (txs == NULL) { 1830 ifp->if_timer = 0; 1831 sc->sc_txwin = 0; 1832 } 1833 } 1834 1835 #if defined(DP83820) 1836 /* 1837 * sip_rxintr: 1838 * 1839 * Helper; handle receive interrupts. 1840 */ 1841 static void 1842 SIP_DECL(rxintr)(struct sip_softc *sc) 1843 { 1844 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1845 struct sip_rxsoft *rxs; 1846 struct mbuf *m; 1847 u_int32_t cmdsts, extsts; 1848 int i, len; 1849 1850 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1851 rxs = &sc->sc_rxsoft[i]; 1852 1853 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1854 1855 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1856 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1857 len = CMDSTS_SIZE(cmdsts); 1858 1859 /* 1860 * NOTE: OWN is set if owned by _consumer_. We're the 1861 * consumer of the receive ring, so if the bit is clear, 1862 * we have processed all of the packets. 1863 */ 1864 if ((cmdsts & CMDSTS_OWN) == 0) { 1865 /* 1866 * We have processed all of the receive buffers. 1867 */ 1868 break; 1869 } 1870 1871 if (__predict_false(sc->sc_rxdiscard)) { 1872 SIP_INIT_RXDESC(sc, i); 1873 if ((cmdsts & CMDSTS_MORE) == 0) { 1874 /* Reset our state. */ 1875 sc->sc_rxdiscard = 0; 1876 } 1877 continue; 1878 } 1879 1880 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1881 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1882 1883 m = rxs->rxs_mbuf; 1884 1885 /* 1886 * Add a new receive buffer to the ring. 1887 */ 1888 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1889 /* 1890 * Failed, throw away what we've done so 1891 * far, and discard the rest of the packet. 1892 */ 1893 ifp->if_ierrors++; 1894 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1895 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1896 SIP_INIT_RXDESC(sc, i); 1897 if (cmdsts & CMDSTS_MORE) 1898 sc->sc_rxdiscard = 1; 1899 if (sc->sc_rxhead != NULL) 1900 m_freem(sc->sc_rxhead); 1901 SIP_RXCHAIN_RESET(sc); 1902 continue; 1903 } 1904 1905 SIP_RXCHAIN_LINK(sc, m); 1906 1907 m->m_len = len; 1908 1909 /* 1910 * If this is not the end of the packet, keep 1911 * looking. 1912 */ 1913 if (cmdsts & CMDSTS_MORE) { 1914 sc->sc_rxlen += len; 1915 continue; 1916 } 1917 1918 /* 1919 * Okay, we have the entire packet now. The chip includes 1920 * the FCS, so we need to trim it. 1921 */ 1922 m->m_len -= ETHER_CRC_LEN; 1923 1924 *sc->sc_rxtailp = NULL; 1925 len = m->m_len + sc->sc_rxlen; 1926 m = sc->sc_rxhead; 1927 1928 SIP_RXCHAIN_RESET(sc); 1929 1930 /* 1931 * If an error occurred, update stats and drop the packet. 1932 */ 1933 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1934 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1935 ifp->if_ierrors++; 1936 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1937 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1938 /* Receive overrun handled elsewhere. */ 1939 printf("%s: receive descriptor error\n", 1940 sc->sc_dev.dv_xname); 1941 } 1942 #define PRINTERR(bit, str) \ 1943 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1944 (cmdsts & (bit)) != 0) \ 1945 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1946 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1947 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1948 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1949 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1950 #undef PRINTERR 1951 m_freem(m); 1952 continue; 1953 } 1954 1955 /* 1956 * If the packet is small enough to fit in a 1957 * single header mbuf, allocate one and copy 1958 * the data into it. This greatly reduces 1959 * memory consumption when we receive lots 1960 * of small packets. 1961 */ 1962 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1963 struct mbuf *nm; 1964 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1965 if (nm == NULL) { 1966 ifp->if_ierrors++; 1967 m_freem(m); 1968 continue; 1969 } 1970 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1971 nm->m_data += 2; 1972 nm->m_pkthdr.len = nm->m_len = len; 1973 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1974 m_freem(m); 1975 m = nm; 1976 } 1977 #ifndef __NO_STRICT_ALIGNMENT 1978 else { 1979 /* 1980 * The DP83820's receive buffers must be 4-byte 1981 * aligned. But this means that the data after 1982 * the Ethernet header is misaligned. To compensate, 1983 * we have artificially shortened the buffer size 1984 * in the descriptor, and we do an overlapping copy 1985 * of the data two bytes further in (in the first 1986 * buffer of the chain only). 1987 */ 1988 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1989 m->m_len); 1990 m->m_data += 2; 1991 } 1992 #endif /* ! __NO_STRICT_ALIGNMENT */ 1993 1994 /* 1995 * If VLANs are enabled, VLAN packets have been unwrapped 1996 * for us. Associate the tag with the packet. 1997 */ 1998 if ((extsts & EXTSTS_VPKT) != 0) { 1999 VLAN_INPUT_TAG(ifp, m, ntohs(extsts & EXTSTS_VTCI), 2000 continue); 2001 } 2002 2003 /* 2004 * Set the incoming checksum information for the 2005 * packet. 2006 */ 2007 if ((extsts & EXTSTS_IPPKT) != 0) { 2008 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2009 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2010 if (extsts & EXTSTS_Rx_IPERR) 2011 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2012 if (extsts & EXTSTS_TCPPKT) { 2013 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2014 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2015 if (extsts & EXTSTS_Rx_TCPERR) 2016 m->m_pkthdr.csum_flags |= 2017 M_CSUM_TCP_UDP_BAD; 2018 } else if (extsts & EXTSTS_UDPPKT) { 2019 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2020 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2021 if (extsts & EXTSTS_Rx_UDPERR) 2022 m->m_pkthdr.csum_flags |= 2023 M_CSUM_TCP_UDP_BAD; 2024 } 2025 } 2026 2027 ifp->if_ipackets++; 2028 m->m_pkthdr.rcvif = ifp; 2029 m->m_pkthdr.len = len; 2030 2031 #if NBPFILTER > 0 2032 /* 2033 * Pass this up to any BPF listeners, but only 2034 * pass if up the stack if it's for us. 2035 */ 2036 if (ifp->if_bpf) 2037 bpf_mtap(ifp->if_bpf, m); 2038 #endif /* NBPFILTER > 0 */ 2039 2040 /* Pass it on. */ 2041 (*ifp->if_input)(ifp, m); 2042 } 2043 2044 /* Update the receive pointer. */ 2045 sc->sc_rxptr = i; 2046 } 2047 #else /* ! DP83820 */ 2048 /* 2049 * sip_rxintr: 2050 * 2051 * Helper; handle receive interrupts. 2052 */ 2053 static void 2054 SIP_DECL(rxintr)(struct sip_softc *sc) 2055 { 2056 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2057 struct sip_rxsoft *rxs; 2058 struct mbuf *m; 2059 u_int32_t cmdsts; 2060 int i, len; 2061 2062 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2063 rxs = &sc->sc_rxsoft[i]; 2064 2065 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2066 2067 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2068 2069 /* 2070 * NOTE: OWN is set if owned by _consumer_. We're the 2071 * consumer of the receive ring, so if the bit is clear, 2072 * we have processed all of the packets. 2073 */ 2074 if ((cmdsts & CMDSTS_OWN) == 0) { 2075 /* 2076 * We have processed all of the receive buffers. 2077 */ 2078 break; 2079 } 2080 2081 /* 2082 * If any collisions were seen on the wire, count one. 2083 */ 2084 if (cmdsts & CMDSTS_Rx_COL) 2085 ifp->if_collisions++; 2086 2087 /* 2088 * If an error occurred, update stats, clear the status 2089 * word, and leave the packet buffer in place. It will 2090 * simply be reused the next time the ring comes around. 2091 */ 2092 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2093 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2094 ifp->if_ierrors++; 2095 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2096 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2097 /* Receive overrun handled elsewhere. */ 2098 printf("%s: receive descriptor error\n", 2099 sc->sc_dev.dv_xname); 2100 } 2101 #define PRINTERR(bit, str) \ 2102 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2103 (cmdsts & (bit)) != 0) \ 2104 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2105 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2106 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2107 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2108 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2109 #undef PRINTERR 2110 SIP_INIT_RXDESC(sc, i); 2111 continue; 2112 } 2113 2114 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2115 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2116 2117 /* 2118 * No errors; receive the packet. Note, the SiS 900 2119 * includes the CRC with every packet. 2120 */ 2121 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2122 2123 #ifdef __NO_STRICT_ALIGNMENT 2124 /* 2125 * If the packet is small enough to fit in a 2126 * single header mbuf, allocate one and copy 2127 * the data into it. This greatly reduces 2128 * memory consumption when we receive lots 2129 * of small packets. 2130 * 2131 * Otherwise, we add a new buffer to the receive 2132 * chain. If this fails, we drop the packet and 2133 * recycle the old buffer. 2134 */ 2135 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2136 MGETHDR(m, M_DONTWAIT, MT_DATA); 2137 if (m == NULL) 2138 goto dropit; 2139 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2140 memcpy(mtod(m, caddr_t), 2141 mtod(rxs->rxs_mbuf, caddr_t), len); 2142 SIP_INIT_RXDESC(sc, i); 2143 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2144 rxs->rxs_dmamap->dm_mapsize, 2145 BUS_DMASYNC_PREREAD); 2146 } else { 2147 m = rxs->rxs_mbuf; 2148 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2149 dropit: 2150 ifp->if_ierrors++; 2151 SIP_INIT_RXDESC(sc, i); 2152 bus_dmamap_sync(sc->sc_dmat, 2153 rxs->rxs_dmamap, 0, 2154 rxs->rxs_dmamap->dm_mapsize, 2155 BUS_DMASYNC_PREREAD); 2156 continue; 2157 } 2158 } 2159 #else 2160 /* 2161 * The SiS 900's receive buffers must be 4-byte aligned. 2162 * But this means that the data after the Ethernet header 2163 * is misaligned. We must allocate a new buffer and 2164 * copy the data, shifted forward 2 bytes. 2165 */ 2166 MGETHDR(m, M_DONTWAIT, MT_DATA); 2167 if (m == NULL) { 2168 dropit: 2169 ifp->if_ierrors++; 2170 SIP_INIT_RXDESC(sc, i); 2171 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2172 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2173 continue; 2174 } 2175 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2176 if (len > (MHLEN - 2)) { 2177 MCLGET(m, M_DONTWAIT); 2178 if ((m->m_flags & M_EXT) == 0) { 2179 m_freem(m); 2180 goto dropit; 2181 } 2182 } 2183 m->m_data += 2; 2184 2185 /* 2186 * Note that we use clusters for incoming frames, so the 2187 * buffer is virtually contiguous. 2188 */ 2189 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2190 2191 /* Allow the receive descriptor to continue using its mbuf. */ 2192 SIP_INIT_RXDESC(sc, i); 2193 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2194 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2195 #endif /* __NO_STRICT_ALIGNMENT */ 2196 2197 ifp->if_ipackets++; 2198 m->m_pkthdr.rcvif = ifp; 2199 m->m_pkthdr.len = m->m_len = len; 2200 2201 #if NBPFILTER > 0 2202 /* 2203 * Pass this up to any BPF listeners, but only 2204 * pass if up the stack if it's for us. 2205 */ 2206 if (ifp->if_bpf) 2207 bpf_mtap(ifp->if_bpf, m); 2208 #endif /* NBPFILTER > 0 */ 2209 2210 /* Pass it on. */ 2211 (*ifp->if_input)(ifp, m); 2212 } 2213 2214 /* Update the receive pointer. */ 2215 sc->sc_rxptr = i; 2216 } 2217 #endif /* DP83820 */ 2218 2219 /* 2220 * sip_tick: 2221 * 2222 * One second timer, used to tick the MII. 2223 */ 2224 static void 2225 SIP_DECL(tick)(void *arg) 2226 { 2227 struct sip_softc *sc = arg; 2228 int s; 2229 2230 s = splnet(); 2231 #ifdef DP83820 2232 #ifdef SIP_EVENT_COUNTERS 2233 /* Read PAUSE related counts from MIB registers. */ 2234 sc->sc_ev_rxpause.ev_count += 2235 bus_space_read_4(sc->sc_st, sc->sc_sh, 2236 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2237 sc->sc_ev_txpause.ev_count += 2238 bus_space_read_4(sc->sc_st, sc->sc_sh, 2239 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2240 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2241 #endif /* SIP_EVENT_COUNTERS */ 2242 #endif /* DP83820 */ 2243 mii_tick(&sc->sc_mii); 2244 splx(s); 2245 2246 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2247 } 2248 2249 /* 2250 * sip_reset: 2251 * 2252 * Perform a soft reset on the SiS 900. 2253 */ 2254 static void 2255 SIP_DECL(reset)(struct sip_softc *sc) 2256 { 2257 bus_space_tag_t st = sc->sc_st; 2258 bus_space_handle_t sh = sc->sc_sh; 2259 int i; 2260 2261 bus_space_write_4(st, sh, SIP_IER, 0); 2262 bus_space_write_4(st, sh, SIP_IMR, 0); 2263 bus_space_write_4(st, sh, SIP_RFCR, 0); 2264 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2265 2266 for (i = 0; i < SIP_TIMEOUT; i++) { 2267 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2268 break; 2269 delay(2); 2270 } 2271 2272 if (i == SIP_TIMEOUT) 2273 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2274 2275 delay(1000); 2276 2277 #ifdef DP83820 2278 /* 2279 * Set the general purpose I/O bits. Do it here in case we 2280 * need to have GPIO set up to talk to the media interface. 2281 */ 2282 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2283 delay(1000); 2284 #endif /* DP83820 */ 2285 } 2286 2287 /* 2288 * sip_init: [ ifnet interface function ] 2289 * 2290 * Initialize the interface. Must be called at splnet(). 2291 */ 2292 static int 2293 SIP_DECL(init)(struct ifnet *ifp) 2294 { 2295 struct sip_softc *sc = ifp->if_softc; 2296 bus_space_tag_t st = sc->sc_st; 2297 bus_space_handle_t sh = sc->sc_sh; 2298 struct sip_txsoft *txs; 2299 struct sip_rxsoft *rxs; 2300 struct sip_desc *sipd; 2301 #if defined(DP83820) 2302 u_int32_t reg; 2303 #endif 2304 int i, error = 0; 2305 2306 /* 2307 * Cancel any pending I/O. 2308 */ 2309 SIP_DECL(stop)(ifp, 0); 2310 2311 /* 2312 * Reset the chip to a known state. 2313 */ 2314 SIP_DECL(reset)(sc); 2315 2316 #if !defined(DP83820) 2317 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2318 /* 2319 * DP83815 manual, page 78: 2320 * 4.4 Recommended Registers Configuration 2321 * For optimum performance of the DP83815, version noted 2322 * as DP83815CVNG (SRR = 203h), the listed register 2323 * modifications must be followed in sequence... 2324 * 2325 * It's not clear if this should be 302h or 203h because that 2326 * chip name is listed as SRR 302h in the description of the 2327 * SRR register. However, my revision 302h DP83815 on the 2328 * Netgear FA311 purchased in 02/2001 needs these settings 2329 * to avoid tons of errors in AcceptPerfectMatch (non- 2330 * IFF_PROMISC) mode. I do not know if other revisions need 2331 * this set or not. [briggs -- 09 March 2001] 2332 * 2333 * Note that only the low-order 12 bits of 0xe4 are documented 2334 * and that this sets reserved bits in that register. 2335 */ 2336 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2337 2338 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2339 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2340 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2341 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2342 2343 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2344 } 2345 #endif /* ! DP83820 */ 2346 2347 /* 2348 * Initialize the transmit descriptor ring. 2349 */ 2350 for (i = 0; i < SIP_NTXDESC; i++) { 2351 sipd = &sc->sc_txdescs[i]; 2352 memset(sipd, 0, sizeof(struct sip_desc)); 2353 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2354 } 2355 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2356 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2357 sc->sc_txfree = SIP_NTXDESC; 2358 sc->sc_txnext = 0; 2359 sc->sc_txwin = 0; 2360 2361 /* 2362 * Initialize the transmit job descriptors. 2363 */ 2364 SIMPLEQ_INIT(&sc->sc_txfreeq); 2365 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2366 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2367 txs = &sc->sc_txsoft[i]; 2368 txs->txs_mbuf = NULL; 2369 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2370 } 2371 2372 /* 2373 * Initialize the receive descriptor and receive job 2374 * descriptor rings. 2375 */ 2376 for (i = 0; i < SIP_NRXDESC; i++) { 2377 rxs = &sc->sc_rxsoft[i]; 2378 if (rxs->rxs_mbuf == NULL) { 2379 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2380 printf("%s: unable to allocate or map rx " 2381 "buffer %d, error = %d\n", 2382 sc->sc_dev.dv_xname, i, error); 2383 /* 2384 * XXX Should attempt to run with fewer receive 2385 * XXX buffers instead of just failing. 2386 */ 2387 SIP_DECL(rxdrain)(sc); 2388 goto out; 2389 } 2390 } else 2391 SIP_INIT_RXDESC(sc, i); 2392 } 2393 sc->sc_rxptr = 0; 2394 #ifdef DP83820 2395 sc->sc_rxdiscard = 0; 2396 SIP_RXCHAIN_RESET(sc); 2397 #endif /* DP83820 */ 2398 2399 /* 2400 * Set the configuration register; it's already initialized 2401 * in sip_attach(). 2402 */ 2403 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2404 2405 /* 2406 * Initialize the prototype TXCFG register. 2407 */ 2408 #if defined(DP83820) 2409 sc->sc_txcfg = TXCFG_MXDMA_512; 2410 sc->sc_rxcfg = RXCFG_MXDMA_512; 2411 #else 2412 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2413 SIP_SIS900_REV(sc, SIS_REV_960) || 2414 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2415 (sc->sc_cfg & CFG_EDBMASTEN)) { 2416 sc->sc_txcfg = TXCFG_MXDMA_64; 2417 sc->sc_rxcfg = RXCFG_MXDMA_64; 2418 } else { 2419 sc->sc_txcfg = TXCFG_MXDMA_512; 2420 sc->sc_rxcfg = RXCFG_MXDMA_512; 2421 } 2422 #endif /* DP83820 */ 2423 2424 sc->sc_txcfg |= TXCFG_ATP | 2425 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2426 sc->sc_tx_drain_thresh; 2427 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2428 2429 /* 2430 * Initialize the receive drain threshold if we have never 2431 * done so. 2432 */ 2433 if (sc->sc_rx_drain_thresh == 0) { 2434 /* 2435 * XXX This value should be tuned. This is set to the 2436 * maximum of 248 bytes, and we may be able to improve 2437 * performance by decreasing it (although we should never 2438 * set this value lower than 2; 14 bytes are required to 2439 * filter the packet). 2440 */ 2441 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2442 } 2443 2444 /* 2445 * Initialize the prototype RXCFG register. 2446 */ 2447 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2448 #ifdef DP83820 2449 /* 2450 * Accept long packets (including FCS) so we can handle 2451 * 802.1q-tagged frames and jumbo frames properly. 2452 */ 2453 if (ifp->if_mtu > ETHERMTU || 2454 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2455 sc->sc_rxcfg |= RXCFG_ALP; 2456 2457 /* 2458 * Checksum offloading is disabled if the user selects an MTU 2459 * larger than 8109. (FreeBSD says 8152, but there is emperical 2460 * evidence that >8109 does not work on some boards, such as the 2461 * Planex GN-1000TE). 2462 */ 2463 if (ifp->if_mtu > 8109 && 2464 (ifp->if_capenable & 2465 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2466 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2467 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2468 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2469 "disabled.\n", sc->sc_dev.dv_xname); 2470 ifp->if_capenable &= 2471 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2472 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2473 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2474 ifp->if_csum_flags_tx = 0; 2475 ifp->if_csum_flags_rx = 0; 2476 } 2477 #else 2478 /* 2479 * Accept packets >1518 bytes (including FCS) so we can handle 2480 * 802.1q-tagged frames properly. 2481 */ 2482 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2483 sc->sc_rxcfg |= RXCFG_ALP; 2484 #endif 2485 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2486 2487 #ifdef DP83820 2488 /* 2489 * Initialize the VLAN/IP receive control register. 2490 * We enable checksum computation on all incoming 2491 * packets, and do not reject packets w/ bad checksums. 2492 */ 2493 reg = 0; 2494 if (ifp->if_capenable & 2495 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2496 reg |= VRCR_IPEN; 2497 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2498 reg |= VRCR_VTDEN|VRCR_VTREN; 2499 bus_space_write_4(st, sh, SIP_VRCR, reg); 2500 2501 /* 2502 * Initialize the VLAN/IP transmit control register. 2503 * We enable outgoing checksum computation on a 2504 * per-packet basis. 2505 */ 2506 reg = 0; 2507 if (ifp->if_capenable & 2508 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2509 reg |= VTCR_PPCHK; 2510 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2511 reg |= VTCR_VPPTI; 2512 bus_space_write_4(st, sh, SIP_VTCR, reg); 2513 2514 /* 2515 * If we're using VLANs, initialize the VLAN data register. 2516 * To understand why we bswap the VLAN Ethertype, see section 2517 * 4.2.36 of the DP83820 manual. 2518 */ 2519 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2520 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2521 #endif /* DP83820 */ 2522 2523 /* 2524 * Give the transmit and receive rings to the chip. 2525 */ 2526 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2527 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2528 2529 /* 2530 * Initialize the interrupt mask. 2531 */ 2532 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2533 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2534 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2535 2536 /* Set up the receive filter. */ 2537 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2538 2539 #ifdef DP83820 2540 /* 2541 * Tune sc_rx_flow_thresh. 2542 * XXX "More than 8KB" is too short for jumbo frames. 2543 * XXX TODO: Threshold value should be user-settable. 2544 */ 2545 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2546 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2547 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2548 #endif 2549 2550 /* 2551 * Set the current media. Do this after initializing the prototype 2552 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2553 * control. 2554 */ 2555 mii_mediachg(&sc->sc_mii); 2556 2557 #ifdef DP83820 2558 /* 2559 * Set the interrupt hold-off timer to 100us. 2560 */ 2561 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2562 #endif 2563 2564 /* 2565 * Enable interrupts. 2566 */ 2567 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2568 2569 /* 2570 * Start the transmit and receive processes. 2571 */ 2572 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2573 2574 /* 2575 * Start the one second MII clock. 2576 */ 2577 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2578 2579 /* 2580 * ...all done! 2581 */ 2582 ifp->if_flags |= IFF_RUNNING; 2583 ifp->if_flags &= ~IFF_OACTIVE; 2584 sc->sc_if_flags = ifp->if_flags; 2585 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2586 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2587 sc->sc_prev.if_capenable = ifp->if_capenable; 2588 2589 out: 2590 if (error) 2591 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2592 return (error); 2593 } 2594 2595 /* 2596 * sip_drain: 2597 * 2598 * Drain the receive queue. 2599 */ 2600 static void 2601 SIP_DECL(rxdrain)(struct sip_softc *sc) 2602 { 2603 struct sip_rxsoft *rxs; 2604 int i; 2605 2606 for (i = 0; i < SIP_NRXDESC; i++) { 2607 rxs = &sc->sc_rxsoft[i]; 2608 if (rxs->rxs_mbuf != NULL) { 2609 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2610 m_freem(rxs->rxs_mbuf); 2611 rxs->rxs_mbuf = NULL; 2612 } 2613 } 2614 } 2615 2616 /* 2617 * sip_stop: [ ifnet interface function ] 2618 * 2619 * Stop transmission on the interface. 2620 */ 2621 static void 2622 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2623 { 2624 struct sip_softc *sc = ifp->if_softc; 2625 bus_space_tag_t st = sc->sc_st; 2626 bus_space_handle_t sh = sc->sc_sh; 2627 struct sip_txsoft *txs; 2628 u_int32_t cmdsts = 0; /* DEBUG */ 2629 2630 /* 2631 * Stop the one second clock. 2632 */ 2633 callout_stop(&sc->sc_tick_ch); 2634 2635 /* Down the MII. */ 2636 mii_down(&sc->sc_mii); 2637 2638 /* 2639 * Disable interrupts. 2640 */ 2641 bus_space_write_4(st, sh, SIP_IER, 0); 2642 2643 /* 2644 * Stop receiver and transmitter. 2645 */ 2646 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2647 2648 /* 2649 * Release any queued transmit buffers. 2650 */ 2651 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2652 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2653 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2654 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2655 CMDSTS_INTR) == 0) 2656 printf("%s: sip_stop: last descriptor does not " 2657 "have INTR bit set\n", sc->sc_dev.dv_xname); 2658 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2659 #ifdef DIAGNOSTIC 2660 if (txs->txs_mbuf == NULL) { 2661 printf("%s: dirty txsoft with no mbuf chain\n", 2662 sc->sc_dev.dv_xname); 2663 panic("sip_stop"); 2664 } 2665 #endif 2666 cmdsts |= /* DEBUG */ 2667 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2668 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2669 m_freem(txs->txs_mbuf); 2670 txs->txs_mbuf = NULL; 2671 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2672 } 2673 2674 if (disable) 2675 SIP_DECL(rxdrain)(sc); 2676 2677 /* 2678 * Mark the interface down and cancel the watchdog timer. 2679 */ 2680 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2681 ifp->if_timer = 0; 2682 2683 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2684 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2685 printf("%s: sip_stop: no INTR bits set in dirty tx " 2686 "descriptors\n", sc->sc_dev.dv_xname); 2687 } 2688 2689 /* 2690 * sip_read_eeprom: 2691 * 2692 * Read data from the serial EEPROM. 2693 */ 2694 static void 2695 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2696 u_int16_t *data) 2697 { 2698 bus_space_tag_t st = sc->sc_st; 2699 bus_space_handle_t sh = sc->sc_sh; 2700 u_int16_t reg; 2701 int i, x; 2702 2703 for (i = 0; i < wordcnt; i++) { 2704 /* Send CHIP SELECT. */ 2705 reg = EROMAR_EECS; 2706 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2707 2708 /* Shift in the READ opcode. */ 2709 for (x = 3; x > 0; x--) { 2710 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2711 reg |= EROMAR_EEDI; 2712 else 2713 reg &= ~EROMAR_EEDI; 2714 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2715 bus_space_write_4(st, sh, SIP_EROMAR, 2716 reg | EROMAR_EESK); 2717 delay(4); 2718 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2719 delay(4); 2720 } 2721 2722 /* Shift in address. */ 2723 for (x = 6; x > 0; x--) { 2724 if ((word + i) & (1 << (x - 1))) 2725 reg |= EROMAR_EEDI; 2726 else 2727 reg &= ~EROMAR_EEDI; 2728 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2729 bus_space_write_4(st, sh, SIP_EROMAR, 2730 reg | EROMAR_EESK); 2731 delay(4); 2732 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2733 delay(4); 2734 } 2735 2736 /* Shift out data. */ 2737 reg = EROMAR_EECS; 2738 data[i] = 0; 2739 for (x = 16; x > 0; x--) { 2740 bus_space_write_4(st, sh, SIP_EROMAR, 2741 reg | EROMAR_EESK); 2742 delay(4); 2743 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2744 data[i] |= (1 << (x - 1)); 2745 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2746 delay(4); 2747 } 2748 2749 /* Clear CHIP SELECT. */ 2750 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2751 delay(4); 2752 } 2753 } 2754 2755 /* 2756 * sip_add_rxbuf: 2757 * 2758 * Add a receive buffer to the indicated descriptor. 2759 */ 2760 static int 2761 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2762 { 2763 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2764 struct mbuf *m; 2765 int error; 2766 2767 MGETHDR(m, M_DONTWAIT, MT_DATA); 2768 if (m == NULL) 2769 return (ENOBUFS); 2770 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2771 2772 MCLGET(m, M_DONTWAIT); 2773 if ((m->m_flags & M_EXT) == 0) { 2774 m_freem(m); 2775 return (ENOBUFS); 2776 } 2777 2778 #if defined(DP83820) 2779 m->m_len = SIP_RXBUF_LEN; 2780 #endif /* DP83820 */ 2781 2782 if (rxs->rxs_mbuf != NULL) 2783 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2784 2785 rxs->rxs_mbuf = m; 2786 2787 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2788 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2789 BUS_DMA_READ|BUS_DMA_NOWAIT); 2790 if (error) { 2791 printf("%s: can't load rx DMA map %d, error = %d\n", 2792 sc->sc_dev.dv_xname, idx, error); 2793 panic("sip_add_rxbuf"); /* XXX */ 2794 } 2795 2796 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2797 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2798 2799 SIP_INIT_RXDESC(sc, idx); 2800 2801 return (0); 2802 } 2803 2804 #if !defined(DP83820) 2805 /* 2806 * sip_sis900_set_filter: 2807 * 2808 * Set up the receive filter. 2809 */ 2810 static void 2811 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2812 { 2813 bus_space_tag_t st = sc->sc_st; 2814 bus_space_handle_t sh = sc->sc_sh; 2815 struct ethercom *ec = &sc->sc_ethercom; 2816 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2817 struct ether_multi *enm; 2818 u_int8_t *cp; 2819 struct ether_multistep step; 2820 u_int32_t crc, mchash[16]; 2821 2822 /* 2823 * Initialize the prototype RFCR. 2824 */ 2825 sc->sc_rfcr = RFCR_RFEN; 2826 if (ifp->if_flags & IFF_BROADCAST) 2827 sc->sc_rfcr |= RFCR_AAB; 2828 if (ifp->if_flags & IFF_PROMISC) { 2829 sc->sc_rfcr |= RFCR_AAP; 2830 goto allmulti; 2831 } 2832 2833 /* 2834 * Set up the multicast address filter by passing all multicast 2835 * addresses through a CRC generator, and then using the high-order 2836 * 6 bits as an index into the 128 bit multicast hash table (only 2837 * the lower 16 bits of each 32 bit multicast hash register are 2838 * valid). The high order bits select the register, while the 2839 * rest of the bits select the bit within the register. 2840 */ 2841 2842 memset(mchash, 0, sizeof(mchash)); 2843 2844 /* 2845 * SiS900 (at least SiS963) requires us to register the address of 2846 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2847 */ 2848 crc = 0x0ed423f9; 2849 2850 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2851 SIP_SIS900_REV(sc, SIS_REV_960) || 2852 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2853 /* Just want the 8 most significant bits. */ 2854 crc >>= 24; 2855 } else { 2856 /* Just want the 7 most significant bits. */ 2857 crc >>= 25; 2858 } 2859 2860 /* Set the corresponding bit in the hash table. */ 2861 mchash[crc >> 4] |= 1 << (crc & 0xf); 2862 2863 ETHER_FIRST_MULTI(step, ec, enm); 2864 while (enm != NULL) { 2865 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2866 /* 2867 * We must listen to a range of multicast addresses. 2868 * For now, just accept all multicasts, rather than 2869 * trying to set only those filter bits needed to match 2870 * the range. (At this time, the only use of address 2871 * ranges is for IP multicast routing, for which the 2872 * range is big enough to require all bits set.) 2873 */ 2874 goto allmulti; 2875 } 2876 2877 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2878 2879 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2880 SIP_SIS900_REV(sc, SIS_REV_960) || 2881 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2882 /* Just want the 8 most significant bits. */ 2883 crc >>= 24; 2884 } else { 2885 /* Just want the 7 most significant bits. */ 2886 crc >>= 25; 2887 } 2888 2889 /* Set the corresponding bit in the hash table. */ 2890 mchash[crc >> 4] |= 1 << (crc & 0xf); 2891 2892 ETHER_NEXT_MULTI(step, enm); 2893 } 2894 2895 ifp->if_flags &= ~IFF_ALLMULTI; 2896 goto setit; 2897 2898 allmulti: 2899 ifp->if_flags |= IFF_ALLMULTI; 2900 sc->sc_rfcr |= RFCR_AAM; 2901 2902 setit: 2903 #define FILTER_EMIT(addr, data) \ 2904 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2905 delay(1); \ 2906 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2907 delay(1) 2908 2909 /* 2910 * Disable receive filter, and program the node address. 2911 */ 2912 cp = LLADDR(ifp->if_sadl); 2913 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2914 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2915 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2916 2917 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2918 /* 2919 * Program the multicast hash table. 2920 */ 2921 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2922 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2923 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2924 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2925 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2926 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2927 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2928 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2929 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2930 SIP_SIS900_REV(sc, SIS_REV_960) || 2931 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2932 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2933 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2934 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2935 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2936 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2937 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2938 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2939 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2940 } 2941 } 2942 #undef FILTER_EMIT 2943 2944 /* 2945 * Re-enable the receiver filter. 2946 */ 2947 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2948 } 2949 #endif /* ! DP83820 */ 2950 2951 /* 2952 * sip_dp83815_set_filter: 2953 * 2954 * Set up the receive filter. 2955 */ 2956 static void 2957 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2958 { 2959 bus_space_tag_t st = sc->sc_st; 2960 bus_space_handle_t sh = sc->sc_sh; 2961 struct ethercom *ec = &sc->sc_ethercom; 2962 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2963 struct ether_multi *enm; 2964 u_int8_t *cp; 2965 struct ether_multistep step; 2966 u_int32_t crc, hash, slot, bit; 2967 #ifdef DP83820 2968 #define MCHASH_NWORDS 128 2969 #else 2970 #define MCHASH_NWORDS 32 2971 #endif /* DP83820 */ 2972 u_int16_t mchash[MCHASH_NWORDS]; 2973 int i; 2974 2975 /* 2976 * Initialize the prototype RFCR. 2977 * Enable the receive filter, and accept on 2978 * Perfect (destination address) Match 2979 * If IFF_BROADCAST, also accept all broadcast packets. 2980 * If IFF_PROMISC, accept all unicast packets (and later, set 2981 * IFF_ALLMULTI and accept all multicast, too). 2982 */ 2983 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2984 if (ifp->if_flags & IFF_BROADCAST) 2985 sc->sc_rfcr |= RFCR_AAB; 2986 if (ifp->if_flags & IFF_PROMISC) { 2987 sc->sc_rfcr |= RFCR_AAP; 2988 goto allmulti; 2989 } 2990 2991 #ifdef DP83820 2992 /* 2993 * Set up the DP83820 multicast address filter by passing all multicast 2994 * addresses through a CRC generator, and then using the high-order 2995 * 11 bits as an index into the 2048 bit multicast hash table. The 2996 * high-order 7 bits select the slot, while the low-order 4 bits 2997 * select the bit within the slot. Note that only the low 16-bits 2998 * of each filter word are used, and there are 128 filter words. 2999 */ 3000 #else 3001 /* 3002 * Set up the DP83815 multicast address filter by passing all multicast 3003 * addresses through a CRC generator, and then using the high-order 3004 * 9 bits as an index into the 512 bit multicast hash table. The 3005 * high-order 5 bits select the slot, while the low-order 4 bits 3006 * select the bit within the slot. Note that only the low 16-bits 3007 * of each filter word are used, and there are 32 filter words. 3008 */ 3009 #endif /* DP83820 */ 3010 3011 memset(mchash, 0, sizeof(mchash)); 3012 3013 ifp->if_flags &= ~IFF_ALLMULTI; 3014 ETHER_FIRST_MULTI(step, ec, enm); 3015 if (enm == NULL) 3016 goto setit; 3017 while (enm != NULL) { 3018 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3019 /* 3020 * We must listen to a range of multicast addresses. 3021 * For now, just accept all multicasts, rather than 3022 * trying to set only those filter bits needed to match 3023 * the range. (At this time, the only use of address 3024 * ranges is for IP multicast routing, for which the 3025 * range is big enough to require all bits set.) 3026 */ 3027 goto allmulti; 3028 } 3029 3030 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3031 3032 #ifdef DP83820 3033 /* Just want the 11 most significant bits. */ 3034 hash = crc >> 21; 3035 #else 3036 /* Just want the 9 most significant bits. */ 3037 hash = crc >> 23; 3038 #endif /* DP83820 */ 3039 3040 slot = hash >> 4; 3041 bit = hash & 0xf; 3042 3043 /* Set the corresponding bit in the hash table. */ 3044 mchash[slot] |= 1 << bit; 3045 3046 ETHER_NEXT_MULTI(step, enm); 3047 } 3048 sc->sc_rfcr |= RFCR_MHEN; 3049 goto setit; 3050 3051 allmulti: 3052 ifp->if_flags |= IFF_ALLMULTI; 3053 sc->sc_rfcr |= RFCR_AAM; 3054 3055 setit: 3056 #define FILTER_EMIT(addr, data) \ 3057 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3058 delay(1); \ 3059 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3060 delay(1) 3061 3062 /* 3063 * Disable receive filter, and program the node address. 3064 */ 3065 cp = LLADDR(ifp->if_sadl); 3066 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3067 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3068 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3069 3070 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3071 /* 3072 * Program the multicast hash table. 3073 */ 3074 for (i = 0; i < MCHASH_NWORDS; i++) { 3075 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3076 mchash[i]); 3077 } 3078 } 3079 #undef FILTER_EMIT 3080 #undef MCHASH_NWORDS 3081 3082 /* 3083 * Re-enable the receiver filter. 3084 */ 3085 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3086 } 3087 3088 #if defined(DP83820) 3089 /* 3090 * sip_dp83820_mii_readreg: [mii interface function] 3091 * 3092 * Read a PHY register on the MII of the DP83820. 3093 */ 3094 static int 3095 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3096 { 3097 struct sip_softc *sc = (void *) self; 3098 3099 if (sc->sc_cfg & CFG_TBI_EN) { 3100 bus_addr_t tbireg; 3101 int rv; 3102 3103 if (phy != 0) 3104 return (0); 3105 3106 switch (reg) { 3107 case MII_BMCR: tbireg = SIP_TBICR; break; 3108 case MII_BMSR: tbireg = SIP_TBISR; break; 3109 case MII_ANAR: tbireg = SIP_TANAR; break; 3110 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3111 case MII_ANER: tbireg = SIP_TANER; break; 3112 case MII_EXTSR: 3113 /* 3114 * Don't even bother reading the TESR register. 3115 * The manual documents that the device has 3116 * 1000baseX full/half capability, but the 3117 * register itself seems read back 0 on some 3118 * boards. Just hard-code the result. 3119 */ 3120 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3121 3122 default: 3123 return (0); 3124 } 3125 3126 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3127 if (tbireg == SIP_TBISR) { 3128 /* LINK and ACOMP are switched! */ 3129 int val = rv; 3130 3131 rv = 0; 3132 if (val & TBISR_MR_LINK_STATUS) 3133 rv |= BMSR_LINK; 3134 if (val & TBISR_MR_AN_COMPLETE) 3135 rv |= BMSR_ACOMP; 3136 3137 /* 3138 * The manual claims this register reads back 0 3139 * on hard and soft reset. But we want to let 3140 * the gentbi driver know that we support auto- 3141 * negotiation, so hard-code this bit in the 3142 * result. 3143 */ 3144 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3145 } 3146 3147 return (rv); 3148 } 3149 3150 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3151 phy, reg)); 3152 } 3153 3154 /* 3155 * sip_dp83820_mii_writereg: [mii interface function] 3156 * 3157 * Write a PHY register on the MII of the DP83820. 3158 */ 3159 static void 3160 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3161 { 3162 struct sip_softc *sc = (void *) self; 3163 3164 if (sc->sc_cfg & CFG_TBI_EN) { 3165 bus_addr_t tbireg; 3166 3167 if (phy != 0) 3168 return; 3169 3170 switch (reg) { 3171 case MII_BMCR: tbireg = SIP_TBICR; break; 3172 case MII_ANAR: tbireg = SIP_TANAR; break; 3173 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3174 default: 3175 return; 3176 } 3177 3178 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3179 return; 3180 } 3181 3182 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3183 phy, reg, val); 3184 } 3185 3186 /* 3187 * sip_dp83820_mii_statchg: [mii interface function] 3188 * 3189 * Callback from MII layer when media changes. 3190 */ 3191 static void 3192 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3193 { 3194 struct sip_softc *sc = (struct sip_softc *) self; 3195 struct mii_data *mii = &sc->sc_mii; 3196 u_int32_t cfg, pcr; 3197 3198 /* 3199 * Get flow control negotiation result. 3200 */ 3201 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3202 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3203 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3204 mii->mii_media_active &= ~IFM_ETH_FMASK; 3205 } 3206 3207 /* 3208 * Update TXCFG for full-duplex operation. 3209 */ 3210 if ((mii->mii_media_active & IFM_FDX) != 0) 3211 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3212 else 3213 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3214 3215 /* 3216 * Update RXCFG for full-duplex or loopback. 3217 */ 3218 if ((mii->mii_media_active & IFM_FDX) != 0 || 3219 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3220 sc->sc_rxcfg |= RXCFG_ATX; 3221 else 3222 sc->sc_rxcfg &= ~RXCFG_ATX; 3223 3224 /* 3225 * Update CFG for MII/GMII. 3226 */ 3227 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3228 cfg = sc->sc_cfg | CFG_MODE_1000; 3229 else 3230 cfg = sc->sc_cfg; 3231 3232 /* 3233 * 802.3x flow control. 3234 */ 3235 pcr = 0; 3236 if (sc->sc_flowflags & IFM_FLOW) { 3237 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3238 pcr |= sc->sc_rx_flow_thresh; 3239 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3240 pcr |= PCR_PSEN | PCR_PS_MCAST; 3241 } 3242 3243 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3244 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3245 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3246 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3247 } 3248 #endif /* ! DP83820 */ 3249 3250 /* 3251 * sip_mii_bitbang_read: [mii bit-bang interface function] 3252 * 3253 * Read the MII serial port for the MII bit-bang module. 3254 */ 3255 static u_int32_t 3256 SIP_DECL(mii_bitbang_read)(struct device *self) 3257 { 3258 struct sip_softc *sc = (void *) self; 3259 3260 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3261 } 3262 3263 /* 3264 * sip_mii_bitbang_write: [mii big-bang interface function] 3265 * 3266 * Write the MII serial port for the MII bit-bang module. 3267 */ 3268 static void 3269 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3270 { 3271 struct sip_softc *sc = (void *) self; 3272 3273 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3274 } 3275 3276 #ifndef DP83820 3277 /* 3278 * sip_sis900_mii_readreg: [mii interface function] 3279 * 3280 * Read a PHY register on the MII. 3281 */ 3282 static int 3283 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3284 { 3285 struct sip_softc *sc = (struct sip_softc *) self; 3286 u_int32_t enphy; 3287 3288 /* 3289 * The PHY of recent SiS chipsets is accessed through bitbang 3290 * operations. 3291 */ 3292 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3293 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3294 phy, reg)); 3295 3296 #ifndef SIS900_MII_RESTRICT 3297 /* 3298 * The SiS 900 has only an internal PHY on the MII. Only allow 3299 * MII address 0. 3300 */ 3301 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3302 return (0); 3303 #endif 3304 3305 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3306 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3307 ENPHY_RWCMD | ENPHY_ACCESS); 3308 do { 3309 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3310 } while (enphy & ENPHY_ACCESS); 3311 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3312 } 3313 3314 /* 3315 * sip_sis900_mii_writereg: [mii interface function] 3316 * 3317 * Write a PHY register on the MII. 3318 */ 3319 static void 3320 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3321 { 3322 struct sip_softc *sc = (struct sip_softc *) self; 3323 u_int32_t enphy; 3324 3325 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3326 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3327 phy, reg, val); 3328 return; 3329 } 3330 3331 #ifndef SIS900_MII_RESTRICT 3332 /* 3333 * The SiS 900 has only an internal PHY on the MII. Only allow 3334 * MII address 0. 3335 */ 3336 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3337 return; 3338 #endif 3339 3340 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3341 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3342 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3343 do { 3344 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3345 } while (enphy & ENPHY_ACCESS); 3346 } 3347 3348 /* 3349 * sip_sis900_mii_statchg: [mii interface function] 3350 * 3351 * Callback from MII layer when media changes. 3352 */ 3353 static void 3354 SIP_DECL(sis900_mii_statchg)(struct device *self) 3355 { 3356 struct sip_softc *sc = (struct sip_softc *) self; 3357 struct mii_data *mii = &sc->sc_mii; 3358 u_int32_t flowctl; 3359 3360 /* 3361 * Get flow control negotiation result. 3362 */ 3363 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3364 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3365 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3366 mii->mii_media_active &= ~IFM_ETH_FMASK; 3367 } 3368 3369 /* 3370 * Update TXCFG for full-duplex operation. 3371 */ 3372 if ((mii->mii_media_active & IFM_FDX) != 0) 3373 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3374 else 3375 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3376 3377 /* 3378 * Update RXCFG for full-duplex or loopback. 3379 */ 3380 if ((mii->mii_media_active & IFM_FDX) != 0 || 3381 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3382 sc->sc_rxcfg |= RXCFG_ATX; 3383 else 3384 sc->sc_rxcfg &= ~RXCFG_ATX; 3385 3386 /* 3387 * Update IMR for use of 802.3x flow control. 3388 */ 3389 if (sc->sc_flowflags & IFM_FLOW) { 3390 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3391 flowctl = FLOWCTL_FLOWEN; 3392 } else { 3393 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3394 flowctl = 0; 3395 } 3396 3397 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3398 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3399 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3400 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3401 } 3402 3403 /* 3404 * sip_dp83815_mii_readreg: [mii interface function] 3405 * 3406 * Read a PHY register on the MII. 3407 */ 3408 static int 3409 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3410 { 3411 struct sip_softc *sc = (struct sip_softc *) self; 3412 u_int32_t val; 3413 3414 /* 3415 * The DP83815 only has an internal PHY. Only allow 3416 * MII address 0. 3417 */ 3418 if (phy != 0) 3419 return (0); 3420 3421 /* 3422 * Apparently, after a reset, the DP83815 can take a while 3423 * to respond. During this recovery period, the BMSR returns 3424 * a value of 0. Catch this -- it's not supposed to happen 3425 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3426 * PHY to come back to life. 3427 * 3428 * This works out because the BMSR is the first register 3429 * read during the PHY probe process. 3430 */ 3431 do { 3432 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3433 } while (reg == MII_BMSR && val == 0); 3434 3435 return (val & 0xffff); 3436 } 3437 3438 /* 3439 * sip_dp83815_mii_writereg: [mii interface function] 3440 * 3441 * Write a PHY register to the MII. 3442 */ 3443 static void 3444 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3445 { 3446 struct sip_softc *sc = (struct sip_softc *) self; 3447 3448 /* 3449 * The DP83815 only has an internal PHY. Only allow 3450 * MII address 0. 3451 */ 3452 if (phy != 0) 3453 return; 3454 3455 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3456 } 3457 3458 /* 3459 * sip_dp83815_mii_statchg: [mii interface function] 3460 * 3461 * Callback from MII layer when media changes. 3462 */ 3463 static void 3464 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3465 { 3466 struct sip_softc *sc = (struct sip_softc *) self; 3467 3468 /* 3469 * Update TXCFG for full-duplex operation. 3470 */ 3471 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3472 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3473 else 3474 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3475 3476 /* 3477 * Update RXCFG for full-duplex or loopback. 3478 */ 3479 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3480 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3481 sc->sc_rxcfg |= RXCFG_ATX; 3482 else 3483 sc->sc_rxcfg &= ~RXCFG_ATX; 3484 3485 /* 3486 * XXX 802.3x flow control. 3487 */ 3488 3489 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3491 3492 /* 3493 * Some DP83815s experience problems when used with short 3494 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3495 * sequence adjusts the DSP's signal attenuation to fix the 3496 * problem. 3497 */ 3498 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3499 uint32_t reg; 3500 3501 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3502 3503 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3504 reg &= 0x0fff; 3505 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3506 delay(100); 3507 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3508 reg &= 0x00ff; 3509 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3510 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3511 0x00e8); 3512 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3513 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3514 reg | 0x20); 3515 } 3516 3517 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3518 } 3519 } 3520 #endif /* DP83820 */ 3521 3522 #if defined(DP83820) 3523 static void 3524 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3525 const struct pci_attach_args *pa, u_int8_t *enaddr) 3526 { 3527 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3528 u_int8_t cksum, *e, match; 3529 int i; 3530 3531 /* 3532 * EEPROM data format for the DP83820 can be found in 3533 * the DP83820 manual, section 4.2.4. 3534 */ 3535 3536 SIP_DECL(read_eeprom)(sc, 0, 3537 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3538 3539 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3540 match = ~(match - 1); 3541 3542 cksum = 0x55; 3543 e = (u_int8_t *) eeprom_data; 3544 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3545 cksum += *e++; 3546 3547 if (cksum != match) 3548 printf("%s: Checksum (%x) mismatch (%x)", 3549 sc->sc_dev.dv_xname, cksum, match); 3550 3551 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3552 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3553 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3554 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3555 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3556 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3557 } 3558 #else /* ! DP83820 */ 3559 static void 3560 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3561 { 3562 int i; 3563 3564 /* 3565 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3566 * a reason, but I don't know it. 3567 */ 3568 for (i = 0; i < 10; i++) 3569 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3570 } 3571 3572 static void 3573 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3574 const struct pci_attach_args *pa, u_int8_t *enaddr) 3575 { 3576 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3577 3578 switch (sc->sc_rev) { 3579 case SIS_REV_630S: 3580 case SIS_REV_630E: 3581 case SIS_REV_630EA1: 3582 case SIS_REV_630ET: 3583 case SIS_REV_635: 3584 /* 3585 * The MAC address for the on-board Ethernet of 3586 * the SiS 630 chipset is in the NVRAM. Kick 3587 * the chip into re-loading it from NVRAM, and 3588 * read the MAC address out of the filter registers. 3589 */ 3590 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3591 3592 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3593 RFCR_RFADDR_NODE0); 3594 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3595 0xffff; 3596 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3598 RFCR_RFADDR_NODE2); 3599 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3600 0xffff; 3601 3602 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3603 RFCR_RFADDR_NODE4); 3604 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3605 0xffff; 3606 break; 3607 3608 case SIS_REV_960: 3609 { 3610 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3611 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3612 3613 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3614 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3615 3616 int waittime, i; 3617 3618 /* Allow to read EEPROM from LAN. It is shared 3619 * between a 1394 controller and the NIC and each 3620 * time we access it, we need to set SIS_EECMD_REQ. 3621 */ 3622 SIS_SET_EROMAR(sc, EROMAR_REQ); 3623 3624 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3625 /* Force EEPROM to idle state. */ 3626 3627 /* 3628 * XXX-cube This is ugly. I'll look for docs about it. 3629 */ 3630 SIS_SET_EROMAR(sc, EROMAR_EECS); 3631 SIP_DECL(sis900_eeprom_delay)(sc); 3632 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3633 SIS_SET_EROMAR(sc, EROMAR_EESK); 3634 SIP_DECL(sis900_eeprom_delay)(sc); 3635 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3636 SIP_DECL(sis900_eeprom_delay)(sc); 3637 } 3638 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3639 SIP_DECL(sis900_eeprom_delay)(sc); 3640 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3641 3642 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3643 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3644 sizeof(myea) / sizeof(myea[0]), myea); 3645 break; 3646 } 3647 DELAY(1); 3648 } 3649 3650 /* 3651 * Set SIS_EECTL_CLK to high, so a other master 3652 * can operate on the i2c bus. 3653 */ 3654 SIS_SET_EROMAR(sc, EROMAR_EESK); 3655 3656 /* Refuse EEPROM access by LAN */ 3657 SIS_SET_EROMAR(sc, EROMAR_DONE); 3658 } break; 3659 3660 default: 3661 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3662 sizeof(myea) / sizeof(myea[0]), myea); 3663 } 3664 3665 enaddr[0] = myea[0] & 0xff; 3666 enaddr[1] = myea[0] >> 8; 3667 enaddr[2] = myea[1] & 0xff; 3668 enaddr[3] = myea[1] >> 8; 3669 enaddr[4] = myea[2] & 0xff; 3670 enaddr[5] = myea[2] >> 8; 3671 } 3672 3673 /* Table and macro to bit-reverse an octet. */ 3674 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3675 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3676 3677 static void 3678 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3679 const struct pci_attach_args *pa, u_int8_t *enaddr) 3680 { 3681 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3682 u_int8_t cksum, *e, match; 3683 int i; 3684 3685 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3686 sizeof(eeprom_data[0]), eeprom_data); 3687 3688 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3689 match = ~(match - 1); 3690 3691 cksum = 0x55; 3692 e = (u_int8_t *) eeprom_data; 3693 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3694 cksum += *e++; 3695 } 3696 if (cksum != match) { 3697 printf("%s: Checksum (%x) mismatch (%x)", 3698 sc->sc_dev.dv_xname, cksum, match); 3699 } 3700 3701 /* 3702 * Unrolled because it makes slightly more sense this way. 3703 * The DP83815 stores the MAC address in bit 0 of word 6 3704 * through bit 15 of word 8. 3705 */ 3706 ea = &eeprom_data[6]; 3707 enaddr[0] = ((*ea & 0x1) << 7); 3708 ea++; 3709 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3710 enaddr[1] = ((*ea & 0x1FE) >> 1); 3711 enaddr[2] = ((*ea & 0x1) << 7); 3712 ea++; 3713 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3714 enaddr[3] = ((*ea & 0x1FE) >> 1); 3715 enaddr[4] = ((*ea & 0x1) << 7); 3716 ea++; 3717 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3718 enaddr[5] = ((*ea & 0x1FE) >> 1); 3719 3720 /* 3721 * In case that's not weird enough, we also need to reverse 3722 * the bits in each byte. This all actually makes more sense 3723 * if you think about the EEPROM storage as an array of bits 3724 * being shifted into bytes, but that's not how we're looking 3725 * at it here... 3726 */ 3727 for (i = 0; i < 6 ;i++) 3728 enaddr[i] = bbr(enaddr[i]); 3729 } 3730 #endif /* DP83820 */ 3731 3732 /* 3733 * sip_mediastatus: [ifmedia interface function] 3734 * 3735 * Get the current interface media status. 3736 */ 3737 static void 3738 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3739 { 3740 struct sip_softc *sc = ifp->if_softc; 3741 3742 mii_pollstat(&sc->sc_mii); 3743 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3744 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3745 sc->sc_flowflags; 3746 } 3747 3748 /* 3749 * sip_mediachange: [ifmedia interface function] 3750 * 3751 * Set hardware to newly-selected media. 3752 */ 3753 static int 3754 SIP_DECL(mediachange)(struct ifnet *ifp) 3755 { 3756 struct sip_softc *sc = ifp->if_softc; 3757 3758 if (ifp->if_flags & IFF_UP) 3759 mii_mediachg(&sc->sc_mii); 3760 return (0); 3761 } 3762
Indexes created Tue Sep 30 11:09:46 GMT 2025