if_sip.c revision 1.104.6.1
1 /* $NetBSD: if_sip.c,v 1.104.6.1 2006/03/28 09:42:13 tron Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.104.6.1 2006/03/28 09:42:13 tron Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 short sc_if_flags; 313 314 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 315 #if defined(DP83820) 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 #endif /* DP83820 */ 322 323 #if NRND > 0 324 rndsource_element_t rnd_source; /* random source */ 325 #endif 326 }; 327 328 #ifdef DP83820 329 #define SIP_RXCHAIN_RESET(sc) \ 330 do { \ 331 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 332 *(sc)->sc_rxtailp = NULL; \ 333 (sc)->sc_rxlen = 0; \ 334 } while (/*CONSTCOND*/0) 335 336 #define SIP_RXCHAIN_LINK(sc, m) \ 337 do { \ 338 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 339 (sc)->sc_rxtailp = &(m)->m_next; \ 340 } while (/*CONSTCOND*/0) 341 #endif /* DP83820 */ 342 343 #ifdef SIP_EVENT_COUNTERS 344 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 345 #else 346 #define SIP_EVCNT_INCR(ev) /* nothing */ 347 #endif 348 349 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 350 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 351 352 #define SIP_CDTXSYNC(sc, x, n, ops) \ 353 do { \ 354 int __x, __n; \ 355 \ 356 __x = (x); \ 357 __n = (n); \ 358 \ 359 /* If it will wrap around, sync to the end of the ring. */ \ 360 if ((__x + __n) > SIP_NTXDESC) { \ 361 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 362 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 363 (SIP_NTXDESC - __x), (ops)); \ 364 __n -= (SIP_NTXDESC - __x); \ 365 __x = 0; \ 366 } \ 367 \ 368 /* Now sync whatever is left. */ \ 369 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 370 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 371 } while (0) 372 373 #define SIP_CDRXSYNC(sc, x, ops) \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 376 377 #ifdef DP83820 378 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 379 #define SIP_RXBUF_LEN (MCLBYTES - 8) 380 #else 381 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 382 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 383 #endif 384 #define SIP_INIT_RXDESC(sc, x) \ 385 do { \ 386 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 387 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 388 \ 389 __sipd->sipd_link = \ 390 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 391 __sipd->sipd_bufptr = \ 392 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 393 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 394 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 395 SIP_INIT_RXDESC_EXTSTS \ 396 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 397 } while (0) 398 399 #define SIP_CHIP_VERS(sc, v, p, r) \ 400 ((sc)->sc_model->sip_vendor == (v) && \ 401 (sc)->sc_model->sip_product == (p) && \ 402 (sc)->sc_rev == (r)) 403 404 #define SIP_CHIP_MODEL(sc, v, p) \ 405 ((sc)->sc_model->sip_vendor == (v) && \ 406 (sc)->sc_model->sip_product == (p)) 407 408 #if !defined(DP83820) 409 #define SIP_SIS900_REV(sc, rev) \ 410 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 411 #endif 412 413 #define SIP_TIMEOUT 1000 414 415 static void SIP_DECL(start)(struct ifnet *); 416 static void SIP_DECL(watchdog)(struct ifnet *); 417 static int SIP_DECL(ioctl)(struct ifnet *, u_long, caddr_t); 418 static int SIP_DECL(init)(struct ifnet *); 419 static void SIP_DECL(stop)(struct ifnet *, int); 420 421 static void SIP_DECL(shutdown)(void *); 422 423 static void SIP_DECL(reset)(struct sip_softc *); 424 static void SIP_DECL(rxdrain)(struct sip_softc *); 425 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 426 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 427 u_int16_t *); 428 static void SIP_DECL(tick)(void *); 429 430 #if !defined(DP83820) 431 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 432 #endif /* ! DP83820 */ 433 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 434 435 #if defined(DP83820) 436 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 437 const struct pci_attach_args *, u_int8_t *); 438 #else 439 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 440 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 441 const struct pci_attach_args *, u_int8_t *); 442 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 #endif /* DP83820 */ 445 446 static int SIP_DECL(intr)(void *); 447 static void SIP_DECL(txintr)(struct sip_softc *); 448 static void SIP_DECL(rxintr)(struct sip_softc *); 449 450 #if defined(DP83820) 451 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 452 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 453 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 454 #else 455 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 456 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 457 static void SIP_DECL(sis900_mii_statchg)(struct device *); 458 459 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 460 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 461 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 462 #endif /* DP83820 */ 463 464 static int SIP_DECL(mediachange)(struct ifnet *); 465 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 466 467 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 468 static void SIP_DECL(attach)(struct device *, struct device *, void *); 469 470 int SIP_DECL(copy_small) = 0; 471 472 #ifdef DP83820 473 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 474 gsip_match, gsip_attach, NULL, NULL); 475 #else 476 CFATTACH_DECL(sip, sizeof(struct sip_softc), 477 sip_match, sip_attach, NULL, NULL); 478 #endif 479 480 /* 481 * Descriptions of the variants of the SiS900. 482 */ 483 struct sip_variant { 484 int (*sipv_mii_readreg)(struct device *, int, int); 485 void (*sipv_mii_writereg)(struct device *, int, int, int); 486 void (*sipv_mii_statchg)(struct device *); 487 void (*sipv_set_filter)(struct sip_softc *); 488 void (*sipv_read_macaddr)(struct sip_softc *, 489 const struct pci_attach_args *, u_int8_t *); 490 }; 491 492 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 493 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 494 495 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 496 SIP_DECL(mii_bitbang_read), 497 SIP_DECL(mii_bitbang_write), 498 { 499 EROMAR_MDIO, /* MII_BIT_MDO */ 500 EROMAR_MDIO, /* MII_BIT_MDI */ 501 EROMAR_MDC, /* MII_BIT_MDC */ 502 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 503 0, /* MII_BIT_DIR_PHY_HOST */ 504 } 505 }; 506 507 #if defined(DP83820) 508 static const struct sip_variant SIP_DECL(variant_dp83820) = { 509 SIP_DECL(dp83820_mii_readreg), 510 SIP_DECL(dp83820_mii_writereg), 511 SIP_DECL(dp83820_mii_statchg), 512 SIP_DECL(dp83815_set_filter), 513 SIP_DECL(dp83820_read_macaddr), 514 }; 515 #else 516 static const struct sip_variant SIP_DECL(variant_sis900) = { 517 SIP_DECL(sis900_mii_readreg), 518 SIP_DECL(sis900_mii_writereg), 519 SIP_DECL(sis900_mii_statchg), 520 SIP_DECL(sis900_set_filter), 521 SIP_DECL(sis900_read_macaddr), 522 }; 523 524 static const struct sip_variant SIP_DECL(variant_dp83815) = { 525 SIP_DECL(dp83815_mii_readreg), 526 SIP_DECL(dp83815_mii_writereg), 527 SIP_DECL(dp83815_mii_statchg), 528 SIP_DECL(dp83815_set_filter), 529 SIP_DECL(dp83815_read_macaddr), 530 }; 531 #endif /* DP83820 */ 532 533 /* 534 * Devices supported by this driver. 535 */ 536 static const struct sip_product { 537 pci_vendor_id_t sip_vendor; 538 pci_product_id_t sip_product; 539 const char *sip_name; 540 const struct sip_variant *sip_variant; 541 } SIP_DECL(products)[] = { 542 #if defined(DP83820) 543 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 544 "NatSemi DP83820 Gigabit Ethernet", 545 &SIP_DECL(variant_dp83820) }, 546 #else 547 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 548 "SiS 900 10/100 Ethernet", 549 &SIP_DECL(variant_sis900) }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 551 "SiS 7016 10/100 Ethernet", 552 &SIP_DECL(variant_sis900) }, 553 554 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 555 "NatSemi DP83815 10/100 Ethernet", 556 &SIP_DECL(variant_dp83815) }, 557 #endif /* DP83820 */ 558 559 { 0, 0, 560 NULL, 561 NULL }, 562 }; 563 564 static const struct sip_product * 565 SIP_DECL(lookup)(const struct pci_attach_args *pa) 566 { 567 const struct sip_product *sip; 568 569 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 570 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 571 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 572 return (sip); 573 } 574 return (NULL); 575 } 576 577 #ifdef DP83820 578 /* 579 * I really hate stupid hardware vendors. There's a bit in the EEPROM 580 * which indicates if the card can do 64-bit data transfers. Unfortunately, 581 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 582 * which means we try to use 64-bit data transfers on those cards if we 583 * happen to be plugged into a 32-bit slot. 584 * 585 * What we do is use this table of cards known to be 64-bit cards. If 586 * you have a 64-bit card who's subsystem ID is not listed in this table, 587 * send the output of "pcictl dump ..." of the device to me so that your 588 * card will use the 64-bit data path when plugged into a 64-bit slot. 589 * 590 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 591 * June 30, 2002 592 */ 593 static int 594 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 595 { 596 static const struct { 597 pci_vendor_id_t c64_vendor; 598 pci_product_id_t c64_product; 599 } card64[] = { 600 /* Asante GigaNIX */ 601 { 0x128a, 0x0002 }, 602 603 /* Accton EN1407-T, Planex GN-1000TE */ 604 { 0x1113, 0x1407 }, 605 606 /* Netgear GA-621 */ 607 { 0x1385, 0x621a }, 608 609 /* SMC EZ Card */ 610 { 0x10b8, 0x9462 }, 611 612 { 0, 0} 613 }; 614 pcireg_t subsys; 615 int i; 616 617 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 618 619 for (i = 0; card64[i].c64_vendor != 0; i++) { 620 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 621 PCI_PRODUCT(subsys) == card64[i].c64_product) 622 return (1); 623 } 624 625 return (0); 626 } 627 #endif /* DP83820 */ 628 629 static int 630 SIP_DECL(match)(struct device *parent, struct cfdata *cf, void *aux) 631 { 632 struct pci_attach_args *pa = aux; 633 634 if (SIP_DECL(lookup)(pa) != NULL) 635 return (1); 636 637 return (0); 638 } 639 640 static void 641 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 642 { 643 struct sip_softc *sc = (struct sip_softc *) self; 644 struct pci_attach_args *pa = aux; 645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 646 pci_chipset_tag_t pc = pa->pa_pc; 647 pci_intr_handle_t ih; 648 const char *intrstr = NULL; 649 bus_space_tag_t iot, memt; 650 bus_space_handle_t ioh, memh; 651 bus_dma_segment_t seg; 652 int ioh_valid, memh_valid; 653 int i, rseg, error; 654 const struct sip_product *sip; 655 pcireg_t pmode; 656 u_int8_t enaddr[ETHER_ADDR_LEN]; 657 int pmreg; 658 #ifdef DP83820 659 pcireg_t memtype; 660 u_int32_t reg; 661 #endif /* DP83820 */ 662 663 callout_init(&sc->sc_tick_ch); 664 665 sip = SIP_DECL(lookup)(pa); 666 if (sip == NULL) { 667 printf("\n"); 668 panic(SIP_STR(attach) ": impossible"); 669 } 670 sc->sc_rev = PCI_REVISION(pa->pa_class); 671 672 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 673 674 sc->sc_model = sip; 675 676 /* 677 * XXX Work-around broken PXE firmware on some boards. 678 * 679 * The DP83815 shares an address decoder with the MEM BAR 680 * and the ROM BAR. Make sure the ROM BAR is disabled, 681 * so that memory mapped access works. 682 */ 683 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 684 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 685 ~PCI_MAPREG_ROM_ENABLE); 686 687 /* 688 * Map the device. 689 */ 690 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 691 PCI_MAPREG_TYPE_IO, 0, 692 &iot, &ioh, NULL, NULL) == 0); 693 #ifdef DP83820 694 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 695 switch (memtype) { 696 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 697 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 698 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 699 memtype, 0, &memt, &memh, NULL, NULL) == 0); 700 break; 701 default: 702 memh_valid = 0; 703 } 704 #else 705 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 706 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 707 &memt, &memh, NULL, NULL) == 0); 708 #endif /* DP83820 */ 709 710 if (memh_valid) { 711 sc->sc_st = memt; 712 sc->sc_sh = memh; 713 } else if (ioh_valid) { 714 sc->sc_st = iot; 715 sc->sc_sh = ioh; 716 } else { 717 printf("%s: unable to map device registers\n", 718 sc->sc_dev.dv_xname); 719 return; 720 } 721 722 sc->sc_dmat = pa->pa_dmat; 723 724 /* 725 * Make sure bus mastering is enabled. Also make sure 726 * Write/Invalidate is enabled if we're allowed to use it. 727 */ 728 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 729 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 730 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 731 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 732 pmreg | PCI_COMMAND_MASTER_ENABLE); 733 734 /* Get it out of power save mode if needed. */ 735 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 736 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + PCI_PMCSR) & 737 PCI_PMCSR_STATE_MASK; 738 if (pmode == PCI_PMCSR_STATE_D3) { 739 /* 740 * The card has lost all configuration data in 741 * this state, so punt. 742 */ 743 printf("%s: unable to wake up from power state D3\n", 744 sc->sc_dev.dv_xname); 745 return; 746 } 747 if (pmode != PCI_PMCSR_STATE_D0) { 748 printf("%s: waking up from power state D%d\n", 749 sc->sc_dev.dv_xname, pmode); 750 pci_conf_write(pc, pa->pa_tag, pmreg + PCI_PMCSR, 751 PCI_PMCSR_STATE_D0); 752 } 753 } 754 755 /* 756 * Map and establish our interrupt. 757 */ 758 if (pci_intr_map(pa, &ih)) { 759 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 764 if (sc->sc_ih == NULL) { 765 printf("%s: unable to establish interrupt", 766 sc->sc_dev.dv_xname); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 printf("\n"); 770 return; 771 } 772 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 773 774 SIMPLEQ_INIT(&sc->sc_txfreeq); 775 SIMPLEQ_INIT(&sc->sc_txdirtyq); 776 777 /* 778 * Allocate the control data structures, and create and load the 779 * DMA map for it. 780 */ 781 if ((error = bus_dmamem_alloc(sc->sc_dmat, 782 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 783 0)) != 0) { 784 printf("%s: unable to allocate control data, error = %d\n", 785 sc->sc_dev.dv_xname, error); 786 goto fail_0; 787 } 788 789 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 790 sizeof(struct sip_control_data), (caddr_t *)&sc->sc_control_data, 791 BUS_DMA_COHERENT)) != 0) { 792 printf("%s: unable to map control data, error = %d\n", 793 sc->sc_dev.dv_xname, error); 794 goto fail_1; 795 } 796 797 if ((error = bus_dmamap_create(sc->sc_dmat, 798 sizeof(struct sip_control_data), 1, 799 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 800 printf("%s: unable to create control data DMA map, " 801 "error = %d\n", sc->sc_dev.dv_xname, error); 802 goto fail_2; 803 } 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 806 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 807 0)) != 0) { 808 printf("%s: unable to load control data DMA map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 goto fail_3; 811 } 812 813 /* 814 * Create the transmit buffer DMA maps. 815 */ 816 for (i = 0; i < SIP_TXQUEUELEN; i++) { 817 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 818 SIP_NTXSEGS, MCLBYTES, 0, 0, 819 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 820 printf("%s: unable to create tx DMA map %d, " 821 "error = %d\n", sc->sc_dev.dv_xname, i, error); 822 goto fail_4; 823 } 824 } 825 826 /* 827 * Create the receive buffer DMA maps. 828 */ 829 for (i = 0; i < SIP_NRXDESC; i++) { 830 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 831 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 832 printf("%s: unable to create rx DMA map %d, " 833 "error = %d\n", sc->sc_dev.dv_xname, i, error); 834 goto fail_5; 835 } 836 sc->sc_rxsoft[i].rxs_mbuf = NULL; 837 } 838 839 /* 840 * Reset the chip to a known state. 841 */ 842 SIP_DECL(reset)(sc); 843 844 /* 845 * Read the Ethernet address from the EEPROM. This might 846 * also fetch other stuff from the EEPROM and stash it 847 * in the softc. 848 */ 849 sc->sc_cfg = 0; 850 #if !defined(DP83820) 851 if (SIP_SIS900_REV(sc,SIS_REV_635) || 852 SIP_SIS900_REV(sc,SIS_REV_900B)) 853 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 854 855 if (SIP_SIS900_REV(sc,SIS_REV_635) || 856 SIP_SIS900_REV(sc,SIS_REV_960) || 857 SIP_SIS900_REV(sc,SIS_REV_900B)) 858 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 859 SIP_CFG) & CFG_EDBMASTEN); 860 #endif 861 862 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 863 864 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 865 ether_sprintf(enaddr)); 866 867 /* 868 * Initialize the configuration register: aggressive PCI 869 * bus request algorithm, default backoff, default OW timer, 870 * default parity error detection. 871 * 872 * NOTE: "Big endian mode" is useless on the SiS900 and 873 * friends -- it affects packet data, not descriptors. 874 */ 875 #ifdef DP83820 876 /* 877 * Cause the chip to load configuration data from the EEPROM. 878 */ 879 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 880 for (i = 0; i < 10000; i++) { 881 delay(10); 882 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 883 PTSCR_EELOAD_EN) == 0) 884 break; 885 } 886 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 887 PTSCR_EELOAD_EN) { 888 printf("%s: timeout loading configuration from EEPROM\n", 889 sc->sc_dev.dv_xname); 890 return; 891 } 892 893 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 894 895 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 896 if (reg & CFG_PCI64_DET) { 897 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 898 /* 899 * Check to see if this card is 64-bit. If so, enable 64-bit 900 * data transfers. 901 * 902 * We can't use the DATA64_EN bit in the EEPROM, because 903 * vendors of 32-bit cards fail to clear that bit in many 904 * cases (yet the card still detects that it's in a 64-bit 905 * slot; go figure). 906 */ 907 if (SIP_DECL(check_64bit)(pa)) { 908 sc->sc_cfg |= CFG_DATA64_EN; 909 printf(", using 64-bit data transfers"); 910 } 911 printf("\n"); 912 } 913 914 /* 915 * XXX Need some PCI flags indicating support for 916 * XXX 64-bit addressing. 917 */ 918 #if 0 919 if (reg & CFG_M64ADDR) 920 sc->sc_cfg |= CFG_M64ADDR; 921 if (reg & CFG_T64ADDR) 922 sc->sc_cfg |= CFG_T64ADDR; 923 #endif 924 925 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 926 const char *sep = ""; 927 printf("%s: using ", sc->sc_dev.dv_xname); 928 if (reg & CFG_EXT_125) { 929 sc->sc_cfg |= CFG_EXT_125; 930 printf("%s125MHz clock", sep); 931 sep = ", "; 932 } 933 if (reg & CFG_TBI_EN) { 934 sc->sc_cfg |= CFG_TBI_EN; 935 printf("%sten-bit interface", sep); 936 sep = ", "; 937 } 938 printf("\n"); 939 } 940 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 941 (reg & CFG_MRM_DIS) != 0) 942 sc->sc_cfg |= CFG_MRM_DIS; 943 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 944 (reg & CFG_MWI_DIS) != 0) 945 sc->sc_cfg |= CFG_MWI_DIS; 946 947 /* 948 * Use the extended descriptor format on the DP83820. This 949 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 950 * checksumming. 951 */ 952 sc->sc_cfg |= CFG_EXTSTS_EN; 953 #endif /* DP83820 */ 954 955 /* 956 * Initialize our media structures and probe the MII. 957 */ 958 sc->sc_mii.mii_ifp = ifp; 959 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 960 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 961 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 962 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 963 SIP_DECL(mediastatus)); 964 965 /* 966 * XXX We cannot handle flow control on the DP83815. 967 */ 968 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, 0); 971 else 972 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 973 MII_OFFSET_ANY, MIIF_DOPAUSE); 974 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 975 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 976 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 977 } else 978 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 979 980 ifp = &sc->sc_ethercom.ec_if; 981 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 982 ifp->if_softc = sc; 983 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 984 sc->sc_if_flags = ifp->if_flags; 985 ifp->if_ioctl = SIP_DECL(ioctl); 986 ifp->if_start = SIP_DECL(start); 987 ifp->if_watchdog = SIP_DECL(watchdog); 988 ifp->if_init = SIP_DECL(init); 989 ifp->if_stop = SIP_DECL(stop); 990 IFQ_SET_READY(&ifp->if_snd); 991 992 /* 993 * We can support 802.1Q VLAN-sized frames. 994 */ 995 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 996 997 #ifdef DP83820 998 /* 999 * And the DP83820 can do VLAN tagging in hardware, and 1000 * support the jumbo Ethernet MTU. 1001 */ 1002 sc->sc_ethercom.ec_capabilities |= 1003 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1004 1005 /* 1006 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1007 * in hardware. 1008 */ 1009 ifp->if_capabilities |= 1010 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1011 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1012 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1013 #endif /* DP83820 */ 1014 1015 /* 1016 * Attach the interface. 1017 */ 1018 if_attach(ifp); 1019 ether_ifattach(ifp, enaddr); 1020 #if NRND > 0 1021 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1022 RND_TYPE_NET, 0); 1023 #endif 1024 1025 /* 1026 * The number of bytes that must be available in 1027 * the Tx FIFO before the bus master can DMA more 1028 * data into the FIFO. 1029 */ 1030 sc->sc_tx_fill_thresh = 64 / 32; 1031 1032 /* 1033 * Start at a drain threshold of 512 bytes. We will 1034 * increase it if a DMA underrun occurs. 1035 * 1036 * XXX The minimum value of this variable should be 1037 * tuned. We may be able to improve performance 1038 * by starting with a lower value. That, however, 1039 * may trash the first few outgoing packets if the 1040 * PCI bus is saturated. 1041 */ 1042 #ifdef DP83820 1043 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1044 #else 1045 sc->sc_tx_drain_thresh = 1504 / 32; 1046 #endif 1047 1048 /* 1049 * Initialize the Rx FIFO drain threshold. 1050 * 1051 * This is in units of 8 bytes. 1052 * 1053 * We should never set this value lower than 2; 14 bytes are 1054 * required to filter the packet. 1055 */ 1056 sc->sc_rx_drain_thresh = 128 / 8; 1057 1058 #ifdef SIP_EVENT_COUNTERS 1059 /* 1060 * Attach event counters. 1061 */ 1062 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txsstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1065 NULL, sc->sc_dev.dv_xname, "txdstall"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txdintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "txiintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "rxintr"); 1074 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1075 NULL, sc->sc_dev.dv_xname, "hiberr"); 1076 #ifndef DP83820 1077 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1078 NULL, sc->sc_dev.dv_xname, "rxpause"); 1079 #endif /* !DP83820 */ 1080 #ifdef DP83820 1081 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "rxpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "txpause"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txipsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1095 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1096 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1097 #endif /* DP83820 */ 1098 #endif /* SIP_EVENT_COUNTERS */ 1099 1100 /* 1101 * Make sure the interface is shutdown during reboot. 1102 */ 1103 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1104 if (sc->sc_sdhook == NULL) 1105 printf("%s: WARNING: unable to establish shutdown hook\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 1109 /* 1110 * Free any resources we've allocated during the failed attach 1111 * attempt. Do this in reverse order and fall through. 1112 */ 1113 fail_5: 1114 for (i = 0; i < SIP_NRXDESC; i++) { 1115 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1116 bus_dmamap_destroy(sc->sc_dmat, 1117 sc->sc_rxsoft[i].rxs_dmamap); 1118 } 1119 fail_4: 1120 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1121 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1122 bus_dmamap_destroy(sc->sc_dmat, 1123 sc->sc_txsoft[i].txs_dmamap); 1124 } 1125 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_3: 1127 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1128 fail_2: 1129 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 1130 sizeof(struct sip_control_data)); 1131 fail_1: 1132 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1133 fail_0: 1134 return; 1135 } 1136 1137 /* 1138 * sip_shutdown: 1139 * 1140 * Make sure the interface is stopped at reboot time. 1141 */ 1142 static void 1143 SIP_DECL(shutdown)(void *arg) 1144 { 1145 struct sip_softc *sc = arg; 1146 1147 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1148 } 1149 1150 /* 1151 * sip_start: [ifnet interface function] 1152 * 1153 * Start packet transmission on the interface. 1154 */ 1155 static void 1156 SIP_DECL(start)(struct ifnet *ifp) 1157 { 1158 struct sip_softc *sc = ifp->if_softc; 1159 struct mbuf *m0; 1160 #ifndef DP83820 1161 struct mbuf *m; 1162 #endif 1163 struct sip_txsoft *txs; 1164 bus_dmamap_t dmamap; 1165 int error, nexttx, lasttx, seg; 1166 int ofree = sc->sc_txfree; 1167 #if 0 1168 int firsttx = sc->sc_txnext; 1169 #endif 1170 #ifdef DP83820 1171 struct m_tag *mtag; 1172 u_int32_t extsts; 1173 #endif 1174 1175 #ifndef DP83820 1176 /* 1177 * If we've been told to pause, don't transmit any more packets. 1178 */ 1179 if (sc->sc_paused) 1180 ifp->if_flags |= IFF_OACTIVE; 1181 #endif 1182 1183 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1184 return; 1185 1186 /* 1187 * Loop through the send queue, setting up transmit descriptors 1188 * until we drain the queue, or use up all available transmit 1189 * descriptors. 1190 */ 1191 for (;;) { 1192 /* Get a work queue entry. */ 1193 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1194 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1195 break; 1196 } 1197 1198 /* 1199 * Grab a packet off the queue. 1200 */ 1201 IFQ_POLL(&ifp->if_snd, m0); 1202 if (m0 == NULL) 1203 break; 1204 #ifndef DP83820 1205 m = NULL; 1206 #endif 1207 1208 dmamap = txs->txs_dmamap; 1209 1210 #ifdef DP83820 1211 /* 1212 * Load the DMA map. If this fails, the packet either 1213 * didn't fit in the allotted number of segments, or we 1214 * were short on resources. For the too-many-segments 1215 * case, we simply report an error and drop the packet, 1216 * since we can't sanely copy a jumbo packet to a single 1217 * buffer. 1218 */ 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1220 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1221 if (error) { 1222 if (error == EFBIG) { 1223 printf("%s: Tx packet consumes too many " 1224 "DMA segments, dropping...\n", 1225 sc->sc_dev.dv_xname); 1226 IFQ_DEQUEUE(&ifp->if_snd, m0); 1227 m_freem(m0); 1228 continue; 1229 } 1230 /* 1231 * Short on resources, just stop for now. 1232 */ 1233 break; 1234 } 1235 #else /* DP83820 */ 1236 /* 1237 * Load the DMA map. If this fails, the packet either 1238 * didn't fit in the alloted number of segments, or we 1239 * were short on resources. In this case, we'll copy 1240 * and try again. 1241 */ 1242 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1243 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1244 MGETHDR(m, M_DONTWAIT, MT_DATA); 1245 if (m == NULL) { 1246 printf("%s: unable to allocate Tx mbuf\n", 1247 sc->sc_dev.dv_xname); 1248 break; 1249 } 1250 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1251 if (m0->m_pkthdr.len > MHLEN) { 1252 MCLGET(m, M_DONTWAIT); 1253 if ((m->m_flags & M_EXT) == 0) { 1254 printf("%s: unable to allocate Tx " 1255 "cluster\n", sc->sc_dev.dv_xname); 1256 m_freem(m); 1257 break; 1258 } 1259 } 1260 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1261 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1262 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1263 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1264 if (error) { 1265 printf("%s: unable to load Tx buffer, " 1266 "error = %d\n", sc->sc_dev.dv_xname, error); 1267 break; 1268 } 1269 } 1270 #endif /* DP83820 */ 1271 1272 /* 1273 * Ensure we have enough descriptors free to describe 1274 * the packet. Note, we always reserve one descriptor 1275 * at the end of the ring as a termination point, to 1276 * prevent wrap-around. 1277 */ 1278 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1279 /* 1280 * Not enough free descriptors to transmit this 1281 * packet. We haven't committed anything yet, 1282 * so just unload the DMA map, put the packet 1283 * back on the queue, and punt. Notify the upper 1284 * layer that there are not more slots left. 1285 * 1286 * XXX We could allocate an mbuf and copy, but 1287 * XXX is it worth it? 1288 */ 1289 ifp->if_flags |= IFF_OACTIVE; 1290 bus_dmamap_unload(sc->sc_dmat, dmamap); 1291 #ifndef DP83820 1292 if (m != NULL) 1293 m_freem(m); 1294 #endif 1295 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1296 break; 1297 } 1298 1299 IFQ_DEQUEUE(&ifp->if_snd, m0); 1300 #ifndef DP83820 1301 if (m != NULL) { 1302 m_freem(m0); 1303 m0 = m; 1304 } 1305 #endif 1306 1307 /* 1308 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1309 */ 1310 1311 /* Sync the DMA map. */ 1312 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1313 BUS_DMASYNC_PREWRITE); 1314 1315 /* 1316 * Initialize the transmit descriptors. 1317 */ 1318 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1319 seg < dmamap->dm_nsegs; 1320 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1321 /* 1322 * If this is the first descriptor we're 1323 * enqueueing, don't set the OWN bit just 1324 * yet. That could cause a race condition. 1325 * We'll do it below. 1326 */ 1327 sc->sc_txdescs[nexttx].sipd_bufptr = 1328 htole32(dmamap->dm_segs[seg].ds_addr); 1329 sc->sc_txdescs[nexttx].sipd_cmdsts = 1330 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1331 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1332 #ifdef DP83820 1333 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1334 #endif /* DP83820 */ 1335 lasttx = nexttx; 1336 } 1337 1338 /* Clear the MORE bit on the last segment. */ 1339 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1340 1341 /* 1342 * If we're in the interrupt delay window, delay the 1343 * interrupt. 1344 */ 1345 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1346 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1347 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1348 htole32(CMDSTS_INTR); 1349 sc->sc_txwin = 0; 1350 } 1351 1352 #ifdef DP83820 1353 /* 1354 * If VLANs are enabled and the packet has a VLAN tag, set 1355 * up the descriptor to encapsulate the packet for us. 1356 * 1357 * This apparently has to be on the last descriptor of 1358 * the packet. 1359 */ 1360 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1361 sc->sc_txdescs[lasttx].sipd_extsts |= 1362 htole32(EXTSTS_VPKT | 1363 (VLAN_TAG_VALUE(mtag) & EXTSTS_VTCI)); 1364 } 1365 1366 /* 1367 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1368 * checksumming, set up the descriptor to do this work 1369 * for us. 1370 * 1371 * This apparently has to be on the first descriptor of 1372 * the packet. 1373 * 1374 * Byte-swap constants so the compiler can optimize. 1375 */ 1376 extsts = 0; 1377 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1378 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1379 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1380 extsts |= htole32(EXTSTS_IPPKT); 1381 } 1382 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1383 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1384 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1385 extsts |= htole32(EXTSTS_TCPPKT); 1386 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1387 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1388 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1389 extsts |= htole32(EXTSTS_UDPPKT); 1390 } 1391 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1392 #endif /* DP83820 */ 1393 1394 /* Sync the descriptors we're using. */ 1395 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1396 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1397 1398 /* 1399 * The entire packet is set up. Give the first descrptor 1400 * to the chip now. 1401 */ 1402 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1403 htole32(CMDSTS_OWN); 1404 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1405 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1406 1407 /* 1408 * Store a pointer to the packet so we can free it later, 1409 * and remember what txdirty will be once the packet is 1410 * done. 1411 */ 1412 txs->txs_mbuf = m0; 1413 txs->txs_firstdesc = sc->sc_txnext; 1414 txs->txs_lastdesc = lasttx; 1415 1416 /* Advance the tx pointer. */ 1417 sc->sc_txfree -= dmamap->dm_nsegs; 1418 sc->sc_txnext = nexttx; 1419 1420 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1421 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1422 1423 #if NBPFILTER > 0 1424 /* 1425 * Pass the packet to any BPF listeners. 1426 */ 1427 if (ifp->if_bpf) 1428 bpf_mtap(ifp->if_bpf, m0); 1429 #endif /* NBPFILTER > 0 */ 1430 } 1431 1432 if (txs == NULL || sc->sc_txfree == 0) { 1433 /* No more slots left; notify upper layer. */ 1434 ifp->if_flags |= IFF_OACTIVE; 1435 } 1436 1437 if (sc->sc_txfree != ofree) { 1438 /* 1439 * Start the transmit process. Note, the manual says 1440 * that if there are no pending transmissions in the 1441 * chip's internal queue (indicated by TXE being clear), 1442 * then the driver software must set the TXDP to the 1443 * first descriptor to be transmitted. However, if we 1444 * do this, it causes serious performance degredation on 1445 * the DP83820 under load, not setting TXDP doesn't seem 1446 * to adversely affect the SiS 900 or DP83815. 1447 * 1448 * Well, I guess it wouldn't be the first time a manual 1449 * has lied -- and they could be speaking of the NULL- 1450 * terminated descriptor list case, rather than OWN- 1451 * terminated rings. 1452 */ 1453 #if 0 1454 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1455 CR_TXE) == 0) { 1456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1457 SIP_CDTXADDR(sc, firsttx)); 1458 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1459 } 1460 #else 1461 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1462 #endif 1463 1464 /* Set a watchdog timer in case the chip flakes out. */ 1465 #ifdef DP83820 1466 /* Gigabit autonegotiation takes 5 seconds. */ 1467 ifp->if_timer = 10; 1468 #else 1469 ifp->if_timer = 5; 1470 #endif 1471 } 1472 } 1473 1474 /* 1475 * sip_watchdog: [ifnet interface function] 1476 * 1477 * Watchdog timer handler. 1478 */ 1479 static void 1480 SIP_DECL(watchdog)(struct ifnet *ifp) 1481 { 1482 struct sip_softc *sc = ifp->if_softc; 1483 1484 /* 1485 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1486 * If we get a timeout, try and sweep up transmit descriptors. 1487 * If we manage to sweep them all up, ignore the lack of 1488 * interrupt. 1489 */ 1490 SIP_DECL(txintr)(sc); 1491 1492 if (sc->sc_txfree != SIP_NTXDESC) { 1493 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1494 ifp->if_oerrors++; 1495 1496 /* Reset the interface. */ 1497 (void) SIP_DECL(init)(ifp); 1498 } else if (ifp->if_flags & IFF_DEBUG) 1499 printf("%s: recovered from device timeout\n", 1500 sc->sc_dev.dv_xname); 1501 1502 /* Try to get more packets going. */ 1503 SIP_DECL(start)(ifp); 1504 } 1505 1506 /* 1507 * sip_ioctl: [ifnet interface function] 1508 * 1509 * Handle control requests from the operator. 1510 */ 1511 static int 1512 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, caddr_t data) 1513 { 1514 struct sip_softc *sc = ifp->if_softc; 1515 struct ifreq *ifr = (struct ifreq *)data; 1516 int s, error; 1517 1518 s = splnet(); 1519 1520 switch (cmd) { 1521 case SIOCSIFMEDIA: 1522 /* Flow control requires full-duplex mode. */ 1523 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1524 (ifr->ifr_media & IFM_FDX) == 0) 1525 ifr->ifr_media &= ~IFM_ETH_FMASK; 1526 #ifdef DP83820 1527 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1528 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1529 /* We can do both TXPAUSE and RXPAUSE. */ 1530 ifr->ifr_media |= 1531 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1532 } 1533 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1534 } 1535 #else 1536 /* XXX */ 1537 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1538 ifr->ifr_media &= ~IFM_ETH_FMASK; 1539 1540 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1541 if (ifr->ifr_media & IFM_FLOW) { 1542 /* 1543 * Both TXPAUSE and RXPAUSE must be set. 1544 * (SiS900 and DP83815 don't have PAUSE_ASYM 1545 * feature.) 1546 * 1547 * XXX Can SiS900 and DP83815 send PAUSE? 1548 */ 1549 ifr->ifr_media |= 1550 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1551 } 1552 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1553 } 1554 #endif 1555 /* FALLTHROUGH */ 1556 case SIOCGIFMEDIA: 1557 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1558 break; 1559 case SIOCSIFFLAGS: 1560 /* If the interface is up and running, only modify the receive 1561 * filter when setting promiscuous or debug mode. Otherwise 1562 * fall through to ether_ioctl, which will reset the chip. 1563 */ 1564 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1565 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1566 == (IFF_UP|IFF_RUNNING)) 1567 && ((ifp->if_flags & (~RESETIGN)) 1568 == (sc->sc_if_flags & (~RESETIGN)))) { 1569 /* Set up the receive filter. */ 1570 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1571 error = 0; 1572 break; 1573 #undef RESETIGN 1574 } 1575 /* FALLTHROUGH */ 1576 default: 1577 error = ether_ioctl(ifp, cmd, data); 1578 if (error == ENETRESET) { 1579 /* 1580 * Multicast list has changed; set the hardware filter 1581 * accordingly. 1582 */ 1583 if (ifp->if_flags & IFF_RUNNING) 1584 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1585 error = 0; 1586 } 1587 break; 1588 } 1589 1590 /* Try to get more packets going. */ 1591 SIP_DECL(start)(ifp); 1592 1593 sc->sc_if_flags = ifp->if_flags; 1594 splx(s); 1595 return (error); 1596 } 1597 1598 /* 1599 * sip_intr: 1600 * 1601 * Interrupt service routine. 1602 */ 1603 static int 1604 SIP_DECL(intr)(void *arg) 1605 { 1606 struct sip_softc *sc = arg; 1607 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1608 u_int32_t isr; 1609 int handled = 0; 1610 1611 /* Disable interrupts. */ 1612 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1613 1614 for (;;) { 1615 /* Reading clears interrupt. */ 1616 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1617 if ((isr & sc->sc_imr) == 0) 1618 break; 1619 1620 #if NRND > 0 1621 if (RND_ENABLED(&sc->rnd_source)) 1622 rnd_add_uint32(&sc->rnd_source, isr); 1623 #endif 1624 1625 handled = 1; 1626 1627 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1628 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1629 1630 /* Grab any new packets. */ 1631 SIP_DECL(rxintr)(sc); 1632 1633 if (isr & ISR_RXORN) { 1634 printf("%s: receive FIFO overrun\n", 1635 sc->sc_dev.dv_xname); 1636 1637 /* XXX adjust rx_drain_thresh? */ 1638 } 1639 1640 if (isr & ISR_RXIDLE) { 1641 printf("%s: receive ring overrun\n", 1642 sc->sc_dev.dv_xname); 1643 1644 /* Get the receive process going again. */ 1645 bus_space_write_4(sc->sc_st, sc->sc_sh, 1646 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1647 bus_space_write_4(sc->sc_st, sc->sc_sh, 1648 SIP_CR, CR_RXE); 1649 } 1650 } 1651 1652 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1653 #ifdef SIP_EVENT_COUNTERS 1654 if (isr & ISR_TXDESC) 1655 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1656 else if (isr & ISR_TXIDLE) 1657 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1658 #endif 1659 1660 /* Sweep up transmit descriptors. */ 1661 SIP_DECL(txintr)(sc); 1662 1663 if (isr & ISR_TXURN) { 1664 u_int32_t thresh; 1665 1666 printf("%s: transmit FIFO underrun", 1667 sc->sc_dev.dv_xname); 1668 1669 thresh = sc->sc_tx_drain_thresh + 1; 1670 if (thresh <= TXCFG_DRTH && 1671 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1672 (sc->sc_tx_fill_thresh * 32))) { 1673 printf("; increasing Tx drain " 1674 "threshold to %u bytes\n", 1675 thresh * 32); 1676 sc->sc_tx_drain_thresh = thresh; 1677 (void) SIP_DECL(init)(ifp); 1678 } else { 1679 (void) SIP_DECL(init)(ifp); 1680 printf("\n"); 1681 } 1682 } 1683 } 1684 1685 #if !defined(DP83820) 1686 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1687 if (isr & ISR_PAUSE_ST) { 1688 sc->sc_paused = 1; 1689 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1690 ifp->if_flags |= IFF_OACTIVE; 1691 } 1692 if (isr & ISR_PAUSE_END) { 1693 sc->sc_paused = 0; 1694 ifp->if_flags &= ~IFF_OACTIVE; 1695 } 1696 } 1697 #endif /* ! DP83820 */ 1698 1699 if (isr & ISR_HIBERR) { 1700 int want_init = 0; 1701 1702 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1703 1704 #define PRINTERR(bit, str) \ 1705 do { \ 1706 if ((isr & (bit)) != 0) { \ 1707 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1708 printf("%s: %s\n", \ 1709 sc->sc_dev.dv_xname, str); \ 1710 want_init = 1; \ 1711 } \ 1712 } while (/*CONSTCOND*/0) 1713 1714 PRINTERR(ISR_DPERR, "parity error"); 1715 PRINTERR(ISR_SSERR, "system error"); 1716 PRINTERR(ISR_RMABT, "master abort"); 1717 PRINTERR(ISR_RTABT, "target abort"); 1718 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1719 /* 1720 * Ignore: 1721 * Tx reset complete 1722 * Rx reset complete 1723 */ 1724 if (want_init) 1725 (void) SIP_DECL(init)(ifp); 1726 #undef PRINTERR 1727 } 1728 } 1729 1730 /* Re-enable interrupts. */ 1731 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1732 1733 /* Try to get more packets going. */ 1734 SIP_DECL(start)(ifp); 1735 1736 return (handled); 1737 } 1738 1739 /* 1740 * sip_txintr: 1741 * 1742 * Helper; handle transmit interrupts. 1743 */ 1744 static void 1745 SIP_DECL(txintr)(struct sip_softc *sc) 1746 { 1747 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1748 struct sip_txsoft *txs; 1749 u_int32_t cmdsts; 1750 1751 #ifndef DP83820 1752 if (sc->sc_paused == 0) 1753 #endif 1754 ifp->if_flags &= ~IFF_OACTIVE; 1755 1756 /* 1757 * Go through our Tx list and free mbufs for those 1758 * frames which have been transmitted. 1759 */ 1760 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1761 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1762 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1763 1764 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1765 if (cmdsts & CMDSTS_OWN) 1766 break; 1767 1768 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1769 1770 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1771 1772 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1773 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1774 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1775 m_freem(txs->txs_mbuf); 1776 txs->txs_mbuf = NULL; 1777 1778 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1779 1780 /* 1781 * Check for errors and collisions. 1782 */ 1783 if (cmdsts & 1784 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1785 ifp->if_oerrors++; 1786 if (cmdsts & CMDSTS_Tx_EC) 1787 ifp->if_collisions += 16; 1788 if (ifp->if_flags & IFF_DEBUG) { 1789 if (cmdsts & CMDSTS_Tx_ED) 1790 printf("%s: excessive deferral\n", 1791 sc->sc_dev.dv_xname); 1792 if (cmdsts & CMDSTS_Tx_EC) 1793 printf("%s: excessive collisions\n", 1794 sc->sc_dev.dv_xname); 1795 } 1796 } else { 1797 /* Packet was transmitted successfully. */ 1798 ifp->if_opackets++; 1799 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1800 } 1801 } 1802 1803 /* 1804 * If there are no more pending transmissions, cancel the watchdog 1805 * timer. 1806 */ 1807 if (txs == NULL) { 1808 ifp->if_timer = 0; 1809 sc->sc_txwin = 0; 1810 } 1811 } 1812 1813 #if defined(DP83820) 1814 /* 1815 * sip_rxintr: 1816 * 1817 * Helper; handle receive interrupts. 1818 */ 1819 static void 1820 SIP_DECL(rxintr)(struct sip_softc *sc) 1821 { 1822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1823 struct sip_rxsoft *rxs; 1824 struct mbuf *m; 1825 u_int32_t cmdsts, extsts; 1826 int i, len; 1827 1828 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1829 rxs = &sc->sc_rxsoft[i]; 1830 1831 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1832 1833 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1834 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1835 len = CMDSTS_SIZE(cmdsts); 1836 1837 /* 1838 * NOTE: OWN is set if owned by _consumer_. We're the 1839 * consumer of the receive ring, so if the bit is clear, 1840 * we have processed all of the packets. 1841 */ 1842 if ((cmdsts & CMDSTS_OWN) == 0) { 1843 /* 1844 * We have processed all of the receive buffers. 1845 */ 1846 break; 1847 } 1848 1849 if (__predict_false(sc->sc_rxdiscard)) { 1850 SIP_INIT_RXDESC(sc, i); 1851 if ((cmdsts & CMDSTS_MORE) == 0) { 1852 /* Reset our state. */ 1853 sc->sc_rxdiscard = 0; 1854 } 1855 continue; 1856 } 1857 1858 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1859 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1860 1861 m = rxs->rxs_mbuf; 1862 1863 /* 1864 * Add a new receive buffer to the ring. 1865 */ 1866 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1867 /* 1868 * Failed, throw away what we've done so 1869 * far, and discard the rest of the packet. 1870 */ 1871 ifp->if_ierrors++; 1872 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1873 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1874 SIP_INIT_RXDESC(sc, i); 1875 if (cmdsts & CMDSTS_MORE) 1876 sc->sc_rxdiscard = 1; 1877 if (sc->sc_rxhead != NULL) 1878 m_freem(sc->sc_rxhead); 1879 SIP_RXCHAIN_RESET(sc); 1880 continue; 1881 } 1882 1883 SIP_RXCHAIN_LINK(sc, m); 1884 1885 m->m_len = len; 1886 1887 /* 1888 * If this is not the end of the packet, keep 1889 * looking. 1890 */ 1891 if (cmdsts & CMDSTS_MORE) { 1892 sc->sc_rxlen += len; 1893 continue; 1894 } 1895 1896 /* 1897 * Okay, we have the entire packet now. The chip includes 1898 * the FCS, so we need to trim it. 1899 */ 1900 m->m_len -= ETHER_CRC_LEN; 1901 1902 *sc->sc_rxtailp = NULL; 1903 len = m->m_len + sc->sc_rxlen; 1904 m = sc->sc_rxhead; 1905 1906 SIP_RXCHAIN_RESET(sc); 1907 1908 /* 1909 * If an error occurred, update stats and drop the packet. 1910 */ 1911 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1912 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1913 ifp->if_ierrors++; 1914 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1915 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1916 /* Receive overrun handled elsewhere. */ 1917 printf("%s: receive descriptor error\n", 1918 sc->sc_dev.dv_xname); 1919 } 1920 #define PRINTERR(bit, str) \ 1921 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1922 (cmdsts & (bit)) != 0) \ 1923 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1924 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1925 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1926 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1927 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1928 #undef PRINTERR 1929 m_freem(m); 1930 continue; 1931 } 1932 1933 /* 1934 * If the packet is small enough to fit in a 1935 * single header mbuf, allocate one and copy 1936 * the data into it. This greatly reduces 1937 * memory consumption when we receive lots 1938 * of small packets. 1939 */ 1940 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1941 struct mbuf *nm; 1942 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1943 if (nm == NULL) { 1944 ifp->if_ierrors++; 1945 m_freem(m); 1946 continue; 1947 } 1948 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1949 nm->m_data += 2; 1950 nm->m_pkthdr.len = nm->m_len = len; 1951 m_copydata(m, 0, len, mtod(nm, caddr_t)); 1952 m_freem(m); 1953 m = nm; 1954 } 1955 #ifndef __NO_STRICT_ALIGNMENT 1956 else { 1957 /* 1958 * The DP83820's receive buffers must be 4-byte 1959 * aligned. But this means that the data after 1960 * the Ethernet header is misaligned. To compensate, 1961 * we have artificially shortened the buffer size 1962 * in the descriptor, and we do an overlapping copy 1963 * of the data two bytes further in (in the first 1964 * buffer of the chain only). 1965 */ 1966 memmove(mtod(m, caddr_t) + 2, mtod(m, caddr_t), 1967 m->m_len); 1968 m->m_data += 2; 1969 } 1970 #endif /* ! __NO_STRICT_ALIGNMENT */ 1971 1972 /* 1973 * If VLANs are enabled, VLAN packets have been unwrapped 1974 * for us. Associate the tag with the packet. 1975 */ 1976 if ((extsts & EXTSTS_VPKT) != 0) { 1977 VLAN_INPUT_TAG(ifp, m, ntohs(extsts & EXTSTS_VTCI), 1978 continue); 1979 } 1980 1981 /* 1982 * Set the incoming checksum information for the 1983 * packet. 1984 */ 1985 if ((extsts & EXTSTS_IPPKT) != 0) { 1986 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 1987 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1988 if (extsts & EXTSTS_Rx_IPERR) 1989 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1990 if (extsts & EXTSTS_TCPPKT) { 1991 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 1992 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1993 if (extsts & EXTSTS_Rx_TCPERR) 1994 m->m_pkthdr.csum_flags |= 1995 M_CSUM_TCP_UDP_BAD; 1996 } else if (extsts & EXTSTS_UDPPKT) { 1997 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 1998 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1999 if (extsts & EXTSTS_Rx_UDPERR) 2000 m->m_pkthdr.csum_flags |= 2001 M_CSUM_TCP_UDP_BAD; 2002 } 2003 } 2004 2005 ifp->if_ipackets++; 2006 m->m_pkthdr.rcvif = ifp; 2007 m->m_pkthdr.len = len; 2008 2009 #if NBPFILTER > 0 2010 /* 2011 * Pass this up to any BPF listeners, but only 2012 * pass if up the stack if it's for us. 2013 */ 2014 if (ifp->if_bpf) 2015 bpf_mtap(ifp->if_bpf, m); 2016 #endif /* NBPFILTER > 0 */ 2017 2018 /* Pass it on. */ 2019 (*ifp->if_input)(ifp, m); 2020 } 2021 2022 /* Update the receive pointer. */ 2023 sc->sc_rxptr = i; 2024 } 2025 #else /* ! DP83820 */ 2026 /* 2027 * sip_rxintr: 2028 * 2029 * Helper; handle receive interrupts. 2030 */ 2031 static void 2032 SIP_DECL(rxintr)(struct sip_softc *sc) 2033 { 2034 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2035 struct sip_rxsoft *rxs; 2036 struct mbuf *m; 2037 u_int32_t cmdsts; 2038 int i, len; 2039 2040 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2041 rxs = &sc->sc_rxsoft[i]; 2042 2043 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2044 2045 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2046 2047 /* 2048 * NOTE: OWN is set if owned by _consumer_. We're the 2049 * consumer of the receive ring, so if the bit is clear, 2050 * we have processed all of the packets. 2051 */ 2052 if ((cmdsts & CMDSTS_OWN) == 0) { 2053 /* 2054 * We have processed all of the receive buffers. 2055 */ 2056 break; 2057 } 2058 2059 /* 2060 * If any collisions were seen on the wire, count one. 2061 */ 2062 if (cmdsts & CMDSTS_Rx_COL) 2063 ifp->if_collisions++; 2064 2065 /* 2066 * If an error occurred, update stats, clear the status 2067 * word, and leave the packet buffer in place. It will 2068 * simply be reused the next time the ring comes around. 2069 */ 2070 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2071 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2072 ifp->if_ierrors++; 2073 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2074 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2075 /* Receive overrun handled elsewhere. */ 2076 printf("%s: receive descriptor error\n", 2077 sc->sc_dev.dv_xname); 2078 } 2079 #define PRINTERR(bit, str) \ 2080 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2081 (cmdsts & (bit)) != 0) \ 2082 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2083 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2084 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2085 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2086 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2087 #undef PRINTERR 2088 SIP_INIT_RXDESC(sc, i); 2089 continue; 2090 } 2091 2092 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2093 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2094 2095 /* 2096 * No errors; receive the packet. Note, the SiS 900 2097 * includes the CRC with every packet. 2098 */ 2099 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2100 2101 #ifdef __NO_STRICT_ALIGNMENT 2102 /* 2103 * If the packet is small enough to fit in a 2104 * single header mbuf, allocate one and copy 2105 * the data into it. This greatly reduces 2106 * memory consumption when we receive lots 2107 * of small packets. 2108 * 2109 * Otherwise, we add a new buffer to the receive 2110 * chain. If this fails, we drop the packet and 2111 * recycle the old buffer. 2112 */ 2113 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2114 MGETHDR(m, M_DONTWAIT, MT_DATA); 2115 if (m == NULL) 2116 goto dropit; 2117 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2118 memcpy(mtod(m, caddr_t), 2119 mtod(rxs->rxs_mbuf, caddr_t), len); 2120 SIP_INIT_RXDESC(sc, i); 2121 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2122 rxs->rxs_dmamap->dm_mapsize, 2123 BUS_DMASYNC_PREREAD); 2124 } else { 2125 m = rxs->rxs_mbuf; 2126 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2127 dropit: 2128 ifp->if_ierrors++; 2129 SIP_INIT_RXDESC(sc, i); 2130 bus_dmamap_sync(sc->sc_dmat, 2131 rxs->rxs_dmamap, 0, 2132 rxs->rxs_dmamap->dm_mapsize, 2133 BUS_DMASYNC_PREREAD); 2134 continue; 2135 } 2136 } 2137 #else 2138 /* 2139 * The SiS 900's receive buffers must be 4-byte aligned. 2140 * But this means that the data after the Ethernet header 2141 * is misaligned. We must allocate a new buffer and 2142 * copy the data, shifted forward 2 bytes. 2143 */ 2144 MGETHDR(m, M_DONTWAIT, MT_DATA); 2145 if (m == NULL) { 2146 dropit: 2147 ifp->if_ierrors++; 2148 SIP_INIT_RXDESC(sc, i); 2149 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2150 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2151 continue; 2152 } 2153 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2154 if (len > (MHLEN - 2)) { 2155 MCLGET(m, M_DONTWAIT); 2156 if ((m->m_flags & M_EXT) == 0) { 2157 m_freem(m); 2158 goto dropit; 2159 } 2160 } 2161 m->m_data += 2; 2162 2163 /* 2164 * Note that we use clusters for incoming frames, so the 2165 * buffer is virtually contiguous. 2166 */ 2167 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 2168 2169 /* Allow the receive descriptor to continue using its mbuf. */ 2170 SIP_INIT_RXDESC(sc, i); 2171 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2172 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2173 #endif /* __NO_STRICT_ALIGNMENT */ 2174 2175 ifp->if_ipackets++; 2176 m->m_pkthdr.rcvif = ifp; 2177 m->m_pkthdr.len = m->m_len = len; 2178 2179 #if NBPFILTER > 0 2180 /* 2181 * Pass this up to any BPF listeners, but only 2182 * pass if up the stack if it's for us. 2183 */ 2184 if (ifp->if_bpf) 2185 bpf_mtap(ifp->if_bpf, m); 2186 #endif /* NBPFILTER > 0 */ 2187 2188 /* Pass it on. */ 2189 (*ifp->if_input)(ifp, m); 2190 } 2191 2192 /* Update the receive pointer. */ 2193 sc->sc_rxptr = i; 2194 } 2195 #endif /* DP83820 */ 2196 2197 /* 2198 * sip_tick: 2199 * 2200 * One second timer, used to tick the MII. 2201 */ 2202 static void 2203 SIP_DECL(tick)(void *arg) 2204 { 2205 struct sip_softc *sc = arg; 2206 int s; 2207 2208 s = splnet(); 2209 #ifdef DP83820 2210 #ifdef SIP_EVENT_COUNTERS 2211 /* Read PAUSE related counts from MIB registers. */ 2212 sc->sc_ev_rxpause.ev_count += 2213 bus_space_read_4(sc->sc_st, sc->sc_sh, 2214 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2215 sc->sc_ev_txpause.ev_count += 2216 bus_space_read_4(sc->sc_st, sc->sc_sh, 2217 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2218 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2219 #endif /* SIP_EVENT_COUNTERS */ 2220 #endif /* DP83820 */ 2221 mii_tick(&sc->sc_mii); 2222 splx(s); 2223 2224 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2225 } 2226 2227 /* 2228 * sip_reset: 2229 * 2230 * Perform a soft reset on the SiS 900. 2231 */ 2232 static void 2233 SIP_DECL(reset)(struct sip_softc *sc) 2234 { 2235 bus_space_tag_t st = sc->sc_st; 2236 bus_space_handle_t sh = sc->sc_sh; 2237 int i; 2238 2239 bus_space_write_4(st, sh, SIP_IER, 0); 2240 bus_space_write_4(st, sh, SIP_IMR, 0); 2241 bus_space_write_4(st, sh, SIP_RFCR, 0); 2242 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2243 2244 for (i = 0; i < SIP_TIMEOUT; i++) { 2245 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2246 break; 2247 delay(2); 2248 } 2249 2250 if (i == SIP_TIMEOUT) 2251 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2252 2253 delay(1000); 2254 2255 #ifdef DP83820 2256 /* 2257 * Set the general purpose I/O bits. Do it here in case we 2258 * need to have GPIO set up to talk to the media interface. 2259 */ 2260 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2261 delay(1000); 2262 #endif /* DP83820 */ 2263 } 2264 2265 /* 2266 * sip_init: [ ifnet interface function ] 2267 * 2268 * Initialize the interface. Must be called at splnet(). 2269 */ 2270 static int 2271 SIP_DECL(init)(struct ifnet *ifp) 2272 { 2273 struct sip_softc *sc = ifp->if_softc; 2274 bus_space_tag_t st = sc->sc_st; 2275 bus_space_handle_t sh = sc->sc_sh; 2276 struct sip_txsoft *txs; 2277 struct sip_rxsoft *rxs; 2278 struct sip_desc *sipd; 2279 #if defined(DP83820) 2280 u_int32_t reg; 2281 #endif 2282 int i, error = 0; 2283 2284 /* 2285 * Cancel any pending I/O. 2286 */ 2287 SIP_DECL(stop)(ifp, 0); 2288 2289 /* 2290 * Reset the chip to a known state. 2291 */ 2292 SIP_DECL(reset)(sc); 2293 2294 #if !defined(DP83820) 2295 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2296 /* 2297 * DP83815 manual, page 78: 2298 * 4.4 Recommended Registers Configuration 2299 * For optimum performance of the DP83815, version noted 2300 * as DP83815CVNG (SRR = 203h), the listed register 2301 * modifications must be followed in sequence... 2302 * 2303 * It's not clear if this should be 302h or 203h because that 2304 * chip name is listed as SRR 302h in the description of the 2305 * SRR register. However, my revision 302h DP83815 on the 2306 * Netgear FA311 purchased in 02/2001 needs these settings 2307 * to avoid tons of errors in AcceptPerfectMatch (non- 2308 * IFF_PROMISC) mode. I do not know if other revisions need 2309 * this set or not. [briggs -- 09 March 2001] 2310 * 2311 * Note that only the low-order 12 bits of 0xe4 are documented 2312 * and that this sets reserved bits in that register. 2313 */ 2314 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2315 2316 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2317 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2318 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2319 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2320 2321 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2322 } 2323 #endif /* ! DP83820 */ 2324 2325 /* 2326 * Initialize the transmit descriptor ring. 2327 */ 2328 for (i = 0; i < SIP_NTXDESC; i++) { 2329 sipd = &sc->sc_txdescs[i]; 2330 memset(sipd, 0, sizeof(struct sip_desc)); 2331 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2332 } 2333 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2334 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2335 sc->sc_txfree = SIP_NTXDESC; 2336 sc->sc_txnext = 0; 2337 sc->sc_txwin = 0; 2338 2339 /* 2340 * Initialize the transmit job descriptors. 2341 */ 2342 SIMPLEQ_INIT(&sc->sc_txfreeq); 2343 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2344 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2345 txs = &sc->sc_txsoft[i]; 2346 txs->txs_mbuf = NULL; 2347 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2348 } 2349 2350 /* 2351 * Initialize the receive descriptor and receive job 2352 * descriptor rings. 2353 */ 2354 for (i = 0; i < SIP_NRXDESC; i++) { 2355 rxs = &sc->sc_rxsoft[i]; 2356 if (rxs->rxs_mbuf == NULL) { 2357 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2358 printf("%s: unable to allocate or map rx " 2359 "buffer %d, error = %d\n", 2360 sc->sc_dev.dv_xname, i, error); 2361 /* 2362 * XXX Should attempt to run with fewer receive 2363 * XXX buffers instead of just failing. 2364 */ 2365 SIP_DECL(rxdrain)(sc); 2366 goto out; 2367 } 2368 } else 2369 SIP_INIT_RXDESC(sc, i); 2370 } 2371 sc->sc_rxptr = 0; 2372 #ifdef DP83820 2373 sc->sc_rxdiscard = 0; 2374 SIP_RXCHAIN_RESET(sc); 2375 #endif /* DP83820 */ 2376 2377 /* 2378 * Set the configuration register; it's already initialized 2379 * in sip_attach(). 2380 */ 2381 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2382 2383 /* 2384 * Initialize the prototype TXCFG register. 2385 */ 2386 #if defined(DP83820) 2387 sc->sc_txcfg = TXCFG_MXDMA_512; 2388 sc->sc_rxcfg = RXCFG_MXDMA_512; 2389 #else 2390 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2391 SIP_SIS900_REV(sc, SIS_REV_960) || 2392 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2393 (sc->sc_cfg & CFG_EDBMASTEN)) { 2394 sc->sc_txcfg = TXCFG_MXDMA_64; 2395 sc->sc_rxcfg = RXCFG_MXDMA_64; 2396 } else { 2397 sc->sc_txcfg = TXCFG_MXDMA_512; 2398 sc->sc_rxcfg = RXCFG_MXDMA_512; 2399 } 2400 #endif /* DP83820 */ 2401 2402 sc->sc_txcfg |= TXCFG_ATP | 2403 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2404 sc->sc_tx_drain_thresh; 2405 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2406 2407 /* 2408 * Initialize the receive drain threshold if we have never 2409 * done so. 2410 */ 2411 if (sc->sc_rx_drain_thresh == 0) { 2412 /* 2413 * XXX This value should be tuned. This is set to the 2414 * maximum of 248 bytes, and we may be able to improve 2415 * performance by decreasing it (although we should never 2416 * set this value lower than 2; 14 bytes are required to 2417 * filter the packet). 2418 */ 2419 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2420 } 2421 2422 /* 2423 * Initialize the prototype RXCFG register. 2424 */ 2425 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2426 #ifdef DP83820 2427 /* 2428 * Accept long packets (including FCS) so we can handle 2429 * 802.1q-tagged frames and jumbo frames properly. 2430 */ 2431 if (ifp->if_mtu > ETHERMTU || 2432 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2433 sc->sc_rxcfg |= RXCFG_ALP; 2434 2435 /* 2436 * Checksum offloading is disabled if the user selects an MTU 2437 * larger than 8109. (FreeBSD says 8152, but there is emperical 2438 * evidence that >8109 does not work on some boards, such as the 2439 * Planex GN-1000TE). 2440 */ 2441 if (ifp->if_mtu > 8109 && 2442 (ifp->if_capenable & 2443 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2444 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2445 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2446 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2447 "disabled.\n", sc->sc_dev.dv_xname); 2448 ifp->if_capenable &= 2449 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2450 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2451 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2452 ifp->if_csum_flags_tx = 0; 2453 ifp->if_csum_flags_rx = 0; 2454 } 2455 #else 2456 /* 2457 * Accept packets >1518 bytes (including FCS) so we can handle 2458 * 802.1q-tagged frames properly. 2459 */ 2460 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2461 sc->sc_rxcfg |= RXCFG_ALP; 2462 #endif 2463 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2464 2465 #ifdef DP83820 2466 /* 2467 * Initialize the VLAN/IP receive control register. 2468 * We enable checksum computation on all incoming 2469 * packets, and do not reject packets w/ bad checksums. 2470 */ 2471 reg = 0; 2472 if (ifp->if_capenable & 2473 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2474 reg |= VRCR_IPEN; 2475 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2476 reg |= VRCR_VTDEN|VRCR_VTREN; 2477 bus_space_write_4(st, sh, SIP_VRCR, reg); 2478 2479 /* 2480 * Initialize the VLAN/IP transmit control register. 2481 * We enable outgoing checksum computation on a 2482 * per-packet basis. 2483 */ 2484 reg = 0; 2485 if (ifp->if_capenable & 2486 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2487 reg |= VTCR_PPCHK; 2488 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2489 reg |= VTCR_VPPTI; 2490 bus_space_write_4(st, sh, SIP_VTCR, reg); 2491 2492 /* 2493 * If we're using VLANs, initialize the VLAN data register. 2494 * To understand why we bswap the VLAN Ethertype, see section 2495 * 4.2.36 of the DP83820 manual. 2496 */ 2497 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2498 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2499 #endif /* DP83820 */ 2500 2501 /* 2502 * Give the transmit and receive rings to the chip. 2503 */ 2504 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2505 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2506 2507 /* 2508 * Initialize the interrupt mask. 2509 */ 2510 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2511 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2512 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2513 2514 /* Set up the receive filter. */ 2515 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2516 2517 #ifdef DP83820 2518 /* 2519 * Tune sc_rx_flow_thresh. 2520 * XXX "More than 8KB" is too short for jumbo frames. 2521 * XXX TODO: Threshold value should be user-settable. 2522 */ 2523 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2524 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2525 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2526 #endif 2527 2528 /* 2529 * Set the current media. Do this after initializing the prototype 2530 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2531 * control. 2532 */ 2533 mii_mediachg(&sc->sc_mii); 2534 2535 #ifdef DP83820 2536 /* 2537 * Set the interrupt hold-off timer to 100us. 2538 */ 2539 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2540 #endif 2541 2542 /* 2543 * Enable interrupts. 2544 */ 2545 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2546 2547 /* 2548 * Start the transmit and receive processes. 2549 */ 2550 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2551 2552 /* 2553 * Start the one second MII clock. 2554 */ 2555 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2556 2557 /* 2558 * ...all done! 2559 */ 2560 ifp->if_flags |= IFF_RUNNING; 2561 ifp->if_flags &= ~IFF_OACTIVE; 2562 sc->sc_if_flags = ifp->if_flags; 2563 2564 out: 2565 if (error) 2566 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2567 return (error); 2568 } 2569 2570 /* 2571 * sip_drain: 2572 * 2573 * Drain the receive queue. 2574 */ 2575 static void 2576 SIP_DECL(rxdrain)(struct sip_softc *sc) 2577 { 2578 struct sip_rxsoft *rxs; 2579 int i; 2580 2581 for (i = 0; i < SIP_NRXDESC; i++) { 2582 rxs = &sc->sc_rxsoft[i]; 2583 if (rxs->rxs_mbuf != NULL) { 2584 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2585 m_freem(rxs->rxs_mbuf); 2586 rxs->rxs_mbuf = NULL; 2587 } 2588 } 2589 } 2590 2591 /* 2592 * sip_stop: [ ifnet interface function ] 2593 * 2594 * Stop transmission on the interface. 2595 */ 2596 static void 2597 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2598 { 2599 struct sip_softc *sc = ifp->if_softc; 2600 bus_space_tag_t st = sc->sc_st; 2601 bus_space_handle_t sh = sc->sc_sh; 2602 struct sip_txsoft *txs; 2603 u_int32_t cmdsts = 0; /* DEBUG */ 2604 2605 /* 2606 * Stop the one second clock. 2607 */ 2608 callout_stop(&sc->sc_tick_ch); 2609 2610 /* Down the MII. */ 2611 mii_down(&sc->sc_mii); 2612 2613 /* 2614 * Disable interrupts. 2615 */ 2616 bus_space_write_4(st, sh, SIP_IER, 0); 2617 2618 /* 2619 * Stop receiver and transmitter. 2620 */ 2621 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2622 2623 /* 2624 * Release any queued transmit buffers. 2625 */ 2626 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2627 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2628 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2629 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2630 CMDSTS_INTR) == 0) 2631 printf("%s: sip_stop: last descriptor does not " 2632 "have INTR bit set\n", sc->sc_dev.dv_xname); 2633 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2634 #ifdef DIAGNOSTIC 2635 if (txs->txs_mbuf == NULL) { 2636 printf("%s: dirty txsoft with no mbuf chain\n", 2637 sc->sc_dev.dv_xname); 2638 panic("sip_stop"); 2639 } 2640 #endif 2641 cmdsts |= /* DEBUG */ 2642 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2643 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2644 m_freem(txs->txs_mbuf); 2645 txs->txs_mbuf = NULL; 2646 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2647 } 2648 2649 if (disable) 2650 SIP_DECL(rxdrain)(sc); 2651 2652 /* 2653 * Mark the interface down and cancel the watchdog timer. 2654 */ 2655 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2656 ifp->if_timer = 0; 2657 2658 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2659 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2660 printf("%s: sip_stop: no INTR bits set in dirty tx " 2661 "descriptors\n", sc->sc_dev.dv_xname); 2662 } 2663 2664 /* 2665 * sip_read_eeprom: 2666 * 2667 * Read data from the serial EEPROM. 2668 */ 2669 static void 2670 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2671 u_int16_t *data) 2672 { 2673 bus_space_tag_t st = sc->sc_st; 2674 bus_space_handle_t sh = sc->sc_sh; 2675 u_int16_t reg; 2676 int i, x; 2677 2678 for (i = 0; i < wordcnt; i++) { 2679 /* Send CHIP SELECT. */ 2680 reg = EROMAR_EECS; 2681 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2682 2683 /* Shift in the READ opcode. */ 2684 for (x = 3; x > 0; x--) { 2685 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2686 reg |= EROMAR_EEDI; 2687 else 2688 reg &= ~EROMAR_EEDI; 2689 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2690 bus_space_write_4(st, sh, SIP_EROMAR, 2691 reg | EROMAR_EESK); 2692 delay(4); 2693 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2694 delay(4); 2695 } 2696 2697 /* Shift in address. */ 2698 for (x = 6; x > 0; x--) { 2699 if ((word + i) & (1 << (x - 1))) 2700 reg |= EROMAR_EEDI; 2701 else 2702 reg &= ~EROMAR_EEDI; 2703 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2704 bus_space_write_4(st, sh, SIP_EROMAR, 2705 reg | EROMAR_EESK); 2706 delay(4); 2707 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2708 delay(4); 2709 } 2710 2711 /* Shift out data. */ 2712 reg = EROMAR_EECS; 2713 data[i] = 0; 2714 for (x = 16; x > 0; x--) { 2715 bus_space_write_4(st, sh, SIP_EROMAR, 2716 reg | EROMAR_EESK); 2717 delay(4); 2718 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2719 data[i] |= (1 << (x - 1)); 2720 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2721 delay(4); 2722 } 2723 2724 /* Clear CHIP SELECT. */ 2725 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2726 delay(4); 2727 } 2728 } 2729 2730 /* 2731 * sip_add_rxbuf: 2732 * 2733 * Add a receive buffer to the indicated descriptor. 2734 */ 2735 static int 2736 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2737 { 2738 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2739 struct mbuf *m; 2740 int error; 2741 2742 MGETHDR(m, M_DONTWAIT, MT_DATA); 2743 if (m == NULL) 2744 return (ENOBUFS); 2745 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2746 2747 MCLGET(m, M_DONTWAIT); 2748 if ((m->m_flags & M_EXT) == 0) { 2749 m_freem(m); 2750 return (ENOBUFS); 2751 } 2752 2753 #if defined(DP83820) 2754 m->m_len = SIP_RXBUF_LEN; 2755 #endif /* DP83820 */ 2756 2757 if (rxs->rxs_mbuf != NULL) 2758 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2759 2760 rxs->rxs_mbuf = m; 2761 2762 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2763 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2764 BUS_DMA_READ|BUS_DMA_NOWAIT); 2765 if (error) { 2766 printf("%s: can't load rx DMA map %d, error = %d\n", 2767 sc->sc_dev.dv_xname, idx, error); 2768 panic("sip_add_rxbuf"); /* XXX */ 2769 } 2770 2771 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2772 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2773 2774 SIP_INIT_RXDESC(sc, idx); 2775 2776 return (0); 2777 } 2778 2779 #if !defined(DP83820) 2780 /* 2781 * sip_sis900_set_filter: 2782 * 2783 * Set up the receive filter. 2784 */ 2785 static void 2786 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2787 { 2788 bus_space_tag_t st = sc->sc_st; 2789 bus_space_handle_t sh = sc->sc_sh; 2790 struct ethercom *ec = &sc->sc_ethercom; 2791 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2792 struct ether_multi *enm; 2793 u_int8_t *cp; 2794 struct ether_multistep step; 2795 u_int32_t crc, mchash[16]; 2796 2797 /* 2798 * Initialize the prototype RFCR. 2799 */ 2800 sc->sc_rfcr = RFCR_RFEN; 2801 if (ifp->if_flags & IFF_BROADCAST) 2802 sc->sc_rfcr |= RFCR_AAB; 2803 if (ifp->if_flags & IFF_PROMISC) { 2804 sc->sc_rfcr |= RFCR_AAP; 2805 goto allmulti; 2806 } 2807 2808 /* 2809 * Set up the multicast address filter by passing all multicast 2810 * addresses through a CRC generator, and then using the high-order 2811 * 6 bits as an index into the 128 bit multicast hash table (only 2812 * the lower 16 bits of each 32 bit multicast hash register are 2813 * valid). The high order bits select the register, while the 2814 * rest of the bits select the bit within the register. 2815 */ 2816 2817 memset(mchash, 0, sizeof(mchash)); 2818 2819 /* 2820 * SiS900 (at least SiS963) requires us to register the address of 2821 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2822 */ 2823 crc = 0x0ed423f9; 2824 2825 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2826 SIP_SIS900_REV(sc, SIS_REV_960) || 2827 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2828 /* Just want the 8 most significant bits. */ 2829 crc >>= 24; 2830 } else { 2831 /* Just want the 7 most significant bits. */ 2832 crc >>= 25; 2833 } 2834 2835 /* Set the corresponding bit in the hash table. */ 2836 mchash[crc >> 4] |= 1 << (crc & 0xf); 2837 2838 ETHER_FIRST_MULTI(step, ec, enm); 2839 while (enm != NULL) { 2840 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2841 /* 2842 * We must listen to a range of multicast addresses. 2843 * For now, just accept all multicasts, rather than 2844 * trying to set only those filter bits needed to match 2845 * the range. (At this time, the only use of address 2846 * ranges is for IP multicast routing, for which the 2847 * range is big enough to require all bits set.) 2848 */ 2849 goto allmulti; 2850 } 2851 2852 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2853 2854 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2855 SIP_SIS900_REV(sc, SIS_REV_960) || 2856 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2857 /* Just want the 8 most significant bits. */ 2858 crc >>= 24; 2859 } else { 2860 /* Just want the 7 most significant bits. */ 2861 crc >>= 25; 2862 } 2863 2864 /* Set the corresponding bit in the hash table. */ 2865 mchash[crc >> 4] |= 1 << (crc & 0xf); 2866 2867 ETHER_NEXT_MULTI(step, enm); 2868 } 2869 2870 ifp->if_flags &= ~IFF_ALLMULTI; 2871 goto setit; 2872 2873 allmulti: 2874 ifp->if_flags |= IFF_ALLMULTI; 2875 sc->sc_rfcr |= RFCR_AAM; 2876 2877 setit: 2878 #define FILTER_EMIT(addr, data) \ 2879 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2880 delay(1); \ 2881 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2882 delay(1) 2883 2884 /* 2885 * Disable receive filter, and program the node address. 2886 */ 2887 cp = LLADDR(ifp->if_sadl); 2888 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2889 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2890 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2891 2892 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2893 /* 2894 * Program the multicast hash table. 2895 */ 2896 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2897 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2898 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2899 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2900 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2901 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2902 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2903 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2904 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2905 SIP_SIS900_REV(sc, SIS_REV_960) || 2906 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2907 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2908 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2909 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2910 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2911 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2912 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2913 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2914 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2915 } 2916 } 2917 #undef FILTER_EMIT 2918 2919 /* 2920 * Re-enable the receiver filter. 2921 */ 2922 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2923 } 2924 #endif /* ! DP83820 */ 2925 2926 /* 2927 * sip_dp83815_set_filter: 2928 * 2929 * Set up the receive filter. 2930 */ 2931 static void 2932 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2933 { 2934 bus_space_tag_t st = sc->sc_st; 2935 bus_space_handle_t sh = sc->sc_sh; 2936 struct ethercom *ec = &sc->sc_ethercom; 2937 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2938 struct ether_multi *enm; 2939 u_int8_t *cp; 2940 struct ether_multistep step; 2941 u_int32_t crc, hash, slot, bit; 2942 #ifdef DP83820 2943 #define MCHASH_NWORDS 128 2944 #else 2945 #define MCHASH_NWORDS 32 2946 #endif /* DP83820 */ 2947 u_int16_t mchash[MCHASH_NWORDS]; 2948 int i; 2949 2950 /* 2951 * Initialize the prototype RFCR. 2952 * Enable the receive filter, and accept on 2953 * Perfect (destination address) Match 2954 * If IFF_BROADCAST, also accept all broadcast packets. 2955 * If IFF_PROMISC, accept all unicast packets (and later, set 2956 * IFF_ALLMULTI and accept all multicast, too). 2957 */ 2958 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2959 if (ifp->if_flags & IFF_BROADCAST) 2960 sc->sc_rfcr |= RFCR_AAB; 2961 if (ifp->if_flags & IFF_PROMISC) { 2962 sc->sc_rfcr |= RFCR_AAP; 2963 goto allmulti; 2964 } 2965 2966 #ifdef DP83820 2967 /* 2968 * Set up the DP83820 multicast address filter by passing all multicast 2969 * addresses through a CRC generator, and then using the high-order 2970 * 11 bits as an index into the 2048 bit multicast hash table. The 2971 * high-order 7 bits select the slot, while the low-order 4 bits 2972 * select the bit within the slot. Note that only the low 16-bits 2973 * of each filter word are used, and there are 128 filter words. 2974 */ 2975 #else 2976 /* 2977 * Set up the DP83815 multicast address filter by passing all multicast 2978 * addresses through a CRC generator, and then using the high-order 2979 * 9 bits as an index into the 512 bit multicast hash table. The 2980 * high-order 5 bits select the slot, while the low-order 4 bits 2981 * select the bit within the slot. Note that only the low 16-bits 2982 * of each filter word are used, and there are 32 filter words. 2983 */ 2984 #endif /* DP83820 */ 2985 2986 memset(mchash, 0, sizeof(mchash)); 2987 2988 ifp->if_flags &= ~IFF_ALLMULTI; 2989 ETHER_FIRST_MULTI(step, ec, enm); 2990 if (enm == NULL) 2991 goto setit; 2992 while (enm != NULL) { 2993 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2994 /* 2995 * We must listen to a range of multicast addresses. 2996 * For now, just accept all multicasts, rather than 2997 * trying to set only those filter bits needed to match 2998 * the range. (At this time, the only use of address 2999 * ranges is for IP multicast routing, for which the 3000 * range is big enough to require all bits set.) 3001 */ 3002 goto allmulti; 3003 } 3004 3005 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3006 3007 #ifdef DP83820 3008 /* Just want the 11 most significant bits. */ 3009 hash = crc >> 21; 3010 #else 3011 /* Just want the 9 most significant bits. */ 3012 hash = crc >> 23; 3013 #endif /* DP83820 */ 3014 3015 slot = hash >> 4; 3016 bit = hash & 0xf; 3017 3018 /* Set the corresponding bit in the hash table. */ 3019 mchash[slot] |= 1 << bit; 3020 3021 ETHER_NEXT_MULTI(step, enm); 3022 } 3023 sc->sc_rfcr |= RFCR_MHEN; 3024 goto setit; 3025 3026 allmulti: 3027 ifp->if_flags |= IFF_ALLMULTI; 3028 sc->sc_rfcr |= RFCR_AAM; 3029 3030 setit: 3031 #define FILTER_EMIT(addr, data) \ 3032 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3033 delay(1); \ 3034 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3035 delay(1) 3036 3037 /* 3038 * Disable receive filter, and program the node address. 3039 */ 3040 cp = LLADDR(ifp->if_sadl); 3041 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3042 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3043 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3044 3045 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3046 /* 3047 * Program the multicast hash table. 3048 */ 3049 for (i = 0; i < MCHASH_NWORDS; i++) { 3050 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3051 mchash[i]); 3052 } 3053 } 3054 #undef FILTER_EMIT 3055 #undef MCHASH_NWORDS 3056 3057 /* 3058 * Re-enable the receiver filter. 3059 */ 3060 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3061 } 3062 3063 #if defined(DP83820) 3064 /* 3065 * sip_dp83820_mii_readreg: [mii interface function] 3066 * 3067 * Read a PHY register on the MII of the DP83820. 3068 */ 3069 static int 3070 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3071 { 3072 struct sip_softc *sc = (void *) self; 3073 3074 if (sc->sc_cfg & CFG_TBI_EN) { 3075 bus_addr_t tbireg; 3076 int rv; 3077 3078 if (phy != 0) 3079 return (0); 3080 3081 switch (reg) { 3082 case MII_BMCR: tbireg = SIP_TBICR; break; 3083 case MII_BMSR: tbireg = SIP_TBISR; break; 3084 case MII_ANAR: tbireg = SIP_TANAR; break; 3085 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3086 case MII_ANER: tbireg = SIP_TANER; break; 3087 case MII_EXTSR: 3088 /* 3089 * Don't even bother reading the TESR register. 3090 * The manual documents that the device has 3091 * 1000baseX full/half capability, but the 3092 * register itself seems read back 0 on some 3093 * boards. Just hard-code the result. 3094 */ 3095 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3096 3097 default: 3098 return (0); 3099 } 3100 3101 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3102 if (tbireg == SIP_TBISR) { 3103 /* LINK and ACOMP are switched! */ 3104 int val = rv; 3105 3106 rv = 0; 3107 if (val & TBISR_MR_LINK_STATUS) 3108 rv |= BMSR_LINK; 3109 if (val & TBISR_MR_AN_COMPLETE) 3110 rv |= BMSR_ACOMP; 3111 3112 /* 3113 * The manual claims this register reads back 0 3114 * on hard and soft reset. But we want to let 3115 * the gentbi driver know that we support auto- 3116 * negotiation, so hard-code this bit in the 3117 * result. 3118 */ 3119 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3120 } 3121 3122 return (rv); 3123 } 3124 3125 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3126 phy, reg)); 3127 } 3128 3129 /* 3130 * sip_dp83820_mii_writereg: [mii interface function] 3131 * 3132 * Write a PHY register on the MII of the DP83820. 3133 */ 3134 static void 3135 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3136 { 3137 struct sip_softc *sc = (void *) self; 3138 3139 if (sc->sc_cfg & CFG_TBI_EN) { 3140 bus_addr_t tbireg; 3141 3142 if (phy != 0) 3143 return; 3144 3145 switch (reg) { 3146 case MII_BMCR: tbireg = SIP_TBICR; break; 3147 case MII_ANAR: tbireg = SIP_TANAR; break; 3148 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3149 default: 3150 return; 3151 } 3152 3153 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3154 return; 3155 } 3156 3157 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3158 phy, reg, val); 3159 } 3160 3161 /* 3162 * sip_dp83820_mii_statchg: [mii interface function] 3163 * 3164 * Callback from MII layer when media changes. 3165 */ 3166 static void 3167 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3168 { 3169 struct sip_softc *sc = (struct sip_softc *) self; 3170 struct mii_data *mii = &sc->sc_mii; 3171 u_int32_t cfg, pcr; 3172 3173 /* 3174 * Get flow control negotiation result. 3175 */ 3176 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3177 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3178 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3179 mii->mii_media_active &= ~IFM_ETH_FMASK; 3180 } 3181 3182 /* 3183 * Update TXCFG for full-duplex operation. 3184 */ 3185 if ((mii->mii_media_active & IFM_FDX) != 0) 3186 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3187 else 3188 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3189 3190 /* 3191 * Update RXCFG for full-duplex or loopback. 3192 */ 3193 if ((mii->mii_media_active & IFM_FDX) != 0 || 3194 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3195 sc->sc_rxcfg |= RXCFG_ATX; 3196 else 3197 sc->sc_rxcfg &= ~RXCFG_ATX; 3198 3199 /* 3200 * Update CFG for MII/GMII. 3201 */ 3202 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3203 cfg = sc->sc_cfg | CFG_MODE_1000; 3204 else 3205 cfg = sc->sc_cfg; 3206 3207 /* 3208 * 802.3x flow control. 3209 */ 3210 pcr = 0; 3211 if (sc->sc_flowflags & IFM_FLOW) { 3212 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3213 pcr |= sc->sc_rx_flow_thresh; 3214 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3215 pcr |= PCR_PSEN | PCR_PS_MCAST; 3216 } 3217 3218 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3219 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3220 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3221 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3222 } 3223 #endif /* ! DP83820 */ 3224 3225 /* 3226 * sip_mii_bitbang_read: [mii bit-bang interface function] 3227 * 3228 * Read the MII serial port for the MII bit-bang module. 3229 */ 3230 static u_int32_t 3231 SIP_DECL(mii_bitbang_read)(struct device *self) 3232 { 3233 struct sip_softc *sc = (void *) self; 3234 3235 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3236 } 3237 3238 /* 3239 * sip_mii_bitbang_write: [mii big-bang interface function] 3240 * 3241 * Write the MII serial port for the MII bit-bang module. 3242 */ 3243 static void 3244 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3245 { 3246 struct sip_softc *sc = (void *) self; 3247 3248 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3249 } 3250 3251 #ifndef DP83820 3252 /* 3253 * sip_sis900_mii_readreg: [mii interface function] 3254 * 3255 * Read a PHY register on the MII. 3256 */ 3257 static int 3258 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3259 { 3260 struct sip_softc *sc = (struct sip_softc *) self; 3261 u_int32_t enphy; 3262 3263 /* 3264 * The PHY of recent SiS chipsets is accessed through bitbang 3265 * operations. 3266 */ 3267 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3268 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3269 phy, reg)); 3270 3271 #ifndef SIS900_MII_RESTRICT 3272 /* 3273 * The SiS 900 has only an internal PHY on the MII. Only allow 3274 * MII address 0. 3275 */ 3276 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3277 return (0); 3278 #endif 3279 3280 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3281 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3282 ENPHY_RWCMD | ENPHY_ACCESS); 3283 do { 3284 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3285 } while (enphy & ENPHY_ACCESS); 3286 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3287 } 3288 3289 /* 3290 * sip_sis900_mii_writereg: [mii interface function] 3291 * 3292 * Write a PHY register on the MII. 3293 */ 3294 static void 3295 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3296 { 3297 struct sip_softc *sc = (struct sip_softc *) self; 3298 u_int32_t enphy; 3299 3300 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3301 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3302 phy, reg, val); 3303 return; 3304 } 3305 3306 #ifndef SIS900_MII_RESTRICT 3307 /* 3308 * The SiS 900 has only an internal PHY on the MII. Only allow 3309 * MII address 0. 3310 */ 3311 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3312 return; 3313 #endif 3314 3315 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3316 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3317 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3318 do { 3319 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3320 } while (enphy & ENPHY_ACCESS); 3321 } 3322 3323 /* 3324 * sip_sis900_mii_statchg: [mii interface function] 3325 * 3326 * Callback from MII layer when media changes. 3327 */ 3328 static void 3329 SIP_DECL(sis900_mii_statchg)(struct device *self) 3330 { 3331 struct sip_softc *sc = (struct sip_softc *) self; 3332 struct mii_data *mii = &sc->sc_mii; 3333 u_int32_t flowctl; 3334 3335 /* 3336 * Get flow control negotiation result. 3337 */ 3338 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3339 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3340 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3341 mii->mii_media_active &= ~IFM_ETH_FMASK; 3342 } 3343 3344 /* 3345 * Update TXCFG for full-duplex operation. 3346 */ 3347 if ((mii->mii_media_active & IFM_FDX) != 0) 3348 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3349 else 3350 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3351 3352 /* 3353 * Update RXCFG for full-duplex or loopback. 3354 */ 3355 if ((mii->mii_media_active & IFM_FDX) != 0 || 3356 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3357 sc->sc_rxcfg |= RXCFG_ATX; 3358 else 3359 sc->sc_rxcfg &= ~RXCFG_ATX; 3360 3361 /* 3362 * Update IMR for use of 802.3x flow control. 3363 */ 3364 if (sc->sc_flowflags & IFM_FLOW) { 3365 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3366 flowctl = FLOWCTL_FLOWEN; 3367 } else { 3368 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3369 flowctl = 0; 3370 } 3371 3372 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3373 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3374 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3375 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3376 } 3377 3378 /* 3379 * sip_dp83815_mii_readreg: [mii interface function] 3380 * 3381 * Read a PHY register on the MII. 3382 */ 3383 static int 3384 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3385 { 3386 struct sip_softc *sc = (struct sip_softc *) self; 3387 u_int32_t val; 3388 3389 /* 3390 * The DP83815 only has an internal PHY. Only allow 3391 * MII address 0. 3392 */ 3393 if (phy != 0) 3394 return (0); 3395 3396 /* 3397 * Apparently, after a reset, the DP83815 can take a while 3398 * to respond. During this recovery period, the BMSR returns 3399 * a value of 0. Catch this -- it's not supposed to happen 3400 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3401 * PHY to come back to life. 3402 * 3403 * This works out because the BMSR is the first register 3404 * read during the PHY probe process. 3405 */ 3406 do { 3407 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3408 } while (reg == MII_BMSR && val == 0); 3409 3410 return (val & 0xffff); 3411 } 3412 3413 /* 3414 * sip_dp83815_mii_writereg: [mii interface function] 3415 * 3416 * Write a PHY register to the MII. 3417 */ 3418 static void 3419 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3420 { 3421 struct sip_softc *sc = (struct sip_softc *) self; 3422 3423 /* 3424 * The DP83815 only has an internal PHY. Only allow 3425 * MII address 0. 3426 */ 3427 if (phy != 0) 3428 return; 3429 3430 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3431 } 3432 3433 /* 3434 * sip_dp83815_mii_statchg: [mii interface function] 3435 * 3436 * Callback from MII layer when media changes. 3437 */ 3438 static void 3439 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3440 { 3441 struct sip_softc *sc = (struct sip_softc *) self; 3442 3443 /* 3444 * Update TXCFG for full-duplex operation. 3445 */ 3446 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3447 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3448 else 3449 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3450 3451 /* 3452 * Update RXCFG for full-duplex or loopback. 3453 */ 3454 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3455 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3456 sc->sc_rxcfg |= RXCFG_ATX; 3457 else 3458 sc->sc_rxcfg &= ~RXCFG_ATX; 3459 3460 /* 3461 * XXX 802.3x flow control. 3462 */ 3463 3464 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3466 3467 /* 3468 * Some DP83815s experience problems when used with short 3469 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3470 * sequence adjusts the DSP's signal attenuation to fix the 3471 * problem. 3472 */ 3473 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3474 uint32_t reg; 3475 3476 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3477 3478 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3479 reg &= 0x0fff; 3480 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3481 delay(100); 3482 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3483 reg &= 0x00ff; 3484 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3485 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3486 0x00e8); 3487 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3488 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3489 reg | 0x20); 3490 } 3491 3492 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3493 } 3494 } 3495 #endif /* DP83820 */ 3496 3497 #if defined(DP83820) 3498 static void 3499 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3500 const struct pci_attach_args *pa, u_int8_t *enaddr) 3501 { 3502 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3503 u_int8_t cksum, *e, match; 3504 int i; 3505 3506 /* 3507 * EEPROM data format for the DP83820 can be found in 3508 * the DP83820 manual, section 4.2.4. 3509 */ 3510 3511 SIP_DECL(read_eeprom)(sc, 0, 3512 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3513 3514 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3515 match = ~(match - 1); 3516 3517 cksum = 0x55; 3518 e = (u_int8_t *) eeprom_data; 3519 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3520 cksum += *e++; 3521 3522 if (cksum != match) 3523 printf("%s: Checksum (%x) mismatch (%x)", 3524 sc->sc_dev.dv_xname, cksum, match); 3525 3526 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3527 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3528 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3529 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3530 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3531 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3532 } 3533 #else /* ! DP83820 */ 3534 static void 3535 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3536 { 3537 int i; 3538 3539 /* 3540 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3541 * a reason, but I don't know it. 3542 */ 3543 for (i = 0; i < 10; i++) 3544 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3545 } 3546 3547 static void 3548 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3549 const struct pci_attach_args *pa, u_int8_t *enaddr) 3550 { 3551 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3552 3553 switch (sc->sc_rev) { 3554 case SIS_REV_630S: 3555 case SIS_REV_630E: 3556 case SIS_REV_630EA1: 3557 case SIS_REV_630ET: 3558 case SIS_REV_635: 3559 /* 3560 * The MAC address for the on-board Ethernet of 3561 * the SiS 630 chipset is in the NVRAM. Kick 3562 * the chip into re-loading it from NVRAM, and 3563 * read the MAC address out of the filter registers. 3564 */ 3565 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3566 3567 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3568 RFCR_RFADDR_NODE0); 3569 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3570 0xffff; 3571 3572 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3573 RFCR_RFADDR_NODE2); 3574 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3575 0xffff; 3576 3577 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3578 RFCR_RFADDR_NODE4); 3579 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3580 0xffff; 3581 break; 3582 3583 case SIS_REV_960: 3584 { 3585 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3586 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3587 3588 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3589 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3590 3591 int waittime, i; 3592 3593 /* Allow to read EEPROM from LAN. It is shared 3594 * between a 1394 controller and the NIC and each 3595 * time we access it, we need to set SIS_EECMD_REQ. 3596 */ 3597 SIS_SET_EROMAR(sc, EROMAR_REQ); 3598 3599 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3600 /* Force EEPROM to idle state. */ 3601 3602 /* 3603 * XXX-cube This is ugly. I'll look for docs about it. 3604 */ 3605 SIS_SET_EROMAR(sc, EROMAR_EECS); 3606 SIP_DECL(sis900_eeprom_delay)(sc); 3607 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3608 SIS_SET_EROMAR(sc, EROMAR_EESK); 3609 SIP_DECL(sis900_eeprom_delay)(sc); 3610 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3611 SIP_DECL(sis900_eeprom_delay)(sc); 3612 } 3613 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3614 SIP_DECL(sis900_eeprom_delay)(sc); 3615 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3616 3617 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3618 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3619 sizeof(myea) / sizeof(myea[0]), myea); 3620 break; 3621 } 3622 DELAY(1); 3623 } 3624 3625 /* 3626 * Set SIS_EECTL_CLK to high, so a other master 3627 * can operate on the i2c bus. 3628 */ 3629 SIS_SET_EROMAR(sc, EROMAR_EESK); 3630 3631 /* Refuse EEPROM access by LAN */ 3632 SIS_SET_EROMAR(sc, EROMAR_DONE); 3633 } break; 3634 3635 default: 3636 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3637 sizeof(myea) / sizeof(myea[0]), myea); 3638 } 3639 3640 enaddr[0] = myea[0] & 0xff; 3641 enaddr[1] = myea[0] >> 8; 3642 enaddr[2] = myea[1] & 0xff; 3643 enaddr[3] = myea[1] >> 8; 3644 enaddr[4] = myea[2] & 0xff; 3645 enaddr[5] = myea[2] >> 8; 3646 } 3647 3648 /* Table and macro to bit-reverse an octet. */ 3649 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3650 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3651 3652 static void 3653 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3654 const struct pci_attach_args *pa, u_int8_t *enaddr) 3655 { 3656 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3657 u_int8_t cksum, *e, match; 3658 int i; 3659 3660 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3661 sizeof(eeprom_data[0]), eeprom_data); 3662 3663 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3664 match = ~(match - 1); 3665 3666 cksum = 0x55; 3667 e = (u_int8_t *) eeprom_data; 3668 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3669 cksum += *e++; 3670 } 3671 if (cksum != match) { 3672 printf("%s: Checksum (%x) mismatch (%x)", 3673 sc->sc_dev.dv_xname, cksum, match); 3674 } 3675 3676 /* 3677 * Unrolled because it makes slightly more sense this way. 3678 * The DP83815 stores the MAC address in bit 0 of word 6 3679 * through bit 15 of word 8. 3680 */ 3681 ea = &eeprom_data[6]; 3682 enaddr[0] = ((*ea & 0x1) << 7); 3683 ea++; 3684 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3685 enaddr[1] = ((*ea & 0x1FE) >> 1); 3686 enaddr[2] = ((*ea & 0x1) << 7); 3687 ea++; 3688 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3689 enaddr[3] = ((*ea & 0x1FE) >> 1); 3690 enaddr[4] = ((*ea & 0x1) << 7); 3691 ea++; 3692 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3693 enaddr[5] = ((*ea & 0x1FE) >> 1); 3694 3695 /* 3696 * In case that's not weird enough, we also need to reverse 3697 * the bits in each byte. This all actually makes more sense 3698 * if you think about the EEPROM storage as an array of bits 3699 * being shifted into bytes, but that's not how we're looking 3700 * at it here... 3701 */ 3702 for (i = 0; i < 6 ;i++) 3703 enaddr[i] = bbr(enaddr[i]); 3704 } 3705 #endif /* DP83820 */ 3706 3707 /* 3708 * sip_mediastatus: [ifmedia interface function] 3709 * 3710 * Get the current interface media status. 3711 */ 3712 static void 3713 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3714 { 3715 struct sip_softc *sc = ifp->if_softc; 3716 3717 mii_pollstat(&sc->sc_mii); 3718 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3719 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3720 sc->sc_flowflags; 3721 } 3722 3723 /* 3724 * sip_mediachange: [ifmedia interface function] 3725 * 3726 * Set hardware to newly-selected media. 3727 */ 3728 static int 3729 SIP_DECL(mediachange)(struct ifnet *ifp) 3730 { 3731 struct sip_softc *sc = ifp->if_softc; 3732 3733 if (ifp->if_flags & IFF_UP) 3734 mii_mediachg(&sc->sc_mii); 3735 return (0); 3736 } 3737
Indexes created Tue Sep 30 11:09:46 GMT 2025