if_sip.c revision 1.112
1 /* $NetBSD: if_sip.c,v 1.112 2007/03/04 15:05:24 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.112 2007/03/04 15:05:24 yamt Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <machine/bus.h> 116 #include <machine/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 void *sc_sdhook; /* shutdown hook */ 233 234 const struct sip_product *sc_model; /* which model are we? */ 235 int sc_rev; /* chip revision */ 236 237 void *sc_ih; /* interrupt cookie */ 238 239 struct mii_data sc_mii; /* MII/media information */ 240 241 struct callout sc_tick_ch; /* tick callout */ 242 243 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 244 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 245 246 /* 247 * Software state for transmit and receive descriptors. 248 */ 249 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 250 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 251 252 /* 253 * Control data structures. 254 */ 255 struct sip_control_data *sc_control_data; 256 #define sc_txdescs sc_control_data->scd_txdescs 257 #define sc_rxdescs sc_control_data->scd_rxdescs 258 259 #ifdef SIP_EVENT_COUNTERS 260 /* 261 * Event counters. 262 */ 263 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 264 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 265 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 266 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 267 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 268 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 269 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 270 struct evcnt sc_ev_rxpause; /* PAUSE received */ 271 #ifdef DP83820 272 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 273 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 274 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 275 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 276 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 277 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 278 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 279 #endif /* DP83820 */ 280 #endif /* SIP_EVENT_COUNTERS */ 281 282 u_int32_t sc_txcfg; /* prototype TXCFG register */ 283 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 284 u_int32_t sc_imr; /* prototype IMR register */ 285 u_int32_t sc_rfcr; /* prototype RFCR register */ 286 287 u_int32_t sc_cfg; /* prototype CFG register */ 288 289 #ifdef DP83820 290 u_int32_t sc_gpior; /* prototype GPIOR register */ 291 #endif /* DP83820 */ 292 293 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 294 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 295 296 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 297 298 int sc_flowflags; /* 802.3x flow control flags */ 299 #ifdef DP83820 300 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 301 #else 302 int sc_paused; /* paused indication */ 303 #endif 304 305 int sc_txfree; /* number of free Tx descriptors */ 306 int sc_txnext; /* next ready Tx descriptor */ 307 int sc_txwin; /* Tx descriptors since last intr */ 308 309 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 310 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 311 312 /* values of interface state at last init */ 313 struct { 314 /* if_capenable */ 315 uint64_t if_capenable; 316 /* ec_capenable */ 317 int ec_capenable; 318 /* VLAN_ATTACHED */ 319 int is_vlan; 320 } sc_prev; 321 322 short sc_if_flags; 323 324 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 325 #if defined(DP83820) 326 int sc_rxdiscard; 327 int sc_rxlen; 328 struct mbuf *sc_rxhead; 329 struct mbuf *sc_rxtail; 330 struct mbuf **sc_rxtailp; 331 #endif /* DP83820 */ 332 333 #if NRND > 0 334 rndsource_element_t rnd_source; /* random source */ 335 #endif 336 }; 337 338 #ifdef DP83820 339 #define SIP_RXCHAIN_RESET(sc) \ 340 do { \ 341 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 342 *(sc)->sc_rxtailp = NULL; \ 343 (sc)->sc_rxlen = 0; \ 344 } while (/*CONSTCOND*/0) 345 346 #define SIP_RXCHAIN_LINK(sc, m) \ 347 do { \ 348 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 349 (sc)->sc_rxtailp = &(m)->m_next; \ 350 } while (/*CONSTCOND*/0) 351 #endif /* DP83820 */ 352 353 #ifdef SIP_EVENT_COUNTERS 354 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 355 #else 356 #define SIP_EVCNT_INCR(ev) /* nothing */ 357 #endif 358 359 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 360 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 361 362 #define SIP_CDTXSYNC(sc, x, n, ops) \ 363 do { \ 364 int __x, __n; \ 365 \ 366 __x = (x); \ 367 __n = (n); \ 368 \ 369 /* If it will wrap around, sync to the end of the ring. */ \ 370 if ((__x + __n) > SIP_NTXDESC) { \ 371 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 372 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 373 (SIP_NTXDESC - __x), (ops)); \ 374 __n -= (SIP_NTXDESC - __x); \ 375 __x = 0; \ 376 } \ 377 \ 378 /* Now sync whatever is left. */ \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 381 } while (0) 382 383 #define SIP_CDRXSYNC(sc, x, ops) \ 384 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 385 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 386 387 #ifdef DP83820 388 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 389 #define SIP_RXBUF_LEN (MCLBYTES - 8) 390 #else 391 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 392 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 393 #endif 394 #define SIP_INIT_RXDESC(sc, x) \ 395 do { \ 396 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 397 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 398 \ 399 __sipd->sipd_link = \ 400 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 401 __sipd->sipd_bufptr = \ 402 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 403 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 404 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 405 SIP_INIT_RXDESC_EXTSTS \ 406 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 407 } while (0) 408 409 #define SIP_CHIP_VERS(sc, v, p, r) \ 410 ((sc)->sc_model->sip_vendor == (v) && \ 411 (sc)->sc_model->sip_product == (p) && \ 412 (sc)->sc_rev == (r)) 413 414 #define SIP_CHIP_MODEL(sc, v, p) \ 415 ((sc)->sc_model->sip_vendor == (v) && \ 416 (sc)->sc_model->sip_product == (p)) 417 418 #if !defined(DP83820) 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 #endif 422 423 #define SIP_TIMEOUT 1000 424 425 static void SIP_DECL(start)(struct ifnet *); 426 static void SIP_DECL(watchdog)(struct ifnet *); 427 static int SIP_DECL(ioctl)(struct ifnet *, u_long, void *); 428 static int SIP_DECL(init)(struct ifnet *); 429 static void SIP_DECL(stop)(struct ifnet *, int); 430 431 static void SIP_DECL(shutdown)(void *); 432 433 static void SIP_DECL(reset)(struct sip_softc *); 434 static void SIP_DECL(rxdrain)(struct sip_softc *); 435 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 436 static void SIP_DECL(read_eeprom)(struct sip_softc *, int, int, 437 u_int16_t *); 438 static void SIP_DECL(tick)(void *); 439 440 #if !defined(DP83820) 441 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 442 #endif /* ! DP83820 */ 443 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 444 445 #if defined(DP83820) 446 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 447 const struct pci_attach_args *, u_int8_t *); 448 #else 449 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 450 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 451 const struct pci_attach_args *, u_int8_t *); 452 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 453 const struct pci_attach_args *, u_int8_t *); 454 #endif /* DP83820 */ 455 456 static int SIP_DECL(intr)(void *); 457 static void SIP_DECL(txintr)(struct sip_softc *); 458 static void SIP_DECL(rxintr)(struct sip_softc *); 459 460 #if defined(DP83820) 461 static int SIP_DECL(dp83820_mii_readreg)(struct device *, int, int); 462 static void SIP_DECL(dp83820_mii_writereg)(struct device *, int, int, int); 463 static void SIP_DECL(dp83820_mii_statchg)(struct device *); 464 #else 465 static int SIP_DECL(sis900_mii_readreg)(struct device *, int, int); 466 static void SIP_DECL(sis900_mii_writereg)(struct device *, int, int, int); 467 static void SIP_DECL(sis900_mii_statchg)(struct device *); 468 469 static int SIP_DECL(dp83815_mii_readreg)(struct device *, int, int); 470 static void SIP_DECL(dp83815_mii_writereg)(struct device *, int, int, int); 471 static void SIP_DECL(dp83815_mii_statchg)(struct device *); 472 #endif /* DP83820 */ 473 474 static int SIP_DECL(mediachange)(struct ifnet *); 475 static void SIP_DECL(mediastatus)(struct ifnet *, struct ifmediareq *); 476 477 static int SIP_DECL(match)(struct device *, struct cfdata *, void *); 478 static void SIP_DECL(attach)(struct device *, struct device *, void *); 479 480 int SIP_DECL(copy_small) = 0; 481 482 #ifdef DP83820 483 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 484 gsip_match, gsip_attach, NULL, NULL); 485 #else 486 CFATTACH_DECL(sip, sizeof(struct sip_softc), 487 sip_match, sip_attach, NULL, NULL); 488 #endif 489 490 /* 491 * Descriptions of the variants of the SiS900. 492 */ 493 struct sip_variant { 494 int (*sipv_mii_readreg)(struct device *, int, int); 495 void (*sipv_mii_writereg)(struct device *, int, int, int); 496 void (*sipv_mii_statchg)(struct device *); 497 void (*sipv_set_filter)(struct sip_softc *); 498 void (*sipv_read_macaddr)(struct sip_softc *, 499 const struct pci_attach_args *, u_int8_t *); 500 }; 501 502 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 503 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 504 505 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 506 SIP_DECL(mii_bitbang_read), 507 SIP_DECL(mii_bitbang_write), 508 { 509 EROMAR_MDIO, /* MII_BIT_MDO */ 510 EROMAR_MDIO, /* MII_BIT_MDI */ 511 EROMAR_MDC, /* MII_BIT_MDC */ 512 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 513 0, /* MII_BIT_DIR_PHY_HOST */ 514 } 515 }; 516 517 #if defined(DP83820) 518 static const struct sip_variant SIP_DECL(variant_dp83820) = { 519 SIP_DECL(dp83820_mii_readreg), 520 SIP_DECL(dp83820_mii_writereg), 521 SIP_DECL(dp83820_mii_statchg), 522 SIP_DECL(dp83815_set_filter), 523 SIP_DECL(dp83820_read_macaddr), 524 }; 525 #else 526 static const struct sip_variant SIP_DECL(variant_sis900) = { 527 SIP_DECL(sis900_mii_readreg), 528 SIP_DECL(sis900_mii_writereg), 529 SIP_DECL(sis900_mii_statchg), 530 SIP_DECL(sis900_set_filter), 531 SIP_DECL(sis900_read_macaddr), 532 }; 533 534 static const struct sip_variant SIP_DECL(variant_dp83815) = { 535 SIP_DECL(dp83815_mii_readreg), 536 SIP_DECL(dp83815_mii_writereg), 537 SIP_DECL(dp83815_mii_statchg), 538 SIP_DECL(dp83815_set_filter), 539 SIP_DECL(dp83815_read_macaddr), 540 }; 541 #endif /* DP83820 */ 542 543 /* 544 * Devices supported by this driver. 545 */ 546 static const struct sip_product { 547 pci_vendor_id_t sip_vendor; 548 pci_product_id_t sip_product; 549 const char *sip_name; 550 const struct sip_variant *sip_variant; 551 } SIP_DECL(products)[] = { 552 #if defined(DP83820) 553 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 554 "NatSemi DP83820 Gigabit Ethernet", 555 &SIP_DECL(variant_dp83820) }, 556 #else 557 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 558 "SiS 900 10/100 Ethernet", 559 &SIP_DECL(variant_sis900) }, 560 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 561 "SiS 7016 10/100 Ethernet", 562 &SIP_DECL(variant_sis900) }, 563 564 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 565 "NatSemi DP83815 10/100 Ethernet", 566 &SIP_DECL(variant_dp83815) }, 567 #endif /* DP83820 */ 568 569 { 0, 0, 570 NULL, 571 NULL }, 572 }; 573 574 static const struct sip_product * 575 SIP_DECL(lookup)(const struct pci_attach_args *pa) 576 { 577 const struct sip_product *sip; 578 579 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 580 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 581 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 582 return (sip); 583 } 584 return (NULL); 585 } 586 587 #ifdef DP83820 588 /* 589 * I really hate stupid hardware vendors. There's a bit in the EEPROM 590 * which indicates if the card can do 64-bit data transfers. Unfortunately, 591 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 592 * which means we try to use 64-bit data transfers on those cards if we 593 * happen to be plugged into a 32-bit slot. 594 * 595 * What we do is use this table of cards known to be 64-bit cards. If 596 * you have a 64-bit card who's subsystem ID is not listed in this table, 597 * send the output of "pcictl dump ..." of the device to me so that your 598 * card will use the 64-bit data path when plugged into a 64-bit slot. 599 * 600 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 601 * June 30, 2002 602 */ 603 static int 604 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 605 { 606 static const struct { 607 pci_vendor_id_t c64_vendor; 608 pci_product_id_t c64_product; 609 } card64[] = { 610 /* Asante GigaNIX */ 611 { 0x128a, 0x0002 }, 612 613 /* Accton EN1407-T, Planex GN-1000TE */ 614 { 0x1113, 0x1407 }, 615 616 /* Netgear GA-621 */ 617 { 0x1385, 0x621a }, 618 619 /* SMC EZ Card */ 620 { 0x10b8, 0x9462 }, 621 622 { 0, 0} 623 }; 624 pcireg_t subsys; 625 int i; 626 627 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 628 629 for (i = 0; card64[i].c64_vendor != 0; i++) { 630 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 631 PCI_PRODUCT(subsys) == card64[i].c64_product) 632 return (1); 633 } 634 635 return (0); 636 } 637 #endif /* DP83820 */ 638 639 static int 640 SIP_DECL(match)(struct device *parent, struct cfdata *cf, 641 void *aux) 642 { 643 struct pci_attach_args *pa = aux; 644 645 if (SIP_DECL(lookup)(pa) != NULL) 646 return (1); 647 648 return (0); 649 } 650 651 static void 652 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 653 { 654 struct sip_softc *sc = (struct sip_softc *) self; 655 struct pci_attach_args *pa = aux; 656 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 657 pci_chipset_tag_t pc = pa->pa_pc; 658 pci_intr_handle_t ih; 659 const char *intrstr = NULL; 660 bus_space_tag_t iot, memt; 661 bus_space_handle_t ioh, memh; 662 bus_dma_segment_t seg; 663 int ioh_valid, memh_valid; 664 int i, rseg, error; 665 const struct sip_product *sip; 666 u_int8_t enaddr[ETHER_ADDR_LEN]; 667 pcireg_t pmreg; 668 #ifdef DP83820 669 pcireg_t memtype; 670 u_int32_t reg; 671 #endif /* DP83820 */ 672 673 callout_init(&sc->sc_tick_ch); 674 675 sip = SIP_DECL(lookup)(pa); 676 if (sip == NULL) { 677 printf("\n"); 678 panic(SIP_STR(attach) ": impossible"); 679 } 680 sc->sc_rev = PCI_REVISION(pa->pa_class); 681 682 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 683 684 sc->sc_model = sip; 685 686 /* 687 * XXX Work-around broken PXE firmware on some boards. 688 * 689 * The DP83815 shares an address decoder with the MEM BAR 690 * and the ROM BAR. Make sure the ROM BAR is disabled, 691 * so that memory mapped access works. 692 */ 693 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 694 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 695 ~PCI_MAPREG_ROM_ENABLE); 696 697 /* 698 * Map the device. 699 */ 700 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 701 PCI_MAPREG_TYPE_IO, 0, 702 &iot, &ioh, NULL, NULL) == 0); 703 #ifdef DP83820 704 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 705 switch (memtype) { 706 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 707 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 708 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 709 memtype, 0, &memt, &memh, NULL, NULL) == 0); 710 break; 711 default: 712 memh_valid = 0; 713 } 714 #else 715 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 716 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 717 &memt, &memh, NULL, NULL) == 0); 718 #endif /* DP83820 */ 719 720 if (memh_valid) { 721 sc->sc_st = memt; 722 sc->sc_sh = memh; 723 } else if (ioh_valid) { 724 sc->sc_st = iot; 725 sc->sc_sh = ioh; 726 } else { 727 printf("%s: unable to map device registers\n", 728 sc->sc_dev.dv_xname); 729 return; 730 } 731 732 sc->sc_dmat = pa->pa_dmat; 733 734 /* 735 * Make sure bus mastering is enabled. Also make sure 736 * Write/Invalidate is enabled if we're allowed to use it. 737 */ 738 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 739 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 740 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 741 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 742 pmreg | PCI_COMMAND_MASTER_ENABLE); 743 744 /* power up chip */ 745 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 746 NULL)) && error != EOPNOTSUPP) { 747 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 748 error); 749 return; 750 } 751 752 /* 753 * Map and establish our interrupt. 754 */ 755 if (pci_intr_map(pa, &ih)) { 756 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 757 return; 758 } 759 intrstr = pci_intr_string(pc, ih); 760 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 761 if (sc->sc_ih == NULL) { 762 printf("%s: unable to establish interrupt", 763 sc->sc_dev.dv_xname); 764 if (intrstr != NULL) 765 printf(" at %s", intrstr); 766 printf("\n"); 767 return; 768 } 769 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 770 771 SIMPLEQ_INIT(&sc->sc_txfreeq); 772 SIMPLEQ_INIT(&sc->sc_txdirtyq); 773 774 /* 775 * Allocate the control data structures, and create and load the 776 * DMA map for it. 777 */ 778 if ((error = bus_dmamem_alloc(sc->sc_dmat, 779 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 780 0)) != 0) { 781 printf("%s: unable to allocate control data, error = %d\n", 782 sc->sc_dev.dv_xname, error); 783 goto fail_0; 784 } 785 786 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 787 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 788 BUS_DMA_COHERENT)) != 0) { 789 printf("%s: unable to map control data, error = %d\n", 790 sc->sc_dev.dv_xname, error); 791 goto fail_1; 792 } 793 794 if ((error = bus_dmamap_create(sc->sc_dmat, 795 sizeof(struct sip_control_data), 1, 796 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 797 printf("%s: unable to create control data DMA map, " 798 "error = %d\n", sc->sc_dev.dv_xname, error); 799 goto fail_2; 800 } 801 802 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 803 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 804 0)) != 0) { 805 printf("%s: unable to load control data DMA map, error = %d\n", 806 sc->sc_dev.dv_xname, error); 807 goto fail_3; 808 } 809 810 /* 811 * Create the transmit buffer DMA maps. 812 */ 813 for (i = 0; i < SIP_TXQUEUELEN; i++) { 814 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 815 SIP_NTXSEGS, MCLBYTES, 0, 0, 816 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 817 printf("%s: unable to create tx DMA map %d, " 818 "error = %d\n", sc->sc_dev.dv_xname, i, error); 819 goto fail_4; 820 } 821 } 822 823 /* 824 * Create the receive buffer DMA maps. 825 */ 826 for (i = 0; i < SIP_NRXDESC; i++) { 827 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 828 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 829 printf("%s: unable to create rx DMA map %d, " 830 "error = %d\n", sc->sc_dev.dv_xname, i, error); 831 goto fail_5; 832 } 833 sc->sc_rxsoft[i].rxs_mbuf = NULL; 834 } 835 836 /* 837 * Reset the chip to a known state. 838 */ 839 SIP_DECL(reset)(sc); 840 841 /* 842 * Read the Ethernet address from the EEPROM. This might 843 * also fetch other stuff from the EEPROM and stash it 844 * in the softc. 845 */ 846 sc->sc_cfg = 0; 847 #if !defined(DP83820) 848 if (SIP_SIS900_REV(sc,SIS_REV_635) || 849 SIP_SIS900_REV(sc,SIS_REV_900B)) 850 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 851 852 if (SIP_SIS900_REV(sc,SIS_REV_635) || 853 SIP_SIS900_REV(sc,SIS_REV_960) || 854 SIP_SIS900_REV(sc,SIS_REV_900B)) 855 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 856 SIP_CFG) & CFG_EDBMASTEN); 857 #endif 858 859 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 860 861 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 862 ether_sprintf(enaddr)); 863 864 /* 865 * Initialize the configuration register: aggressive PCI 866 * bus request algorithm, default backoff, default OW timer, 867 * default parity error detection. 868 * 869 * NOTE: "Big endian mode" is useless on the SiS900 and 870 * friends -- it affects packet data, not descriptors. 871 */ 872 #ifdef DP83820 873 /* 874 * Cause the chip to load configuration data from the EEPROM. 875 */ 876 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 877 for (i = 0; i < 10000; i++) { 878 delay(10); 879 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 880 PTSCR_EELOAD_EN) == 0) 881 break; 882 } 883 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 884 PTSCR_EELOAD_EN) { 885 printf("%s: timeout loading configuration from EEPROM\n", 886 sc->sc_dev.dv_xname); 887 return; 888 } 889 890 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 891 892 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 893 if (reg & CFG_PCI64_DET) { 894 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 895 /* 896 * Check to see if this card is 64-bit. If so, enable 64-bit 897 * data transfers. 898 * 899 * We can't use the DATA64_EN bit in the EEPROM, because 900 * vendors of 32-bit cards fail to clear that bit in many 901 * cases (yet the card still detects that it's in a 64-bit 902 * slot; go figure). 903 */ 904 if (SIP_DECL(check_64bit)(pa)) { 905 sc->sc_cfg |= CFG_DATA64_EN; 906 printf(", using 64-bit data transfers"); 907 } 908 printf("\n"); 909 } 910 911 /* 912 * XXX Need some PCI flags indicating support for 913 * XXX 64-bit addressing. 914 */ 915 #if 0 916 if (reg & CFG_M64ADDR) 917 sc->sc_cfg |= CFG_M64ADDR; 918 if (reg & CFG_T64ADDR) 919 sc->sc_cfg |= CFG_T64ADDR; 920 #endif 921 922 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 923 const char *sep = ""; 924 printf("%s: using ", sc->sc_dev.dv_xname); 925 if (reg & CFG_EXT_125) { 926 sc->sc_cfg |= CFG_EXT_125; 927 printf("%s125MHz clock", sep); 928 sep = ", "; 929 } 930 if (reg & CFG_TBI_EN) { 931 sc->sc_cfg |= CFG_TBI_EN; 932 printf("%sten-bit interface", sep); 933 sep = ", "; 934 } 935 printf("\n"); 936 } 937 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 938 (reg & CFG_MRM_DIS) != 0) 939 sc->sc_cfg |= CFG_MRM_DIS; 940 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 941 (reg & CFG_MWI_DIS) != 0) 942 sc->sc_cfg |= CFG_MWI_DIS; 943 944 /* 945 * Use the extended descriptor format on the DP83820. This 946 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 947 * checksumming. 948 */ 949 sc->sc_cfg |= CFG_EXTSTS_EN; 950 #endif /* DP83820 */ 951 952 /* 953 * Initialize our media structures and probe the MII. 954 */ 955 sc->sc_mii.mii_ifp = ifp; 956 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 957 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 958 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 959 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, SIP_DECL(mediachange), 960 SIP_DECL(mediastatus)); 961 962 /* 963 * XXX We cannot handle flow control on the DP83815. 964 */ 965 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 966 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 967 MII_OFFSET_ANY, 0); 968 else 969 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 970 MII_OFFSET_ANY, MIIF_DOPAUSE); 971 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 972 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 973 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 974 } else 975 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 976 977 ifp = &sc->sc_ethercom.ec_if; 978 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 979 ifp->if_softc = sc; 980 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 981 sc->sc_if_flags = ifp->if_flags; 982 ifp->if_ioctl = SIP_DECL(ioctl); 983 ifp->if_start = SIP_DECL(start); 984 ifp->if_watchdog = SIP_DECL(watchdog); 985 ifp->if_init = SIP_DECL(init); 986 ifp->if_stop = SIP_DECL(stop); 987 IFQ_SET_READY(&ifp->if_snd); 988 989 /* 990 * We can support 802.1Q VLAN-sized frames. 991 */ 992 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 993 994 #ifdef DP83820 995 /* 996 * And the DP83820 can do VLAN tagging in hardware, and 997 * support the jumbo Ethernet MTU. 998 */ 999 sc->sc_ethercom.ec_capabilities |= 1000 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1001 1002 /* 1003 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1004 * in hardware. 1005 */ 1006 ifp->if_capabilities |= 1007 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1008 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1009 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1010 #endif /* DP83820 */ 1011 1012 /* 1013 * Attach the interface. 1014 */ 1015 if_attach(ifp); 1016 ether_ifattach(ifp, enaddr); 1017 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1018 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1019 sc->sc_prev.if_capenable = ifp->if_capenable; 1020 #if NRND > 0 1021 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1022 RND_TYPE_NET, 0); 1023 #endif 1024 1025 /* 1026 * The number of bytes that must be available in 1027 * the Tx FIFO before the bus master can DMA more 1028 * data into the FIFO. 1029 */ 1030 sc->sc_tx_fill_thresh = 64 / 32; 1031 1032 /* 1033 * Start at a drain threshold of 512 bytes. We will 1034 * increase it if a DMA underrun occurs. 1035 * 1036 * XXX The minimum value of this variable should be 1037 * tuned. We may be able to improve performance 1038 * by starting with a lower value. That, however, 1039 * may trash the first few outgoing packets if the 1040 * PCI bus is saturated. 1041 */ 1042 #ifdef DP83820 1043 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1044 #else 1045 sc->sc_tx_drain_thresh = 1504 / 32; 1046 #endif 1047 1048 /* 1049 * Initialize the Rx FIFO drain threshold. 1050 * 1051 * This is in units of 8 bytes. 1052 * 1053 * We should never set this value lower than 2; 14 bytes are 1054 * required to filter the packet. 1055 */ 1056 sc->sc_rx_drain_thresh = 128 / 8; 1057 1058 #ifdef SIP_EVENT_COUNTERS 1059 /* 1060 * Attach event counters. 1061 */ 1062 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1063 NULL, sc->sc_dev.dv_xname, "txsstall"); 1064 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1065 NULL, sc->sc_dev.dv_xname, "txdstall"); 1066 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1067 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1068 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1069 NULL, sc->sc_dev.dv_xname, "txdintr"); 1070 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1071 NULL, sc->sc_dev.dv_xname, "txiintr"); 1072 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1073 NULL, sc->sc_dev.dv_xname, "rxintr"); 1074 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1075 NULL, sc->sc_dev.dv_xname, "hiberr"); 1076 #ifndef DP83820 1077 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1078 NULL, sc->sc_dev.dv_xname, "rxpause"); 1079 #endif /* !DP83820 */ 1080 #ifdef DP83820 1081 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1082 NULL, sc->sc_dev.dv_xname, "rxpause"); 1083 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1084 NULL, sc->sc_dev.dv_xname, "txpause"); 1085 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1086 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1087 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1088 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1089 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1090 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1091 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1092 NULL, sc->sc_dev.dv_xname, "txipsum"); 1093 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1094 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1095 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1096 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1097 #endif /* DP83820 */ 1098 #endif /* SIP_EVENT_COUNTERS */ 1099 1100 /* 1101 * Make sure the interface is shutdown during reboot. 1102 */ 1103 sc->sc_sdhook = shutdownhook_establish(SIP_DECL(shutdown), sc); 1104 if (sc->sc_sdhook == NULL) 1105 printf("%s: WARNING: unable to establish shutdown hook\n", 1106 sc->sc_dev.dv_xname); 1107 return; 1108 1109 /* 1110 * Free any resources we've allocated during the failed attach 1111 * attempt. Do this in reverse order and fall through. 1112 */ 1113 fail_5: 1114 for (i = 0; i < SIP_NRXDESC; i++) { 1115 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1116 bus_dmamap_destroy(sc->sc_dmat, 1117 sc->sc_rxsoft[i].rxs_dmamap); 1118 } 1119 fail_4: 1120 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1121 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1122 bus_dmamap_destroy(sc->sc_dmat, 1123 sc->sc_txsoft[i].txs_dmamap); 1124 } 1125 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1126 fail_3: 1127 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1128 fail_2: 1129 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1130 sizeof(struct sip_control_data)); 1131 fail_1: 1132 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1133 fail_0: 1134 return; 1135 } 1136 1137 /* 1138 * sip_shutdown: 1139 * 1140 * Make sure the interface is stopped at reboot time. 1141 */ 1142 static void 1143 SIP_DECL(shutdown)(void *arg) 1144 { 1145 struct sip_softc *sc = arg; 1146 1147 SIP_DECL(stop)(&sc->sc_ethercom.ec_if, 1); 1148 } 1149 1150 /* 1151 * sip_start: [ifnet interface function] 1152 * 1153 * Start packet transmission on the interface. 1154 */ 1155 static void 1156 SIP_DECL(start)(struct ifnet *ifp) 1157 { 1158 struct sip_softc *sc = ifp->if_softc; 1159 struct mbuf *m0; 1160 #ifndef DP83820 1161 struct mbuf *m; 1162 #endif 1163 struct sip_txsoft *txs; 1164 bus_dmamap_t dmamap; 1165 int error, nexttx, lasttx, seg; 1166 int ofree = sc->sc_txfree; 1167 #if 0 1168 int firsttx = sc->sc_txnext; 1169 #endif 1170 #ifdef DP83820 1171 struct m_tag *mtag; 1172 u_int32_t extsts; 1173 #endif 1174 1175 #ifndef DP83820 1176 /* 1177 * If we've been told to pause, don't transmit any more packets. 1178 */ 1179 if (sc->sc_paused) 1180 ifp->if_flags |= IFF_OACTIVE; 1181 #endif 1182 1183 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1184 return; 1185 1186 /* 1187 * Loop through the send queue, setting up transmit descriptors 1188 * until we drain the queue, or use up all available transmit 1189 * descriptors. 1190 */ 1191 for (;;) { 1192 /* Get a work queue entry. */ 1193 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1194 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1195 break; 1196 } 1197 1198 /* 1199 * Grab a packet off the queue. 1200 */ 1201 IFQ_POLL(&ifp->if_snd, m0); 1202 if (m0 == NULL) 1203 break; 1204 #ifndef DP83820 1205 m = NULL; 1206 #endif 1207 1208 dmamap = txs->txs_dmamap; 1209 1210 #ifdef DP83820 1211 /* 1212 * Load the DMA map. If this fails, the packet either 1213 * didn't fit in the allotted number of segments, or we 1214 * were short on resources. For the too-many-segments 1215 * case, we simply report an error and drop the packet, 1216 * since we can't sanely copy a jumbo packet to a single 1217 * buffer. 1218 */ 1219 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1220 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1221 if (error) { 1222 if (error == EFBIG) { 1223 printf("%s: Tx packet consumes too many " 1224 "DMA segments, dropping...\n", 1225 sc->sc_dev.dv_xname); 1226 IFQ_DEQUEUE(&ifp->if_snd, m0); 1227 m_freem(m0); 1228 continue; 1229 } 1230 /* 1231 * Short on resources, just stop for now. 1232 */ 1233 break; 1234 } 1235 #else /* DP83820 */ 1236 /* 1237 * Load the DMA map. If this fails, the packet either 1238 * didn't fit in the alloted number of segments, or we 1239 * were short on resources. In this case, we'll copy 1240 * and try again. 1241 */ 1242 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1243 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1244 MGETHDR(m, M_DONTWAIT, MT_DATA); 1245 if (m == NULL) { 1246 printf("%s: unable to allocate Tx mbuf\n", 1247 sc->sc_dev.dv_xname); 1248 break; 1249 } 1250 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1251 if (m0->m_pkthdr.len > MHLEN) { 1252 MCLGET(m, M_DONTWAIT); 1253 if ((m->m_flags & M_EXT) == 0) { 1254 printf("%s: unable to allocate Tx " 1255 "cluster\n", sc->sc_dev.dv_xname); 1256 m_freem(m); 1257 break; 1258 } 1259 } 1260 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1261 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1262 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1263 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1264 if (error) { 1265 printf("%s: unable to load Tx buffer, " 1266 "error = %d\n", sc->sc_dev.dv_xname, error); 1267 break; 1268 } 1269 } 1270 #endif /* DP83820 */ 1271 1272 /* 1273 * Ensure we have enough descriptors free to describe 1274 * the packet. Note, we always reserve one descriptor 1275 * at the end of the ring as a termination point, to 1276 * prevent wrap-around. 1277 */ 1278 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1279 /* 1280 * Not enough free descriptors to transmit this 1281 * packet. We haven't committed anything yet, 1282 * so just unload the DMA map, put the packet 1283 * back on the queue, and punt. Notify the upper 1284 * layer that there are not more slots left. 1285 * 1286 * XXX We could allocate an mbuf and copy, but 1287 * XXX is it worth it? 1288 */ 1289 ifp->if_flags |= IFF_OACTIVE; 1290 bus_dmamap_unload(sc->sc_dmat, dmamap); 1291 #ifndef DP83820 1292 if (m != NULL) 1293 m_freem(m); 1294 #endif 1295 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1296 break; 1297 } 1298 1299 IFQ_DEQUEUE(&ifp->if_snd, m0); 1300 #ifndef DP83820 1301 if (m != NULL) { 1302 m_freem(m0); 1303 m0 = m; 1304 } 1305 #endif 1306 1307 /* 1308 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1309 */ 1310 1311 /* Sync the DMA map. */ 1312 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1313 BUS_DMASYNC_PREWRITE); 1314 1315 /* 1316 * Initialize the transmit descriptors. 1317 */ 1318 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1319 seg < dmamap->dm_nsegs; 1320 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1321 /* 1322 * If this is the first descriptor we're 1323 * enqueueing, don't set the OWN bit just 1324 * yet. That could cause a race condition. 1325 * We'll do it below. 1326 */ 1327 sc->sc_txdescs[nexttx].sipd_bufptr = 1328 htole32(dmamap->dm_segs[seg].ds_addr); 1329 sc->sc_txdescs[nexttx].sipd_cmdsts = 1330 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1331 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1332 #ifdef DP83820 1333 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1334 #endif /* DP83820 */ 1335 lasttx = nexttx; 1336 } 1337 1338 /* Clear the MORE bit on the last segment. */ 1339 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1340 1341 /* 1342 * If we're in the interrupt delay window, delay the 1343 * interrupt. 1344 */ 1345 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1346 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1347 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1348 htole32(CMDSTS_INTR); 1349 sc->sc_txwin = 0; 1350 } 1351 1352 #ifdef DP83820 1353 /* 1354 * If VLANs are enabled and the packet has a VLAN tag, set 1355 * up the descriptor to encapsulate the packet for us. 1356 * 1357 * This apparently has to be on the last descriptor of 1358 * the packet. 1359 */ 1360 1361 /* 1362 * Byte swapping is tricky. We need to provide the tag 1363 * in a network byte order. On a big-endian machine, 1364 * the byteorder is correct, but we need to swap it 1365 * anyway, because this will be undone by the outside 1366 * htole32(). That's why there must be an 1367 * unconditional swap instead of htons() inside. 1368 */ 1369 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1370 sc->sc_txdescs[lasttx].sipd_extsts |= 1371 htole32(EXTSTS_VPKT | 1372 (bswap16(VLAN_TAG_VALUE(mtag)) & 1373 EXTSTS_VTCI)); 1374 } 1375 1376 /* 1377 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1378 * checksumming, set up the descriptor to do this work 1379 * for us. 1380 * 1381 * This apparently has to be on the first descriptor of 1382 * the packet. 1383 * 1384 * Byte-swap constants so the compiler can optimize. 1385 */ 1386 extsts = 0; 1387 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1388 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1389 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1390 extsts |= htole32(EXTSTS_IPPKT); 1391 } 1392 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1393 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1394 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1395 extsts |= htole32(EXTSTS_TCPPKT); 1396 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1397 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1398 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1399 extsts |= htole32(EXTSTS_UDPPKT); 1400 } 1401 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1402 #endif /* DP83820 */ 1403 1404 /* Sync the descriptors we're using. */ 1405 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1406 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1407 1408 /* 1409 * The entire packet is set up. Give the first descrptor 1410 * to the chip now. 1411 */ 1412 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1413 htole32(CMDSTS_OWN); 1414 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1415 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1416 1417 /* 1418 * Store a pointer to the packet so we can free it later, 1419 * and remember what txdirty will be once the packet is 1420 * done. 1421 */ 1422 txs->txs_mbuf = m0; 1423 txs->txs_firstdesc = sc->sc_txnext; 1424 txs->txs_lastdesc = lasttx; 1425 1426 /* Advance the tx pointer. */ 1427 sc->sc_txfree -= dmamap->dm_nsegs; 1428 sc->sc_txnext = nexttx; 1429 1430 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1431 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1432 1433 #if NBPFILTER > 0 1434 /* 1435 * Pass the packet to any BPF listeners. 1436 */ 1437 if (ifp->if_bpf) 1438 bpf_mtap(ifp->if_bpf, m0); 1439 #endif /* NBPFILTER > 0 */ 1440 } 1441 1442 if (txs == NULL || sc->sc_txfree == 0) { 1443 /* No more slots left; notify upper layer. */ 1444 ifp->if_flags |= IFF_OACTIVE; 1445 } 1446 1447 if (sc->sc_txfree != ofree) { 1448 /* 1449 * Start the transmit process. Note, the manual says 1450 * that if there are no pending transmissions in the 1451 * chip's internal queue (indicated by TXE being clear), 1452 * then the driver software must set the TXDP to the 1453 * first descriptor to be transmitted. However, if we 1454 * do this, it causes serious performance degredation on 1455 * the DP83820 under load, not setting TXDP doesn't seem 1456 * to adversely affect the SiS 900 or DP83815. 1457 * 1458 * Well, I guess it wouldn't be the first time a manual 1459 * has lied -- and they could be speaking of the NULL- 1460 * terminated descriptor list case, rather than OWN- 1461 * terminated rings. 1462 */ 1463 #if 0 1464 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1465 CR_TXE) == 0) { 1466 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1467 SIP_CDTXADDR(sc, firsttx)); 1468 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1469 } 1470 #else 1471 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1472 #endif 1473 1474 /* Set a watchdog timer in case the chip flakes out. */ 1475 #ifdef DP83820 1476 /* Gigabit autonegotiation takes 5 seconds. */ 1477 ifp->if_timer = 10; 1478 #else 1479 ifp->if_timer = 5; 1480 #endif 1481 } 1482 } 1483 1484 /* 1485 * sip_watchdog: [ifnet interface function] 1486 * 1487 * Watchdog timer handler. 1488 */ 1489 static void 1490 SIP_DECL(watchdog)(struct ifnet *ifp) 1491 { 1492 struct sip_softc *sc = ifp->if_softc; 1493 1494 /* 1495 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1496 * If we get a timeout, try and sweep up transmit descriptors. 1497 * If we manage to sweep them all up, ignore the lack of 1498 * interrupt. 1499 */ 1500 SIP_DECL(txintr)(sc); 1501 1502 if (sc->sc_txfree != SIP_NTXDESC) { 1503 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1504 ifp->if_oerrors++; 1505 1506 /* Reset the interface. */ 1507 (void) SIP_DECL(init)(ifp); 1508 } else if (ifp->if_flags & IFF_DEBUG) 1509 printf("%s: recovered from device timeout\n", 1510 sc->sc_dev.dv_xname); 1511 1512 /* Try to get more packets going. */ 1513 SIP_DECL(start)(ifp); 1514 } 1515 1516 /* 1517 * sip_ioctl: [ifnet interface function] 1518 * 1519 * Handle control requests from the operator. 1520 */ 1521 static int 1522 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, void *data) 1523 { 1524 struct sip_softc *sc = ifp->if_softc; 1525 struct ifreq *ifr = (struct ifreq *)data; 1526 int s, error; 1527 1528 s = splnet(); 1529 1530 switch (cmd) { 1531 case SIOCSIFMEDIA: 1532 /* Flow control requires full-duplex mode. */ 1533 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1534 (ifr->ifr_media & IFM_FDX) == 0) 1535 ifr->ifr_media &= ~IFM_ETH_FMASK; 1536 #ifdef DP83820 1537 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1538 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1539 /* We can do both TXPAUSE and RXPAUSE. */ 1540 ifr->ifr_media |= 1541 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1542 } 1543 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1544 } 1545 #else 1546 /* XXX */ 1547 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1548 ifr->ifr_media &= ~IFM_ETH_FMASK; 1549 1550 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1551 if (ifr->ifr_media & IFM_FLOW) { 1552 /* 1553 * Both TXPAUSE and RXPAUSE must be set. 1554 * (SiS900 and DP83815 don't have PAUSE_ASYM 1555 * feature.) 1556 * 1557 * XXX Can SiS900 and DP83815 send PAUSE? 1558 */ 1559 ifr->ifr_media |= 1560 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1561 } 1562 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1563 } 1564 #endif 1565 /* FALLTHROUGH */ 1566 case SIOCGIFMEDIA: 1567 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1568 break; 1569 case SIOCSIFFLAGS: 1570 /* If the interface is up and running, only modify the receive 1571 * filter when setting promiscuous or debug mode. Otherwise 1572 * fall through to ether_ioctl, which will reset the chip. 1573 */ 1574 1575 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1576 == (sc)->sc_ethercom.ec_capenable) \ 1577 && ((sc)->sc_prev.is_vlan == \ 1578 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1579 1580 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1581 1582 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1583 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1584 == (IFF_UP|IFF_RUNNING)) 1585 && ((ifp->if_flags & (~RESETIGN)) 1586 == (sc->sc_if_flags & (~RESETIGN))) 1587 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1588 /* Set up the receive filter. */ 1589 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1590 error = 0; 1591 break; 1592 #undef RESETIGN 1593 } 1594 /* FALLTHROUGH */ 1595 default: 1596 error = ether_ioctl(ifp, cmd, data); 1597 if (error == ENETRESET) { 1598 /* 1599 * Multicast list has changed; set the hardware filter 1600 * accordingly. 1601 */ 1602 if (ifp->if_flags & IFF_RUNNING) 1603 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1604 error = 0; 1605 } 1606 break; 1607 } 1608 1609 /* Try to get more packets going. */ 1610 SIP_DECL(start)(ifp); 1611 1612 sc->sc_if_flags = ifp->if_flags; 1613 splx(s); 1614 return (error); 1615 } 1616 1617 /* 1618 * sip_intr: 1619 * 1620 * Interrupt service routine. 1621 */ 1622 static int 1623 SIP_DECL(intr)(void *arg) 1624 { 1625 struct sip_softc *sc = arg; 1626 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1627 u_int32_t isr; 1628 int handled = 0; 1629 1630 /* Disable interrupts. */ 1631 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1632 1633 for (;;) { 1634 /* Reading clears interrupt. */ 1635 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1636 if ((isr & sc->sc_imr) == 0) 1637 break; 1638 1639 #if NRND > 0 1640 if (RND_ENABLED(&sc->rnd_source)) 1641 rnd_add_uint32(&sc->rnd_source, isr); 1642 #endif 1643 1644 handled = 1; 1645 1646 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1647 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1648 1649 /* Grab any new packets. */ 1650 SIP_DECL(rxintr)(sc); 1651 1652 if (isr & ISR_RXORN) { 1653 printf("%s: receive FIFO overrun\n", 1654 sc->sc_dev.dv_xname); 1655 1656 /* XXX adjust rx_drain_thresh? */ 1657 } 1658 1659 if (isr & ISR_RXIDLE) { 1660 printf("%s: receive ring overrun\n", 1661 sc->sc_dev.dv_xname); 1662 1663 /* Get the receive process going again. */ 1664 bus_space_write_4(sc->sc_st, sc->sc_sh, 1665 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1666 bus_space_write_4(sc->sc_st, sc->sc_sh, 1667 SIP_CR, CR_RXE); 1668 } 1669 } 1670 1671 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1672 #ifdef SIP_EVENT_COUNTERS 1673 if (isr & ISR_TXDESC) 1674 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1675 else if (isr & ISR_TXIDLE) 1676 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1677 #endif 1678 1679 /* Sweep up transmit descriptors. */ 1680 SIP_DECL(txintr)(sc); 1681 1682 if (isr & ISR_TXURN) { 1683 u_int32_t thresh; 1684 1685 printf("%s: transmit FIFO underrun", 1686 sc->sc_dev.dv_xname); 1687 1688 thresh = sc->sc_tx_drain_thresh + 1; 1689 if (thresh <= TXCFG_DRTH && 1690 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1691 (sc->sc_tx_fill_thresh * 32))) { 1692 printf("; increasing Tx drain " 1693 "threshold to %u bytes\n", 1694 thresh * 32); 1695 sc->sc_tx_drain_thresh = thresh; 1696 (void) SIP_DECL(init)(ifp); 1697 } else { 1698 (void) SIP_DECL(init)(ifp); 1699 printf("\n"); 1700 } 1701 } 1702 } 1703 1704 #if !defined(DP83820) 1705 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1706 if (isr & ISR_PAUSE_ST) { 1707 sc->sc_paused = 1; 1708 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1709 ifp->if_flags |= IFF_OACTIVE; 1710 } 1711 if (isr & ISR_PAUSE_END) { 1712 sc->sc_paused = 0; 1713 ifp->if_flags &= ~IFF_OACTIVE; 1714 } 1715 } 1716 #endif /* ! DP83820 */ 1717 1718 if (isr & ISR_HIBERR) { 1719 int want_init = 0; 1720 1721 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1722 1723 #define PRINTERR(bit, str) \ 1724 do { \ 1725 if ((isr & (bit)) != 0) { \ 1726 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1727 printf("%s: %s\n", \ 1728 sc->sc_dev.dv_xname, str); \ 1729 want_init = 1; \ 1730 } \ 1731 } while (/*CONSTCOND*/0) 1732 1733 PRINTERR(ISR_DPERR, "parity error"); 1734 PRINTERR(ISR_SSERR, "system error"); 1735 PRINTERR(ISR_RMABT, "master abort"); 1736 PRINTERR(ISR_RTABT, "target abort"); 1737 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1738 /* 1739 * Ignore: 1740 * Tx reset complete 1741 * Rx reset complete 1742 */ 1743 if (want_init) 1744 (void) SIP_DECL(init)(ifp); 1745 #undef PRINTERR 1746 } 1747 } 1748 1749 /* Re-enable interrupts. */ 1750 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1751 1752 /* Try to get more packets going. */ 1753 SIP_DECL(start)(ifp); 1754 1755 return (handled); 1756 } 1757 1758 /* 1759 * sip_txintr: 1760 * 1761 * Helper; handle transmit interrupts. 1762 */ 1763 static void 1764 SIP_DECL(txintr)(struct sip_softc *sc) 1765 { 1766 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1767 struct sip_txsoft *txs; 1768 u_int32_t cmdsts; 1769 1770 #ifndef DP83820 1771 if (sc->sc_paused == 0) 1772 #endif 1773 ifp->if_flags &= ~IFF_OACTIVE; 1774 1775 /* 1776 * Go through our Tx list and free mbufs for those 1777 * frames which have been transmitted. 1778 */ 1779 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1780 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1781 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1782 1783 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1784 if (cmdsts & CMDSTS_OWN) 1785 break; 1786 1787 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1788 1789 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1790 1791 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1792 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1793 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1794 m_freem(txs->txs_mbuf); 1795 txs->txs_mbuf = NULL; 1796 1797 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1798 1799 /* 1800 * Check for errors and collisions. 1801 */ 1802 if (cmdsts & 1803 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1804 ifp->if_oerrors++; 1805 if (cmdsts & CMDSTS_Tx_EC) 1806 ifp->if_collisions += 16; 1807 if (ifp->if_flags & IFF_DEBUG) { 1808 if (cmdsts & CMDSTS_Tx_ED) 1809 printf("%s: excessive deferral\n", 1810 sc->sc_dev.dv_xname); 1811 if (cmdsts & CMDSTS_Tx_EC) 1812 printf("%s: excessive collisions\n", 1813 sc->sc_dev.dv_xname); 1814 } 1815 } else { 1816 /* Packet was transmitted successfully. */ 1817 ifp->if_opackets++; 1818 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1819 } 1820 } 1821 1822 /* 1823 * If there are no more pending transmissions, cancel the watchdog 1824 * timer. 1825 */ 1826 if (txs == NULL) { 1827 ifp->if_timer = 0; 1828 sc->sc_txwin = 0; 1829 } 1830 } 1831 1832 #if defined(DP83820) 1833 /* 1834 * sip_rxintr: 1835 * 1836 * Helper; handle receive interrupts. 1837 */ 1838 static void 1839 SIP_DECL(rxintr)(struct sip_softc *sc) 1840 { 1841 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1842 struct sip_rxsoft *rxs; 1843 struct mbuf *m; 1844 u_int32_t cmdsts, extsts; 1845 int i, len; 1846 1847 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 1848 rxs = &sc->sc_rxsoft[i]; 1849 1850 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1851 1852 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1853 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1854 len = CMDSTS_SIZE(cmdsts); 1855 1856 /* 1857 * NOTE: OWN is set if owned by _consumer_. We're the 1858 * consumer of the receive ring, so if the bit is clear, 1859 * we have processed all of the packets. 1860 */ 1861 if ((cmdsts & CMDSTS_OWN) == 0) { 1862 /* 1863 * We have processed all of the receive buffers. 1864 */ 1865 break; 1866 } 1867 1868 if (__predict_false(sc->sc_rxdiscard)) { 1869 SIP_INIT_RXDESC(sc, i); 1870 if ((cmdsts & CMDSTS_MORE) == 0) { 1871 /* Reset our state. */ 1872 sc->sc_rxdiscard = 0; 1873 } 1874 continue; 1875 } 1876 1877 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1878 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1879 1880 m = rxs->rxs_mbuf; 1881 1882 /* 1883 * Add a new receive buffer to the ring. 1884 */ 1885 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1886 /* 1887 * Failed, throw away what we've done so 1888 * far, and discard the rest of the packet. 1889 */ 1890 ifp->if_ierrors++; 1891 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1892 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1893 SIP_INIT_RXDESC(sc, i); 1894 if (cmdsts & CMDSTS_MORE) 1895 sc->sc_rxdiscard = 1; 1896 if (sc->sc_rxhead != NULL) 1897 m_freem(sc->sc_rxhead); 1898 SIP_RXCHAIN_RESET(sc); 1899 continue; 1900 } 1901 1902 SIP_RXCHAIN_LINK(sc, m); 1903 1904 m->m_len = len; 1905 1906 /* 1907 * If this is not the end of the packet, keep 1908 * looking. 1909 */ 1910 if (cmdsts & CMDSTS_MORE) { 1911 sc->sc_rxlen += len; 1912 continue; 1913 } 1914 1915 /* 1916 * Okay, we have the entire packet now. The chip includes 1917 * the FCS, so we need to trim it. 1918 */ 1919 m->m_len -= ETHER_CRC_LEN; 1920 1921 *sc->sc_rxtailp = NULL; 1922 len = m->m_len + sc->sc_rxlen; 1923 m = sc->sc_rxhead; 1924 1925 SIP_RXCHAIN_RESET(sc); 1926 1927 /* 1928 * If an error occurred, update stats and drop the packet. 1929 */ 1930 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1931 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1932 ifp->if_ierrors++; 1933 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1934 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1935 /* Receive overrun handled elsewhere. */ 1936 printf("%s: receive descriptor error\n", 1937 sc->sc_dev.dv_xname); 1938 } 1939 #define PRINTERR(bit, str) \ 1940 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1941 (cmdsts & (bit)) != 0) \ 1942 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1943 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1944 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1945 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1946 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1947 #undef PRINTERR 1948 m_freem(m); 1949 continue; 1950 } 1951 1952 /* 1953 * If the packet is small enough to fit in a 1954 * single header mbuf, allocate one and copy 1955 * the data into it. This greatly reduces 1956 * memory consumption when we receive lots 1957 * of small packets. 1958 */ 1959 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1960 struct mbuf *nm; 1961 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1962 if (nm == NULL) { 1963 ifp->if_ierrors++; 1964 m_freem(m); 1965 continue; 1966 } 1967 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1968 nm->m_data += 2; 1969 nm->m_pkthdr.len = nm->m_len = len; 1970 m_copydata(m, 0, len, mtod(nm, void *)); 1971 m_freem(m); 1972 m = nm; 1973 } 1974 #ifndef __NO_STRICT_ALIGNMENT 1975 else { 1976 /* 1977 * The DP83820's receive buffers must be 4-byte 1978 * aligned. But this means that the data after 1979 * the Ethernet header is misaligned. To compensate, 1980 * we have artificially shortened the buffer size 1981 * in the descriptor, and we do an overlapping copy 1982 * of the data two bytes further in (in the first 1983 * buffer of the chain only). 1984 */ 1985 memmove(mtod(m, char *) + 2, mtod(m, void *), 1986 m->m_len); 1987 m->m_data += 2; 1988 } 1989 #endif /* ! __NO_STRICT_ALIGNMENT */ 1990 1991 /* 1992 * If VLANs are enabled, VLAN packets have been unwrapped 1993 * for us. Associate the tag with the packet. 1994 */ 1995 1996 /* 1997 * Again, byte swapping is tricky. Hardware provided 1998 * the tag in the network byte order, but extsts was 1999 * passed through le32toh() in the meantime. On a 2000 * big-endian machine, we need to swap it again. On a 2001 * little-endian machine, we need to convert from the 2002 * network to host byte order. This means that we must 2003 * swap it in any case, so unconditional swap instead 2004 * of htons() is used. 2005 */ 2006 if ((extsts & EXTSTS_VPKT) != 0) { 2007 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2008 continue); 2009 } 2010 2011 /* 2012 * Set the incoming checksum information for the 2013 * packet. 2014 */ 2015 if ((extsts & EXTSTS_IPPKT) != 0) { 2016 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2017 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2018 if (extsts & EXTSTS_Rx_IPERR) 2019 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2020 if (extsts & EXTSTS_TCPPKT) { 2021 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2022 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2023 if (extsts & EXTSTS_Rx_TCPERR) 2024 m->m_pkthdr.csum_flags |= 2025 M_CSUM_TCP_UDP_BAD; 2026 } else if (extsts & EXTSTS_UDPPKT) { 2027 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2028 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2029 if (extsts & EXTSTS_Rx_UDPERR) 2030 m->m_pkthdr.csum_flags |= 2031 M_CSUM_TCP_UDP_BAD; 2032 } 2033 } 2034 2035 ifp->if_ipackets++; 2036 m->m_pkthdr.rcvif = ifp; 2037 m->m_pkthdr.len = len; 2038 2039 #if NBPFILTER > 0 2040 /* 2041 * Pass this up to any BPF listeners, but only 2042 * pass if up the stack if it's for us. 2043 */ 2044 if (ifp->if_bpf) 2045 bpf_mtap(ifp->if_bpf, m); 2046 #endif /* NBPFILTER > 0 */ 2047 2048 /* Pass it on. */ 2049 (*ifp->if_input)(ifp, m); 2050 } 2051 2052 /* Update the receive pointer. */ 2053 sc->sc_rxptr = i; 2054 } 2055 #else /* ! DP83820 */ 2056 /* 2057 * sip_rxintr: 2058 * 2059 * Helper; handle receive interrupts. 2060 */ 2061 static void 2062 SIP_DECL(rxintr)(struct sip_softc *sc) 2063 { 2064 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2065 struct sip_rxsoft *rxs; 2066 struct mbuf *m; 2067 u_int32_t cmdsts; 2068 int i, len; 2069 2070 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2071 rxs = &sc->sc_rxsoft[i]; 2072 2073 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2074 2075 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2076 2077 /* 2078 * NOTE: OWN is set if owned by _consumer_. We're the 2079 * consumer of the receive ring, so if the bit is clear, 2080 * we have processed all of the packets. 2081 */ 2082 if ((cmdsts & CMDSTS_OWN) == 0) { 2083 /* 2084 * We have processed all of the receive buffers. 2085 */ 2086 break; 2087 } 2088 2089 /* 2090 * If any collisions were seen on the wire, count one. 2091 */ 2092 if (cmdsts & CMDSTS_Rx_COL) 2093 ifp->if_collisions++; 2094 2095 /* 2096 * If an error occurred, update stats, clear the status 2097 * word, and leave the packet buffer in place. It will 2098 * simply be reused the next time the ring comes around. 2099 */ 2100 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2101 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2102 ifp->if_ierrors++; 2103 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2104 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2105 /* Receive overrun handled elsewhere. */ 2106 printf("%s: receive descriptor error\n", 2107 sc->sc_dev.dv_xname); 2108 } 2109 #define PRINTERR(bit, str) \ 2110 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2111 (cmdsts & (bit)) != 0) \ 2112 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2113 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2114 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2115 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2116 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2117 #undef PRINTERR 2118 SIP_INIT_RXDESC(sc, i); 2119 continue; 2120 } 2121 2122 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2123 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2124 2125 /* 2126 * No errors; receive the packet. Note, the SiS 900 2127 * includes the CRC with every packet. 2128 */ 2129 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2130 2131 #ifdef __NO_STRICT_ALIGNMENT 2132 /* 2133 * If the packet is small enough to fit in a 2134 * single header mbuf, allocate one and copy 2135 * the data into it. This greatly reduces 2136 * memory consumption when we receive lots 2137 * of small packets. 2138 * 2139 * Otherwise, we add a new buffer to the receive 2140 * chain. If this fails, we drop the packet and 2141 * recycle the old buffer. 2142 */ 2143 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2144 MGETHDR(m, M_DONTWAIT, MT_DATA); 2145 if (m == NULL) 2146 goto dropit; 2147 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2148 memcpy(mtod(m, void *), 2149 mtod(rxs->rxs_mbuf, void *), len); 2150 SIP_INIT_RXDESC(sc, i); 2151 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2152 rxs->rxs_dmamap->dm_mapsize, 2153 BUS_DMASYNC_PREREAD); 2154 } else { 2155 m = rxs->rxs_mbuf; 2156 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2157 dropit: 2158 ifp->if_ierrors++; 2159 SIP_INIT_RXDESC(sc, i); 2160 bus_dmamap_sync(sc->sc_dmat, 2161 rxs->rxs_dmamap, 0, 2162 rxs->rxs_dmamap->dm_mapsize, 2163 BUS_DMASYNC_PREREAD); 2164 continue; 2165 } 2166 } 2167 #else 2168 /* 2169 * The SiS 900's receive buffers must be 4-byte aligned. 2170 * But this means that the data after the Ethernet header 2171 * is misaligned. We must allocate a new buffer and 2172 * copy the data, shifted forward 2 bytes. 2173 */ 2174 MGETHDR(m, M_DONTWAIT, MT_DATA); 2175 if (m == NULL) { 2176 dropit: 2177 ifp->if_ierrors++; 2178 SIP_INIT_RXDESC(sc, i); 2179 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2180 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2181 continue; 2182 } 2183 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2184 if (len > (MHLEN - 2)) { 2185 MCLGET(m, M_DONTWAIT); 2186 if ((m->m_flags & M_EXT) == 0) { 2187 m_freem(m); 2188 goto dropit; 2189 } 2190 } 2191 m->m_data += 2; 2192 2193 /* 2194 * Note that we use clusters for incoming frames, so the 2195 * buffer is virtually contiguous. 2196 */ 2197 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2198 2199 /* Allow the receive descriptor to continue using its mbuf. */ 2200 SIP_INIT_RXDESC(sc, i); 2201 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2202 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2203 #endif /* __NO_STRICT_ALIGNMENT */ 2204 2205 ifp->if_ipackets++; 2206 m->m_pkthdr.rcvif = ifp; 2207 m->m_pkthdr.len = m->m_len = len; 2208 2209 #if NBPFILTER > 0 2210 /* 2211 * Pass this up to any BPF listeners, but only 2212 * pass if up the stack if it's for us. 2213 */ 2214 if (ifp->if_bpf) 2215 bpf_mtap(ifp->if_bpf, m); 2216 #endif /* NBPFILTER > 0 */ 2217 2218 /* Pass it on. */ 2219 (*ifp->if_input)(ifp, m); 2220 } 2221 2222 /* Update the receive pointer. */ 2223 sc->sc_rxptr = i; 2224 } 2225 #endif /* DP83820 */ 2226 2227 /* 2228 * sip_tick: 2229 * 2230 * One second timer, used to tick the MII. 2231 */ 2232 static void 2233 SIP_DECL(tick)(void *arg) 2234 { 2235 struct sip_softc *sc = arg; 2236 int s; 2237 2238 s = splnet(); 2239 #ifdef DP83820 2240 #ifdef SIP_EVENT_COUNTERS 2241 /* Read PAUSE related counts from MIB registers. */ 2242 sc->sc_ev_rxpause.ev_count += 2243 bus_space_read_4(sc->sc_st, sc->sc_sh, 2244 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2245 sc->sc_ev_txpause.ev_count += 2246 bus_space_read_4(sc->sc_st, sc->sc_sh, 2247 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2248 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2249 #endif /* SIP_EVENT_COUNTERS */ 2250 #endif /* DP83820 */ 2251 mii_tick(&sc->sc_mii); 2252 splx(s); 2253 2254 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2255 } 2256 2257 /* 2258 * sip_reset: 2259 * 2260 * Perform a soft reset on the SiS 900. 2261 */ 2262 static void 2263 SIP_DECL(reset)(struct sip_softc *sc) 2264 { 2265 bus_space_tag_t st = sc->sc_st; 2266 bus_space_handle_t sh = sc->sc_sh; 2267 int i; 2268 2269 bus_space_write_4(st, sh, SIP_IER, 0); 2270 bus_space_write_4(st, sh, SIP_IMR, 0); 2271 bus_space_write_4(st, sh, SIP_RFCR, 0); 2272 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2273 2274 for (i = 0; i < SIP_TIMEOUT; i++) { 2275 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2276 break; 2277 delay(2); 2278 } 2279 2280 if (i == SIP_TIMEOUT) 2281 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2282 2283 delay(1000); 2284 2285 #ifdef DP83820 2286 /* 2287 * Set the general purpose I/O bits. Do it here in case we 2288 * need to have GPIO set up to talk to the media interface. 2289 */ 2290 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2291 delay(1000); 2292 #endif /* DP83820 */ 2293 } 2294 2295 /* 2296 * sip_init: [ ifnet interface function ] 2297 * 2298 * Initialize the interface. Must be called at splnet(). 2299 */ 2300 static int 2301 SIP_DECL(init)(struct ifnet *ifp) 2302 { 2303 struct sip_softc *sc = ifp->if_softc; 2304 bus_space_tag_t st = sc->sc_st; 2305 bus_space_handle_t sh = sc->sc_sh; 2306 struct sip_txsoft *txs; 2307 struct sip_rxsoft *rxs; 2308 struct sip_desc *sipd; 2309 #if defined(DP83820) 2310 u_int32_t reg; 2311 #endif 2312 int i, error = 0; 2313 2314 /* 2315 * Cancel any pending I/O. 2316 */ 2317 SIP_DECL(stop)(ifp, 0); 2318 2319 /* 2320 * Reset the chip to a known state. 2321 */ 2322 SIP_DECL(reset)(sc); 2323 2324 #if !defined(DP83820) 2325 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2326 /* 2327 * DP83815 manual, page 78: 2328 * 4.4 Recommended Registers Configuration 2329 * For optimum performance of the DP83815, version noted 2330 * as DP83815CVNG (SRR = 203h), the listed register 2331 * modifications must be followed in sequence... 2332 * 2333 * It's not clear if this should be 302h or 203h because that 2334 * chip name is listed as SRR 302h in the description of the 2335 * SRR register. However, my revision 302h DP83815 on the 2336 * Netgear FA311 purchased in 02/2001 needs these settings 2337 * to avoid tons of errors in AcceptPerfectMatch (non- 2338 * IFF_PROMISC) mode. I do not know if other revisions need 2339 * this set or not. [briggs -- 09 March 2001] 2340 * 2341 * Note that only the low-order 12 bits of 0xe4 are documented 2342 * and that this sets reserved bits in that register. 2343 */ 2344 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2345 2346 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2347 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2348 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2349 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2350 2351 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2352 } 2353 #endif /* ! DP83820 */ 2354 2355 /* 2356 * Initialize the transmit descriptor ring. 2357 */ 2358 for (i = 0; i < SIP_NTXDESC; i++) { 2359 sipd = &sc->sc_txdescs[i]; 2360 memset(sipd, 0, sizeof(struct sip_desc)); 2361 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2362 } 2363 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2364 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2365 sc->sc_txfree = SIP_NTXDESC; 2366 sc->sc_txnext = 0; 2367 sc->sc_txwin = 0; 2368 2369 /* 2370 * Initialize the transmit job descriptors. 2371 */ 2372 SIMPLEQ_INIT(&sc->sc_txfreeq); 2373 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2374 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2375 txs = &sc->sc_txsoft[i]; 2376 txs->txs_mbuf = NULL; 2377 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2378 } 2379 2380 /* 2381 * Initialize the receive descriptor and receive job 2382 * descriptor rings. 2383 */ 2384 for (i = 0; i < SIP_NRXDESC; i++) { 2385 rxs = &sc->sc_rxsoft[i]; 2386 if (rxs->rxs_mbuf == NULL) { 2387 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2388 printf("%s: unable to allocate or map rx " 2389 "buffer %d, error = %d\n", 2390 sc->sc_dev.dv_xname, i, error); 2391 /* 2392 * XXX Should attempt to run with fewer receive 2393 * XXX buffers instead of just failing. 2394 */ 2395 SIP_DECL(rxdrain)(sc); 2396 goto out; 2397 } 2398 } else 2399 SIP_INIT_RXDESC(sc, i); 2400 } 2401 sc->sc_rxptr = 0; 2402 #ifdef DP83820 2403 sc->sc_rxdiscard = 0; 2404 SIP_RXCHAIN_RESET(sc); 2405 #endif /* DP83820 */ 2406 2407 /* 2408 * Set the configuration register; it's already initialized 2409 * in sip_attach(). 2410 */ 2411 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2412 2413 /* 2414 * Initialize the prototype TXCFG register. 2415 */ 2416 #if defined(DP83820) 2417 sc->sc_txcfg = TXCFG_MXDMA_512; 2418 sc->sc_rxcfg = RXCFG_MXDMA_512; 2419 #else 2420 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2421 SIP_SIS900_REV(sc, SIS_REV_960) || 2422 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2423 (sc->sc_cfg & CFG_EDBMASTEN)) { 2424 sc->sc_txcfg = TXCFG_MXDMA_64; 2425 sc->sc_rxcfg = RXCFG_MXDMA_64; 2426 } else { 2427 sc->sc_txcfg = TXCFG_MXDMA_512; 2428 sc->sc_rxcfg = RXCFG_MXDMA_512; 2429 } 2430 #endif /* DP83820 */ 2431 2432 sc->sc_txcfg |= TXCFG_ATP | 2433 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2434 sc->sc_tx_drain_thresh; 2435 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2436 2437 /* 2438 * Initialize the receive drain threshold if we have never 2439 * done so. 2440 */ 2441 if (sc->sc_rx_drain_thresh == 0) { 2442 /* 2443 * XXX This value should be tuned. This is set to the 2444 * maximum of 248 bytes, and we may be able to improve 2445 * performance by decreasing it (although we should never 2446 * set this value lower than 2; 14 bytes are required to 2447 * filter the packet). 2448 */ 2449 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2450 } 2451 2452 /* 2453 * Initialize the prototype RXCFG register. 2454 */ 2455 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2456 #ifdef DP83820 2457 /* 2458 * Accept long packets (including FCS) so we can handle 2459 * 802.1q-tagged frames and jumbo frames properly. 2460 */ 2461 if (ifp->if_mtu > ETHERMTU || 2462 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2463 sc->sc_rxcfg |= RXCFG_ALP; 2464 2465 /* 2466 * Checksum offloading is disabled if the user selects an MTU 2467 * larger than 8109. (FreeBSD says 8152, but there is emperical 2468 * evidence that >8109 does not work on some boards, such as the 2469 * Planex GN-1000TE). 2470 */ 2471 if (ifp->if_mtu > 8109 && 2472 (ifp->if_capenable & 2473 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2474 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2475 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2476 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2477 "disabled.\n", sc->sc_dev.dv_xname); 2478 ifp->if_capenable &= 2479 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2480 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2481 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2482 ifp->if_csum_flags_tx = 0; 2483 ifp->if_csum_flags_rx = 0; 2484 } 2485 #else 2486 /* 2487 * Accept packets >1518 bytes (including FCS) so we can handle 2488 * 802.1q-tagged frames properly. 2489 */ 2490 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2491 sc->sc_rxcfg |= RXCFG_ALP; 2492 #endif 2493 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2494 2495 #ifdef DP83820 2496 /* 2497 * Initialize the VLAN/IP receive control register. 2498 * We enable checksum computation on all incoming 2499 * packets, and do not reject packets w/ bad checksums. 2500 */ 2501 reg = 0; 2502 if (ifp->if_capenable & 2503 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2504 reg |= VRCR_IPEN; 2505 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2506 reg |= VRCR_VTDEN|VRCR_VTREN; 2507 bus_space_write_4(st, sh, SIP_VRCR, reg); 2508 2509 /* 2510 * Initialize the VLAN/IP transmit control register. 2511 * We enable outgoing checksum computation on a 2512 * per-packet basis. 2513 */ 2514 reg = 0; 2515 if (ifp->if_capenable & 2516 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2517 reg |= VTCR_PPCHK; 2518 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2519 reg |= VTCR_VPPTI; 2520 bus_space_write_4(st, sh, SIP_VTCR, reg); 2521 2522 /* 2523 * If we're using VLANs, initialize the VLAN data register. 2524 * To understand why we bswap the VLAN Ethertype, see section 2525 * 4.2.36 of the DP83820 manual. 2526 */ 2527 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2528 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2529 #endif /* DP83820 */ 2530 2531 /* 2532 * Give the transmit and receive rings to the chip. 2533 */ 2534 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2535 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2536 2537 /* 2538 * Initialize the interrupt mask. 2539 */ 2540 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2541 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2542 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2543 2544 /* Set up the receive filter. */ 2545 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2546 2547 #ifdef DP83820 2548 /* 2549 * Tune sc_rx_flow_thresh. 2550 * XXX "More than 8KB" is too short for jumbo frames. 2551 * XXX TODO: Threshold value should be user-settable. 2552 */ 2553 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2554 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2555 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2556 #endif 2557 2558 /* 2559 * Set the current media. Do this after initializing the prototype 2560 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2561 * control. 2562 */ 2563 mii_mediachg(&sc->sc_mii); 2564 2565 #ifdef DP83820 2566 /* 2567 * Set the interrupt hold-off timer to 100us. 2568 */ 2569 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2570 #endif 2571 2572 /* 2573 * Enable interrupts. 2574 */ 2575 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2576 2577 /* 2578 * Start the transmit and receive processes. 2579 */ 2580 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2581 2582 /* 2583 * Start the one second MII clock. 2584 */ 2585 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2586 2587 /* 2588 * ...all done! 2589 */ 2590 ifp->if_flags |= IFF_RUNNING; 2591 ifp->if_flags &= ~IFF_OACTIVE; 2592 sc->sc_if_flags = ifp->if_flags; 2593 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2594 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2595 sc->sc_prev.if_capenable = ifp->if_capenable; 2596 2597 out: 2598 if (error) 2599 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2600 return (error); 2601 } 2602 2603 /* 2604 * sip_drain: 2605 * 2606 * Drain the receive queue. 2607 */ 2608 static void 2609 SIP_DECL(rxdrain)(struct sip_softc *sc) 2610 { 2611 struct sip_rxsoft *rxs; 2612 int i; 2613 2614 for (i = 0; i < SIP_NRXDESC; i++) { 2615 rxs = &sc->sc_rxsoft[i]; 2616 if (rxs->rxs_mbuf != NULL) { 2617 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2618 m_freem(rxs->rxs_mbuf); 2619 rxs->rxs_mbuf = NULL; 2620 } 2621 } 2622 } 2623 2624 /* 2625 * sip_stop: [ ifnet interface function ] 2626 * 2627 * Stop transmission on the interface. 2628 */ 2629 static void 2630 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2631 { 2632 struct sip_softc *sc = ifp->if_softc; 2633 bus_space_tag_t st = sc->sc_st; 2634 bus_space_handle_t sh = sc->sc_sh; 2635 struct sip_txsoft *txs; 2636 u_int32_t cmdsts = 0; /* DEBUG */ 2637 2638 /* 2639 * Stop the one second clock. 2640 */ 2641 callout_stop(&sc->sc_tick_ch); 2642 2643 /* Down the MII. */ 2644 mii_down(&sc->sc_mii); 2645 2646 /* 2647 * Disable interrupts. 2648 */ 2649 bus_space_write_4(st, sh, SIP_IER, 0); 2650 2651 /* 2652 * Stop receiver and transmitter. 2653 */ 2654 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2655 2656 /* 2657 * Release any queued transmit buffers. 2658 */ 2659 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2660 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2661 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2662 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2663 CMDSTS_INTR) == 0) 2664 printf("%s: sip_stop: last descriptor does not " 2665 "have INTR bit set\n", sc->sc_dev.dv_xname); 2666 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2667 #ifdef DIAGNOSTIC 2668 if (txs->txs_mbuf == NULL) { 2669 printf("%s: dirty txsoft with no mbuf chain\n", 2670 sc->sc_dev.dv_xname); 2671 panic("sip_stop"); 2672 } 2673 #endif 2674 cmdsts |= /* DEBUG */ 2675 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2676 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2677 m_freem(txs->txs_mbuf); 2678 txs->txs_mbuf = NULL; 2679 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2680 } 2681 2682 if (disable) 2683 SIP_DECL(rxdrain)(sc); 2684 2685 /* 2686 * Mark the interface down and cancel the watchdog timer. 2687 */ 2688 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2689 ifp->if_timer = 0; 2690 2691 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2692 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2693 printf("%s: sip_stop: no INTR bits set in dirty tx " 2694 "descriptors\n", sc->sc_dev.dv_xname); 2695 } 2696 2697 /* 2698 * sip_read_eeprom: 2699 * 2700 * Read data from the serial EEPROM. 2701 */ 2702 static void 2703 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2704 u_int16_t *data) 2705 { 2706 bus_space_tag_t st = sc->sc_st; 2707 bus_space_handle_t sh = sc->sc_sh; 2708 u_int16_t reg; 2709 int i, x; 2710 2711 for (i = 0; i < wordcnt; i++) { 2712 /* Send CHIP SELECT. */ 2713 reg = EROMAR_EECS; 2714 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2715 2716 /* Shift in the READ opcode. */ 2717 for (x = 3; x > 0; x--) { 2718 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2719 reg |= EROMAR_EEDI; 2720 else 2721 reg &= ~EROMAR_EEDI; 2722 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2723 bus_space_write_4(st, sh, SIP_EROMAR, 2724 reg | EROMAR_EESK); 2725 delay(4); 2726 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2727 delay(4); 2728 } 2729 2730 /* Shift in address. */ 2731 for (x = 6; x > 0; x--) { 2732 if ((word + i) & (1 << (x - 1))) 2733 reg |= EROMAR_EEDI; 2734 else 2735 reg &= ~EROMAR_EEDI; 2736 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2737 bus_space_write_4(st, sh, SIP_EROMAR, 2738 reg | EROMAR_EESK); 2739 delay(4); 2740 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2741 delay(4); 2742 } 2743 2744 /* Shift out data. */ 2745 reg = EROMAR_EECS; 2746 data[i] = 0; 2747 for (x = 16; x > 0; x--) { 2748 bus_space_write_4(st, sh, SIP_EROMAR, 2749 reg | EROMAR_EESK); 2750 delay(4); 2751 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2752 data[i] |= (1 << (x - 1)); 2753 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2754 delay(4); 2755 } 2756 2757 /* Clear CHIP SELECT. */ 2758 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2759 delay(4); 2760 } 2761 } 2762 2763 /* 2764 * sip_add_rxbuf: 2765 * 2766 * Add a receive buffer to the indicated descriptor. 2767 */ 2768 static int 2769 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2770 { 2771 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2772 struct mbuf *m; 2773 int error; 2774 2775 MGETHDR(m, M_DONTWAIT, MT_DATA); 2776 if (m == NULL) 2777 return (ENOBUFS); 2778 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2779 2780 MCLGET(m, M_DONTWAIT); 2781 if ((m->m_flags & M_EXT) == 0) { 2782 m_freem(m); 2783 return (ENOBUFS); 2784 } 2785 2786 #if defined(DP83820) 2787 m->m_len = SIP_RXBUF_LEN; 2788 #endif /* DP83820 */ 2789 2790 if (rxs->rxs_mbuf != NULL) 2791 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2792 2793 rxs->rxs_mbuf = m; 2794 2795 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2796 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2797 BUS_DMA_READ|BUS_DMA_NOWAIT); 2798 if (error) { 2799 printf("%s: can't load rx DMA map %d, error = %d\n", 2800 sc->sc_dev.dv_xname, idx, error); 2801 panic("sip_add_rxbuf"); /* XXX */ 2802 } 2803 2804 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2805 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2806 2807 SIP_INIT_RXDESC(sc, idx); 2808 2809 return (0); 2810 } 2811 2812 #if !defined(DP83820) 2813 /* 2814 * sip_sis900_set_filter: 2815 * 2816 * Set up the receive filter. 2817 */ 2818 static void 2819 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 2820 { 2821 bus_space_tag_t st = sc->sc_st; 2822 bus_space_handle_t sh = sc->sc_sh; 2823 struct ethercom *ec = &sc->sc_ethercom; 2824 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2825 struct ether_multi *enm; 2826 u_int8_t *cp; 2827 struct ether_multistep step; 2828 u_int32_t crc, mchash[16]; 2829 2830 /* 2831 * Initialize the prototype RFCR. 2832 */ 2833 sc->sc_rfcr = RFCR_RFEN; 2834 if (ifp->if_flags & IFF_BROADCAST) 2835 sc->sc_rfcr |= RFCR_AAB; 2836 if (ifp->if_flags & IFF_PROMISC) { 2837 sc->sc_rfcr |= RFCR_AAP; 2838 goto allmulti; 2839 } 2840 2841 /* 2842 * Set up the multicast address filter by passing all multicast 2843 * addresses through a CRC generator, and then using the high-order 2844 * 6 bits as an index into the 128 bit multicast hash table (only 2845 * the lower 16 bits of each 32 bit multicast hash register are 2846 * valid). The high order bits select the register, while the 2847 * rest of the bits select the bit within the register. 2848 */ 2849 2850 memset(mchash, 0, sizeof(mchash)); 2851 2852 /* 2853 * SiS900 (at least SiS963) requires us to register the address of 2854 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2855 */ 2856 crc = 0x0ed423f9; 2857 2858 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2859 SIP_SIS900_REV(sc, SIS_REV_960) || 2860 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2861 /* Just want the 8 most significant bits. */ 2862 crc >>= 24; 2863 } else { 2864 /* Just want the 7 most significant bits. */ 2865 crc >>= 25; 2866 } 2867 2868 /* Set the corresponding bit in the hash table. */ 2869 mchash[crc >> 4] |= 1 << (crc & 0xf); 2870 2871 ETHER_FIRST_MULTI(step, ec, enm); 2872 while (enm != NULL) { 2873 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2874 /* 2875 * We must listen to a range of multicast addresses. 2876 * For now, just accept all multicasts, rather than 2877 * trying to set only those filter bits needed to match 2878 * the range. (At this time, the only use of address 2879 * ranges is for IP multicast routing, for which the 2880 * range is big enough to require all bits set.) 2881 */ 2882 goto allmulti; 2883 } 2884 2885 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2886 2887 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2888 SIP_SIS900_REV(sc, SIS_REV_960) || 2889 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2890 /* Just want the 8 most significant bits. */ 2891 crc >>= 24; 2892 } else { 2893 /* Just want the 7 most significant bits. */ 2894 crc >>= 25; 2895 } 2896 2897 /* Set the corresponding bit in the hash table. */ 2898 mchash[crc >> 4] |= 1 << (crc & 0xf); 2899 2900 ETHER_NEXT_MULTI(step, enm); 2901 } 2902 2903 ifp->if_flags &= ~IFF_ALLMULTI; 2904 goto setit; 2905 2906 allmulti: 2907 ifp->if_flags |= IFF_ALLMULTI; 2908 sc->sc_rfcr |= RFCR_AAM; 2909 2910 setit: 2911 #define FILTER_EMIT(addr, data) \ 2912 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2913 delay(1); \ 2914 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2915 delay(1) 2916 2917 /* 2918 * Disable receive filter, and program the node address. 2919 */ 2920 cp = LLADDR(ifp->if_sadl); 2921 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2922 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2923 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2924 2925 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2926 /* 2927 * Program the multicast hash table. 2928 */ 2929 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2930 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2931 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2932 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2933 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2934 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2935 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2936 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2937 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2938 SIP_SIS900_REV(sc, SIS_REV_960) || 2939 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2940 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2941 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2942 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2943 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2944 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2945 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2946 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2947 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2948 } 2949 } 2950 #undef FILTER_EMIT 2951 2952 /* 2953 * Re-enable the receiver filter. 2954 */ 2955 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2956 } 2957 #endif /* ! DP83820 */ 2958 2959 /* 2960 * sip_dp83815_set_filter: 2961 * 2962 * Set up the receive filter. 2963 */ 2964 static void 2965 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 2966 { 2967 bus_space_tag_t st = sc->sc_st; 2968 bus_space_handle_t sh = sc->sc_sh; 2969 struct ethercom *ec = &sc->sc_ethercom; 2970 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2971 struct ether_multi *enm; 2972 u_int8_t *cp; 2973 struct ether_multistep step; 2974 u_int32_t crc, hash, slot, bit; 2975 #ifdef DP83820 2976 #define MCHASH_NWORDS 128 2977 #else 2978 #define MCHASH_NWORDS 32 2979 #endif /* DP83820 */ 2980 u_int16_t mchash[MCHASH_NWORDS]; 2981 int i; 2982 2983 /* 2984 * Initialize the prototype RFCR. 2985 * Enable the receive filter, and accept on 2986 * Perfect (destination address) Match 2987 * If IFF_BROADCAST, also accept all broadcast packets. 2988 * If IFF_PROMISC, accept all unicast packets (and later, set 2989 * IFF_ALLMULTI and accept all multicast, too). 2990 */ 2991 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 2992 if (ifp->if_flags & IFF_BROADCAST) 2993 sc->sc_rfcr |= RFCR_AAB; 2994 if (ifp->if_flags & IFF_PROMISC) { 2995 sc->sc_rfcr |= RFCR_AAP; 2996 goto allmulti; 2997 } 2998 2999 #ifdef DP83820 3000 /* 3001 * Set up the DP83820 multicast address filter by passing all multicast 3002 * addresses through a CRC generator, and then using the high-order 3003 * 11 bits as an index into the 2048 bit multicast hash table. The 3004 * high-order 7 bits select the slot, while the low-order 4 bits 3005 * select the bit within the slot. Note that only the low 16-bits 3006 * of each filter word are used, and there are 128 filter words. 3007 */ 3008 #else 3009 /* 3010 * Set up the DP83815 multicast address filter by passing all multicast 3011 * addresses through a CRC generator, and then using the high-order 3012 * 9 bits as an index into the 512 bit multicast hash table. The 3013 * high-order 5 bits select the slot, while the low-order 4 bits 3014 * select the bit within the slot. Note that only the low 16-bits 3015 * of each filter word are used, and there are 32 filter words. 3016 */ 3017 #endif /* DP83820 */ 3018 3019 memset(mchash, 0, sizeof(mchash)); 3020 3021 ifp->if_flags &= ~IFF_ALLMULTI; 3022 ETHER_FIRST_MULTI(step, ec, enm); 3023 if (enm == NULL) 3024 goto setit; 3025 while (enm != NULL) { 3026 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3027 /* 3028 * We must listen to a range of multicast addresses. 3029 * For now, just accept all multicasts, rather than 3030 * trying to set only those filter bits needed to match 3031 * the range. (At this time, the only use of address 3032 * ranges is for IP multicast routing, for which the 3033 * range is big enough to require all bits set.) 3034 */ 3035 goto allmulti; 3036 } 3037 3038 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3039 3040 #ifdef DP83820 3041 /* Just want the 11 most significant bits. */ 3042 hash = crc >> 21; 3043 #else 3044 /* Just want the 9 most significant bits. */ 3045 hash = crc >> 23; 3046 #endif /* DP83820 */ 3047 3048 slot = hash >> 4; 3049 bit = hash & 0xf; 3050 3051 /* Set the corresponding bit in the hash table. */ 3052 mchash[slot] |= 1 << bit; 3053 3054 ETHER_NEXT_MULTI(step, enm); 3055 } 3056 sc->sc_rfcr |= RFCR_MHEN; 3057 goto setit; 3058 3059 allmulti: 3060 ifp->if_flags |= IFF_ALLMULTI; 3061 sc->sc_rfcr |= RFCR_AAM; 3062 3063 setit: 3064 #define FILTER_EMIT(addr, data) \ 3065 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3066 delay(1); \ 3067 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3068 delay(1) 3069 3070 /* 3071 * Disable receive filter, and program the node address. 3072 */ 3073 cp = LLADDR(ifp->if_sadl); 3074 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3075 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3076 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3077 3078 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3079 /* 3080 * Program the multicast hash table. 3081 */ 3082 for (i = 0; i < MCHASH_NWORDS; i++) { 3083 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3084 mchash[i]); 3085 } 3086 } 3087 #undef FILTER_EMIT 3088 #undef MCHASH_NWORDS 3089 3090 /* 3091 * Re-enable the receiver filter. 3092 */ 3093 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3094 } 3095 3096 #if defined(DP83820) 3097 /* 3098 * sip_dp83820_mii_readreg: [mii interface function] 3099 * 3100 * Read a PHY register on the MII of the DP83820. 3101 */ 3102 static int 3103 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3104 { 3105 struct sip_softc *sc = (void *) self; 3106 3107 if (sc->sc_cfg & CFG_TBI_EN) { 3108 bus_addr_t tbireg; 3109 int rv; 3110 3111 if (phy != 0) 3112 return (0); 3113 3114 switch (reg) { 3115 case MII_BMCR: tbireg = SIP_TBICR; break; 3116 case MII_BMSR: tbireg = SIP_TBISR; break; 3117 case MII_ANAR: tbireg = SIP_TANAR; break; 3118 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3119 case MII_ANER: tbireg = SIP_TANER; break; 3120 case MII_EXTSR: 3121 /* 3122 * Don't even bother reading the TESR register. 3123 * The manual documents that the device has 3124 * 1000baseX full/half capability, but the 3125 * register itself seems read back 0 on some 3126 * boards. Just hard-code the result. 3127 */ 3128 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3129 3130 default: 3131 return (0); 3132 } 3133 3134 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3135 if (tbireg == SIP_TBISR) { 3136 /* LINK and ACOMP are switched! */ 3137 int val = rv; 3138 3139 rv = 0; 3140 if (val & TBISR_MR_LINK_STATUS) 3141 rv |= BMSR_LINK; 3142 if (val & TBISR_MR_AN_COMPLETE) 3143 rv |= BMSR_ACOMP; 3144 3145 /* 3146 * The manual claims this register reads back 0 3147 * on hard and soft reset. But we want to let 3148 * the gentbi driver know that we support auto- 3149 * negotiation, so hard-code this bit in the 3150 * result. 3151 */ 3152 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3153 } 3154 3155 return (rv); 3156 } 3157 3158 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3159 phy, reg)); 3160 } 3161 3162 /* 3163 * sip_dp83820_mii_writereg: [mii interface function] 3164 * 3165 * Write a PHY register on the MII of the DP83820. 3166 */ 3167 static void 3168 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3169 { 3170 struct sip_softc *sc = (void *) self; 3171 3172 if (sc->sc_cfg & CFG_TBI_EN) { 3173 bus_addr_t tbireg; 3174 3175 if (phy != 0) 3176 return; 3177 3178 switch (reg) { 3179 case MII_BMCR: tbireg = SIP_TBICR; break; 3180 case MII_ANAR: tbireg = SIP_TANAR; break; 3181 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3182 default: 3183 return; 3184 } 3185 3186 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3187 return; 3188 } 3189 3190 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3191 phy, reg, val); 3192 } 3193 3194 /* 3195 * sip_dp83820_mii_statchg: [mii interface function] 3196 * 3197 * Callback from MII layer when media changes. 3198 */ 3199 static void 3200 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3201 { 3202 struct sip_softc *sc = (struct sip_softc *) self; 3203 struct mii_data *mii = &sc->sc_mii; 3204 u_int32_t cfg, pcr; 3205 3206 /* 3207 * Get flow control negotiation result. 3208 */ 3209 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3210 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3211 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3212 mii->mii_media_active &= ~IFM_ETH_FMASK; 3213 } 3214 3215 /* 3216 * Update TXCFG for full-duplex operation. 3217 */ 3218 if ((mii->mii_media_active & IFM_FDX) != 0) 3219 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3220 else 3221 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3222 3223 /* 3224 * Update RXCFG for full-duplex or loopback. 3225 */ 3226 if ((mii->mii_media_active & IFM_FDX) != 0 || 3227 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3228 sc->sc_rxcfg |= RXCFG_ATX; 3229 else 3230 sc->sc_rxcfg &= ~RXCFG_ATX; 3231 3232 /* 3233 * Update CFG for MII/GMII. 3234 */ 3235 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3236 cfg = sc->sc_cfg | CFG_MODE_1000; 3237 else 3238 cfg = sc->sc_cfg; 3239 3240 /* 3241 * 802.3x flow control. 3242 */ 3243 pcr = 0; 3244 if (sc->sc_flowflags & IFM_FLOW) { 3245 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3246 pcr |= sc->sc_rx_flow_thresh; 3247 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3248 pcr |= PCR_PSEN | PCR_PS_MCAST; 3249 } 3250 3251 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3252 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3253 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3254 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3255 } 3256 #endif /* ! DP83820 */ 3257 3258 /* 3259 * sip_mii_bitbang_read: [mii bit-bang interface function] 3260 * 3261 * Read the MII serial port for the MII bit-bang module. 3262 */ 3263 static u_int32_t 3264 SIP_DECL(mii_bitbang_read)(struct device *self) 3265 { 3266 struct sip_softc *sc = (void *) self; 3267 3268 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3269 } 3270 3271 /* 3272 * sip_mii_bitbang_write: [mii big-bang interface function] 3273 * 3274 * Write the MII serial port for the MII bit-bang module. 3275 */ 3276 static void 3277 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3278 { 3279 struct sip_softc *sc = (void *) self; 3280 3281 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3282 } 3283 3284 #ifndef DP83820 3285 /* 3286 * sip_sis900_mii_readreg: [mii interface function] 3287 * 3288 * Read a PHY register on the MII. 3289 */ 3290 static int 3291 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3292 { 3293 struct sip_softc *sc = (struct sip_softc *) self; 3294 u_int32_t enphy; 3295 3296 /* 3297 * The PHY of recent SiS chipsets is accessed through bitbang 3298 * operations. 3299 */ 3300 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3301 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3302 phy, reg)); 3303 3304 #ifndef SIS900_MII_RESTRICT 3305 /* 3306 * The SiS 900 has only an internal PHY on the MII. Only allow 3307 * MII address 0. 3308 */ 3309 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3310 return (0); 3311 #endif 3312 3313 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3314 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3315 ENPHY_RWCMD | ENPHY_ACCESS); 3316 do { 3317 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3318 } while (enphy & ENPHY_ACCESS); 3319 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3320 } 3321 3322 /* 3323 * sip_sis900_mii_writereg: [mii interface function] 3324 * 3325 * Write a PHY register on the MII. 3326 */ 3327 static void 3328 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3329 { 3330 struct sip_softc *sc = (struct sip_softc *) self; 3331 u_int32_t enphy; 3332 3333 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3334 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3335 phy, reg, val); 3336 return; 3337 } 3338 3339 #ifndef SIS900_MII_RESTRICT 3340 /* 3341 * The SiS 900 has only an internal PHY on the MII. Only allow 3342 * MII address 0. 3343 */ 3344 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3345 return; 3346 #endif 3347 3348 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3349 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3350 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3351 do { 3352 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3353 } while (enphy & ENPHY_ACCESS); 3354 } 3355 3356 /* 3357 * sip_sis900_mii_statchg: [mii interface function] 3358 * 3359 * Callback from MII layer when media changes. 3360 */ 3361 static void 3362 SIP_DECL(sis900_mii_statchg)(struct device *self) 3363 { 3364 struct sip_softc *sc = (struct sip_softc *) self; 3365 struct mii_data *mii = &sc->sc_mii; 3366 u_int32_t flowctl; 3367 3368 /* 3369 * Get flow control negotiation result. 3370 */ 3371 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3372 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3373 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3374 mii->mii_media_active &= ~IFM_ETH_FMASK; 3375 } 3376 3377 /* 3378 * Update TXCFG for full-duplex operation. 3379 */ 3380 if ((mii->mii_media_active & IFM_FDX) != 0) 3381 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3382 else 3383 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3384 3385 /* 3386 * Update RXCFG for full-duplex or loopback. 3387 */ 3388 if ((mii->mii_media_active & IFM_FDX) != 0 || 3389 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3390 sc->sc_rxcfg |= RXCFG_ATX; 3391 else 3392 sc->sc_rxcfg &= ~RXCFG_ATX; 3393 3394 /* 3395 * Update IMR for use of 802.3x flow control. 3396 */ 3397 if (sc->sc_flowflags & IFM_FLOW) { 3398 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3399 flowctl = FLOWCTL_FLOWEN; 3400 } else { 3401 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3402 flowctl = 0; 3403 } 3404 3405 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3406 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3407 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3408 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3409 } 3410 3411 /* 3412 * sip_dp83815_mii_readreg: [mii interface function] 3413 * 3414 * Read a PHY register on the MII. 3415 */ 3416 static int 3417 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3418 { 3419 struct sip_softc *sc = (struct sip_softc *) self; 3420 u_int32_t val; 3421 3422 /* 3423 * The DP83815 only has an internal PHY. Only allow 3424 * MII address 0. 3425 */ 3426 if (phy != 0) 3427 return (0); 3428 3429 /* 3430 * Apparently, after a reset, the DP83815 can take a while 3431 * to respond. During this recovery period, the BMSR returns 3432 * a value of 0. Catch this -- it's not supposed to happen 3433 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3434 * PHY to come back to life. 3435 * 3436 * This works out because the BMSR is the first register 3437 * read during the PHY probe process. 3438 */ 3439 do { 3440 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3441 } while (reg == MII_BMSR && val == 0); 3442 3443 return (val & 0xffff); 3444 } 3445 3446 /* 3447 * sip_dp83815_mii_writereg: [mii interface function] 3448 * 3449 * Write a PHY register to the MII. 3450 */ 3451 static void 3452 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3453 { 3454 struct sip_softc *sc = (struct sip_softc *) self; 3455 3456 /* 3457 * The DP83815 only has an internal PHY. Only allow 3458 * MII address 0. 3459 */ 3460 if (phy != 0) 3461 return; 3462 3463 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3464 } 3465 3466 /* 3467 * sip_dp83815_mii_statchg: [mii interface function] 3468 * 3469 * Callback from MII layer when media changes. 3470 */ 3471 static void 3472 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3473 { 3474 struct sip_softc *sc = (struct sip_softc *) self; 3475 3476 /* 3477 * Update TXCFG for full-duplex operation. 3478 */ 3479 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3480 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3481 else 3482 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3483 3484 /* 3485 * Update RXCFG for full-duplex or loopback. 3486 */ 3487 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3488 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3489 sc->sc_rxcfg |= RXCFG_ATX; 3490 else 3491 sc->sc_rxcfg &= ~RXCFG_ATX; 3492 3493 /* 3494 * XXX 802.3x flow control. 3495 */ 3496 3497 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3498 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3499 3500 /* 3501 * Some DP83815s experience problems when used with short 3502 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3503 * sequence adjusts the DSP's signal attenuation to fix the 3504 * problem. 3505 */ 3506 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3507 uint32_t reg; 3508 3509 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3510 3511 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3512 reg &= 0x0fff; 3513 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3514 delay(100); 3515 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3516 reg &= 0x00ff; 3517 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3518 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3519 0x00e8); 3520 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3521 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3522 reg | 0x20); 3523 } 3524 3525 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3526 } 3527 } 3528 #endif /* DP83820 */ 3529 3530 #if defined(DP83820) 3531 static void 3532 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3533 const struct pci_attach_args *pa, u_int8_t *enaddr) 3534 { 3535 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3536 u_int8_t cksum, *e, match; 3537 int i; 3538 3539 /* 3540 * EEPROM data format for the DP83820 can be found in 3541 * the DP83820 manual, section 4.2.4. 3542 */ 3543 3544 SIP_DECL(read_eeprom)(sc, 0, 3545 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3546 3547 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3548 match = ~(match - 1); 3549 3550 cksum = 0x55; 3551 e = (u_int8_t *) eeprom_data; 3552 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3553 cksum += *e++; 3554 3555 if (cksum != match) 3556 printf("%s: Checksum (%x) mismatch (%x)", 3557 sc->sc_dev.dv_xname, cksum, match); 3558 3559 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3560 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3561 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3562 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3563 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3564 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3565 } 3566 #else /* ! DP83820 */ 3567 static void 3568 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3569 { 3570 int i; 3571 3572 /* 3573 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3574 * a reason, but I don't know it. 3575 */ 3576 for (i = 0; i < 10; i++) 3577 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3578 } 3579 3580 static void 3581 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3582 const struct pci_attach_args *pa, u_int8_t *enaddr) 3583 { 3584 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3585 3586 switch (sc->sc_rev) { 3587 case SIS_REV_630S: 3588 case SIS_REV_630E: 3589 case SIS_REV_630EA1: 3590 case SIS_REV_630ET: 3591 case SIS_REV_635: 3592 /* 3593 * The MAC address for the on-board Ethernet of 3594 * the SiS 630 chipset is in the NVRAM. Kick 3595 * the chip into re-loading it from NVRAM, and 3596 * read the MAC address out of the filter registers. 3597 */ 3598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3599 3600 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3601 RFCR_RFADDR_NODE0); 3602 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3603 0xffff; 3604 3605 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3606 RFCR_RFADDR_NODE2); 3607 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3608 0xffff; 3609 3610 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3611 RFCR_RFADDR_NODE4); 3612 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3613 0xffff; 3614 break; 3615 3616 case SIS_REV_960: 3617 { 3618 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3619 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3620 3621 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3622 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3623 3624 int waittime, i; 3625 3626 /* Allow to read EEPROM from LAN. It is shared 3627 * between a 1394 controller and the NIC and each 3628 * time we access it, we need to set SIS_EECMD_REQ. 3629 */ 3630 SIS_SET_EROMAR(sc, EROMAR_REQ); 3631 3632 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3633 /* Force EEPROM to idle state. */ 3634 3635 /* 3636 * XXX-cube This is ugly. I'll look for docs about it. 3637 */ 3638 SIS_SET_EROMAR(sc, EROMAR_EECS); 3639 SIP_DECL(sis900_eeprom_delay)(sc); 3640 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3641 SIS_SET_EROMAR(sc, EROMAR_EESK); 3642 SIP_DECL(sis900_eeprom_delay)(sc); 3643 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3644 SIP_DECL(sis900_eeprom_delay)(sc); 3645 } 3646 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3647 SIP_DECL(sis900_eeprom_delay)(sc); 3648 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3649 3650 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3651 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3652 sizeof(myea) / sizeof(myea[0]), myea); 3653 break; 3654 } 3655 DELAY(1); 3656 } 3657 3658 /* 3659 * Set SIS_EECTL_CLK to high, so a other master 3660 * can operate on the i2c bus. 3661 */ 3662 SIS_SET_EROMAR(sc, EROMAR_EESK); 3663 3664 /* Refuse EEPROM access by LAN */ 3665 SIS_SET_EROMAR(sc, EROMAR_DONE); 3666 } break; 3667 3668 default: 3669 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3670 sizeof(myea) / sizeof(myea[0]), myea); 3671 } 3672 3673 enaddr[0] = myea[0] & 0xff; 3674 enaddr[1] = myea[0] >> 8; 3675 enaddr[2] = myea[1] & 0xff; 3676 enaddr[3] = myea[1] >> 8; 3677 enaddr[4] = myea[2] & 0xff; 3678 enaddr[5] = myea[2] >> 8; 3679 } 3680 3681 /* Table and macro to bit-reverse an octet. */ 3682 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3683 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3684 3685 static void 3686 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3687 const struct pci_attach_args *pa, u_int8_t *enaddr) 3688 { 3689 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3690 u_int8_t cksum, *e, match; 3691 int i; 3692 3693 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3694 sizeof(eeprom_data[0]), eeprom_data); 3695 3696 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3697 match = ~(match - 1); 3698 3699 cksum = 0x55; 3700 e = (u_int8_t *) eeprom_data; 3701 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3702 cksum += *e++; 3703 } 3704 if (cksum != match) { 3705 printf("%s: Checksum (%x) mismatch (%x)", 3706 sc->sc_dev.dv_xname, cksum, match); 3707 } 3708 3709 /* 3710 * Unrolled because it makes slightly more sense this way. 3711 * The DP83815 stores the MAC address in bit 0 of word 6 3712 * through bit 15 of word 8. 3713 */ 3714 ea = &eeprom_data[6]; 3715 enaddr[0] = ((*ea & 0x1) << 7); 3716 ea++; 3717 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3718 enaddr[1] = ((*ea & 0x1FE) >> 1); 3719 enaddr[2] = ((*ea & 0x1) << 7); 3720 ea++; 3721 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3722 enaddr[3] = ((*ea & 0x1FE) >> 1); 3723 enaddr[4] = ((*ea & 0x1) << 7); 3724 ea++; 3725 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3726 enaddr[5] = ((*ea & 0x1FE) >> 1); 3727 3728 /* 3729 * In case that's not weird enough, we also need to reverse 3730 * the bits in each byte. This all actually makes more sense 3731 * if you think about the EEPROM storage as an array of bits 3732 * being shifted into bytes, but that's not how we're looking 3733 * at it here... 3734 */ 3735 for (i = 0; i < 6 ;i++) 3736 enaddr[i] = bbr(enaddr[i]); 3737 } 3738 #endif /* DP83820 */ 3739 3740 /* 3741 * sip_mediastatus: [ifmedia interface function] 3742 * 3743 * Get the current interface media status. 3744 */ 3745 static void 3746 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3747 { 3748 struct sip_softc *sc = ifp->if_softc; 3749 3750 mii_pollstat(&sc->sc_mii); 3751 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3752 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3753 sc->sc_flowflags; 3754 } 3755 3756 /* 3757 * sip_mediachange: [ifmedia interface function] 3758 * 3759 * Set hardware to newly-selected media. 3760 */ 3761 static int 3762 SIP_DECL(mediachange)(struct ifnet *ifp) 3763 { 3764 struct sip_softc *sc = ifp->if_softc; 3765 3766 if (ifp->if_flags & IFF_UP) 3767 mii_mediachg(&sc->sc_mii); 3768 return (0); 3769 } 3770
Indexes created Mon Sep 22 13:09:51 GMT 2025