if_sip.c revision 1.115.2.1
1 /* $NetBSD: if_sip.c,v 1.115.2.1 2008/02/18 21:05:57 mjf Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.115.2.1 2008/02/18 21:05:57 mjf Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 #define SIP_STR(x) __STRING(SIP_DECL(x)) 136 137 /* 138 * Transmit descriptor list size. This is arbitrary, but allocate 139 * enough descriptors for 128 pending transmissions, and 8 segments 140 * per packet (64 for DP83820 for jumbo frames). 141 * 142 * This MUST work out to a power of 2. 143 */ 144 #ifdef DP83820 145 #define SIP_NTXSEGS 64 146 #define SIP_NTXSEGS_ALLOC 16 147 #else 148 #define SIP_NTXSEGS 16 149 #define SIP_NTXSEGS_ALLOC 8 150 #endif 151 152 #define SIP_TXQUEUELEN 256 153 #define SIP_NTXDESC (SIP_TXQUEUELEN * SIP_NTXSEGS_ALLOC) 154 #define SIP_NTXDESC_MASK (SIP_NTXDESC - 1) 155 #define SIP_NEXTTX(x) (((x) + 1) & SIP_NTXDESC_MASK) 156 157 #if defined(DP83820) 158 #define TX_DMAMAP_SIZE ETHER_MAX_LEN_JUMBO 159 #else 160 #define TX_DMAMAP_SIZE MCLBYTES 161 #endif 162 163 /* 164 * Receive descriptor list size. We have one Rx buffer per incoming 165 * packet, so this logic is a little simpler. 166 * 167 * Actually, on the DP83820, we allow the packet to consume more than 168 * one buffer, in order to support jumbo Ethernet frames. In that 169 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 170 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 171 * so we'd better be quick about handling receive interrupts. 172 */ 173 #if defined(DP83820) 174 #define SIP_NRXDESC 256 175 #else 176 #define SIP_NRXDESC 128 177 #endif /* DP83820 */ 178 #define SIP_NRXDESC_MASK (SIP_NRXDESC - 1) 179 #define SIP_NEXTRX(x) (((x) + 1) & SIP_NRXDESC_MASK) 180 181 /* 182 * Control structures are DMA'd to the SiS900 chip. We allocate them in 183 * a single clump that maps to a single DMA segment to make several things 184 * easier. 185 */ 186 struct sip_control_data { 187 /* 188 * The transmit descriptors. 189 */ 190 struct sip_desc scd_txdescs[SIP_NTXDESC]; 191 192 /* 193 * The receive descriptors. 194 */ 195 struct sip_desc scd_rxdescs[SIP_NRXDESC]; 196 }; 197 198 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 199 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 200 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 201 202 /* 203 * Software state for transmit jobs. 204 */ 205 struct sip_txsoft { 206 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 207 bus_dmamap_t txs_dmamap; /* our DMA map */ 208 int txs_firstdesc; /* first descriptor in packet */ 209 int txs_lastdesc; /* last descriptor in packet */ 210 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 211 }; 212 213 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 214 215 /* 216 * Software state for receive jobs. 217 */ 218 struct sip_rxsoft { 219 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 220 bus_dmamap_t rxs_dmamap; /* our DMA map */ 221 }; 222 223 /* 224 * Software state per device. 225 */ 226 struct sip_softc { 227 struct device sc_dev; /* generic device information */ 228 bus_space_tag_t sc_st; /* bus space tag */ 229 bus_space_handle_t sc_sh; /* bus space handle */ 230 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 231 struct ethercom sc_ethercom; /* ethernet common data */ 232 233 const struct sip_product *sc_model; /* which model are we? */ 234 int sc_rev; /* chip revision */ 235 236 void *sc_ih; /* interrupt cookie */ 237 238 struct mii_data sc_mii; /* MII/media information */ 239 240 callout_t sc_tick_ch; /* tick callout */ 241 242 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 243 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 244 245 /* 246 * Software state for transmit and receive descriptors. 247 */ 248 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 249 struct sip_rxsoft sc_rxsoft[SIP_NRXDESC]; 250 251 /* 252 * Control data structures. 253 */ 254 struct sip_control_data *sc_control_data; 255 #define sc_txdescs sc_control_data->scd_txdescs 256 #define sc_rxdescs sc_control_data->scd_rxdescs 257 258 #ifdef SIP_EVENT_COUNTERS 259 /* 260 * Event counters. 261 */ 262 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 263 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 264 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 265 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 266 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 267 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 268 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 269 struct evcnt sc_ev_rxpause; /* PAUSE received */ 270 #ifdef DP83820 271 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 272 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 273 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 274 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 275 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 276 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 277 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 278 #endif /* DP83820 */ 279 #endif /* SIP_EVENT_COUNTERS */ 280 281 u_int32_t sc_txcfg; /* prototype TXCFG register */ 282 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 283 u_int32_t sc_imr; /* prototype IMR register */ 284 u_int32_t sc_rfcr; /* prototype RFCR register */ 285 286 u_int32_t sc_cfg; /* prototype CFG register */ 287 288 #ifdef DP83820 289 u_int32_t sc_gpior; /* prototype GPIOR register */ 290 #endif /* DP83820 */ 291 292 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 293 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 294 295 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 296 297 int sc_flowflags; /* 802.3x flow control flags */ 298 #ifdef DP83820 299 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 300 #else 301 int sc_paused; /* paused indication */ 302 #endif 303 304 int sc_txfree; /* number of free Tx descriptors */ 305 int sc_txnext; /* next ready Tx descriptor */ 306 int sc_txwin; /* Tx descriptors since last intr */ 307 308 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 309 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 310 311 /* values of interface state at last init */ 312 struct { 313 /* if_capenable */ 314 uint64_t if_capenable; 315 /* ec_capenable */ 316 int ec_capenable; 317 /* VLAN_ATTACHED */ 318 int is_vlan; 319 } sc_prev; 320 321 short sc_if_flags; 322 323 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 324 #if defined(DP83820) 325 int sc_rxdiscard; 326 int sc_rxlen; 327 struct mbuf *sc_rxhead; 328 struct mbuf *sc_rxtail; 329 struct mbuf **sc_rxtailp; 330 #endif /* DP83820 */ 331 332 #if NRND > 0 333 rndsource_element_t rnd_source; /* random source */ 334 #endif 335 }; 336 337 #ifdef DP83820 338 #define SIP_RXCHAIN_RESET(sc) \ 339 do { \ 340 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 341 *(sc)->sc_rxtailp = NULL; \ 342 (sc)->sc_rxlen = 0; \ 343 } while (/*CONSTCOND*/0) 344 345 #define SIP_RXCHAIN_LINK(sc, m) \ 346 do { \ 347 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 348 (sc)->sc_rxtailp = &(m)->m_next; \ 349 } while (/*CONSTCOND*/0) 350 #endif /* DP83820 */ 351 352 #ifdef SIP_EVENT_COUNTERS 353 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 354 #else 355 #define SIP_EVCNT_INCR(ev) /* nothing */ 356 #endif 357 358 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 359 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 360 361 #define SIP_CDTXSYNC(sc, x, n, ops) \ 362 do { \ 363 int __x, __n; \ 364 \ 365 __x = (x); \ 366 __n = (n); \ 367 \ 368 /* If it will wrap around, sync to the end of the ring. */ \ 369 if ((__x + __n) > SIP_NTXDESC) { \ 370 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 371 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 372 (SIP_NTXDESC - __x), (ops)); \ 373 __n -= (SIP_NTXDESC - __x); \ 374 __x = 0; \ 375 } \ 376 \ 377 /* Now sync whatever is left. */ \ 378 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 379 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 380 } while (0) 381 382 #define SIP_CDRXSYNC(sc, x, ops) \ 383 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 384 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 385 386 #ifdef DP83820 387 #define SIP_INIT_RXDESC_EXTSTS __sipd->sipd_extsts = 0; 388 #define SIP_RXBUF_LEN (MCLBYTES - 8) 389 #else 390 #define SIP_INIT_RXDESC_EXTSTS /* nothing */ 391 #define SIP_RXBUF_LEN (MCLBYTES - 1) /* field width */ 392 #endif 393 #define SIP_INIT_RXDESC(sc, x) \ 394 do { \ 395 struct sip_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \ 396 struct sip_desc *__sipd = &(sc)->sc_rxdescs[(x)]; \ 397 \ 398 __sipd->sipd_link = \ 399 htole32(SIP_CDRXADDR((sc), SIP_NEXTRX((x)))); \ 400 __sipd->sipd_bufptr = \ 401 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 402 __sipd->sipd_cmdsts = htole32(CMDSTS_INTR | \ 403 (SIP_RXBUF_LEN & CMDSTS_SIZE_MASK)); \ 404 SIP_INIT_RXDESC_EXTSTS \ 405 SIP_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 406 } while (0) 407 408 #define SIP_CHIP_VERS(sc, v, p, r) \ 409 ((sc)->sc_model->sip_vendor == (v) && \ 410 (sc)->sc_model->sip_product == (p) && \ 411 (sc)->sc_rev == (r)) 412 413 #define SIP_CHIP_MODEL(sc, v, p) \ 414 ((sc)->sc_model->sip_vendor == (v) && \ 415 (sc)->sc_model->sip_product == (p)) 416 417 #if !defined(DP83820) 418 #define SIP_SIS900_REV(sc, rev) \ 419 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 420 #endif 421 422 #define SIP_TIMEOUT 1000 423 424 static void sipcom_start(struct ifnet *); 425 static void sipcom_watchdog(struct ifnet *); 426 static int sipcom_ioctl(struct ifnet *, u_long, void *); 427 static int sipcom_init(struct ifnet *); 428 static void sipcom_stop(struct ifnet *, int); 429 430 static bool sipcom_reset(struct sip_softc *); 431 static void sipcom_rxdrain(struct sip_softc *); 432 static int sipcom_add_rxbuf(struct sip_softc *, int); 433 static void sipcom_read_eeprom(struct sip_softc *, int, int, 434 u_int16_t *); 435 static void SIP_DECL(tick)(void *); 436 437 #if !defined(DP83820) 438 static void SIP_DECL(sis900_set_filter)(struct sip_softc *); 439 #endif /* ! DP83820 */ 440 static void SIP_DECL(dp83815_set_filter)(struct sip_softc *); 441 442 #if defined(DP83820) 443 static void SIP_DECL(dp83820_read_macaddr)(struct sip_softc *, 444 const struct pci_attach_args *, u_int8_t *); 445 #else 446 static void SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc); 447 static void SIP_DECL(sis900_read_macaddr)(struct sip_softc *, 448 const struct pci_attach_args *, u_int8_t *); 449 static void SIP_DECL(dp83815_read_macaddr)(struct sip_softc *, 450 const struct pci_attach_args *, u_int8_t *); 451 #endif /* DP83820 */ 452 453 static int sipcom_intr(void *); 454 static void sipcom_txintr(struct sip_softc *); 455 static void sip_rxintr(struct sip_softc *); 456 static void gsip_rxintr(struct sip_softc *); 457 458 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 459 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 460 static void sipcom_dp83820_mii_statchg(struct device *); 461 462 static int sipcom_sis900_mii_readreg(struct device *, int, int); 463 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 464 static void sipcom_sis900_mii_statchg(struct device *); 465 466 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 467 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 468 static void sipcom_dp83815_mii_statchg(struct device *); 469 470 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 471 472 static int sipcom_match(struct device *, struct cfdata *, void *); 473 static void sipcom_attach(struct device *, struct device *, void *); 474 static void sipcom_do_detach(device_t, enum sip_attach_stage); 475 static int sipcom_detach(device_t, int); 476 static bool sipcom_resume(device_t); 477 478 int SIP_DECL(copy_small) = 0; 479 480 #ifdef DP83820 481 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 482 gsip_match, gsip_attach, NULL, NULL); 483 #else 484 CFATTACH_DECL(sip, sizeof(struct sip_softc), 485 sip_match, sip_attach, NULL, NULL); 486 #endif 487 488 /* 489 * Descriptions of the variants of the SiS900. 490 */ 491 struct sip_variant { 492 int (*sipv_mii_readreg)(struct device *, int, int); 493 void (*sipv_mii_writereg)(struct device *, int, int, int); 494 void (*sipv_mii_statchg)(struct device *); 495 void (*sipv_set_filter)(struct sip_softc *); 496 void (*sipv_read_macaddr)(struct sip_softc *, 497 const struct pci_attach_args *, u_int8_t *); 498 }; 499 500 static u_int32_t SIP_DECL(mii_bitbang_read)(struct device *); 501 static void SIP_DECL(mii_bitbang_write)(struct device *, u_int32_t); 502 503 static const struct mii_bitbang_ops SIP_DECL(mii_bitbang_ops) = { 504 SIP_DECL(mii_bitbang_read), 505 SIP_DECL(mii_bitbang_write), 506 { 507 EROMAR_MDIO, /* MII_BIT_MDO */ 508 EROMAR_MDIO, /* MII_BIT_MDI */ 509 EROMAR_MDC, /* MII_BIT_MDC */ 510 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 511 0, /* MII_BIT_DIR_PHY_HOST */ 512 } 513 }; 514 515 #if defined(DP83820) 516 static const struct sip_variant SIP_DECL(variant_dp83820) = { 517 SIP_DECL(dp83820_mii_readreg), 518 SIP_DECL(dp83820_mii_writereg), 519 SIP_DECL(dp83820_mii_statchg), 520 SIP_DECL(dp83815_set_filter), 521 SIP_DECL(dp83820_read_macaddr), 522 }; 523 #else 524 static const struct sip_variant SIP_DECL(variant_sis900) = { 525 SIP_DECL(sis900_mii_readreg), 526 SIP_DECL(sis900_mii_writereg), 527 SIP_DECL(sis900_mii_statchg), 528 SIP_DECL(sis900_set_filter), 529 SIP_DECL(sis900_read_macaddr), 530 }; 531 532 static const struct sip_variant SIP_DECL(variant_dp83815) = { 533 SIP_DECL(dp83815_mii_readreg), 534 SIP_DECL(dp83815_mii_writereg), 535 SIP_DECL(dp83815_mii_statchg), 536 SIP_DECL(dp83815_set_filter), 537 SIP_DECL(dp83815_read_macaddr), 538 }; 539 #endif /* DP83820 */ 540 541 /* 542 * Devices supported by this driver. 543 */ 544 static const struct sip_product { 545 pci_vendor_id_t sip_vendor; 546 pci_product_id_t sip_product; 547 const char *sip_name; 548 const struct sip_variant *sip_variant; 549 } SIP_DECL(products)[] = { 550 #if defined(DP83820) 551 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 552 "NatSemi DP83820 Gigabit Ethernet", 553 &SIP_DECL(variant_dp83820) }, 554 #else 555 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 556 "SiS 900 10/100 Ethernet", 557 &SIP_DECL(variant_sis900) }, 558 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 559 "SiS 7016 10/100 Ethernet", 560 &SIP_DECL(variant_sis900) }, 561 562 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 563 "NatSemi DP83815 10/100 Ethernet", 564 &SIP_DECL(variant_dp83815) }, 565 #endif /* DP83820 */ 566 567 { 0, 0, 568 NULL, 569 NULL }, 570 }; 571 572 static const struct sip_product * 573 SIP_DECL(lookup)(const struct pci_attach_args *pa) 574 { 575 const struct sip_product *sip; 576 577 for (sip = SIP_DECL(products); sip->sip_name != NULL; sip++) { 578 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 579 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 580 return (sip); 581 } 582 return (NULL); 583 } 584 585 #ifdef DP83820 586 /* 587 * I really hate stupid hardware vendors. There's a bit in the EEPROM 588 * which indicates if the card can do 64-bit data transfers. Unfortunately, 589 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 590 * which means we try to use 64-bit data transfers on those cards if we 591 * happen to be plugged into a 32-bit slot. 592 * 593 * What we do is use this table of cards known to be 64-bit cards. If 594 * you have a 64-bit card who's subsystem ID is not listed in this table, 595 * send the output of "pcictl dump ..." of the device to me so that your 596 * card will use the 64-bit data path when plugged into a 64-bit slot. 597 * 598 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 599 * June 30, 2002 600 */ 601 static int 602 SIP_DECL(check_64bit)(const struct pci_attach_args *pa) 603 { 604 static const struct { 605 pci_vendor_id_t c64_vendor; 606 pci_product_id_t c64_product; 607 } card64[] = { 608 /* Asante GigaNIX */ 609 { 0x128a, 0x0002 }, 610 611 /* Accton EN1407-T, Planex GN-1000TE */ 612 { 0x1113, 0x1407 }, 613 614 /* Netgear GA-621 */ 615 { 0x1385, 0x621a }, 616 617 /* SMC EZ Card */ 618 { 0x10b8, 0x9462 }, 619 620 { 0, 0} 621 }; 622 pcireg_t subsys; 623 int i; 624 625 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 626 627 for (i = 0; card64[i].c64_vendor != 0; i++) { 628 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 629 PCI_PRODUCT(subsys) == card64[i].c64_product) 630 return (1); 631 } 632 633 return (0); 634 } 635 #endif /* DP83820 */ 636 637 static int 638 SIP_DECL(match)(struct device *parent, struct cfdata *cf, 639 void *aux) 640 { 641 struct pci_attach_args *pa = aux; 642 643 if (SIP_DECL(lookup)(pa) != NULL) 644 return (1); 645 646 return 0; 647 } 648 649 static void 650 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 651 { 652 u_int32_t reg; 653 int i; 654 655 /* 656 * Cause the chip to load configuration data from the EEPROM. 657 */ 658 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 659 for (i = 0; i < 10000; i++) { 660 delay(10); 661 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 662 PTSCR_EELOAD_EN) == 0) 663 break; 664 } 665 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 666 PTSCR_EELOAD_EN) { 667 printf("%s: timeout loading configuration from EEPROM\n", 668 sc->sc_dev.dv_xname); 669 return; 670 } 671 672 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 673 674 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 675 if (reg & CFG_PCI64_DET) { 676 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 677 /* 678 * Check to see if this card is 64-bit. If so, enable 64-bit 679 * data transfers. 680 * 681 * We can't use the DATA64_EN bit in the EEPROM, because 682 * vendors of 32-bit cards fail to clear that bit in many 683 * cases (yet the card still detects that it's in a 64-bit 684 * slot; go figure). 685 */ 686 if (sipcom_check_64bit(pa)) { 687 sc->sc_cfg |= CFG_DATA64_EN; 688 printf(", using 64-bit data transfers"); 689 } 690 printf("\n"); 691 } 692 693 /* 694 * XXX Need some PCI flags indicating support for 695 * XXX 64-bit addressing. 696 */ 697 #if 0 698 if (reg & CFG_M64ADDR) 699 sc->sc_cfg |= CFG_M64ADDR; 700 if (reg & CFG_T64ADDR) 701 sc->sc_cfg |= CFG_T64ADDR; 702 #endif 703 704 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 705 const char *sep = ""; 706 printf("%s: using ", sc->sc_dev.dv_xname); 707 if (reg & CFG_EXT_125) { 708 sc->sc_cfg |= CFG_EXT_125; 709 printf("%s125MHz clock", sep); 710 sep = ", "; 711 } 712 if (reg & CFG_TBI_EN) { 713 sc->sc_cfg |= CFG_TBI_EN; 714 printf("%sten-bit interface", sep); 715 sep = ", "; 716 } 717 printf("\n"); 718 } 719 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 720 (reg & CFG_MRM_DIS) != 0) 721 sc->sc_cfg |= CFG_MRM_DIS; 722 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 723 (reg & CFG_MWI_DIS) != 0) 724 sc->sc_cfg |= CFG_MWI_DIS; 725 726 /* 727 * Use the extended descriptor format on the DP83820. This 728 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 729 * checksumming. 730 */ 731 sc->sc_cfg |= CFG_EXTSTS_EN; 732 } 733 734 static int 735 sipcom_detach(device_t self, int flags) 736 { 737 int s; 738 739 s = splnet(); 740 sipcom_do_detach(self, SIP_ATTACH_FIN); 741 splx(s); 742 743 return 0; 744 } 745 746 static void 747 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 748 { 749 int i; 750 struct sip_softc *sc = device_private(self); 751 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 752 753 /* 754 * Free any resources we've allocated during attach. 755 * Do this in reverse order and fall through. 756 */ 757 switch (stage) { 758 case SIP_ATTACH_FIN: 759 sipcom_stop(ifp, 1); 760 pmf_device_deregister(self); 761 #ifdef SIP_EVENT_COUNTERS 762 /* 763 * Attach event counters. 764 */ 765 evcnt_detach(&sc->sc_ev_txforceintr); 766 evcnt_detach(&sc->sc_ev_txdstall); 767 evcnt_detach(&sc->sc_ev_txsstall); 768 evcnt_detach(&sc->sc_ev_hiberr); 769 evcnt_detach(&sc->sc_ev_rxintr); 770 evcnt_detach(&sc->sc_ev_txiintr); 771 evcnt_detach(&sc->sc_ev_txdintr); 772 if (!sc->sc_gigabit) { 773 evcnt_detach(&sc->sc_ev_rxpause); 774 } else { 775 evcnt_detach(&sc->sc_ev_txudpsum); 776 evcnt_detach(&sc->sc_ev_txtcpsum); 777 evcnt_detach(&sc->sc_ev_txipsum); 778 evcnt_detach(&sc->sc_ev_rxudpsum); 779 evcnt_detach(&sc->sc_ev_rxtcpsum); 780 evcnt_detach(&sc->sc_ev_rxipsum); 781 evcnt_detach(&sc->sc_ev_txpause); 782 evcnt_detach(&sc->sc_ev_rxpause); 783 } 784 #endif /* SIP_EVENT_COUNTERS */ 785 786 #if NRND > 0 787 rnd_detach_source(&sc->rnd_source); 788 #endif 789 790 ether_ifdetach(ifp); 791 if_detach(ifp); 792 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 793 794 /*FALLTHROUGH*/ 795 case SIP_ATTACH_CREATE_RXMAP: 796 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 797 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 798 bus_dmamap_destroy(sc->sc_dmat, 799 sc->sc_rxsoft[i].rxs_dmamap); 800 } 801 /*FALLTHROUGH*/ 802 case SIP_ATTACH_CREATE_TXMAP: 803 for (i = 0; i < SIP_TXQUEUELEN; i++) { 804 if (sc->sc_txsoft[i].txs_dmamap != NULL) 805 bus_dmamap_destroy(sc->sc_dmat, 806 sc->sc_txsoft[i].txs_dmamap); 807 } 808 /*FALLTHROUGH*/ 809 case SIP_ATTACH_LOAD_MAP: 810 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 811 /*FALLTHROUGH*/ 812 case SIP_ATTACH_CREATE_MAP: 813 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 814 /*FALLTHROUGH*/ 815 case SIP_ATTACH_MAP_MEM: 816 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 817 sizeof(struct sip_control_data)); 818 /*FALLTHROUGH*/ 819 case SIP_ATTACH_ALLOC_MEM: 820 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 821 /* FALLTHROUGH*/ 822 case SIP_ATTACH_INTR: 823 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 824 /* FALLTHROUGH*/ 825 case SIP_ATTACH_MAP: 826 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 827 break; 828 default: 829 break; 830 } 831 return; 832 } 833 834 static bool 835 sipcom_resume(device_t self) 836 { 837 struct sip_softc *sc = device_private(self); 838 839 return sipcom_reset(sc); 840 } 841 842 static void 843 SIP_DECL(attach)(struct device *parent, struct device *self, void *aux) 844 { 845 struct sip_softc *sc = (struct sip_softc *) self; 846 struct pci_attach_args *pa = aux; 847 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 848 pci_chipset_tag_t pc = pa->pa_pc; 849 pci_intr_handle_t ih; 850 const char *intrstr = NULL; 851 bus_space_tag_t iot, memt; 852 bus_space_handle_t ioh, memh; 853 bus_dma_segment_t seg; 854 int ioh_valid, memh_valid; 855 int i, rseg, error; 856 const struct sip_product *sip; 857 u_int8_t enaddr[ETHER_ADDR_LEN]; 858 pcireg_t pmreg; 859 #ifdef DP83820 860 pcireg_t memtype; 861 u_int32_t reg; 862 #endif /* DP83820 */ 863 864 callout_init(&sc->sc_tick_ch, 0); 865 866 sip = SIP_DECL(lookup)(pa); 867 if (sip == NULL) { 868 printf("\n"); 869 panic(SIP_STR(attach) ": impossible"); 870 } 871 sc->sc_rev = PCI_REVISION(pa->pa_class); 872 873 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 874 875 sc->sc_model = sip; 876 877 /* 878 * XXX Work-around broken PXE firmware on some boards. 879 * 880 * The DP83815 shares an address decoder with the MEM BAR 881 * and the ROM BAR. Make sure the ROM BAR is disabled, 882 * so that memory mapped access works. 883 */ 884 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 885 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 886 ~PCI_MAPREG_ROM_ENABLE); 887 888 /* 889 * Map the device. 890 */ 891 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 892 PCI_MAPREG_TYPE_IO, 0, 893 &iot, &ioh, NULL, NULL) == 0); 894 #ifdef DP83820 895 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 896 switch (memtype) { 897 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 898 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 899 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 900 memtype, 0, &memt, &memh, NULL, NULL) == 0); 901 break; 902 default: 903 memh_valid = 0; 904 } 905 #else 906 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 907 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 908 &memt, &memh, NULL, NULL) == 0); 909 #endif /* DP83820 */ 910 911 if (memh_valid) { 912 sc->sc_st = memt; 913 sc->sc_sh = memh; 914 } else if (ioh_valid) { 915 sc->sc_st = iot; 916 sc->sc_sh = ioh; 917 } else { 918 printf("%s: unable to map device registers\n", 919 sc->sc_dev.dv_xname); 920 return; 921 } 922 923 sc->sc_dmat = pa->pa_dmat; 924 925 /* 926 * Make sure bus mastering is enabled. Also make sure 927 * Write/Invalidate is enabled if we're allowed to use it. 928 */ 929 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 930 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 931 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 932 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 933 pmreg | PCI_COMMAND_MASTER_ENABLE); 934 935 /* power up chip */ 936 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 937 NULL)) && error != EOPNOTSUPP) { 938 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 939 error); 940 return; 941 } 942 943 /* 944 * Map and establish our interrupt. 945 */ 946 if (pci_intr_map(pa, &ih)) { 947 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 948 return; 949 } 950 intrstr = pci_intr_string(pc, ih); 951 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, SIP_DECL(intr), sc); 952 if (sc->sc_ih == NULL) { 953 printf("%s: unable to establish interrupt", 954 sc->sc_dev.dv_xname); 955 if (intrstr != NULL) 956 printf(" at %s", intrstr); 957 printf("\n"); 958 return; 959 } 960 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 961 962 SIMPLEQ_INIT(&sc->sc_txfreeq); 963 SIMPLEQ_INIT(&sc->sc_txdirtyq); 964 965 /* 966 * Allocate the control data structures, and create and load the 967 * DMA map for it. 968 */ 969 if ((error = bus_dmamem_alloc(sc->sc_dmat, 970 sizeof(struct sip_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 971 0)) != 0) { 972 printf("%s: unable to allocate control data, error = %d\n", 973 sc->sc_dev.dv_xname, error); 974 goto fail_0; 975 } 976 977 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 978 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 979 BUS_DMA_COHERENT)) != 0) { 980 printf("%s: unable to map control data, error = %d\n", 981 sc->sc_dev.dv_xname, error); 982 goto fail_1; 983 } 984 985 if ((error = bus_dmamap_create(sc->sc_dmat, 986 sizeof(struct sip_control_data), 1, 987 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 988 printf("%s: unable to create control data DMA map, " 989 "error = %d\n", sc->sc_dev.dv_xname, error); 990 goto fail_2; 991 } 992 993 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 994 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 995 0)) != 0) { 996 printf("%s: unable to load control data DMA map, error = %d\n", 997 sc->sc_dev.dv_xname, error); 998 goto fail_3; 999 } 1000 1001 /* 1002 * Create the transmit buffer DMA maps. 1003 */ 1004 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1005 if ((error = bus_dmamap_create(sc->sc_dmat, TX_DMAMAP_SIZE, 1006 SIP_NTXSEGS, MCLBYTES, 0, 0, 1007 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1008 printf("%s: unable to create tx DMA map %d, " 1009 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1010 goto fail_4; 1011 } 1012 } 1013 1014 /* 1015 * Create the receive buffer DMA maps. 1016 */ 1017 for (i = 0; i < SIP_NRXDESC; i++) { 1018 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1019 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1020 printf("%s: unable to create rx DMA map %d, " 1021 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1022 goto fail_5; 1023 } 1024 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1025 } 1026 1027 /* 1028 * Reset the chip to a known state. 1029 */ 1030 SIP_DECL(reset)(sc); 1031 1032 /* 1033 * Read the Ethernet address from the EEPROM. This might 1034 * also fetch other stuff from the EEPROM and stash it 1035 * in the softc. 1036 */ 1037 sc->sc_cfg = 0; 1038 #if !defined(DP83820) 1039 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1040 SIP_SIS900_REV(sc,SIS_REV_900B)) 1041 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1042 1043 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1044 SIP_SIS900_REV(sc,SIS_REV_960) || 1045 SIP_SIS900_REV(sc,SIS_REV_900B)) 1046 sc->sc_cfg |= (bus_space_read_4(sc->sc_st, sc->sc_sh, 1047 SIP_CFG) & CFG_EDBMASTEN); 1048 #endif 1049 1050 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1051 1052 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1053 ether_sprintf(enaddr)); 1054 1055 /* 1056 * Initialize the configuration register: aggressive PCI 1057 * bus request algorithm, default backoff, default OW timer, 1058 * default parity error detection. 1059 * 1060 * NOTE: "Big endian mode" is useless on the SiS900 and 1061 * friends -- it affects packet data, not descriptors. 1062 */ 1063 #ifdef DP83820 1064 /* 1065 * Cause the chip to load configuration data from the EEPROM. 1066 */ 1067 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 1068 for (i = 0; i < 10000; i++) { 1069 delay(10); 1070 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 1071 PTSCR_EELOAD_EN) == 0) 1072 break; 1073 } 1074 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 1075 PTSCR_EELOAD_EN) { 1076 printf("%s: timeout loading configuration from EEPROM\n", 1077 sc->sc_dev.dv_xname); 1078 return; 1079 } 1080 1081 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 1082 1083 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 1084 if (reg & CFG_PCI64_DET) { 1085 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 1086 /* 1087 * Check to see if this card is 64-bit. If so, enable 64-bit 1088 * data transfers. 1089 * 1090 * We can't use the DATA64_EN bit in the EEPROM, because 1091 * vendors of 32-bit cards fail to clear that bit in many 1092 * cases (yet the card still detects that it's in a 64-bit 1093 * slot; go figure). 1094 */ 1095 if (SIP_DECL(check_64bit)(pa)) { 1096 sc->sc_cfg |= CFG_DATA64_EN; 1097 printf(", using 64-bit data transfers"); 1098 } 1099 printf("\n"); 1100 } 1101 1102 /* 1103 * XXX Need some PCI flags indicating support for 1104 * XXX 64-bit addressing. 1105 */ 1106 #if 0 1107 if (reg & CFG_M64ADDR) 1108 sc->sc_cfg |= CFG_M64ADDR; 1109 if (reg & CFG_T64ADDR) 1110 sc->sc_cfg |= CFG_T64ADDR; 1111 #endif 1112 1113 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 1114 const char *sep = ""; 1115 printf("%s: using ", sc->sc_dev.dv_xname); 1116 if (reg & CFG_EXT_125) { 1117 sc->sc_cfg |= CFG_EXT_125; 1118 printf("%s125MHz clock", sep); 1119 sep = ", "; 1120 } 1121 if (reg & CFG_TBI_EN) { 1122 sc->sc_cfg |= CFG_TBI_EN; 1123 printf("%sten-bit interface", sep); 1124 sep = ", "; 1125 } 1126 printf("\n"); 1127 } 1128 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 1129 (reg & CFG_MRM_DIS) != 0) 1130 sc->sc_cfg |= CFG_MRM_DIS; 1131 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 1132 (reg & CFG_MWI_DIS) != 0) 1133 sc->sc_cfg |= CFG_MWI_DIS; 1134 1135 /* 1136 * Use the extended descriptor format on the DP83820. This 1137 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 1138 * checksumming. 1139 */ 1140 sc->sc_cfg |= CFG_EXTSTS_EN; 1141 #endif /* DP83820 */ 1142 1143 /* 1144 * Initialize our media structures and probe the MII. 1145 */ 1146 sc->sc_mii.mii_ifp = ifp; 1147 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1148 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1149 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1150 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1151 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1152 sipcom_mediastatus); 1153 1154 /* 1155 * XXX We cannot handle flow control on the DP83815. 1156 */ 1157 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1158 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1159 MII_OFFSET_ANY, 0); 1160 else 1161 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1162 MII_OFFSET_ANY, MIIF_DOPAUSE); 1163 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1164 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1165 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1166 } else 1167 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1168 1169 ifp = &sc->sc_ethercom.ec_if; 1170 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1171 ifp->if_softc = sc; 1172 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1173 sc->sc_if_flags = ifp->if_flags; 1174 ifp->if_ioctl = SIP_DECL(ioctl); 1175 ifp->if_start = SIP_DECL(start); 1176 ifp->if_watchdog = SIP_DECL(watchdog); 1177 ifp->if_init = SIP_DECL(init); 1178 ifp->if_stop = SIP_DECL(stop); 1179 IFQ_SET_READY(&ifp->if_snd); 1180 1181 /* 1182 * We can support 802.1Q VLAN-sized frames. 1183 */ 1184 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1185 1186 #ifdef DP83820 1187 /* 1188 * And the DP83820 can do VLAN tagging in hardware, and 1189 * support the jumbo Ethernet MTU. 1190 */ 1191 sc->sc_ethercom.ec_capabilities |= 1192 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1193 1194 /* 1195 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1196 * in hardware. 1197 */ 1198 ifp->if_capabilities |= 1199 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1200 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1201 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1202 #endif /* DP83820 */ 1203 1204 /* 1205 * Attach the interface. 1206 */ 1207 if_attach(ifp); 1208 ether_ifattach(ifp, enaddr); 1209 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1210 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1211 sc->sc_prev.if_capenable = ifp->if_capenable; 1212 #if NRND > 0 1213 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1214 RND_TYPE_NET, 0); 1215 #endif 1216 1217 /* 1218 * The number of bytes that must be available in 1219 * the Tx FIFO before the bus master can DMA more 1220 * data into the FIFO. 1221 */ 1222 sc->sc_tx_fill_thresh = 64 / 32; 1223 1224 /* 1225 * Start at a drain threshold of 512 bytes. We will 1226 * increase it if a DMA underrun occurs. 1227 * 1228 * XXX The minimum value of this variable should be 1229 * tuned. We may be able to improve performance 1230 * by starting with a lower value. That, however, 1231 * may trash the first few outgoing packets if the 1232 * PCI bus is saturated. 1233 */ 1234 #ifdef DP83820 1235 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1236 #else 1237 sc->sc_tx_drain_thresh = 1504 / 32; 1238 #endif 1239 1240 /* 1241 * Initialize the Rx FIFO drain threshold. 1242 * 1243 * This is in units of 8 bytes. 1244 * 1245 * We should never set this value lower than 2; 14 bytes are 1246 * required to filter the packet. 1247 */ 1248 sc->sc_rx_drain_thresh = 128 / 8; 1249 1250 #ifdef SIP_EVENT_COUNTERS 1251 /* 1252 * Attach event counters. 1253 */ 1254 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1255 NULL, sc->sc_dev.dv_xname, "txsstall"); 1256 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1257 NULL, sc->sc_dev.dv_xname, "txdstall"); 1258 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1259 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1260 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1261 NULL, sc->sc_dev.dv_xname, "txdintr"); 1262 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1263 NULL, sc->sc_dev.dv_xname, "txiintr"); 1264 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1265 NULL, sc->sc_dev.dv_xname, "rxintr"); 1266 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1267 NULL, sc->sc_dev.dv_xname, "hiberr"); 1268 #ifndef DP83820 1269 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1270 NULL, sc->sc_dev.dv_xname, "rxpause"); 1271 #endif /* !DP83820 */ 1272 #ifdef DP83820 1273 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1274 NULL, sc->sc_dev.dv_xname, "rxpause"); 1275 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1276 NULL, sc->sc_dev.dv_xname, "txpause"); 1277 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1278 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1279 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1280 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1281 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1282 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1283 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1284 NULL, sc->sc_dev.dv_xname, "txipsum"); 1285 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1286 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1287 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1288 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1289 #endif /* DP83820 */ 1290 #endif /* SIP_EVENT_COUNTERS */ 1291 1292 if (!pmf_device_register(self, NULL, sipcom_resume)) 1293 aprint_error_dev(self, "couldn't establish power handler\n"); 1294 else 1295 pmf_class_network_register(self, ifp); 1296 } 1297 1298 static inline void 1299 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1300 uint64_t capenable) 1301 { 1302 struct m_tag *mtag; 1303 u_int32_t extsts; 1304 #ifdef DEBUG 1305 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1306 #endif 1307 /* 1308 * If VLANs are enabled and the packet has a VLAN tag, set 1309 * up the descriptor to encapsulate the packet for us. 1310 * 1311 * This apparently has to be on the last descriptor of 1312 * the packet. 1313 */ 1314 1315 /* 1316 * Byte swapping is tricky. We need to provide the tag 1317 * in a network byte order. On a big-endian machine, 1318 * the byteorder is correct, but we need to swap it 1319 * anyway, because this will be undone by the outside 1320 * htole32(). That's why there must be an 1321 * unconditional swap instead of htons() inside. 1322 */ 1323 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1324 sc->sc_txdescs[lasttx].sipd_extsts |= 1325 htole32(EXTSTS_VPKT | 1326 (bswap16(VLAN_TAG_VALUE(mtag)) & 1327 EXTSTS_VTCI)); 1328 } 1329 1330 /* 1331 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1332 * checksumming, set up the descriptor to do this work 1333 * for us. 1334 * 1335 * This apparently has to be on the first descriptor of 1336 * the packet. 1337 * 1338 * Byte-swap constants so the compiler can optimize. 1339 */ 1340 extsts = 0; 1341 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1342 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1343 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1344 extsts |= htole32(EXTSTS_IPPKT); 1345 } 1346 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1347 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1348 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1349 extsts |= htole32(EXTSTS_TCPPKT); 1350 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1351 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1352 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1353 extsts |= htole32(EXTSTS_UDPPKT); 1354 } 1355 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1356 } 1357 1358 /* 1359 * sip_start: [ifnet interface function] 1360 * 1361 * Start packet transmission on the interface. 1362 */ 1363 static void 1364 SIP_DECL(start)(struct ifnet *ifp) 1365 { 1366 struct sip_softc *sc = ifp->if_softc; 1367 struct mbuf *m0; 1368 #ifndef DP83820 1369 struct mbuf *m; 1370 #endif 1371 struct sip_txsoft *txs; 1372 bus_dmamap_t dmamap; 1373 int error, nexttx, lasttx, seg; 1374 int ofree = sc->sc_txfree; 1375 #if 0 1376 int firsttx = sc->sc_txnext; 1377 #endif 1378 #ifdef DP83820 1379 struct m_tag *mtag; 1380 u_int32_t extsts; 1381 #endif 1382 1383 #ifndef DP83820 1384 /* 1385 * If we've been told to pause, don't transmit any more packets. 1386 */ 1387 if (sc->sc_paused) 1388 ifp->if_flags |= IFF_OACTIVE; 1389 #endif 1390 1391 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1392 return; 1393 1394 /* 1395 * Loop through the send queue, setting up transmit descriptors 1396 * until we drain the queue, or use up all available transmit 1397 * descriptors. 1398 */ 1399 for (;;) { 1400 /* Get a work queue entry. */ 1401 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1402 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1403 break; 1404 } 1405 1406 /* 1407 * Grab a packet off the queue. 1408 */ 1409 IFQ_POLL(&ifp->if_snd, m0); 1410 if (m0 == NULL) 1411 break; 1412 #ifndef DP83820 1413 m = NULL; 1414 #endif 1415 1416 dmamap = txs->txs_dmamap; 1417 1418 #ifdef DP83820 1419 /* 1420 * Load the DMA map. If this fails, the packet either 1421 * didn't fit in the allotted number of segments, or we 1422 * were short on resources. For the too-many-segments 1423 * case, we simply report an error and drop the packet, 1424 * since we can't sanely copy a jumbo packet to a single 1425 * buffer. 1426 */ 1427 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1428 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1429 if (error) { 1430 if (error == EFBIG) { 1431 printf("%s: Tx packet consumes too many " 1432 "DMA segments, dropping...\n", 1433 sc->sc_dev.dv_xname); 1434 IFQ_DEQUEUE(&ifp->if_snd, m0); 1435 m_freem(m0); 1436 continue; 1437 } 1438 /* 1439 * Short on resources, just stop for now. 1440 */ 1441 break; 1442 } 1443 #else /* DP83820 */ 1444 /* 1445 * Load the DMA map. If this fails, the packet either 1446 * didn't fit in the alloted number of segments, or we 1447 * were short on resources. In this case, we'll copy 1448 * and try again. 1449 */ 1450 if (bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1451 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1452 MGETHDR(m, M_DONTWAIT, MT_DATA); 1453 if (m == NULL) { 1454 printf("%s: unable to allocate Tx mbuf\n", 1455 sc->sc_dev.dv_xname); 1456 break; 1457 } 1458 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1459 if (m0->m_pkthdr.len > MHLEN) { 1460 MCLGET(m, M_DONTWAIT); 1461 if ((m->m_flags & M_EXT) == 0) { 1462 printf("%s: unable to allocate Tx " 1463 "cluster\n", sc->sc_dev.dv_xname); 1464 m_freem(m); 1465 break; 1466 } 1467 } 1468 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1469 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1470 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1471 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1472 if (error) { 1473 printf("%s: unable to load Tx buffer, " 1474 "error = %d\n", sc->sc_dev.dv_xname, error); 1475 break; 1476 } 1477 } 1478 #endif /* DP83820 */ 1479 1480 /* 1481 * Ensure we have enough descriptors free to describe 1482 * the packet. Note, we always reserve one descriptor 1483 * at the end of the ring as a termination point, to 1484 * prevent wrap-around. 1485 */ 1486 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1487 /* 1488 * Not enough free descriptors to transmit this 1489 * packet. We haven't committed anything yet, 1490 * so just unload the DMA map, put the packet 1491 * back on the queue, and punt. Notify the upper 1492 * layer that there are not more slots left. 1493 * 1494 * XXX We could allocate an mbuf and copy, but 1495 * XXX is it worth it? 1496 */ 1497 ifp->if_flags |= IFF_OACTIVE; 1498 bus_dmamap_unload(sc->sc_dmat, dmamap); 1499 #ifndef DP83820 1500 if (m != NULL) 1501 m_freem(m); 1502 #endif 1503 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1504 break; 1505 } 1506 1507 IFQ_DEQUEUE(&ifp->if_snd, m0); 1508 #ifndef DP83820 1509 if (m != NULL) { 1510 m_freem(m0); 1511 m0 = m; 1512 } 1513 #endif 1514 1515 /* 1516 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1517 */ 1518 1519 /* Sync the DMA map. */ 1520 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1521 BUS_DMASYNC_PREWRITE); 1522 1523 /* 1524 * Initialize the transmit descriptors. 1525 */ 1526 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1527 seg < dmamap->dm_nsegs; 1528 seg++, nexttx = SIP_NEXTTX(nexttx)) { 1529 /* 1530 * If this is the first descriptor we're 1531 * enqueueing, don't set the OWN bit just 1532 * yet. That could cause a race condition. 1533 * We'll do it below. 1534 */ 1535 sc->sc_txdescs[nexttx].sipd_bufptr = 1536 htole32(dmamap->dm_segs[seg].ds_addr); 1537 sc->sc_txdescs[nexttx].sipd_cmdsts = 1538 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1539 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1540 #ifdef DP83820 1541 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1542 #endif /* DP83820 */ 1543 lasttx = nexttx; 1544 } 1545 1546 /* Clear the MORE bit on the last segment. */ 1547 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1548 1549 /* 1550 * If we're in the interrupt delay window, delay the 1551 * interrupt. 1552 */ 1553 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1554 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1555 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1556 htole32(CMDSTS_INTR); 1557 sc->sc_txwin = 0; 1558 } 1559 1560 #ifdef DP83820 1561 /* 1562 * If VLANs are enabled and the packet has a VLAN tag, set 1563 * up the descriptor to encapsulate the packet for us. 1564 * 1565 * This apparently has to be on the last descriptor of 1566 * the packet. 1567 */ 1568 1569 /* 1570 * Byte swapping is tricky. We need to provide the tag 1571 * in a network byte order. On a big-endian machine, 1572 * the byteorder is correct, but we need to swap it 1573 * anyway, because this will be undone by the outside 1574 * htole32(). That's why there must be an 1575 * unconditional swap instead of htons() inside. 1576 */ 1577 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1578 sc->sc_txdescs[lasttx].sipd_extsts |= 1579 htole32(EXTSTS_VPKT | 1580 (bswap16(VLAN_TAG_VALUE(mtag)) & 1581 EXTSTS_VTCI)); 1582 } 1583 1584 /* 1585 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1586 * checksumming, set up the descriptor to do this work 1587 * for us. 1588 * 1589 * This apparently has to be on the first descriptor of 1590 * the packet. 1591 * 1592 * Byte-swap constants so the compiler can optimize. 1593 */ 1594 extsts = 0; 1595 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1596 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1597 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1598 extsts |= htole32(EXTSTS_IPPKT); 1599 } 1600 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1601 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1602 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1603 extsts |= htole32(EXTSTS_TCPPKT); 1604 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1605 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1606 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1607 extsts |= htole32(EXTSTS_UDPPKT); 1608 } 1609 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1610 #endif /* DP83820 */ 1611 1612 /* Sync the descriptors we're using. */ 1613 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1614 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1615 1616 /* 1617 * The entire packet is set up. Give the first descrptor 1618 * to the chip now. 1619 */ 1620 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1621 htole32(CMDSTS_OWN); 1622 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1623 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1624 1625 /* 1626 * Store a pointer to the packet so we can free it later, 1627 * and remember what txdirty will be once the packet is 1628 * done. 1629 */ 1630 txs->txs_mbuf = m0; 1631 txs->txs_firstdesc = sc->sc_txnext; 1632 txs->txs_lastdesc = lasttx; 1633 1634 /* Advance the tx pointer. */ 1635 sc->sc_txfree -= dmamap->dm_nsegs; 1636 sc->sc_txnext = nexttx; 1637 1638 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1639 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1640 1641 #if NBPFILTER > 0 1642 /* 1643 * Pass the packet to any BPF listeners. 1644 */ 1645 if (ifp->if_bpf) 1646 bpf_mtap(ifp->if_bpf, m0); 1647 #endif /* NBPFILTER > 0 */ 1648 } 1649 1650 if (txs == NULL || sc->sc_txfree == 0) { 1651 /* No more slots left; notify upper layer. */ 1652 ifp->if_flags |= IFF_OACTIVE; 1653 } 1654 1655 if (sc->sc_txfree != ofree) { 1656 /* 1657 * Start the transmit process. Note, the manual says 1658 * that if there are no pending transmissions in the 1659 * chip's internal queue (indicated by TXE being clear), 1660 * then the driver software must set the TXDP to the 1661 * first descriptor to be transmitted. However, if we 1662 * do this, it causes serious performance degredation on 1663 * the DP83820 under load, not setting TXDP doesn't seem 1664 * to adversely affect the SiS 900 or DP83815. 1665 * 1666 * Well, I guess it wouldn't be the first time a manual 1667 * has lied -- and they could be speaking of the NULL- 1668 * terminated descriptor list case, rather than OWN- 1669 * terminated rings. 1670 */ 1671 #if 0 1672 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1673 CR_TXE) == 0) { 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1675 SIP_CDTXADDR(sc, firsttx)); 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1677 } 1678 #else 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1680 #endif 1681 1682 /* Set a watchdog timer in case the chip flakes out. */ 1683 #ifdef DP83820 1684 /* Gigabit autonegotiation takes 5 seconds. */ 1685 ifp->if_timer = 10; 1686 #else 1687 ifp->if_timer = 5; 1688 #endif 1689 } 1690 } 1691 1692 /* 1693 * sip_watchdog: [ifnet interface function] 1694 * 1695 * Watchdog timer handler. 1696 */ 1697 static void 1698 SIP_DECL(watchdog)(struct ifnet *ifp) 1699 { 1700 struct sip_softc *sc = ifp->if_softc; 1701 1702 /* 1703 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1704 * If we get a timeout, try and sweep up transmit descriptors. 1705 * If we manage to sweep them all up, ignore the lack of 1706 * interrupt. 1707 */ 1708 SIP_DECL(txintr)(sc); 1709 1710 if (sc->sc_txfree != SIP_NTXDESC) { 1711 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1712 ifp->if_oerrors++; 1713 1714 /* Reset the interface. */ 1715 (void) SIP_DECL(init)(ifp); 1716 } else if (ifp->if_flags & IFF_DEBUG) 1717 printf("%s: recovered from device timeout\n", 1718 sc->sc_dev.dv_xname); 1719 1720 /* Try to get more packets going. */ 1721 SIP_DECL(start)(ifp); 1722 } 1723 1724 /* 1725 * sip_ioctl: [ifnet interface function] 1726 * 1727 * Handle control requests from the operator. 1728 */ 1729 static int 1730 SIP_DECL(ioctl)(struct ifnet *ifp, u_long cmd, void *data) 1731 { 1732 struct sip_softc *sc = ifp->if_softc; 1733 struct ifreq *ifr = (struct ifreq *)data; 1734 int s, error; 1735 1736 s = splnet(); 1737 1738 switch (cmd) { 1739 case SIOCSIFMEDIA: 1740 /* Flow control requires full-duplex mode. */ 1741 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1742 (ifr->ifr_media & IFM_FDX) == 0) 1743 ifr->ifr_media &= ~IFM_ETH_FMASK; 1744 #ifdef DP83820 1745 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1746 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1747 /* We can do both TXPAUSE and RXPAUSE. */ 1748 ifr->ifr_media |= 1749 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1750 } 1751 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1752 } 1753 #else 1754 /* XXX */ 1755 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1756 ifr->ifr_media &= ~IFM_ETH_FMASK; 1757 1758 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1759 if (ifr->ifr_media & IFM_FLOW) { 1760 /* 1761 * Both TXPAUSE and RXPAUSE must be set. 1762 * (SiS900 and DP83815 don't have PAUSE_ASYM 1763 * feature.) 1764 * 1765 * XXX Can SiS900 and DP83815 send PAUSE? 1766 */ 1767 ifr->ifr_media |= 1768 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1769 } 1770 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1771 } 1772 goto ethioctl; 1773 case SIOCSIFFLAGS: 1774 /* If the interface is up and running, only modify the receive 1775 * filter when setting promiscuous or debug mode. Otherwise 1776 * fall through to ether_ioctl, which will reset the chip. 1777 */ 1778 1779 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1780 == (sc)->sc_ethercom.ec_capenable) \ 1781 && ((sc)->sc_prev.is_vlan == \ 1782 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1783 1784 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1785 1786 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1787 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1788 == (IFF_UP|IFF_RUNNING)) 1789 && ((ifp->if_flags & (~RESETIGN)) 1790 == (sc->sc_if_flags & (~RESETIGN))) 1791 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1792 /* Set up the receive filter. */ 1793 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1794 error = 0; 1795 break; 1796 #undef RESETIGN 1797 } 1798 /* FALLTHROUGH */ 1799 ethioctl: 1800 default: 1801 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1802 break; 1803 1804 error = 0; 1805 1806 if (cmd == SIOCSIFCAP) 1807 error = (*ifp->if_init)(ifp); 1808 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1809 ; 1810 else if (ifp->if_flags & IFF_RUNNING) { 1811 /* 1812 * Multicast list has changed; set the hardware filter 1813 * accordingly. 1814 */ 1815 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1816 } 1817 break; 1818 } 1819 1820 /* Try to get more packets going. */ 1821 SIP_DECL(start)(ifp); 1822 1823 sc->sc_if_flags = ifp->if_flags; 1824 splx(s); 1825 return (error); 1826 } 1827 1828 /* 1829 * sip_intr: 1830 * 1831 * Interrupt service routine. 1832 */ 1833 static int 1834 SIP_DECL(intr)(void *arg) 1835 { 1836 struct sip_softc *sc = arg; 1837 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1838 u_int32_t isr; 1839 int handled = 0; 1840 1841 /* Disable interrupts. */ 1842 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1843 1844 for (;;) { 1845 /* Reading clears interrupt. */ 1846 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1847 if ((isr & sc->sc_imr) == 0) 1848 break; 1849 1850 #if NRND > 0 1851 if (RND_ENABLED(&sc->rnd_source)) 1852 rnd_add_uint32(&sc->rnd_source, isr); 1853 #endif 1854 1855 handled = 1; 1856 1857 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1858 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1859 1860 /* Grab any new packets. */ 1861 SIP_DECL(rxintr)(sc); 1862 1863 if (isr & ISR_RXORN) { 1864 printf("%s: receive FIFO overrun\n", 1865 sc->sc_dev.dv_xname); 1866 1867 /* XXX adjust rx_drain_thresh? */ 1868 } 1869 1870 if (isr & ISR_RXIDLE) { 1871 printf("%s: receive ring overrun\n", 1872 sc->sc_dev.dv_xname); 1873 1874 /* Get the receive process going again. */ 1875 bus_space_write_4(sc->sc_st, sc->sc_sh, 1876 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1877 bus_space_write_4(sc->sc_st, sc->sc_sh, 1878 SIP_CR, CR_RXE); 1879 } 1880 } 1881 1882 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1883 #ifdef SIP_EVENT_COUNTERS 1884 if (isr & ISR_TXDESC) 1885 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1886 else if (isr & ISR_TXIDLE) 1887 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1888 #endif 1889 1890 /* Sweep up transmit descriptors. */ 1891 SIP_DECL(txintr)(sc); 1892 1893 if (isr & ISR_TXURN) { 1894 u_int32_t thresh; 1895 1896 printf("%s: transmit FIFO underrun", 1897 sc->sc_dev.dv_xname); 1898 1899 thresh = sc->sc_tx_drain_thresh + 1; 1900 if (thresh <= TXCFG_DRTH && 1901 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1902 (sc->sc_tx_fill_thresh * 32))) { 1903 printf("; increasing Tx drain " 1904 "threshold to %u bytes\n", 1905 thresh * 32); 1906 sc->sc_tx_drain_thresh = thresh; 1907 (void) SIP_DECL(init)(ifp); 1908 } else { 1909 (void) SIP_DECL(init)(ifp); 1910 printf("\n"); 1911 } 1912 } 1913 } 1914 1915 #if !defined(DP83820) 1916 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1917 if (isr & ISR_PAUSE_ST) { 1918 sc->sc_paused = 1; 1919 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1920 ifp->if_flags |= IFF_OACTIVE; 1921 } 1922 if (isr & ISR_PAUSE_END) { 1923 sc->sc_paused = 0; 1924 ifp->if_flags &= ~IFF_OACTIVE; 1925 } 1926 } 1927 #endif /* ! DP83820 */ 1928 1929 if (isr & ISR_HIBERR) { 1930 int want_init = 0; 1931 1932 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1933 1934 #define PRINTERR(bit, str) \ 1935 do { \ 1936 if ((isr & (bit)) != 0) { \ 1937 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1938 printf("%s: %s\n", \ 1939 sc->sc_dev.dv_xname, str); \ 1940 want_init = 1; \ 1941 } \ 1942 } while (/*CONSTCOND*/0) 1943 1944 PRINTERR(ISR_DPERR, "parity error"); 1945 PRINTERR(ISR_SSERR, "system error"); 1946 PRINTERR(ISR_RMABT, "master abort"); 1947 PRINTERR(ISR_RTABT, "target abort"); 1948 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1949 /* 1950 * Ignore: 1951 * Tx reset complete 1952 * Rx reset complete 1953 */ 1954 if (want_init) 1955 (void) SIP_DECL(init)(ifp); 1956 #undef PRINTERR 1957 } 1958 } 1959 1960 /* Re-enable interrupts. */ 1961 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1962 1963 /* Try to get more packets going. */ 1964 SIP_DECL(start)(ifp); 1965 1966 return (handled); 1967 } 1968 1969 /* 1970 * sip_txintr: 1971 * 1972 * Helper; handle transmit interrupts. 1973 */ 1974 static void 1975 SIP_DECL(txintr)(struct sip_softc *sc) 1976 { 1977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1978 struct sip_txsoft *txs; 1979 u_int32_t cmdsts; 1980 1981 #ifndef DP83820 1982 if (sc->sc_paused == 0) 1983 #endif 1984 ifp->if_flags &= ~IFF_OACTIVE; 1985 1986 /* 1987 * Go through our Tx list and free mbufs for those 1988 * frames which have been transmitted. 1989 */ 1990 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1991 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1992 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1993 1994 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1995 if (cmdsts & CMDSTS_OWN) 1996 break; 1997 1998 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1999 2000 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2001 2002 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2003 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2004 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2005 m_freem(txs->txs_mbuf); 2006 txs->txs_mbuf = NULL; 2007 2008 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2009 2010 /* 2011 * Check for errors and collisions. 2012 */ 2013 if (cmdsts & 2014 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2015 ifp->if_oerrors++; 2016 if (cmdsts & CMDSTS_Tx_EC) 2017 ifp->if_collisions += 16; 2018 if (ifp->if_flags & IFF_DEBUG) { 2019 if (cmdsts & CMDSTS_Tx_ED) 2020 printf("%s: excessive deferral\n", 2021 sc->sc_dev.dv_xname); 2022 if (cmdsts & CMDSTS_Tx_EC) 2023 printf("%s: excessive collisions\n", 2024 sc->sc_dev.dv_xname); 2025 } 2026 } else { 2027 /* Packet was transmitted successfully. */ 2028 ifp->if_opackets++; 2029 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2030 } 2031 } 2032 2033 /* 2034 * If there are no more pending transmissions, cancel the watchdog 2035 * timer. 2036 */ 2037 if (txs == NULL) { 2038 ifp->if_timer = 0; 2039 sc->sc_txwin = 0; 2040 } 2041 } 2042 2043 #if defined(DP83820) 2044 /* 2045 * sip_rxintr: 2046 * 2047 * Helper; handle receive interrupts. 2048 */ 2049 static void 2050 SIP_DECL(rxintr)(struct sip_softc *sc) 2051 { 2052 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2053 struct sip_rxsoft *rxs; 2054 struct mbuf *m; 2055 u_int32_t cmdsts, extsts; 2056 int i, len; 2057 2058 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2059 rxs = &sc->sc_rxsoft[i]; 2060 2061 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2062 2063 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2064 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2065 len = CMDSTS_SIZE(cmdsts); 2066 2067 /* 2068 * NOTE: OWN is set if owned by _consumer_. We're the 2069 * consumer of the receive ring, so if the bit is clear, 2070 * we have processed all of the packets. 2071 */ 2072 if ((cmdsts & CMDSTS_OWN) == 0) { 2073 /* 2074 * We have processed all of the receive buffers. 2075 */ 2076 break; 2077 } 2078 2079 if (__predict_false(sc->sc_rxdiscard)) { 2080 SIP_INIT_RXDESC(sc, i); 2081 if ((cmdsts & CMDSTS_MORE) == 0) { 2082 /* Reset our state. */ 2083 sc->sc_rxdiscard = 0; 2084 } 2085 continue; 2086 } 2087 2088 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2089 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2090 2091 m = rxs->rxs_mbuf; 2092 2093 /* 2094 * Add a new receive buffer to the ring. 2095 */ 2096 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2097 /* 2098 * Failed, throw away what we've done so 2099 * far, and discard the rest of the packet. 2100 */ 2101 ifp->if_ierrors++; 2102 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2103 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2104 SIP_INIT_RXDESC(sc, i); 2105 if (cmdsts & CMDSTS_MORE) 2106 sc->sc_rxdiscard = 1; 2107 if (sc->sc_rxhead != NULL) 2108 m_freem(sc->sc_rxhead); 2109 SIP_RXCHAIN_RESET(sc); 2110 continue; 2111 } 2112 2113 SIP_RXCHAIN_LINK(sc, m); 2114 2115 m->m_len = len; 2116 2117 /* 2118 * If this is not the end of the packet, keep 2119 * looking. 2120 */ 2121 if (cmdsts & CMDSTS_MORE) { 2122 sc->sc_rxlen += len; 2123 continue; 2124 } 2125 2126 /* 2127 * Okay, we have the entire packet now. The chip includes 2128 * the FCS, so we need to trim it. 2129 */ 2130 m->m_len -= ETHER_CRC_LEN; 2131 2132 *sc->sc_rxtailp = NULL; 2133 len = m->m_len + sc->sc_rxlen; 2134 m = sc->sc_rxhead; 2135 2136 SIP_RXCHAIN_RESET(sc); 2137 2138 /* 2139 * If an error occurred, update stats and drop the packet. 2140 */ 2141 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2142 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2143 ifp->if_ierrors++; 2144 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2145 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2146 /* Receive overrun handled elsewhere. */ 2147 printf("%s: receive descriptor error\n", 2148 sc->sc_dev.dv_xname); 2149 } 2150 #define PRINTERR(bit, str) \ 2151 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2152 (cmdsts & (bit)) != 0) \ 2153 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2154 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2155 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2156 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2157 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2158 #undef PRINTERR 2159 m_freem(m); 2160 continue; 2161 } 2162 2163 /* 2164 * If the packet is small enough to fit in a 2165 * single header mbuf, allocate one and copy 2166 * the data into it. This greatly reduces 2167 * memory consumption when we receive lots 2168 * of small packets. 2169 */ 2170 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 2171 struct mbuf *nm; 2172 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2173 if (nm == NULL) { 2174 ifp->if_ierrors++; 2175 m_freem(m); 2176 continue; 2177 } 2178 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2179 nm->m_data += 2; 2180 nm->m_pkthdr.len = nm->m_len = len; 2181 m_copydata(m, 0, len, mtod(nm, void *)); 2182 m_freem(m); 2183 m = nm; 2184 } 2185 #ifndef __NO_STRICT_ALIGNMENT 2186 else { 2187 /* 2188 * The DP83820's receive buffers must be 4-byte 2189 * aligned. But this means that the data after 2190 * the Ethernet header is misaligned. To compensate, 2191 * we have artificially shortened the buffer size 2192 * in the descriptor, and we do an overlapping copy 2193 * of the data two bytes further in (in the first 2194 * buffer of the chain only). 2195 */ 2196 memmove(mtod(m, char *) + 2, mtod(m, void *), 2197 m->m_len); 2198 m->m_data += 2; 2199 } 2200 #endif /* ! __NO_STRICT_ALIGNMENT */ 2201 2202 /* 2203 * If VLANs are enabled, VLAN packets have been unwrapped 2204 * for us. Associate the tag with the packet. 2205 */ 2206 2207 /* 2208 * Again, byte swapping is tricky. Hardware provided 2209 * the tag in the network byte order, but extsts was 2210 * passed through le32toh() in the meantime. On a 2211 * big-endian machine, we need to swap it again. On a 2212 * little-endian machine, we need to convert from the 2213 * network to host byte order. This means that we must 2214 * swap it in any case, so unconditional swap instead 2215 * of htons() is used. 2216 */ 2217 if ((extsts & EXTSTS_VPKT) != 0) { 2218 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2219 continue); 2220 } 2221 2222 /* 2223 * Set the incoming checksum information for the 2224 * packet. 2225 */ 2226 if ((extsts & EXTSTS_IPPKT) != 0) { 2227 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2228 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2229 if (extsts & EXTSTS_Rx_IPERR) 2230 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2231 if (extsts & EXTSTS_TCPPKT) { 2232 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2233 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2234 if (extsts & EXTSTS_Rx_TCPERR) 2235 m->m_pkthdr.csum_flags |= 2236 M_CSUM_TCP_UDP_BAD; 2237 } else if (extsts & EXTSTS_UDPPKT) { 2238 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2239 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2240 if (extsts & EXTSTS_Rx_UDPERR) 2241 m->m_pkthdr.csum_flags |= 2242 M_CSUM_TCP_UDP_BAD; 2243 } 2244 } 2245 2246 ifp->if_ipackets++; 2247 m->m_pkthdr.rcvif = ifp; 2248 m->m_pkthdr.len = len; 2249 2250 #if NBPFILTER > 0 2251 /* 2252 * Pass this up to any BPF listeners, but only 2253 * pass if up the stack if it's for us. 2254 */ 2255 if (ifp->if_bpf) 2256 bpf_mtap(ifp->if_bpf, m); 2257 #endif /* NBPFILTER > 0 */ 2258 2259 /* Pass it on. */ 2260 (*ifp->if_input)(ifp, m); 2261 } 2262 2263 /* Update the receive pointer. */ 2264 sc->sc_rxptr = i; 2265 } 2266 #else /* ! DP83820 */ 2267 /* 2268 * sip_rxintr: 2269 * 2270 * Helper; handle receive interrupts. 2271 */ 2272 static void 2273 SIP_DECL(rxintr)(struct sip_softc *sc) 2274 { 2275 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2276 struct sip_rxsoft *rxs; 2277 struct mbuf *m; 2278 u_int32_t cmdsts; 2279 int i, len; 2280 2281 for (i = sc->sc_rxptr;; i = SIP_NEXTRX(i)) { 2282 rxs = &sc->sc_rxsoft[i]; 2283 2284 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2285 2286 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2287 2288 /* 2289 * NOTE: OWN is set if owned by _consumer_. We're the 2290 * consumer of the receive ring, so if the bit is clear, 2291 * we have processed all of the packets. 2292 */ 2293 if ((cmdsts & CMDSTS_OWN) == 0) { 2294 /* 2295 * We have processed all of the receive buffers. 2296 */ 2297 break; 2298 } 2299 2300 /* 2301 * If any collisions were seen on the wire, count one. 2302 */ 2303 if (cmdsts & CMDSTS_Rx_COL) 2304 ifp->if_collisions++; 2305 2306 /* 2307 * If an error occurred, update stats, clear the status 2308 * word, and leave the packet buffer in place. It will 2309 * simply be reused the next time the ring comes around. 2310 */ 2311 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2312 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2313 ifp->if_ierrors++; 2314 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2315 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2316 /* Receive overrun handled elsewhere. */ 2317 printf("%s: receive descriptor error\n", 2318 sc->sc_dev.dv_xname); 2319 } 2320 #define PRINTERR(bit, str) \ 2321 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2322 (cmdsts & (bit)) != 0) \ 2323 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2324 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2325 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2326 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2327 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2328 #undef PRINTERR 2329 SIP_INIT_RXDESC(sc, i); 2330 continue; 2331 } 2332 2333 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2334 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2335 2336 /* 2337 * No errors; receive the packet. Note, the SiS 900 2338 * includes the CRC with every packet. 2339 */ 2340 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2341 2342 #ifdef __NO_STRICT_ALIGNMENT 2343 /* 2344 * If the packet is small enough to fit in a 2345 * single header mbuf, allocate one and copy 2346 * the data into it. This greatly reduces 2347 * memory consumption when we receive lots 2348 * of small packets. 2349 * 2350 * Otherwise, we add a new buffer to the receive 2351 * chain. If this fails, we drop the packet and 2352 * recycle the old buffer. 2353 */ 2354 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2355 MGETHDR(m, M_DONTWAIT, MT_DATA); 2356 if (m == NULL) 2357 goto dropit; 2358 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2359 memcpy(mtod(m, void *), 2360 mtod(rxs->rxs_mbuf, void *), len); 2361 SIP_INIT_RXDESC(sc, i); 2362 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2363 rxs->rxs_dmamap->dm_mapsize, 2364 BUS_DMASYNC_PREREAD); 2365 } else { 2366 m = rxs->rxs_mbuf; 2367 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2368 dropit: 2369 ifp->if_ierrors++; 2370 SIP_INIT_RXDESC(sc, i); 2371 bus_dmamap_sync(sc->sc_dmat, 2372 rxs->rxs_dmamap, 0, 2373 rxs->rxs_dmamap->dm_mapsize, 2374 BUS_DMASYNC_PREREAD); 2375 continue; 2376 } 2377 } 2378 #else 2379 /* 2380 * The SiS 900's receive buffers must be 4-byte aligned. 2381 * But this means that the data after the Ethernet header 2382 * is misaligned. We must allocate a new buffer and 2383 * copy the data, shifted forward 2 bytes. 2384 */ 2385 MGETHDR(m, M_DONTWAIT, MT_DATA); 2386 if (m == NULL) { 2387 dropit: 2388 ifp->if_ierrors++; 2389 SIP_INIT_RXDESC(sc, i); 2390 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2391 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2392 continue; 2393 } 2394 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2395 if (len > (MHLEN - 2)) { 2396 MCLGET(m, M_DONTWAIT); 2397 if ((m->m_flags & M_EXT) == 0) { 2398 m_freem(m); 2399 goto dropit; 2400 } 2401 } 2402 m->m_data += 2; 2403 2404 /* 2405 * Note that we use clusters for incoming frames, so the 2406 * buffer is virtually contiguous. 2407 */ 2408 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2409 2410 /* Allow the receive descriptor to continue using its mbuf. */ 2411 SIP_INIT_RXDESC(sc, i); 2412 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2413 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2414 #endif /* __NO_STRICT_ALIGNMENT */ 2415 2416 ifp->if_ipackets++; 2417 m->m_pkthdr.rcvif = ifp; 2418 m->m_pkthdr.len = m->m_len = len; 2419 2420 #if NBPFILTER > 0 2421 /* 2422 * Pass this up to any BPF listeners, but only 2423 * pass if up the stack if it's for us. 2424 */ 2425 if (ifp->if_bpf) 2426 bpf_mtap(ifp->if_bpf, m); 2427 #endif /* NBPFILTER > 0 */ 2428 2429 /* Pass it on. */ 2430 (*ifp->if_input)(ifp, m); 2431 } 2432 2433 /* Update the receive pointer. */ 2434 sc->sc_rxptr = i; 2435 } 2436 #endif /* DP83820 */ 2437 2438 /* 2439 * sip_tick: 2440 * 2441 * One second timer, used to tick the MII. 2442 */ 2443 static void 2444 SIP_DECL(tick)(void *arg) 2445 { 2446 struct sip_softc *sc = arg; 2447 int s; 2448 2449 s = splnet(); 2450 #ifdef DP83820 2451 #ifdef SIP_EVENT_COUNTERS 2452 /* Read PAUSE related counts from MIB registers. */ 2453 sc->sc_ev_rxpause.ev_count += 2454 bus_space_read_4(sc->sc_st, sc->sc_sh, 2455 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2456 sc->sc_ev_txpause.ev_count += 2457 bus_space_read_4(sc->sc_st, sc->sc_sh, 2458 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2460 #endif /* SIP_EVENT_COUNTERS */ 2461 #endif /* DP83820 */ 2462 mii_tick(&sc->sc_mii); 2463 splx(s); 2464 2465 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2466 } 2467 2468 /* 2469 * sip_reset: 2470 * 2471 * Perform a soft reset on the SiS 900. 2472 */ 2473 static void 2474 SIP_DECL(reset)(struct sip_softc *sc) 2475 { 2476 bus_space_tag_t st = sc->sc_st; 2477 bus_space_handle_t sh = sc->sc_sh; 2478 int i; 2479 2480 bus_space_write_4(st, sh, SIP_IER, 0); 2481 bus_space_write_4(st, sh, SIP_IMR, 0); 2482 bus_space_write_4(st, sh, SIP_RFCR, 0); 2483 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2484 2485 for (i = 0; i < SIP_TIMEOUT; i++) { 2486 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2487 break; 2488 delay(2); 2489 } 2490 2491 if (i == SIP_TIMEOUT) 2492 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2493 2494 delay(1000); 2495 2496 #ifdef DP83820 2497 /* 2498 * Set the general purpose I/O bits. Do it here in case we 2499 * need to have GPIO set up to talk to the media interface. 2500 */ 2501 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2502 delay(1000); 2503 #endif /* DP83820 */ 2504 } 2505 2506 /* 2507 * sip_init: [ ifnet interface function ] 2508 * 2509 * Initialize the interface. Must be called at splnet(). 2510 */ 2511 static int 2512 SIP_DECL(init)(struct ifnet *ifp) 2513 { 2514 struct sip_softc *sc = ifp->if_softc; 2515 bus_space_tag_t st = sc->sc_st; 2516 bus_space_handle_t sh = sc->sc_sh; 2517 struct sip_txsoft *txs; 2518 struct sip_rxsoft *rxs; 2519 struct sip_desc *sipd; 2520 #if defined(DP83820) 2521 u_int32_t reg; 2522 #endif 2523 int i, error = 0; 2524 2525 /* 2526 * Cancel any pending I/O. 2527 */ 2528 SIP_DECL(stop)(ifp, 0); 2529 2530 /* 2531 * Reset the chip to a known state. 2532 */ 2533 SIP_DECL(reset)(sc); 2534 2535 #if !defined(DP83820) 2536 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2537 /* 2538 * DP83815 manual, page 78: 2539 * 4.4 Recommended Registers Configuration 2540 * For optimum performance of the DP83815, version noted 2541 * as DP83815CVNG (SRR = 203h), the listed register 2542 * modifications must be followed in sequence... 2543 * 2544 * It's not clear if this should be 302h or 203h because that 2545 * chip name is listed as SRR 302h in the description of the 2546 * SRR register. However, my revision 302h DP83815 on the 2547 * Netgear FA311 purchased in 02/2001 needs these settings 2548 * to avoid tons of errors in AcceptPerfectMatch (non- 2549 * IFF_PROMISC) mode. I do not know if other revisions need 2550 * this set or not. [briggs -- 09 March 2001] 2551 * 2552 * Note that only the low-order 12 bits of 0xe4 are documented 2553 * and that this sets reserved bits in that register. 2554 */ 2555 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2556 2557 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2558 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2559 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2560 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2561 2562 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2563 } 2564 #endif /* ! DP83820 */ 2565 2566 /* 2567 * Initialize the transmit descriptor ring. 2568 */ 2569 for (i = 0; i < SIP_NTXDESC; i++) { 2570 sipd = &sc->sc_txdescs[i]; 2571 memset(sipd, 0, sizeof(struct sip_desc)); 2572 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, SIP_NEXTTX(i))); 2573 } 2574 SIP_CDTXSYNC(sc, 0, SIP_NTXDESC, 2575 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2576 sc->sc_txfree = SIP_NTXDESC; 2577 sc->sc_txnext = 0; 2578 sc->sc_txwin = 0; 2579 2580 /* 2581 * Initialize the transmit job descriptors. 2582 */ 2583 SIMPLEQ_INIT(&sc->sc_txfreeq); 2584 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2585 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2586 txs = &sc->sc_txsoft[i]; 2587 txs->txs_mbuf = NULL; 2588 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2589 } 2590 2591 /* 2592 * Initialize the receive descriptor and receive job 2593 * descriptor rings. 2594 */ 2595 for (i = 0; i < SIP_NRXDESC; i++) { 2596 rxs = &sc->sc_rxsoft[i]; 2597 if (rxs->rxs_mbuf == NULL) { 2598 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2599 printf("%s: unable to allocate or map rx " 2600 "buffer %d, error = %d\n", 2601 sc->sc_dev.dv_xname, i, error); 2602 /* 2603 * XXX Should attempt to run with fewer receive 2604 * XXX buffers instead of just failing. 2605 */ 2606 SIP_DECL(rxdrain)(sc); 2607 goto out; 2608 } 2609 } else 2610 SIP_INIT_RXDESC(sc, i); 2611 } 2612 sc->sc_rxptr = 0; 2613 #ifdef DP83820 2614 sc->sc_rxdiscard = 0; 2615 SIP_RXCHAIN_RESET(sc); 2616 #endif /* DP83820 */ 2617 2618 /* 2619 * Set the configuration register; it's already initialized 2620 * in sip_attach(). 2621 */ 2622 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2623 2624 /* 2625 * Initialize the prototype TXCFG register. 2626 */ 2627 #if defined(DP83820) 2628 sc->sc_txcfg = TXCFG_MXDMA_512; 2629 sc->sc_rxcfg = RXCFG_MXDMA_512; 2630 #else 2631 if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2632 SIP_SIS900_REV(sc, SIS_REV_960) || 2633 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2634 (sc->sc_cfg & CFG_EDBMASTEN)) { 2635 sc->sc_txcfg = TXCFG_MXDMA_64; 2636 sc->sc_rxcfg = RXCFG_MXDMA_64; 2637 } else { 2638 sc->sc_txcfg = TXCFG_MXDMA_512; 2639 sc->sc_rxcfg = RXCFG_MXDMA_512; 2640 } 2641 #endif /* DP83820 */ 2642 2643 sc->sc_txcfg |= TXCFG_ATP | 2644 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2645 sc->sc_tx_drain_thresh; 2646 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2647 2648 /* 2649 * Initialize the receive drain threshold if we have never 2650 * done so. 2651 */ 2652 if (sc->sc_rx_drain_thresh == 0) { 2653 /* 2654 * XXX This value should be tuned. This is set to the 2655 * maximum of 248 bytes, and we may be able to improve 2656 * performance by decreasing it (although we should never 2657 * set this value lower than 2; 14 bytes are required to 2658 * filter the packet). 2659 */ 2660 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2661 } 2662 2663 /* 2664 * Initialize the prototype RXCFG register. 2665 */ 2666 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2667 #ifdef DP83820 2668 /* 2669 * Accept long packets (including FCS) so we can handle 2670 * 802.1q-tagged frames and jumbo frames properly. 2671 */ 2672 if (ifp->if_mtu > ETHERMTU || 2673 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2674 sc->sc_rxcfg |= RXCFG_ALP; 2675 2676 /* 2677 * Checksum offloading is disabled if the user selects an MTU 2678 * larger than 8109. (FreeBSD says 8152, but there is emperical 2679 * evidence that >8109 does not work on some boards, such as the 2680 * Planex GN-1000TE). 2681 */ 2682 if (ifp->if_mtu > 8109 && 2683 (ifp->if_capenable & 2684 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2685 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2686 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2687 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2688 "disabled.\n", sc->sc_dev.dv_xname); 2689 ifp->if_capenable &= 2690 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2691 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2692 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2693 ifp->if_csum_flags_tx = 0; 2694 ifp->if_csum_flags_rx = 0; 2695 } 2696 #else 2697 /* 2698 * Accept packets >1518 bytes (including FCS) so we can handle 2699 * 802.1q-tagged frames properly. 2700 */ 2701 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2702 sc->sc_rxcfg |= RXCFG_ALP; 2703 #endif 2704 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2705 2706 #ifdef DP83820 2707 /* 2708 * Initialize the VLAN/IP receive control register. 2709 * We enable checksum computation on all incoming 2710 * packets, and do not reject packets w/ bad checksums. 2711 */ 2712 reg = 0; 2713 if (ifp->if_capenable & 2714 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2715 reg |= VRCR_IPEN; 2716 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2717 reg |= VRCR_VTDEN|VRCR_VTREN; 2718 bus_space_write_4(st, sh, SIP_VRCR, reg); 2719 2720 /* 2721 * Initialize the VLAN/IP transmit control register. 2722 * We enable outgoing checksum computation on a 2723 * per-packet basis. 2724 */ 2725 reg = 0; 2726 if (ifp->if_capenable & 2727 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2728 reg |= VTCR_PPCHK; 2729 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2730 reg |= VTCR_VPPTI; 2731 bus_space_write_4(st, sh, SIP_VTCR, reg); 2732 2733 /* 2734 * If we're using VLANs, initialize the VLAN data register. 2735 * To understand why we bswap the VLAN Ethertype, see section 2736 * 4.2.36 of the DP83820 manual. 2737 */ 2738 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2739 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2740 #endif /* DP83820 */ 2741 2742 /* 2743 * Give the transmit and receive rings to the chip. 2744 */ 2745 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2746 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2747 2748 /* 2749 * Initialize the interrupt mask. 2750 */ 2751 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2752 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2753 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2754 2755 /* Set up the receive filter. */ 2756 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2757 2758 #ifdef DP83820 2759 /* 2760 * Tune sc_rx_flow_thresh. 2761 * XXX "More than 8KB" is too short for jumbo frames. 2762 * XXX TODO: Threshold value should be user-settable. 2763 */ 2764 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2765 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2766 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2767 #endif 2768 2769 /* 2770 * Set the current media. Do this after initializing the prototype 2771 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2772 * control. 2773 */ 2774 if ((error = ether_mediachange(ifp)) != 0) 2775 goto out; 2776 2777 #ifdef DP83820 2778 /* 2779 * Set the interrupt hold-off timer to 100us. 2780 */ 2781 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2782 #endif 2783 2784 /* 2785 * Enable interrupts. 2786 */ 2787 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2788 2789 /* 2790 * Start the transmit and receive processes. 2791 */ 2792 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2793 2794 /* 2795 * Start the one second MII clock. 2796 */ 2797 callout_reset(&sc->sc_tick_ch, hz, SIP_DECL(tick), sc); 2798 2799 /* 2800 * ...all done! 2801 */ 2802 ifp->if_flags |= IFF_RUNNING; 2803 ifp->if_flags &= ~IFF_OACTIVE; 2804 sc->sc_if_flags = ifp->if_flags; 2805 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2806 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2807 sc->sc_prev.if_capenable = ifp->if_capenable; 2808 2809 out: 2810 if (error) 2811 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2812 return (error); 2813 } 2814 2815 /* 2816 * sip_drain: 2817 * 2818 * Drain the receive queue. 2819 */ 2820 static void 2821 SIP_DECL(rxdrain)(struct sip_softc *sc) 2822 { 2823 struct sip_rxsoft *rxs; 2824 int i; 2825 2826 for (i = 0; i < SIP_NRXDESC; i++) { 2827 rxs = &sc->sc_rxsoft[i]; 2828 if (rxs->rxs_mbuf != NULL) { 2829 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2830 m_freem(rxs->rxs_mbuf); 2831 rxs->rxs_mbuf = NULL; 2832 } 2833 } 2834 } 2835 2836 /* 2837 * sip_stop: [ ifnet interface function ] 2838 * 2839 * Stop transmission on the interface. 2840 */ 2841 static void 2842 SIP_DECL(stop)(struct ifnet *ifp, int disable) 2843 { 2844 struct sip_softc *sc = ifp->if_softc; 2845 bus_space_tag_t st = sc->sc_st; 2846 bus_space_handle_t sh = sc->sc_sh; 2847 struct sip_txsoft *txs; 2848 u_int32_t cmdsts = 0; /* DEBUG */ 2849 2850 /* 2851 * Stop the one second clock. 2852 */ 2853 callout_stop(&sc->sc_tick_ch); 2854 2855 /* Down the MII. */ 2856 mii_down(&sc->sc_mii); 2857 2858 /* 2859 * Disable interrupts. 2860 */ 2861 bus_space_write_4(st, sh, SIP_IER, 0); 2862 2863 /* 2864 * Stop receiver and transmitter. 2865 */ 2866 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2867 2868 /* 2869 * Release any queued transmit buffers. 2870 */ 2871 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2872 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2873 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2874 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2875 CMDSTS_INTR) == 0) 2876 printf("%s: sip_stop: last descriptor does not " 2877 "have INTR bit set\n", sc->sc_dev.dv_xname); 2878 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2879 #ifdef DIAGNOSTIC 2880 if (txs->txs_mbuf == NULL) { 2881 printf("%s: dirty txsoft with no mbuf chain\n", 2882 sc->sc_dev.dv_xname); 2883 panic("sip_stop"); 2884 } 2885 #endif 2886 cmdsts |= /* DEBUG */ 2887 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2888 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2889 m_freem(txs->txs_mbuf); 2890 txs->txs_mbuf = NULL; 2891 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2892 } 2893 2894 if (disable) 2895 SIP_DECL(rxdrain)(sc); 2896 2897 /* 2898 * Mark the interface down and cancel the watchdog timer. 2899 */ 2900 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2901 ifp->if_timer = 0; 2902 2903 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2904 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != SIP_NTXDESC) 2905 printf("%s: sip_stop: no INTR bits set in dirty tx " 2906 "descriptors\n", sc->sc_dev.dv_xname); 2907 } 2908 2909 /* 2910 * sip_read_eeprom: 2911 * 2912 * Read data from the serial EEPROM. 2913 */ 2914 static void 2915 SIP_DECL(read_eeprom)(struct sip_softc *sc, int word, int wordcnt, 2916 u_int16_t *data) 2917 { 2918 bus_space_tag_t st = sc->sc_st; 2919 bus_space_handle_t sh = sc->sc_sh; 2920 u_int16_t reg; 2921 int i, x; 2922 2923 for (i = 0; i < wordcnt; i++) { 2924 /* Send CHIP SELECT. */ 2925 reg = EROMAR_EECS; 2926 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2927 2928 /* Shift in the READ opcode. */ 2929 for (x = 3; x > 0; x--) { 2930 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2931 reg |= EROMAR_EEDI; 2932 else 2933 reg &= ~EROMAR_EEDI; 2934 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2935 bus_space_write_4(st, sh, SIP_EROMAR, 2936 reg | EROMAR_EESK); 2937 delay(4); 2938 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2939 delay(4); 2940 } 2941 2942 /* Shift in address. */ 2943 for (x = 6; x > 0; x--) { 2944 if ((word + i) & (1 << (x - 1))) 2945 reg |= EROMAR_EEDI; 2946 else 2947 reg &= ~EROMAR_EEDI; 2948 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2949 bus_space_write_4(st, sh, SIP_EROMAR, 2950 reg | EROMAR_EESK); 2951 delay(4); 2952 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2953 delay(4); 2954 } 2955 2956 /* Shift out data. */ 2957 reg = EROMAR_EECS; 2958 data[i] = 0; 2959 for (x = 16; x > 0; x--) { 2960 bus_space_write_4(st, sh, SIP_EROMAR, 2961 reg | EROMAR_EESK); 2962 delay(4); 2963 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2964 data[i] |= (1 << (x - 1)); 2965 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2966 delay(4); 2967 } 2968 2969 /* Clear CHIP SELECT. */ 2970 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2971 delay(4); 2972 } 2973 } 2974 2975 /* 2976 * sip_add_rxbuf: 2977 * 2978 * Add a receive buffer to the indicated descriptor. 2979 */ 2980 static int 2981 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2982 { 2983 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2984 struct mbuf *m; 2985 int error; 2986 2987 MGETHDR(m, M_DONTWAIT, MT_DATA); 2988 if (m == NULL) 2989 return (ENOBUFS); 2990 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2991 2992 MCLGET(m, M_DONTWAIT); 2993 if ((m->m_flags & M_EXT) == 0) { 2994 m_freem(m); 2995 return (ENOBUFS); 2996 } 2997 2998 #if defined(DP83820) 2999 m->m_len = SIP_RXBUF_LEN; 3000 #endif /* DP83820 */ 3001 3002 if (rxs->rxs_mbuf != NULL) 3003 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3004 3005 rxs->rxs_mbuf = m; 3006 3007 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3008 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3009 BUS_DMA_READ|BUS_DMA_NOWAIT); 3010 if (error) { 3011 printf("%s: can't load rx DMA map %d, error = %d\n", 3012 sc->sc_dev.dv_xname, idx, error); 3013 panic("sip_add_rxbuf"); /* XXX */ 3014 } 3015 3016 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3017 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3018 3019 SIP_INIT_RXDESC(sc, idx); 3020 3021 return (0); 3022 } 3023 3024 #if !defined(DP83820) 3025 /* 3026 * sip_sis900_set_filter: 3027 * 3028 * Set up the receive filter. 3029 */ 3030 static void 3031 SIP_DECL(sis900_set_filter)(struct sip_softc *sc) 3032 { 3033 bus_space_tag_t st = sc->sc_st; 3034 bus_space_handle_t sh = sc->sc_sh; 3035 struct ethercom *ec = &sc->sc_ethercom; 3036 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3037 struct ether_multi *enm; 3038 const u_int8_t *cp; 3039 struct ether_multistep step; 3040 u_int32_t crc, mchash[16]; 3041 3042 /* 3043 * Initialize the prototype RFCR. 3044 */ 3045 sc->sc_rfcr = RFCR_RFEN; 3046 if (ifp->if_flags & IFF_BROADCAST) 3047 sc->sc_rfcr |= RFCR_AAB; 3048 if (ifp->if_flags & IFF_PROMISC) { 3049 sc->sc_rfcr |= RFCR_AAP; 3050 goto allmulti; 3051 } 3052 3053 /* 3054 * Set up the multicast address filter by passing all multicast 3055 * addresses through a CRC generator, and then using the high-order 3056 * 6 bits as an index into the 128 bit multicast hash table (only 3057 * the lower 16 bits of each 32 bit multicast hash register are 3058 * valid). The high order bits select the register, while the 3059 * rest of the bits select the bit within the register. 3060 */ 3061 3062 memset(mchash, 0, sizeof(mchash)); 3063 3064 /* 3065 * SiS900 (at least SiS963) requires us to register the address of 3066 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3067 */ 3068 crc = 0x0ed423f9; 3069 3070 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3071 SIP_SIS900_REV(sc, SIS_REV_960) || 3072 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3073 /* Just want the 8 most significant bits. */ 3074 crc >>= 24; 3075 } else { 3076 /* Just want the 7 most significant bits. */ 3077 crc >>= 25; 3078 } 3079 3080 /* Set the corresponding bit in the hash table. */ 3081 mchash[crc >> 4] |= 1 << (crc & 0xf); 3082 3083 ETHER_FIRST_MULTI(step, ec, enm); 3084 while (enm != NULL) { 3085 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3086 /* 3087 * We must listen to a range of multicast addresses. 3088 * For now, just accept all multicasts, rather than 3089 * trying to set only those filter bits needed to match 3090 * the range. (At this time, the only use of address 3091 * ranges is for IP multicast routing, for which the 3092 * range is big enough to require all bits set.) 3093 */ 3094 goto allmulti; 3095 } 3096 3097 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3098 3099 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3100 SIP_SIS900_REV(sc, SIS_REV_960) || 3101 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3102 /* Just want the 8 most significant bits. */ 3103 crc >>= 24; 3104 } else { 3105 /* Just want the 7 most significant bits. */ 3106 crc >>= 25; 3107 } 3108 3109 /* Set the corresponding bit in the hash table. */ 3110 mchash[crc >> 4] |= 1 << (crc & 0xf); 3111 3112 ETHER_NEXT_MULTI(step, enm); 3113 } 3114 3115 ifp->if_flags &= ~IFF_ALLMULTI; 3116 goto setit; 3117 3118 allmulti: 3119 ifp->if_flags |= IFF_ALLMULTI; 3120 sc->sc_rfcr |= RFCR_AAM; 3121 3122 setit: 3123 #define FILTER_EMIT(addr, data) \ 3124 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3125 delay(1); \ 3126 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3127 delay(1) 3128 3129 /* 3130 * Disable receive filter, and program the node address. 3131 */ 3132 cp = CLLADDR(ifp->if_sadl); 3133 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3134 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3135 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3136 3137 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3138 /* 3139 * Program the multicast hash table. 3140 */ 3141 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3142 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3143 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3144 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3145 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3146 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3147 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3148 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3149 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3150 SIP_SIS900_REV(sc, SIS_REV_960) || 3151 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3152 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3153 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3154 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3155 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3156 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3157 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3158 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3159 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3160 } 3161 } 3162 #undef FILTER_EMIT 3163 3164 /* 3165 * Re-enable the receiver filter. 3166 */ 3167 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3168 } 3169 #endif /* ! DP83820 */ 3170 3171 /* 3172 * sip_dp83815_set_filter: 3173 * 3174 * Set up the receive filter. 3175 */ 3176 static void 3177 SIP_DECL(dp83815_set_filter)(struct sip_softc *sc) 3178 { 3179 bus_space_tag_t st = sc->sc_st; 3180 bus_space_handle_t sh = sc->sc_sh; 3181 struct ethercom *ec = &sc->sc_ethercom; 3182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3183 struct ether_multi *enm; 3184 const u_int8_t *cp; 3185 struct ether_multistep step; 3186 u_int32_t crc, hash, slot, bit; 3187 #ifdef DP83820 3188 #define MCHASH_NWORDS 128 3189 #else 3190 #define MCHASH_NWORDS 32 3191 #endif /* DP83820 */ 3192 u_int16_t mchash[MCHASH_NWORDS]; 3193 int i; 3194 3195 /* 3196 * Initialize the prototype RFCR. 3197 * Enable the receive filter, and accept on 3198 * Perfect (destination address) Match 3199 * If IFF_BROADCAST, also accept all broadcast packets. 3200 * If IFF_PROMISC, accept all unicast packets (and later, set 3201 * IFF_ALLMULTI and accept all multicast, too). 3202 */ 3203 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3204 if (ifp->if_flags & IFF_BROADCAST) 3205 sc->sc_rfcr |= RFCR_AAB; 3206 if (ifp->if_flags & IFF_PROMISC) { 3207 sc->sc_rfcr |= RFCR_AAP; 3208 goto allmulti; 3209 } 3210 3211 #ifdef DP83820 3212 /* 3213 * Set up the DP83820 multicast address filter by passing all multicast 3214 * addresses through a CRC generator, and then using the high-order 3215 * 11 bits as an index into the 2048 bit multicast hash table. The 3216 * high-order 7 bits select the slot, while the low-order 4 bits 3217 * select the bit within the slot. Note that only the low 16-bits 3218 * of each filter word are used, and there are 128 filter words. 3219 */ 3220 #else 3221 /* 3222 * Set up the DP83815 multicast address filter by passing all multicast 3223 * addresses through a CRC generator, and then using the high-order 3224 * 9 bits as an index into the 512 bit multicast hash table. The 3225 * high-order 5 bits select the slot, while the low-order 4 bits 3226 * select the bit within the slot. Note that only the low 16-bits 3227 * of each filter word are used, and there are 32 filter words. 3228 */ 3229 #endif /* DP83820 */ 3230 3231 memset(mchash, 0, sizeof(mchash)); 3232 3233 ifp->if_flags &= ~IFF_ALLMULTI; 3234 ETHER_FIRST_MULTI(step, ec, enm); 3235 if (enm == NULL) 3236 goto setit; 3237 while (enm != NULL) { 3238 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3239 /* 3240 * We must listen to a range of multicast addresses. 3241 * For now, just accept all multicasts, rather than 3242 * trying to set only those filter bits needed to match 3243 * the range. (At this time, the only use of address 3244 * ranges is for IP multicast routing, for which the 3245 * range is big enough to require all bits set.) 3246 */ 3247 goto allmulti; 3248 } 3249 3250 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3251 3252 #ifdef DP83820 3253 /* Just want the 11 most significant bits. */ 3254 hash = crc >> 21; 3255 #else 3256 /* Just want the 9 most significant bits. */ 3257 hash = crc >> 23; 3258 #endif /* DP83820 */ 3259 3260 slot = hash >> 4; 3261 bit = hash & 0xf; 3262 3263 /* Set the corresponding bit in the hash table. */ 3264 mchash[slot] |= 1 << bit; 3265 3266 ETHER_NEXT_MULTI(step, enm); 3267 } 3268 sc->sc_rfcr |= RFCR_MHEN; 3269 goto setit; 3270 3271 allmulti: 3272 ifp->if_flags |= IFF_ALLMULTI; 3273 sc->sc_rfcr |= RFCR_AAM; 3274 3275 setit: 3276 #define FILTER_EMIT(addr, data) \ 3277 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3278 delay(1); \ 3279 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3280 delay(1) 3281 3282 /* 3283 * Disable receive filter, and program the node address. 3284 */ 3285 cp = CLLADDR(ifp->if_sadl); 3286 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3287 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3288 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3289 3290 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3291 /* 3292 * Program the multicast hash table. 3293 */ 3294 for (i = 0; i < MCHASH_NWORDS; i++) { 3295 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3296 mchash[i]); 3297 } 3298 } 3299 #undef FILTER_EMIT 3300 #undef MCHASH_NWORDS 3301 3302 /* 3303 * Re-enable the receiver filter. 3304 */ 3305 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3306 } 3307 3308 #if defined(DP83820) 3309 /* 3310 * sip_dp83820_mii_readreg: [mii interface function] 3311 * 3312 * Read a PHY register on the MII of the DP83820. 3313 */ 3314 static int 3315 SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg) 3316 { 3317 struct sip_softc *sc = (void *) self; 3318 3319 if (sc->sc_cfg & CFG_TBI_EN) { 3320 bus_addr_t tbireg; 3321 int rv; 3322 3323 if (phy != 0) 3324 return (0); 3325 3326 switch (reg) { 3327 case MII_BMCR: tbireg = SIP_TBICR; break; 3328 case MII_BMSR: tbireg = SIP_TBISR; break; 3329 case MII_ANAR: tbireg = SIP_TANAR; break; 3330 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3331 case MII_ANER: tbireg = SIP_TANER; break; 3332 case MII_EXTSR: 3333 /* 3334 * Don't even bother reading the TESR register. 3335 * The manual documents that the device has 3336 * 1000baseX full/half capability, but the 3337 * register itself seems read back 0 on some 3338 * boards. Just hard-code the result. 3339 */ 3340 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3341 3342 default: 3343 return (0); 3344 } 3345 3346 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3347 if (tbireg == SIP_TBISR) { 3348 /* LINK and ACOMP are switched! */ 3349 int val = rv; 3350 3351 rv = 0; 3352 if (val & TBISR_MR_LINK_STATUS) 3353 rv |= BMSR_LINK; 3354 if (val & TBISR_MR_AN_COMPLETE) 3355 rv |= BMSR_ACOMP; 3356 3357 /* 3358 * The manual claims this register reads back 0 3359 * on hard and soft reset. But we want to let 3360 * the gentbi driver know that we support auto- 3361 * negotiation, so hard-code this bit in the 3362 * result. 3363 */ 3364 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3365 } 3366 3367 return (rv); 3368 } 3369 3370 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3371 phy, reg)); 3372 } 3373 3374 /* 3375 * sip_dp83820_mii_writereg: [mii interface function] 3376 * 3377 * Write a PHY register on the MII of the DP83820. 3378 */ 3379 static void 3380 SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val) 3381 { 3382 struct sip_softc *sc = (void *) self; 3383 3384 if (sc->sc_cfg & CFG_TBI_EN) { 3385 bus_addr_t tbireg; 3386 3387 if (phy != 0) 3388 return; 3389 3390 switch (reg) { 3391 case MII_BMCR: tbireg = SIP_TBICR; break; 3392 case MII_ANAR: tbireg = SIP_TANAR; break; 3393 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3394 default: 3395 return; 3396 } 3397 3398 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3399 return; 3400 } 3401 3402 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3403 phy, reg, val); 3404 } 3405 3406 /* 3407 * sip_dp83820_mii_statchg: [mii interface function] 3408 * 3409 * Callback from MII layer when media changes. 3410 */ 3411 static void 3412 SIP_DECL(dp83820_mii_statchg)(struct device *self) 3413 { 3414 struct sip_softc *sc = (struct sip_softc *) self; 3415 struct mii_data *mii = &sc->sc_mii; 3416 u_int32_t cfg, pcr; 3417 3418 /* 3419 * Get flow control negotiation result. 3420 */ 3421 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3422 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3423 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3424 mii->mii_media_active &= ~IFM_ETH_FMASK; 3425 } 3426 3427 /* 3428 * Update TXCFG for full-duplex operation. 3429 */ 3430 if ((mii->mii_media_active & IFM_FDX) != 0) 3431 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3432 else 3433 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3434 3435 /* 3436 * Update RXCFG for full-duplex or loopback. 3437 */ 3438 if ((mii->mii_media_active & IFM_FDX) != 0 || 3439 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3440 sc->sc_rxcfg |= RXCFG_ATX; 3441 else 3442 sc->sc_rxcfg &= ~RXCFG_ATX; 3443 3444 /* 3445 * Update CFG for MII/GMII. 3446 */ 3447 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3448 cfg = sc->sc_cfg | CFG_MODE_1000; 3449 else 3450 cfg = sc->sc_cfg; 3451 3452 /* 3453 * 802.3x flow control. 3454 */ 3455 pcr = 0; 3456 if (sc->sc_flowflags & IFM_FLOW) { 3457 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3458 pcr |= sc->sc_rx_flow_thresh; 3459 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3460 pcr |= PCR_PSEN | PCR_PS_MCAST; 3461 } 3462 3463 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3464 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3465 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3466 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3467 } 3468 #endif /* ! DP83820 */ 3469 3470 /* 3471 * sip_mii_bitbang_read: [mii bit-bang interface function] 3472 * 3473 * Read the MII serial port for the MII bit-bang module. 3474 */ 3475 static u_int32_t 3476 SIP_DECL(mii_bitbang_read)(struct device *self) 3477 { 3478 struct sip_softc *sc = (void *) self; 3479 3480 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3481 } 3482 3483 /* 3484 * sip_mii_bitbang_write: [mii big-bang interface function] 3485 * 3486 * Write the MII serial port for the MII bit-bang module. 3487 */ 3488 static void 3489 SIP_DECL(mii_bitbang_write)(struct device *self, u_int32_t val) 3490 { 3491 struct sip_softc *sc = (void *) self; 3492 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3494 } 3495 3496 #ifndef DP83820 3497 /* 3498 * sip_sis900_mii_readreg: [mii interface function] 3499 * 3500 * Read a PHY register on the MII. 3501 */ 3502 static int 3503 SIP_DECL(sis900_mii_readreg)(struct device *self, int phy, int reg) 3504 { 3505 struct sip_softc *sc = (struct sip_softc *) self; 3506 u_int32_t enphy; 3507 3508 /* 3509 * The PHY of recent SiS chipsets is accessed through bitbang 3510 * operations. 3511 */ 3512 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3513 return (mii_bitbang_readreg(self, &SIP_DECL(mii_bitbang_ops), 3514 phy, reg)); 3515 3516 #ifndef SIS900_MII_RESTRICT 3517 /* 3518 * The SiS 900 has only an internal PHY on the MII. Only allow 3519 * MII address 0. 3520 */ 3521 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3522 return (0); 3523 #endif 3524 3525 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3526 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3527 ENPHY_RWCMD | ENPHY_ACCESS); 3528 do { 3529 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3530 } while (enphy & ENPHY_ACCESS); 3531 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3532 } 3533 3534 /* 3535 * sip_sis900_mii_writereg: [mii interface function] 3536 * 3537 * Write a PHY register on the MII. 3538 */ 3539 static void 3540 SIP_DECL(sis900_mii_writereg)(struct device *self, int phy, int reg, int val) 3541 { 3542 struct sip_softc *sc = (struct sip_softc *) self; 3543 u_int32_t enphy; 3544 3545 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3546 mii_bitbang_writereg(self, &SIP_DECL(mii_bitbang_ops), 3547 phy, reg, val); 3548 return; 3549 } 3550 3551 #ifndef SIS900_MII_RESTRICT 3552 /* 3553 * The SiS 900 has only an internal PHY on the MII. Only allow 3554 * MII address 0. 3555 */ 3556 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3557 return; 3558 #endif 3559 3560 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3561 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3562 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3563 do { 3564 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3565 } while (enphy & ENPHY_ACCESS); 3566 } 3567 3568 /* 3569 * sip_sis900_mii_statchg: [mii interface function] 3570 * 3571 * Callback from MII layer when media changes. 3572 */ 3573 static void 3574 SIP_DECL(sis900_mii_statchg)(struct device *self) 3575 { 3576 struct sip_softc *sc = (struct sip_softc *) self; 3577 struct mii_data *mii = &sc->sc_mii; 3578 u_int32_t flowctl; 3579 3580 /* 3581 * Get flow control negotiation result. 3582 */ 3583 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3584 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3585 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3586 mii->mii_media_active &= ~IFM_ETH_FMASK; 3587 } 3588 3589 /* 3590 * Update TXCFG for full-duplex operation. 3591 */ 3592 if ((mii->mii_media_active & IFM_FDX) != 0) 3593 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3594 else 3595 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3596 3597 /* 3598 * Update RXCFG for full-duplex or loopback. 3599 */ 3600 if ((mii->mii_media_active & IFM_FDX) != 0 || 3601 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3602 sc->sc_rxcfg |= RXCFG_ATX; 3603 else 3604 sc->sc_rxcfg &= ~RXCFG_ATX; 3605 3606 /* 3607 * Update IMR for use of 802.3x flow control. 3608 */ 3609 if (sc->sc_flowflags & IFM_FLOW) { 3610 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3611 flowctl = FLOWCTL_FLOWEN; 3612 } else { 3613 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3614 flowctl = 0; 3615 } 3616 3617 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3618 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3619 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3620 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3621 } 3622 3623 /* 3624 * sip_dp83815_mii_readreg: [mii interface function] 3625 * 3626 * Read a PHY register on the MII. 3627 */ 3628 static int 3629 SIP_DECL(dp83815_mii_readreg)(struct device *self, int phy, int reg) 3630 { 3631 struct sip_softc *sc = (struct sip_softc *) self; 3632 u_int32_t val; 3633 3634 /* 3635 * The DP83815 only has an internal PHY. Only allow 3636 * MII address 0. 3637 */ 3638 if (phy != 0) 3639 return (0); 3640 3641 /* 3642 * Apparently, after a reset, the DP83815 can take a while 3643 * to respond. During this recovery period, the BMSR returns 3644 * a value of 0. Catch this -- it's not supposed to happen 3645 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3646 * PHY to come back to life. 3647 * 3648 * This works out because the BMSR is the first register 3649 * read during the PHY probe process. 3650 */ 3651 do { 3652 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3653 } while (reg == MII_BMSR && val == 0); 3654 3655 return (val & 0xffff); 3656 } 3657 3658 /* 3659 * sip_dp83815_mii_writereg: [mii interface function] 3660 * 3661 * Write a PHY register to the MII. 3662 */ 3663 static void 3664 SIP_DECL(dp83815_mii_writereg)(struct device *self, int phy, int reg, int val) 3665 { 3666 struct sip_softc *sc = (struct sip_softc *) self; 3667 3668 /* 3669 * The DP83815 only has an internal PHY. Only allow 3670 * MII address 0. 3671 */ 3672 if (phy != 0) 3673 return; 3674 3675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3676 } 3677 3678 /* 3679 * sip_dp83815_mii_statchg: [mii interface function] 3680 * 3681 * Callback from MII layer when media changes. 3682 */ 3683 static void 3684 SIP_DECL(dp83815_mii_statchg)(struct device *self) 3685 { 3686 struct sip_softc *sc = (struct sip_softc *) self; 3687 3688 /* 3689 * Update TXCFG for full-duplex operation. 3690 */ 3691 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3692 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3693 else 3694 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3695 3696 /* 3697 * Update RXCFG for full-duplex or loopback. 3698 */ 3699 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3700 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3701 sc->sc_rxcfg |= RXCFG_ATX; 3702 else 3703 sc->sc_rxcfg &= ~RXCFG_ATX; 3704 3705 /* 3706 * XXX 802.3x flow control. 3707 */ 3708 3709 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3710 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3711 3712 /* 3713 * Some DP83815s experience problems when used with short 3714 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3715 * sequence adjusts the DSP's signal attenuation to fix the 3716 * problem. 3717 */ 3718 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3719 uint32_t reg; 3720 3721 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3722 3723 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3724 reg &= 0x0fff; 3725 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3726 delay(100); 3727 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3728 reg &= 0x00ff; 3729 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3730 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3731 0x00e8); 3732 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3733 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3734 reg | 0x20); 3735 } 3736 3737 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3738 } 3739 } 3740 #endif /* DP83820 */ 3741 3742 #if defined(DP83820) 3743 static void 3744 SIP_DECL(dp83820_read_macaddr)(struct sip_softc *sc, 3745 const struct pci_attach_args *pa, u_int8_t *enaddr) 3746 { 3747 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3748 u_int8_t cksum, *e, match; 3749 int i; 3750 3751 /* 3752 * EEPROM data format for the DP83820 can be found in 3753 * the DP83820 manual, section 4.2.4. 3754 */ 3755 3756 SIP_DECL(read_eeprom)(sc, 0, 3757 sizeof(eeprom_data) / sizeof(eeprom_data[0]), eeprom_data); 3758 3759 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3760 match = ~(match - 1); 3761 3762 cksum = 0x55; 3763 e = (u_int8_t *) eeprom_data; 3764 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3765 cksum += *e++; 3766 3767 if (cksum != match) 3768 printf("%s: Checksum (%x) mismatch (%x)", 3769 sc->sc_dev.dv_xname, cksum, match); 3770 3771 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3772 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3773 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3774 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3775 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3776 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3777 } 3778 #else /* ! DP83820 */ 3779 static void 3780 SIP_DECL(sis900_eeprom_delay)(struct sip_softc *sc) 3781 { 3782 int i; 3783 3784 /* 3785 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3786 * a reason, but I don't know it. 3787 */ 3788 for (i = 0; i < 10; i++) 3789 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3790 } 3791 3792 static void 3793 SIP_DECL(sis900_read_macaddr)(struct sip_softc *sc, 3794 const struct pci_attach_args *pa, u_int8_t *enaddr) 3795 { 3796 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3797 3798 switch (sc->sc_rev) { 3799 case SIS_REV_630S: 3800 case SIS_REV_630E: 3801 case SIS_REV_630EA1: 3802 case SIS_REV_630ET: 3803 case SIS_REV_635: 3804 /* 3805 * The MAC address for the on-board Ethernet of 3806 * the SiS 630 chipset is in the NVRAM. Kick 3807 * the chip into re-loading it from NVRAM, and 3808 * read the MAC address out of the filter registers. 3809 */ 3810 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3811 3812 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3813 RFCR_RFADDR_NODE0); 3814 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3815 0xffff; 3816 3817 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3818 RFCR_RFADDR_NODE2); 3819 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3820 0xffff; 3821 3822 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3823 RFCR_RFADDR_NODE4); 3824 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3825 0xffff; 3826 break; 3827 3828 case SIS_REV_960: 3829 { 3830 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3831 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3832 3833 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3834 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3835 3836 int waittime, i; 3837 3838 /* Allow to read EEPROM from LAN. It is shared 3839 * between a 1394 controller and the NIC and each 3840 * time we access it, we need to set SIS_EECMD_REQ. 3841 */ 3842 SIS_SET_EROMAR(sc, EROMAR_REQ); 3843 3844 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3845 /* Force EEPROM to idle state. */ 3846 3847 /* 3848 * XXX-cube This is ugly. I'll look for docs about it. 3849 */ 3850 SIS_SET_EROMAR(sc, EROMAR_EECS); 3851 SIP_DECL(sis900_eeprom_delay)(sc); 3852 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3853 SIS_SET_EROMAR(sc, EROMAR_EESK); 3854 SIP_DECL(sis900_eeprom_delay)(sc); 3855 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3856 SIP_DECL(sis900_eeprom_delay)(sc); 3857 } 3858 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3859 SIP_DECL(sis900_eeprom_delay)(sc); 3860 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3861 3862 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3863 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3864 sizeof(myea) / sizeof(myea[0]), myea); 3865 break; 3866 } 3867 DELAY(1); 3868 } 3869 3870 /* 3871 * Set SIS_EECTL_CLK to high, so a other master 3872 * can operate on the i2c bus. 3873 */ 3874 SIS_SET_EROMAR(sc, EROMAR_EESK); 3875 3876 /* Refuse EEPROM access by LAN */ 3877 SIS_SET_EROMAR(sc, EROMAR_DONE); 3878 } break; 3879 3880 default: 3881 SIP_DECL(read_eeprom)(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3882 sizeof(myea) / sizeof(myea[0]), myea); 3883 } 3884 3885 enaddr[0] = myea[0] & 0xff; 3886 enaddr[1] = myea[0] >> 8; 3887 enaddr[2] = myea[1] & 0xff; 3888 enaddr[3] = myea[1] >> 8; 3889 enaddr[4] = myea[2] & 0xff; 3890 enaddr[5] = myea[2] >> 8; 3891 } 3892 3893 /* Table and macro to bit-reverse an octet. */ 3894 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3895 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3896 3897 static void 3898 SIP_DECL(dp83815_read_macaddr)(struct sip_softc *sc, 3899 const struct pci_attach_args *pa, u_int8_t *enaddr) 3900 { 3901 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3902 u_int8_t cksum, *e, match; 3903 int i; 3904 3905 SIP_DECL(read_eeprom)(sc, 0, sizeof(eeprom_data) / 3906 sizeof(eeprom_data[0]), eeprom_data); 3907 3908 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3909 match = ~(match - 1); 3910 3911 cksum = 0x55; 3912 e = (u_int8_t *) eeprom_data; 3913 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3914 cksum += *e++; 3915 } 3916 if (cksum != match) { 3917 printf("%s: Checksum (%x) mismatch (%x)", 3918 sc->sc_dev.dv_xname, cksum, match); 3919 } 3920 3921 /* 3922 * Unrolled because it makes slightly more sense this way. 3923 * The DP83815 stores the MAC address in bit 0 of word 6 3924 * through bit 15 of word 8. 3925 */ 3926 ea = &eeprom_data[6]; 3927 enaddr[0] = ((*ea & 0x1) << 7); 3928 ea++; 3929 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3930 enaddr[1] = ((*ea & 0x1FE) >> 1); 3931 enaddr[2] = ((*ea & 0x1) << 7); 3932 ea++; 3933 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3934 enaddr[3] = ((*ea & 0x1FE) >> 1); 3935 enaddr[4] = ((*ea & 0x1) << 7); 3936 ea++; 3937 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3938 enaddr[5] = ((*ea & 0x1FE) >> 1); 3939 3940 /* 3941 * In case that's not weird enough, we also need to reverse 3942 * the bits in each byte. This all actually makes more sense 3943 * if you think about the EEPROM storage as an array of bits 3944 * being shifted into bytes, but that's not how we're looking 3945 * at it here... 3946 */ 3947 for (i = 0; i < 6 ;i++) 3948 enaddr[i] = bbr(enaddr[i]); 3949 } 3950 #endif /* DP83820 */ 3951 3952 /* 3953 * sip_mediastatus: [ifmedia interface function] 3954 * 3955 * Get the current interface media status. 3956 */ 3957 static void 3958 SIP_DECL(mediastatus)(struct ifnet *ifp, struct ifmediareq *ifmr) 3959 { 3960 struct sip_softc *sc = ifp->if_softc; 3961 3962 ether_mediastatus(ifp, ifmr); 3963 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3964 sc->sc_flowflags; 3965 } 3966
Indexes created Tue Sep 30 11:09:46 GMT 2025