if_sip.c revision 1.115.8.2
1 /* $NetBSD: if_sip.c,v 1.115.8.2 2008/01/10 23:44:24 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.115.8.2 2008/01/10 23:44:24 bouyer Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 /* 130 * Transmit descriptor list size. This is arbitrary, but allocate 131 * enough descriptors for 128 pending transmissions, and 8 segments 132 * per packet (64 for DP83820 for jumbo frames). 133 * 134 * This MUST work out to a power of 2. 135 */ 136 #define GSIP_NTXSEGS_ALLOC 16 137 #define SIP_NTXSEGS_ALLOC 8 138 139 #define SIP_TXQUEUELEN 256 140 #define MAX_SIP_NTXDESC \ 141 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer per incoming 145 * packet, so this logic is a little simpler. 146 * 147 * Actually, on the DP83820, we allow the packet to consume more than 148 * one buffer, in order to support jumbo Ethernet frames. In that 149 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 150 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 151 * so we'd better be quick about handling receive interrupts. 152 */ 153 #define GSIP_NRXDESC 256 154 #define SIP_NRXDESC 128 155 156 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 157 158 /* 159 * Control structures are DMA'd to the SiS900 chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct sip_control_data { 164 /* 165 * The transmit descriptors. 166 */ 167 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 168 169 /* 170 * The receive descriptors. 171 */ 172 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 173 }; 174 175 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 176 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 177 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 178 179 /* 180 * Software state for transmit jobs. 181 */ 182 struct sip_txsoft { 183 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t txs_dmamap; /* our DMA map */ 185 int txs_firstdesc; /* first descriptor in packet */ 186 int txs_lastdesc; /* last descriptor in packet */ 187 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 188 }; 189 190 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 191 192 /* 193 * Software state for receive jobs. 194 */ 195 struct sip_rxsoft { 196 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t rxs_dmamap; /* our DMA map */ 198 }; 199 200 enum sip_attach_stage { 201 SIP_ATTACH_FIN = 0 202 , SIP_ATTACH_CREATE_RXMAP 203 , SIP_ATTACH_CREATE_TXMAP 204 , SIP_ATTACH_LOAD_MAP 205 , SIP_ATTACH_CREATE_MAP 206 , SIP_ATTACH_MAP_MEM 207 , SIP_ATTACH_ALLOC_MEM 208 , SIP_ATTACH_INTR 209 , SIP_ATTACH_MAP 210 }; 211 212 /* 213 * Software state per device. 214 */ 215 struct sip_softc { 216 struct device sc_dev; /* generic device information */ 217 bus_space_tag_t sc_st; /* bus space tag */ 218 bus_space_handle_t sc_sh; /* bus space handle */ 219 bus_size_t sc_sz; /* bus space size */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t sc_pc; 222 bus_dma_segment_t sc_seg; 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 225 const struct sip_product *sc_model; /* which model are we? */ 226 int sc_gigabit; /* 1: 83820, 0: other */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 callout_t sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 262 struct evcnt sc_ev_rxpause; /* PAUSE received */ 263 /* DP83820 only */ 264 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 265 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 266 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 267 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 268 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 269 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 270 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 271 #endif /* SIP_EVENT_COUNTERS */ 272 273 u_int32_t sc_txcfg; /* prototype TXCFG register */ 274 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 275 u_int32_t sc_imr; /* prototype IMR register */ 276 u_int32_t sc_rfcr; /* prototype RFCR register */ 277 278 u_int32_t sc_cfg; /* prototype CFG register */ 279 280 u_int32_t sc_gpior; /* prototype GPIOR register */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flowflags; /* 802.3x flow control flags */ 288 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 289 int sc_paused; /* paused indication */ 290 291 int sc_txfree; /* number of free Tx descriptors */ 292 int sc_txnext; /* next ready Tx descriptor */ 293 int sc_txwin; /* Tx descriptors since last intr */ 294 295 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 296 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 297 298 /* values of interface state at last init */ 299 struct { 300 /* if_capenable */ 301 uint64_t if_capenable; 302 /* ec_capenable */ 303 int ec_capenable; 304 /* VLAN_ATTACHED */ 305 int is_vlan; 306 } sc_prev; 307 308 short sc_if_flags; 309 310 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 311 int sc_rxdiscard; 312 int sc_rxlen; 313 struct mbuf *sc_rxhead; 314 struct mbuf *sc_rxtail; 315 struct mbuf **sc_rxtailp; 316 317 int sc_ntxdesc; 318 int sc_ntxdesc_mask; 319 320 int sc_nrxdesc_mask; 321 322 const struct sip_parm { 323 const struct sip_regs { 324 int r_rxcfg; 325 int r_txcfg; 326 } p_regs; 327 328 const struct sip_bits { 329 uint32_t b_txcfg_mxdma_8; 330 uint32_t b_txcfg_mxdma_16; 331 uint32_t b_txcfg_mxdma_32; 332 uint32_t b_txcfg_mxdma_64; 333 uint32_t b_txcfg_mxdma_128; 334 uint32_t b_txcfg_mxdma_256; 335 uint32_t b_txcfg_mxdma_512; 336 uint32_t b_txcfg_flth_mask; 337 uint32_t b_txcfg_drth_mask; 338 339 uint32_t b_rxcfg_mxdma_8; 340 uint32_t b_rxcfg_mxdma_16; 341 uint32_t b_rxcfg_mxdma_32; 342 uint32_t b_rxcfg_mxdma_64; 343 uint32_t b_rxcfg_mxdma_128; 344 uint32_t b_rxcfg_mxdma_256; 345 uint32_t b_rxcfg_mxdma_512; 346 347 uint32_t b_isr_txrcmp; 348 uint32_t b_isr_rxrcmp; 349 uint32_t b_isr_dperr; 350 uint32_t b_isr_sserr; 351 uint32_t b_isr_rmabt; 352 uint32_t b_isr_rtabt; 353 354 uint32_t b_cmdsts_size_mask; 355 } p_bits; 356 int p_filtmem; 357 int p_rxbuf_len; 358 bus_size_t p_tx_dmamap_size; 359 int p_ntxsegs; 360 int p_ntxsegs_alloc; 361 int p_nrxdesc; 362 } *sc_parm; 363 364 void (*sc_rxintr)(struct sip_softc *); 365 366 #if NRND > 0 367 rndsource_element_t rnd_source; /* random source */ 368 #endif 369 }; 370 371 #define sc_bits sc_parm->p_bits 372 #define sc_regs sc_parm->p_regs 373 374 static const struct sip_parm sip_parm = { 375 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 376 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 377 , .p_tx_dmamap_size = MCLBYTES 378 , .p_ntxsegs = 16 379 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 380 , .p_nrxdesc = SIP_NRXDESC 381 , .p_bits = { 382 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 383 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 384 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 385 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 386 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 387 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 388 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 389 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 390 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 391 392 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 393 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 394 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 395 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 396 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 397 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 398 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 399 400 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 401 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 402 , .b_isr_dperr = 0x00800000 /* detected parity error */ 403 , .b_isr_sserr = 0x00400000 /* signalled system error */ 404 , .b_isr_rmabt = 0x00200000 /* received master abort */ 405 , .b_isr_rtabt = 0x00100000 /* received target abort */ 406 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 407 } 408 , .p_regs = { 409 .r_rxcfg = OTHER_SIP_RXCFG, 410 .r_txcfg = OTHER_SIP_TXCFG 411 } 412 }, gsip_parm = { 413 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 414 , .p_rxbuf_len = MCLBYTES - 8 415 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 416 , .p_ntxsegs = 64 417 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 418 , .p_nrxdesc = GSIP_NRXDESC 419 , .p_bits = { 420 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 421 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 422 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 423 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 424 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 425 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 426 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 427 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 428 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 429 430 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 431 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 432 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 433 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 434 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 435 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 436 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 437 438 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 439 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 440 , .b_isr_dperr = 0x00100000 /* detected parity error */ 441 , .b_isr_sserr = 0x00080000 /* signalled system error */ 442 , .b_isr_rmabt = 0x00040000 /* received master abort */ 443 , .b_isr_rtabt = 0x00020000 /* received target abort */ 444 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 445 } 446 , .p_regs = { 447 .r_rxcfg = DP83820_SIP_RXCFG, 448 .r_txcfg = DP83820_SIP_TXCFG 449 } 450 }; 451 452 static inline int 453 sip_nexttx(const struct sip_softc *sc, int x) 454 { 455 return (x + 1) & sc->sc_ntxdesc_mask; 456 } 457 458 static inline int 459 sip_nextrx(const struct sip_softc *sc, int x) 460 { 461 return (x + 1) & sc->sc_nrxdesc_mask; 462 } 463 464 /* 83820 only */ 465 static inline void 466 sip_rxchain_reset(struct sip_softc *sc) 467 { 468 sc->sc_rxtailp = &sc->sc_rxhead; 469 *sc->sc_rxtailp = NULL; 470 sc->sc_rxlen = 0; 471 } 472 473 /* 83820 only */ 474 static inline void 475 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 476 { 477 *sc->sc_rxtailp = sc->sc_rxtail = m; 478 sc->sc_rxtailp = &m->m_next; 479 } 480 481 #ifdef SIP_EVENT_COUNTERS 482 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 483 #else 484 #define SIP_EVCNT_INCR(ev) /* nothing */ 485 #endif 486 487 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 488 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 489 490 static inline void 491 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 492 { 493 int x, n; 494 495 x = x0; 496 n = n0; 497 498 /* If it will wrap around, sync to the end of the ring. */ 499 if (x + n > sc->sc_ntxdesc) { 500 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 501 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 502 (sc->sc_ntxdesc - x), ops); 503 n -= (sc->sc_ntxdesc - x); 504 x = 0; 505 } 506 507 /* Now sync whatever is left. */ 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 510 } 511 512 static inline void 513 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 514 { 515 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 516 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 517 } 518 519 #if 0 520 #ifdef DP83820 521 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 522 u_int32_t sipd_cmdsts; /* command/status word */ 523 #else 524 u_int32_t sipd_cmdsts; /* command/status word */ 525 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 526 #endif /* DP83820 */ 527 #endif /* 0 */ 528 529 static inline volatile uint32_t * 530 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 531 { 532 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 533 } 534 535 static inline volatile uint32_t * 536 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 537 { 538 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 539 } 540 541 static inline void 542 sip_init_rxdesc(struct sip_softc *sc, int x) 543 { 544 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 545 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 546 547 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 548 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 549 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 550 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 551 sipd->sipd_extsts = 0; 552 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 553 } 554 555 #define SIP_CHIP_VERS(sc, v, p, r) \ 556 ((sc)->sc_model->sip_vendor == (v) && \ 557 (sc)->sc_model->sip_product == (p) && \ 558 (sc)->sc_rev == (r)) 559 560 #define SIP_CHIP_MODEL(sc, v, p) \ 561 ((sc)->sc_model->sip_vendor == (v) && \ 562 (sc)->sc_model->sip_product == (p)) 563 564 #define SIP_SIS900_REV(sc, rev) \ 565 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 566 567 #define SIP_TIMEOUT 1000 568 569 static void sipcom_start(struct ifnet *); 570 static void sipcom_watchdog(struct ifnet *); 571 static int sipcom_ioctl(struct ifnet *, u_long, void *); 572 static int sipcom_init(struct ifnet *); 573 static void sipcom_stop(struct ifnet *, int); 574 575 static bool sipcom_reset(struct sip_softc *); 576 static void sipcom_rxdrain(struct sip_softc *); 577 static int sipcom_add_rxbuf(struct sip_softc *, int); 578 static void sipcom_read_eeprom(struct sip_softc *, int, int, 579 u_int16_t *); 580 static void sipcom_tick(void *); 581 582 static void sipcom_sis900_set_filter(struct sip_softc *); 583 static void sipcom_dp83815_set_filter(struct sip_softc *); 584 585 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 586 const struct pci_attach_args *, u_int8_t *); 587 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 588 static void sipcom_sis900_read_macaddr(struct sip_softc *, 589 const struct pci_attach_args *, u_int8_t *); 590 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 591 const struct pci_attach_args *, u_int8_t *); 592 593 static int sipcom_intr(void *); 594 static void sipcom_txintr(struct sip_softc *); 595 static void sip_rxintr(struct sip_softc *); 596 static void gsip_rxintr(struct sip_softc *); 597 598 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 599 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 600 static void sipcom_dp83820_mii_statchg(struct device *); 601 602 static int sipcom_sis900_mii_readreg(struct device *, int, int); 603 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 604 static void sipcom_sis900_mii_statchg(struct device *); 605 606 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 607 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 608 static void sipcom_dp83815_mii_statchg(struct device *); 609 610 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 611 612 static int sipcom_match(struct device *, struct cfdata *, void *); 613 static void sipcom_attach(struct device *, struct device *, void *); 614 static void sipcom_do_detach(device_t, enum sip_attach_stage); 615 static int sipcom_detach(device_t, int); 616 static bool sipcom_resume(device_t); 617 618 int gsip_copy_small = 0; 619 int sip_copy_small = 0; 620 621 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 622 sipcom_match, sipcom_attach, sipcom_detach, NULL); 623 CFATTACH_DECL(sip, sizeof(struct sip_softc), 624 sipcom_match, sipcom_attach, sipcom_detach, NULL); 625 626 /* 627 * Descriptions of the variants of the SiS900. 628 */ 629 struct sip_variant { 630 int (*sipv_mii_readreg)(struct device *, int, int); 631 void (*sipv_mii_writereg)(struct device *, int, int, int); 632 void (*sipv_mii_statchg)(struct device *); 633 void (*sipv_set_filter)(struct sip_softc *); 634 void (*sipv_read_macaddr)(struct sip_softc *, 635 const struct pci_attach_args *, u_int8_t *); 636 }; 637 638 static u_int32_t sipcom_mii_bitbang_read(struct device *); 639 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 640 641 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 642 sipcom_mii_bitbang_read, 643 sipcom_mii_bitbang_write, 644 { 645 EROMAR_MDIO, /* MII_BIT_MDO */ 646 EROMAR_MDIO, /* MII_BIT_MDI */ 647 EROMAR_MDC, /* MII_BIT_MDC */ 648 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 649 0, /* MII_BIT_DIR_PHY_HOST */ 650 } 651 }; 652 653 static const struct sip_variant sipcom_variant_dp83820 = { 654 sipcom_dp83820_mii_readreg, 655 sipcom_dp83820_mii_writereg, 656 sipcom_dp83820_mii_statchg, 657 sipcom_dp83815_set_filter, 658 sipcom_dp83820_read_macaddr, 659 }; 660 661 static const struct sip_variant sipcom_variant_sis900 = { 662 sipcom_sis900_mii_readreg, 663 sipcom_sis900_mii_writereg, 664 sipcom_sis900_mii_statchg, 665 sipcom_sis900_set_filter, 666 sipcom_sis900_read_macaddr, 667 }; 668 669 static const struct sip_variant sipcom_variant_dp83815 = { 670 sipcom_dp83815_mii_readreg, 671 sipcom_dp83815_mii_writereg, 672 sipcom_dp83815_mii_statchg, 673 sipcom_dp83815_set_filter, 674 sipcom_dp83815_read_macaddr, 675 }; 676 677 678 /* 679 * Devices supported by this driver. 680 */ 681 static const struct sip_product { 682 pci_vendor_id_t sip_vendor; 683 pci_product_id_t sip_product; 684 const char *sip_name; 685 const struct sip_variant *sip_variant; 686 int sip_gigabit; 687 } sipcom_products[] = { 688 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 689 "NatSemi DP83820 Gigabit Ethernet", 690 &sipcom_variant_dp83820, 1 }, 691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 692 "SiS 900 10/100 Ethernet", 693 &sipcom_variant_sis900, 0 }, 694 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 695 "SiS 7016 10/100 Ethernet", 696 &sipcom_variant_sis900, 0 }, 697 698 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 699 "NatSemi DP83815 10/100 Ethernet", 700 &sipcom_variant_dp83815, 0 }, 701 702 { 0, 0, 703 NULL, 704 NULL, 0 }, 705 }; 706 707 static const struct sip_product * 708 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 709 { 710 const struct sip_product *sip; 711 712 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 713 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 714 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 715 sip->sip_gigabit == gigabit) 716 return sip; 717 } 718 return NULL; 719 } 720 721 /* 722 * I really hate stupid hardware vendors. There's a bit in the EEPROM 723 * which indicates if the card can do 64-bit data transfers. Unfortunately, 724 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 725 * which means we try to use 64-bit data transfers on those cards if we 726 * happen to be plugged into a 32-bit slot. 727 * 728 * What we do is use this table of cards known to be 64-bit cards. If 729 * you have a 64-bit card who's subsystem ID is not listed in this table, 730 * send the output of "pcictl dump ..." of the device to me so that your 731 * card will use the 64-bit data path when plugged into a 64-bit slot. 732 * 733 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 734 * June 30, 2002 735 */ 736 static int 737 sipcom_check_64bit(const struct pci_attach_args *pa) 738 { 739 static const struct { 740 pci_vendor_id_t c64_vendor; 741 pci_product_id_t c64_product; 742 } card64[] = { 743 /* Asante GigaNIX */ 744 { 0x128a, 0x0002 }, 745 746 /* Accton EN1407-T, Planex GN-1000TE */ 747 { 0x1113, 0x1407 }, 748 749 /* Netgear GA-621 */ 750 { 0x1385, 0x621a }, 751 752 /* SMC EZ Card */ 753 { 0x10b8, 0x9462 }, 754 755 { 0, 0} 756 }; 757 pcireg_t subsys; 758 int i; 759 760 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 761 762 for (i = 0; card64[i].c64_vendor != 0; i++) { 763 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 764 PCI_PRODUCT(subsys) == card64[i].c64_product) 765 return (1); 766 } 767 768 return (0); 769 } 770 771 static int 772 sipcom_match(struct device *parent, struct cfdata *cf, void *aux) 773 { 774 struct pci_attach_args *pa = aux; 775 776 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 777 return 1; 778 779 return 0; 780 } 781 782 static void 783 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 784 { 785 u_int32_t reg; 786 int i; 787 788 /* 789 * Cause the chip to load configuration data from the EEPROM. 790 */ 791 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 792 for (i = 0; i < 10000; i++) { 793 delay(10); 794 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 795 PTSCR_EELOAD_EN) == 0) 796 break; 797 } 798 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 799 PTSCR_EELOAD_EN) { 800 printf("%s: timeout loading configuration from EEPROM\n", 801 sc->sc_dev.dv_xname); 802 return; 803 } 804 805 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 806 807 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 808 if (reg & CFG_PCI64_DET) { 809 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 810 /* 811 * Check to see if this card is 64-bit. If so, enable 64-bit 812 * data transfers. 813 * 814 * We can't use the DATA64_EN bit in the EEPROM, because 815 * vendors of 32-bit cards fail to clear that bit in many 816 * cases (yet the card still detects that it's in a 64-bit 817 * slot; go figure). 818 */ 819 if (sipcom_check_64bit(pa)) { 820 sc->sc_cfg |= CFG_DATA64_EN; 821 printf(", using 64-bit data transfers"); 822 } 823 printf("\n"); 824 } 825 826 /* 827 * XXX Need some PCI flags indicating support for 828 * XXX 64-bit addressing. 829 */ 830 #if 0 831 if (reg & CFG_M64ADDR) 832 sc->sc_cfg |= CFG_M64ADDR; 833 if (reg & CFG_T64ADDR) 834 sc->sc_cfg |= CFG_T64ADDR; 835 #endif 836 837 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 838 const char *sep = ""; 839 printf("%s: using ", sc->sc_dev.dv_xname); 840 if (reg & CFG_EXT_125) { 841 sc->sc_cfg |= CFG_EXT_125; 842 printf("%s125MHz clock", sep); 843 sep = ", "; 844 } 845 if (reg & CFG_TBI_EN) { 846 sc->sc_cfg |= CFG_TBI_EN; 847 printf("%sten-bit interface", sep); 848 sep = ", "; 849 } 850 printf("\n"); 851 } 852 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 853 (reg & CFG_MRM_DIS) != 0) 854 sc->sc_cfg |= CFG_MRM_DIS; 855 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 856 (reg & CFG_MWI_DIS) != 0) 857 sc->sc_cfg |= CFG_MWI_DIS; 858 859 /* 860 * Use the extended descriptor format on the DP83820. This 861 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 862 * checksumming. 863 */ 864 sc->sc_cfg |= CFG_EXTSTS_EN; 865 } 866 867 static int 868 sipcom_detach(device_t self, int flags) 869 { 870 int s; 871 872 s = splnet(); 873 sipcom_do_detach(self, SIP_ATTACH_FIN); 874 splx(s); 875 876 return 0; 877 } 878 879 static void 880 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 881 { 882 int i; 883 struct sip_softc *sc = device_private(self); 884 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 885 886 /* 887 * Free any resources we've allocated during attach. 888 * Do this in reverse order and fall through. 889 */ 890 switch (stage) { 891 case SIP_ATTACH_FIN: 892 sipcom_stop(ifp, 1); 893 pmf_device_deregister(self); 894 #ifdef SIP_EVENT_COUNTERS 895 /* 896 * Attach event counters. 897 */ 898 evcnt_detach(&sc->sc_ev_txforceintr); 899 evcnt_detach(&sc->sc_ev_txdstall); 900 evcnt_detach(&sc->sc_ev_txsstall); 901 evcnt_detach(&sc->sc_ev_hiberr); 902 evcnt_detach(&sc->sc_ev_rxintr); 903 evcnt_detach(&sc->sc_ev_txiintr); 904 evcnt_detach(&sc->sc_ev_txdintr); 905 if (!sc->sc_gigabit) { 906 evcnt_detach(&sc->sc_ev_rxpause); 907 } else { 908 evcnt_detach(&sc->sc_ev_txudpsum); 909 evcnt_detach(&sc->sc_ev_txtcpsum); 910 evcnt_detach(&sc->sc_ev_txipsum); 911 evcnt_detach(&sc->sc_ev_rxudpsum); 912 evcnt_detach(&sc->sc_ev_rxtcpsum); 913 evcnt_detach(&sc->sc_ev_rxipsum); 914 evcnt_detach(&sc->sc_ev_txpause); 915 evcnt_detach(&sc->sc_ev_rxpause); 916 } 917 #endif /* SIP_EVENT_COUNTERS */ 918 919 #if NRND > 0 920 rnd_detach_source(&sc->rnd_source); 921 #endif 922 923 ether_ifdetach(ifp); 924 if_detach(ifp); 925 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 926 927 /*FALLTHROUGH*/ 928 case SIP_ATTACH_CREATE_RXMAP: 929 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 930 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 931 bus_dmamap_destroy(sc->sc_dmat, 932 sc->sc_rxsoft[i].rxs_dmamap); 933 } 934 /*FALLTHROUGH*/ 935 case SIP_ATTACH_CREATE_TXMAP: 936 for (i = 0; i < SIP_TXQUEUELEN; i++) { 937 if (sc->sc_txsoft[i].txs_dmamap != NULL) 938 bus_dmamap_destroy(sc->sc_dmat, 939 sc->sc_txsoft[i].txs_dmamap); 940 } 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_LOAD_MAP: 943 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 944 /*FALLTHROUGH*/ 945 case SIP_ATTACH_CREATE_MAP: 946 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 947 /*FALLTHROUGH*/ 948 case SIP_ATTACH_MAP_MEM: 949 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 950 sizeof(struct sip_control_data)); 951 /*FALLTHROUGH*/ 952 case SIP_ATTACH_ALLOC_MEM: 953 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 954 /* FALLTHROUGH*/ 955 case SIP_ATTACH_INTR: 956 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 957 /* FALLTHROUGH*/ 958 case SIP_ATTACH_MAP: 959 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 960 break; 961 default: 962 break; 963 } 964 return; 965 } 966 967 static bool 968 sipcom_resume(device_t self) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 return sipcom_reset(sc); 973 } 974 975 static void 976 sipcom_attach(device_t parent, device_t self, void *aux) 977 { 978 struct sip_softc *sc = (struct sip_softc *) self; 979 struct pci_attach_args *pa = aux; 980 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 981 pci_chipset_tag_t pc = pa->pa_pc; 982 pci_intr_handle_t ih; 983 const char *intrstr = NULL; 984 bus_space_tag_t iot, memt; 985 bus_space_handle_t ioh, memh; 986 bus_size_t iosz, memsz; 987 int ioh_valid, memh_valid; 988 int i, rseg, error; 989 const struct sip_product *sip; 990 u_int8_t enaddr[ETHER_ADDR_LEN]; 991 pcireg_t pmreg; 992 pcireg_t memtype; 993 bus_size_t tx_dmamap_size; 994 int ntxsegs_alloc; 995 cfdata_t cf = device_cfdata(self); 996 997 callout_init(&sc->sc_tick_ch, 0); 998 999 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1000 if (sip == NULL) { 1001 printf("\n"); 1002 panic("%s: impossible", __func__); 1003 } 1004 sc->sc_gigabit = sip->sip_gigabit; 1005 1006 sc->sc_pc = pc; 1007 1008 if (sc->sc_gigabit) { 1009 sc->sc_rxintr = gsip_rxintr; 1010 sc->sc_parm = &gsip_parm; 1011 } else { 1012 sc->sc_rxintr = sip_rxintr; 1013 sc->sc_parm = &sip_parm; 1014 } 1015 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1016 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1017 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1018 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1019 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1020 1021 sc->sc_rev = PCI_REVISION(pa->pa_class); 1022 1023 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1024 1025 sc->sc_model = sip; 1026 1027 /* 1028 * XXX Work-around broken PXE firmware on some boards. 1029 * 1030 * The DP83815 shares an address decoder with the MEM BAR 1031 * and the ROM BAR. Make sure the ROM BAR is disabled, 1032 * so that memory mapped access works. 1033 */ 1034 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1035 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1036 ~PCI_MAPREG_ROM_ENABLE); 1037 1038 /* 1039 * Map the device. 1040 */ 1041 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1042 PCI_MAPREG_TYPE_IO, 0, 1043 &iot, &ioh, NULL, &iosz) == 0); 1044 if (sc->sc_gigabit) { 1045 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1046 switch (memtype) { 1047 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1048 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1049 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1050 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1051 break; 1052 default: 1053 memh_valid = 0; 1054 } 1055 } else { 1056 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1057 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1058 &memt, &memh, NULL, &memsz) == 0); 1059 } 1060 1061 if (memh_valid) { 1062 sc->sc_st = memt; 1063 sc->sc_sh = memh; 1064 sc->sc_sz = memsz; 1065 } else if (ioh_valid) { 1066 sc->sc_st = iot; 1067 sc->sc_sh = ioh; 1068 sc->sc_sz = iosz; 1069 } else { 1070 printf("%s: unable to map device registers\n", 1071 sc->sc_dev.dv_xname); 1072 return; 1073 } 1074 1075 sc->sc_dmat = pa->pa_dmat; 1076 1077 /* 1078 * Make sure bus mastering is enabled. Also make sure 1079 * Write/Invalidate is enabled if we're allowed to use it. 1080 */ 1081 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1082 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1083 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1084 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1085 pmreg | PCI_COMMAND_MASTER_ENABLE); 1086 1087 /* power up chip */ 1088 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1089 NULL)) && error != EOPNOTSUPP) { 1090 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 1091 error); 1092 return; 1093 } 1094 1095 /* 1096 * Map and establish our interrupt. 1097 */ 1098 if (pci_intr_map(pa, &ih)) { 1099 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 1100 return; 1101 } 1102 intrstr = pci_intr_string(pc, ih); 1103 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1104 if (sc->sc_ih == NULL) { 1105 printf("%s: unable to establish interrupt", 1106 sc->sc_dev.dv_xname); 1107 if (intrstr != NULL) 1108 printf(" at %s", intrstr); 1109 printf("\n"); 1110 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1111 } 1112 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1113 1114 SIMPLEQ_INIT(&sc->sc_txfreeq); 1115 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1116 1117 /* 1118 * Allocate the control data structures, and create and load the 1119 * DMA map for it. 1120 */ 1121 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1122 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1123 &rseg, 0)) != 0) { 1124 printf("%s: unable to allocate control data, error = %d\n", 1125 sc->sc_dev.dv_xname, error); 1126 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1127 } 1128 1129 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1130 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1131 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1132 printf("%s: unable to map control data, error = %d\n", 1133 sc->sc_dev.dv_xname, error); 1134 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1135 } 1136 1137 if ((error = bus_dmamap_create(sc->sc_dmat, 1138 sizeof(struct sip_control_data), 1, 1139 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1140 printf("%s: unable to create control data DMA map, " 1141 "error = %d\n", sc->sc_dev.dv_xname, error); 1142 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1143 } 1144 1145 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1146 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1147 0)) != 0) { 1148 printf("%s: unable to load control data DMA map, error = %d\n", 1149 sc->sc_dev.dv_xname, error); 1150 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1151 } 1152 1153 /* 1154 * Create the transmit buffer DMA maps. 1155 */ 1156 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1157 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1158 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1159 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1160 printf("%s: unable to create tx DMA map %d, " 1161 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1162 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1163 } 1164 } 1165 1166 /* 1167 * Create the receive buffer DMA maps. 1168 */ 1169 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1170 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1171 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1172 printf("%s: unable to create rx DMA map %d, " 1173 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1174 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1175 } 1176 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1177 } 1178 1179 /* 1180 * Reset the chip to a known state. 1181 */ 1182 sipcom_reset(sc); 1183 1184 /* 1185 * Read the Ethernet address from the EEPROM. This might 1186 * also fetch other stuff from the EEPROM and stash it 1187 * in the softc. 1188 */ 1189 sc->sc_cfg = 0; 1190 if (!sc->sc_gigabit) { 1191 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1192 SIP_SIS900_REV(sc,SIS_REV_900B)) 1193 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1194 1195 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1196 SIP_SIS900_REV(sc,SIS_REV_960) || 1197 SIP_SIS900_REV(sc,SIS_REV_900B)) 1198 sc->sc_cfg |= 1199 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1200 CFG_EDBMASTEN); 1201 } 1202 1203 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1204 1205 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1206 ether_sprintf(enaddr)); 1207 1208 /* 1209 * Initialize the configuration register: aggressive PCI 1210 * bus request algorithm, default backoff, default OW timer, 1211 * default parity error detection. 1212 * 1213 * NOTE: "Big endian mode" is useless on the SiS900 and 1214 * friends -- it affects packet data, not descriptors. 1215 */ 1216 if (sc->sc_gigabit) 1217 sipcom_dp83820_attach(sc, pa); 1218 1219 /* 1220 * Initialize our media structures and probe the MII. 1221 */ 1222 sc->sc_mii.mii_ifp = ifp; 1223 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1224 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1225 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1226 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1227 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1228 sipcom_mediastatus); 1229 1230 /* 1231 * XXX We cannot handle flow control on the DP83815. 1232 */ 1233 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1234 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1235 MII_OFFSET_ANY, 0); 1236 else 1237 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, MIIF_DOPAUSE); 1239 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1240 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1241 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1242 } else 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1244 1245 ifp = &sc->sc_ethercom.ec_if; 1246 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1247 ifp->if_softc = sc; 1248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1249 sc->sc_if_flags = ifp->if_flags; 1250 ifp->if_ioctl = sipcom_ioctl; 1251 ifp->if_start = sipcom_start; 1252 ifp->if_watchdog = sipcom_watchdog; 1253 ifp->if_init = sipcom_init; 1254 ifp->if_stop = sipcom_stop; 1255 IFQ_SET_READY(&ifp->if_snd); 1256 1257 /* 1258 * We can support 802.1Q VLAN-sized frames. 1259 */ 1260 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1261 1262 if (sc->sc_gigabit) { 1263 /* 1264 * And the DP83820 can do VLAN tagging in hardware, and 1265 * support the jumbo Ethernet MTU. 1266 */ 1267 sc->sc_ethercom.ec_capabilities |= 1268 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1269 1270 /* 1271 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1272 * in hardware. 1273 */ 1274 ifp->if_capabilities |= 1275 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1276 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1277 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1278 } 1279 1280 /* 1281 * Attach the interface. 1282 */ 1283 if_attach(ifp); 1284 ether_ifattach(ifp, enaddr); 1285 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1286 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1287 sc->sc_prev.if_capenable = ifp->if_capenable; 1288 #if NRND > 0 1289 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1290 RND_TYPE_NET, 0); 1291 #endif 1292 1293 /* 1294 * The number of bytes that must be available in 1295 * the Tx FIFO before the bus master can DMA more 1296 * data into the FIFO. 1297 */ 1298 sc->sc_tx_fill_thresh = 64 / 32; 1299 1300 /* 1301 * Start at a drain threshold of 512 bytes. We will 1302 * increase it if a DMA underrun occurs. 1303 * 1304 * XXX The minimum value of this variable should be 1305 * tuned. We may be able to improve performance 1306 * by starting with a lower value. That, however, 1307 * may trash the first few outgoing packets if the 1308 * PCI bus is saturated. 1309 */ 1310 if (sc->sc_gigabit) 1311 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1312 else 1313 sc->sc_tx_drain_thresh = 1504 / 32; 1314 1315 /* 1316 * Initialize the Rx FIFO drain threshold. 1317 * 1318 * This is in units of 8 bytes. 1319 * 1320 * We should never set this value lower than 2; 14 bytes are 1321 * required to filter the packet. 1322 */ 1323 sc->sc_rx_drain_thresh = 128 / 8; 1324 1325 #ifdef SIP_EVENT_COUNTERS 1326 /* 1327 * Attach event counters. 1328 */ 1329 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1330 NULL, sc->sc_dev.dv_xname, "txsstall"); 1331 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1332 NULL, sc->sc_dev.dv_xname, "txdstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1334 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1336 NULL, sc->sc_dev.dv_xname, "txdintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1338 NULL, sc->sc_dev.dv_xname, "txiintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1340 NULL, sc->sc_dev.dv_xname, "rxintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1342 NULL, sc->sc_dev.dv_xname, "hiberr"); 1343 if (!sc->sc_gigabit) { 1344 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1345 NULL, sc->sc_dev.dv_xname, "rxpause"); 1346 } else { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1348 NULL, sc->sc_dev.dv_xname, "rxpause"); 1349 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1350 NULL, sc->sc_dev.dv_xname, "txpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1352 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1354 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1356 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1358 NULL, sc->sc_dev.dv_xname, "txipsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1360 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1362 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1363 } 1364 #endif /* SIP_EVENT_COUNTERS */ 1365 1366 if (!pmf_device_register(self, NULL, sipcom_resume)) 1367 aprint_error_dev(self, "couldn't establish power handler\n"); 1368 else 1369 pmf_class_network_register(self, ifp); 1370 } 1371 1372 static inline void 1373 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1374 uint64_t capenable) 1375 { 1376 struct m_tag *mtag; 1377 u_int32_t extsts; 1378 #ifdef DEBUG 1379 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1380 #endif 1381 /* 1382 * If VLANs are enabled and the packet has a VLAN tag, set 1383 * up the descriptor to encapsulate the packet for us. 1384 * 1385 * This apparently has to be on the last descriptor of 1386 * the packet. 1387 */ 1388 1389 /* 1390 * Byte swapping is tricky. We need to provide the tag 1391 * in a network byte order. On a big-endian machine, 1392 * the byteorder is correct, but we need to swap it 1393 * anyway, because this will be undone by the outside 1394 * htole32(). That's why there must be an 1395 * unconditional swap instead of htons() inside. 1396 */ 1397 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1398 sc->sc_txdescs[lasttx].sipd_extsts |= 1399 htole32(EXTSTS_VPKT | 1400 (bswap16(VLAN_TAG_VALUE(mtag)) & 1401 EXTSTS_VTCI)); 1402 } 1403 1404 /* 1405 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1406 * checksumming, set up the descriptor to do this work 1407 * for us. 1408 * 1409 * This apparently has to be on the first descriptor of 1410 * the packet. 1411 * 1412 * Byte-swap constants so the compiler can optimize. 1413 */ 1414 extsts = 0; 1415 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1416 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1417 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1418 extsts |= htole32(EXTSTS_IPPKT); 1419 } 1420 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1421 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1422 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1423 extsts |= htole32(EXTSTS_TCPPKT); 1424 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1425 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1426 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1427 extsts |= htole32(EXTSTS_UDPPKT); 1428 } 1429 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1430 } 1431 1432 /* 1433 * sip_start: [ifnet interface function] 1434 * 1435 * Start packet transmission on the interface. 1436 */ 1437 static void 1438 sipcom_start(struct ifnet *ifp) 1439 { 1440 struct sip_softc *sc = ifp->if_softc; 1441 struct mbuf *m0; 1442 struct mbuf *m; 1443 struct sip_txsoft *txs; 1444 bus_dmamap_t dmamap; 1445 int error, nexttx, lasttx, seg; 1446 int ofree = sc->sc_txfree; 1447 #if 0 1448 int firsttx = sc->sc_txnext; 1449 #endif 1450 1451 /* 1452 * If we've been told to pause, don't transmit any more packets. 1453 */ 1454 if (!sc->sc_gigabit && sc->sc_paused) 1455 ifp->if_flags |= IFF_OACTIVE; 1456 1457 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1458 return; 1459 1460 /* 1461 * Loop through the send queue, setting up transmit descriptors 1462 * until we drain the queue, or use up all available transmit 1463 * descriptors. 1464 */ 1465 for (;;) { 1466 /* Get a work queue entry. */ 1467 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1468 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1469 break; 1470 } 1471 1472 /* 1473 * Grab a packet off the queue. 1474 */ 1475 IFQ_POLL(&ifp->if_snd, m0); 1476 if (m0 == NULL) 1477 break; 1478 m = NULL; 1479 1480 dmamap = txs->txs_dmamap; 1481 1482 /* 1483 * Load the DMA map. If this fails, the packet either 1484 * didn't fit in the alloted number of segments, or we 1485 * were short on resources. 1486 */ 1487 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1488 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1489 /* In the non-gigabit case, we'll copy and try again. */ 1490 if (error != 0 && !sc->sc_gigabit) { 1491 MGETHDR(m, M_DONTWAIT, MT_DATA); 1492 if (m == NULL) { 1493 printf("%s: unable to allocate Tx mbuf\n", 1494 sc->sc_dev.dv_xname); 1495 break; 1496 } 1497 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1498 if (m0->m_pkthdr.len > MHLEN) { 1499 MCLGET(m, M_DONTWAIT); 1500 if ((m->m_flags & M_EXT) == 0) { 1501 printf("%s: unable to allocate Tx " 1502 "cluster\n", sc->sc_dev.dv_xname); 1503 m_freem(m); 1504 break; 1505 } 1506 } 1507 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1508 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1509 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1510 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1511 if (error) { 1512 printf("%s: unable to load Tx buffer, " 1513 "error = %d\n", sc->sc_dev.dv_xname, error); 1514 break; 1515 } 1516 } else if (error == EFBIG) { 1517 /* 1518 * For the too-many-segments case, we simply 1519 * report an error and drop the packet, 1520 * since we can't sanely copy a jumbo packet 1521 * to a single buffer. 1522 */ 1523 printf("%s: Tx packet consumes too many " 1524 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1525 IFQ_DEQUEUE(&ifp->if_snd, m0); 1526 m_freem(m0); 1527 continue; 1528 } else if (error != 0) { 1529 /* 1530 * Short on resources, just stop for now. 1531 */ 1532 break; 1533 } 1534 1535 /* 1536 * Ensure we have enough descriptors free to describe 1537 * the packet. Note, we always reserve one descriptor 1538 * at the end of the ring as a termination point, to 1539 * prevent wrap-around. 1540 */ 1541 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1542 /* 1543 * Not enough free descriptors to transmit this 1544 * packet. We haven't committed anything yet, 1545 * so just unload the DMA map, put the packet 1546 * back on the queue, and punt. Notify the upper 1547 * layer that there are not more slots left. 1548 * 1549 * XXX We could allocate an mbuf and copy, but 1550 * XXX is it worth it? 1551 */ 1552 ifp->if_flags |= IFF_OACTIVE; 1553 bus_dmamap_unload(sc->sc_dmat, dmamap); 1554 if (m != NULL) 1555 m_freem(m); 1556 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1557 break; 1558 } 1559 1560 IFQ_DEQUEUE(&ifp->if_snd, m0); 1561 if (m != NULL) { 1562 m_freem(m0); 1563 m0 = m; 1564 } 1565 1566 /* 1567 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1568 */ 1569 1570 /* Sync the DMA map. */ 1571 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1572 BUS_DMASYNC_PREWRITE); 1573 1574 /* 1575 * Initialize the transmit descriptors. 1576 */ 1577 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1578 seg < dmamap->dm_nsegs; 1579 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1580 /* 1581 * If this is the first descriptor we're 1582 * enqueueing, don't set the OWN bit just 1583 * yet. That could cause a race condition. 1584 * We'll do it below. 1585 */ 1586 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1587 htole32(dmamap->dm_segs[seg].ds_addr); 1588 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1589 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1590 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1591 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1592 lasttx = nexttx; 1593 } 1594 1595 /* Clear the MORE bit on the last segment. */ 1596 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1597 htole32(~CMDSTS_MORE); 1598 1599 /* 1600 * If we're in the interrupt delay window, delay the 1601 * interrupt. 1602 */ 1603 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1604 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1605 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1606 htole32(CMDSTS_INTR); 1607 sc->sc_txwin = 0; 1608 } 1609 1610 if (sc->sc_gigabit) 1611 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1612 1613 /* Sync the descriptors we're using. */ 1614 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1615 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1616 1617 /* 1618 * The entire packet is set up. Give the first descrptor 1619 * to the chip now. 1620 */ 1621 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1622 htole32(CMDSTS_OWN); 1623 sip_cdtxsync(sc, sc->sc_txnext, 1, 1624 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1625 1626 /* 1627 * Store a pointer to the packet so we can free it later, 1628 * and remember what txdirty will be once the packet is 1629 * done. 1630 */ 1631 txs->txs_mbuf = m0; 1632 txs->txs_firstdesc = sc->sc_txnext; 1633 txs->txs_lastdesc = lasttx; 1634 1635 /* Advance the tx pointer. */ 1636 sc->sc_txfree -= dmamap->dm_nsegs; 1637 sc->sc_txnext = nexttx; 1638 1639 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1640 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1641 1642 #if NBPFILTER > 0 1643 /* 1644 * Pass the packet to any BPF listeners. 1645 */ 1646 if (ifp->if_bpf) 1647 bpf_mtap(ifp->if_bpf, m0); 1648 #endif /* NBPFILTER > 0 */ 1649 } 1650 1651 if (txs == NULL || sc->sc_txfree == 0) { 1652 /* No more slots left; notify upper layer. */ 1653 ifp->if_flags |= IFF_OACTIVE; 1654 } 1655 1656 if (sc->sc_txfree != ofree) { 1657 /* 1658 * Start the transmit process. Note, the manual says 1659 * that if there are no pending transmissions in the 1660 * chip's internal queue (indicated by TXE being clear), 1661 * then the driver software must set the TXDP to the 1662 * first descriptor to be transmitted. However, if we 1663 * do this, it causes serious performance degredation on 1664 * the DP83820 under load, not setting TXDP doesn't seem 1665 * to adversely affect the SiS 900 or DP83815. 1666 * 1667 * Well, I guess it wouldn't be the first time a manual 1668 * has lied -- and they could be speaking of the NULL- 1669 * terminated descriptor list case, rather than OWN- 1670 * terminated rings. 1671 */ 1672 #if 0 1673 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1674 CR_TXE) == 0) { 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1676 SIP_CDTXADDR(sc, firsttx)); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1678 } 1679 #else 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1681 #endif 1682 1683 /* Set a watchdog timer in case the chip flakes out. */ 1684 /* Gigabit autonegotiation takes 5 seconds. */ 1685 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1686 } 1687 } 1688 1689 /* 1690 * sip_watchdog: [ifnet interface function] 1691 * 1692 * Watchdog timer handler. 1693 */ 1694 static void 1695 sipcom_watchdog(struct ifnet *ifp) 1696 { 1697 struct sip_softc *sc = ifp->if_softc; 1698 1699 /* 1700 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1701 * If we get a timeout, try and sweep up transmit descriptors. 1702 * If we manage to sweep them all up, ignore the lack of 1703 * interrupt. 1704 */ 1705 sipcom_txintr(sc); 1706 1707 if (sc->sc_txfree != sc->sc_ntxdesc) { 1708 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1709 ifp->if_oerrors++; 1710 1711 /* Reset the interface. */ 1712 (void) sipcom_init(ifp); 1713 } else if (ifp->if_flags & IFF_DEBUG) 1714 printf("%s: recovered from device timeout\n", 1715 sc->sc_dev.dv_xname); 1716 1717 /* Try to get more packets going. */ 1718 sipcom_start(ifp); 1719 } 1720 1721 /* 1722 * sip_ioctl: [ifnet interface function] 1723 * 1724 * Handle control requests from the operator. 1725 */ 1726 static int 1727 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1728 { 1729 struct sip_softc *sc = ifp->if_softc; 1730 struct ifreq *ifr = (struct ifreq *)data; 1731 int s, error; 1732 1733 s = splnet(); 1734 1735 switch (cmd) { 1736 case SIOCSIFMEDIA: 1737 /* Flow control requires full-duplex mode. */ 1738 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1739 (ifr->ifr_media & IFM_FDX) == 0) 1740 ifr->ifr_media &= ~IFM_ETH_FMASK; 1741 1742 /* XXX */ 1743 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1744 ifr->ifr_media &= ~IFM_ETH_FMASK; 1745 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1746 if (sc->sc_gigabit && 1747 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1748 /* We can do both TXPAUSE and RXPAUSE. */ 1749 ifr->ifr_media |= 1750 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1751 } else if (ifr->ifr_media & IFM_FLOW) { 1752 /* 1753 * Both TXPAUSE and RXPAUSE must be set. 1754 * (SiS900 and DP83815 don't have PAUSE_ASYM 1755 * feature.) 1756 * 1757 * XXX Can SiS900 and DP83815 send PAUSE? 1758 */ 1759 ifr->ifr_media |= 1760 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1761 } 1762 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1763 } 1764 /* FALLTHROUGH */ 1765 case SIOCGIFMEDIA: 1766 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1767 break; 1768 case SIOCSIFFLAGS: 1769 /* If the interface is up and running, only modify the receive 1770 * filter when setting promiscuous or debug mode. Otherwise 1771 * fall through to ether_ioctl, which will reset the chip. 1772 */ 1773 1774 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1775 == (sc)->sc_ethercom.ec_capenable) \ 1776 && ((sc)->sc_prev.is_vlan == \ 1777 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1778 1779 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1780 1781 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1782 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1783 == (IFF_UP|IFF_RUNNING)) 1784 && ((ifp->if_flags & (~RESETIGN)) 1785 == (sc->sc_if_flags & (~RESETIGN))) 1786 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1787 /* Set up the receive filter. */ 1788 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1789 error = 0; 1790 break; 1791 #undef RESETIGN 1792 } 1793 /* FALLTHROUGH */ 1794 default: 1795 error = ether_ioctl(ifp, cmd, data); 1796 if (error == ENETRESET) { 1797 /* 1798 * Multicast list has changed; set the hardware filter 1799 * accordingly. 1800 */ 1801 if (ifp->if_flags & IFF_RUNNING) 1802 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1803 error = 0; 1804 } 1805 break; 1806 } 1807 1808 /* Try to get more packets going. */ 1809 sipcom_start(ifp); 1810 1811 sc->sc_if_flags = ifp->if_flags; 1812 splx(s); 1813 return (error); 1814 } 1815 1816 /* 1817 * sip_intr: 1818 * 1819 * Interrupt service routine. 1820 */ 1821 static int 1822 sipcom_intr(void *arg) 1823 { 1824 struct sip_softc *sc = arg; 1825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1826 u_int32_t isr; 1827 int handled = 0; 1828 1829 /* Disable interrupts. */ 1830 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1831 1832 for (;;) { 1833 /* Reading clears interrupt. */ 1834 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1835 if ((isr & sc->sc_imr) == 0) 1836 break; 1837 1838 #if NRND > 0 1839 if (RND_ENABLED(&sc->rnd_source)) 1840 rnd_add_uint32(&sc->rnd_source, isr); 1841 #endif 1842 1843 handled = 1; 1844 1845 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1846 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1847 1848 /* Grab any new packets. */ 1849 (*sc->sc_rxintr)(sc); 1850 1851 if (isr & ISR_RXORN) { 1852 printf("%s: receive FIFO overrun\n", 1853 sc->sc_dev.dv_xname); 1854 1855 /* XXX adjust rx_drain_thresh? */ 1856 } 1857 1858 if (isr & ISR_RXIDLE) { 1859 printf("%s: receive ring overrun\n", 1860 sc->sc_dev.dv_xname); 1861 1862 /* Get the receive process going again. */ 1863 bus_space_write_4(sc->sc_st, sc->sc_sh, 1864 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1865 bus_space_write_4(sc->sc_st, sc->sc_sh, 1866 SIP_CR, CR_RXE); 1867 } 1868 } 1869 1870 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1871 #ifdef SIP_EVENT_COUNTERS 1872 if (isr & ISR_TXDESC) 1873 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1874 else if (isr & ISR_TXIDLE) 1875 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1876 #endif 1877 1878 /* Sweep up transmit descriptors. */ 1879 sipcom_txintr(sc); 1880 1881 if (isr & ISR_TXURN) { 1882 u_int32_t thresh; 1883 int txfifo_size = (sc->sc_gigabit) 1884 ? DP83820_SIP_TXFIFO_SIZE 1885 : OTHER_SIP_TXFIFO_SIZE; 1886 1887 printf("%s: transmit FIFO underrun", 1888 sc->sc_dev.dv_xname); 1889 thresh = sc->sc_tx_drain_thresh + 1; 1890 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1891 && (thresh * 32) <= (txfifo_size - 1892 (sc->sc_tx_fill_thresh * 32))) { 1893 printf("; increasing Tx drain " 1894 "threshold to %u bytes\n", 1895 thresh * 32); 1896 sc->sc_tx_drain_thresh = thresh; 1897 (void) sipcom_init(ifp); 1898 } else { 1899 (void) sipcom_init(ifp); 1900 printf("\n"); 1901 } 1902 } 1903 } 1904 1905 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1906 if (isr & ISR_PAUSE_ST) { 1907 sc->sc_paused = 1; 1908 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1909 ifp->if_flags |= IFF_OACTIVE; 1910 } 1911 if (isr & ISR_PAUSE_END) { 1912 sc->sc_paused = 0; 1913 ifp->if_flags &= ~IFF_OACTIVE; 1914 } 1915 } 1916 1917 if (isr & ISR_HIBERR) { 1918 int want_init = 0; 1919 1920 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1921 1922 #define PRINTERR(bit, str) \ 1923 do { \ 1924 if ((isr & (bit)) != 0) { \ 1925 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1926 printf("%s: %s\n", \ 1927 sc->sc_dev.dv_xname, str); \ 1928 want_init = 1; \ 1929 } \ 1930 } while (/*CONSTCOND*/0) 1931 1932 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1933 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1934 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1935 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1936 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1937 /* 1938 * Ignore: 1939 * Tx reset complete 1940 * Rx reset complete 1941 */ 1942 if (want_init) 1943 (void) sipcom_init(ifp); 1944 #undef PRINTERR 1945 } 1946 } 1947 1948 /* Re-enable interrupts. */ 1949 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1950 1951 /* Try to get more packets going. */ 1952 sipcom_start(ifp); 1953 1954 return (handled); 1955 } 1956 1957 /* 1958 * sip_txintr: 1959 * 1960 * Helper; handle transmit interrupts. 1961 */ 1962 static void 1963 sipcom_txintr(struct sip_softc *sc) 1964 { 1965 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1966 struct sip_txsoft *txs; 1967 u_int32_t cmdsts; 1968 1969 if (sc->sc_paused == 0) 1970 ifp->if_flags &= ~IFF_OACTIVE; 1971 1972 /* 1973 * Go through our Tx list and free mbufs for those 1974 * frames which have been transmitted. 1975 */ 1976 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1977 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1978 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1979 1980 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1981 if (cmdsts & CMDSTS_OWN) 1982 break; 1983 1984 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1985 1986 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1987 1988 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1989 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1990 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1991 m_freem(txs->txs_mbuf); 1992 txs->txs_mbuf = NULL; 1993 1994 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1995 1996 /* 1997 * Check for errors and collisions. 1998 */ 1999 if (cmdsts & 2000 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2001 ifp->if_oerrors++; 2002 if (cmdsts & CMDSTS_Tx_EC) 2003 ifp->if_collisions += 16; 2004 if (ifp->if_flags & IFF_DEBUG) { 2005 if (cmdsts & CMDSTS_Tx_ED) 2006 printf("%s: excessive deferral\n", 2007 sc->sc_dev.dv_xname); 2008 if (cmdsts & CMDSTS_Tx_EC) 2009 printf("%s: excessive collisions\n", 2010 sc->sc_dev.dv_xname); 2011 } 2012 } else { 2013 /* Packet was transmitted successfully. */ 2014 ifp->if_opackets++; 2015 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2016 } 2017 } 2018 2019 /* 2020 * If there are no more pending transmissions, cancel the watchdog 2021 * timer. 2022 */ 2023 if (txs == NULL) { 2024 ifp->if_timer = 0; 2025 sc->sc_txwin = 0; 2026 } 2027 } 2028 2029 /* 2030 * gsip_rxintr: 2031 * 2032 * Helper; handle receive interrupts on gigabit parts. 2033 */ 2034 static void 2035 gsip_rxintr(struct sip_softc *sc) 2036 { 2037 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2038 struct sip_rxsoft *rxs; 2039 struct mbuf *m; 2040 u_int32_t cmdsts, extsts; 2041 int i, len; 2042 2043 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2044 rxs = &sc->sc_rxsoft[i]; 2045 2046 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2047 2048 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2049 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2050 len = CMDSTS_SIZE(sc, cmdsts); 2051 2052 /* 2053 * NOTE: OWN is set if owned by _consumer_. We're the 2054 * consumer of the receive ring, so if the bit is clear, 2055 * we have processed all of the packets. 2056 */ 2057 if ((cmdsts & CMDSTS_OWN) == 0) { 2058 /* 2059 * We have processed all of the receive buffers. 2060 */ 2061 break; 2062 } 2063 2064 if (__predict_false(sc->sc_rxdiscard)) { 2065 sip_init_rxdesc(sc, i); 2066 if ((cmdsts & CMDSTS_MORE) == 0) { 2067 /* Reset our state. */ 2068 sc->sc_rxdiscard = 0; 2069 } 2070 continue; 2071 } 2072 2073 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2074 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2075 2076 m = rxs->rxs_mbuf; 2077 2078 /* 2079 * Add a new receive buffer to the ring. 2080 */ 2081 if (sipcom_add_rxbuf(sc, i) != 0) { 2082 /* 2083 * Failed, throw away what we've done so 2084 * far, and discard the rest of the packet. 2085 */ 2086 ifp->if_ierrors++; 2087 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2088 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2089 sip_init_rxdesc(sc, i); 2090 if (cmdsts & CMDSTS_MORE) 2091 sc->sc_rxdiscard = 1; 2092 if (sc->sc_rxhead != NULL) 2093 m_freem(sc->sc_rxhead); 2094 sip_rxchain_reset(sc); 2095 continue; 2096 } 2097 2098 sip_rxchain_link(sc, m); 2099 2100 m->m_len = len; 2101 2102 /* 2103 * If this is not the end of the packet, keep 2104 * looking. 2105 */ 2106 if (cmdsts & CMDSTS_MORE) { 2107 sc->sc_rxlen += len; 2108 continue; 2109 } 2110 2111 /* 2112 * Okay, we have the entire packet now. The chip includes 2113 * the FCS, so we need to trim it. 2114 */ 2115 m->m_len -= ETHER_CRC_LEN; 2116 2117 *sc->sc_rxtailp = NULL; 2118 len = m->m_len + sc->sc_rxlen; 2119 m = sc->sc_rxhead; 2120 2121 sip_rxchain_reset(sc); 2122 2123 /* 2124 * If an error occurred, update stats and drop the packet. 2125 */ 2126 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2127 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2128 ifp->if_ierrors++; 2129 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2130 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2131 /* Receive overrun handled elsewhere. */ 2132 printf("%s: receive descriptor error\n", 2133 sc->sc_dev.dv_xname); 2134 } 2135 #define PRINTERR(bit, str) \ 2136 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2137 (cmdsts & (bit)) != 0) \ 2138 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2139 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2140 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2141 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2142 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2143 #undef PRINTERR 2144 m_freem(m); 2145 continue; 2146 } 2147 2148 /* 2149 * If the packet is small enough to fit in a 2150 * single header mbuf, allocate one and copy 2151 * the data into it. This greatly reduces 2152 * memory consumption when we receive lots 2153 * of small packets. 2154 */ 2155 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2156 struct mbuf *nm; 2157 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2158 if (nm == NULL) { 2159 ifp->if_ierrors++; 2160 m_freem(m); 2161 continue; 2162 } 2163 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2164 nm->m_data += 2; 2165 nm->m_pkthdr.len = nm->m_len = len; 2166 m_copydata(m, 0, len, mtod(nm, void *)); 2167 m_freem(m); 2168 m = nm; 2169 } 2170 #ifndef __NO_STRICT_ALIGNMENT 2171 else { 2172 /* 2173 * The DP83820's receive buffers must be 4-byte 2174 * aligned. But this means that the data after 2175 * the Ethernet header is misaligned. To compensate, 2176 * we have artificially shortened the buffer size 2177 * in the descriptor, and we do an overlapping copy 2178 * of the data two bytes further in (in the first 2179 * buffer of the chain only). 2180 */ 2181 memmove(mtod(m, char *) + 2, mtod(m, void *), 2182 m->m_len); 2183 m->m_data += 2; 2184 } 2185 #endif /* ! __NO_STRICT_ALIGNMENT */ 2186 2187 /* 2188 * If VLANs are enabled, VLAN packets have been unwrapped 2189 * for us. Associate the tag with the packet. 2190 */ 2191 2192 /* 2193 * Again, byte swapping is tricky. Hardware provided 2194 * the tag in the network byte order, but extsts was 2195 * passed through le32toh() in the meantime. On a 2196 * big-endian machine, we need to swap it again. On a 2197 * little-endian machine, we need to convert from the 2198 * network to host byte order. This means that we must 2199 * swap it in any case, so unconditional swap instead 2200 * of htons() is used. 2201 */ 2202 if ((extsts & EXTSTS_VPKT) != 0) { 2203 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2204 continue); 2205 } 2206 2207 /* 2208 * Set the incoming checksum information for the 2209 * packet. 2210 */ 2211 if ((extsts & EXTSTS_IPPKT) != 0) { 2212 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2213 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2214 if (extsts & EXTSTS_Rx_IPERR) 2215 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2216 if (extsts & EXTSTS_TCPPKT) { 2217 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2218 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2219 if (extsts & EXTSTS_Rx_TCPERR) 2220 m->m_pkthdr.csum_flags |= 2221 M_CSUM_TCP_UDP_BAD; 2222 } else if (extsts & EXTSTS_UDPPKT) { 2223 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2224 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2225 if (extsts & EXTSTS_Rx_UDPERR) 2226 m->m_pkthdr.csum_flags |= 2227 M_CSUM_TCP_UDP_BAD; 2228 } 2229 } 2230 2231 ifp->if_ipackets++; 2232 m->m_pkthdr.rcvif = ifp; 2233 m->m_pkthdr.len = len; 2234 2235 #if NBPFILTER > 0 2236 /* 2237 * Pass this up to any BPF listeners, but only 2238 * pass if up the stack if it's for us. 2239 */ 2240 if (ifp->if_bpf) 2241 bpf_mtap(ifp->if_bpf, m); 2242 #endif /* NBPFILTER > 0 */ 2243 2244 /* Pass it on. */ 2245 (*ifp->if_input)(ifp, m); 2246 } 2247 2248 /* Update the receive pointer. */ 2249 sc->sc_rxptr = i; 2250 } 2251 2252 /* 2253 * sip_rxintr: 2254 * 2255 * Helper; handle receive interrupts on 10/100 parts. 2256 */ 2257 static void 2258 sip_rxintr(struct sip_softc *sc) 2259 { 2260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2261 struct sip_rxsoft *rxs; 2262 struct mbuf *m; 2263 u_int32_t cmdsts; 2264 int i, len; 2265 2266 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2267 rxs = &sc->sc_rxsoft[i]; 2268 2269 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2270 2271 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2272 2273 /* 2274 * NOTE: OWN is set if owned by _consumer_. We're the 2275 * consumer of the receive ring, so if the bit is clear, 2276 * we have processed all of the packets. 2277 */ 2278 if ((cmdsts & CMDSTS_OWN) == 0) { 2279 /* 2280 * We have processed all of the receive buffers. 2281 */ 2282 break; 2283 } 2284 2285 /* 2286 * If any collisions were seen on the wire, count one. 2287 */ 2288 if (cmdsts & CMDSTS_Rx_COL) 2289 ifp->if_collisions++; 2290 2291 /* 2292 * If an error occurred, update stats, clear the status 2293 * word, and leave the packet buffer in place. It will 2294 * simply be reused the next time the ring comes around. 2295 */ 2296 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2297 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2298 ifp->if_ierrors++; 2299 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2300 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2301 /* Receive overrun handled elsewhere. */ 2302 printf("%s: receive descriptor error\n", 2303 sc->sc_dev.dv_xname); 2304 } 2305 #define PRINTERR(bit, str) \ 2306 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2307 (cmdsts & (bit)) != 0) \ 2308 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2309 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2310 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2311 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2312 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2313 #undef PRINTERR 2314 sip_init_rxdesc(sc, i); 2315 continue; 2316 } 2317 2318 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2319 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2320 2321 /* 2322 * No errors; receive the packet. Note, the SiS 900 2323 * includes the CRC with every packet. 2324 */ 2325 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2326 2327 #ifdef __NO_STRICT_ALIGNMENT 2328 /* 2329 * If the packet is small enough to fit in a 2330 * single header mbuf, allocate one and copy 2331 * the data into it. This greatly reduces 2332 * memory consumption when we receive lots 2333 * of small packets. 2334 * 2335 * Otherwise, we add a new buffer to the receive 2336 * chain. If this fails, we drop the packet and 2337 * recycle the old buffer. 2338 */ 2339 if (sip_copy_small != 0 && len <= MHLEN) { 2340 MGETHDR(m, M_DONTWAIT, MT_DATA); 2341 if (m == NULL) 2342 goto dropit; 2343 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2344 memcpy(mtod(m, void *), 2345 mtod(rxs->rxs_mbuf, void *), len); 2346 sip_init_rxdesc(sc, i); 2347 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2348 rxs->rxs_dmamap->dm_mapsize, 2349 BUS_DMASYNC_PREREAD); 2350 } else { 2351 m = rxs->rxs_mbuf; 2352 if (sipcom_add_rxbuf(sc, i) != 0) { 2353 dropit: 2354 ifp->if_ierrors++; 2355 sip_init_rxdesc(sc, i); 2356 bus_dmamap_sync(sc->sc_dmat, 2357 rxs->rxs_dmamap, 0, 2358 rxs->rxs_dmamap->dm_mapsize, 2359 BUS_DMASYNC_PREREAD); 2360 continue; 2361 } 2362 } 2363 #else 2364 /* 2365 * The SiS 900's receive buffers must be 4-byte aligned. 2366 * But this means that the data after the Ethernet header 2367 * is misaligned. We must allocate a new buffer and 2368 * copy the data, shifted forward 2 bytes. 2369 */ 2370 MGETHDR(m, M_DONTWAIT, MT_DATA); 2371 if (m == NULL) { 2372 dropit: 2373 ifp->if_ierrors++; 2374 sip_init_rxdesc(sc, i); 2375 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2376 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2377 continue; 2378 } 2379 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2380 if (len > (MHLEN - 2)) { 2381 MCLGET(m, M_DONTWAIT); 2382 if ((m->m_flags & M_EXT) == 0) { 2383 m_freem(m); 2384 goto dropit; 2385 } 2386 } 2387 m->m_data += 2; 2388 2389 /* 2390 * Note that we use clusters for incoming frames, so the 2391 * buffer is virtually contiguous. 2392 */ 2393 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2394 2395 /* Allow the receive descriptor to continue using its mbuf. */ 2396 sip_init_rxdesc(sc, i); 2397 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2398 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2399 #endif /* __NO_STRICT_ALIGNMENT */ 2400 2401 ifp->if_ipackets++; 2402 m->m_pkthdr.rcvif = ifp; 2403 m->m_pkthdr.len = m->m_len = len; 2404 2405 #if NBPFILTER > 0 2406 /* 2407 * Pass this up to any BPF listeners, but only 2408 * pass if up the stack if it's for us. 2409 */ 2410 if (ifp->if_bpf) 2411 bpf_mtap(ifp->if_bpf, m); 2412 #endif /* NBPFILTER > 0 */ 2413 2414 /* Pass it on. */ 2415 (*ifp->if_input)(ifp, m); 2416 } 2417 2418 /* Update the receive pointer. */ 2419 sc->sc_rxptr = i; 2420 } 2421 2422 /* 2423 * sip_tick: 2424 * 2425 * One second timer, used to tick the MII. 2426 */ 2427 static void 2428 sipcom_tick(void *arg) 2429 { 2430 struct sip_softc *sc = arg; 2431 int s; 2432 2433 s = splnet(); 2434 #ifdef SIP_EVENT_COUNTERS 2435 if (sc->sc_gigabit) { 2436 /* Read PAUSE related counts from MIB registers. */ 2437 sc->sc_ev_rxpause.ev_count += 2438 bus_space_read_4(sc->sc_st, sc->sc_sh, 2439 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2440 sc->sc_ev_txpause.ev_count += 2441 bus_space_read_4(sc->sc_st, sc->sc_sh, 2442 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2443 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2444 } 2445 #endif /* SIP_EVENT_COUNTERS */ 2446 mii_tick(&sc->sc_mii); 2447 splx(s); 2448 2449 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2450 } 2451 2452 /* 2453 * sip_reset: 2454 * 2455 * Perform a soft reset on the SiS 900. 2456 */ 2457 static bool 2458 sipcom_reset(struct sip_softc *sc) 2459 { 2460 bus_space_tag_t st = sc->sc_st; 2461 bus_space_handle_t sh = sc->sc_sh; 2462 int i; 2463 2464 bus_space_write_4(st, sh, SIP_IER, 0); 2465 bus_space_write_4(st, sh, SIP_IMR, 0); 2466 bus_space_write_4(st, sh, SIP_RFCR, 0); 2467 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2468 2469 for (i = 0; i < SIP_TIMEOUT; i++) { 2470 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2471 break; 2472 delay(2); 2473 } 2474 2475 if (i == SIP_TIMEOUT) { 2476 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2477 return false; 2478 } 2479 2480 delay(1000); 2481 2482 if (sc->sc_gigabit) { 2483 /* 2484 * Set the general purpose I/O bits. Do it here in case we 2485 * need to have GPIO set up to talk to the media interface. 2486 */ 2487 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2488 delay(1000); 2489 } 2490 return true; 2491 } 2492 2493 static void 2494 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2495 { 2496 u_int32_t reg; 2497 bus_space_tag_t st = sc->sc_st; 2498 bus_space_handle_t sh = sc->sc_sh; 2499 /* 2500 * Initialize the VLAN/IP receive control register. 2501 * We enable checksum computation on all incoming 2502 * packets, and do not reject packets w/ bad checksums. 2503 */ 2504 reg = 0; 2505 if (capenable & 2506 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2507 reg |= VRCR_IPEN; 2508 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2509 reg |= VRCR_VTDEN|VRCR_VTREN; 2510 bus_space_write_4(st, sh, SIP_VRCR, reg); 2511 2512 /* 2513 * Initialize the VLAN/IP transmit control register. 2514 * We enable outgoing checksum computation on a 2515 * per-packet basis. 2516 */ 2517 reg = 0; 2518 if (capenable & 2519 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2520 reg |= VTCR_PPCHK; 2521 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2522 reg |= VTCR_VPPTI; 2523 bus_space_write_4(st, sh, SIP_VTCR, reg); 2524 2525 /* 2526 * If we're using VLANs, initialize the VLAN data register. 2527 * To understand why we bswap the VLAN Ethertype, see section 2528 * 4.2.36 of the DP83820 manual. 2529 */ 2530 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2531 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2532 } 2533 2534 /* 2535 * sip_init: [ ifnet interface function ] 2536 * 2537 * Initialize the interface. Must be called at splnet(). 2538 */ 2539 static int 2540 sipcom_init(struct ifnet *ifp) 2541 { 2542 struct sip_softc *sc = ifp->if_softc; 2543 bus_space_tag_t st = sc->sc_st; 2544 bus_space_handle_t sh = sc->sc_sh; 2545 struct sip_txsoft *txs; 2546 struct sip_rxsoft *rxs; 2547 struct sip_desc *sipd; 2548 int i, error = 0; 2549 2550 if (!device_has_power(&sc->sc_dev)) 2551 return EBUSY; 2552 2553 /* 2554 * Cancel any pending I/O. 2555 */ 2556 sipcom_stop(ifp, 0); 2557 2558 /* 2559 * Reset the chip to a known state. 2560 */ 2561 if (!sipcom_reset(sc)) 2562 return EBUSY; 2563 2564 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2565 /* 2566 * DP83815 manual, page 78: 2567 * 4.4 Recommended Registers Configuration 2568 * For optimum performance of the DP83815, version noted 2569 * as DP83815CVNG (SRR = 203h), the listed register 2570 * modifications must be followed in sequence... 2571 * 2572 * It's not clear if this should be 302h or 203h because that 2573 * chip name is listed as SRR 302h in the description of the 2574 * SRR register. However, my revision 302h DP83815 on the 2575 * Netgear FA311 purchased in 02/2001 needs these settings 2576 * to avoid tons of errors in AcceptPerfectMatch (non- 2577 * IFF_PROMISC) mode. I do not know if other revisions need 2578 * this set or not. [briggs -- 09 March 2001] 2579 * 2580 * Note that only the low-order 12 bits of 0xe4 are documented 2581 * and that this sets reserved bits in that register. 2582 */ 2583 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2584 2585 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2586 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2587 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2588 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2589 2590 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2591 } 2592 2593 /* 2594 * Initialize the transmit descriptor ring. 2595 */ 2596 for (i = 0; i < sc->sc_ntxdesc; i++) { 2597 sipd = &sc->sc_txdescs[i]; 2598 memset(sipd, 0, sizeof(struct sip_desc)); 2599 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2600 } 2601 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2602 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2603 sc->sc_txfree = sc->sc_ntxdesc; 2604 sc->sc_txnext = 0; 2605 sc->sc_txwin = 0; 2606 2607 /* 2608 * Initialize the transmit job descriptors. 2609 */ 2610 SIMPLEQ_INIT(&sc->sc_txfreeq); 2611 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2612 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2613 txs = &sc->sc_txsoft[i]; 2614 txs->txs_mbuf = NULL; 2615 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2616 } 2617 2618 /* 2619 * Initialize the receive descriptor and receive job 2620 * descriptor rings. 2621 */ 2622 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2623 rxs = &sc->sc_rxsoft[i]; 2624 if (rxs->rxs_mbuf == NULL) { 2625 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2626 printf("%s: unable to allocate or map rx " 2627 "buffer %d, error = %d\n", 2628 sc->sc_dev.dv_xname, i, error); 2629 /* 2630 * XXX Should attempt to run with fewer receive 2631 * XXX buffers instead of just failing. 2632 */ 2633 sipcom_rxdrain(sc); 2634 goto out; 2635 } 2636 } else 2637 sip_init_rxdesc(sc, i); 2638 } 2639 sc->sc_rxptr = 0; 2640 sc->sc_rxdiscard = 0; 2641 sip_rxchain_reset(sc); 2642 2643 /* 2644 * Set the configuration register; it's already initialized 2645 * in sip_attach(). 2646 */ 2647 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2648 2649 /* 2650 * Initialize the prototype TXCFG register. 2651 */ 2652 if (sc->sc_gigabit) { 2653 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2654 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2655 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2656 SIP_SIS900_REV(sc, SIS_REV_960) || 2657 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2658 (sc->sc_cfg & CFG_EDBMASTEN)) { 2659 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2660 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2661 } else { 2662 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2663 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2664 } 2665 2666 sc->sc_txcfg |= TXCFG_ATP | 2667 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2668 sc->sc_tx_drain_thresh; 2669 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2670 2671 /* 2672 * Initialize the receive drain threshold if we have never 2673 * done so. 2674 */ 2675 if (sc->sc_rx_drain_thresh == 0) { 2676 /* 2677 * XXX This value should be tuned. This is set to the 2678 * maximum of 248 bytes, and we may be able to improve 2679 * performance by decreasing it (although we should never 2680 * set this value lower than 2; 14 bytes are required to 2681 * filter the packet). 2682 */ 2683 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2684 } 2685 2686 /* 2687 * Initialize the prototype RXCFG register. 2688 */ 2689 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2690 /* 2691 * Accept long packets (including FCS) so we can handle 2692 * 802.1q-tagged frames and jumbo frames properly. 2693 */ 2694 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2695 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2696 sc->sc_rxcfg |= RXCFG_ALP; 2697 2698 /* 2699 * Checksum offloading is disabled if the user selects an MTU 2700 * larger than 8109. (FreeBSD says 8152, but there is emperical 2701 * evidence that >8109 does not work on some boards, such as the 2702 * Planex GN-1000TE). 2703 */ 2704 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2705 (ifp->if_capenable & 2706 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2707 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2708 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2709 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2710 "disabled.\n", sc->sc_dev.dv_xname); 2711 ifp->if_capenable &= 2712 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2713 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2714 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2715 ifp->if_csum_flags_tx = 0; 2716 ifp->if_csum_flags_rx = 0; 2717 } 2718 2719 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2720 2721 if (sc->sc_gigabit) 2722 sipcom_dp83820_init(sc, ifp->if_capenable); 2723 2724 /* 2725 * Give the transmit and receive rings to the chip. 2726 */ 2727 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2728 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2729 2730 /* 2731 * Initialize the interrupt mask. 2732 */ 2733 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2734 sc->sc_bits.b_isr_sserr | 2735 sc->sc_bits.b_isr_rmabt | 2736 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2737 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2738 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2739 2740 /* Set up the receive filter. */ 2741 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2742 2743 /* 2744 * Tune sc_rx_flow_thresh. 2745 * XXX "More than 8KB" is too short for jumbo frames. 2746 * XXX TODO: Threshold value should be user-settable. 2747 */ 2748 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2749 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2750 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2751 2752 /* 2753 * Set the current media. Do this after initializing the prototype 2754 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2755 * control. 2756 */ 2757 if ((error = ether_mediachange(ifp)) != 0) 2758 goto out; 2759 2760 /* 2761 * Set the interrupt hold-off timer to 100us. 2762 */ 2763 if (sc->sc_gigabit) 2764 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2765 2766 /* 2767 * Enable interrupts. 2768 */ 2769 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2770 2771 /* 2772 * Start the transmit and receive processes. 2773 */ 2774 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2775 2776 /* 2777 * Start the one second MII clock. 2778 */ 2779 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2780 2781 /* 2782 * ...all done! 2783 */ 2784 ifp->if_flags |= IFF_RUNNING; 2785 ifp->if_flags &= ~IFF_OACTIVE; 2786 sc->sc_if_flags = ifp->if_flags; 2787 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2788 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2789 sc->sc_prev.if_capenable = ifp->if_capenable; 2790 2791 out: 2792 if (error) 2793 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2794 return (error); 2795 } 2796 2797 /* 2798 * sip_drain: 2799 * 2800 * Drain the receive queue. 2801 */ 2802 static void 2803 sipcom_rxdrain(struct sip_softc *sc) 2804 { 2805 struct sip_rxsoft *rxs; 2806 int i; 2807 2808 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2809 rxs = &sc->sc_rxsoft[i]; 2810 if (rxs->rxs_mbuf != NULL) { 2811 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2812 m_freem(rxs->rxs_mbuf); 2813 rxs->rxs_mbuf = NULL; 2814 } 2815 } 2816 } 2817 2818 /* 2819 * sip_stop: [ ifnet interface function ] 2820 * 2821 * Stop transmission on the interface. 2822 */ 2823 static void 2824 sipcom_stop(struct ifnet *ifp, int disable) 2825 { 2826 struct sip_softc *sc = ifp->if_softc; 2827 bus_space_tag_t st = sc->sc_st; 2828 bus_space_handle_t sh = sc->sc_sh; 2829 struct sip_txsoft *txs; 2830 u_int32_t cmdsts = 0; /* DEBUG */ 2831 2832 /* 2833 * Stop the one second clock. 2834 */ 2835 callout_stop(&sc->sc_tick_ch); 2836 2837 /* Down the MII. */ 2838 mii_down(&sc->sc_mii); 2839 2840 /* 2841 * Disable interrupts. 2842 */ 2843 bus_space_write_4(st, sh, SIP_IER, 0); 2844 2845 /* 2846 * Stop receiver and transmitter. 2847 */ 2848 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2849 2850 /* 2851 * Release any queued transmit buffers. 2852 */ 2853 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2854 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2855 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2856 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2857 CMDSTS_INTR) == 0) 2858 printf("%s: sip_stop: last descriptor does not " 2859 "have INTR bit set\n", sc->sc_dev.dv_xname); 2860 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2861 #ifdef DIAGNOSTIC 2862 if (txs->txs_mbuf == NULL) { 2863 printf("%s: dirty txsoft with no mbuf chain\n", 2864 sc->sc_dev.dv_xname); 2865 panic("sip_stop"); 2866 } 2867 #endif 2868 cmdsts |= /* DEBUG */ 2869 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2870 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2871 m_freem(txs->txs_mbuf); 2872 txs->txs_mbuf = NULL; 2873 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2874 } 2875 2876 if (disable) 2877 sipcom_rxdrain(sc); 2878 2879 /* 2880 * Mark the interface down and cancel the watchdog timer. 2881 */ 2882 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2883 ifp->if_timer = 0; 2884 2885 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2886 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2887 printf("%s: sip_stop: no INTR bits set in dirty tx " 2888 "descriptors\n", sc->sc_dev.dv_xname); 2889 } 2890 2891 /* 2892 * sip_read_eeprom: 2893 * 2894 * Read data from the serial EEPROM. 2895 */ 2896 static void 2897 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2898 u_int16_t *data) 2899 { 2900 bus_space_tag_t st = sc->sc_st; 2901 bus_space_handle_t sh = sc->sc_sh; 2902 u_int16_t reg; 2903 int i, x; 2904 2905 for (i = 0; i < wordcnt; i++) { 2906 /* Send CHIP SELECT. */ 2907 reg = EROMAR_EECS; 2908 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2909 2910 /* Shift in the READ opcode. */ 2911 for (x = 3; x > 0; x--) { 2912 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2913 reg |= EROMAR_EEDI; 2914 else 2915 reg &= ~EROMAR_EEDI; 2916 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2917 bus_space_write_4(st, sh, SIP_EROMAR, 2918 reg | EROMAR_EESK); 2919 delay(4); 2920 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2921 delay(4); 2922 } 2923 2924 /* Shift in address. */ 2925 for (x = 6; x > 0; x--) { 2926 if ((word + i) & (1 << (x - 1))) 2927 reg |= EROMAR_EEDI; 2928 else 2929 reg &= ~EROMAR_EEDI; 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 bus_space_write_4(st, sh, SIP_EROMAR, 2932 reg | EROMAR_EESK); 2933 delay(4); 2934 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2935 delay(4); 2936 } 2937 2938 /* Shift out data. */ 2939 reg = EROMAR_EECS; 2940 data[i] = 0; 2941 for (x = 16; x > 0; x--) { 2942 bus_space_write_4(st, sh, SIP_EROMAR, 2943 reg | EROMAR_EESK); 2944 delay(4); 2945 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2946 data[i] |= (1 << (x - 1)); 2947 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2948 delay(4); 2949 } 2950 2951 /* Clear CHIP SELECT. */ 2952 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2953 delay(4); 2954 } 2955 } 2956 2957 /* 2958 * sipcom_add_rxbuf: 2959 * 2960 * Add a receive buffer to the indicated descriptor. 2961 */ 2962 static int 2963 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2964 { 2965 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2966 struct mbuf *m; 2967 int error; 2968 2969 MGETHDR(m, M_DONTWAIT, MT_DATA); 2970 if (m == NULL) 2971 return (ENOBUFS); 2972 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2973 2974 MCLGET(m, M_DONTWAIT); 2975 if ((m->m_flags & M_EXT) == 0) { 2976 m_freem(m); 2977 return (ENOBUFS); 2978 } 2979 2980 /* XXX I don't believe this is necessary. --dyoung */ 2981 if (sc->sc_gigabit) 2982 m->m_len = sc->sc_parm->p_rxbuf_len; 2983 2984 if (rxs->rxs_mbuf != NULL) 2985 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2986 2987 rxs->rxs_mbuf = m; 2988 2989 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2990 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2991 BUS_DMA_READ|BUS_DMA_NOWAIT); 2992 if (error) { 2993 printf("%s: can't load rx DMA map %d, error = %d\n", 2994 sc->sc_dev.dv_xname, idx, error); 2995 panic("%s", __func__); /* XXX */ 2996 } 2997 2998 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2999 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3000 3001 sip_init_rxdesc(sc, idx); 3002 3003 return (0); 3004 } 3005 3006 /* 3007 * sip_sis900_set_filter: 3008 * 3009 * Set up the receive filter. 3010 */ 3011 static void 3012 sipcom_sis900_set_filter(struct sip_softc *sc) 3013 { 3014 bus_space_tag_t st = sc->sc_st; 3015 bus_space_handle_t sh = sc->sc_sh; 3016 struct ethercom *ec = &sc->sc_ethercom; 3017 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3018 struct ether_multi *enm; 3019 const u_int8_t *cp; 3020 struct ether_multistep step; 3021 u_int32_t crc, mchash[16]; 3022 3023 /* 3024 * Initialize the prototype RFCR. 3025 */ 3026 sc->sc_rfcr = RFCR_RFEN; 3027 if (ifp->if_flags & IFF_BROADCAST) 3028 sc->sc_rfcr |= RFCR_AAB; 3029 if (ifp->if_flags & IFF_PROMISC) { 3030 sc->sc_rfcr |= RFCR_AAP; 3031 goto allmulti; 3032 } 3033 3034 /* 3035 * Set up the multicast address filter by passing all multicast 3036 * addresses through a CRC generator, and then using the high-order 3037 * 6 bits as an index into the 128 bit multicast hash table (only 3038 * the lower 16 bits of each 32 bit multicast hash register are 3039 * valid). The high order bits select the register, while the 3040 * rest of the bits select the bit within the register. 3041 */ 3042 3043 memset(mchash, 0, sizeof(mchash)); 3044 3045 /* 3046 * SiS900 (at least SiS963) requires us to register the address of 3047 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3048 */ 3049 crc = 0x0ed423f9; 3050 3051 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3052 SIP_SIS900_REV(sc, SIS_REV_960) || 3053 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3054 /* Just want the 8 most significant bits. */ 3055 crc >>= 24; 3056 } else { 3057 /* Just want the 7 most significant bits. */ 3058 crc >>= 25; 3059 } 3060 3061 /* Set the corresponding bit in the hash table. */ 3062 mchash[crc >> 4] |= 1 << (crc & 0xf); 3063 3064 ETHER_FIRST_MULTI(step, ec, enm); 3065 while (enm != NULL) { 3066 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3067 /* 3068 * We must listen to a range of multicast addresses. 3069 * For now, just accept all multicasts, rather than 3070 * trying to set only those filter bits needed to match 3071 * the range. (At this time, the only use of address 3072 * ranges is for IP multicast routing, for which the 3073 * range is big enough to require all bits set.) 3074 */ 3075 goto allmulti; 3076 } 3077 3078 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3079 3080 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3081 SIP_SIS900_REV(sc, SIS_REV_960) || 3082 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3083 /* Just want the 8 most significant bits. */ 3084 crc >>= 24; 3085 } else { 3086 /* Just want the 7 most significant bits. */ 3087 crc >>= 25; 3088 } 3089 3090 /* Set the corresponding bit in the hash table. */ 3091 mchash[crc >> 4] |= 1 << (crc & 0xf); 3092 3093 ETHER_NEXT_MULTI(step, enm); 3094 } 3095 3096 ifp->if_flags &= ~IFF_ALLMULTI; 3097 goto setit; 3098 3099 allmulti: 3100 ifp->if_flags |= IFF_ALLMULTI; 3101 sc->sc_rfcr |= RFCR_AAM; 3102 3103 setit: 3104 #define FILTER_EMIT(addr, data) \ 3105 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3106 delay(1); \ 3107 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3108 delay(1) 3109 3110 /* 3111 * Disable receive filter, and program the node address. 3112 */ 3113 cp = CLLADDR(ifp->if_sadl); 3114 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3115 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3116 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3117 3118 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3119 /* 3120 * Program the multicast hash table. 3121 */ 3122 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3123 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3124 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3125 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3126 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3127 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3128 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3129 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3130 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3131 SIP_SIS900_REV(sc, SIS_REV_960) || 3132 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3133 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3134 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3135 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3136 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3137 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3138 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3139 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3140 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3141 } 3142 } 3143 #undef FILTER_EMIT 3144 3145 /* 3146 * Re-enable the receiver filter. 3147 */ 3148 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3149 } 3150 3151 /* 3152 * sip_dp83815_set_filter: 3153 * 3154 * Set up the receive filter. 3155 */ 3156 static void 3157 sipcom_dp83815_set_filter(struct sip_softc *sc) 3158 { 3159 bus_space_tag_t st = sc->sc_st; 3160 bus_space_handle_t sh = sc->sc_sh; 3161 struct ethercom *ec = &sc->sc_ethercom; 3162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3163 struct ether_multi *enm; 3164 const u_int8_t *cp; 3165 struct ether_multistep step; 3166 u_int32_t crc, hash, slot, bit; 3167 #define MCHASH_NWORDS_83820 128 3168 #define MCHASH_NWORDS_83815 32 3169 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3170 u_int16_t mchash[MCHASH_NWORDS]; 3171 int i; 3172 3173 /* 3174 * Initialize the prototype RFCR. 3175 * Enable the receive filter, and accept on 3176 * Perfect (destination address) Match 3177 * If IFF_BROADCAST, also accept all broadcast packets. 3178 * If IFF_PROMISC, accept all unicast packets (and later, set 3179 * IFF_ALLMULTI and accept all multicast, too). 3180 */ 3181 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3182 if (ifp->if_flags & IFF_BROADCAST) 3183 sc->sc_rfcr |= RFCR_AAB; 3184 if (ifp->if_flags & IFF_PROMISC) { 3185 sc->sc_rfcr |= RFCR_AAP; 3186 goto allmulti; 3187 } 3188 3189 /* 3190 * Set up the DP83820/DP83815 multicast address filter by 3191 * passing all multicast addresses through a CRC generator, 3192 * and then using the high-order 11/9 bits as an index into 3193 * the 2048/512 bit multicast hash table. The high-order 3194 * 7/5 bits select the slot, while the low-order 4 bits 3195 * select the bit within the slot. Note that only the low 3196 * 16-bits of each filter word are used, and there are 3197 * 128/32 filter words. 3198 */ 3199 3200 memset(mchash, 0, sizeof(mchash)); 3201 3202 ifp->if_flags &= ~IFF_ALLMULTI; 3203 ETHER_FIRST_MULTI(step, ec, enm); 3204 if (enm == NULL) 3205 goto setit; 3206 while (enm != NULL) { 3207 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3208 /* 3209 * We must listen to a range of multicast addresses. 3210 * For now, just accept all multicasts, rather than 3211 * trying to set only those filter bits needed to match 3212 * the range. (At this time, the only use of address 3213 * ranges is for IP multicast routing, for which the 3214 * range is big enough to require all bits set.) 3215 */ 3216 goto allmulti; 3217 } 3218 3219 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3220 3221 if (sc->sc_gigabit) { 3222 /* Just want the 11 most significant bits. */ 3223 hash = crc >> 21; 3224 } else { 3225 /* Just want the 9 most significant bits. */ 3226 hash = crc >> 23; 3227 } 3228 3229 slot = hash >> 4; 3230 bit = hash & 0xf; 3231 3232 /* Set the corresponding bit in the hash table. */ 3233 mchash[slot] |= 1 << bit; 3234 3235 ETHER_NEXT_MULTI(step, enm); 3236 } 3237 sc->sc_rfcr |= RFCR_MHEN; 3238 goto setit; 3239 3240 allmulti: 3241 ifp->if_flags |= IFF_ALLMULTI; 3242 sc->sc_rfcr |= RFCR_AAM; 3243 3244 setit: 3245 #define FILTER_EMIT(addr, data) \ 3246 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3247 delay(1); \ 3248 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3249 delay(1) 3250 3251 /* 3252 * Disable receive filter, and program the node address. 3253 */ 3254 cp = CLLADDR(ifp->if_sadl); 3255 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3256 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3257 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3258 3259 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3260 int nwords = 3261 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3262 /* 3263 * Program the multicast hash table. 3264 */ 3265 for (i = 0; i < nwords; i++) { 3266 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3267 } 3268 } 3269 #undef FILTER_EMIT 3270 #undef MCHASH_NWORDS 3271 #undef MCHASH_NWORDS_83815 3272 #undef MCHASH_NWORDS_83820 3273 3274 /* 3275 * Re-enable the receiver filter. 3276 */ 3277 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3278 } 3279 3280 /* 3281 * sip_dp83820_mii_readreg: [mii interface function] 3282 * 3283 * Read a PHY register on the MII of the DP83820. 3284 */ 3285 static int 3286 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3287 { 3288 struct sip_softc *sc = (void *) self; 3289 3290 if (sc->sc_cfg & CFG_TBI_EN) { 3291 bus_addr_t tbireg; 3292 int rv; 3293 3294 if (phy != 0) 3295 return (0); 3296 3297 switch (reg) { 3298 case MII_BMCR: tbireg = SIP_TBICR; break; 3299 case MII_BMSR: tbireg = SIP_TBISR; break; 3300 case MII_ANAR: tbireg = SIP_TANAR; break; 3301 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3302 case MII_ANER: tbireg = SIP_TANER; break; 3303 case MII_EXTSR: 3304 /* 3305 * Don't even bother reading the TESR register. 3306 * The manual documents that the device has 3307 * 1000baseX full/half capability, but the 3308 * register itself seems read back 0 on some 3309 * boards. Just hard-code the result. 3310 */ 3311 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3312 3313 default: 3314 return (0); 3315 } 3316 3317 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3318 if (tbireg == SIP_TBISR) { 3319 /* LINK and ACOMP are switched! */ 3320 int val = rv; 3321 3322 rv = 0; 3323 if (val & TBISR_MR_LINK_STATUS) 3324 rv |= BMSR_LINK; 3325 if (val & TBISR_MR_AN_COMPLETE) 3326 rv |= BMSR_ACOMP; 3327 3328 /* 3329 * The manual claims this register reads back 0 3330 * on hard and soft reset. But we want to let 3331 * the gentbi driver know that we support auto- 3332 * negotiation, so hard-code this bit in the 3333 * result. 3334 */ 3335 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3336 } 3337 3338 return (rv); 3339 } 3340 3341 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3342 } 3343 3344 /* 3345 * sip_dp83820_mii_writereg: [mii interface function] 3346 * 3347 * Write a PHY register on the MII of the DP83820. 3348 */ 3349 static void 3350 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3351 { 3352 struct sip_softc *sc = (void *) self; 3353 3354 if (sc->sc_cfg & CFG_TBI_EN) { 3355 bus_addr_t tbireg; 3356 3357 if (phy != 0) 3358 return; 3359 3360 switch (reg) { 3361 case MII_BMCR: tbireg = SIP_TBICR; break; 3362 case MII_ANAR: tbireg = SIP_TANAR; break; 3363 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3364 default: 3365 return; 3366 } 3367 3368 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3369 return; 3370 } 3371 3372 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3373 } 3374 3375 /* 3376 * sip_dp83820_mii_statchg: [mii interface function] 3377 * 3378 * Callback from MII layer when media changes. 3379 */ 3380 static void 3381 sipcom_dp83820_mii_statchg(struct device *self) 3382 { 3383 struct sip_softc *sc = (struct sip_softc *) self; 3384 struct mii_data *mii = &sc->sc_mii; 3385 u_int32_t cfg, pcr; 3386 3387 /* 3388 * Get flow control negotiation result. 3389 */ 3390 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3391 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3392 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3393 mii->mii_media_active &= ~IFM_ETH_FMASK; 3394 } 3395 3396 /* 3397 * Update TXCFG for full-duplex operation. 3398 */ 3399 if ((mii->mii_media_active & IFM_FDX) != 0) 3400 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3401 else 3402 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3403 3404 /* 3405 * Update RXCFG for full-duplex or loopback. 3406 */ 3407 if ((mii->mii_media_active & IFM_FDX) != 0 || 3408 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3409 sc->sc_rxcfg |= RXCFG_ATX; 3410 else 3411 sc->sc_rxcfg &= ~RXCFG_ATX; 3412 3413 /* 3414 * Update CFG for MII/GMII. 3415 */ 3416 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3417 cfg = sc->sc_cfg | CFG_MODE_1000; 3418 else 3419 cfg = sc->sc_cfg; 3420 3421 /* 3422 * 802.3x flow control. 3423 */ 3424 pcr = 0; 3425 if (sc->sc_flowflags & IFM_FLOW) { 3426 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3427 pcr |= sc->sc_rx_flow_thresh; 3428 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3429 pcr |= PCR_PSEN | PCR_PS_MCAST; 3430 } 3431 3432 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3433 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3434 sc->sc_txcfg); 3435 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3436 sc->sc_rxcfg); 3437 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3438 } 3439 3440 /* 3441 * sip_mii_bitbang_read: [mii bit-bang interface function] 3442 * 3443 * Read the MII serial port for the MII bit-bang module. 3444 */ 3445 static u_int32_t 3446 sipcom_mii_bitbang_read(struct device *self) 3447 { 3448 struct sip_softc *sc = (void *) self; 3449 3450 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3451 } 3452 3453 /* 3454 * sip_mii_bitbang_write: [mii big-bang interface function] 3455 * 3456 * Write the MII serial port for the MII bit-bang module. 3457 */ 3458 static void 3459 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3460 { 3461 struct sip_softc *sc = (void *) self; 3462 3463 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3464 } 3465 3466 /* 3467 * sip_sis900_mii_readreg: [mii interface function] 3468 * 3469 * Read a PHY register on the MII. 3470 */ 3471 static int 3472 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3473 { 3474 struct sip_softc *sc = (struct sip_softc *) self; 3475 u_int32_t enphy; 3476 3477 /* 3478 * The PHY of recent SiS chipsets is accessed through bitbang 3479 * operations. 3480 */ 3481 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3482 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3483 phy, reg); 3484 3485 #ifndef SIS900_MII_RESTRICT 3486 /* 3487 * The SiS 900 has only an internal PHY on the MII. Only allow 3488 * MII address 0. 3489 */ 3490 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3491 return (0); 3492 #endif 3493 3494 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3495 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3496 ENPHY_RWCMD | ENPHY_ACCESS); 3497 do { 3498 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3499 } while (enphy & ENPHY_ACCESS); 3500 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3501 } 3502 3503 /* 3504 * sip_sis900_mii_writereg: [mii interface function] 3505 * 3506 * Write a PHY register on the MII. 3507 */ 3508 static void 3509 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3510 { 3511 struct sip_softc *sc = (struct sip_softc *) self; 3512 u_int32_t enphy; 3513 3514 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3515 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3516 phy, reg, val); 3517 return; 3518 } 3519 3520 #ifndef SIS900_MII_RESTRICT 3521 /* 3522 * The SiS 900 has only an internal PHY on the MII. Only allow 3523 * MII address 0. 3524 */ 3525 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3526 return; 3527 #endif 3528 3529 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3530 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3531 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3532 do { 3533 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3534 } while (enphy & ENPHY_ACCESS); 3535 } 3536 3537 /* 3538 * sip_sis900_mii_statchg: [mii interface function] 3539 * 3540 * Callback from MII layer when media changes. 3541 */ 3542 static void 3543 sipcom_sis900_mii_statchg(struct device *self) 3544 { 3545 struct sip_softc *sc = (struct sip_softc *) self; 3546 struct mii_data *mii = &sc->sc_mii; 3547 u_int32_t flowctl; 3548 3549 /* 3550 * Get flow control negotiation result. 3551 */ 3552 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3553 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3554 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3555 mii->mii_media_active &= ~IFM_ETH_FMASK; 3556 } 3557 3558 /* 3559 * Update TXCFG for full-duplex operation. 3560 */ 3561 if ((mii->mii_media_active & IFM_FDX) != 0) 3562 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3563 else 3564 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3565 3566 /* 3567 * Update RXCFG for full-duplex or loopback. 3568 */ 3569 if ((mii->mii_media_active & IFM_FDX) != 0 || 3570 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3571 sc->sc_rxcfg |= RXCFG_ATX; 3572 else 3573 sc->sc_rxcfg &= ~RXCFG_ATX; 3574 3575 /* 3576 * Update IMR for use of 802.3x flow control. 3577 */ 3578 if (sc->sc_flowflags & IFM_FLOW) { 3579 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3580 flowctl = FLOWCTL_FLOWEN; 3581 } else { 3582 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3583 flowctl = 0; 3584 } 3585 3586 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3587 sc->sc_txcfg); 3588 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3589 sc->sc_rxcfg); 3590 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3591 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3592 } 3593 3594 /* 3595 * sip_dp83815_mii_readreg: [mii interface function] 3596 * 3597 * Read a PHY register on the MII. 3598 */ 3599 static int 3600 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3601 { 3602 struct sip_softc *sc = (struct sip_softc *) self; 3603 u_int32_t val; 3604 3605 /* 3606 * The DP83815 only has an internal PHY. Only allow 3607 * MII address 0. 3608 */ 3609 if (phy != 0) 3610 return (0); 3611 3612 /* 3613 * Apparently, after a reset, the DP83815 can take a while 3614 * to respond. During this recovery period, the BMSR returns 3615 * a value of 0. Catch this -- it's not supposed to happen 3616 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3617 * PHY to come back to life. 3618 * 3619 * This works out because the BMSR is the first register 3620 * read during the PHY probe process. 3621 */ 3622 do { 3623 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3624 } while (reg == MII_BMSR && val == 0); 3625 3626 return (val & 0xffff); 3627 } 3628 3629 /* 3630 * sip_dp83815_mii_writereg: [mii interface function] 3631 * 3632 * Write a PHY register to the MII. 3633 */ 3634 static void 3635 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3636 { 3637 struct sip_softc *sc = (struct sip_softc *) self; 3638 3639 /* 3640 * The DP83815 only has an internal PHY. Only allow 3641 * MII address 0. 3642 */ 3643 if (phy != 0) 3644 return; 3645 3646 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3647 } 3648 3649 /* 3650 * sip_dp83815_mii_statchg: [mii interface function] 3651 * 3652 * Callback from MII layer when media changes. 3653 */ 3654 static void 3655 sipcom_dp83815_mii_statchg(struct device *self) 3656 { 3657 struct sip_softc *sc = (struct sip_softc *) self; 3658 3659 /* 3660 * Update TXCFG for full-duplex operation. 3661 */ 3662 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3663 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3664 else 3665 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3666 3667 /* 3668 * Update RXCFG for full-duplex or loopback. 3669 */ 3670 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3671 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3672 sc->sc_rxcfg |= RXCFG_ATX; 3673 else 3674 sc->sc_rxcfg &= ~RXCFG_ATX; 3675 3676 /* 3677 * XXX 802.3x flow control. 3678 */ 3679 3680 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3681 sc->sc_txcfg); 3682 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3683 sc->sc_rxcfg); 3684 3685 /* 3686 * Some DP83815s experience problems when used with short 3687 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3688 * sequence adjusts the DSP's signal attenuation to fix the 3689 * problem. 3690 */ 3691 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3692 uint32_t reg; 3693 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3695 3696 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3697 reg &= 0x0fff; 3698 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3699 delay(100); 3700 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3701 reg &= 0x00ff; 3702 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3703 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3704 0x00e8); 3705 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3706 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3707 reg | 0x20); 3708 } 3709 3710 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3711 } 3712 } 3713 3714 static void 3715 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3716 const struct pci_attach_args *pa, u_int8_t *enaddr) 3717 { 3718 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3719 u_int8_t cksum, *e, match; 3720 int i; 3721 3722 /* 3723 * EEPROM data format for the DP83820 can be found in 3724 * the DP83820 manual, section 4.2.4. 3725 */ 3726 3727 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3728 3729 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3730 match = ~(match - 1); 3731 3732 cksum = 0x55; 3733 e = (u_int8_t *) eeprom_data; 3734 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3735 cksum += *e++; 3736 3737 if (cksum != match) 3738 printf("%s: Checksum (%x) mismatch (%x)", 3739 sc->sc_dev.dv_xname, cksum, match); 3740 3741 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3742 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3743 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3744 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3745 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3746 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3747 } 3748 3749 static void 3750 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3751 { 3752 int i; 3753 3754 /* 3755 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3756 * a reason, but I don't know it. 3757 */ 3758 for (i = 0; i < 10; i++) 3759 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3760 } 3761 3762 static void 3763 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3764 const struct pci_attach_args *pa, u_int8_t *enaddr) 3765 { 3766 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3767 3768 switch (sc->sc_rev) { 3769 case SIS_REV_630S: 3770 case SIS_REV_630E: 3771 case SIS_REV_630EA1: 3772 case SIS_REV_630ET: 3773 case SIS_REV_635: 3774 /* 3775 * The MAC address for the on-board Ethernet of 3776 * the SiS 630 chipset is in the NVRAM. Kick 3777 * the chip into re-loading it from NVRAM, and 3778 * read the MAC address out of the filter registers. 3779 */ 3780 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3781 3782 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3783 RFCR_RFADDR_NODE0); 3784 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3785 0xffff; 3786 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3788 RFCR_RFADDR_NODE2); 3789 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3790 0xffff; 3791 3792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3793 RFCR_RFADDR_NODE4); 3794 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3795 0xffff; 3796 break; 3797 3798 case SIS_REV_960: 3799 { 3800 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3801 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3802 3803 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3804 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3805 3806 int waittime, i; 3807 3808 /* Allow to read EEPROM from LAN. It is shared 3809 * between a 1394 controller and the NIC and each 3810 * time we access it, we need to set SIS_EECMD_REQ. 3811 */ 3812 SIS_SET_EROMAR(sc, EROMAR_REQ); 3813 3814 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3815 /* Force EEPROM to idle state. */ 3816 3817 /* 3818 * XXX-cube This is ugly. I'll look for docs about it. 3819 */ 3820 SIS_SET_EROMAR(sc, EROMAR_EECS); 3821 sipcom_sis900_eeprom_delay(sc); 3822 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3823 SIS_SET_EROMAR(sc, EROMAR_EESK); 3824 sipcom_sis900_eeprom_delay(sc); 3825 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3826 sipcom_sis900_eeprom_delay(sc); 3827 } 3828 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3829 sipcom_sis900_eeprom_delay(sc); 3830 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3831 3832 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3833 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3834 sizeof(myea) / sizeof(myea[0]), myea); 3835 break; 3836 } 3837 DELAY(1); 3838 } 3839 3840 /* 3841 * Set SIS_EECTL_CLK to high, so a other master 3842 * can operate on the i2c bus. 3843 */ 3844 SIS_SET_EROMAR(sc, EROMAR_EESK); 3845 3846 /* Refuse EEPROM access by LAN */ 3847 SIS_SET_EROMAR(sc, EROMAR_DONE); 3848 } break; 3849 3850 default: 3851 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3852 sizeof(myea) / sizeof(myea[0]), myea); 3853 } 3854 3855 enaddr[0] = myea[0] & 0xff; 3856 enaddr[1] = myea[0] >> 8; 3857 enaddr[2] = myea[1] & 0xff; 3858 enaddr[3] = myea[1] >> 8; 3859 enaddr[4] = myea[2] & 0xff; 3860 enaddr[5] = myea[2] >> 8; 3861 } 3862 3863 /* Table and macro to bit-reverse an octet. */ 3864 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3865 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3866 3867 static void 3868 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3869 const struct pci_attach_args *pa, u_int8_t *enaddr) 3870 { 3871 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3872 u_int8_t cksum, *e, match; 3873 int i; 3874 3875 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3876 sizeof(eeprom_data[0]), eeprom_data); 3877 3878 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3879 match = ~(match - 1); 3880 3881 cksum = 0x55; 3882 e = (u_int8_t *) eeprom_data; 3883 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3884 cksum += *e++; 3885 } 3886 if (cksum != match) { 3887 printf("%s: Checksum (%x) mismatch (%x)", 3888 sc->sc_dev.dv_xname, cksum, match); 3889 } 3890 3891 /* 3892 * Unrolled because it makes slightly more sense this way. 3893 * The DP83815 stores the MAC address in bit 0 of word 6 3894 * through bit 15 of word 8. 3895 */ 3896 ea = &eeprom_data[6]; 3897 enaddr[0] = ((*ea & 0x1) << 7); 3898 ea++; 3899 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3900 enaddr[1] = ((*ea & 0x1FE) >> 1); 3901 enaddr[2] = ((*ea & 0x1) << 7); 3902 ea++; 3903 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3904 enaddr[3] = ((*ea & 0x1FE) >> 1); 3905 enaddr[4] = ((*ea & 0x1) << 7); 3906 ea++; 3907 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3908 enaddr[5] = ((*ea & 0x1FE) >> 1); 3909 3910 /* 3911 * In case that's not weird enough, we also need to reverse 3912 * the bits in each byte. This all actually makes more sense 3913 * if you think about the EEPROM storage as an array of bits 3914 * being shifted into bytes, but that's not how we're looking 3915 * at it here... 3916 */ 3917 for (i = 0; i < 6 ;i++) 3918 enaddr[i] = bbr(enaddr[i]); 3919 } 3920 3921 /* 3922 * sip_mediastatus: [ifmedia interface function] 3923 * 3924 * Get the current interface media status. 3925 */ 3926 static void 3927 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3928 { 3929 struct sip_softc *sc = ifp->if_softc; 3930 3931 ether_mediastatus(ifp, ifmr); 3932 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3933 sc->sc_flowflags; 3934 } 3935
Indexes created Tue Sep 30 11:09:46 GMT 2025