if_sip.c revision 1.116
1 /* $NetBSD: if_sip.c,v 1.116 2007/12/14 01:55:35 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.116 2007/12/14 01:55:35 dyoung Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 /* 136 * Transmit descriptor list size. This is arbitrary, but allocate 137 * enough descriptors for 128 pending transmissions, and 8 segments 138 * per packet (64 for DP83820 for jumbo frames). 139 * 140 * This MUST work out to a power of 2. 141 */ 142 #define GSIP_NTXSEGS_ALLOC 16 143 #define SIP_NTXSEGS_ALLOC 8 144 145 #define SIP_TXQUEUELEN 256 146 #define MAX_SIP_NTXDESC \ 147 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 148 149 /* 150 * Receive descriptor list size. We have one Rx buffer per incoming 151 * packet, so this logic is a little simpler. 152 * 153 * Actually, on the DP83820, we allow the packet to consume more than 154 * one buffer, in order to support jumbo Ethernet frames. In that 155 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 156 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 157 * so we'd better be quick about handling receive interrupts. 158 */ 159 #define GSIP_NRXDESC 256 160 #define SIP_NRXDESC 128 161 162 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 163 164 /* 165 * Control structures are DMA'd to the SiS900 chip. We allocate them in 166 * a single clump that maps to a single DMA segment to make several things 167 * easier. 168 */ 169 struct sip_control_data { 170 /* 171 * The transmit descriptors. 172 */ 173 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 174 175 /* 176 * The receive descriptors. 177 */ 178 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 179 }; 180 181 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 182 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 183 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 184 185 /* 186 * Software state for transmit jobs. 187 */ 188 struct sip_txsoft { 189 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t txs_dmamap; /* our DMA map */ 191 int txs_firstdesc; /* first descriptor in packet */ 192 int txs_lastdesc; /* last descriptor in packet */ 193 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 194 }; 195 196 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 197 198 /* 199 * Software state for receive jobs. 200 */ 201 struct sip_rxsoft { 202 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 203 bus_dmamap_t rxs_dmamap; /* our DMA map */ 204 }; 205 206 enum sip_attach_stage { 207 SIP_ATTACH_FIN = 0 208 , SIP_ATTACH_CREATE_RXMAP 209 , SIP_ATTACH_CREATE_TXMAP 210 , SIP_ATTACH_LOAD_MAP 211 , SIP_ATTACH_CREATE_MAP 212 , SIP_ATTACH_MAP_MEM 213 , SIP_ATTACH_ALLOC_MEM 214 , SIP_ATTACH_BEGIN 215 }; 216 217 /* 218 * Software state per device. 219 */ 220 struct sip_softc { 221 struct device sc_dev; /* generic device information */ 222 bus_space_tag_t sc_st; /* bus space tag */ 223 bus_space_handle_t sc_sh; /* bus space handle */ 224 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 225 pci_chipset_tag_t sc_pc; 226 bus_dma_segment_t sc_seg; 227 struct ethercom sc_ethercom; /* ethernet common data */ 228 void *sc_sdhook; /* shutdown hook */ 229 230 const struct sip_product *sc_model; /* which model are we? */ 231 int sc_gigabit; /* 1: 83820, 0: other */ 232 int sc_rev; /* chip revision */ 233 234 void *sc_ih; /* interrupt cookie */ 235 236 struct mii_data sc_mii; /* MII/media information */ 237 238 callout_t sc_tick_ch; /* tick callout */ 239 240 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 241 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 242 243 /* 244 * Software state for transmit and receive descriptors. 245 */ 246 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 247 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 248 249 /* 250 * Control data structures. 251 */ 252 struct sip_control_data *sc_control_data; 253 #define sc_txdescs sc_control_data->scd_txdescs 254 #define sc_rxdescs sc_control_data->scd_rxdescs 255 256 #ifdef SIP_EVENT_COUNTERS 257 /* 258 * Event counters. 259 */ 260 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 261 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 262 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 263 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 264 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 265 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 266 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 267 struct evcnt sc_ev_rxpause; /* PAUSE received */ 268 /* DP83820 only */ 269 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 270 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 271 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 272 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 273 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 274 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 275 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 276 #endif /* SIP_EVENT_COUNTERS */ 277 278 u_int32_t sc_txcfg; /* prototype TXCFG register */ 279 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 280 u_int32_t sc_imr; /* prototype IMR register */ 281 u_int32_t sc_rfcr; /* prototype RFCR register */ 282 283 u_int32_t sc_cfg; /* prototype CFG register */ 284 285 u_int32_t sc_gpior; /* prototype GPIOR register */ 286 287 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 288 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 289 290 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 291 292 int sc_flowflags; /* 802.3x flow control flags */ 293 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 294 int sc_paused; /* paused indication */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 int sc_txwin; /* Tx descriptors since last intr */ 299 300 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 301 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 302 303 /* values of interface state at last init */ 304 struct { 305 /* if_capenable */ 306 uint64_t if_capenable; 307 /* ec_capenable */ 308 int ec_capenable; 309 /* VLAN_ATTACHED */ 310 int is_vlan; 311 } sc_prev; 312 313 short sc_if_flags; 314 315 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 322 int sc_ntxdesc; 323 int sc_ntxdesc_mask; 324 int sc_ntxsegs; 325 326 int sc_nrxdesc; 327 int sc_nrxdesc_mask; 328 int sc_rxbuf_len; 329 330 int sc_suspended; 331 332 #if NRND > 0 333 rndsource_element_t rnd_source; /* random source */ 334 #endif 335 }; 336 337 static inline int 338 sip_nexttx(const struct sip_softc *sc, int x) 339 { 340 return (x + 1) & sc->sc_ntxdesc_mask; 341 } 342 343 static inline int 344 sip_nextrx(const struct sip_softc *sc, int x) 345 { 346 return (x + 1) & sc->sc_nrxdesc_mask; 347 } 348 349 /* 83820 only */ 350 #define SIP_RXCHAIN_RESET(sc) \ 351 do { \ 352 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 353 *(sc)->sc_rxtailp = NULL; \ 354 (sc)->sc_rxlen = 0; \ 355 } while (/*CONSTCOND*/0) 356 357 /* 83820 only */ 358 #define SIP_RXCHAIN_LINK(sc, m) \ 359 do { \ 360 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 361 (sc)->sc_rxtailp = &(m)->m_next; \ 362 } while (/*CONSTCOND*/0) 363 364 #ifdef SIP_EVENT_COUNTERS 365 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 366 #else 367 #define SIP_EVCNT_INCR(ev) /* nothing */ 368 #endif 369 370 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 371 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 372 373 #define SIP_CDTXSYNC(sc, x, n, ops) \ 374 do { \ 375 int __x, __n; \ 376 \ 377 __x = (x); \ 378 __n = (n); \ 379 \ 380 /* If it will wrap around, sync to the end of the ring. */ \ 381 if ((__x + __n) > sc->sc_ntxdesc) { \ 382 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 383 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 384 (sc->sc_ntxdesc - __x), (ops)); \ 385 __n -= (sc->sc_ntxdesc - __x); \ 386 __x = 0; \ 387 } \ 388 \ 389 /* Now sync whatever is left. */ \ 390 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 391 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 392 } while (0) 393 394 #define SIP_CDRXSYNC(sc, x, ops) \ 395 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 396 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 397 398 static inline void 399 SIP_INIT_RXDESC(struct sip_softc *sc, int x) 400 { 401 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 402 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 403 404 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 405 sipd->sipd_bufptr = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 406 sipd->sipd_cmdsts = htole32(CMDSTS_INTR | 407 (sc->sc_rxbuf_len & CMDSTS_SIZE_MASK)); 408 sipd->sipd_extsts = 0; 409 SIP_CDRXSYNC(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 410 } 411 412 #define SIP_CHIP_VERS(sc, v, p, r) \ 413 ((sc)->sc_model->sip_vendor == (v) && \ 414 (sc)->sc_model->sip_product == (p) && \ 415 (sc)->sc_rev == (r)) 416 417 #define SIP_CHIP_MODEL(sc, v, p) \ 418 ((sc)->sc_model->sip_vendor == (v) && \ 419 (sc)->sc_model->sip_product == (p)) 420 421 #define SIP_SIS900_REV(sc, rev) \ 422 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 423 424 #define SIP_TIMEOUT 1000 425 426 static void sipcom_start(struct ifnet *); 427 static void sipcom_watchdog(struct ifnet *); 428 static int sipcom_ioctl(struct ifnet *, u_long, void *); 429 static int sipcom_init(struct ifnet *); 430 static void sipcom_stop(struct ifnet *, int); 431 432 static void sipcom_shutdown(void *); 433 434 static bool sipcom_reset(struct sip_softc *); 435 static void sipcom_rxdrain(struct sip_softc *); 436 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 437 static void sipcom_read_eeprom(struct sip_softc *, int, int, 438 u_int16_t *); 439 static void sipcom_tick(void *); 440 441 static void sipcom_sis900_set_filter(struct sip_softc *); 442 static void sipcom_dp83815_set_filter(struct sip_softc *); 443 444 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 445 const struct pci_attach_args *, u_int8_t *); 446 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 447 static void sipcom_sis900_read_macaddr(struct sip_softc *, 448 const struct pci_attach_args *, u_int8_t *); 449 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 450 const struct pci_attach_args *, u_int8_t *); 451 452 static int sipcom_intr(void *); 453 static void sipcom_txintr(struct sip_softc *); 454 static void SIP_DECL(rxintr)(struct sip_softc *); 455 456 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 457 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 458 static void sipcom_dp83820_mii_statchg(struct device *); 459 460 static int sipcom_sis900_mii_readreg(struct device *, int, int); 461 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 462 static void sipcom_sis900_mii_statchg(struct device *); 463 464 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 465 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 466 static void sipcom_dp83815_mii_statchg(struct device *); 467 468 static int sipcom_mediachange(struct ifnet *); 469 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 470 471 static int sipcom_match(struct device *, struct cfdata *, void *); 472 static void sipcom_attach(struct device *, struct device *, void *); 473 static void sipcom_do_detach(device_t, enum sip_attach_stage); 474 static int sipcom_detach(device_t, int); 475 static bool sipcom_resume(device_t); 476 static bool sipcom_suspend(device_t); 477 478 int SIP_DECL(copy_small) = 0; 479 480 #ifdef DP83820 481 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 482 sipcom_match, sipcom_attach, sipcom_detach, NULL); 483 #else 484 CFATTACH_DECL(sip, sizeof(struct sip_softc), 485 sipcom_match, sipcom_attach, sipcom_detach, NULL); 486 #endif 487 488 /* 489 * Descriptions of the variants of the SiS900. 490 */ 491 struct sip_variant { 492 int (*sipv_mii_readreg)(struct device *, int, int); 493 void (*sipv_mii_writereg)(struct device *, int, int, int); 494 void (*sipv_mii_statchg)(struct device *); 495 void (*sipv_set_filter)(struct sip_softc *); 496 void (*sipv_read_macaddr)(struct sip_softc *, 497 const struct pci_attach_args *, u_int8_t *); 498 }; 499 500 static u_int32_t sipcom_mii_bitbang_read(struct device *); 501 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 502 503 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 504 sipcom_mii_bitbang_read, 505 sipcom_mii_bitbang_write, 506 { 507 EROMAR_MDIO, /* MII_BIT_MDO */ 508 EROMAR_MDIO, /* MII_BIT_MDI */ 509 EROMAR_MDC, /* MII_BIT_MDC */ 510 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 511 0, /* MII_BIT_DIR_PHY_HOST */ 512 } 513 }; 514 515 static const struct sip_variant sipcom_variant_dp83820 = { 516 sipcom_dp83820_mii_readreg, 517 sipcom_dp83820_mii_writereg, 518 sipcom_dp83820_mii_statchg, 519 sipcom_dp83815_set_filter, 520 sipcom_dp83820_read_macaddr, 521 }; 522 523 static const struct sip_variant sipcom_variant_sis900 = { 524 sipcom_sis900_mii_readreg, 525 sipcom_sis900_mii_writereg, 526 sipcom_sis900_mii_statchg, 527 sipcom_sis900_set_filter, 528 sipcom_sis900_read_macaddr, 529 }; 530 531 static const struct sip_variant sipcom_variant_dp83815 = { 532 sipcom_dp83815_mii_readreg, 533 sipcom_dp83815_mii_writereg, 534 sipcom_dp83815_mii_statchg, 535 sipcom_dp83815_set_filter, 536 sipcom_dp83815_read_macaddr, 537 }; 538 539 540 /* 541 * Devices supported by this driver. 542 */ 543 static const struct sip_product { 544 pci_vendor_id_t sip_vendor; 545 pci_product_id_t sip_product; 546 const char *sip_name; 547 const struct sip_variant *sip_variant; 548 const int sip_gigabit; 549 } sipcom_products[] = { 550 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 551 "NatSemi DP83820 Gigabit Ethernet", 552 &sipcom_variant_dp83820, 1 }, 553 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 554 "SiS 900 10/100 Ethernet", 555 &sipcom_variant_sis900, 0 }, 556 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 557 "SiS 7016 10/100 Ethernet", 558 &sipcom_variant_sis900, 0 }, 559 560 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 561 "NatSemi DP83815 10/100 Ethernet", 562 &sipcom_variant_dp83815, 0 }, 563 564 { 0, 0, 565 NULL, 566 NULL, 0 }, 567 }; 568 569 static const struct sip_product * 570 sipcom_lookup(const struct pci_attach_args *pa) 571 { 572 const struct sip_product *sip; 573 574 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 575 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 576 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 577 return (sip); 578 } 579 return (NULL); 580 } 581 582 /* 583 * I really hate stupid hardware vendors. There's a bit in the EEPROM 584 * which indicates if the card can do 64-bit data transfers. Unfortunately, 585 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 586 * which means we try to use 64-bit data transfers on those cards if we 587 * happen to be plugged into a 32-bit slot. 588 * 589 * What we do is use this table of cards known to be 64-bit cards. If 590 * you have a 64-bit card who's subsystem ID is not listed in this table, 591 * send the output of "pcictl dump ..." of the device to me so that your 592 * card will use the 64-bit data path when plugged into a 64-bit slot. 593 * 594 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 595 * June 30, 2002 596 */ 597 static int 598 sipcom_check_64bit(const struct pci_attach_args *pa) 599 { 600 static const struct { 601 pci_vendor_id_t c64_vendor; 602 pci_product_id_t c64_product; 603 } card64[] = { 604 /* Asante GigaNIX */ 605 { 0x128a, 0x0002 }, 606 607 /* Accton EN1407-T, Planex GN-1000TE */ 608 { 0x1113, 0x1407 }, 609 610 /* Netgear GA-621 */ 611 { 0x1385, 0x621a }, 612 613 /* SMC EZ Card */ 614 { 0x10b8, 0x9462 }, 615 616 { 0, 0} 617 }; 618 pcireg_t subsys; 619 int i; 620 621 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 622 623 for (i = 0; card64[i].c64_vendor != 0; i++) { 624 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 625 PCI_PRODUCT(subsys) == card64[i].c64_product) 626 return (1); 627 } 628 629 return (0); 630 } 631 632 static int 633 sipcom_match(struct device *parent, struct cfdata *cf, 634 void *aux) 635 { 636 struct pci_attach_args *pa = aux; 637 638 if (sipcom_lookup(pa) != NULL) 639 return (1); 640 641 return (0); 642 } 643 644 static void 645 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 646 { 647 u_int32_t reg; 648 int i; 649 650 /* 651 * Cause the chip to load configuration data from the EEPROM. 652 */ 653 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 654 for (i = 0; i < 10000; i++) { 655 delay(10); 656 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 657 PTSCR_EELOAD_EN) == 0) 658 break; 659 } 660 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 661 PTSCR_EELOAD_EN) { 662 printf("%s: timeout loading configuration from EEPROM\n", 663 sc->sc_dev.dv_xname); 664 return; 665 } 666 667 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 668 669 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 670 if (reg & CFG_PCI64_DET) { 671 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 672 /* 673 * Check to see if this card is 64-bit. If so, enable 64-bit 674 * data transfers. 675 * 676 * We can't use the DATA64_EN bit in the EEPROM, because 677 * vendors of 32-bit cards fail to clear that bit in many 678 * cases (yet the card still detects that it's in a 64-bit 679 * slot; go figure). 680 */ 681 if (sipcom_check_64bit(pa)) { 682 sc->sc_cfg |= CFG_DATA64_EN; 683 printf(", using 64-bit data transfers"); 684 } 685 printf("\n"); 686 } 687 688 /* 689 * XXX Need some PCI flags indicating support for 690 * XXX 64-bit addressing. 691 */ 692 #if 0 693 if (reg & CFG_M64ADDR) 694 sc->sc_cfg |= CFG_M64ADDR; 695 if (reg & CFG_T64ADDR) 696 sc->sc_cfg |= CFG_T64ADDR; 697 #endif 698 699 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 700 const char *sep = ""; 701 printf("%s: using ", sc->sc_dev.dv_xname); 702 if (reg & CFG_EXT_125) { 703 sc->sc_cfg |= CFG_EXT_125; 704 printf("%s125MHz clock", sep); 705 sep = ", "; 706 } 707 if (reg & CFG_TBI_EN) { 708 sc->sc_cfg |= CFG_TBI_EN; 709 printf("%sten-bit interface", sep); 710 sep = ", "; 711 } 712 printf("\n"); 713 } 714 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 715 (reg & CFG_MRM_DIS) != 0) 716 sc->sc_cfg |= CFG_MRM_DIS; 717 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 718 (reg & CFG_MWI_DIS) != 0) 719 sc->sc_cfg |= CFG_MWI_DIS; 720 721 /* 722 * Use the extended descriptor format on the DP83820. This 723 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 724 * checksumming. 725 */ 726 sc->sc_cfg |= CFG_EXTSTS_EN; 727 } 728 729 static int 730 sipcom_detach(device_t self, int flags) 731 { 732 sipcom_do_detach(self, SIP_ATTACH_FIN); 733 return 0; 734 } 735 736 static void 737 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 738 { 739 int i; 740 struct sip_softc *sc = device_private(self); 741 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 742 743 /* 744 * Free any resources we've allocated during attach. 745 * Do this in reverse order and fall through. 746 */ 747 switch (stage) { 748 case SIP_ATTACH_FIN: 749 sipcom_stop(ifp, 1); 750 pmf_device_deregister(self); 751 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 752 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 753 754 if (sc->sc_sdhook != NULL) 755 shutdownhook_disestablish(sc->sc_sdhook); 756 757 /*FALLTHROUGH*/ 758 case SIP_ATTACH_CREATE_RXMAP: 759 for (i = 0; i < sc->sc_nrxdesc; i++) { 760 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 761 bus_dmamap_destroy(sc->sc_dmat, 762 sc->sc_rxsoft[i].rxs_dmamap); 763 } 764 /*FALLTHROUGH*/ 765 case SIP_ATTACH_CREATE_TXMAP: 766 for (i = 0; i < SIP_TXQUEUELEN; i++) { 767 if (sc->sc_txsoft[i].txs_dmamap != NULL) 768 bus_dmamap_destroy(sc->sc_dmat, 769 sc->sc_txsoft[i].txs_dmamap); 770 } 771 /*FALLTHROUGH*/ 772 case SIP_ATTACH_LOAD_MAP: 773 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 774 /*FALLTHROUGH*/ 775 case SIP_ATTACH_CREATE_MAP: 776 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 777 /*FALLTHROUGH*/ 778 case SIP_ATTACH_MAP_MEM: 779 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 780 sizeof(struct sip_control_data)); 781 /*FALLTHROUGH*/ 782 case SIP_ATTACH_ALLOC_MEM: 783 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 784 break; 785 default: 786 break; 787 } 788 return; 789 } 790 791 static bool 792 sipcom_suspend(device_t self) 793 { 794 struct sip_softc *sc = device_private(self); 795 796 sc->sc_suspended = 1; 797 return true; 798 } 799 800 static bool 801 sipcom_resume(device_t self) 802 { 803 struct sip_softc *sc = device_private(self); 804 805 if (!sipcom_reset(sc)) 806 return false; 807 808 sc->sc_suspended = 0; 809 return true; 810 } 811 812 static void 813 sipcom_attach(struct device *parent, struct device *self, void *aux) 814 { 815 struct sip_softc *sc = (struct sip_softc *) self; 816 struct pci_attach_args *pa = aux; 817 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 818 pci_chipset_tag_t pc = pa->pa_pc; 819 pci_intr_handle_t ih; 820 const char *intrstr = NULL; 821 bus_space_tag_t iot, memt; 822 bus_space_handle_t ioh, memh; 823 int ioh_valid, memh_valid; 824 int i, rseg, error; 825 const struct sip_product *sip; 826 u_int8_t enaddr[ETHER_ADDR_LEN]; 827 pcireg_t pmreg; 828 pcireg_t memtype; 829 bus_size_t tx_dmamap_size; 830 int ntxsegs_alloc; 831 832 callout_init(&sc->sc_tick_ch, 0); 833 834 sip = sipcom_lookup(pa); 835 if (sip == NULL) { 836 printf("\n"); 837 panic("%s: impossible", __func__); 838 } 839 sc->sc_gigabit = sip->sip_gigabit; 840 841 sc->sc_pc = pc; 842 843 if (sc->sc_gigabit) { 844 sc->sc_rxbuf_len = MCLBYTES - 8; 845 tx_dmamap_size = ETHER_MAX_LEN_JUMBO; 846 sc->sc_ntxsegs = 64; 847 ntxsegs_alloc = GSIP_NTXSEGS_ALLOC; 848 sc->sc_nrxdesc = GSIP_NRXDESC; 849 } else { 850 sc->sc_rxbuf_len = MCLBYTES - 1; /* field width */ 851 tx_dmamap_size = MCLBYTES; 852 sc->sc_ntxsegs = 16; 853 ntxsegs_alloc = SIP_NTXSEGS_ALLOC; 854 sc->sc_nrxdesc = SIP_NRXDESC; 855 } 856 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 857 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 858 sc->sc_nrxdesc_mask = sc->sc_nrxdesc - 1; 859 860 sc->sc_rev = PCI_REVISION(pa->pa_class); 861 862 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 863 864 sc->sc_model = sip; 865 866 /* 867 * XXX Work-around broken PXE firmware on some boards. 868 * 869 * The DP83815 shares an address decoder with the MEM BAR 870 * and the ROM BAR. Make sure the ROM BAR is disabled, 871 * so that memory mapped access works. 872 */ 873 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 874 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 875 ~PCI_MAPREG_ROM_ENABLE); 876 877 /* 878 * Map the device. 879 */ 880 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 881 PCI_MAPREG_TYPE_IO, 0, 882 &iot, &ioh, NULL, NULL) == 0); 883 if (sc->sc_gigabit) { 884 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 885 switch (memtype) { 886 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 887 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 888 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 889 memtype, 0, &memt, &memh, NULL, NULL) == 0); 890 break; 891 default: 892 memh_valid = 0; 893 } 894 } else { 895 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 896 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 897 &memt, &memh, NULL, NULL) == 0); 898 } 899 900 if (memh_valid) { 901 sc->sc_st = memt; 902 sc->sc_sh = memh; 903 } else if (ioh_valid) { 904 sc->sc_st = iot; 905 sc->sc_sh = ioh; 906 } else { 907 printf("%s: unable to map device registers\n", 908 sc->sc_dev.dv_xname); 909 return; 910 } 911 912 sc->sc_dmat = pa->pa_dmat; 913 914 /* 915 * Make sure bus mastering is enabled. Also make sure 916 * Write/Invalidate is enabled if we're allowed to use it. 917 */ 918 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 919 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 920 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 921 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 922 pmreg | PCI_COMMAND_MASTER_ENABLE); 923 924 /* power up chip */ 925 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 926 NULL)) && error != EOPNOTSUPP) { 927 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 928 error); 929 return; 930 } 931 932 /* 933 * Map and establish our interrupt. 934 */ 935 if (pci_intr_map(pa, &ih)) { 936 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 937 return; 938 } 939 intrstr = pci_intr_string(pc, ih); 940 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 941 if (sc->sc_ih == NULL) { 942 printf("%s: unable to establish interrupt", 943 sc->sc_dev.dv_xname); 944 if (intrstr != NULL) 945 printf(" at %s", intrstr); 946 printf("\n"); 947 return; 948 } 949 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 950 951 SIMPLEQ_INIT(&sc->sc_txfreeq); 952 SIMPLEQ_INIT(&sc->sc_txdirtyq); 953 954 /* 955 * Allocate the control data structures, and create and load the 956 * DMA map for it. 957 */ 958 if ((error = bus_dmamem_alloc(sc->sc_dmat, 959 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 960 &rseg, 0)) != 0) { 961 printf("%s: unable to allocate control data, error = %d\n", 962 sc->sc_dev.dv_xname, error); 963 return sipcom_do_detach(self, -1); 964 } 965 966 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 967 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 968 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 969 printf("%s: unable to map control data, error = %d\n", 970 sc->sc_dev.dv_xname, error); 971 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 972 } 973 974 if ((error = bus_dmamap_create(sc->sc_dmat, 975 sizeof(struct sip_control_data), 1, 976 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 977 printf("%s: unable to create control data DMA map, " 978 "error = %d\n", sc->sc_dev.dv_xname, error); 979 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 980 } 981 982 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 983 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 984 0)) != 0) { 985 printf("%s: unable to load control data DMA map, error = %d\n", 986 sc->sc_dev.dv_xname, error); 987 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 988 } 989 990 /* 991 * Create the transmit buffer DMA maps. 992 */ 993 for (i = 0; i < SIP_TXQUEUELEN; i++) { 994 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 995 sc->sc_ntxsegs, MCLBYTES, 0, 0, 996 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 997 printf("%s: unable to create tx DMA map %d, " 998 "error = %d\n", sc->sc_dev.dv_xname, i, error); 999 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1000 } 1001 } 1002 1003 /* 1004 * Create the receive buffer DMA maps. 1005 */ 1006 for (i = 0; i < sc->sc_nrxdesc; i++) { 1007 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1008 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1009 printf("%s: unable to create rx DMA map %d, " 1010 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1011 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1012 } 1013 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1014 } 1015 1016 /* 1017 * Reset the chip to a known state. 1018 */ 1019 sipcom_reset(sc); 1020 1021 /* 1022 * Read the Ethernet address from the EEPROM. This might 1023 * also fetch other stuff from the EEPROM and stash it 1024 * in the softc. 1025 */ 1026 sc->sc_cfg = 0; 1027 if (!sc->sc_gigabit) { 1028 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1029 SIP_SIS900_REV(sc,SIS_REV_900B)) 1030 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1031 1032 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1033 SIP_SIS900_REV(sc,SIS_REV_960) || 1034 SIP_SIS900_REV(sc,SIS_REV_900B)) 1035 sc->sc_cfg |= 1036 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1037 CFG_EDBMASTEN); 1038 } 1039 1040 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1041 1042 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1043 ether_sprintf(enaddr)); 1044 1045 /* 1046 * Initialize the configuration register: aggressive PCI 1047 * bus request algorithm, default backoff, default OW timer, 1048 * default parity error detection. 1049 * 1050 * NOTE: "Big endian mode" is useless on the SiS900 and 1051 * friends -- it affects packet data, not descriptors. 1052 */ 1053 if (sc->sc_gigabit) 1054 sipcom_dp83820_attach(sc, pa); 1055 1056 /* 1057 * Initialize our media structures and probe the MII. 1058 */ 1059 sc->sc_mii.mii_ifp = ifp; 1060 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1061 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1062 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1063 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sipcom_mediachange, 1064 sipcom_mediastatus); 1065 1066 /* 1067 * XXX We cannot handle flow control on the DP83815. 1068 */ 1069 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1070 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1071 MII_OFFSET_ANY, 0); 1072 else 1073 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1074 MII_OFFSET_ANY, MIIF_DOPAUSE); 1075 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1076 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1077 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1078 } else 1079 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1080 1081 ifp = &sc->sc_ethercom.ec_if; 1082 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1083 ifp->if_softc = sc; 1084 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1085 sc->sc_if_flags = ifp->if_flags; 1086 ifp->if_ioctl = sipcom_ioctl; 1087 ifp->if_start = sipcom_start; 1088 ifp->if_watchdog = sipcom_watchdog; 1089 ifp->if_init = sipcom_init; 1090 ifp->if_stop = sipcom_stop; 1091 IFQ_SET_READY(&ifp->if_snd); 1092 1093 /* 1094 * We can support 802.1Q VLAN-sized frames. 1095 */ 1096 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1097 1098 if (sc->sc_gigabit) { 1099 /* 1100 * And the DP83820 can do VLAN tagging in hardware, and 1101 * support the jumbo Ethernet MTU. 1102 */ 1103 sc->sc_ethercom.ec_capabilities |= 1104 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1105 1106 /* 1107 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1108 * in hardware. 1109 */ 1110 ifp->if_capabilities |= 1111 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1112 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1113 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1114 } 1115 1116 /* 1117 * Attach the interface. 1118 */ 1119 if_attach(ifp); 1120 ether_ifattach(ifp, enaddr); 1121 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1122 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1123 sc->sc_prev.if_capenable = ifp->if_capenable; 1124 #if NRND > 0 1125 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1126 RND_TYPE_NET, 0); 1127 #endif 1128 1129 /* 1130 * The number of bytes that must be available in 1131 * the Tx FIFO before the bus master can DMA more 1132 * data into the FIFO. 1133 */ 1134 sc->sc_tx_fill_thresh = 64 / 32; 1135 1136 /* 1137 * Start at a drain threshold of 512 bytes. We will 1138 * increase it if a DMA underrun occurs. 1139 * 1140 * XXX The minimum value of this variable should be 1141 * tuned. We may be able to improve performance 1142 * by starting with a lower value. That, however, 1143 * may trash the first few outgoing packets if the 1144 * PCI bus is saturated. 1145 */ 1146 if (sc->sc_gigabit) 1147 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1148 else 1149 sc->sc_tx_drain_thresh = 1504 / 32; 1150 1151 /* 1152 * Initialize the Rx FIFO drain threshold. 1153 * 1154 * This is in units of 8 bytes. 1155 * 1156 * We should never set this value lower than 2; 14 bytes are 1157 * required to filter the packet. 1158 */ 1159 sc->sc_rx_drain_thresh = 128 / 8; 1160 1161 #ifdef SIP_EVENT_COUNTERS 1162 /* 1163 * Attach event counters. 1164 */ 1165 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1166 NULL, sc->sc_dev.dv_xname, "txsstall"); 1167 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1168 NULL, sc->sc_dev.dv_xname, "txdstall"); 1169 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1170 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1171 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1172 NULL, sc->sc_dev.dv_xname, "txdintr"); 1173 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1174 NULL, sc->sc_dev.dv_xname, "txiintr"); 1175 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1176 NULL, sc->sc_dev.dv_xname, "rxintr"); 1177 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1178 NULL, sc->sc_dev.dv_xname, "hiberr"); 1179 if (!sc->sc_gigabit) { 1180 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1181 NULL, sc->sc_dev.dv_xname, "rxpause"); 1182 } else { 1183 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1184 NULL, sc->sc_dev.dv_xname, "rxpause"); 1185 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1186 NULL, sc->sc_dev.dv_xname, "txpause"); 1187 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1188 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1189 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1190 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1191 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1192 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1193 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1194 NULL, sc->sc_dev.dv_xname, "txipsum"); 1195 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1196 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1197 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1198 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1199 } 1200 #endif /* SIP_EVENT_COUNTERS */ 1201 1202 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1203 aprint_error_dev(self, "couldn't establish power handler\n"); 1204 else 1205 pmf_class_network_register(self, ifp); 1206 1207 /* 1208 * Make sure the interface is shutdown during reboot. 1209 */ 1210 sc->sc_sdhook = shutdownhook_establish(sipcom_shutdown, sc); 1211 if (sc->sc_sdhook == NULL) 1212 printf("%s: WARNING: unable to establish shutdown hook\n", 1213 sc->sc_dev.dv_xname); 1214 } 1215 1216 /* 1217 * sip_shutdown: 1218 * 1219 * Make sure the interface is stopped at reboot time. 1220 */ 1221 static void 1222 sipcom_shutdown(void *arg) 1223 { 1224 struct sip_softc *sc = arg; 1225 1226 sipcom_stop(&sc->sc_ethercom.ec_if, 1); 1227 } 1228 1229 static inline void 1230 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1231 uint64_t capenable) 1232 { 1233 struct m_tag *mtag; 1234 u_int32_t extsts; 1235 /* 1236 * If VLANs are enabled and the packet has a VLAN tag, set 1237 * up the descriptor to encapsulate the packet for us. 1238 * 1239 * This apparently has to be on the last descriptor of 1240 * the packet. 1241 */ 1242 1243 /* 1244 * Byte swapping is tricky. We need to provide the tag 1245 * in a network byte order. On a big-endian machine, 1246 * the byteorder is correct, but we need to swap it 1247 * anyway, because this will be undone by the outside 1248 * htole32(). That's why there must be an 1249 * unconditional swap instead of htons() inside. 1250 */ 1251 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1252 sc->sc_txdescs[lasttx].sipd_extsts |= 1253 htole32(EXTSTS_VPKT | 1254 (bswap16(VLAN_TAG_VALUE(mtag)) & 1255 EXTSTS_VTCI)); 1256 } 1257 1258 /* 1259 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1260 * checksumming, set up the descriptor to do this work 1261 * for us. 1262 * 1263 * This apparently has to be on the first descriptor of 1264 * the packet. 1265 * 1266 * Byte-swap constants so the compiler can optimize. 1267 */ 1268 extsts = 0; 1269 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1270 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1271 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1272 extsts |= htole32(EXTSTS_IPPKT); 1273 } 1274 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1275 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1276 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1277 extsts |= htole32(EXTSTS_TCPPKT); 1278 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1279 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1280 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1281 extsts |= htole32(EXTSTS_UDPPKT); 1282 } 1283 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1284 } 1285 1286 /* 1287 * sip_start: [ifnet interface function] 1288 * 1289 * Start packet transmission on the interface. 1290 */ 1291 static void 1292 sipcom_start(struct ifnet *ifp) 1293 { 1294 struct sip_softc *sc = ifp->if_softc; 1295 struct mbuf *m0; 1296 struct mbuf *m; 1297 struct sip_txsoft *txs; 1298 bus_dmamap_t dmamap; 1299 int error, nexttx, lasttx, seg; 1300 int ofree = sc->sc_txfree; 1301 #if 0 1302 int firsttx = sc->sc_txnext; 1303 #endif 1304 1305 /* 1306 * If we've been told to pause, don't transmit any more packets. 1307 */ 1308 if (!sc->sc_gigabit && sc->sc_paused) 1309 ifp->if_flags |= IFF_OACTIVE; 1310 1311 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1312 return; 1313 1314 /* 1315 * Loop through the send queue, setting up transmit descriptors 1316 * until we drain the queue, or use up all available transmit 1317 * descriptors. 1318 */ 1319 for (;;) { 1320 /* Get a work queue entry. */ 1321 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1322 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1323 break; 1324 } 1325 1326 /* 1327 * Grab a packet off the queue. 1328 */ 1329 IFQ_POLL(&ifp->if_snd, m0); 1330 if (m0 == NULL) 1331 break; 1332 m = NULL; 1333 1334 dmamap = txs->txs_dmamap; 1335 1336 /* 1337 * Load the DMA map. If this fails, the packet either 1338 * didn't fit in the alloted number of segments, or we 1339 * were short on resources. 1340 */ 1341 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1342 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1343 /* In the non-gigabit case, we'll copy and try again. */ 1344 if (error != 0 && !sc->sc_gigabit) { 1345 MGETHDR(m, M_DONTWAIT, MT_DATA); 1346 if (m == NULL) { 1347 printf("%s: unable to allocate Tx mbuf\n", 1348 sc->sc_dev.dv_xname); 1349 break; 1350 } 1351 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1352 if (m0->m_pkthdr.len > MHLEN) { 1353 MCLGET(m, M_DONTWAIT); 1354 if ((m->m_flags & M_EXT) == 0) { 1355 printf("%s: unable to allocate Tx " 1356 "cluster\n", sc->sc_dev.dv_xname); 1357 m_freem(m); 1358 break; 1359 } 1360 } 1361 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1362 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1363 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1364 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1365 if (error) { 1366 printf("%s: unable to load Tx buffer, " 1367 "error = %d\n", sc->sc_dev.dv_xname, error); 1368 break; 1369 } 1370 } else if (error == EFBIG) { 1371 /* 1372 * For the too-many-segments case, we simply 1373 * report an error and drop the packet, 1374 * since we can't sanely copy a jumbo packet 1375 * to a single buffer. 1376 */ 1377 printf("%s: Tx packet consumes too many " 1378 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1379 IFQ_DEQUEUE(&ifp->if_snd, m0); 1380 m_freem(m0); 1381 continue; 1382 } else if (error != 0) { 1383 /* 1384 * Short on resources, just stop for now. 1385 */ 1386 break; 1387 } 1388 1389 /* 1390 * Ensure we have enough descriptors free to describe 1391 * the packet. Note, we always reserve one descriptor 1392 * at the end of the ring as a termination point, to 1393 * prevent wrap-around. 1394 */ 1395 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1396 /* 1397 * Not enough free descriptors to transmit this 1398 * packet. We haven't committed anything yet, 1399 * so just unload the DMA map, put the packet 1400 * back on the queue, and punt. Notify the upper 1401 * layer that there are not more slots left. 1402 * 1403 * XXX We could allocate an mbuf and copy, but 1404 * XXX is it worth it? 1405 */ 1406 ifp->if_flags |= IFF_OACTIVE; 1407 bus_dmamap_unload(sc->sc_dmat, dmamap); 1408 if (m != NULL) 1409 m_freem(m); 1410 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1411 break; 1412 } 1413 1414 IFQ_DEQUEUE(&ifp->if_snd, m0); 1415 if (m != NULL) { 1416 m_freem(m0); 1417 m0 = m; 1418 } 1419 1420 /* 1421 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1422 */ 1423 1424 /* Sync the DMA map. */ 1425 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1426 BUS_DMASYNC_PREWRITE); 1427 1428 /* 1429 * Initialize the transmit descriptors. 1430 */ 1431 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1432 seg < dmamap->dm_nsegs; 1433 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1434 /* 1435 * If this is the first descriptor we're 1436 * enqueueing, don't set the OWN bit just 1437 * yet. That could cause a race condition. 1438 * We'll do it below. 1439 */ 1440 sc->sc_txdescs[nexttx].sipd_bufptr = 1441 htole32(dmamap->dm_segs[seg].ds_addr); 1442 sc->sc_txdescs[nexttx].sipd_cmdsts = 1443 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1444 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1445 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1446 lasttx = nexttx; 1447 } 1448 1449 /* Clear the MORE bit on the last segment. */ 1450 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1451 1452 /* 1453 * If we're in the interrupt delay window, delay the 1454 * interrupt. 1455 */ 1456 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1457 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1458 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1459 htole32(CMDSTS_INTR); 1460 sc->sc_txwin = 0; 1461 } 1462 1463 if (sc->sc_gigabit) 1464 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1465 1466 /* Sync the descriptors we're using. */ 1467 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1468 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1469 1470 /* 1471 * The entire packet is set up. Give the first descrptor 1472 * to the chip now. 1473 */ 1474 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1475 htole32(CMDSTS_OWN); 1476 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1477 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1478 1479 /* 1480 * Store a pointer to the packet so we can free it later, 1481 * and remember what txdirty will be once the packet is 1482 * done. 1483 */ 1484 txs->txs_mbuf = m0; 1485 txs->txs_firstdesc = sc->sc_txnext; 1486 txs->txs_lastdesc = lasttx; 1487 1488 /* Advance the tx pointer. */ 1489 sc->sc_txfree -= dmamap->dm_nsegs; 1490 sc->sc_txnext = nexttx; 1491 1492 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1493 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1494 1495 #if NBPFILTER > 0 1496 /* 1497 * Pass the packet to any BPF listeners. 1498 */ 1499 if (ifp->if_bpf) 1500 bpf_mtap(ifp->if_bpf, m0); 1501 #endif /* NBPFILTER > 0 */ 1502 } 1503 1504 if (txs == NULL || sc->sc_txfree == 0) { 1505 /* No more slots left; notify upper layer. */ 1506 ifp->if_flags |= IFF_OACTIVE; 1507 } 1508 1509 if (sc->sc_txfree != ofree) { 1510 /* 1511 * Start the transmit process. Note, the manual says 1512 * that if there are no pending transmissions in the 1513 * chip's internal queue (indicated by TXE being clear), 1514 * then the driver software must set the TXDP to the 1515 * first descriptor to be transmitted. However, if we 1516 * do this, it causes serious performance degredation on 1517 * the DP83820 under load, not setting TXDP doesn't seem 1518 * to adversely affect the SiS 900 or DP83815. 1519 * 1520 * Well, I guess it wouldn't be the first time a manual 1521 * has lied -- and they could be speaking of the NULL- 1522 * terminated descriptor list case, rather than OWN- 1523 * terminated rings. 1524 */ 1525 #if 0 1526 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1527 CR_TXE) == 0) { 1528 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1529 SIP_CDTXADDR(sc, firsttx)); 1530 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1531 } 1532 #else 1533 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1534 #endif 1535 1536 /* Set a watchdog timer in case the chip flakes out. */ 1537 /* Gigabit autonegotiation takes 5 seconds. */ 1538 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1539 } 1540 } 1541 1542 /* 1543 * sip_watchdog: [ifnet interface function] 1544 * 1545 * Watchdog timer handler. 1546 */ 1547 static void 1548 sipcom_watchdog(struct ifnet *ifp) 1549 { 1550 struct sip_softc *sc = ifp->if_softc; 1551 1552 /* 1553 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1554 * If we get a timeout, try and sweep up transmit descriptors. 1555 * If we manage to sweep them all up, ignore the lack of 1556 * interrupt. 1557 */ 1558 sipcom_txintr(sc); 1559 1560 if (sc->sc_txfree != sc->sc_ntxdesc) { 1561 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1562 ifp->if_oerrors++; 1563 1564 /* Reset the interface. */ 1565 (void) sipcom_init(ifp); 1566 } else if (ifp->if_flags & IFF_DEBUG) 1567 printf("%s: recovered from device timeout\n", 1568 sc->sc_dev.dv_xname); 1569 1570 /* Try to get more packets going. */ 1571 sipcom_start(ifp); 1572 } 1573 1574 /* 1575 * sip_ioctl: [ifnet interface function] 1576 * 1577 * Handle control requests from the operator. 1578 */ 1579 static int 1580 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1581 { 1582 struct sip_softc *sc = ifp->if_softc; 1583 struct ifreq *ifr = (struct ifreq *)data; 1584 int s, error; 1585 1586 s = splnet(); 1587 1588 switch (cmd) { 1589 case SIOCSIFMEDIA: 1590 /* Flow control requires full-duplex mode. */ 1591 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1592 (ifr->ifr_media & IFM_FDX) == 0) 1593 ifr->ifr_media &= ~IFM_ETH_FMASK; 1594 1595 /* XXX */ 1596 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1597 ifr->ifr_media &= ~IFM_ETH_FMASK; 1598 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1599 if (sc->sc_gigabit && 1600 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1601 /* We can do both TXPAUSE and RXPAUSE. */ 1602 ifr->ifr_media |= 1603 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1604 } else if (ifr->ifr_media & IFM_FLOW) { 1605 /* 1606 * Both TXPAUSE and RXPAUSE must be set. 1607 * (SiS900 and DP83815 don't have PAUSE_ASYM 1608 * feature.) 1609 * 1610 * XXX Can SiS900 and DP83815 send PAUSE? 1611 */ 1612 ifr->ifr_media |= 1613 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1614 } 1615 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1616 } 1617 /* FALLTHROUGH */ 1618 case SIOCGIFMEDIA: 1619 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1620 break; 1621 case SIOCSIFFLAGS: 1622 /* If the interface is up and running, only modify the receive 1623 * filter when setting promiscuous or debug mode. Otherwise 1624 * fall through to ether_ioctl, which will reset the chip. 1625 */ 1626 1627 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1628 == (sc)->sc_ethercom.ec_capenable) \ 1629 && ((sc)->sc_prev.is_vlan == \ 1630 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1631 1632 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1633 1634 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1635 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1636 == (IFF_UP|IFF_RUNNING)) 1637 && ((ifp->if_flags & (~RESETIGN)) 1638 == (sc->sc_if_flags & (~RESETIGN))) 1639 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1640 /* Set up the receive filter. */ 1641 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1642 error = 0; 1643 break; 1644 #undef RESETIGN 1645 } 1646 /* FALLTHROUGH */ 1647 default: 1648 error = ether_ioctl(ifp, cmd, data); 1649 if (error == ENETRESET) { 1650 /* 1651 * Multicast list has changed; set the hardware filter 1652 * accordingly. 1653 */ 1654 if (ifp->if_flags & IFF_RUNNING) 1655 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1656 error = 0; 1657 } 1658 break; 1659 } 1660 1661 /* Try to get more packets going. */ 1662 sipcom_start(ifp); 1663 1664 sc->sc_if_flags = ifp->if_flags; 1665 splx(s); 1666 return (error); 1667 } 1668 1669 /* 1670 * sip_intr: 1671 * 1672 * Interrupt service routine. 1673 */ 1674 static int 1675 sipcom_intr(void *arg) 1676 { 1677 struct sip_softc *sc = arg; 1678 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1679 u_int32_t isr; 1680 int handled = 0; 1681 1682 /* Disable interrupts. */ 1683 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1684 1685 for (;;) { 1686 /* Reading clears interrupt. */ 1687 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1688 if ((isr & sc->sc_imr) == 0) 1689 break; 1690 1691 #if NRND > 0 1692 if (RND_ENABLED(&sc->rnd_source)) 1693 rnd_add_uint32(&sc->rnd_source, isr); 1694 #endif 1695 1696 handled = 1; 1697 1698 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1699 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1700 1701 /* Grab any new packets. */ 1702 SIP_DECL(rxintr)(sc); 1703 1704 if (isr & ISR_RXORN) { 1705 printf("%s: receive FIFO overrun\n", 1706 sc->sc_dev.dv_xname); 1707 1708 /* XXX adjust rx_drain_thresh? */ 1709 } 1710 1711 if (isr & ISR_RXIDLE) { 1712 printf("%s: receive ring overrun\n", 1713 sc->sc_dev.dv_xname); 1714 1715 /* Get the receive process going again. */ 1716 bus_space_write_4(sc->sc_st, sc->sc_sh, 1717 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1718 bus_space_write_4(sc->sc_st, sc->sc_sh, 1719 SIP_CR, CR_RXE); 1720 } 1721 } 1722 1723 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1724 #ifdef SIP_EVENT_COUNTERS 1725 if (isr & ISR_TXDESC) 1726 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1727 else if (isr & ISR_TXIDLE) 1728 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1729 #endif 1730 1731 /* Sweep up transmit descriptors. */ 1732 sipcom_txintr(sc); 1733 1734 if (isr & ISR_TXURN) { 1735 u_int32_t thresh; 1736 1737 printf("%s: transmit FIFO underrun", 1738 sc->sc_dev.dv_xname); 1739 1740 thresh = sc->sc_tx_drain_thresh + 1; 1741 if (thresh <= TXCFG_DRTH && 1742 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1743 (sc->sc_tx_fill_thresh * 32))) { 1744 printf("; increasing Tx drain " 1745 "threshold to %u bytes\n", 1746 thresh * 32); 1747 sc->sc_tx_drain_thresh = thresh; 1748 (void) sipcom_init(ifp); 1749 } else { 1750 (void) sipcom_init(ifp); 1751 printf("\n"); 1752 } 1753 } 1754 } 1755 1756 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1757 if (isr & ISR_PAUSE_ST) { 1758 sc->sc_paused = 1; 1759 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1760 ifp->if_flags |= IFF_OACTIVE; 1761 } 1762 if (isr & ISR_PAUSE_END) { 1763 sc->sc_paused = 0; 1764 ifp->if_flags &= ~IFF_OACTIVE; 1765 } 1766 } 1767 1768 if (isr & ISR_HIBERR) { 1769 int want_init = 0; 1770 1771 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1772 1773 #define PRINTERR(bit, str) \ 1774 do { \ 1775 if ((isr & (bit)) != 0) { \ 1776 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1777 printf("%s: %s\n", \ 1778 sc->sc_dev.dv_xname, str); \ 1779 want_init = 1; \ 1780 } \ 1781 } while (/*CONSTCOND*/0) 1782 1783 PRINTERR(ISR_DPERR, "parity error"); 1784 PRINTERR(ISR_SSERR, "system error"); 1785 PRINTERR(ISR_RMABT, "master abort"); 1786 PRINTERR(ISR_RTABT, "target abort"); 1787 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1788 /* 1789 * Ignore: 1790 * Tx reset complete 1791 * Rx reset complete 1792 */ 1793 if (want_init) 1794 (void) sipcom_init(ifp); 1795 #undef PRINTERR 1796 } 1797 } 1798 1799 /* Re-enable interrupts. */ 1800 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1801 1802 /* Try to get more packets going. */ 1803 sipcom_start(ifp); 1804 1805 return (handled); 1806 } 1807 1808 /* 1809 * sip_txintr: 1810 * 1811 * Helper; handle transmit interrupts. 1812 */ 1813 static void 1814 sipcom_txintr(struct sip_softc *sc) 1815 { 1816 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1817 struct sip_txsoft *txs; 1818 u_int32_t cmdsts; 1819 1820 if (sc->sc_paused == 0) 1821 ifp->if_flags &= ~IFF_OACTIVE; 1822 1823 /* 1824 * Go through our Tx list and free mbufs for those 1825 * frames which have been transmitted. 1826 */ 1827 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1828 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1829 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1830 1831 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1832 if (cmdsts & CMDSTS_OWN) 1833 break; 1834 1835 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1836 1837 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1838 1839 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1840 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1841 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1842 m_freem(txs->txs_mbuf); 1843 txs->txs_mbuf = NULL; 1844 1845 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1846 1847 /* 1848 * Check for errors and collisions. 1849 */ 1850 if (cmdsts & 1851 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1852 ifp->if_oerrors++; 1853 if (cmdsts & CMDSTS_Tx_EC) 1854 ifp->if_collisions += 16; 1855 if (ifp->if_flags & IFF_DEBUG) { 1856 if (cmdsts & CMDSTS_Tx_ED) 1857 printf("%s: excessive deferral\n", 1858 sc->sc_dev.dv_xname); 1859 if (cmdsts & CMDSTS_Tx_EC) 1860 printf("%s: excessive collisions\n", 1861 sc->sc_dev.dv_xname); 1862 } 1863 } else { 1864 /* Packet was transmitted successfully. */ 1865 ifp->if_opackets++; 1866 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1867 } 1868 } 1869 1870 /* 1871 * If there are no more pending transmissions, cancel the watchdog 1872 * timer. 1873 */ 1874 if (txs == NULL) { 1875 ifp->if_timer = 0; 1876 sc->sc_txwin = 0; 1877 } 1878 } 1879 1880 #if defined(DP83820) 1881 /* 1882 * sip_rxintr: 1883 * 1884 * Helper; handle receive interrupts. 1885 */ 1886 static void 1887 SIP_DECL(rxintr)(struct sip_softc *sc) 1888 { 1889 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1890 struct sip_rxsoft *rxs; 1891 struct mbuf *m; 1892 u_int32_t cmdsts, extsts; 1893 int i, len; 1894 1895 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 1896 rxs = &sc->sc_rxsoft[i]; 1897 1898 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1899 1900 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1901 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1902 len = CMDSTS_SIZE(cmdsts); 1903 1904 /* 1905 * NOTE: OWN is set if owned by _consumer_. We're the 1906 * consumer of the receive ring, so if the bit is clear, 1907 * we have processed all of the packets. 1908 */ 1909 if ((cmdsts & CMDSTS_OWN) == 0) { 1910 /* 1911 * We have processed all of the receive buffers. 1912 */ 1913 break; 1914 } 1915 1916 if (__predict_false(sc->sc_rxdiscard)) { 1917 SIP_INIT_RXDESC(sc, i); 1918 if ((cmdsts & CMDSTS_MORE) == 0) { 1919 /* Reset our state. */ 1920 sc->sc_rxdiscard = 0; 1921 } 1922 continue; 1923 } 1924 1925 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1926 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1927 1928 m = rxs->rxs_mbuf; 1929 1930 /* 1931 * Add a new receive buffer to the ring. 1932 */ 1933 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1934 /* 1935 * Failed, throw away what we've done so 1936 * far, and discard the rest of the packet. 1937 */ 1938 ifp->if_ierrors++; 1939 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1940 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1941 SIP_INIT_RXDESC(sc, i); 1942 if (cmdsts & CMDSTS_MORE) 1943 sc->sc_rxdiscard = 1; 1944 if (sc->sc_rxhead != NULL) 1945 m_freem(sc->sc_rxhead); 1946 SIP_RXCHAIN_RESET(sc); 1947 continue; 1948 } 1949 1950 SIP_RXCHAIN_LINK(sc, m); 1951 1952 m->m_len = len; 1953 1954 /* 1955 * If this is not the end of the packet, keep 1956 * looking. 1957 */ 1958 if (cmdsts & CMDSTS_MORE) { 1959 sc->sc_rxlen += len; 1960 continue; 1961 } 1962 1963 /* 1964 * Okay, we have the entire packet now. The chip includes 1965 * the FCS, so we need to trim it. 1966 */ 1967 m->m_len -= ETHER_CRC_LEN; 1968 1969 *sc->sc_rxtailp = NULL; 1970 len = m->m_len + sc->sc_rxlen; 1971 m = sc->sc_rxhead; 1972 1973 SIP_RXCHAIN_RESET(sc); 1974 1975 /* 1976 * If an error occurred, update stats and drop the packet. 1977 */ 1978 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1979 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1980 ifp->if_ierrors++; 1981 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1982 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1983 /* Receive overrun handled elsewhere. */ 1984 printf("%s: receive descriptor error\n", 1985 sc->sc_dev.dv_xname); 1986 } 1987 #define PRINTERR(bit, str) \ 1988 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1989 (cmdsts & (bit)) != 0) \ 1990 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1991 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1992 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1993 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1994 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1995 #undef PRINTERR 1996 m_freem(m); 1997 continue; 1998 } 1999 2000 /* 2001 * If the packet is small enough to fit in a 2002 * single header mbuf, allocate one and copy 2003 * the data into it. This greatly reduces 2004 * memory consumption when we receive lots 2005 * of small packets. 2006 */ 2007 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 2008 struct mbuf *nm; 2009 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2010 if (nm == NULL) { 2011 ifp->if_ierrors++; 2012 m_freem(m); 2013 continue; 2014 } 2015 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2016 nm->m_data += 2; 2017 nm->m_pkthdr.len = nm->m_len = len; 2018 m_copydata(m, 0, len, mtod(nm, void *)); 2019 m_freem(m); 2020 m = nm; 2021 } 2022 #ifndef __NO_STRICT_ALIGNMENT 2023 else { 2024 /* 2025 * The DP83820's receive buffers must be 4-byte 2026 * aligned. But this means that the data after 2027 * the Ethernet header is misaligned. To compensate, 2028 * we have artificially shortened the buffer size 2029 * in the descriptor, and we do an overlapping copy 2030 * of the data two bytes further in (in the first 2031 * buffer of the chain only). 2032 */ 2033 memmove(mtod(m, char *) + 2, mtod(m, void *), 2034 m->m_len); 2035 m->m_data += 2; 2036 } 2037 #endif /* ! __NO_STRICT_ALIGNMENT */ 2038 2039 /* 2040 * If VLANs are enabled, VLAN packets have been unwrapped 2041 * for us. Associate the tag with the packet. 2042 */ 2043 2044 /* 2045 * Again, byte swapping is tricky. Hardware provided 2046 * the tag in the network byte order, but extsts was 2047 * passed through le32toh() in the meantime. On a 2048 * big-endian machine, we need to swap it again. On a 2049 * little-endian machine, we need to convert from the 2050 * network to host byte order. This means that we must 2051 * swap it in any case, so unconditional swap instead 2052 * of htons() is used. 2053 */ 2054 if ((extsts & EXTSTS_VPKT) != 0) { 2055 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2056 continue); 2057 } 2058 2059 /* 2060 * Set the incoming checksum information for the 2061 * packet. 2062 */ 2063 if ((extsts & EXTSTS_IPPKT) != 0) { 2064 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2065 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2066 if (extsts & EXTSTS_Rx_IPERR) 2067 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2068 if (extsts & EXTSTS_TCPPKT) { 2069 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2070 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2071 if (extsts & EXTSTS_Rx_TCPERR) 2072 m->m_pkthdr.csum_flags |= 2073 M_CSUM_TCP_UDP_BAD; 2074 } else if (extsts & EXTSTS_UDPPKT) { 2075 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2076 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2077 if (extsts & EXTSTS_Rx_UDPERR) 2078 m->m_pkthdr.csum_flags |= 2079 M_CSUM_TCP_UDP_BAD; 2080 } 2081 } 2082 2083 ifp->if_ipackets++; 2084 m->m_pkthdr.rcvif = ifp; 2085 m->m_pkthdr.len = len; 2086 2087 #if NBPFILTER > 0 2088 /* 2089 * Pass this up to any BPF listeners, but only 2090 * pass if up the stack if it's for us. 2091 */ 2092 if (ifp->if_bpf) 2093 bpf_mtap(ifp->if_bpf, m); 2094 #endif /* NBPFILTER > 0 */ 2095 2096 /* Pass it on. */ 2097 (*ifp->if_input)(ifp, m); 2098 } 2099 2100 /* Update the receive pointer. */ 2101 sc->sc_rxptr = i; 2102 } 2103 #else /* ! DP83820 */ 2104 /* 2105 * sip_rxintr: 2106 * 2107 * Helper; handle receive interrupts. 2108 */ 2109 static void 2110 SIP_DECL(rxintr)(struct sip_softc *sc) 2111 { 2112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2113 struct sip_rxsoft *rxs; 2114 struct mbuf *m; 2115 u_int32_t cmdsts; 2116 int i, len; 2117 2118 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2119 rxs = &sc->sc_rxsoft[i]; 2120 2121 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2122 2123 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2124 2125 /* 2126 * NOTE: OWN is set if owned by _consumer_. We're the 2127 * consumer of the receive ring, so if the bit is clear, 2128 * we have processed all of the packets. 2129 */ 2130 if ((cmdsts & CMDSTS_OWN) == 0) { 2131 /* 2132 * We have processed all of the receive buffers. 2133 */ 2134 break; 2135 } 2136 2137 /* 2138 * If any collisions were seen on the wire, count one. 2139 */ 2140 if (cmdsts & CMDSTS_Rx_COL) 2141 ifp->if_collisions++; 2142 2143 /* 2144 * If an error occurred, update stats, clear the status 2145 * word, and leave the packet buffer in place. It will 2146 * simply be reused the next time the ring comes around. 2147 */ 2148 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2149 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2150 ifp->if_ierrors++; 2151 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2152 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2153 /* Receive overrun handled elsewhere. */ 2154 printf("%s: receive descriptor error\n", 2155 sc->sc_dev.dv_xname); 2156 } 2157 #define PRINTERR(bit, str) \ 2158 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2159 (cmdsts & (bit)) != 0) \ 2160 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2161 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2162 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2163 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2164 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2165 #undef PRINTERR 2166 SIP_INIT_RXDESC(sc, i); 2167 continue; 2168 } 2169 2170 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2171 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2172 2173 /* 2174 * No errors; receive the packet. Note, the SiS 900 2175 * includes the CRC with every packet. 2176 */ 2177 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2178 2179 #ifdef __NO_STRICT_ALIGNMENT 2180 /* 2181 * If the packet is small enough to fit in a 2182 * single header mbuf, allocate one and copy 2183 * the data into it. This greatly reduces 2184 * memory consumption when we receive lots 2185 * of small packets. 2186 * 2187 * Otherwise, we add a new buffer to the receive 2188 * chain. If this fails, we drop the packet and 2189 * recycle the old buffer. 2190 */ 2191 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2192 MGETHDR(m, M_DONTWAIT, MT_DATA); 2193 if (m == NULL) 2194 goto dropit; 2195 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2196 memcpy(mtod(m, void *), 2197 mtod(rxs->rxs_mbuf, void *), len); 2198 SIP_INIT_RXDESC(sc, i); 2199 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2200 rxs->rxs_dmamap->dm_mapsize, 2201 BUS_DMASYNC_PREREAD); 2202 } else { 2203 m = rxs->rxs_mbuf; 2204 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2205 dropit: 2206 ifp->if_ierrors++; 2207 SIP_INIT_RXDESC(sc, i); 2208 bus_dmamap_sync(sc->sc_dmat, 2209 rxs->rxs_dmamap, 0, 2210 rxs->rxs_dmamap->dm_mapsize, 2211 BUS_DMASYNC_PREREAD); 2212 continue; 2213 } 2214 } 2215 #else 2216 /* 2217 * The SiS 900's receive buffers must be 4-byte aligned. 2218 * But this means that the data after the Ethernet header 2219 * is misaligned. We must allocate a new buffer and 2220 * copy the data, shifted forward 2 bytes. 2221 */ 2222 MGETHDR(m, M_DONTWAIT, MT_DATA); 2223 if (m == NULL) { 2224 dropit: 2225 ifp->if_ierrors++; 2226 SIP_INIT_RXDESC(sc, i); 2227 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2228 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2229 continue; 2230 } 2231 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2232 if (len > (MHLEN - 2)) { 2233 MCLGET(m, M_DONTWAIT); 2234 if ((m->m_flags & M_EXT) == 0) { 2235 m_freem(m); 2236 goto dropit; 2237 } 2238 } 2239 m->m_data += 2; 2240 2241 /* 2242 * Note that we use clusters for incoming frames, so the 2243 * buffer is virtually contiguous. 2244 */ 2245 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2246 2247 /* Allow the receive descriptor to continue using its mbuf. */ 2248 SIP_INIT_RXDESC(sc, i); 2249 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2250 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2251 #endif /* __NO_STRICT_ALIGNMENT */ 2252 2253 ifp->if_ipackets++; 2254 m->m_pkthdr.rcvif = ifp; 2255 m->m_pkthdr.len = m->m_len = len; 2256 2257 #if NBPFILTER > 0 2258 /* 2259 * Pass this up to any BPF listeners, but only 2260 * pass if up the stack if it's for us. 2261 */ 2262 if (ifp->if_bpf) 2263 bpf_mtap(ifp->if_bpf, m); 2264 #endif /* NBPFILTER > 0 */ 2265 2266 /* Pass it on. */ 2267 (*ifp->if_input)(ifp, m); 2268 } 2269 2270 /* Update the receive pointer. */ 2271 sc->sc_rxptr = i; 2272 } 2273 #endif /* DP83820 */ 2274 2275 /* 2276 * sip_tick: 2277 * 2278 * One second timer, used to tick the MII. 2279 */ 2280 static void 2281 sipcom_tick(void *arg) 2282 { 2283 struct sip_softc *sc = arg; 2284 int s; 2285 2286 s = splnet(); 2287 #ifdef SIP_EVENT_COUNTERS 2288 if (sc->sc_gigabit) { 2289 /* Read PAUSE related counts from MIB registers. */ 2290 sc->sc_ev_rxpause.ev_count += 2291 bus_space_read_4(sc->sc_st, sc->sc_sh, 2292 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2293 sc->sc_ev_txpause.ev_count += 2294 bus_space_read_4(sc->sc_st, sc->sc_sh, 2295 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2296 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2297 } 2298 #endif /* SIP_EVENT_COUNTERS */ 2299 mii_tick(&sc->sc_mii); 2300 splx(s); 2301 2302 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2303 } 2304 2305 /* 2306 * sip_reset: 2307 * 2308 * Perform a soft reset on the SiS 900. 2309 */ 2310 static bool 2311 sipcom_reset(struct sip_softc *sc) 2312 { 2313 bus_space_tag_t st = sc->sc_st; 2314 bus_space_handle_t sh = sc->sc_sh; 2315 int i; 2316 2317 bus_space_write_4(st, sh, SIP_IER, 0); 2318 bus_space_write_4(st, sh, SIP_IMR, 0); 2319 bus_space_write_4(st, sh, SIP_RFCR, 0); 2320 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2321 2322 for (i = 0; i < SIP_TIMEOUT; i++) { 2323 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2324 break; 2325 delay(2); 2326 } 2327 2328 if (i == SIP_TIMEOUT) { 2329 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2330 return false; 2331 } 2332 2333 delay(1000); 2334 2335 if (sc->sc_gigabit) { 2336 /* 2337 * Set the general purpose I/O bits. Do it here in case we 2338 * need to have GPIO set up to talk to the media interface. 2339 */ 2340 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2341 delay(1000); 2342 } 2343 return true; 2344 } 2345 2346 static void 2347 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2348 { 2349 u_int32_t reg; 2350 bus_space_tag_t st = sc->sc_st; 2351 bus_space_handle_t sh = sc->sc_sh; 2352 /* 2353 * Initialize the VLAN/IP receive control register. 2354 * We enable checksum computation on all incoming 2355 * packets, and do not reject packets w/ bad checksums. 2356 */ 2357 reg = 0; 2358 if (capenable & 2359 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2360 reg |= VRCR_IPEN; 2361 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2362 reg |= VRCR_VTDEN|VRCR_VTREN; 2363 bus_space_write_4(st, sh, SIP_VRCR, reg); 2364 2365 /* 2366 * Initialize the VLAN/IP transmit control register. 2367 * We enable outgoing checksum computation on a 2368 * per-packet basis. 2369 */ 2370 reg = 0; 2371 if (capenable & 2372 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2373 reg |= VTCR_PPCHK; 2374 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2375 reg |= VTCR_VPPTI; 2376 bus_space_write_4(st, sh, SIP_VTCR, reg); 2377 2378 /* 2379 * If we're using VLANs, initialize the VLAN data register. 2380 * To understand why we bswap the VLAN Ethertype, see section 2381 * 4.2.36 of the DP83820 manual. 2382 */ 2383 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2384 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2385 } 2386 2387 /* 2388 * sip_init: [ ifnet interface function ] 2389 * 2390 * Initialize the interface. Must be called at splnet(). 2391 */ 2392 static int 2393 sipcom_init(struct ifnet *ifp) 2394 { 2395 struct sip_softc *sc = ifp->if_softc; 2396 bus_space_tag_t st = sc->sc_st; 2397 bus_space_handle_t sh = sc->sc_sh; 2398 struct sip_txsoft *txs; 2399 struct sip_rxsoft *rxs; 2400 struct sip_desc *sipd; 2401 int i, error = 0; 2402 2403 if (sc->sc_suspended) 2404 return EBUSY; 2405 2406 /* 2407 * Cancel any pending I/O. 2408 */ 2409 sipcom_stop(ifp, 0); 2410 2411 /* 2412 * Reset the chip to a known state. 2413 */ 2414 if (!sipcom_reset(sc)) 2415 return EBUSY; 2416 2417 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2418 /* 2419 * DP83815 manual, page 78: 2420 * 4.4 Recommended Registers Configuration 2421 * For optimum performance of the DP83815, version noted 2422 * as DP83815CVNG (SRR = 203h), the listed register 2423 * modifications must be followed in sequence... 2424 * 2425 * It's not clear if this should be 302h or 203h because that 2426 * chip name is listed as SRR 302h in the description of the 2427 * SRR register. However, my revision 302h DP83815 on the 2428 * Netgear FA311 purchased in 02/2001 needs these settings 2429 * to avoid tons of errors in AcceptPerfectMatch (non- 2430 * IFF_PROMISC) mode. I do not know if other revisions need 2431 * this set or not. [briggs -- 09 March 2001] 2432 * 2433 * Note that only the low-order 12 bits of 0xe4 are documented 2434 * and that this sets reserved bits in that register. 2435 */ 2436 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2437 2438 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2439 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2440 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2441 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2442 2443 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2444 } 2445 2446 /* 2447 * Initialize the transmit descriptor ring. 2448 */ 2449 for (i = 0; i < sc->sc_ntxdesc; i++) { 2450 sipd = &sc->sc_txdescs[i]; 2451 memset(sipd, 0, sizeof(struct sip_desc)); 2452 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2453 } 2454 SIP_CDTXSYNC(sc, 0, sc->sc_ntxdesc, 2455 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2456 sc->sc_txfree = sc->sc_ntxdesc; 2457 sc->sc_txnext = 0; 2458 sc->sc_txwin = 0; 2459 2460 /* 2461 * Initialize the transmit job descriptors. 2462 */ 2463 SIMPLEQ_INIT(&sc->sc_txfreeq); 2464 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2465 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2466 txs = &sc->sc_txsoft[i]; 2467 txs->txs_mbuf = NULL; 2468 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2469 } 2470 2471 /* 2472 * Initialize the receive descriptor and receive job 2473 * descriptor rings. 2474 */ 2475 for (i = 0; i < sc->sc_nrxdesc; i++) { 2476 rxs = &sc->sc_rxsoft[i]; 2477 if (rxs->rxs_mbuf == NULL) { 2478 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2479 printf("%s: unable to allocate or map rx " 2480 "buffer %d, error = %d\n", 2481 sc->sc_dev.dv_xname, i, error); 2482 /* 2483 * XXX Should attempt to run with fewer receive 2484 * XXX buffers instead of just failing. 2485 */ 2486 sipcom_rxdrain(sc); 2487 goto out; 2488 } 2489 } else 2490 SIP_INIT_RXDESC(sc, i); 2491 } 2492 sc->sc_rxptr = 0; 2493 sc->sc_rxdiscard = 0; 2494 SIP_RXCHAIN_RESET(sc); 2495 2496 /* 2497 * Set the configuration register; it's already initialized 2498 * in sip_attach(). 2499 */ 2500 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2501 2502 /* 2503 * Initialize the prototype TXCFG register. 2504 */ 2505 if (sc->sc_gigabit) { 2506 sc->sc_txcfg = TXCFG_MXDMA_512; 2507 sc->sc_rxcfg = RXCFG_MXDMA_512; 2508 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2509 SIP_SIS900_REV(sc, SIS_REV_960) || 2510 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2511 (sc->sc_cfg & CFG_EDBMASTEN)) { 2512 sc->sc_txcfg = TXCFG_MXDMA_64; 2513 sc->sc_rxcfg = RXCFG_MXDMA_64; 2514 } else { 2515 sc->sc_txcfg = TXCFG_MXDMA_512; 2516 sc->sc_rxcfg = RXCFG_MXDMA_512; 2517 } 2518 2519 sc->sc_txcfg |= TXCFG_ATP | 2520 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2521 sc->sc_tx_drain_thresh; 2522 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2523 2524 /* 2525 * Initialize the receive drain threshold if we have never 2526 * done so. 2527 */ 2528 if (sc->sc_rx_drain_thresh == 0) { 2529 /* 2530 * XXX This value should be tuned. This is set to the 2531 * maximum of 248 bytes, and we may be able to improve 2532 * performance by decreasing it (although we should never 2533 * set this value lower than 2; 14 bytes are required to 2534 * filter the packet). 2535 */ 2536 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2537 } 2538 2539 /* 2540 * Initialize the prototype RXCFG register. 2541 */ 2542 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2543 /* 2544 * Accept long packets (including FCS) so we can handle 2545 * 802.1q-tagged frames and jumbo frames properly. 2546 */ 2547 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2548 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2549 sc->sc_rxcfg |= RXCFG_ALP; 2550 2551 /* 2552 * Checksum offloading is disabled if the user selects an MTU 2553 * larger than 8109. (FreeBSD says 8152, but there is emperical 2554 * evidence that >8109 does not work on some boards, such as the 2555 * Planex GN-1000TE). 2556 */ 2557 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2558 (ifp->if_capenable & 2559 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2560 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2561 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2562 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2563 "disabled.\n", sc->sc_dev.dv_xname); 2564 ifp->if_capenable &= 2565 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2566 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2567 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2568 ifp->if_csum_flags_tx = 0; 2569 ifp->if_csum_flags_rx = 0; 2570 } 2571 2572 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2573 2574 if (sc->sc_gigabit) 2575 sipcom_dp83820_init(sc, ifp->if_capenable); 2576 2577 /* 2578 * Give the transmit and receive rings to the chip. 2579 */ 2580 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2581 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2582 2583 /* 2584 * Initialize the interrupt mask. 2585 */ 2586 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2587 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2588 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2589 2590 /* Set up the receive filter. */ 2591 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2592 2593 /* 2594 * Tune sc_rx_flow_thresh. 2595 * XXX "More than 8KB" is too short for jumbo frames. 2596 * XXX TODO: Threshold value should be user-settable. 2597 */ 2598 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2599 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2600 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2601 2602 /* 2603 * Set the current media. Do this after initializing the prototype 2604 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2605 * control. 2606 */ 2607 mii_mediachg(&sc->sc_mii); 2608 2609 /* 2610 * Set the interrupt hold-off timer to 100us. 2611 */ 2612 if (sc->sc_gigabit) 2613 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2614 2615 /* 2616 * Enable interrupts. 2617 */ 2618 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2619 2620 /* 2621 * Start the transmit and receive processes. 2622 */ 2623 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2624 2625 /* 2626 * Start the one second MII clock. 2627 */ 2628 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2629 2630 /* 2631 * ...all done! 2632 */ 2633 ifp->if_flags |= IFF_RUNNING; 2634 ifp->if_flags &= ~IFF_OACTIVE; 2635 sc->sc_if_flags = ifp->if_flags; 2636 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2637 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2638 sc->sc_prev.if_capenable = ifp->if_capenable; 2639 2640 out: 2641 if (error) 2642 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2643 return (error); 2644 } 2645 2646 /* 2647 * sip_drain: 2648 * 2649 * Drain the receive queue. 2650 */ 2651 static void 2652 sipcom_rxdrain(struct sip_softc *sc) 2653 { 2654 struct sip_rxsoft *rxs; 2655 int i; 2656 2657 for (i = 0; i < sc->sc_nrxdesc; i++) { 2658 rxs = &sc->sc_rxsoft[i]; 2659 if (rxs->rxs_mbuf != NULL) { 2660 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2661 m_freem(rxs->rxs_mbuf); 2662 rxs->rxs_mbuf = NULL; 2663 } 2664 } 2665 } 2666 2667 /* 2668 * sip_stop: [ ifnet interface function ] 2669 * 2670 * Stop transmission on the interface. 2671 */ 2672 static void 2673 sipcom_stop(struct ifnet *ifp, int disable) 2674 { 2675 struct sip_softc *sc = ifp->if_softc; 2676 bus_space_tag_t st = sc->sc_st; 2677 bus_space_handle_t sh = sc->sc_sh; 2678 struct sip_txsoft *txs; 2679 u_int32_t cmdsts = 0; /* DEBUG */ 2680 2681 /* 2682 * Stop the one second clock. 2683 */ 2684 callout_stop(&sc->sc_tick_ch); 2685 2686 /* Down the MII. */ 2687 mii_down(&sc->sc_mii); 2688 2689 /* 2690 * Disable interrupts. 2691 */ 2692 bus_space_write_4(st, sh, SIP_IER, 0); 2693 2694 /* 2695 * Stop receiver and transmitter. 2696 */ 2697 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2698 2699 /* 2700 * Release any queued transmit buffers. 2701 */ 2702 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2703 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2704 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2705 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2706 CMDSTS_INTR) == 0) 2707 printf("%s: sip_stop: last descriptor does not " 2708 "have INTR bit set\n", sc->sc_dev.dv_xname); 2709 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2710 #ifdef DIAGNOSTIC 2711 if (txs->txs_mbuf == NULL) { 2712 printf("%s: dirty txsoft with no mbuf chain\n", 2713 sc->sc_dev.dv_xname); 2714 panic("sip_stop"); 2715 } 2716 #endif 2717 cmdsts |= /* DEBUG */ 2718 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2719 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2720 m_freem(txs->txs_mbuf); 2721 txs->txs_mbuf = NULL; 2722 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2723 } 2724 2725 if (disable) 2726 sipcom_rxdrain(sc); 2727 2728 /* 2729 * Mark the interface down and cancel the watchdog timer. 2730 */ 2731 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2732 ifp->if_timer = 0; 2733 2734 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2735 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2736 printf("%s: sip_stop: no INTR bits set in dirty tx " 2737 "descriptors\n", sc->sc_dev.dv_xname); 2738 } 2739 2740 /* 2741 * sip_read_eeprom: 2742 * 2743 * Read data from the serial EEPROM. 2744 */ 2745 static void 2746 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2747 u_int16_t *data) 2748 { 2749 bus_space_tag_t st = sc->sc_st; 2750 bus_space_handle_t sh = sc->sc_sh; 2751 u_int16_t reg; 2752 int i, x; 2753 2754 for (i = 0; i < wordcnt; i++) { 2755 /* Send CHIP SELECT. */ 2756 reg = EROMAR_EECS; 2757 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2758 2759 /* Shift in the READ opcode. */ 2760 for (x = 3; x > 0; x--) { 2761 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2762 reg |= EROMAR_EEDI; 2763 else 2764 reg &= ~EROMAR_EEDI; 2765 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2766 bus_space_write_4(st, sh, SIP_EROMAR, 2767 reg | EROMAR_EESK); 2768 delay(4); 2769 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2770 delay(4); 2771 } 2772 2773 /* Shift in address. */ 2774 for (x = 6; x > 0; x--) { 2775 if ((word + i) & (1 << (x - 1))) 2776 reg |= EROMAR_EEDI; 2777 else 2778 reg &= ~EROMAR_EEDI; 2779 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2780 bus_space_write_4(st, sh, SIP_EROMAR, 2781 reg | EROMAR_EESK); 2782 delay(4); 2783 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2784 delay(4); 2785 } 2786 2787 /* Shift out data. */ 2788 reg = EROMAR_EECS; 2789 data[i] = 0; 2790 for (x = 16; x > 0; x--) { 2791 bus_space_write_4(st, sh, SIP_EROMAR, 2792 reg | EROMAR_EESK); 2793 delay(4); 2794 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2795 data[i] |= (1 << (x - 1)); 2796 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2797 delay(4); 2798 } 2799 2800 /* Clear CHIP SELECT. */ 2801 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2802 delay(4); 2803 } 2804 } 2805 2806 /* 2807 * sip_add_rxbuf: 2808 * 2809 * Add a receive buffer to the indicated descriptor. 2810 */ 2811 static int 2812 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2813 { 2814 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2815 struct mbuf *m; 2816 int error; 2817 2818 MGETHDR(m, M_DONTWAIT, MT_DATA); 2819 if (m == NULL) 2820 return (ENOBUFS); 2821 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2822 2823 MCLGET(m, M_DONTWAIT); 2824 if ((m->m_flags & M_EXT) == 0) { 2825 m_freem(m); 2826 return (ENOBUFS); 2827 } 2828 2829 /* XXX I don't believe this is necessary. --dyoung */ 2830 #if 0 || defined(DP83820) 2831 m->m_len = sc->sc_rxbuf_len; 2832 #endif /* DP83820 */ 2833 2834 if (rxs->rxs_mbuf != NULL) 2835 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2836 2837 rxs->rxs_mbuf = m; 2838 2839 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2840 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2841 BUS_DMA_READ|BUS_DMA_NOWAIT); 2842 if (error) { 2843 printf("%s: can't load rx DMA map %d, error = %d\n", 2844 sc->sc_dev.dv_xname, idx, error); 2845 panic("%s", __func__); /* XXX */ 2846 } 2847 2848 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2849 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2850 2851 SIP_INIT_RXDESC(sc, idx); 2852 2853 return (0); 2854 } 2855 2856 /* 2857 * sip_sis900_set_filter: 2858 * 2859 * Set up the receive filter. 2860 */ 2861 static void 2862 sipcom_sis900_set_filter(struct sip_softc *sc) 2863 { 2864 bus_space_tag_t st = sc->sc_st; 2865 bus_space_handle_t sh = sc->sc_sh; 2866 struct ethercom *ec = &sc->sc_ethercom; 2867 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2868 struct ether_multi *enm; 2869 const u_int8_t *cp; 2870 struct ether_multistep step; 2871 u_int32_t crc, mchash[16]; 2872 2873 /* 2874 * Initialize the prototype RFCR. 2875 */ 2876 sc->sc_rfcr = RFCR_RFEN; 2877 if (ifp->if_flags & IFF_BROADCAST) 2878 sc->sc_rfcr |= RFCR_AAB; 2879 if (ifp->if_flags & IFF_PROMISC) { 2880 sc->sc_rfcr |= RFCR_AAP; 2881 goto allmulti; 2882 } 2883 2884 /* 2885 * Set up the multicast address filter by passing all multicast 2886 * addresses through a CRC generator, and then using the high-order 2887 * 6 bits as an index into the 128 bit multicast hash table (only 2888 * the lower 16 bits of each 32 bit multicast hash register are 2889 * valid). The high order bits select the register, while the 2890 * rest of the bits select the bit within the register. 2891 */ 2892 2893 memset(mchash, 0, sizeof(mchash)); 2894 2895 /* 2896 * SiS900 (at least SiS963) requires us to register the address of 2897 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2898 */ 2899 crc = 0x0ed423f9; 2900 2901 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2902 SIP_SIS900_REV(sc, SIS_REV_960) || 2903 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2904 /* Just want the 8 most significant bits. */ 2905 crc >>= 24; 2906 } else { 2907 /* Just want the 7 most significant bits. */ 2908 crc >>= 25; 2909 } 2910 2911 /* Set the corresponding bit in the hash table. */ 2912 mchash[crc >> 4] |= 1 << (crc & 0xf); 2913 2914 ETHER_FIRST_MULTI(step, ec, enm); 2915 while (enm != NULL) { 2916 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2917 /* 2918 * We must listen to a range of multicast addresses. 2919 * For now, just accept all multicasts, rather than 2920 * trying to set only those filter bits needed to match 2921 * the range. (At this time, the only use of address 2922 * ranges is for IP multicast routing, for which the 2923 * range is big enough to require all bits set.) 2924 */ 2925 goto allmulti; 2926 } 2927 2928 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2929 2930 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2931 SIP_SIS900_REV(sc, SIS_REV_960) || 2932 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2933 /* Just want the 8 most significant bits. */ 2934 crc >>= 24; 2935 } else { 2936 /* Just want the 7 most significant bits. */ 2937 crc >>= 25; 2938 } 2939 2940 /* Set the corresponding bit in the hash table. */ 2941 mchash[crc >> 4] |= 1 << (crc & 0xf); 2942 2943 ETHER_NEXT_MULTI(step, enm); 2944 } 2945 2946 ifp->if_flags &= ~IFF_ALLMULTI; 2947 goto setit; 2948 2949 allmulti: 2950 ifp->if_flags |= IFF_ALLMULTI; 2951 sc->sc_rfcr |= RFCR_AAM; 2952 2953 setit: 2954 #define FILTER_EMIT(addr, data) \ 2955 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2956 delay(1); \ 2957 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2958 delay(1) 2959 2960 /* 2961 * Disable receive filter, and program the node address. 2962 */ 2963 cp = CLLADDR(ifp->if_sadl); 2964 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2965 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2966 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2967 2968 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2969 /* 2970 * Program the multicast hash table. 2971 */ 2972 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2973 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2974 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2975 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2976 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2977 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2978 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2979 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2980 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2981 SIP_SIS900_REV(sc, SIS_REV_960) || 2982 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2983 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2984 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2985 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2986 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2987 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2988 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2989 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2990 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2991 } 2992 } 2993 #undef FILTER_EMIT 2994 2995 /* 2996 * Re-enable the receiver filter. 2997 */ 2998 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2999 } 3000 3001 /* 3002 * sip_dp83815_set_filter: 3003 * 3004 * Set up the receive filter. 3005 */ 3006 static void 3007 sipcom_dp83815_set_filter(struct sip_softc *sc) 3008 { 3009 bus_space_tag_t st = sc->sc_st; 3010 bus_space_handle_t sh = sc->sc_sh; 3011 struct ethercom *ec = &sc->sc_ethercom; 3012 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3013 struct ether_multi *enm; 3014 const u_int8_t *cp; 3015 struct ether_multistep step; 3016 u_int32_t crc, hash, slot, bit; 3017 #define MCHASH_NWORDS_83820 128 3018 #define MCHASH_NWORDS_83815 32 3019 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3020 u_int16_t mchash[MCHASH_NWORDS]; 3021 int i; 3022 3023 /* 3024 * Initialize the prototype RFCR. 3025 * Enable the receive filter, and accept on 3026 * Perfect (destination address) Match 3027 * If IFF_BROADCAST, also accept all broadcast packets. 3028 * If IFF_PROMISC, accept all unicast packets (and later, set 3029 * IFF_ALLMULTI and accept all multicast, too). 3030 */ 3031 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3032 if (ifp->if_flags & IFF_BROADCAST) 3033 sc->sc_rfcr |= RFCR_AAB; 3034 if (ifp->if_flags & IFF_PROMISC) { 3035 sc->sc_rfcr |= RFCR_AAP; 3036 goto allmulti; 3037 } 3038 3039 /* 3040 * Set up the DP83820/DP83815 multicast address filter by 3041 * passing all multicast addresses through a CRC generator, 3042 * and then using the high-order 11/9 bits as an index into 3043 * the 2048/512 bit multicast hash table. The high-order 3044 * 7/5 bits select the slot, while the low-order 4 bits 3045 * select the bit within the slot. Note that only the low 3046 * 16-bits of each filter word are used, and there are 3047 * 128/32 filter words. 3048 */ 3049 3050 memset(mchash, 0, sizeof(mchash)); 3051 3052 ifp->if_flags &= ~IFF_ALLMULTI; 3053 ETHER_FIRST_MULTI(step, ec, enm); 3054 if (enm == NULL) 3055 goto setit; 3056 while (enm != NULL) { 3057 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3058 /* 3059 * We must listen to a range of multicast addresses. 3060 * For now, just accept all multicasts, rather than 3061 * trying to set only those filter bits needed to match 3062 * the range. (At this time, the only use of address 3063 * ranges is for IP multicast routing, for which the 3064 * range is big enough to require all bits set.) 3065 */ 3066 goto allmulti; 3067 } 3068 3069 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3070 3071 if (sc->sc_gigabit) { 3072 /* Just want the 11 most significant bits. */ 3073 hash = crc >> 21; 3074 } else { 3075 /* Just want the 9 most significant bits. */ 3076 hash = crc >> 23; 3077 } 3078 3079 slot = hash >> 4; 3080 bit = hash & 0xf; 3081 3082 /* Set the corresponding bit in the hash table. */ 3083 mchash[slot] |= 1 << bit; 3084 3085 ETHER_NEXT_MULTI(step, enm); 3086 } 3087 sc->sc_rfcr |= RFCR_MHEN; 3088 goto setit; 3089 3090 allmulti: 3091 ifp->if_flags |= IFF_ALLMULTI; 3092 sc->sc_rfcr |= RFCR_AAM; 3093 3094 setit: 3095 #define FILTER_EMIT(addr, data) \ 3096 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3097 delay(1); \ 3098 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3099 delay(1) 3100 3101 /* 3102 * Disable receive filter, and program the node address. 3103 */ 3104 cp = CLLADDR(ifp->if_sadl); 3105 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3106 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3107 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3108 3109 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3110 int nwords = 3111 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3112 /* 3113 * Program the multicast hash table. 3114 */ 3115 for (i = 0; i < nwords; i++) { 3116 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3117 mchash[i]); 3118 } 3119 } 3120 #undef FILTER_EMIT 3121 #undef MCHASH_NWORDS 3122 #undef MCHASH_NWORDS_83815 3123 #undef MCHASH_NWORDS_83820 3124 3125 /* 3126 * Re-enable the receiver filter. 3127 */ 3128 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3129 } 3130 3131 /* 3132 * sip_dp83820_mii_readreg: [mii interface function] 3133 * 3134 * Read a PHY register on the MII of the DP83820. 3135 */ 3136 static int 3137 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3138 { 3139 struct sip_softc *sc = (void *) self; 3140 3141 if (sc->sc_cfg & CFG_TBI_EN) { 3142 bus_addr_t tbireg; 3143 int rv; 3144 3145 if (phy != 0) 3146 return (0); 3147 3148 switch (reg) { 3149 case MII_BMCR: tbireg = SIP_TBICR; break; 3150 case MII_BMSR: tbireg = SIP_TBISR; break; 3151 case MII_ANAR: tbireg = SIP_TANAR; break; 3152 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3153 case MII_ANER: tbireg = SIP_TANER; break; 3154 case MII_EXTSR: 3155 /* 3156 * Don't even bother reading the TESR register. 3157 * The manual documents that the device has 3158 * 1000baseX full/half capability, but the 3159 * register itself seems read back 0 on some 3160 * boards. Just hard-code the result. 3161 */ 3162 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3163 3164 default: 3165 return (0); 3166 } 3167 3168 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3169 if (tbireg == SIP_TBISR) { 3170 /* LINK and ACOMP are switched! */ 3171 int val = rv; 3172 3173 rv = 0; 3174 if (val & TBISR_MR_LINK_STATUS) 3175 rv |= BMSR_LINK; 3176 if (val & TBISR_MR_AN_COMPLETE) 3177 rv |= BMSR_ACOMP; 3178 3179 /* 3180 * The manual claims this register reads back 0 3181 * on hard and soft reset. But we want to let 3182 * the gentbi driver know that we support auto- 3183 * negotiation, so hard-code this bit in the 3184 * result. 3185 */ 3186 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3187 } 3188 3189 return (rv); 3190 } 3191 3192 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3193 } 3194 3195 /* 3196 * sip_dp83820_mii_writereg: [mii interface function] 3197 * 3198 * Write a PHY register on the MII of the DP83820. 3199 */ 3200 static void 3201 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3202 { 3203 struct sip_softc *sc = (void *) self; 3204 3205 if (sc->sc_cfg & CFG_TBI_EN) { 3206 bus_addr_t tbireg; 3207 3208 if (phy != 0) 3209 return; 3210 3211 switch (reg) { 3212 case MII_BMCR: tbireg = SIP_TBICR; break; 3213 case MII_ANAR: tbireg = SIP_TANAR; break; 3214 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3215 default: 3216 return; 3217 } 3218 3219 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3220 return; 3221 } 3222 3223 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3224 } 3225 3226 /* 3227 * sip_dp83820_mii_statchg: [mii interface function] 3228 * 3229 * Callback from MII layer when media changes. 3230 */ 3231 static void 3232 sipcom_dp83820_mii_statchg(struct device *self) 3233 { 3234 struct sip_softc *sc = (struct sip_softc *) self; 3235 struct mii_data *mii = &sc->sc_mii; 3236 u_int32_t cfg, pcr; 3237 3238 /* 3239 * Get flow control negotiation result. 3240 */ 3241 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3242 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3243 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3244 mii->mii_media_active &= ~IFM_ETH_FMASK; 3245 } 3246 3247 /* 3248 * Update TXCFG for full-duplex operation. 3249 */ 3250 if ((mii->mii_media_active & IFM_FDX) != 0) 3251 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3252 else 3253 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3254 3255 /* 3256 * Update RXCFG for full-duplex or loopback. 3257 */ 3258 if ((mii->mii_media_active & IFM_FDX) != 0 || 3259 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3260 sc->sc_rxcfg |= RXCFG_ATX; 3261 else 3262 sc->sc_rxcfg &= ~RXCFG_ATX; 3263 3264 /* 3265 * Update CFG for MII/GMII. 3266 */ 3267 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3268 cfg = sc->sc_cfg | CFG_MODE_1000; 3269 else 3270 cfg = sc->sc_cfg; 3271 3272 /* 3273 * 802.3x flow control. 3274 */ 3275 pcr = 0; 3276 if (sc->sc_flowflags & IFM_FLOW) { 3277 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3278 pcr |= sc->sc_rx_flow_thresh; 3279 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3280 pcr |= PCR_PSEN | PCR_PS_MCAST; 3281 } 3282 3283 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3284 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3285 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3286 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3287 } 3288 3289 /* 3290 * sip_mii_bitbang_read: [mii bit-bang interface function] 3291 * 3292 * Read the MII serial port for the MII bit-bang module. 3293 */ 3294 static u_int32_t 3295 sipcom_mii_bitbang_read(struct device *self) 3296 { 3297 struct sip_softc *sc = (void *) self; 3298 3299 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3300 } 3301 3302 /* 3303 * sip_mii_bitbang_write: [mii big-bang interface function] 3304 * 3305 * Write the MII serial port for the MII bit-bang module. 3306 */ 3307 static void 3308 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3309 { 3310 struct sip_softc *sc = (void *) self; 3311 3312 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3313 } 3314 3315 /* 3316 * sip_sis900_mii_readreg: [mii interface function] 3317 * 3318 * Read a PHY register on the MII. 3319 */ 3320 static int 3321 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3322 { 3323 struct sip_softc *sc = (struct sip_softc *) self; 3324 u_int32_t enphy; 3325 3326 /* 3327 * The PHY of recent SiS chipsets is accessed through bitbang 3328 * operations. 3329 */ 3330 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3331 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3332 phy, reg); 3333 3334 #ifndef SIS900_MII_RESTRICT 3335 /* 3336 * The SiS 900 has only an internal PHY on the MII. Only allow 3337 * MII address 0. 3338 */ 3339 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3340 return (0); 3341 #endif 3342 3343 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3344 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3345 ENPHY_RWCMD | ENPHY_ACCESS); 3346 do { 3347 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3348 } while (enphy & ENPHY_ACCESS); 3349 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3350 } 3351 3352 /* 3353 * sip_sis900_mii_writereg: [mii interface function] 3354 * 3355 * Write a PHY register on the MII. 3356 */ 3357 static void 3358 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3359 { 3360 struct sip_softc *sc = (struct sip_softc *) self; 3361 u_int32_t enphy; 3362 3363 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3364 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3365 phy, reg, val); 3366 return; 3367 } 3368 3369 #ifndef SIS900_MII_RESTRICT 3370 /* 3371 * The SiS 900 has only an internal PHY on the MII. Only allow 3372 * MII address 0. 3373 */ 3374 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3375 return; 3376 #endif 3377 3378 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3379 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3380 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3381 do { 3382 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3383 } while (enphy & ENPHY_ACCESS); 3384 } 3385 3386 /* 3387 * sip_sis900_mii_statchg: [mii interface function] 3388 * 3389 * Callback from MII layer when media changes. 3390 */ 3391 static void 3392 sipcom_sis900_mii_statchg(struct device *self) 3393 { 3394 struct sip_softc *sc = (struct sip_softc *) self; 3395 struct mii_data *mii = &sc->sc_mii; 3396 u_int32_t flowctl; 3397 3398 /* 3399 * Get flow control negotiation result. 3400 */ 3401 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3402 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3403 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3404 mii->mii_media_active &= ~IFM_ETH_FMASK; 3405 } 3406 3407 /* 3408 * Update TXCFG for full-duplex operation. 3409 */ 3410 if ((mii->mii_media_active & IFM_FDX) != 0) 3411 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3412 else 3413 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3414 3415 /* 3416 * Update RXCFG for full-duplex or loopback. 3417 */ 3418 if ((mii->mii_media_active & IFM_FDX) != 0 || 3419 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3420 sc->sc_rxcfg |= RXCFG_ATX; 3421 else 3422 sc->sc_rxcfg &= ~RXCFG_ATX; 3423 3424 /* 3425 * Update IMR for use of 802.3x flow control. 3426 */ 3427 if (sc->sc_flowflags & IFM_FLOW) { 3428 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3429 flowctl = FLOWCTL_FLOWEN; 3430 } else { 3431 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3432 flowctl = 0; 3433 } 3434 3435 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3436 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3437 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3438 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3439 } 3440 3441 /* 3442 * sip_dp83815_mii_readreg: [mii interface function] 3443 * 3444 * Read a PHY register on the MII. 3445 */ 3446 static int 3447 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3448 { 3449 struct sip_softc *sc = (struct sip_softc *) self; 3450 u_int32_t val; 3451 3452 /* 3453 * The DP83815 only has an internal PHY. Only allow 3454 * MII address 0. 3455 */ 3456 if (phy != 0) 3457 return (0); 3458 3459 /* 3460 * Apparently, after a reset, the DP83815 can take a while 3461 * to respond. During this recovery period, the BMSR returns 3462 * a value of 0. Catch this -- it's not supposed to happen 3463 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3464 * PHY to come back to life. 3465 * 3466 * This works out because the BMSR is the first register 3467 * read during the PHY probe process. 3468 */ 3469 do { 3470 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3471 } while (reg == MII_BMSR && val == 0); 3472 3473 return (val & 0xffff); 3474 } 3475 3476 /* 3477 * sip_dp83815_mii_writereg: [mii interface function] 3478 * 3479 * Write a PHY register to the MII. 3480 */ 3481 static void 3482 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3483 { 3484 struct sip_softc *sc = (struct sip_softc *) self; 3485 3486 /* 3487 * The DP83815 only has an internal PHY. Only allow 3488 * MII address 0. 3489 */ 3490 if (phy != 0) 3491 return; 3492 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3494 } 3495 3496 /* 3497 * sip_dp83815_mii_statchg: [mii interface function] 3498 * 3499 * Callback from MII layer when media changes. 3500 */ 3501 static void 3502 sipcom_dp83815_mii_statchg(struct device *self) 3503 { 3504 struct sip_softc *sc = (struct sip_softc *) self; 3505 3506 /* 3507 * Update TXCFG for full-duplex operation. 3508 */ 3509 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3510 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3511 else 3512 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3513 3514 /* 3515 * Update RXCFG for full-duplex or loopback. 3516 */ 3517 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3518 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3519 sc->sc_rxcfg |= RXCFG_ATX; 3520 else 3521 sc->sc_rxcfg &= ~RXCFG_ATX; 3522 3523 /* 3524 * XXX 802.3x flow control. 3525 */ 3526 3527 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3528 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3529 3530 /* 3531 * Some DP83815s experience problems when used with short 3532 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3533 * sequence adjusts the DSP's signal attenuation to fix the 3534 * problem. 3535 */ 3536 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3537 uint32_t reg; 3538 3539 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3540 3541 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3542 reg &= 0x0fff; 3543 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3544 delay(100); 3545 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3546 reg &= 0x00ff; 3547 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3548 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3549 0x00e8); 3550 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3551 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3552 reg | 0x20); 3553 } 3554 3555 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3556 } 3557 } 3558 3559 static void 3560 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3561 const struct pci_attach_args *pa, u_int8_t *enaddr) 3562 { 3563 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3564 u_int8_t cksum, *e, match; 3565 int i; 3566 3567 /* 3568 * EEPROM data format for the DP83820 can be found in 3569 * the DP83820 manual, section 4.2.4. 3570 */ 3571 3572 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3573 3574 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3575 match = ~(match - 1); 3576 3577 cksum = 0x55; 3578 e = (u_int8_t *) eeprom_data; 3579 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3580 cksum += *e++; 3581 3582 if (cksum != match) 3583 printf("%s: Checksum (%x) mismatch (%x)", 3584 sc->sc_dev.dv_xname, cksum, match); 3585 3586 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3587 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3588 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3589 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3590 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3591 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3592 } 3593 3594 static void 3595 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3596 { 3597 int i; 3598 3599 /* 3600 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3601 * a reason, but I don't know it. 3602 */ 3603 for (i = 0; i < 10; i++) 3604 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3605 } 3606 3607 static void 3608 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3609 const struct pci_attach_args *pa, u_int8_t *enaddr) 3610 { 3611 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3612 3613 switch (sc->sc_rev) { 3614 case SIS_REV_630S: 3615 case SIS_REV_630E: 3616 case SIS_REV_630EA1: 3617 case SIS_REV_630ET: 3618 case SIS_REV_635: 3619 /* 3620 * The MAC address for the on-board Ethernet of 3621 * the SiS 630 chipset is in the NVRAM. Kick 3622 * the chip into re-loading it from NVRAM, and 3623 * read the MAC address out of the filter registers. 3624 */ 3625 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3626 3627 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3628 RFCR_RFADDR_NODE0); 3629 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3630 0xffff; 3631 3632 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3633 RFCR_RFADDR_NODE2); 3634 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3635 0xffff; 3636 3637 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3638 RFCR_RFADDR_NODE4); 3639 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3640 0xffff; 3641 break; 3642 3643 case SIS_REV_960: 3644 { 3645 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3646 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3647 3648 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3649 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3650 3651 int waittime, i; 3652 3653 /* Allow to read EEPROM from LAN. It is shared 3654 * between a 1394 controller and the NIC and each 3655 * time we access it, we need to set SIS_EECMD_REQ. 3656 */ 3657 SIS_SET_EROMAR(sc, EROMAR_REQ); 3658 3659 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3660 /* Force EEPROM to idle state. */ 3661 3662 /* 3663 * XXX-cube This is ugly. I'll look for docs about it. 3664 */ 3665 SIS_SET_EROMAR(sc, EROMAR_EECS); 3666 sipcom_sis900_eeprom_delay(sc); 3667 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3668 SIS_SET_EROMAR(sc, EROMAR_EESK); 3669 sipcom_sis900_eeprom_delay(sc); 3670 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3671 sipcom_sis900_eeprom_delay(sc); 3672 } 3673 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3674 sipcom_sis900_eeprom_delay(sc); 3675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3676 3677 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3678 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3679 sizeof(myea) / sizeof(myea[0]), myea); 3680 break; 3681 } 3682 DELAY(1); 3683 } 3684 3685 /* 3686 * Set SIS_EECTL_CLK to high, so a other master 3687 * can operate on the i2c bus. 3688 */ 3689 SIS_SET_EROMAR(sc, EROMAR_EESK); 3690 3691 /* Refuse EEPROM access by LAN */ 3692 SIS_SET_EROMAR(sc, EROMAR_DONE); 3693 } break; 3694 3695 default: 3696 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3697 sizeof(myea) / sizeof(myea[0]), myea); 3698 } 3699 3700 enaddr[0] = myea[0] & 0xff; 3701 enaddr[1] = myea[0] >> 8; 3702 enaddr[2] = myea[1] & 0xff; 3703 enaddr[3] = myea[1] >> 8; 3704 enaddr[4] = myea[2] & 0xff; 3705 enaddr[5] = myea[2] >> 8; 3706 } 3707 3708 /* Table and macro to bit-reverse an octet. */ 3709 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3710 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3711 3712 static void 3713 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3714 const struct pci_attach_args *pa, u_int8_t *enaddr) 3715 { 3716 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3717 u_int8_t cksum, *e, match; 3718 int i; 3719 3720 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3721 sizeof(eeprom_data[0]), eeprom_data); 3722 3723 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3724 match = ~(match - 1); 3725 3726 cksum = 0x55; 3727 e = (u_int8_t *) eeprom_data; 3728 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3729 cksum += *e++; 3730 } 3731 if (cksum != match) { 3732 printf("%s: Checksum (%x) mismatch (%x)", 3733 sc->sc_dev.dv_xname, cksum, match); 3734 } 3735 3736 /* 3737 * Unrolled because it makes slightly more sense this way. 3738 * The DP83815 stores the MAC address in bit 0 of word 6 3739 * through bit 15 of word 8. 3740 */ 3741 ea = &eeprom_data[6]; 3742 enaddr[0] = ((*ea & 0x1) << 7); 3743 ea++; 3744 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3745 enaddr[1] = ((*ea & 0x1FE) >> 1); 3746 enaddr[2] = ((*ea & 0x1) << 7); 3747 ea++; 3748 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3749 enaddr[3] = ((*ea & 0x1FE) >> 1); 3750 enaddr[4] = ((*ea & 0x1) << 7); 3751 ea++; 3752 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3753 enaddr[5] = ((*ea & 0x1FE) >> 1); 3754 3755 /* 3756 * In case that's not weird enough, we also need to reverse 3757 * the bits in each byte. This all actually makes more sense 3758 * if you think about the EEPROM storage as an array of bits 3759 * being shifted into bytes, but that's not how we're looking 3760 * at it here... 3761 */ 3762 for (i = 0; i < 6 ;i++) 3763 enaddr[i] = bbr(enaddr[i]); 3764 } 3765 3766 /* 3767 * sip_mediastatus: [ifmedia interface function] 3768 * 3769 * Get the current interface media status. 3770 */ 3771 static void 3772 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3773 { 3774 struct sip_softc *sc = ifp->if_softc; 3775 3776 mii_pollstat(&sc->sc_mii); 3777 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3778 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3779 sc->sc_flowflags; 3780 } 3781 3782 /* 3783 * sip_mediachange: [ifmedia interface function] 3784 * 3785 * Set hardware to newly-selected media. 3786 */ 3787 static int 3788 sipcom_mediachange(struct ifnet *ifp) 3789 { 3790 struct sip_softc *sc = ifp->if_softc; 3791 3792 if (ifp->if_flags & IFF_UP) 3793 mii_mediachg(&sc->sc_mii); 3794 return (0); 3795 } 3796
Indexes created Tue Sep 30 11:09:46 GMT 2025