if_sip.c revision 1.117
1 /* $NetBSD: if_sip.c,v 1.117 2007/12/14 03:38:19 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.117 2007/12/14 03:38:19 dyoung Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 /* 136 * Transmit descriptor list size. This is arbitrary, but allocate 137 * enough descriptors for 128 pending transmissions, and 8 segments 138 * per packet (64 for DP83820 for jumbo frames). 139 * 140 * This MUST work out to a power of 2. 141 */ 142 #define GSIP_NTXSEGS_ALLOC 16 143 #define SIP_NTXSEGS_ALLOC 8 144 145 #define SIP_TXQUEUELEN 256 146 #define MAX_SIP_NTXDESC \ 147 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 148 149 /* 150 * Receive descriptor list size. We have one Rx buffer per incoming 151 * packet, so this logic is a little simpler. 152 * 153 * Actually, on the DP83820, we allow the packet to consume more than 154 * one buffer, in order to support jumbo Ethernet frames. In that 155 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 156 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 157 * so we'd better be quick about handling receive interrupts. 158 */ 159 #define GSIP_NRXDESC 256 160 #define SIP_NRXDESC 128 161 162 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 163 164 /* 165 * Control structures are DMA'd to the SiS900 chip. We allocate them in 166 * a single clump that maps to a single DMA segment to make several things 167 * easier. 168 */ 169 struct sip_control_data { 170 /* 171 * The transmit descriptors. 172 */ 173 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 174 175 /* 176 * The receive descriptors. 177 */ 178 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 179 }; 180 181 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 182 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 183 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 184 185 /* 186 * Software state for transmit jobs. 187 */ 188 struct sip_txsoft { 189 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t txs_dmamap; /* our DMA map */ 191 int txs_firstdesc; /* first descriptor in packet */ 192 int txs_lastdesc; /* last descriptor in packet */ 193 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 194 }; 195 196 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 197 198 /* 199 * Software state for receive jobs. 200 */ 201 struct sip_rxsoft { 202 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 203 bus_dmamap_t rxs_dmamap; /* our DMA map */ 204 }; 205 206 enum sip_attach_stage { 207 SIP_ATTACH_FIN = 0 208 , SIP_ATTACH_CREATE_RXMAP 209 , SIP_ATTACH_CREATE_TXMAP 210 , SIP_ATTACH_LOAD_MAP 211 , SIP_ATTACH_CREATE_MAP 212 , SIP_ATTACH_MAP_MEM 213 , SIP_ATTACH_ALLOC_MEM 214 , SIP_ATTACH_BEGIN 215 }; 216 217 /* 218 * Software state per device. 219 */ 220 struct sip_softc { 221 struct device sc_dev; /* generic device information */ 222 bus_space_tag_t sc_st; /* bus space tag */ 223 bus_space_handle_t sc_sh; /* bus space handle */ 224 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 225 pci_chipset_tag_t sc_pc; 226 bus_dma_segment_t sc_seg; 227 struct ethercom sc_ethercom; /* ethernet common data */ 228 void *sc_sdhook; /* shutdown hook */ 229 230 const struct sip_product *sc_model; /* which model are we? */ 231 int sc_gigabit; /* 1: 83820, 0: other */ 232 int sc_rev; /* chip revision */ 233 234 void *sc_ih; /* interrupt cookie */ 235 236 struct mii_data sc_mii; /* MII/media information */ 237 238 callout_t sc_tick_ch; /* tick callout */ 239 240 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 241 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 242 243 /* 244 * Software state for transmit and receive descriptors. 245 */ 246 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 247 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 248 249 /* 250 * Control data structures. 251 */ 252 struct sip_control_data *sc_control_data; 253 #define sc_txdescs sc_control_data->scd_txdescs 254 #define sc_rxdescs sc_control_data->scd_rxdescs 255 256 #ifdef SIP_EVENT_COUNTERS 257 /* 258 * Event counters. 259 */ 260 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 261 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 262 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 263 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 264 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 265 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 266 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 267 struct evcnt sc_ev_rxpause; /* PAUSE received */ 268 /* DP83820 only */ 269 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 270 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 271 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 272 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 273 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 274 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 275 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 276 #endif /* SIP_EVENT_COUNTERS */ 277 278 u_int32_t sc_txcfg; /* prototype TXCFG register */ 279 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 280 u_int32_t sc_imr; /* prototype IMR register */ 281 u_int32_t sc_rfcr; /* prototype RFCR register */ 282 283 u_int32_t sc_cfg; /* prototype CFG register */ 284 285 u_int32_t sc_gpior; /* prototype GPIOR register */ 286 287 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 288 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 289 290 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 291 292 int sc_flowflags; /* 802.3x flow control flags */ 293 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 294 int sc_paused; /* paused indication */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 int sc_txwin; /* Tx descriptors since last intr */ 299 300 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 301 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 302 303 /* values of interface state at last init */ 304 struct { 305 /* if_capenable */ 306 uint64_t if_capenable; 307 /* ec_capenable */ 308 int ec_capenable; 309 /* VLAN_ATTACHED */ 310 int is_vlan; 311 } sc_prev; 312 313 short sc_if_flags; 314 315 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 322 int sc_ntxdesc; 323 int sc_ntxdesc_mask; 324 int sc_ntxsegs; 325 326 int sc_nrxdesc; 327 int sc_nrxdesc_mask; 328 int sc_rxbuf_len; 329 330 #if NRND > 0 331 rndsource_element_t rnd_source; /* random source */ 332 #endif 333 }; 334 335 static inline int 336 sip_nexttx(const struct sip_softc *sc, int x) 337 { 338 return (x + 1) & sc->sc_ntxdesc_mask; 339 } 340 341 static inline int 342 sip_nextrx(const struct sip_softc *sc, int x) 343 { 344 return (x + 1) & sc->sc_nrxdesc_mask; 345 } 346 347 /* 83820 only */ 348 #define SIP_RXCHAIN_RESET(sc) \ 349 do { \ 350 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 351 *(sc)->sc_rxtailp = NULL; \ 352 (sc)->sc_rxlen = 0; \ 353 } while (/*CONSTCOND*/0) 354 355 /* 83820 only */ 356 #define SIP_RXCHAIN_LINK(sc, m) \ 357 do { \ 358 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 359 (sc)->sc_rxtailp = &(m)->m_next; \ 360 } while (/*CONSTCOND*/0) 361 362 #ifdef SIP_EVENT_COUNTERS 363 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 364 #else 365 #define SIP_EVCNT_INCR(ev) /* nothing */ 366 #endif 367 368 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 369 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 370 371 #define SIP_CDTXSYNC(sc, x, n, ops) \ 372 do { \ 373 int __x, __n; \ 374 \ 375 __x = (x); \ 376 __n = (n); \ 377 \ 378 /* If it will wrap around, sync to the end of the ring. */ \ 379 if ((__x + __n) > sc->sc_ntxdesc) { \ 380 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 381 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 382 (sc->sc_ntxdesc - __x), (ops)); \ 383 __n -= (sc->sc_ntxdesc - __x); \ 384 __x = 0; \ 385 } \ 386 \ 387 /* Now sync whatever is left. */ \ 388 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 389 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 390 } while (0) 391 392 #define SIP_CDRXSYNC(sc, x, ops) \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 395 396 static inline void 397 SIP_INIT_RXDESC(struct sip_softc *sc, int x) 398 { 399 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 400 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 401 402 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 403 sipd->sipd_bufptr = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 404 sipd->sipd_cmdsts = htole32(CMDSTS_INTR | 405 (sc->sc_rxbuf_len & CMDSTS_SIZE_MASK)); 406 sipd->sipd_extsts = 0; 407 SIP_CDRXSYNC(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 408 } 409 410 #define SIP_CHIP_VERS(sc, v, p, r) \ 411 ((sc)->sc_model->sip_vendor == (v) && \ 412 (sc)->sc_model->sip_product == (p) && \ 413 (sc)->sc_rev == (r)) 414 415 #define SIP_CHIP_MODEL(sc, v, p) \ 416 ((sc)->sc_model->sip_vendor == (v) && \ 417 (sc)->sc_model->sip_product == (p)) 418 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 422 #define SIP_TIMEOUT 1000 423 424 static void sipcom_start(struct ifnet *); 425 static void sipcom_watchdog(struct ifnet *); 426 static int sipcom_ioctl(struct ifnet *, u_long, void *); 427 static int sipcom_init(struct ifnet *); 428 static void sipcom_stop(struct ifnet *, int); 429 430 static void sipcom_shutdown(void *); 431 432 static bool sipcom_reset(struct sip_softc *); 433 static void sipcom_rxdrain(struct sip_softc *); 434 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 435 static void sipcom_read_eeprom(struct sip_softc *, int, int, 436 u_int16_t *); 437 static void sipcom_tick(void *); 438 439 static void sipcom_sis900_set_filter(struct sip_softc *); 440 static void sipcom_dp83815_set_filter(struct sip_softc *); 441 442 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 445 static void sipcom_sis900_read_macaddr(struct sip_softc *, 446 const struct pci_attach_args *, u_int8_t *); 447 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 448 const struct pci_attach_args *, u_int8_t *); 449 450 static int sipcom_intr(void *); 451 static void sipcom_txintr(struct sip_softc *); 452 static void SIP_DECL(rxintr)(struct sip_softc *); 453 454 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 455 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 456 static void sipcom_dp83820_mii_statchg(struct device *); 457 458 static int sipcom_sis900_mii_readreg(struct device *, int, int); 459 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 460 static void sipcom_sis900_mii_statchg(struct device *); 461 462 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 463 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 464 static void sipcom_dp83815_mii_statchg(struct device *); 465 466 static int sipcom_mediachange(struct ifnet *); 467 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 468 469 static int sipcom_match(struct device *, struct cfdata *, void *); 470 static void sipcom_attach(struct device *, struct device *, void *); 471 static void sipcom_do_detach(device_t, enum sip_attach_stage); 472 static int sipcom_detach(device_t, int); 473 static bool sipcom_resume(device_t); 474 475 int SIP_DECL(copy_small) = 0; 476 477 #ifdef DP83820 478 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 479 sipcom_match, sipcom_attach, sipcom_detach, NULL); 480 #else 481 CFATTACH_DECL(sip, sizeof(struct sip_softc), 482 sipcom_match, sipcom_attach, sipcom_detach, NULL); 483 #endif 484 485 /* 486 * Descriptions of the variants of the SiS900. 487 */ 488 struct sip_variant { 489 int (*sipv_mii_readreg)(struct device *, int, int); 490 void (*sipv_mii_writereg)(struct device *, int, int, int); 491 void (*sipv_mii_statchg)(struct device *); 492 void (*sipv_set_filter)(struct sip_softc *); 493 void (*sipv_read_macaddr)(struct sip_softc *, 494 const struct pci_attach_args *, u_int8_t *); 495 }; 496 497 static u_int32_t sipcom_mii_bitbang_read(struct device *); 498 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 499 500 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 501 sipcom_mii_bitbang_read, 502 sipcom_mii_bitbang_write, 503 { 504 EROMAR_MDIO, /* MII_BIT_MDO */ 505 EROMAR_MDIO, /* MII_BIT_MDI */ 506 EROMAR_MDC, /* MII_BIT_MDC */ 507 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 508 0, /* MII_BIT_DIR_PHY_HOST */ 509 } 510 }; 511 512 static const struct sip_variant sipcom_variant_dp83820 = { 513 sipcom_dp83820_mii_readreg, 514 sipcom_dp83820_mii_writereg, 515 sipcom_dp83820_mii_statchg, 516 sipcom_dp83815_set_filter, 517 sipcom_dp83820_read_macaddr, 518 }; 519 520 static const struct sip_variant sipcom_variant_sis900 = { 521 sipcom_sis900_mii_readreg, 522 sipcom_sis900_mii_writereg, 523 sipcom_sis900_mii_statchg, 524 sipcom_sis900_set_filter, 525 sipcom_sis900_read_macaddr, 526 }; 527 528 static const struct sip_variant sipcom_variant_dp83815 = { 529 sipcom_dp83815_mii_readreg, 530 sipcom_dp83815_mii_writereg, 531 sipcom_dp83815_mii_statchg, 532 sipcom_dp83815_set_filter, 533 sipcom_dp83815_read_macaddr, 534 }; 535 536 537 /* 538 * Devices supported by this driver. 539 */ 540 static const struct sip_product { 541 pci_vendor_id_t sip_vendor; 542 pci_product_id_t sip_product; 543 const char *sip_name; 544 const struct sip_variant *sip_variant; 545 const int sip_gigabit; 546 } sipcom_products[] = { 547 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 548 "NatSemi DP83820 Gigabit Ethernet", 549 &sipcom_variant_dp83820, 1 }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 551 "SiS 900 10/100 Ethernet", 552 &sipcom_variant_sis900, 0 }, 553 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 554 "SiS 7016 10/100 Ethernet", 555 &sipcom_variant_sis900, 0 }, 556 557 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 558 "NatSemi DP83815 10/100 Ethernet", 559 &sipcom_variant_dp83815, 0 }, 560 561 { 0, 0, 562 NULL, 563 NULL, 0 }, 564 }; 565 566 static const struct sip_product * 567 sipcom_lookup(const struct pci_attach_args *pa) 568 { 569 const struct sip_product *sip; 570 571 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 572 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 573 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 574 return (sip); 575 } 576 return (NULL); 577 } 578 579 /* 580 * I really hate stupid hardware vendors. There's a bit in the EEPROM 581 * which indicates if the card can do 64-bit data transfers. Unfortunately, 582 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 583 * which means we try to use 64-bit data transfers on those cards if we 584 * happen to be plugged into a 32-bit slot. 585 * 586 * What we do is use this table of cards known to be 64-bit cards. If 587 * you have a 64-bit card who's subsystem ID is not listed in this table, 588 * send the output of "pcictl dump ..." of the device to me so that your 589 * card will use the 64-bit data path when plugged into a 64-bit slot. 590 * 591 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 592 * June 30, 2002 593 */ 594 static int 595 sipcom_check_64bit(const struct pci_attach_args *pa) 596 { 597 static const struct { 598 pci_vendor_id_t c64_vendor; 599 pci_product_id_t c64_product; 600 } card64[] = { 601 /* Asante GigaNIX */ 602 { 0x128a, 0x0002 }, 603 604 /* Accton EN1407-T, Planex GN-1000TE */ 605 { 0x1113, 0x1407 }, 606 607 /* Netgear GA-621 */ 608 { 0x1385, 0x621a }, 609 610 /* SMC EZ Card */ 611 { 0x10b8, 0x9462 }, 612 613 { 0, 0} 614 }; 615 pcireg_t subsys; 616 int i; 617 618 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 619 620 for (i = 0; card64[i].c64_vendor != 0; i++) { 621 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 622 PCI_PRODUCT(subsys) == card64[i].c64_product) 623 return (1); 624 } 625 626 return (0); 627 } 628 629 static int 630 sipcom_match(struct device *parent, struct cfdata *cf, 631 void *aux) 632 { 633 struct pci_attach_args *pa = aux; 634 635 if (sipcom_lookup(pa) != NULL) 636 return (1); 637 638 return (0); 639 } 640 641 static void 642 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 643 { 644 u_int32_t reg; 645 int i; 646 647 /* 648 * Cause the chip to load configuration data from the EEPROM. 649 */ 650 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 651 for (i = 0; i < 10000; i++) { 652 delay(10); 653 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 654 PTSCR_EELOAD_EN) == 0) 655 break; 656 } 657 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 658 PTSCR_EELOAD_EN) { 659 printf("%s: timeout loading configuration from EEPROM\n", 660 sc->sc_dev.dv_xname); 661 return; 662 } 663 664 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 665 666 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 667 if (reg & CFG_PCI64_DET) { 668 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 669 /* 670 * Check to see if this card is 64-bit. If so, enable 64-bit 671 * data transfers. 672 * 673 * We can't use the DATA64_EN bit in the EEPROM, because 674 * vendors of 32-bit cards fail to clear that bit in many 675 * cases (yet the card still detects that it's in a 64-bit 676 * slot; go figure). 677 */ 678 if (sipcom_check_64bit(pa)) { 679 sc->sc_cfg |= CFG_DATA64_EN; 680 printf(", using 64-bit data transfers"); 681 } 682 printf("\n"); 683 } 684 685 /* 686 * XXX Need some PCI flags indicating support for 687 * XXX 64-bit addressing. 688 */ 689 #if 0 690 if (reg & CFG_M64ADDR) 691 sc->sc_cfg |= CFG_M64ADDR; 692 if (reg & CFG_T64ADDR) 693 sc->sc_cfg |= CFG_T64ADDR; 694 #endif 695 696 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 697 const char *sep = ""; 698 printf("%s: using ", sc->sc_dev.dv_xname); 699 if (reg & CFG_EXT_125) { 700 sc->sc_cfg |= CFG_EXT_125; 701 printf("%s125MHz clock", sep); 702 sep = ", "; 703 } 704 if (reg & CFG_TBI_EN) { 705 sc->sc_cfg |= CFG_TBI_EN; 706 printf("%sten-bit interface", sep); 707 sep = ", "; 708 } 709 printf("\n"); 710 } 711 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 712 (reg & CFG_MRM_DIS) != 0) 713 sc->sc_cfg |= CFG_MRM_DIS; 714 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 715 (reg & CFG_MWI_DIS) != 0) 716 sc->sc_cfg |= CFG_MWI_DIS; 717 718 /* 719 * Use the extended descriptor format on the DP83820. This 720 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 721 * checksumming. 722 */ 723 sc->sc_cfg |= CFG_EXTSTS_EN; 724 } 725 726 static int 727 sipcom_detach(device_t self, int flags) 728 { 729 sipcom_do_detach(self, SIP_ATTACH_FIN); 730 return 0; 731 } 732 733 static void 734 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 735 { 736 int i; 737 struct sip_softc *sc = device_private(self); 738 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 739 740 /* 741 * Free any resources we've allocated during attach. 742 * Do this in reverse order and fall through. 743 */ 744 switch (stage) { 745 case SIP_ATTACH_FIN: 746 sipcom_stop(ifp, 1); 747 pmf_device_deregister(self); 748 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 749 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 750 751 if (sc->sc_sdhook != NULL) 752 shutdownhook_disestablish(sc->sc_sdhook); 753 754 /*FALLTHROUGH*/ 755 case SIP_ATTACH_CREATE_RXMAP: 756 for (i = 0; i < sc->sc_nrxdesc; i++) { 757 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 758 bus_dmamap_destroy(sc->sc_dmat, 759 sc->sc_rxsoft[i].rxs_dmamap); 760 } 761 /*FALLTHROUGH*/ 762 case SIP_ATTACH_CREATE_TXMAP: 763 for (i = 0; i < SIP_TXQUEUELEN; i++) { 764 if (sc->sc_txsoft[i].txs_dmamap != NULL) 765 bus_dmamap_destroy(sc->sc_dmat, 766 sc->sc_txsoft[i].txs_dmamap); 767 } 768 /*FALLTHROUGH*/ 769 case SIP_ATTACH_LOAD_MAP: 770 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 771 /*FALLTHROUGH*/ 772 case SIP_ATTACH_CREATE_MAP: 773 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 774 /*FALLTHROUGH*/ 775 case SIP_ATTACH_MAP_MEM: 776 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 777 sizeof(struct sip_control_data)); 778 /*FALLTHROUGH*/ 779 case SIP_ATTACH_ALLOC_MEM: 780 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 781 break; 782 default: 783 break; 784 } 785 return; 786 } 787 788 static bool 789 sipcom_resume(device_t self) 790 { 791 struct sip_softc *sc = device_private(self); 792 793 return sipcom_reset(sc); 794 } 795 796 static void 797 sipcom_attach(struct device *parent, struct device *self, void *aux) 798 { 799 struct sip_softc *sc = (struct sip_softc *) self; 800 struct pci_attach_args *pa = aux; 801 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 802 pci_chipset_tag_t pc = pa->pa_pc; 803 pci_intr_handle_t ih; 804 const char *intrstr = NULL; 805 bus_space_tag_t iot, memt; 806 bus_space_handle_t ioh, memh; 807 int ioh_valid, memh_valid; 808 int i, rseg, error; 809 const struct sip_product *sip; 810 u_int8_t enaddr[ETHER_ADDR_LEN]; 811 pcireg_t pmreg; 812 pcireg_t memtype; 813 bus_size_t tx_dmamap_size; 814 int ntxsegs_alloc; 815 816 callout_init(&sc->sc_tick_ch, 0); 817 818 sip = sipcom_lookup(pa); 819 if (sip == NULL) { 820 printf("\n"); 821 panic("%s: impossible", __func__); 822 } 823 sc->sc_gigabit = sip->sip_gigabit; 824 825 sc->sc_pc = pc; 826 827 if (sc->sc_gigabit) { 828 sc->sc_rxbuf_len = MCLBYTES - 8; 829 tx_dmamap_size = ETHER_MAX_LEN_JUMBO; 830 sc->sc_ntxsegs = 64; 831 ntxsegs_alloc = GSIP_NTXSEGS_ALLOC; 832 sc->sc_nrxdesc = GSIP_NRXDESC; 833 } else { 834 sc->sc_rxbuf_len = MCLBYTES - 1; /* field width */ 835 tx_dmamap_size = MCLBYTES; 836 sc->sc_ntxsegs = 16; 837 ntxsegs_alloc = SIP_NTXSEGS_ALLOC; 838 sc->sc_nrxdesc = SIP_NRXDESC; 839 } 840 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 841 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 842 sc->sc_nrxdesc_mask = sc->sc_nrxdesc - 1; 843 844 sc->sc_rev = PCI_REVISION(pa->pa_class); 845 846 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 847 848 sc->sc_model = sip; 849 850 /* 851 * XXX Work-around broken PXE firmware on some boards. 852 * 853 * The DP83815 shares an address decoder with the MEM BAR 854 * and the ROM BAR. Make sure the ROM BAR is disabled, 855 * so that memory mapped access works. 856 */ 857 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 858 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 859 ~PCI_MAPREG_ROM_ENABLE); 860 861 /* 862 * Map the device. 863 */ 864 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 865 PCI_MAPREG_TYPE_IO, 0, 866 &iot, &ioh, NULL, NULL) == 0); 867 if (sc->sc_gigabit) { 868 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 869 switch (memtype) { 870 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 871 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 872 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 873 memtype, 0, &memt, &memh, NULL, NULL) == 0); 874 break; 875 default: 876 memh_valid = 0; 877 } 878 } else { 879 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 880 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 881 &memt, &memh, NULL, NULL) == 0); 882 } 883 884 if (memh_valid) { 885 sc->sc_st = memt; 886 sc->sc_sh = memh; 887 } else if (ioh_valid) { 888 sc->sc_st = iot; 889 sc->sc_sh = ioh; 890 } else { 891 printf("%s: unable to map device registers\n", 892 sc->sc_dev.dv_xname); 893 return; 894 } 895 896 sc->sc_dmat = pa->pa_dmat; 897 898 /* 899 * Make sure bus mastering is enabled. Also make sure 900 * Write/Invalidate is enabled if we're allowed to use it. 901 */ 902 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 903 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 904 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 905 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 906 pmreg | PCI_COMMAND_MASTER_ENABLE); 907 908 /* power up chip */ 909 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 910 NULL)) && error != EOPNOTSUPP) { 911 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 912 error); 913 return; 914 } 915 916 /* 917 * Map and establish our interrupt. 918 */ 919 if (pci_intr_map(pa, &ih)) { 920 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 921 return; 922 } 923 intrstr = pci_intr_string(pc, ih); 924 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 925 if (sc->sc_ih == NULL) { 926 printf("%s: unable to establish interrupt", 927 sc->sc_dev.dv_xname); 928 if (intrstr != NULL) 929 printf(" at %s", intrstr); 930 printf("\n"); 931 return; 932 } 933 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 934 935 SIMPLEQ_INIT(&sc->sc_txfreeq); 936 SIMPLEQ_INIT(&sc->sc_txdirtyq); 937 938 /* 939 * Allocate the control data structures, and create and load the 940 * DMA map for it. 941 */ 942 if ((error = bus_dmamem_alloc(sc->sc_dmat, 943 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 944 &rseg, 0)) != 0) { 945 printf("%s: unable to allocate control data, error = %d\n", 946 sc->sc_dev.dv_xname, error); 947 return sipcom_do_detach(self, -1); 948 } 949 950 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 951 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 952 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 953 printf("%s: unable to map control data, error = %d\n", 954 sc->sc_dev.dv_xname, error); 955 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 956 } 957 958 if ((error = bus_dmamap_create(sc->sc_dmat, 959 sizeof(struct sip_control_data), 1, 960 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 961 printf("%s: unable to create control data DMA map, " 962 "error = %d\n", sc->sc_dev.dv_xname, error); 963 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 964 } 965 966 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 967 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 968 0)) != 0) { 969 printf("%s: unable to load control data DMA map, error = %d\n", 970 sc->sc_dev.dv_xname, error); 971 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 972 } 973 974 /* 975 * Create the transmit buffer DMA maps. 976 */ 977 for (i = 0; i < SIP_TXQUEUELEN; i++) { 978 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 979 sc->sc_ntxsegs, MCLBYTES, 0, 0, 980 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 981 printf("%s: unable to create tx DMA map %d, " 982 "error = %d\n", sc->sc_dev.dv_xname, i, error); 983 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 984 } 985 } 986 987 /* 988 * Create the receive buffer DMA maps. 989 */ 990 for (i = 0; i < sc->sc_nrxdesc; i++) { 991 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 992 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 993 printf("%s: unable to create rx DMA map %d, " 994 "error = %d\n", sc->sc_dev.dv_xname, i, error); 995 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 996 } 997 sc->sc_rxsoft[i].rxs_mbuf = NULL; 998 } 999 1000 /* 1001 * Reset the chip to a known state. 1002 */ 1003 sipcom_reset(sc); 1004 1005 /* 1006 * Read the Ethernet address from the EEPROM. This might 1007 * also fetch other stuff from the EEPROM and stash it 1008 * in the softc. 1009 */ 1010 sc->sc_cfg = 0; 1011 if (!sc->sc_gigabit) { 1012 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1013 SIP_SIS900_REV(sc,SIS_REV_900B)) 1014 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1015 1016 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1017 SIP_SIS900_REV(sc,SIS_REV_960) || 1018 SIP_SIS900_REV(sc,SIS_REV_900B)) 1019 sc->sc_cfg |= 1020 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1021 CFG_EDBMASTEN); 1022 } 1023 1024 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1025 1026 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1027 ether_sprintf(enaddr)); 1028 1029 /* 1030 * Initialize the configuration register: aggressive PCI 1031 * bus request algorithm, default backoff, default OW timer, 1032 * default parity error detection. 1033 * 1034 * NOTE: "Big endian mode" is useless on the SiS900 and 1035 * friends -- it affects packet data, not descriptors. 1036 */ 1037 if (sc->sc_gigabit) 1038 sipcom_dp83820_attach(sc, pa); 1039 1040 /* 1041 * Initialize our media structures and probe the MII. 1042 */ 1043 sc->sc_mii.mii_ifp = ifp; 1044 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1045 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1046 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1047 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sipcom_mediachange, 1048 sipcom_mediastatus); 1049 1050 /* 1051 * XXX We cannot handle flow control on the DP83815. 1052 */ 1053 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1054 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1055 MII_OFFSET_ANY, 0); 1056 else 1057 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1058 MII_OFFSET_ANY, MIIF_DOPAUSE); 1059 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1060 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1061 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1062 } else 1063 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1064 1065 ifp = &sc->sc_ethercom.ec_if; 1066 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1067 ifp->if_softc = sc; 1068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1069 sc->sc_if_flags = ifp->if_flags; 1070 ifp->if_ioctl = sipcom_ioctl; 1071 ifp->if_start = sipcom_start; 1072 ifp->if_watchdog = sipcom_watchdog; 1073 ifp->if_init = sipcom_init; 1074 ifp->if_stop = sipcom_stop; 1075 IFQ_SET_READY(&ifp->if_snd); 1076 1077 /* 1078 * We can support 802.1Q VLAN-sized frames. 1079 */ 1080 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1081 1082 if (sc->sc_gigabit) { 1083 /* 1084 * And the DP83820 can do VLAN tagging in hardware, and 1085 * support the jumbo Ethernet MTU. 1086 */ 1087 sc->sc_ethercom.ec_capabilities |= 1088 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1089 1090 /* 1091 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1092 * in hardware. 1093 */ 1094 ifp->if_capabilities |= 1095 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1096 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1097 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1098 } 1099 1100 /* 1101 * Attach the interface. 1102 */ 1103 if_attach(ifp); 1104 ether_ifattach(ifp, enaddr); 1105 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1106 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1107 sc->sc_prev.if_capenable = ifp->if_capenable; 1108 #if NRND > 0 1109 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1110 RND_TYPE_NET, 0); 1111 #endif 1112 1113 /* 1114 * The number of bytes that must be available in 1115 * the Tx FIFO before the bus master can DMA more 1116 * data into the FIFO. 1117 */ 1118 sc->sc_tx_fill_thresh = 64 / 32; 1119 1120 /* 1121 * Start at a drain threshold of 512 bytes. We will 1122 * increase it if a DMA underrun occurs. 1123 * 1124 * XXX The minimum value of this variable should be 1125 * tuned. We may be able to improve performance 1126 * by starting with a lower value. That, however, 1127 * may trash the first few outgoing packets if the 1128 * PCI bus is saturated. 1129 */ 1130 if (sc->sc_gigabit) 1131 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1132 else 1133 sc->sc_tx_drain_thresh = 1504 / 32; 1134 1135 /* 1136 * Initialize the Rx FIFO drain threshold. 1137 * 1138 * This is in units of 8 bytes. 1139 * 1140 * We should never set this value lower than 2; 14 bytes are 1141 * required to filter the packet. 1142 */ 1143 sc->sc_rx_drain_thresh = 128 / 8; 1144 1145 #ifdef SIP_EVENT_COUNTERS 1146 /* 1147 * Attach event counters. 1148 */ 1149 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1150 NULL, sc->sc_dev.dv_xname, "txsstall"); 1151 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1152 NULL, sc->sc_dev.dv_xname, "txdstall"); 1153 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1154 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1155 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1156 NULL, sc->sc_dev.dv_xname, "txdintr"); 1157 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1158 NULL, sc->sc_dev.dv_xname, "txiintr"); 1159 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1160 NULL, sc->sc_dev.dv_xname, "rxintr"); 1161 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1162 NULL, sc->sc_dev.dv_xname, "hiberr"); 1163 if (!sc->sc_gigabit) { 1164 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1165 NULL, sc->sc_dev.dv_xname, "rxpause"); 1166 } else { 1167 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1168 NULL, sc->sc_dev.dv_xname, "rxpause"); 1169 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1170 NULL, sc->sc_dev.dv_xname, "txpause"); 1171 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1172 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1173 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1174 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1175 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1176 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1177 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1178 NULL, sc->sc_dev.dv_xname, "txipsum"); 1179 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1180 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1181 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1182 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1183 } 1184 #endif /* SIP_EVENT_COUNTERS */ 1185 1186 if (!pmf_device_register(self, NULL, sipcom_resume)) 1187 aprint_error_dev(self, "couldn't establish power handler\n"); 1188 else 1189 pmf_class_network_register(self, ifp); 1190 1191 /* 1192 * Make sure the interface is shutdown during reboot. 1193 */ 1194 sc->sc_sdhook = shutdownhook_establish(sipcom_shutdown, sc); 1195 if (sc->sc_sdhook == NULL) 1196 printf("%s: WARNING: unable to establish shutdown hook\n", 1197 sc->sc_dev.dv_xname); 1198 } 1199 1200 /* 1201 * sip_shutdown: 1202 * 1203 * Make sure the interface is stopped at reboot time. 1204 */ 1205 static void 1206 sipcom_shutdown(void *arg) 1207 { 1208 struct sip_softc *sc = arg; 1209 1210 sipcom_stop(&sc->sc_ethercom.ec_if, 1); 1211 } 1212 1213 static inline void 1214 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1215 uint64_t capenable) 1216 { 1217 struct m_tag *mtag; 1218 u_int32_t extsts; 1219 /* 1220 * If VLANs are enabled and the packet has a VLAN tag, set 1221 * up the descriptor to encapsulate the packet for us. 1222 * 1223 * This apparently has to be on the last descriptor of 1224 * the packet. 1225 */ 1226 1227 /* 1228 * Byte swapping is tricky. We need to provide the tag 1229 * in a network byte order. On a big-endian machine, 1230 * the byteorder is correct, but we need to swap it 1231 * anyway, because this will be undone by the outside 1232 * htole32(). That's why there must be an 1233 * unconditional swap instead of htons() inside. 1234 */ 1235 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1236 sc->sc_txdescs[lasttx].sipd_extsts |= 1237 htole32(EXTSTS_VPKT | 1238 (bswap16(VLAN_TAG_VALUE(mtag)) & 1239 EXTSTS_VTCI)); 1240 } 1241 1242 /* 1243 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1244 * checksumming, set up the descriptor to do this work 1245 * for us. 1246 * 1247 * This apparently has to be on the first descriptor of 1248 * the packet. 1249 * 1250 * Byte-swap constants so the compiler can optimize. 1251 */ 1252 extsts = 0; 1253 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1254 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1255 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1256 extsts |= htole32(EXTSTS_IPPKT); 1257 } 1258 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1259 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1260 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1261 extsts |= htole32(EXTSTS_TCPPKT); 1262 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1263 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1264 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1265 extsts |= htole32(EXTSTS_UDPPKT); 1266 } 1267 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1268 } 1269 1270 /* 1271 * sip_start: [ifnet interface function] 1272 * 1273 * Start packet transmission on the interface. 1274 */ 1275 static void 1276 sipcom_start(struct ifnet *ifp) 1277 { 1278 struct sip_softc *sc = ifp->if_softc; 1279 struct mbuf *m0; 1280 struct mbuf *m; 1281 struct sip_txsoft *txs; 1282 bus_dmamap_t dmamap; 1283 int error, nexttx, lasttx, seg; 1284 int ofree = sc->sc_txfree; 1285 #if 0 1286 int firsttx = sc->sc_txnext; 1287 #endif 1288 1289 /* 1290 * If we've been told to pause, don't transmit any more packets. 1291 */ 1292 if (!sc->sc_gigabit && sc->sc_paused) 1293 ifp->if_flags |= IFF_OACTIVE; 1294 1295 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1296 return; 1297 1298 /* 1299 * Loop through the send queue, setting up transmit descriptors 1300 * until we drain the queue, or use up all available transmit 1301 * descriptors. 1302 */ 1303 for (;;) { 1304 /* Get a work queue entry. */ 1305 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1306 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1307 break; 1308 } 1309 1310 /* 1311 * Grab a packet off the queue. 1312 */ 1313 IFQ_POLL(&ifp->if_snd, m0); 1314 if (m0 == NULL) 1315 break; 1316 m = NULL; 1317 1318 dmamap = txs->txs_dmamap; 1319 1320 /* 1321 * Load the DMA map. If this fails, the packet either 1322 * didn't fit in the alloted number of segments, or we 1323 * were short on resources. 1324 */ 1325 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1326 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1327 /* In the non-gigabit case, we'll copy and try again. */ 1328 if (error != 0 && !sc->sc_gigabit) { 1329 MGETHDR(m, M_DONTWAIT, MT_DATA); 1330 if (m == NULL) { 1331 printf("%s: unable to allocate Tx mbuf\n", 1332 sc->sc_dev.dv_xname); 1333 break; 1334 } 1335 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1336 if (m0->m_pkthdr.len > MHLEN) { 1337 MCLGET(m, M_DONTWAIT); 1338 if ((m->m_flags & M_EXT) == 0) { 1339 printf("%s: unable to allocate Tx " 1340 "cluster\n", sc->sc_dev.dv_xname); 1341 m_freem(m); 1342 break; 1343 } 1344 } 1345 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1346 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1347 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1348 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1349 if (error) { 1350 printf("%s: unable to load Tx buffer, " 1351 "error = %d\n", sc->sc_dev.dv_xname, error); 1352 break; 1353 } 1354 } else if (error == EFBIG) { 1355 /* 1356 * For the too-many-segments case, we simply 1357 * report an error and drop the packet, 1358 * since we can't sanely copy a jumbo packet 1359 * to a single buffer. 1360 */ 1361 printf("%s: Tx packet consumes too many " 1362 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1363 IFQ_DEQUEUE(&ifp->if_snd, m0); 1364 m_freem(m0); 1365 continue; 1366 } else if (error != 0) { 1367 /* 1368 * Short on resources, just stop for now. 1369 */ 1370 break; 1371 } 1372 1373 /* 1374 * Ensure we have enough descriptors free to describe 1375 * the packet. Note, we always reserve one descriptor 1376 * at the end of the ring as a termination point, to 1377 * prevent wrap-around. 1378 */ 1379 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1380 /* 1381 * Not enough free descriptors to transmit this 1382 * packet. We haven't committed anything yet, 1383 * so just unload the DMA map, put the packet 1384 * back on the queue, and punt. Notify the upper 1385 * layer that there are not more slots left. 1386 * 1387 * XXX We could allocate an mbuf and copy, but 1388 * XXX is it worth it? 1389 */ 1390 ifp->if_flags |= IFF_OACTIVE; 1391 bus_dmamap_unload(sc->sc_dmat, dmamap); 1392 if (m != NULL) 1393 m_freem(m); 1394 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1395 break; 1396 } 1397 1398 IFQ_DEQUEUE(&ifp->if_snd, m0); 1399 if (m != NULL) { 1400 m_freem(m0); 1401 m0 = m; 1402 } 1403 1404 /* 1405 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1406 */ 1407 1408 /* Sync the DMA map. */ 1409 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1410 BUS_DMASYNC_PREWRITE); 1411 1412 /* 1413 * Initialize the transmit descriptors. 1414 */ 1415 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1416 seg < dmamap->dm_nsegs; 1417 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1418 /* 1419 * If this is the first descriptor we're 1420 * enqueueing, don't set the OWN bit just 1421 * yet. That could cause a race condition. 1422 * We'll do it below. 1423 */ 1424 sc->sc_txdescs[nexttx].sipd_bufptr = 1425 htole32(dmamap->dm_segs[seg].ds_addr); 1426 sc->sc_txdescs[nexttx].sipd_cmdsts = 1427 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1428 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1429 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1430 lasttx = nexttx; 1431 } 1432 1433 /* Clear the MORE bit on the last segment. */ 1434 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1435 1436 /* 1437 * If we're in the interrupt delay window, delay the 1438 * interrupt. 1439 */ 1440 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1441 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1442 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1443 htole32(CMDSTS_INTR); 1444 sc->sc_txwin = 0; 1445 } 1446 1447 if (sc->sc_gigabit) 1448 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1449 1450 /* Sync the descriptors we're using. */ 1451 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1452 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1453 1454 /* 1455 * The entire packet is set up. Give the first descrptor 1456 * to the chip now. 1457 */ 1458 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1459 htole32(CMDSTS_OWN); 1460 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1461 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1462 1463 /* 1464 * Store a pointer to the packet so we can free it later, 1465 * and remember what txdirty will be once the packet is 1466 * done. 1467 */ 1468 txs->txs_mbuf = m0; 1469 txs->txs_firstdesc = sc->sc_txnext; 1470 txs->txs_lastdesc = lasttx; 1471 1472 /* Advance the tx pointer. */ 1473 sc->sc_txfree -= dmamap->dm_nsegs; 1474 sc->sc_txnext = nexttx; 1475 1476 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1477 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1478 1479 #if NBPFILTER > 0 1480 /* 1481 * Pass the packet to any BPF listeners. 1482 */ 1483 if (ifp->if_bpf) 1484 bpf_mtap(ifp->if_bpf, m0); 1485 #endif /* NBPFILTER > 0 */ 1486 } 1487 1488 if (txs == NULL || sc->sc_txfree == 0) { 1489 /* No more slots left; notify upper layer. */ 1490 ifp->if_flags |= IFF_OACTIVE; 1491 } 1492 1493 if (sc->sc_txfree != ofree) { 1494 /* 1495 * Start the transmit process. Note, the manual says 1496 * that if there are no pending transmissions in the 1497 * chip's internal queue (indicated by TXE being clear), 1498 * then the driver software must set the TXDP to the 1499 * first descriptor to be transmitted. However, if we 1500 * do this, it causes serious performance degredation on 1501 * the DP83820 under load, not setting TXDP doesn't seem 1502 * to adversely affect the SiS 900 or DP83815. 1503 * 1504 * Well, I guess it wouldn't be the first time a manual 1505 * has lied -- and they could be speaking of the NULL- 1506 * terminated descriptor list case, rather than OWN- 1507 * terminated rings. 1508 */ 1509 #if 0 1510 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1511 CR_TXE) == 0) { 1512 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1513 SIP_CDTXADDR(sc, firsttx)); 1514 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1515 } 1516 #else 1517 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1518 #endif 1519 1520 /* Set a watchdog timer in case the chip flakes out. */ 1521 /* Gigabit autonegotiation takes 5 seconds. */ 1522 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1523 } 1524 } 1525 1526 /* 1527 * sip_watchdog: [ifnet interface function] 1528 * 1529 * Watchdog timer handler. 1530 */ 1531 static void 1532 sipcom_watchdog(struct ifnet *ifp) 1533 { 1534 struct sip_softc *sc = ifp->if_softc; 1535 1536 /* 1537 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1538 * If we get a timeout, try and sweep up transmit descriptors. 1539 * If we manage to sweep them all up, ignore the lack of 1540 * interrupt. 1541 */ 1542 sipcom_txintr(sc); 1543 1544 if (sc->sc_txfree != sc->sc_ntxdesc) { 1545 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1546 ifp->if_oerrors++; 1547 1548 /* Reset the interface. */ 1549 (void) sipcom_init(ifp); 1550 } else if (ifp->if_flags & IFF_DEBUG) 1551 printf("%s: recovered from device timeout\n", 1552 sc->sc_dev.dv_xname); 1553 1554 /* Try to get more packets going. */ 1555 sipcom_start(ifp); 1556 } 1557 1558 /* 1559 * sip_ioctl: [ifnet interface function] 1560 * 1561 * Handle control requests from the operator. 1562 */ 1563 static int 1564 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1565 { 1566 struct sip_softc *sc = ifp->if_softc; 1567 struct ifreq *ifr = (struct ifreq *)data; 1568 int s, error; 1569 1570 s = splnet(); 1571 1572 switch (cmd) { 1573 case SIOCSIFMEDIA: 1574 /* Flow control requires full-duplex mode. */ 1575 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1576 (ifr->ifr_media & IFM_FDX) == 0) 1577 ifr->ifr_media &= ~IFM_ETH_FMASK; 1578 1579 /* XXX */ 1580 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1581 ifr->ifr_media &= ~IFM_ETH_FMASK; 1582 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1583 if (sc->sc_gigabit && 1584 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1585 /* We can do both TXPAUSE and RXPAUSE. */ 1586 ifr->ifr_media |= 1587 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1588 } else if (ifr->ifr_media & IFM_FLOW) { 1589 /* 1590 * Both TXPAUSE and RXPAUSE must be set. 1591 * (SiS900 and DP83815 don't have PAUSE_ASYM 1592 * feature.) 1593 * 1594 * XXX Can SiS900 and DP83815 send PAUSE? 1595 */ 1596 ifr->ifr_media |= 1597 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1598 } 1599 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1600 } 1601 /* FALLTHROUGH */ 1602 case SIOCGIFMEDIA: 1603 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1604 break; 1605 case SIOCSIFFLAGS: 1606 /* If the interface is up and running, only modify the receive 1607 * filter when setting promiscuous or debug mode. Otherwise 1608 * fall through to ether_ioctl, which will reset the chip. 1609 */ 1610 1611 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1612 == (sc)->sc_ethercom.ec_capenable) \ 1613 && ((sc)->sc_prev.is_vlan == \ 1614 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1615 1616 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1617 1618 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1619 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1620 == (IFF_UP|IFF_RUNNING)) 1621 && ((ifp->if_flags & (~RESETIGN)) 1622 == (sc->sc_if_flags & (~RESETIGN))) 1623 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1624 /* Set up the receive filter. */ 1625 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1626 error = 0; 1627 break; 1628 #undef RESETIGN 1629 } 1630 /* FALLTHROUGH */ 1631 default: 1632 error = ether_ioctl(ifp, cmd, data); 1633 if (error == ENETRESET) { 1634 /* 1635 * Multicast list has changed; set the hardware filter 1636 * accordingly. 1637 */ 1638 if (ifp->if_flags & IFF_RUNNING) 1639 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1640 error = 0; 1641 } 1642 break; 1643 } 1644 1645 /* Try to get more packets going. */ 1646 sipcom_start(ifp); 1647 1648 sc->sc_if_flags = ifp->if_flags; 1649 splx(s); 1650 return (error); 1651 } 1652 1653 /* 1654 * sip_intr: 1655 * 1656 * Interrupt service routine. 1657 */ 1658 static int 1659 sipcom_intr(void *arg) 1660 { 1661 struct sip_softc *sc = arg; 1662 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1663 u_int32_t isr; 1664 int handled = 0; 1665 1666 /* Disable interrupts. */ 1667 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1668 1669 for (;;) { 1670 /* Reading clears interrupt. */ 1671 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1672 if ((isr & sc->sc_imr) == 0) 1673 break; 1674 1675 #if NRND > 0 1676 if (RND_ENABLED(&sc->rnd_source)) 1677 rnd_add_uint32(&sc->rnd_source, isr); 1678 #endif 1679 1680 handled = 1; 1681 1682 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1683 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1684 1685 /* Grab any new packets. */ 1686 SIP_DECL(rxintr)(sc); 1687 1688 if (isr & ISR_RXORN) { 1689 printf("%s: receive FIFO overrun\n", 1690 sc->sc_dev.dv_xname); 1691 1692 /* XXX adjust rx_drain_thresh? */ 1693 } 1694 1695 if (isr & ISR_RXIDLE) { 1696 printf("%s: receive ring overrun\n", 1697 sc->sc_dev.dv_xname); 1698 1699 /* Get the receive process going again. */ 1700 bus_space_write_4(sc->sc_st, sc->sc_sh, 1701 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1702 bus_space_write_4(sc->sc_st, sc->sc_sh, 1703 SIP_CR, CR_RXE); 1704 } 1705 } 1706 1707 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1708 #ifdef SIP_EVENT_COUNTERS 1709 if (isr & ISR_TXDESC) 1710 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1711 else if (isr & ISR_TXIDLE) 1712 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1713 #endif 1714 1715 /* Sweep up transmit descriptors. */ 1716 sipcom_txintr(sc); 1717 1718 if (isr & ISR_TXURN) { 1719 u_int32_t thresh; 1720 1721 printf("%s: transmit FIFO underrun", 1722 sc->sc_dev.dv_xname); 1723 1724 thresh = sc->sc_tx_drain_thresh + 1; 1725 if (thresh <= TXCFG_DRTH && 1726 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1727 (sc->sc_tx_fill_thresh * 32))) { 1728 printf("; increasing Tx drain " 1729 "threshold to %u bytes\n", 1730 thresh * 32); 1731 sc->sc_tx_drain_thresh = thresh; 1732 (void) sipcom_init(ifp); 1733 } else { 1734 (void) sipcom_init(ifp); 1735 printf("\n"); 1736 } 1737 } 1738 } 1739 1740 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1741 if (isr & ISR_PAUSE_ST) { 1742 sc->sc_paused = 1; 1743 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1744 ifp->if_flags |= IFF_OACTIVE; 1745 } 1746 if (isr & ISR_PAUSE_END) { 1747 sc->sc_paused = 0; 1748 ifp->if_flags &= ~IFF_OACTIVE; 1749 } 1750 } 1751 1752 if (isr & ISR_HIBERR) { 1753 int want_init = 0; 1754 1755 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1756 1757 #define PRINTERR(bit, str) \ 1758 do { \ 1759 if ((isr & (bit)) != 0) { \ 1760 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1761 printf("%s: %s\n", \ 1762 sc->sc_dev.dv_xname, str); \ 1763 want_init = 1; \ 1764 } \ 1765 } while (/*CONSTCOND*/0) 1766 1767 PRINTERR(ISR_DPERR, "parity error"); 1768 PRINTERR(ISR_SSERR, "system error"); 1769 PRINTERR(ISR_RMABT, "master abort"); 1770 PRINTERR(ISR_RTABT, "target abort"); 1771 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1772 /* 1773 * Ignore: 1774 * Tx reset complete 1775 * Rx reset complete 1776 */ 1777 if (want_init) 1778 (void) sipcom_init(ifp); 1779 #undef PRINTERR 1780 } 1781 } 1782 1783 /* Re-enable interrupts. */ 1784 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1785 1786 /* Try to get more packets going. */ 1787 sipcom_start(ifp); 1788 1789 return (handled); 1790 } 1791 1792 /* 1793 * sip_txintr: 1794 * 1795 * Helper; handle transmit interrupts. 1796 */ 1797 static void 1798 sipcom_txintr(struct sip_softc *sc) 1799 { 1800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1801 struct sip_txsoft *txs; 1802 u_int32_t cmdsts; 1803 1804 if (sc->sc_paused == 0) 1805 ifp->if_flags &= ~IFF_OACTIVE; 1806 1807 /* 1808 * Go through our Tx list and free mbufs for those 1809 * frames which have been transmitted. 1810 */ 1811 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1812 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1813 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1814 1815 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1816 if (cmdsts & CMDSTS_OWN) 1817 break; 1818 1819 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1820 1821 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1822 1823 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1824 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1825 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1826 m_freem(txs->txs_mbuf); 1827 txs->txs_mbuf = NULL; 1828 1829 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1830 1831 /* 1832 * Check for errors and collisions. 1833 */ 1834 if (cmdsts & 1835 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1836 ifp->if_oerrors++; 1837 if (cmdsts & CMDSTS_Tx_EC) 1838 ifp->if_collisions += 16; 1839 if (ifp->if_flags & IFF_DEBUG) { 1840 if (cmdsts & CMDSTS_Tx_ED) 1841 printf("%s: excessive deferral\n", 1842 sc->sc_dev.dv_xname); 1843 if (cmdsts & CMDSTS_Tx_EC) 1844 printf("%s: excessive collisions\n", 1845 sc->sc_dev.dv_xname); 1846 } 1847 } else { 1848 /* Packet was transmitted successfully. */ 1849 ifp->if_opackets++; 1850 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1851 } 1852 } 1853 1854 /* 1855 * If there are no more pending transmissions, cancel the watchdog 1856 * timer. 1857 */ 1858 if (txs == NULL) { 1859 ifp->if_timer = 0; 1860 sc->sc_txwin = 0; 1861 } 1862 } 1863 1864 #if defined(DP83820) 1865 /* 1866 * sip_rxintr: 1867 * 1868 * Helper; handle receive interrupts. 1869 */ 1870 static void 1871 SIP_DECL(rxintr)(struct sip_softc *sc) 1872 { 1873 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1874 struct sip_rxsoft *rxs; 1875 struct mbuf *m; 1876 u_int32_t cmdsts, extsts; 1877 int i, len; 1878 1879 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 1880 rxs = &sc->sc_rxsoft[i]; 1881 1882 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1883 1884 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1885 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1886 len = CMDSTS_SIZE(cmdsts); 1887 1888 /* 1889 * NOTE: OWN is set if owned by _consumer_. We're the 1890 * consumer of the receive ring, so if the bit is clear, 1891 * we have processed all of the packets. 1892 */ 1893 if ((cmdsts & CMDSTS_OWN) == 0) { 1894 /* 1895 * We have processed all of the receive buffers. 1896 */ 1897 break; 1898 } 1899 1900 if (__predict_false(sc->sc_rxdiscard)) { 1901 SIP_INIT_RXDESC(sc, i); 1902 if ((cmdsts & CMDSTS_MORE) == 0) { 1903 /* Reset our state. */ 1904 sc->sc_rxdiscard = 0; 1905 } 1906 continue; 1907 } 1908 1909 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1910 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1911 1912 m = rxs->rxs_mbuf; 1913 1914 /* 1915 * Add a new receive buffer to the ring. 1916 */ 1917 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1918 /* 1919 * Failed, throw away what we've done so 1920 * far, and discard the rest of the packet. 1921 */ 1922 ifp->if_ierrors++; 1923 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1924 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1925 SIP_INIT_RXDESC(sc, i); 1926 if (cmdsts & CMDSTS_MORE) 1927 sc->sc_rxdiscard = 1; 1928 if (sc->sc_rxhead != NULL) 1929 m_freem(sc->sc_rxhead); 1930 SIP_RXCHAIN_RESET(sc); 1931 continue; 1932 } 1933 1934 SIP_RXCHAIN_LINK(sc, m); 1935 1936 m->m_len = len; 1937 1938 /* 1939 * If this is not the end of the packet, keep 1940 * looking. 1941 */ 1942 if (cmdsts & CMDSTS_MORE) { 1943 sc->sc_rxlen += len; 1944 continue; 1945 } 1946 1947 /* 1948 * Okay, we have the entire packet now. The chip includes 1949 * the FCS, so we need to trim it. 1950 */ 1951 m->m_len -= ETHER_CRC_LEN; 1952 1953 *sc->sc_rxtailp = NULL; 1954 len = m->m_len + sc->sc_rxlen; 1955 m = sc->sc_rxhead; 1956 1957 SIP_RXCHAIN_RESET(sc); 1958 1959 /* 1960 * If an error occurred, update stats and drop the packet. 1961 */ 1962 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1963 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1964 ifp->if_ierrors++; 1965 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1966 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1967 /* Receive overrun handled elsewhere. */ 1968 printf("%s: receive descriptor error\n", 1969 sc->sc_dev.dv_xname); 1970 } 1971 #define PRINTERR(bit, str) \ 1972 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1973 (cmdsts & (bit)) != 0) \ 1974 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1975 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1976 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1977 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1978 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1979 #undef PRINTERR 1980 m_freem(m); 1981 continue; 1982 } 1983 1984 /* 1985 * If the packet is small enough to fit in a 1986 * single header mbuf, allocate one and copy 1987 * the data into it. This greatly reduces 1988 * memory consumption when we receive lots 1989 * of small packets. 1990 */ 1991 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1992 struct mbuf *nm; 1993 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1994 if (nm == NULL) { 1995 ifp->if_ierrors++; 1996 m_freem(m); 1997 continue; 1998 } 1999 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2000 nm->m_data += 2; 2001 nm->m_pkthdr.len = nm->m_len = len; 2002 m_copydata(m, 0, len, mtod(nm, void *)); 2003 m_freem(m); 2004 m = nm; 2005 } 2006 #ifndef __NO_STRICT_ALIGNMENT 2007 else { 2008 /* 2009 * The DP83820's receive buffers must be 4-byte 2010 * aligned. But this means that the data after 2011 * the Ethernet header is misaligned. To compensate, 2012 * we have artificially shortened the buffer size 2013 * in the descriptor, and we do an overlapping copy 2014 * of the data two bytes further in (in the first 2015 * buffer of the chain only). 2016 */ 2017 memmove(mtod(m, char *) + 2, mtod(m, void *), 2018 m->m_len); 2019 m->m_data += 2; 2020 } 2021 #endif /* ! __NO_STRICT_ALIGNMENT */ 2022 2023 /* 2024 * If VLANs are enabled, VLAN packets have been unwrapped 2025 * for us. Associate the tag with the packet. 2026 */ 2027 2028 /* 2029 * Again, byte swapping is tricky. Hardware provided 2030 * the tag in the network byte order, but extsts was 2031 * passed through le32toh() in the meantime. On a 2032 * big-endian machine, we need to swap it again. On a 2033 * little-endian machine, we need to convert from the 2034 * network to host byte order. This means that we must 2035 * swap it in any case, so unconditional swap instead 2036 * of htons() is used. 2037 */ 2038 if ((extsts & EXTSTS_VPKT) != 0) { 2039 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2040 continue); 2041 } 2042 2043 /* 2044 * Set the incoming checksum information for the 2045 * packet. 2046 */ 2047 if ((extsts & EXTSTS_IPPKT) != 0) { 2048 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2049 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2050 if (extsts & EXTSTS_Rx_IPERR) 2051 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2052 if (extsts & EXTSTS_TCPPKT) { 2053 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2054 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2055 if (extsts & EXTSTS_Rx_TCPERR) 2056 m->m_pkthdr.csum_flags |= 2057 M_CSUM_TCP_UDP_BAD; 2058 } else if (extsts & EXTSTS_UDPPKT) { 2059 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2060 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2061 if (extsts & EXTSTS_Rx_UDPERR) 2062 m->m_pkthdr.csum_flags |= 2063 M_CSUM_TCP_UDP_BAD; 2064 } 2065 } 2066 2067 ifp->if_ipackets++; 2068 m->m_pkthdr.rcvif = ifp; 2069 m->m_pkthdr.len = len; 2070 2071 #if NBPFILTER > 0 2072 /* 2073 * Pass this up to any BPF listeners, but only 2074 * pass if up the stack if it's for us. 2075 */ 2076 if (ifp->if_bpf) 2077 bpf_mtap(ifp->if_bpf, m); 2078 #endif /* NBPFILTER > 0 */ 2079 2080 /* Pass it on. */ 2081 (*ifp->if_input)(ifp, m); 2082 } 2083 2084 /* Update the receive pointer. */ 2085 sc->sc_rxptr = i; 2086 } 2087 #else /* ! DP83820 */ 2088 /* 2089 * sip_rxintr: 2090 * 2091 * Helper; handle receive interrupts. 2092 */ 2093 static void 2094 SIP_DECL(rxintr)(struct sip_softc *sc) 2095 { 2096 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2097 struct sip_rxsoft *rxs; 2098 struct mbuf *m; 2099 u_int32_t cmdsts; 2100 int i, len; 2101 2102 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2103 rxs = &sc->sc_rxsoft[i]; 2104 2105 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2106 2107 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2108 2109 /* 2110 * NOTE: OWN is set if owned by _consumer_. We're the 2111 * consumer of the receive ring, so if the bit is clear, 2112 * we have processed all of the packets. 2113 */ 2114 if ((cmdsts & CMDSTS_OWN) == 0) { 2115 /* 2116 * We have processed all of the receive buffers. 2117 */ 2118 break; 2119 } 2120 2121 /* 2122 * If any collisions were seen on the wire, count one. 2123 */ 2124 if (cmdsts & CMDSTS_Rx_COL) 2125 ifp->if_collisions++; 2126 2127 /* 2128 * If an error occurred, update stats, clear the status 2129 * word, and leave the packet buffer in place. It will 2130 * simply be reused the next time the ring comes around. 2131 */ 2132 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2133 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2134 ifp->if_ierrors++; 2135 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2136 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2137 /* Receive overrun handled elsewhere. */ 2138 printf("%s: receive descriptor error\n", 2139 sc->sc_dev.dv_xname); 2140 } 2141 #define PRINTERR(bit, str) \ 2142 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2143 (cmdsts & (bit)) != 0) \ 2144 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2145 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2146 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2147 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2148 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2149 #undef PRINTERR 2150 SIP_INIT_RXDESC(sc, i); 2151 continue; 2152 } 2153 2154 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2155 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2156 2157 /* 2158 * No errors; receive the packet. Note, the SiS 900 2159 * includes the CRC with every packet. 2160 */ 2161 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2162 2163 #ifdef __NO_STRICT_ALIGNMENT 2164 /* 2165 * If the packet is small enough to fit in a 2166 * single header mbuf, allocate one and copy 2167 * the data into it. This greatly reduces 2168 * memory consumption when we receive lots 2169 * of small packets. 2170 * 2171 * Otherwise, we add a new buffer to the receive 2172 * chain. If this fails, we drop the packet and 2173 * recycle the old buffer. 2174 */ 2175 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2176 MGETHDR(m, M_DONTWAIT, MT_DATA); 2177 if (m == NULL) 2178 goto dropit; 2179 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2180 memcpy(mtod(m, void *), 2181 mtod(rxs->rxs_mbuf, void *), len); 2182 SIP_INIT_RXDESC(sc, i); 2183 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2184 rxs->rxs_dmamap->dm_mapsize, 2185 BUS_DMASYNC_PREREAD); 2186 } else { 2187 m = rxs->rxs_mbuf; 2188 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2189 dropit: 2190 ifp->if_ierrors++; 2191 SIP_INIT_RXDESC(sc, i); 2192 bus_dmamap_sync(sc->sc_dmat, 2193 rxs->rxs_dmamap, 0, 2194 rxs->rxs_dmamap->dm_mapsize, 2195 BUS_DMASYNC_PREREAD); 2196 continue; 2197 } 2198 } 2199 #else 2200 /* 2201 * The SiS 900's receive buffers must be 4-byte aligned. 2202 * But this means that the data after the Ethernet header 2203 * is misaligned. We must allocate a new buffer and 2204 * copy the data, shifted forward 2 bytes. 2205 */ 2206 MGETHDR(m, M_DONTWAIT, MT_DATA); 2207 if (m == NULL) { 2208 dropit: 2209 ifp->if_ierrors++; 2210 SIP_INIT_RXDESC(sc, i); 2211 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2212 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2213 continue; 2214 } 2215 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2216 if (len > (MHLEN - 2)) { 2217 MCLGET(m, M_DONTWAIT); 2218 if ((m->m_flags & M_EXT) == 0) { 2219 m_freem(m); 2220 goto dropit; 2221 } 2222 } 2223 m->m_data += 2; 2224 2225 /* 2226 * Note that we use clusters for incoming frames, so the 2227 * buffer is virtually contiguous. 2228 */ 2229 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2230 2231 /* Allow the receive descriptor to continue using its mbuf. */ 2232 SIP_INIT_RXDESC(sc, i); 2233 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2234 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2235 #endif /* __NO_STRICT_ALIGNMENT */ 2236 2237 ifp->if_ipackets++; 2238 m->m_pkthdr.rcvif = ifp; 2239 m->m_pkthdr.len = m->m_len = len; 2240 2241 #if NBPFILTER > 0 2242 /* 2243 * Pass this up to any BPF listeners, but only 2244 * pass if up the stack if it's for us. 2245 */ 2246 if (ifp->if_bpf) 2247 bpf_mtap(ifp->if_bpf, m); 2248 #endif /* NBPFILTER > 0 */ 2249 2250 /* Pass it on. */ 2251 (*ifp->if_input)(ifp, m); 2252 } 2253 2254 /* Update the receive pointer. */ 2255 sc->sc_rxptr = i; 2256 } 2257 #endif /* DP83820 */ 2258 2259 /* 2260 * sip_tick: 2261 * 2262 * One second timer, used to tick the MII. 2263 */ 2264 static void 2265 sipcom_tick(void *arg) 2266 { 2267 struct sip_softc *sc = arg; 2268 int s; 2269 2270 s = splnet(); 2271 #ifdef SIP_EVENT_COUNTERS 2272 if (sc->sc_gigabit) { 2273 /* Read PAUSE related counts from MIB registers. */ 2274 sc->sc_ev_rxpause.ev_count += 2275 bus_space_read_4(sc->sc_st, sc->sc_sh, 2276 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2277 sc->sc_ev_txpause.ev_count += 2278 bus_space_read_4(sc->sc_st, sc->sc_sh, 2279 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2280 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2281 } 2282 #endif /* SIP_EVENT_COUNTERS */ 2283 mii_tick(&sc->sc_mii); 2284 splx(s); 2285 2286 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2287 } 2288 2289 /* 2290 * sip_reset: 2291 * 2292 * Perform a soft reset on the SiS 900. 2293 */ 2294 static bool 2295 sipcom_reset(struct sip_softc *sc) 2296 { 2297 bus_space_tag_t st = sc->sc_st; 2298 bus_space_handle_t sh = sc->sc_sh; 2299 int i; 2300 2301 bus_space_write_4(st, sh, SIP_IER, 0); 2302 bus_space_write_4(st, sh, SIP_IMR, 0); 2303 bus_space_write_4(st, sh, SIP_RFCR, 0); 2304 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2305 2306 for (i = 0; i < SIP_TIMEOUT; i++) { 2307 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2308 break; 2309 delay(2); 2310 } 2311 2312 if (i == SIP_TIMEOUT) { 2313 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2314 return false; 2315 } 2316 2317 delay(1000); 2318 2319 if (sc->sc_gigabit) { 2320 /* 2321 * Set the general purpose I/O bits. Do it here in case we 2322 * need to have GPIO set up to talk to the media interface. 2323 */ 2324 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2325 delay(1000); 2326 } 2327 return true; 2328 } 2329 2330 static void 2331 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2332 { 2333 u_int32_t reg; 2334 bus_space_tag_t st = sc->sc_st; 2335 bus_space_handle_t sh = sc->sc_sh; 2336 /* 2337 * Initialize the VLAN/IP receive control register. 2338 * We enable checksum computation on all incoming 2339 * packets, and do not reject packets w/ bad checksums. 2340 */ 2341 reg = 0; 2342 if (capenable & 2343 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2344 reg |= VRCR_IPEN; 2345 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2346 reg |= VRCR_VTDEN|VRCR_VTREN; 2347 bus_space_write_4(st, sh, SIP_VRCR, reg); 2348 2349 /* 2350 * Initialize the VLAN/IP transmit control register. 2351 * We enable outgoing checksum computation on a 2352 * per-packet basis. 2353 */ 2354 reg = 0; 2355 if (capenable & 2356 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2357 reg |= VTCR_PPCHK; 2358 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2359 reg |= VTCR_VPPTI; 2360 bus_space_write_4(st, sh, SIP_VTCR, reg); 2361 2362 /* 2363 * If we're using VLANs, initialize the VLAN data register. 2364 * To understand why we bswap the VLAN Ethertype, see section 2365 * 4.2.36 of the DP83820 manual. 2366 */ 2367 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2368 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2369 } 2370 2371 /* 2372 * sip_init: [ ifnet interface function ] 2373 * 2374 * Initialize the interface. Must be called at splnet(). 2375 */ 2376 static int 2377 sipcom_init(struct ifnet *ifp) 2378 { 2379 struct sip_softc *sc = ifp->if_softc; 2380 bus_space_tag_t st = sc->sc_st; 2381 bus_space_handle_t sh = sc->sc_sh; 2382 struct sip_txsoft *txs; 2383 struct sip_rxsoft *rxs; 2384 struct sip_desc *sipd; 2385 int i, error = 0; 2386 2387 if (!device_has_power(&sc->sc_dev)) 2388 return EBUSY; 2389 2390 /* 2391 * Cancel any pending I/O. 2392 */ 2393 sipcom_stop(ifp, 0); 2394 2395 /* 2396 * Reset the chip to a known state. 2397 */ 2398 if (!sipcom_reset(sc)) 2399 return EBUSY; 2400 2401 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2402 /* 2403 * DP83815 manual, page 78: 2404 * 4.4 Recommended Registers Configuration 2405 * For optimum performance of the DP83815, version noted 2406 * as DP83815CVNG (SRR = 203h), the listed register 2407 * modifications must be followed in sequence... 2408 * 2409 * It's not clear if this should be 302h or 203h because that 2410 * chip name is listed as SRR 302h in the description of the 2411 * SRR register. However, my revision 302h DP83815 on the 2412 * Netgear FA311 purchased in 02/2001 needs these settings 2413 * to avoid tons of errors in AcceptPerfectMatch (non- 2414 * IFF_PROMISC) mode. I do not know if other revisions need 2415 * this set or not. [briggs -- 09 March 2001] 2416 * 2417 * Note that only the low-order 12 bits of 0xe4 are documented 2418 * and that this sets reserved bits in that register. 2419 */ 2420 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2421 2422 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2423 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2424 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2425 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2426 2427 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2428 } 2429 2430 /* 2431 * Initialize the transmit descriptor ring. 2432 */ 2433 for (i = 0; i < sc->sc_ntxdesc; i++) { 2434 sipd = &sc->sc_txdescs[i]; 2435 memset(sipd, 0, sizeof(struct sip_desc)); 2436 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2437 } 2438 SIP_CDTXSYNC(sc, 0, sc->sc_ntxdesc, 2439 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2440 sc->sc_txfree = sc->sc_ntxdesc; 2441 sc->sc_txnext = 0; 2442 sc->sc_txwin = 0; 2443 2444 /* 2445 * Initialize the transmit job descriptors. 2446 */ 2447 SIMPLEQ_INIT(&sc->sc_txfreeq); 2448 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2449 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2450 txs = &sc->sc_txsoft[i]; 2451 txs->txs_mbuf = NULL; 2452 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2453 } 2454 2455 /* 2456 * Initialize the receive descriptor and receive job 2457 * descriptor rings. 2458 */ 2459 for (i = 0; i < sc->sc_nrxdesc; i++) { 2460 rxs = &sc->sc_rxsoft[i]; 2461 if (rxs->rxs_mbuf == NULL) { 2462 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2463 printf("%s: unable to allocate or map rx " 2464 "buffer %d, error = %d\n", 2465 sc->sc_dev.dv_xname, i, error); 2466 /* 2467 * XXX Should attempt to run with fewer receive 2468 * XXX buffers instead of just failing. 2469 */ 2470 sipcom_rxdrain(sc); 2471 goto out; 2472 } 2473 } else 2474 SIP_INIT_RXDESC(sc, i); 2475 } 2476 sc->sc_rxptr = 0; 2477 sc->sc_rxdiscard = 0; 2478 SIP_RXCHAIN_RESET(sc); 2479 2480 /* 2481 * Set the configuration register; it's already initialized 2482 * in sip_attach(). 2483 */ 2484 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2485 2486 /* 2487 * Initialize the prototype TXCFG register. 2488 */ 2489 if (sc->sc_gigabit) { 2490 sc->sc_txcfg = TXCFG_MXDMA_512; 2491 sc->sc_rxcfg = RXCFG_MXDMA_512; 2492 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2493 SIP_SIS900_REV(sc, SIS_REV_960) || 2494 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2495 (sc->sc_cfg & CFG_EDBMASTEN)) { 2496 sc->sc_txcfg = TXCFG_MXDMA_64; 2497 sc->sc_rxcfg = RXCFG_MXDMA_64; 2498 } else { 2499 sc->sc_txcfg = TXCFG_MXDMA_512; 2500 sc->sc_rxcfg = RXCFG_MXDMA_512; 2501 } 2502 2503 sc->sc_txcfg |= TXCFG_ATP | 2504 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2505 sc->sc_tx_drain_thresh; 2506 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2507 2508 /* 2509 * Initialize the receive drain threshold if we have never 2510 * done so. 2511 */ 2512 if (sc->sc_rx_drain_thresh == 0) { 2513 /* 2514 * XXX This value should be tuned. This is set to the 2515 * maximum of 248 bytes, and we may be able to improve 2516 * performance by decreasing it (although we should never 2517 * set this value lower than 2; 14 bytes are required to 2518 * filter the packet). 2519 */ 2520 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2521 } 2522 2523 /* 2524 * Initialize the prototype RXCFG register. 2525 */ 2526 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2527 /* 2528 * Accept long packets (including FCS) so we can handle 2529 * 802.1q-tagged frames and jumbo frames properly. 2530 */ 2531 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2532 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2533 sc->sc_rxcfg |= RXCFG_ALP; 2534 2535 /* 2536 * Checksum offloading is disabled if the user selects an MTU 2537 * larger than 8109. (FreeBSD says 8152, but there is emperical 2538 * evidence that >8109 does not work on some boards, such as the 2539 * Planex GN-1000TE). 2540 */ 2541 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2542 (ifp->if_capenable & 2543 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2544 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2545 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2546 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2547 "disabled.\n", sc->sc_dev.dv_xname); 2548 ifp->if_capenable &= 2549 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2550 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2551 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2552 ifp->if_csum_flags_tx = 0; 2553 ifp->if_csum_flags_rx = 0; 2554 } 2555 2556 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2557 2558 if (sc->sc_gigabit) 2559 sipcom_dp83820_init(sc, ifp->if_capenable); 2560 2561 /* 2562 * Give the transmit and receive rings to the chip. 2563 */ 2564 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2565 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2566 2567 /* 2568 * Initialize the interrupt mask. 2569 */ 2570 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2571 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2572 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2573 2574 /* Set up the receive filter. */ 2575 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2576 2577 /* 2578 * Tune sc_rx_flow_thresh. 2579 * XXX "More than 8KB" is too short for jumbo frames. 2580 * XXX TODO: Threshold value should be user-settable. 2581 */ 2582 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2583 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2584 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2585 2586 /* 2587 * Set the current media. Do this after initializing the prototype 2588 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2589 * control. 2590 */ 2591 mii_mediachg(&sc->sc_mii); 2592 2593 /* 2594 * Set the interrupt hold-off timer to 100us. 2595 */ 2596 if (sc->sc_gigabit) 2597 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2598 2599 /* 2600 * Enable interrupts. 2601 */ 2602 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2603 2604 /* 2605 * Start the transmit and receive processes. 2606 */ 2607 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2608 2609 /* 2610 * Start the one second MII clock. 2611 */ 2612 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2613 2614 /* 2615 * ...all done! 2616 */ 2617 ifp->if_flags |= IFF_RUNNING; 2618 ifp->if_flags &= ~IFF_OACTIVE; 2619 sc->sc_if_flags = ifp->if_flags; 2620 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2621 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2622 sc->sc_prev.if_capenable = ifp->if_capenable; 2623 2624 out: 2625 if (error) 2626 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2627 return (error); 2628 } 2629 2630 /* 2631 * sip_drain: 2632 * 2633 * Drain the receive queue. 2634 */ 2635 static void 2636 sipcom_rxdrain(struct sip_softc *sc) 2637 { 2638 struct sip_rxsoft *rxs; 2639 int i; 2640 2641 for (i = 0; i < sc->sc_nrxdesc; i++) { 2642 rxs = &sc->sc_rxsoft[i]; 2643 if (rxs->rxs_mbuf != NULL) { 2644 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2645 m_freem(rxs->rxs_mbuf); 2646 rxs->rxs_mbuf = NULL; 2647 } 2648 } 2649 } 2650 2651 /* 2652 * sip_stop: [ ifnet interface function ] 2653 * 2654 * Stop transmission on the interface. 2655 */ 2656 static void 2657 sipcom_stop(struct ifnet *ifp, int disable) 2658 { 2659 struct sip_softc *sc = ifp->if_softc; 2660 bus_space_tag_t st = sc->sc_st; 2661 bus_space_handle_t sh = sc->sc_sh; 2662 struct sip_txsoft *txs; 2663 u_int32_t cmdsts = 0; /* DEBUG */ 2664 2665 /* 2666 * Stop the one second clock. 2667 */ 2668 callout_stop(&sc->sc_tick_ch); 2669 2670 /* Down the MII. */ 2671 mii_down(&sc->sc_mii); 2672 2673 /* 2674 * Disable interrupts. 2675 */ 2676 bus_space_write_4(st, sh, SIP_IER, 0); 2677 2678 /* 2679 * Stop receiver and transmitter. 2680 */ 2681 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2682 2683 /* 2684 * Release any queued transmit buffers. 2685 */ 2686 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2687 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2688 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2689 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2690 CMDSTS_INTR) == 0) 2691 printf("%s: sip_stop: last descriptor does not " 2692 "have INTR bit set\n", sc->sc_dev.dv_xname); 2693 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2694 #ifdef DIAGNOSTIC 2695 if (txs->txs_mbuf == NULL) { 2696 printf("%s: dirty txsoft with no mbuf chain\n", 2697 sc->sc_dev.dv_xname); 2698 panic("sip_stop"); 2699 } 2700 #endif 2701 cmdsts |= /* DEBUG */ 2702 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2703 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2704 m_freem(txs->txs_mbuf); 2705 txs->txs_mbuf = NULL; 2706 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2707 } 2708 2709 if (disable) 2710 sipcom_rxdrain(sc); 2711 2712 /* 2713 * Mark the interface down and cancel the watchdog timer. 2714 */ 2715 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2716 ifp->if_timer = 0; 2717 2718 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2719 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2720 printf("%s: sip_stop: no INTR bits set in dirty tx " 2721 "descriptors\n", sc->sc_dev.dv_xname); 2722 } 2723 2724 /* 2725 * sip_read_eeprom: 2726 * 2727 * Read data from the serial EEPROM. 2728 */ 2729 static void 2730 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2731 u_int16_t *data) 2732 { 2733 bus_space_tag_t st = sc->sc_st; 2734 bus_space_handle_t sh = sc->sc_sh; 2735 u_int16_t reg; 2736 int i, x; 2737 2738 for (i = 0; i < wordcnt; i++) { 2739 /* Send CHIP SELECT. */ 2740 reg = EROMAR_EECS; 2741 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2742 2743 /* Shift in the READ opcode. */ 2744 for (x = 3; x > 0; x--) { 2745 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2746 reg |= EROMAR_EEDI; 2747 else 2748 reg &= ~EROMAR_EEDI; 2749 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2750 bus_space_write_4(st, sh, SIP_EROMAR, 2751 reg | EROMAR_EESK); 2752 delay(4); 2753 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2754 delay(4); 2755 } 2756 2757 /* Shift in address. */ 2758 for (x = 6; x > 0; x--) { 2759 if ((word + i) & (1 << (x - 1))) 2760 reg |= EROMAR_EEDI; 2761 else 2762 reg &= ~EROMAR_EEDI; 2763 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2764 bus_space_write_4(st, sh, SIP_EROMAR, 2765 reg | EROMAR_EESK); 2766 delay(4); 2767 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2768 delay(4); 2769 } 2770 2771 /* Shift out data. */ 2772 reg = EROMAR_EECS; 2773 data[i] = 0; 2774 for (x = 16; x > 0; x--) { 2775 bus_space_write_4(st, sh, SIP_EROMAR, 2776 reg | EROMAR_EESK); 2777 delay(4); 2778 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2779 data[i] |= (1 << (x - 1)); 2780 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2781 delay(4); 2782 } 2783 2784 /* Clear CHIP SELECT. */ 2785 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2786 delay(4); 2787 } 2788 } 2789 2790 /* 2791 * sip_add_rxbuf: 2792 * 2793 * Add a receive buffer to the indicated descriptor. 2794 */ 2795 static int 2796 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2797 { 2798 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2799 struct mbuf *m; 2800 int error; 2801 2802 MGETHDR(m, M_DONTWAIT, MT_DATA); 2803 if (m == NULL) 2804 return (ENOBUFS); 2805 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2806 2807 MCLGET(m, M_DONTWAIT); 2808 if ((m->m_flags & M_EXT) == 0) { 2809 m_freem(m); 2810 return (ENOBUFS); 2811 } 2812 2813 /* XXX I don't believe this is necessary. --dyoung */ 2814 #if 0 || defined(DP83820) 2815 m->m_len = sc->sc_rxbuf_len; 2816 #endif /* DP83820 */ 2817 2818 if (rxs->rxs_mbuf != NULL) 2819 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2820 2821 rxs->rxs_mbuf = m; 2822 2823 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2824 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2825 BUS_DMA_READ|BUS_DMA_NOWAIT); 2826 if (error) { 2827 printf("%s: can't load rx DMA map %d, error = %d\n", 2828 sc->sc_dev.dv_xname, idx, error); 2829 panic("%s", __func__); /* XXX */ 2830 } 2831 2832 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2833 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2834 2835 SIP_INIT_RXDESC(sc, idx); 2836 2837 return (0); 2838 } 2839 2840 /* 2841 * sip_sis900_set_filter: 2842 * 2843 * Set up the receive filter. 2844 */ 2845 static void 2846 sipcom_sis900_set_filter(struct sip_softc *sc) 2847 { 2848 bus_space_tag_t st = sc->sc_st; 2849 bus_space_handle_t sh = sc->sc_sh; 2850 struct ethercom *ec = &sc->sc_ethercom; 2851 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2852 struct ether_multi *enm; 2853 const u_int8_t *cp; 2854 struct ether_multistep step; 2855 u_int32_t crc, mchash[16]; 2856 2857 /* 2858 * Initialize the prototype RFCR. 2859 */ 2860 sc->sc_rfcr = RFCR_RFEN; 2861 if (ifp->if_flags & IFF_BROADCAST) 2862 sc->sc_rfcr |= RFCR_AAB; 2863 if (ifp->if_flags & IFF_PROMISC) { 2864 sc->sc_rfcr |= RFCR_AAP; 2865 goto allmulti; 2866 } 2867 2868 /* 2869 * Set up the multicast address filter by passing all multicast 2870 * addresses through a CRC generator, and then using the high-order 2871 * 6 bits as an index into the 128 bit multicast hash table (only 2872 * the lower 16 bits of each 32 bit multicast hash register are 2873 * valid). The high order bits select the register, while the 2874 * rest of the bits select the bit within the register. 2875 */ 2876 2877 memset(mchash, 0, sizeof(mchash)); 2878 2879 /* 2880 * SiS900 (at least SiS963) requires us to register the address of 2881 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2882 */ 2883 crc = 0x0ed423f9; 2884 2885 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2886 SIP_SIS900_REV(sc, SIS_REV_960) || 2887 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2888 /* Just want the 8 most significant bits. */ 2889 crc >>= 24; 2890 } else { 2891 /* Just want the 7 most significant bits. */ 2892 crc >>= 25; 2893 } 2894 2895 /* Set the corresponding bit in the hash table. */ 2896 mchash[crc >> 4] |= 1 << (crc & 0xf); 2897 2898 ETHER_FIRST_MULTI(step, ec, enm); 2899 while (enm != NULL) { 2900 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2901 /* 2902 * We must listen to a range of multicast addresses. 2903 * For now, just accept all multicasts, rather than 2904 * trying to set only those filter bits needed to match 2905 * the range. (At this time, the only use of address 2906 * ranges is for IP multicast routing, for which the 2907 * range is big enough to require all bits set.) 2908 */ 2909 goto allmulti; 2910 } 2911 2912 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2913 2914 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2915 SIP_SIS900_REV(sc, SIS_REV_960) || 2916 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2917 /* Just want the 8 most significant bits. */ 2918 crc >>= 24; 2919 } else { 2920 /* Just want the 7 most significant bits. */ 2921 crc >>= 25; 2922 } 2923 2924 /* Set the corresponding bit in the hash table. */ 2925 mchash[crc >> 4] |= 1 << (crc & 0xf); 2926 2927 ETHER_NEXT_MULTI(step, enm); 2928 } 2929 2930 ifp->if_flags &= ~IFF_ALLMULTI; 2931 goto setit; 2932 2933 allmulti: 2934 ifp->if_flags |= IFF_ALLMULTI; 2935 sc->sc_rfcr |= RFCR_AAM; 2936 2937 setit: 2938 #define FILTER_EMIT(addr, data) \ 2939 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2940 delay(1); \ 2941 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2942 delay(1) 2943 2944 /* 2945 * Disable receive filter, and program the node address. 2946 */ 2947 cp = CLLADDR(ifp->if_sadl); 2948 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2949 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2950 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2951 2952 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2953 /* 2954 * Program the multicast hash table. 2955 */ 2956 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2957 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2958 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2959 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2960 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2961 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2962 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2963 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2964 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2965 SIP_SIS900_REV(sc, SIS_REV_960) || 2966 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2967 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2968 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2969 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2970 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2971 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2972 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2973 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2974 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2975 } 2976 } 2977 #undef FILTER_EMIT 2978 2979 /* 2980 * Re-enable the receiver filter. 2981 */ 2982 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2983 } 2984 2985 /* 2986 * sip_dp83815_set_filter: 2987 * 2988 * Set up the receive filter. 2989 */ 2990 static void 2991 sipcom_dp83815_set_filter(struct sip_softc *sc) 2992 { 2993 bus_space_tag_t st = sc->sc_st; 2994 bus_space_handle_t sh = sc->sc_sh; 2995 struct ethercom *ec = &sc->sc_ethercom; 2996 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2997 struct ether_multi *enm; 2998 const u_int8_t *cp; 2999 struct ether_multistep step; 3000 u_int32_t crc, hash, slot, bit; 3001 #define MCHASH_NWORDS_83820 128 3002 #define MCHASH_NWORDS_83815 32 3003 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3004 u_int16_t mchash[MCHASH_NWORDS]; 3005 int i; 3006 3007 /* 3008 * Initialize the prototype RFCR. 3009 * Enable the receive filter, and accept on 3010 * Perfect (destination address) Match 3011 * If IFF_BROADCAST, also accept all broadcast packets. 3012 * If IFF_PROMISC, accept all unicast packets (and later, set 3013 * IFF_ALLMULTI and accept all multicast, too). 3014 */ 3015 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3016 if (ifp->if_flags & IFF_BROADCAST) 3017 sc->sc_rfcr |= RFCR_AAB; 3018 if (ifp->if_flags & IFF_PROMISC) { 3019 sc->sc_rfcr |= RFCR_AAP; 3020 goto allmulti; 3021 } 3022 3023 /* 3024 * Set up the DP83820/DP83815 multicast address filter by 3025 * passing all multicast addresses through a CRC generator, 3026 * and then using the high-order 11/9 bits as an index into 3027 * the 2048/512 bit multicast hash table. The high-order 3028 * 7/5 bits select the slot, while the low-order 4 bits 3029 * select the bit within the slot. Note that only the low 3030 * 16-bits of each filter word are used, and there are 3031 * 128/32 filter words. 3032 */ 3033 3034 memset(mchash, 0, sizeof(mchash)); 3035 3036 ifp->if_flags &= ~IFF_ALLMULTI; 3037 ETHER_FIRST_MULTI(step, ec, enm); 3038 if (enm == NULL) 3039 goto setit; 3040 while (enm != NULL) { 3041 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3042 /* 3043 * We must listen to a range of multicast addresses. 3044 * For now, just accept all multicasts, rather than 3045 * trying to set only those filter bits needed to match 3046 * the range. (At this time, the only use of address 3047 * ranges is for IP multicast routing, for which the 3048 * range is big enough to require all bits set.) 3049 */ 3050 goto allmulti; 3051 } 3052 3053 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3054 3055 if (sc->sc_gigabit) { 3056 /* Just want the 11 most significant bits. */ 3057 hash = crc >> 21; 3058 } else { 3059 /* Just want the 9 most significant bits. */ 3060 hash = crc >> 23; 3061 } 3062 3063 slot = hash >> 4; 3064 bit = hash & 0xf; 3065 3066 /* Set the corresponding bit in the hash table. */ 3067 mchash[slot] |= 1 << bit; 3068 3069 ETHER_NEXT_MULTI(step, enm); 3070 } 3071 sc->sc_rfcr |= RFCR_MHEN; 3072 goto setit; 3073 3074 allmulti: 3075 ifp->if_flags |= IFF_ALLMULTI; 3076 sc->sc_rfcr |= RFCR_AAM; 3077 3078 setit: 3079 #define FILTER_EMIT(addr, data) \ 3080 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3081 delay(1); \ 3082 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3083 delay(1) 3084 3085 /* 3086 * Disable receive filter, and program the node address. 3087 */ 3088 cp = CLLADDR(ifp->if_sadl); 3089 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3090 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3091 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3092 3093 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3094 int nwords = 3095 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3096 /* 3097 * Program the multicast hash table. 3098 */ 3099 for (i = 0; i < nwords; i++) { 3100 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3101 mchash[i]); 3102 } 3103 } 3104 #undef FILTER_EMIT 3105 #undef MCHASH_NWORDS 3106 #undef MCHASH_NWORDS_83815 3107 #undef MCHASH_NWORDS_83820 3108 3109 /* 3110 * Re-enable the receiver filter. 3111 */ 3112 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3113 } 3114 3115 /* 3116 * sip_dp83820_mii_readreg: [mii interface function] 3117 * 3118 * Read a PHY register on the MII of the DP83820. 3119 */ 3120 static int 3121 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3122 { 3123 struct sip_softc *sc = (void *) self; 3124 3125 if (sc->sc_cfg & CFG_TBI_EN) { 3126 bus_addr_t tbireg; 3127 int rv; 3128 3129 if (phy != 0) 3130 return (0); 3131 3132 switch (reg) { 3133 case MII_BMCR: tbireg = SIP_TBICR; break; 3134 case MII_BMSR: tbireg = SIP_TBISR; break; 3135 case MII_ANAR: tbireg = SIP_TANAR; break; 3136 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3137 case MII_ANER: tbireg = SIP_TANER; break; 3138 case MII_EXTSR: 3139 /* 3140 * Don't even bother reading the TESR register. 3141 * The manual documents that the device has 3142 * 1000baseX full/half capability, but the 3143 * register itself seems read back 0 on some 3144 * boards. Just hard-code the result. 3145 */ 3146 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3147 3148 default: 3149 return (0); 3150 } 3151 3152 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3153 if (tbireg == SIP_TBISR) { 3154 /* LINK and ACOMP are switched! */ 3155 int val = rv; 3156 3157 rv = 0; 3158 if (val & TBISR_MR_LINK_STATUS) 3159 rv |= BMSR_LINK; 3160 if (val & TBISR_MR_AN_COMPLETE) 3161 rv |= BMSR_ACOMP; 3162 3163 /* 3164 * The manual claims this register reads back 0 3165 * on hard and soft reset. But we want to let 3166 * the gentbi driver know that we support auto- 3167 * negotiation, so hard-code this bit in the 3168 * result. 3169 */ 3170 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3171 } 3172 3173 return (rv); 3174 } 3175 3176 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3177 } 3178 3179 /* 3180 * sip_dp83820_mii_writereg: [mii interface function] 3181 * 3182 * Write a PHY register on the MII of the DP83820. 3183 */ 3184 static void 3185 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3186 { 3187 struct sip_softc *sc = (void *) self; 3188 3189 if (sc->sc_cfg & CFG_TBI_EN) { 3190 bus_addr_t tbireg; 3191 3192 if (phy != 0) 3193 return; 3194 3195 switch (reg) { 3196 case MII_BMCR: tbireg = SIP_TBICR; break; 3197 case MII_ANAR: tbireg = SIP_TANAR; break; 3198 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3199 default: 3200 return; 3201 } 3202 3203 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3204 return; 3205 } 3206 3207 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3208 } 3209 3210 /* 3211 * sip_dp83820_mii_statchg: [mii interface function] 3212 * 3213 * Callback from MII layer when media changes. 3214 */ 3215 static void 3216 sipcom_dp83820_mii_statchg(struct device *self) 3217 { 3218 struct sip_softc *sc = (struct sip_softc *) self; 3219 struct mii_data *mii = &sc->sc_mii; 3220 u_int32_t cfg, pcr; 3221 3222 /* 3223 * Get flow control negotiation result. 3224 */ 3225 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3226 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3227 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3228 mii->mii_media_active &= ~IFM_ETH_FMASK; 3229 } 3230 3231 /* 3232 * Update TXCFG for full-duplex operation. 3233 */ 3234 if ((mii->mii_media_active & IFM_FDX) != 0) 3235 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3236 else 3237 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3238 3239 /* 3240 * Update RXCFG for full-duplex or loopback. 3241 */ 3242 if ((mii->mii_media_active & IFM_FDX) != 0 || 3243 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3244 sc->sc_rxcfg |= RXCFG_ATX; 3245 else 3246 sc->sc_rxcfg &= ~RXCFG_ATX; 3247 3248 /* 3249 * Update CFG for MII/GMII. 3250 */ 3251 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3252 cfg = sc->sc_cfg | CFG_MODE_1000; 3253 else 3254 cfg = sc->sc_cfg; 3255 3256 /* 3257 * 802.3x flow control. 3258 */ 3259 pcr = 0; 3260 if (sc->sc_flowflags & IFM_FLOW) { 3261 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3262 pcr |= sc->sc_rx_flow_thresh; 3263 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3264 pcr |= PCR_PSEN | PCR_PS_MCAST; 3265 } 3266 3267 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3268 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3269 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3270 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3271 } 3272 3273 /* 3274 * sip_mii_bitbang_read: [mii bit-bang interface function] 3275 * 3276 * Read the MII serial port for the MII bit-bang module. 3277 */ 3278 static u_int32_t 3279 sipcom_mii_bitbang_read(struct device *self) 3280 { 3281 struct sip_softc *sc = (void *) self; 3282 3283 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3284 } 3285 3286 /* 3287 * sip_mii_bitbang_write: [mii big-bang interface function] 3288 * 3289 * Write the MII serial port for the MII bit-bang module. 3290 */ 3291 static void 3292 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3293 { 3294 struct sip_softc *sc = (void *) self; 3295 3296 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3297 } 3298 3299 /* 3300 * sip_sis900_mii_readreg: [mii interface function] 3301 * 3302 * Read a PHY register on the MII. 3303 */ 3304 static int 3305 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3306 { 3307 struct sip_softc *sc = (struct sip_softc *) self; 3308 u_int32_t enphy; 3309 3310 /* 3311 * The PHY of recent SiS chipsets is accessed through bitbang 3312 * operations. 3313 */ 3314 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3315 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3316 phy, reg); 3317 3318 #ifndef SIS900_MII_RESTRICT 3319 /* 3320 * The SiS 900 has only an internal PHY on the MII. Only allow 3321 * MII address 0. 3322 */ 3323 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3324 return (0); 3325 #endif 3326 3327 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3328 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3329 ENPHY_RWCMD | ENPHY_ACCESS); 3330 do { 3331 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3332 } while (enphy & ENPHY_ACCESS); 3333 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3334 } 3335 3336 /* 3337 * sip_sis900_mii_writereg: [mii interface function] 3338 * 3339 * Write a PHY register on the MII. 3340 */ 3341 static void 3342 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3343 { 3344 struct sip_softc *sc = (struct sip_softc *) self; 3345 u_int32_t enphy; 3346 3347 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3348 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3349 phy, reg, val); 3350 return; 3351 } 3352 3353 #ifndef SIS900_MII_RESTRICT 3354 /* 3355 * The SiS 900 has only an internal PHY on the MII. Only allow 3356 * MII address 0. 3357 */ 3358 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3359 return; 3360 #endif 3361 3362 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3363 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3364 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3365 do { 3366 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3367 } while (enphy & ENPHY_ACCESS); 3368 } 3369 3370 /* 3371 * sip_sis900_mii_statchg: [mii interface function] 3372 * 3373 * Callback from MII layer when media changes. 3374 */ 3375 static void 3376 sipcom_sis900_mii_statchg(struct device *self) 3377 { 3378 struct sip_softc *sc = (struct sip_softc *) self; 3379 struct mii_data *mii = &sc->sc_mii; 3380 u_int32_t flowctl; 3381 3382 /* 3383 * Get flow control negotiation result. 3384 */ 3385 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3386 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3387 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3388 mii->mii_media_active &= ~IFM_ETH_FMASK; 3389 } 3390 3391 /* 3392 * Update TXCFG for full-duplex operation. 3393 */ 3394 if ((mii->mii_media_active & IFM_FDX) != 0) 3395 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3396 else 3397 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3398 3399 /* 3400 * Update RXCFG for full-duplex or loopback. 3401 */ 3402 if ((mii->mii_media_active & IFM_FDX) != 0 || 3403 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3404 sc->sc_rxcfg |= RXCFG_ATX; 3405 else 3406 sc->sc_rxcfg &= ~RXCFG_ATX; 3407 3408 /* 3409 * Update IMR for use of 802.3x flow control. 3410 */ 3411 if (sc->sc_flowflags & IFM_FLOW) { 3412 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3413 flowctl = FLOWCTL_FLOWEN; 3414 } else { 3415 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3416 flowctl = 0; 3417 } 3418 3419 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3420 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3423 } 3424 3425 /* 3426 * sip_dp83815_mii_readreg: [mii interface function] 3427 * 3428 * Read a PHY register on the MII. 3429 */ 3430 static int 3431 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3432 { 3433 struct sip_softc *sc = (struct sip_softc *) self; 3434 u_int32_t val; 3435 3436 /* 3437 * The DP83815 only has an internal PHY. Only allow 3438 * MII address 0. 3439 */ 3440 if (phy != 0) 3441 return (0); 3442 3443 /* 3444 * Apparently, after a reset, the DP83815 can take a while 3445 * to respond. During this recovery period, the BMSR returns 3446 * a value of 0. Catch this -- it's not supposed to happen 3447 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3448 * PHY to come back to life. 3449 * 3450 * This works out because the BMSR is the first register 3451 * read during the PHY probe process. 3452 */ 3453 do { 3454 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3455 } while (reg == MII_BMSR && val == 0); 3456 3457 return (val & 0xffff); 3458 } 3459 3460 /* 3461 * sip_dp83815_mii_writereg: [mii interface function] 3462 * 3463 * Write a PHY register to the MII. 3464 */ 3465 static void 3466 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3467 { 3468 struct sip_softc *sc = (struct sip_softc *) self; 3469 3470 /* 3471 * The DP83815 only has an internal PHY. Only allow 3472 * MII address 0. 3473 */ 3474 if (phy != 0) 3475 return; 3476 3477 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3478 } 3479 3480 /* 3481 * sip_dp83815_mii_statchg: [mii interface function] 3482 * 3483 * Callback from MII layer when media changes. 3484 */ 3485 static void 3486 sipcom_dp83815_mii_statchg(struct device *self) 3487 { 3488 struct sip_softc *sc = (struct sip_softc *) self; 3489 3490 /* 3491 * Update TXCFG for full-duplex operation. 3492 */ 3493 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3494 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3495 else 3496 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3497 3498 /* 3499 * Update RXCFG for full-duplex or loopback. 3500 */ 3501 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3502 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3503 sc->sc_rxcfg |= RXCFG_ATX; 3504 else 3505 sc->sc_rxcfg &= ~RXCFG_ATX; 3506 3507 /* 3508 * XXX 802.3x flow control. 3509 */ 3510 3511 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3512 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3513 3514 /* 3515 * Some DP83815s experience problems when used with short 3516 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3517 * sequence adjusts the DSP's signal attenuation to fix the 3518 * problem. 3519 */ 3520 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3521 uint32_t reg; 3522 3523 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3524 3525 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3526 reg &= 0x0fff; 3527 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3528 delay(100); 3529 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3530 reg &= 0x00ff; 3531 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3532 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3533 0x00e8); 3534 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3535 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3536 reg | 0x20); 3537 } 3538 3539 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3540 } 3541 } 3542 3543 static void 3544 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3545 const struct pci_attach_args *pa, u_int8_t *enaddr) 3546 { 3547 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3548 u_int8_t cksum, *e, match; 3549 int i; 3550 3551 /* 3552 * EEPROM data format for the DP83820 can be found in 3553 * the DP83820 manual, section 4.2.4. 3554 */ 3555 3556 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3557 3558 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3559 match = ~(match - 1); 3560 3561 cksum = 0x55; 3562 e = (u_int8_t *) eeprom_data; 3563 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3564 cksum += *e++; 3565 3566 if (cksum != match) 3567 printf("%s: Checksum (%x) mismatch (%x)", 3568 sc->sc_dev.dv_xname, cksum, match); 3569 3570 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3571 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3572 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3573 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3574 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3575 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3576 } 3577 3578 static void 3579 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3580 { 3581 int i; 3582 3583 /* 3584 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3585 * a reason, but I don't know it. 3586 */ 3587 for (i = 0; i < 10; i++) 3588 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3589 } 3590 3591 static void 3592 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3593 const struct pci_attach_args *pa, u_int8_t *enaddr) 3594 { 3595 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3596 3597 switch (sc->sc_rev) { 3598 case SIS_REV_630S: 3599 case SIS_REV_630E: 3600 case SIS_REV_630EA1: 3601 case SIS_REV_630ET: 3602 case SIS_REV_635: 3603 /* 3604 * The MAC address for the on-board Ethernet of 3605 * the SiS 630 chipset is in the NVRAM. Kick 3606 * the chip into re-loading it from NVRAM, and 3607 * read the MAC address out of the filter registers. 3608 */ 3609 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3610 3611 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3612 RFCR_RFADDR_NODE0); 3613 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3614 0xffff; 3615 3616 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3617 RFCR_RFADDR_NODE2); 3618 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3619 0xffff; 3620 3621 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3622 RFCR_RFADDR_NODE4); 3623 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3624 0xffff; 3625 break; 3626 3627 case SIS_REV_960: 3628 { 3629 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3630 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3631 3632 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3633 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3634 3635 int waittime, i; 3636 3637 /* Allow to read EEPROM from LAN. It is shared 3638 * between a 1394 controller and the NIC and each 3639 * time we access it, we need to set SIS_EECMD_REQ. 3640 */ 3641 SIS_SET_EROMAR(sc, EROMAR_REQ); 3642 3643 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3644 /* Force EEPROM to idle state. */ 3645 3646 /* 3647 * XXX-cube This is ugly. I'll look for docs about it. 3648 */ 3649 SIS_SET_EROMAR(sc, EROMAR_EECS); 3650 sipcom_sis900_eeprom_delay(sc); 3651 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3652 SIS_SET_EROMAR(sc, EROMAR_EESK); 3653 sipcom_sis900_eeprom_delay(sc); 3654 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3655 sipcom_sis900_eeprom_delay(sc); 3656 } 3657 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3658 sipcom_sis900_eeprom_delay(sc); 3659 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3660 3661 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3662 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3663 sizeof(myea) / sizeof(myea[0]), myea); 3664 break; 3665 } 3666 DELAY(1); 3667 } 3668 3669 /* 3670 * Set SIS_EECTL_CLK to high, so a other master 3671 * can operate on the i2c bus. 3672 */ 3673 SIS_SET_EROMAR(sc, EROMAR_EESK); 3674 3675 /* Refuse EEPROM access by LAN */ 3676 SIS_SET_EROMAR(sc, EROMAR_DONE); 3677 } break; 3678 3679 default: 3680 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3681 sizeof(myea) / sizeof(myea[0]), myea); 3682 } 3683 3684 enaddr[0] = myea[0] & 0xff; 3685 enaddr[1] = myea[0] >> 8; 3686 enaddr[2] = myea[1] & 0xff; 3687 enaddr[3] = myea[1] >> 8; 3688 enaddr[4] = myea[2] & 0xff; 3689 enaddr[5] = myea[2] >> 8; 3690 } 3691 3692 /* Table and macro to bit-reverse an octet. */ 3693 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3694 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3695 3696 static void 3697 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3698 const struct pci_attach_args *pa, u_int8_t *enaddr) 3699 { 3700 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3701 u_int8_t cksum, *e, match; 3702 int i; 3703 3704 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3705 sizeof(eeprom_data[0]), eeprom_data); 3706 3707 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3708 match = ~(match - 1); 3709 3710 cksum = 0x55; 3711 e = (u_int8_t *) eeprom_data; 3712 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3713 cksum += *e++; 3714 } 3715 if (cksum != match) { 3716 printf("%s: Checksum (%x) mismatch (%x)", 3717 sc->sc_dev.dv_xname, cksum, match); 3718 } 3719 3720 /* 3721 * Unrolled because it makes slightly more sense this way. 3722 * The DP83815 stores the MAC address in bit 0 of word 6 3723 * through bit 15 of word 8. 3724 */ 3725 ea = &eeprom_data[6]; 3726 enaddr[0] = ((*ea & 0x1) << 7); 3727 ea++; 3728 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3729 enaddr[1] = ((*ea & 0x1FE) >> 1); 3730 enaddr[2] = ((*ea & 0x1) << 7); 3731 ea++; 3732 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3733 enaddr[3] = ((*ea & 0x1FE) >> 1); 3734 enaddr[4] = ((*ea & 0x1) << 7); 3735 ea++; 3736 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3737 enaddr[5] = ((*ea & 0x1FE) >> 1); 3738 3739 /* 3740 * In case that's not weird enough, we also need to reverse 3741 * the bits in each byte. This all actually makes more sense 3742 * if you think about the EEPROM storage as an array of bits 3743 * being shifted into bytes, but that's not how we're looking 3744 * at it here... 3745 */ 3746 for (i = 0; i < 6 ;i++) 3747 enaddr[i] = bbr(enaddr[i]); 3748 } 3749 3750 /* 3751 * sip_mediastatus: [ifmedia interface function] 3752 * 3753 * Get the current interface media status. 3754 */ 3755 static void 3756 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3757 { 3758 struct sip_softc *sc = ifp->if_softc; 3759 3760 mii_pollstat(&sc->sc_mii); 3761 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3762 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3763 sc->sc_flowflags; 3764 } 3765 3766 /* 3767 * sip_mediachange: [ifmedia interface function] 3768 * 3769 * Set hardware to newly-selected media. 3770 */ 3771 static int 3772 sipcom_mediachange(struct ifnet *ifp) 3773 { 3774 struct sip_softc *sc = ifp->if_softc; 3775 3776 if (ifp->if_flags & IFF_UP) 3777 mii_mediachg(&sc->sc_mii); 3778 return (0); 3779 } 3780
Indexes created Tue Sep 30 11:09:46 GMT 2025