if_sip.c revision 1.118
1 /* $NetBSD: if_sip.c,v 1.118 2007/12/14 08:14:27 dogcow Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.118 2007/12/14 08:14:27 dogcow Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 #ifdef DP83820 /* DP83820 Gigabit Ethernet */ 130 #define SIP_DECL(x) __CONCAT(gsip_,x) 131 #else /* SiS900 and DP83815 */ 132 #define SIP_DECL(x) __CONCAT(sip_,x) 133 #endif 134 135 /* 136 * Transmit descriptor list size. This is arbitrary, but allocate 137 * enough descriptors for 128 pending transmissions, and 8 segments 138 * per packet (64 for DP83820 for jumbo frames). 139 * 140 * This MUST work out to a power of 2. 141 */ 142 #define GSIP_NTXSEGS_ALLOC 16 143 #define SIP_NTXSEGS_ALLOC 8 144 145 #define SIP_TXQUEUELEN 256 146 #define MAX_SIP_NTXDESC \ 147 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 148 149 /* 150 * Receive descriptor list size. We have one Rx buffer per incoming 151 * packet, so this logic is a little simpler. 152 * 153 * Actually, on the DP83820, we allow the packet to consume more than 154 * one buffer, in order to support jumbo Ethernet frames. In that 155 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 156 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 157 * so we'd better be quick about handling receive interrupts. 158 */ 159 #define GSIP_NRXDESC 256 160 #define SIP_NRXDESC 128 161 162 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 163 164 /* 165 * Control structures are DMA'd to the SiS900 chip. We allocate them in 166 * a single clump that maps to a single DMA segment to make several things 167 * easier. 168 */ 169 struct sip_control_data { 170 /* 171 * The transmit descriptors. 172 */ 173 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 174 175 /* 176 * The receive descriptors. 177 */ 178 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 179 }; 180 181 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 182 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 183 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 184 185 /* 186 * Software state for transmit jobs. 187 */ 188 struct sip_txsoft { 189 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t txs_dmamap; /* our DMA map */ 191 int txs_firstdesc; /* first descriptor in packet */ 192 int txs_lastdesc; /* last descriptor in packet */ 193 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 194 }; 195 196 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 197 198 /* 199 * Software state for receive jobs. 200 */ 201 struct sip_rxsoft { 202 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 203 bus_dmamap_t rxs_dmamap; /* our DMA map */ 204 }; 205 206 enum sip_attach_stage { 207 SIP_ATTACH_FIN = 0 208 , SIP_ATTACH_CREATE_RXMAP 209 , SIP_ATTACH_CREATE_TXMAP 210 , SIP_ATTACH_LOAD_MAP 211 , SIP_ATTACH_CREATE_MAP 212 , SIP_ATTACH_MAP_MEM 213 , SIP_ATTACH_ALLOC_MEM 214 , SIP_ATTACH_BEGIN 215 }; 216 217 /* 218 * Software state per device. 219 */ 220 struct sip_softc { 221 struct device sc_dev; /* generic device information */ 222 bus_space_tag_t sc_st; /* bus space tag */ 223 bus_space_handle_t sc_sh; /* bus space handle */ 224 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 225 pci_chipset_tag_t sc_pc; 226 bus_dma_segment_t sc_seg; 227 struct ethercom sc_ethercom; /* ethernet common data */ 228 void *sc_sdhook; /* shutdown hook */ 229 230 const struct sip_product *sc_model; /* which model are we? */ 231 int sc_gigabit; /* 1: 83820, 0: other */ 232 int sc_rev; /* chip revision */ 233 234 void *sc_ih; /* interrupt cookie */ 235 236 struct mii_data sc_mii; /* MII/media information */ 237 238 callout_t sc_tick_ch; /* tick callout */ 239 240 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 241 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 242 243 /* 244 * Software state for transmit and receive descriptors. 245 */ 246 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 247 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 248 249 /* 250 * Control data structures. 251 */ 252 struct sip_control_data *sc_control_data; 253 #define sc_txdescs sc_control_data->scd_txdescs 254 #define sc_rxdescs sc_control_data->scd_rxdescs 255 256 #ifdef SIP_EVENT_COUNTERS 257 /* 258 * Event counters. 259 */ 260 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 261 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 262 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 263 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 264 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 265 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 266 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 267 struct evcnt sc_ev_rxpause; /* PAUSE received */ 268 /* DP83820 only */ 269 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 270 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 271 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 272 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 273 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 274 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 275 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 276 #endif /* SIP_EVENT_COUNTERS */ 277 278 u_int32_t sc_txcfg; /* prototype TXCFG register */ 279 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 280 u_int32_t sc_imr; /* prototype IMR register */ 281 u_int32_t sc_rfcr; /* prototype RFCR register */ 282 283 u_int32_t sc_cfg; /* prototype CFG register */ 284 285 u_int32_t sc_gpior; /* prototype GPIOR register */ 286 287 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 288 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 289 290 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 291 292 int sc_flowflags; /* 802.3x flow control flags */ 293 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 294 int sc_paused; /* paused indication */ 295 296 int sc_txfree; /* number of free Tx descriptors */ 297 int sc_txnext; /* next ready Tx descriptor */ 298 int sc_txwin; /* Tx descriptors since last intr */ 299 300 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 301 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 302 303 /* values of interface state at last init */ 304 struct { 305 /* if_capenable */ 306 uint64_t if_capenable; 307 /* ec_capenable */ 308 int ec_capenable; 309 /* VLAN_ATTACHED */ 310 int is_vlan; 311 } sc_prev; 312 313 short sc_if_flags; 314 315 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 316 int sc_rxdiscard; 317 int sc_rxlen; 318 struct mbuf *sc_rxhead; 319 struct mbuf *sc_rxtail; 320 struct mbuf **sc_rxtailp; 321 322 int sc_ntxdesc; 323 int sc_ntxdesc_mask; 324 int sc_ntxsegs; 325 326 int sc_nrxdesc; 327 int sc_nrxdesc_mask; 328 int sc_rxbuf_len; 329 330 #if NRND > 0 331 rndsource_element_t rnd_source; /* random source */ 332 #endif 333 }; 334 335 static inline int 336 sip_nexttx(const struct sip_softc *sc, int x) 337 { 338 return (x + 1) & sc->sc_ntxdesc_mask; 339 } 340 341 static inline int 342 sip_nextrx(const struct sip_softc *sc, int x) 343 { 344 return (x + 1) & sc->sc_nrxdesc_mask; 345 } 346 347 /* 83820 only */ 348 #define SIP_RXCHAIN_RESET(sc) \ 349 do { \ 350 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 351 *(sc)->sc_rxtailp = NULL; \ 352 (sc)->sc_rxlen = 0; \ 353 } while (/*CONSTCOND*/0) 354 355 /* 83820 only */ 356 #define SIP_RXCHAIN_LINK(sc, m) \ 357 do { \ 358 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 359 (sc)->sc_rxtailp = &(m)->m_next; \ 360 } while (/*CONSTCOND*/0) 361 362 #ifdef SIP_EVENT_COUNTERS 363 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 364 #else 365 #define SIP_EVCNT_INCR(ev) /* nothing */ 366 #endif 367 368 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 369 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 370 371 #define SIP_CDTXSYNC(sc, x, n, ops) \ 372 do { \ 373 int __x, __n; \ 374 \ 375 __x = (x); \ 376 __n = (n); \ 377 \ 378 /* If it will wrap around, sync to the end of the ring. */ \ 379 if ((__x + __n) > sc->sc_ntxdesc) { \ 380 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 381 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 382 (sc->sc_ntxdesc - __x), (ops)); \ 383 __n -= (sc->sc_ntxdesc - __x); \ 384 __x = 0; \ 385 } \ 386 \ 387 /* Now sync whatever is left. */ \ 388 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 389 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 390 } while (0) 391 392 #define SIP_CDRXSYNC(sc, x, ops) \ 393 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 394 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 395 396 static inline void 397 SIP_INIT_RXDESC(struct sip_softc *sc, int x) 398 { 399 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 400 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 401 402 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 403 sipd->sipd_bufptr = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 404 sipd->sipd_cmdsts = htole32(CMDSTS_INTR | 405 (sc->sc_rxbuf_len & CMDSTS_SIZE_MASK)); 406 sipd->sipd_extsts = 0; 407 SIP_CDRXSYNC(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 408 } 409 410 #define SIP_CHIP_VERS(sc, v, p, r) \ 411 ((sc)->sc_model->sip_vendor == (v) && \ 412 (sc)->sc_model->sip_product == (p) && \ 413 (sc)->sc_rev == (r)) 414 415 #define SIP_CHIP_MODEL(sc, v, p) \ 416 ((sc)->sc_model->sip_vendor == (v) && \ 417 (sc)->sc_model->sip_product == (p)) 418 419 #define SIP_SIS900_REV(sc, rev) \ 420 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 421 422 #define SIP_TIMEOUT 1000 423 424 static void sipcom_start(struct ifnet *); 425 static void sipcom_watchdog(struct ifnet *); 426 static int sipcom_ioctl(struct ifnet *, u_long, void *); 427 static int sipcom_init(struct ifnet *); 428 static void sipcom_stop(struct ifnet *, int); 429 430 static void sipcom_shutdown(void *); 431 432 static bool sipcom_reset(struct sip_softc *); 433 static void sipcom_rxdrain(struct sip_softc *); 434 static int SIP_DECL(add_rxbuf)(struct sip_softc *, int); 435 static void sipcom_read_eeprom(struct sip_softc *, int, int, 436 u_int16_t *); 437 static void sipcom_tick(void *); 438 439 static void sipcom_sis900_set_filter(struct sip_softc *); 440 static void sipcom_dp83815_set_filter(struct sip_softc *); 441 442 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 443 const struct pci_attach_args *, u_int8_t *); 444 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 445 static void sipcom_sis900_read_macaddr(struct sip_softc *, 446 const struct pci_attach_args *, u_int8_t *); 447 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 448 const struct pci_attach_args *, u_int8_t *); 449 450 static int sipcom_intr(void *); 451 static void sipcom_txintr(struct sip_softc *); 452 static void SIP_DECL(rxintr)(struct sip_softc *); 453 454 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 455 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 456 static void sipcom_dp83820_mii_statchg(struct device *); 457 458 static int sipcom_sis900_mii_readreg(struct device *, int, int); 459 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 460 static void sipcom_sis900_mii_statchg(struct device *); 461 462 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 463 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 464 static void sipcom_dp83815_mii_statchg(struct device *); 465 466 static int sipcom_mediachange(struct ifnet *); 467 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 468 469 static int sipcom_match(struct device *, struct cfdata *, void *); 470 static void sipcom_attach(struct device *, struct device *, void *); 471 static void sipcom_do_detach(device_t, enum sip_attach_stage); 472 static int sipcom_detach(device_t, int); 473 static bool sipcom_resume(device_t); 474 475 int SIP_DECL(copy_small) = 0; 476 477 #ifdef DP83820 478 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 479 sipcom_match, sipcom_attach, sipcom_detach, NULL); 480 #else 481 CFATTACH_DECL(sip, sizeof(struct sip_softc), 482 sipcom_match, sipcom_attach, sipcom_detach, NULL); 483 #endif 484 485 /* 486 * Descriptions of the variants of the SiS900. 487 */ 488 struct sip_variant { 489 int (*sipv_mii_readreg)(struct device *, int, int); 490 void (*sipv_mii_writereg)(struct device *, int, int, int); 491 void (*sipv_mii_statchg)(struct device *); 492 void (*sipv_set_filter)(struct sip_softc *); 493 void (*sipv_read_macaddr)(struct sip_softc *, 494 const struct pci_attach_args *, u_int8_t *); 495 }; 496 497 static u_int32_t sipcom_mii_bitbang_read(struct device *); 498 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 499 500 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 501 sipcom_mii_bitbang_read, 502 sipcom_mii_bitbang_write, 503 { 504 EROMAR_MDIO, /* MII_BIT_MDO */ 505 EROMAR_MDIO, /* MII_BIT_MDI */ 506 EROMAR_MDC, /* MII_BIT_MDC */ 507 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 508 0, /* MII_BIT_DIR_PHY_HOST */ 509 } 510 }; 511 512 static const struct sip_variant sipcom_variant_dp83820 = { 513 sipcom_dp83820_mii_readreg, 514 sipcom_dp83820_mii_writereg, 515 sipcom_dp83820_mii_statchg, 516 sipcom_dp83815_set_filter, 517 sipcom_dp83820_read_macaddr, 518 }; 519 520 static const struct sip_variant sipcom_variant_sis900 = { 521 sipcom_sis900_mii_readreg, 522 sipcom_sis900_mii_writereg, 523 sipcom_sis900_mii_statchg, 524 sipcom_sis900_set_filter, 525 sipcom_sis900_read_macaddr, 526 }; 527 528 static const struct sip_variant sipcom_variant_dp83815 = { 529 sipcom_dp83815_mii_readreg, 530 sipcom_dp83815_mii_writereg, 531 sipcom_dp83815_mii_statchg, 532 sipcom_dp83815_set_filter, 533 sipcom_dp83815_read_macaddr, 534 }; 535 536 537 /* 538 * Devices supported by this driver. 539 */ 540 static const struct sip_product { 541 pci_vendor_id_t sip_vendor; 542 pci_product_id_t sip_product; 543 const char *sip_name; 544 const struct sip_variant *sip_variant; 545 const int sip_gigabit; 546 } sipcom_products[] = { 547 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 548 "NatSemi DP83820 Gigabit Ethernet", 549 &sipcom_variant_dp83820, 1 }, 550 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 551 "SiS 900 10/100 Ethernet", 552 &sipcom_variant_sis900, 0 }, 553 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 554 "SiS 7016 10/100 Ethernet", 555 &sipcom_variant_sis900, 0 }, 556 557 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 558 "NatSemi DP83815 10/100 Ethernet", 559 &sipcom_variant_dp83815, 0 }, 560 561 { 0, 0, 562 NULL, 563 NULL, 0 }, 564 }; 565 566 static const struct sip_product * 567 sipcom_lookup(const struct pci_attach_args *pa) 568 { 569 const struct sip_product *sip; 570 571 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 572 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 573 PCI_PRODUCT(pa->pa_id) == sip->sip_product) 574 return (sip); 575 } 576 return (NULL); 577 } 578 579 /* 580 * I really hate stupid hardware vendors. There's a bit in the EEPROM 581 * which indicates if the card can do 64-bit data transfers. Unfortunately, 582 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 583 * which means we try to use 64-bit data transfers on those cards if we 584 * happen to be plugged into a 32-bit slot. 585 * 586 * What we do is use this table of cards known to be 64-bit cards. If 587 * you have a 64-bit card who's subsystem ID is not listed in this table, 588 * send the output of "pcictl dump ..." of the device to me so that your 589 * card will use the 64-bit data path when plugged into a 64-bit slot. 590 * 591 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 592 * June 30, 2002 593 */ 594 static int 595 sipcom_check_64bit(const struct pci_attach_args *pa) 596 { 597 static const struct { 598 pci_vendor_id_t c64_vendor; 599 pci_product_id_t c64_product; 600 } card64[] = { 601 /* Asante GigaNIX */ 602 { 0x128a, 0x0002 }, 603 604 /* Accton EN1407-T, Planex GN-1000TE */ 605 { 0x1113, 0x1407 }, 606 607 /* Netgear GA-621 */ 608 { 0x1385, 0x621a }, 609 610 /* SMC EZ Card */ 611 { 0x10b8, 0x9462 }, 612 613 { 0, 0} 614 }; 615 pcireg_t subsys; 616 int i; 617 618 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 619 620 for (i = 0; card64[i].c64_vendor != 0; i++) { 621 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 622 PCI_PRODUCT(subsys) == card64[i].c64_product) 623 return (1); 624 } 625 626 return (0); 627 } 628 629 static int 630 sipcom_match(struct device *parent, struct cfdata *cf, 631 void *aux) 632 { 633 struct pci_attach_args *pa = aux; 634 635 if (sipcom_lookup(pa) != NULL) 636 return (1); 637 638 return (0); 639 } 640 641 static void 642 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 643 { 644 u_int32_t reg; 645 int i; 646 647 /* 648 * Cause the chip to load configuration data from the EEPROM. 649 */ 650 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 651 for (i = 0; i < 10000; i++) { 652 delay(10); 653 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 654 PTSCR_EELOAD_EN) == 0) 655 break; 656 } 657 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 658 PTSCR_EELOAD_EN) { 659 printf("%s: timeout loading configuration from EEPROM\n", 660 sc->sc_dev.dv_xname); 661 return; 662 } 663 664 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 665 666 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 667 if (reg & CFG_PCI64_DET) { 668 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 669 /* 670 * Check to see if this card is 64-bit. If so, enable 64-bit 671 * data transfers. 672 * 673 * We can't use the DATA64_EN bit in the EEPROM, because 674 * vendors of 32-bit cards fail to clear that bit in many 675 * cases (yet the card still detects that it's in a 64-bit 676 * slot; go figure). 677 */ 678 if (sipcom_check_64bit(pa)) { 679 sc->sc_cfg |= CFG_DATA64_EN; 680 printf(", using 64-bit data transfers"); 681 } 682 printf("\n"); 683 } 684 685 /* 686 * XXX Need some PCI flags indicating support for 687 * XXX 64-bit addressing. 688 */ 689 #if 0 690 if (reg & CFG_M64ADDR) 691 sc->sc_cfg |= CFG_M64ADDR; 692 if (reg & CFG_T64ADDR) 693 sc->sc_cfg |= CFG_T64ADDR; 694 #endif 695 696 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 697 const char *sep = ""; 698 printf("%s: using ", sc->sc_dev.dv_xname); 699 if (reg & CFG_EXT_125) { 700 sc->sc_cfg |= CFG_EXT_125; 701 printf("%s125MHz clock", sep); 702 sep = ", "; 703 } 704 if (reg & CFG_TBI_EN) { 705 sc->sc_cfg |= CFG_TBI_EN; 706 printf("%sten-bit interface", sep); 707 sep = ", "; 708 } 709 printf("\n"); 710 } 711 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 712 (reg & CFG_MRM_DIS) != 0) 713 sc->sc_cfg |= CFG_MRM_DIS; 714 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 715 (reg & CFG_MWI_DIS) != 0) 716 sc->sc_cfg |= CFG_MWI_DIS; 717 718 /* 719 * Use the extended descriptor format on the DP83820. This 720 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 721 * checksumming. 722 */ 723 sc->sc_cfg |= CFG_EXTSTS_EN; 724 } 725 726 static int 727 sipcom_detach(device_t self, int flags) 728 { 729 sipcom_do_detach(self, SIP_ATTACH_FIN); 730 return 0; 731 } 732 733 static void 734 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 735 { 736 int i; 737 struct sip_softc *sc = device_private(self); 738 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 739 740 /* 741 * Free any resources we've allocated during attach. 742 * Do this in reverse order and fall through. 743 */ 744 switch (stage) { 745 case SIP_ATTACH_FIN: 746 sipcom_stop(ifp, 1); 747 pmf_device_deregister(self); 748 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 749 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 750 751 if (sc->sc_sdhook != NULL) 752 shutdownhook_disestablish(sc->sc_sdhook); 753 754 /*FALLTHROUGH*/ 755 case SIP_ATTACH_CREATE_RXMAP: 756 for (i = 0; i < sc->sc_nrxdesc; i++) { 757 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 758 bus_dmamap_destroy(sc->sc_dmat, 759 sc->sc_rxsoft[i].rxs_dmamap); 760 } 761 /*FALLTHROUGH*/ 762 case SIP_ATTACH_CREATE_TXMAP: 763 for (i = 0; i < SIP_TXQUEUELEN; i++) { 764 if (sc->sc_txsoft[i].txs_dmamap != NULL) 765 bus_dmamap_destroy(sc->sc_dmat, 766 sc->sc_txsoft[i].txs_dmamap); 767 } 768 /*FALLTHROUGH*/ 769 case SIP_ATTACH_LOAD_MAP: 770 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 771 /*FALLTHROUGH*/ 772 case SIP_ATTACH_CREATE_MAP: 773 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 774 /*FALLTHROUGH*/ 775 case SIP_ATTACH_MAP_MEM: 776 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 777 sizeof(struct sip_control_data)); 778 /*FALLTHROUGH*/ 779 case SIP_ATTACH_ALLOC_MEM: 780 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 781 break; 782 default: 783 break; 784 } 785 return; 786 } 787 788 static bool 789 sipcom_resume(device_t self) 790 { 791 struct sip_softc *sc = device_private(self); 792 793 return sipcom_reset(sc); 794 } 795 796 static void 797 sipcom_attach(struct device *parent, struct device *self, void *aux) 798 { 799 struct sip_softc *sc = (struct sip_softc *) self; 800 struct pci_attach_args *pa = aux; 801 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 802 pci_chipset_tag_t pc = pa->pa_pc; 803 pci_intr_handle_t ih; 804 const char *intrstr = NULL; 805 bus_space_tag_t iot, memt; 806 bus_space_handle_t ioh, memh; 807 int ioh_valid, memh_valid; 808 int i, rseg, error; 809 const struct sip_product *sip; 810 u_int8_t enaddr[ETHER_ADDR_LEN]; 811 pcireg_t pmreg; 812 pcireg_t memtype; 813 bus_size_t tx_dmamap_size; 814 int ntxsegs_alloc; 815 816 callout_init(&sc->sc_tick_ch, 0); 817 818 sip = sipcom_lookup(pa); 819 if (sip == NULL) { 820 printf("\n"); 821 panic("%s: impossible", __func__); 822 } 823 sc->sc_gigabit = sip->sip_gigabit; 824 825 sc->sc_pc = pc; 826 827 if (sc->sc_gigabit) { 828 sc->sc_rxbuf_len = MCLBYTES - 8; 829 tx_dmamap_size = ETHER_MAX_LEN_JUMBO; 830 sc->sc_ntxsegs = 64; 831 ntxsegs_alloc = GSIP_NTXSEGS_ALLOC; 832 sc->sc_nrxdesc = GSIP_NRXDESC; 833 } else { 834 sc->sc_rxbuf_len = MCLBYTES - 1; /* field width */ 835 tx_dmamap_size = MCLBYTES; 836 sc->sc_ntxsegs = 16; 837 ntxsegs_alloc = SIP_NTXSEGS_ALLOC; 838 sc->sc_nrxdesc = SIP_NRXDESC; 839 } 840 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 841 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 842 sc->sc_nrxdesc_mask = sc->sc_nrxdesc - 1; 843 844 sc->sc_rev = PCI_REVISION(pa->pa_class); 845 846 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 847 848 sc->sc_model = sip; 849 850 /* 851 * XXX Work-around broken PXE firmware on some boards. 852 * 853 * The DP83815 shares an address decoder with the MEM BAR 854 * and the ROM BAR. Make sure the ROM BAR is disabled, 855 * so that memory mapped access works. 856 */ 857 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 858 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 859 ~PCI_MAPREG_ROM_ENABLE); 860 861 /* 862 * Map the device. 863 */ 864 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 865 PCI_MAPREG_TYPE_IO, 0, 866 &iot, &ioh, NULL, NULL) == 0); 867 if (sc->sc_gigabit) { 868 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 869 switch (memtype) { 870 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 871 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 872 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 873 memtype, 0, &memt, &memh, NULL, NULL) == 0); 874 break; 875 default: 876 memh_valid = 0; 877 } 878 } else { 879 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 880 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 881 &memt, &memh, NULL, NULL) == 0); 882 } 883 884 if (memh_valid) { 885 sc->sc_st = memt; 886 sc->sc_sh = memh; 887 } else if (ioh_valid) { 888 sc->sc_st = iot; 889 sc->sc_sh = ioh; 890 } else { 891 printf("%s: unable to map device registers\n", 892 sc->sc_dev.dv_xname); 893 return; 894 } 895 896 sc->sc_dmat = pa->pa_dmat; 897 898 /* 899 * Make sure bus mastering is enabled. Also make sure 900 * Write/Invalidate is enabled if we're allowed to use it. 901 */ 902 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 903 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 904 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 905 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 906 pmreg | PCI_COMMAND_MASTER_ENABLE); 907 908 /* power up chip */ 909 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 910 NULL)) && error != EOPNOTSUPP) { 911 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 912 error); 913 return; 914 } 915 916 /* 917 * Map and establish our interrupt. 918 */ 919 if (pci_intr_map(pa, &ih)) { 920 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 921 return; 922 } 923 intrstr = pci_intr_string(pc, ih); 924 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 925 if (sc->sc_ih == NULL) { 926 printf("%s: unable to establish interrupt", 927 sc->sc_dev.dv_xname); 928 if (intrstr != NULL) 929 printf(" at %s", intrstr); 930 printf("\n"); 931 return; 932 } 933 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 934 935 SIMPLEQ_INIT(&sc->sc_txfreeq); 936 SIMPLEQ_INIT(&sc->sc_txdirtyq); 937 938 /* 939 * Allocate the control data structures, and create and load the 940 * DMA map for it. 941 */ 942 if ((error = bus_dmamem_alloc(sc->sc_dmat, 943 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 944 &rseg, 0)) != 0) { 945 printf("%s: unable to allocate control data, error = %d\n", 946 sc->sc_dev.dv_xname, error); 947 return sipcom_do_detach(self, -1); 948 } 949 950 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 951 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 952 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 953 printf("%s: unable to map control data, error = %d\n", 954 sc->sc_dev.dv_xname, error); 955 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 956 } 957 958 if ((error = bus_dmamap_create(sc->sc_dmat, 959 sizeof(struct sip_control_data), 1, 960 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 961 printf("%s: unable to create control data DMA map, " 962 "error = %d\n", sc->sc_dev.dv_xname, error); 963 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 964 } 965 966 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 967 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 968 0)) != 0) { 969 printf("%s: unable to load control data DMA map, error = %d\n", 970 sc->sc_dev.dv_xname, error); 971 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 972 } 973 974 /* 975 * Create the transmit buffer DMA maps. 976 */ 977 for (i = 0; i < SIP_TXQUEUELEN; i++) { 978 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 979 sc->sc_ntxsegs, MCLBYTES, 0, 0, 980 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 981 printf("%s: unable to create tx DMA map %d, " 982 "error = %d\n", sc->sc_dev.dv_xname, i, error); 983 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 984 } 985 } 986 987 /* 988 * Create the receive buffer DMA maps. 989 */ 990 for (i = 0; i < sc->sc_nrxdesc; i++) { 991 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 992 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 993 printf("%s: unable to create rx DMA map %d, " 994 "error = %d\n", sc->sc_dev.dv_xname, i, error); 995 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 996 } 997 sc->sc_rxsoft[i].rxs_mbuf = NULL; 998 } 999 1000 /* 1001 * Reset the chip to a known state. 1002 */ 1003 sipcom_reset(sc); 1004 1005 /* 1006 * Read the Ethernet address from the EEPROM. This might 1007 * also fetch other stuff from the EEPROM and stash it 1008 * in the softc. 1009 */ 1010 sc->sc_cfg = 0; 1011 if (!sc->sc_gigabit) { 1012 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1013 SIP_SIS900_REV(sc,SIS_REV_900B)) 1014 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1015 1016 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1017 SIP_SIS900_REV(sc,SIS_REV_960) || 1018 SIP_SIS900_REV(sc,SIS_REV_900B)) 1019 sc->sc_cfg |= 1020 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1021 CFG_EDBMASTEN); 1022 } 1023 1024 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1025 1026 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1027 ether_sprintf(enaddr)); 1028 1029 /* 1030 * Initialize the configuration register: aggressive PCI 1031 * bus request algorithm, default backoff, default OW timer, 1032 * default parity error detection. 1033 * 1034 * NOTE: "Big endian mode" is useless on the SiS900 and 1035 * friends -- it affects packet data, not descriptors. 1036 */ 1037 if (sc->sc_gigabit) 1038 sipcom_dp83820_attach(sc, pa); 1039 1040 /* 1041 * Initialize our media structures and probe the MII. 1042 */ 1043 sc->sc_mii.mii_ifp = ifp; 1044 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1045 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1046 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1047 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sipcom_mediachange, 1048 sipcom_mediastatus); 1049 1050 /* 1051 * XXX We cannot handle flow control on the DP83815. 1052 */ 1053 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1054 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1055 MII_OFFSET_ANY, 0); 1056 else 1057 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1058 MII_OFFSET_ANY, MIIF_DOPAUSE); 1059 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1060 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1061 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1062 } else 1063 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1064 1065 ifp = &sc->sc_ethercom.ec_if; 1066 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1067 ifp->if_softc = sc; 1068 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1069 sc->sc_if_flags = ifp->if_flags; 1070 ifp->if_ioctl = sipcom_ioctl; 1071 ifp->if_start = sipcom_start; 1072 ifp->if_watchdog = sipcom_watchdog; 1073 ifp->if_init = sipcom_init; 1074 ifp->if_stop = sipcom_stop; 1075 IFQ_SET_READY(&ifp->if_snd); 1076 1077 /* 1078 * We can support 802.1Q VLAN-sized frames. 1079 */ 1080 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1081 1082 if (sc->sc_gigabit) { 1083 /* 1084 * And the DP83820 can do VLAN tagging in hardware, and 1085 * support the jumbo Ethernet MTU. 1086 */ 1087 sc->sc_ethercom.ec_capabilities |= 1088 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1089 1090 /* 1091 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1092 * in hardware. 1093 */ 1094 ifp->if_capabilities |= 1095 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1096 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1097 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1098 } 1099 1100 /* 1101 * Attach the interface. 1102 */ 1103 if_attach(ifp); 1104 ether_ifattach(ifp, enaddr); 1105 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1106 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1107 sc->sc_prev.if_capenable = ifp->if_capenable; 1108 #if NRND > 0 1109 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1110 RND_TYPE_NET, 0); 1111 #endif 1112 1113 /* 1114 * The number of bytes that must be available in 1115 * the Tx FIFO before the bus master can DMA more 1116 * data into the FIFO. 1117 */ 1118 sc->sc_tx_fill_thresh = 64 / 32; 1119 1120 /* 1121 * Start at a drain threshold of 512 bytes. We will 1122 * increase it if a DMA underrun occurs. 1123 * 1124 * XXX The minimum value of this variable should be 1125 * tuned. We may be able to improve performance 1126 * by starting with a lower value. That, however, 1127 * may trash the first few outgoing packets if the 1128 * PCI bus is saturated. 1129 */ 1130 if (sc->sc_gigabit) 1131 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1132 else 1133 sc->sc_tx_drain_thresh = 1504 / 32; 1134 1135 /* 1136 * Initialize the Rx FIFO drain threshold. 1137 * 1138 * This is in units of 8 bytes. 1139 * 1140 * We should never set this value lower than 2; 14 bytes are 1141 * required to filter the packet. 1142 */ 1143 sc->sc_rx_drain_thresh = 128 / 8; 1144 1145 #ifdef SIP_EVENT_COUNTERS 1146 /* 1147 * Attach event counters. 1148 */ 1149 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1150 NULL, sc->sc_dev.dv_xname, "txsstall"); 1151 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1152 NULL, sc->sc_dev.dv_xname, "txdstall"); 1153 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1154 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1155 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1156 NULL, sc->sc_dev.dv_xname, "txdintr"); 1157 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1158 NULL, sc->sc_dev.dv_xname, "txiintr"); 1159 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1160 NULL, sc->sc_dev.dv_xname, "rxintr"); 1161 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1162 NULL, sc->sc_dev.dv_xname, "hiberr"); 1163 if (!sc->sc_gigabit) { 1164 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1165 NULL, sc->sc_dev.dv_xname, "rxpause"); 1166 } else { 1167 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1168 NULL, sc->sc_dev.dv_xname, "rxpause"); 1169 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1170 NULL, sc->sc_dev.dv_xname, "txpause"); 1171 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1172 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1173 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1174 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1175 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1176 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1177 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1178 NULL, sc->sc_dev.dv_xname, "txipsum"); 1179 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1180 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1181 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1182 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1183 } 1184 #endif /* SIP_EVENT_COUNTERS */ 1185 1186 if (!pmf_device_register(self, NULL, sipcom_resume)) 1187 aprint_error_dev(self, "couldn't establish power handler\n"); 1188 else 1189 pmf_class_network_register(self, ifp); 1190 1191 /* 1192 * Make sure the interface is shutdown during reboot. 1193 */ 1194 sc->sc_sdhook = shutdownhook_establish(sipcom_shutdown, sc); 1195 if (sc->sc_sdhook == NULL) 1196 printf("%s: WARNING: unable to establish shutdown hook\n", 1197 sc->sc_dev.dv_xname); 1198 } 1199 1200 /* 1201 * sip_shutdown: 1202 * 1203 * Make sure the interface is stopped at reboot time. 1204 */ 1205 static void 1206 sipcom_shutdown(void *arg) 1207 { 1208 struct sip_softc *sc = arg; 1209 1210 sipcom_stop(&sc->sc_ethercom.ec_if, 1); 1211 } 1212 1213 static inline void 1214 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1215 uint64_t capenable) 1216 { 1217 struct m_tag *mtag; 1218 u_int32_t extsts; 1219 #ifdef DEBUG 1220 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1221 #endif 1222 /* 1223 * If VLANs are enabled and the packet has a VLAN tag, set 1224 * up the descriptor to encapsulate the packet for us. 1225 * 1226 * This apparently has to be on the last descriptor of 1227 * the packet. 1228 */ 1229 1230 /* 1231 * Byte swapping is tricky. We need to provide the tag 1232 * in a network byte order. On a big-endian machine, 1233 * the byteorder is correct, but we need to swap it 1234 * anyway, because this will be undone by the outside 1235 * htole32(). That's why there must be an 1236 * unconditional swap instead of htons() inside. 1237 */ 1238 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1239 sc->sc_txdescs[lasttx].sipd_extsts |= 1240 htole32(EXTSTS_VPKT | 1241 (bswap16(VLAN_TAG_VALUE(mtag)) & 1242 EXTSTS_VTCI)); 1243 } 1244 1245 /* 1246 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1247 * checksumming, set up the descriptor to do this work 1248 * for us. 1249 * 1250 * This apparently has to be on the first descriptor of 1251 * the packet. 1252 * 1253 * Byte-swap constants so the compiler can optimize. 1254 */ 1255 extsts = 0; 1256 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1257 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1258 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1259 extsts |= htole32(EXTSTS_IPPKT); 1260 } 1261 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1262 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1263 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1264 extsts |= htole32(EXTSTS_TCPPKT); 1265 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1266 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1267 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1268 extsts |= htole32(EXTSTS_UDPPKT); 1269 } 1270 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1271 } 1272 1273 /* 1274 * sip_start: [ifnet interface function] 1275 * 1276 * Start packet transmission on the interface. 1277 */ 1278 static void 1279 sipcom_start(struct ifnet *ifp) 1280 { 1281 struct sip_softc *sc = ifp->if_softc; 1282 struct mbuf *m0; 1283 struct mbuf *m; 1284 struct sip_txsoft *txs; 1285 bus_dmamap_t dmamap; 1286 int error, nexttx, lasttx, seg; 1287 int ofree = sc->sc_txfree; 1288 #if 0 1289 int firsttx = sc->sc_txnext; 1290 #endif 1291 1292 /* 1293 * If we've been told to pause, don't transmit any more packets. 1294 */ 1295 if (!sc->sc_gigabit && sc->sc_paused) 1296 ifp->if_flags |= IFF_OACTIVE; 1297 1298 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1299 return; 1300 1301 /* 1302 * Loop through the send queue, setting up transmit descriptors 1303 * until we drain the queue, or use up all available transmit 1304 * descriptors. 1305 */ 1306 for (;;) { 1307 /* Get a work queue entry. */ 1308 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1309 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1310 break; 1311 } 1312 1313 /* 1314 * Grab a packet off the queue. 1315 */ 1316 IFQ_POLL(&ifp->if_snd, m0); 1317 if (m0 == NULL) 1318 break; 1319 m = NULL; 1320 1321 dmamap = txs->txs_dmamap; 1322 1323 /* 1324 * Load the DMA map. If this fails, the packet either 1325 * didn't fit in the alloted number of segments, or we 1326 * were short on resources. 1327 */ 1328 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1329 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1330 /* In the non-gigabit case, we'll copy and try again. */ 1331 if (error != 0 && !sc->sc_gigabit) { 1332 MGETHDR(m, M_DONTWAIT, MT_DATA); 1333 if (m == NULL) { 1334 printf("%s: unable to allocate Tx mbuf\n", 1335 sc->sc_dev.dv_xname); 1336 break; 1337 } 1338 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1339 if (m0->m_pkthdr.len > MHLEN) { 1340 MCLGET(m, M_DONTWAIT); 1341 if ((m->m_flags & M_EXT) == 0) { 1342 printf("%s: unable to allocate Tx " 1343 "cluster\n", sc->sc_dev.dv_xname); 1344 m_freem(m); 1345 break; 1346 } 1347 } 1348 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1349 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1350 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1351 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1352 if (error) { 1353 printf("%s: unable to load Tx buffer, " 1354 "error = %d\n", sc->sc_dev.dv_xname, error); 1355 break; 1356 } 1357 } else if (error == EFBIG) { 1358 /* 1359 * For the too-many-segments case, we simply 1360 * report an error and drop the packet, 1361 * since we can't sanely copy a jumbo packet 1362 * to a single buffer. 1363 */ 1364 printf("%s: Tx packet consumes too many " 1365 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1366 IFQ_DEQUEUE(&ifp->if_snd, m0); 1367 m_freem(m0); 1368 continue; 1369 } else if (error != 0) { 1370 /* 1371 * Short on resources, just stop for now. 1372 */ 1373 break; 1374 } 1375 1376 /* 1377 * Ensure we have enough descriptors free to describe 1378 * the packet. Note, we always reserve one descriptor 1379 * at the end of the ring as a termination point, to 1380 * prevent wrap-around. 1381 */ 1382 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1383 /* 1384 * Not enough free descriptors to transmit this 1385 * packet. We haven't committed anything yet, 1386 * so just unload the DMA map, put the packet 1387 * back on the queue, and punt. Notify the upper 1388 * layer that there are not more slots left. 1389 * 1390 * XXX We could allocate an mbuf and copy, but 1391 * XXX is it worth it? 1392 */ 1393 ifp->if_flags |= IFF_OACTIVE; 1394 bus_dmamap_unload(sc->sc_dmat, dmamap); 1395 if (m != NULL) 1396 m_freem(m); 1397 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1398 break; 1399 } 1400 1401 IFQ_DEQUEUE(&ifp->if_snd, m0); 1402 if (m != NULL) { 1403 m_freem(m0); 1404 m0 = m; 1405 } 1406 1407 /* 1408 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1409 */ 1410 1411 /* Sync the DMA map. */ 1412 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1413 BUS_DMASYNC_PREWRITE); 1414 1415 /* 1416 * Initialize the transmit descriptors. 1417 */ 1418 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1419 seg < dmamap->dm_nsegs; 1420 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1421 /* 1422 * If this is the first descriptor we're 1423 * enqueueing, don't set the OWN bit just 1424 * yet. That could cause a race condition. 1425 * We'll do it below. 1426 */ 1427 sc->sc_txdescs[nexttx].sipd_bufptr = 1428 htole32(dmamap->dm_segs[seg].ds_addr); 1429 sc->sc_txdescs[nexttx].sipd_cmdsts = 1430 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1431 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1432 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1433 lasttx = nexttx; 1434 } 1435 1436 /* Clear the MORE bit on the last segment. */ 1437 sc->sc_txdescs[lasttx].sipd_cmdsts &= htole32(~CMDSTS_MORE); 1438 1439 /* 1440 * If we're in the interrupt delay window, delay the 1441 * interrupt. 1442 */ 1443 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1444 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1445 sc->sc_txdescs[lasttx].sipd_cmdsts |= 1446 htole32(CMDSTS_INTR); 1447 sc->sc_txwin = 0; 1448 } 1449 1450 if (sc->sc_gigabit) 1451 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1452 1453 /* Sync the descriptors we're using. */ 1454 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1455 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1456 1457 /* 1458 * The entire packet is set up. Give the first descrptor 1459 * to the chip now. 1460 */ 1461 sc->sc_txdescs[sc->sc_txnext].sipd_cmdsts |= 1462 htole32(CMDSTS_OWN); 1463 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1464 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1465 1466 /* 1467 * Store a pointer to the packet so we can free it later, 1468 * and remember what txdirty will be once the packet is 1469 * done. 1470 */ 1471 txs->txs_mbuf = m0; 1472 txs->txs_firstdesc = sc->sc_txnext; 1473 txs->txs_lastdesc = lasttx; 1474 1475 /* Advance the tx pointer. */ 1476 sc->sc_txfree -= dmamap->dm_nsegs; 1477 sc->sc_txnext = nexttx; 1478 1479 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1480 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1481 1482 #if NBPFILTER > 0 1483 /* 1484 * Pass the packet to any BPF listeners. 1485 */ 1486 if (ifp->if_bpf) 1487 bpf_mtap(ifp->if_bpf, m0); 1488 #endif /* NBPFILTER > 0 */ 1489 } 1490 1491 if (txs == NULL || sc->sc_txfree == 0) { 1492 /* No more slots left; notify upper layer. */ 1493 ifp->if_flags |= IFF_OACTIVE; 1494 } 1495 1496 if (sc->sc_txfree != ofree) { 1497 /* 1498 * Start the transmit process. Note, the manual says 1499 * that if there are no pending transmissions in the 1500 * chip's internal queue (indicated by TXE being clear), 1501 * then the driver software must set the TXDP to the 1502 * first descriptor to be transmitted. However, if we 1503 * do this, it causes serious performance degredation on 1504 * the DP83820 under load, not setting TXDP doesn't seem 1505 * to adversely affect the SiS 900 or DP83815. 1506 * 1507 * Well, I guess it wouldn't be the first time a manual 1508 * has lied -- and they could be speaking of the NULL- 1509 * terminated descriptor list case, rather than OWN- 1510 * terminated rings. 1511 */ 1512 #if 0 1513 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1514 CR_TXE) == 0) { 1515 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1516 SIP_CDTXADDR(sc, firsttx)); 1517 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1518 } 1519 #else 1520 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1521 #endif 1522 1523 /* Set a watchdog timer in case the chip flakes out. */ 1524 /* Gigabit autonegotiation takes 5 seconds. */ 1525 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1526 } 1527 } 1528 1529 /* 1530 * sip_watchdog: [ifnet interface function] 1531 * 1532 * Watchdog timer handler. 1533 */ 1534 static void 1535 sipcom_watchdog(struct ifnet *ifp) 1536 { 1537 struct sip_softc *sc = ifp->if_softc; 1538 1539 /* 1540 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1541 * If we get a timeout, try and sweep up transmit descriptors. 1542 * If we manage to sweep them all up, ignore the lack of 1543 * interrupt. 1544 */ 1545 sipcom_txintr(sc); 1546 1547 if (sc->sc_txfree != sc->sc_ntxdesc) { 1548 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1549 ifp->if_oerrors++; 1550 1551 /* Reset the interface. */ 1552 (void) sipcom_init(ifp); 1553 } else if (ifp->if_flags & IFF_DEBUG) 1554 printf("%s: recovered from device timeout\n", 1555 sc->sc_dev.dv_xname); 1556 1557 /* Try to get more packets going. */ 1558 sipcom_start(ifp); 1559 } 1560 1561 /* 1562 * sip_ioctl: [ifnet interface function] 1563 * 1564 * Handle control requests from the operator. 1565 */ 1566 static int 1567 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1568 { 1569 struct sip_softc *sc = ifp->if_softc; 1570 struct ifreq *ifr = (struct ifreq *)data; 1571 int s, error; 1572 1573 s = splnet(); 1574 1575 switch (cmd) { 1576 case SIOCSIFMEDIA: 1577 /* Flow control requires full-duplex mode. */ 1578 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1579 (ifr->ifr_media & IFM_FDX) == 0) 1580 ifr->ifr_media &= ~IFM_ETH_FMASK; 1581 1582 /* XXX */ 1583 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1584 ifr->ifr_media &= ~IFM_ETH_FMASK; 1585 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1586 if (sc->sc_gigabit && 1587 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1588 /* We can do both TXPAUSE and RXPAUSE. */ 1589 ifr->ifr_media |= 1590 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1591 } else if (ifr->ifr_media & IFM_FLOW) { 1592 /* 1593 * Both TXPAUSE and RXPAUSE must be set. 1594 * (SiS900 and DP83815 don't have PAUSE_ASYM 1595 * feature.) 1596 * 1597 * XXX Can SiS900 and DP83815 send PAUSE? 1598 */ 1599 ifr->ifr_media |= 1600 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1601 } 1602 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1603 } 1604 /* FALLTHROUGH */ 1605 case SIOCGIFMEDIA: 1606 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1607 break; 1608 case SIOCSIFFLAGS: 1609 /* If the interface is up and running, only modify the receive 1610 * filter when setting promiscuous or debug mode. Otherwise 1611 * fall through to ether_ioctl, which will reset the chip. 1612 */ 1613 1614 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1615 == (sc)->sc_ethercom.ec_capenable) \ 1616 && ((sc)->sc_prev.is_vlan == \ 1617 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1618 1619 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1620 1621 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1622 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1623 == (IFF_UP|IFF_RUNNING)) 1624 && ((ifp->if_flags & (~RESETIGN)) 1625 == (sc->sc_if_flags & (~RESETIGN))) 1626 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1627 /* Set up the receive filter. */ 1628 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1629 error = 0; 1630 break; 1631 #undef RESETIGN 1632 } 1633 /* FALLTHROUGH */ 1634 default: 1635 error = ether_ioctl(ifp, cmd, data); 1636 if (error == ENETRESET) { 1637 /* 1638 * Multicast list has changed; set the hardware filter 1639 * accordingly. 1640 */ 1641 if (ifp->if_flags & IFF_RUNNING) 1642 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1643 error = 0; 1644 } 1645 break; 1646 } 1647 1648 /* Try to get more packets going. */ 1649 sipcom_start(ifp); 1650 1651 sc->sc_if_flags = ifp->if_flags; 1652 splx(s); 1653 return (error); 1654 } 1655 1656 /* 1657 * sip_intr: 1658 * 1659 * Interrupt service routine. 1660 */ 1661 static int 1662 sipcom_intr(void *arg) 1663 { 1664 struct sip_softc *sc = arg; 1665 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1666 u_int32_t isr; 1667 int handled = 0; 1668 1669 /* Disable interrupts. */ 1670 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1671 1672 for (;;) { 1673 /* Reading clears interrupt. */ 1674 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1675 if ((isr & sc->sc_imr) == 0) 1676 break; 1677 1678 #if NRND > 0 1679 if (RND_ENABLED(&sc->rnd_source)) 1680 rnd_add_uint32(&sc->rnd_source, isr); 1681 #endif 1682 1683 handled = 1; 1684 1685 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1686 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1687 1688 /* Grab any new packets. */ 1689 SIP_DECL(rxintr)(sc); 1690 1691 if (isr & ISR_RXORN) { 1692 printf("%s: receive FIFO overrun\n", 1693 sc->sc_dev.dv_xname); 1694 1695 /* XXX adjust rx_drain_thresh? */ 1696 } 1697 1698 if (isr & ISR_RXIDLE) { 1699 printf("%s: receive ring overrun\n", 1700 sc->sc_dev.dv_xname); 1701 1702 /* Get the receive process going again. */ 1703 bus_space_write_4(sc->sc_st, sc->sc_sh, 1704 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1705 bus_space_write_4(sc->sc_st, sc->sc_sh, 1706 SIP_CR, CR_RXE); 1707 } 1708 } 1709 1710 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1711 #ifdef SIP_EVENT_COUNTERS 1712 if (isr & ISR_TXDESC) 1713 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1714 else if (isr & ISR_TXIDLE) 1715 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1716 #endif 1717 1718 /* Sweep up transmit descriptors. */ 1719 sipcom_txintr(sc); 1720 1721 if (isr & ISR_TXURN) { 1722 u_int32_t thresh; 1723 1724 printf("%s: transmit FIFO underrun", 1725 sc->sc_dev.dv_xname); 1726 1727 thresh = sc->sc_tx_drain_thresh + 1; 1728 if (thresh <= TXCFG_DRTH && 1729 (thresh * 32) <= (SIP_TXFIFO_SIZE - 1730 (sc->sc_tx_fill_thresh * 32))) { 1731 printf("; increasing Tx drain " 1732 "threshold to %u bytes\n", 1733 thresh * 32); 1734 sc->sc_tx_drain_thresh = thresh; 1735 (void) sipcom_init(ifp); 1736 } else { 1737 (void) sipcom_init(ifp); 1738 printf("\n"); 1739 } 1740 } 1741 } 1742 1743 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1744 if (isr & ISR_PAUSE_ST) { 1745 sc->sc_paused = 1; 1746 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1747 ifp->if_flags |= IFF_OACTIVE; 1748 } 1749 if (isr & ISR_PAUSE_END) { 1750 sc->sc_paused = 0; 1751 ifp->if_flags &= ~IFF_OACTIVE; 1752 } 1753 } 1754 1755 if (isr & ISR_HIBERR) { 1756 int want_init = 0; 1757 1758 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1759 1760 #define PRINTERR(bit, str) \ 1761 do { \ 1762 if ((isr & (bit)) != 0) { \ 1763 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1764 printf("%s: %s\n", \ 1765 sc->sc_dev.dv_xname, str); \ 1766 want_init = 1; \ 1767 } \ 1768 } while (/*CONSTCOND*/0) 1769 1770 PRINTERR(ISR_DPERR, "parity error"); 1771 PRINTERR(ISR_SSERR, "system error"); 1772 PRINTERR(ISR_RMABT, "master abort"); 1773 PRINTERR(ISR_RTABT, "target abort"); 1774 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1775 /* 1776 * Ignore: 1777 * Tx reset complete 1778 * Rx reset complete 1779 */ 1780 if (want_init) 1781 (void) sipcom_init(ifp); 1782 #undef PRINTERR 1783 } 1784 } 1785 1786 /* Re-enable interrupts. */ 1787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1788 1789 /* Try to get more packets going. */ 1790 sipcom_start(ifp); 1791 1792 return (handled); 1793 } 1794 1795 /* 1796 * sip_txintr: 1797 * 1798 * Helper; handle transmit interrupts. 1799 */ 1800 static void 1801 sipcom_txintr(struct sip_softc *sc) 1802 { 1803 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1804 struct sip_txsoft *txs; 1805 u_int32_t cmdsts; 1806 1807 if (sc->sc_paused == 0) 1808 ifp->if_flags &= ~IFF_OACTIVE; 1809 1810 /* 1811 * Go through our Tx list and free mbufs for those 1812 * frames which have been transmitted. 1813 */ 1814 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1815 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1816 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1817 1818 cmdsts = le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 1819 if (cmdsts & CMDSTS_OWN) 1820 break; 1821 1822 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1823 1824 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1825 1826 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1827 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1828 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1829 m_freem(txs->txs_mbuf); 1830 txs->txs_mbuf = NULL; 1831 1832 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1833 1834 /* 1835 * Check for errors and collisions. 1836 */ 1837 if (cmdsts & 1838 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1839 ifp->if_oerrors++; 1840 if (cmdsts & CMDSTS_Tx_EC) 1841 ifp->if_collisions += 16; 1842 if (ifp->if_flags & IFF_DEBUG) { 1843 if (cmdsts & CMDSTS_Tx_ED) 1844 printf("%s: excessive deferral\n", 1845 sc->sc_dev.dv_xname); 1846 if (cmdsts & CMDSTS_Tx_EC) 1847 printf("%s: excessive collisions\n", 1848 sc->sc_dev.dv_xname); 1849 } 1850 } else { 1851 /* Packet was transmitted successfully. */ 1852 ifp->if_opackets++; 1853 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 1854 } 1855 } 1856 1857 /* 1858 * If there are no more pending transmissions, cancel the watchdog 1859 * timer. 1860 */ 1861 if (txs == NULL) { 1862 ifp->if_timer = 0; 1863 sc->sc_txwin = 0; 1864 } 1865 } 1866 1867 #if defined(DP83820) 1868 /* 1869 * sip_rxintr: 1870 * 1871 * Helper; handle receive interrupts. 1872 */ 1873 static void 1874 SIP_DECL(rxintr)(struct sip_softc *sc) 1875 { 1876 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1877 struct sip_rxsoft *rxs; 1878 struct mbuf *m; 1879 u_int32_t cmdsts, extsts; 1880 int i, len; 1881 1882 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 1883 rxs = &sc->sc_rxsoft[i]; 1884 1885 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1886 1887 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 1888 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 1889 len = CMDSTS_SIZE(cmdsts); 1890 1891 /* 1892 * NOTE: OWN is set if owned by _consumer_. We're the 1893 * consumer of the receive ring, so if the bit is clear, 1894 * we have processed all of the packets. 1895 */ 1896 if ((cmdsts & CMDSTS_OWN) == 0) { 1897 /* 1898 * We have processed all of the receive buffers. 1899 */ 1900 break; 1901 } 1902 1903 if (__predict_false(sc->sc_rxdiscard)) { 1904 SIP_INIT_RXDESC(sc, i); 1905 if ((cmdsts & CMDSTS_MORE) == 0) { 1906 /* Reset our state. */ 1907 sc->sc_rxdiscard = 0; 1908 } 1909 continue; 1910 } 1911 1912 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1913 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1914 1915 m = rxs->rxs_mbuf; 1916 1917 /* 1918 * Add a new receive buffer to the ring. 1919 */ 1920 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 1921 /* 1922 * Failed, throw away what we've done so 1923 * far, and discard the rest of the packet. 1924 */ 1925 ifp->if_ierrors++; 1926 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1927 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1928 SIP_INIT_RXDESC(sc, i); 1929 if (cmdsts & CMDSTS_MORE) 1930 sc->sc_rxdiscard = 1; 1931 if (sc->sc_rxhead != NULL) 1932 m_freem(sc->sc_rxhead); 1933 SIP_RXCHAIN_RESET(sc); 1934 continue; 1935 } 1936 1937 SIP_RXCHAIN_LINK(sc, m); 1938 1939 m->m_len = len; 1940 1941 /* 1942 * If this is not the end of the packet, keep 1943 * looking. 1944 */ 1945 if (cmdsts & CMDSTS_MORE) { 1946 sc->sc_rxlen += len; 1947 continue; 1948 } 1949 1950 /* 1951 * Okay, we have the entire packet now. The chip includes 1952 * the FCS, so we need to trim it. 1953 */ 1954 m->m_len -= ETHER_CRC_LEN; 1955 1956 *sc->sc_rxtailp = NULL; 1957 len = m->m_len + sc->sc_rxlen; 1958 m = sc->sc_rxhead; 1959 1960 SIP_RXCHAIN_RESET(sc); 1961 1962 /* 1963 * If an error occurred, update stats and drop the packet. 1964 */ 1965 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 1966 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 1967 ifp->if_ierrors++; 1968 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 1969 (cmdsts & CMDSTS_Rx_RXO) == 0) { 1970 /* Receive overrun handled elsewhere. */ 1971 printf("%s: receive descriptor error\n", 1972 sc->sc_dev.dv_xname); 1973 } 1974 #define PRINTERR(bit, str) \ 1975 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 1976 (cmdsts & (bit)) != 0) \ 1977 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 1978 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 1979 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 1980 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 1981 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 1982 #undef PRINTERR 1983 m_freem(m); 1984 continue; 1985 } 1986 1987 /* 1988 * If the packet is small enough to fit in a 1989 * single header mbuf, allocate one and copy 1990 * the data into it. This greatly reduces 1991 * memory consumption when we receive lots 1992 * of small packets. 1993 */ 1994 if (SIP_DECL(copy_small) != 0 && len <= (MHLEN - 2)) { 1995 struct mbuf *nm; 1996 MGETHDR(nm, M_DONTWAIT, MT_DATA); 1997 if (nm == NULL) { 1998 ifp->if_ierrors++; 1999 m_freem(m); 2000 continue; 2001 } 2002 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2003 nm->m_data += 2; 2004 nm->m_pkthdr.len = nm->m_len = len; 2005 m_copydata(m, 0, len, mtod(nm, void *)); 2006 m_freem(m); 2007 m = nm; 2008 } 2009 #ifndef __NO_STRICT_ALIGNMENT 2010 else { 2011 /* 2012 * The DP83820's receive buffers must be 4-byte 2013 * aligned. But this means that the data after 2014 * the Ethernet header is misaligned. To compensate, 2015 * we have artificially shortened the buffer size 2016 * in the descriptor, and we do an overlapping copy 2017 * of the data two bytes further in (in the first 2018 * buffer of the chain only). 2019 */ 2020 memmove(mtod(m, char *) + 2, mtod(m, void *), 2021 m->m_len); 2022 m->m_data += 2; 2023 } 2024 #endif /* ! __NO_STRICT_ALIGNMENT */ 2025 2026 /* 2027 * If VLANs are enabled, VLAN packets have been unwrapped 2028 * for us. Associate the tag with the packet. 2029 */ 2030 2031 /* 2032 * Again, byte swapping is tricky. Hardware provided 2033 * the tag in the network byte order, but extsts was 2034 * passed through le32toh() in the meantime. On a 2035 * big-endian machine, we need to swap it again. On a 2036 * little-endian machine, we need to convert from the 2037 * network to host byte order. This means that we must 2038 * swap it in any case, so unconditional swap instead 2039 * of htons() is used. 2040 */ 2041 if ((extsts & EXTSTS_VPKT) != 0) { 2042 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2043 continue); 2044 } 2045 2046 /* 2047 * Set the incoming checksum information for the 2048 * packet. 2049 */ 2050 if ((extsts & EXTSTS_IPPKT) != 0) { 2051 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2052 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2053 if (extsts & EXTSTS_Rx_IPERR) 2054 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2055 if (extsts & EXTSTS_TCPPKT) { 2056 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2057 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2058 if (extsts & EXTSTS_Rx_TCPERR) 2059 m->m_pkthdr.csum_flags |= 2060 M_CSUM_TCP_UDP_BAD; 2061 } else if (extsts & EXTSTS_UDPPKT) { 2062 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2063 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2064 if (extsts & EXTSTS_Rx_UDPERR) 2065 m->m_pkthdr.csum_flags |= 2066 M_CSUM_TCP_UDP_BAD; 2067 } 2068 } 2069 2070 ifp->if_ipackets++; 2071 m->m_pkthdr.rcvif = ifp; 2072 m->m_pkthdr.len = len; 2073 2074 #if NBPFILTER > 0 2075 /* 2076 * Pass this up to any BPF listeners, but only 2077 * pass if up the stack if it's for us. 2078 */ 2079 if (ifp->if_bpf) 2080 bpf_mtap(ifp->if_bpf, m); 2081 #endif /* NBPFILTER > 0 */ 2082 2083 /* Pass it on. */ 2084 (*ifp->if_input)(ifp, m); 2085 } 2086 2087 /* Update the receive pointer. */ 2088 sc->sc_rxptr = i; 2089 } 2090 #else /* ! DP83820 */ 2091 /* 2092 * sip_rxintr: 2093 * 2094 * Helper; handle receive interrupts. 2095 */ 2096 static void 2097 SIP_DECL(rxintr)(struct sip_softc *sc) 2098 { 2099 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2100 struct sip_rxsoft *rxs; 2101 struct mbuf *m; 2102 u_int32_t cmdsts; 2103 int i, len; 2104 2105 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2106 rxs = &sc->sc_rxsoft[i]; 2107 2108 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2109 2110 cmdsts = le32toh(sc->sc_rxdescs[i].sipd_cmdsts); 2111 2112 /* 2113 * NOTE: OWN is set if owned by _consumer_. We're the 2114 * consumer of the receive ring, so if the bit is clear, 2115 * we have processed all of the packets. 2116 */ 2117 if ((cmdsts & CMDSTS_OWN) == 0) { 2118 /* 2119 * We have processed all of the receive buffers. 2120 */ 2121 break; 2122 } 2123 2124 /* 2125 * If any collisions were seen on the wire, count one. 2126 */ 2127 if (cmdsts & CMDSTS_Rx_COL) 2128 ifp->if_collisions++; 2129 2130 /* 2131 * If an error occurred, update stats, clear the status 2132 * word, and leave the packet buffer in place. It will 2133 * simply be reused the next time the ring comes around. 2134 */ 2135 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2136 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2137 ifp->if_ierrors++; 2138 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2139 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2140 /* Receive overrun handled elsewhere. */ 2141 printf("%s: receive descriptor error\n", 2142 sc->sc_dev.dv_xname); 2143 } 2144 #define PRINTERR(bit, str) \ 2145 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2146 (cmdsts & (bit)) != 0) \ 2147 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2148 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2149 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2150 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2151 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2152 #undef PRINTERR 2153 SIP_INIT_RXDESC(sc, i); 2154 continue; 2155 } 2156 2157 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2158 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2159 2160 /* 2161 * No errors; receive the packet. Note, the SiS 900 2162 * includes the CRC with every packet. 2163 */ 2164 len = CMDSTS_SIZE(cmdsts) - ETHER_CRC_LEN; 2165 2166 #ifdef __NO_STRICT_ALIGNMENT 2167 /* 2168 * If the packet is small enough to fit in a 2169 * single header mbuf, allocate one and copy 2170 * the data into it. This greatly reduces 2171 * memory consumption when we receive lots 2172 * of small packets. 2173 * 2174 * Otherwise, we add a new buffer to the receive 2175 * chain. If this fails, we drop the packet and 2176 * recycle the old buffer. 2177 */ 2178 if (SIP_DECL(copy_small) != 0 && len <= MHLEN) { 2179 MGETHDR(m, M_DONTWAIT, MT_DATA); 2180 if (m == NULL) 2181 goto dropit; 2182 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2183 memcpy(mtod(m, void *), 2184 mtod(rxs->rxs_mbuf, void *), len); 2185 SIP_INIT_RXDESC(sc, i); 2186 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2187 rxs->rxs_dmamap->dm_mapsize, 2188 BUS_DMASYNC_PREREAD); 2189 } else { 2190 m = rxs->rxs_mbuf; 2191 if (SIP_DECL(add_rxbuf)(sc, i) != 0) { 2192 dropit: 2193 ifp->if_ierrors++; 2194 SIP_INIT_RXDESC(sc, i); 2195 bus_dmamap_sync(sc->sc_dmat, 2196 rxs->rxs_dmamap, 0, 2197 rxs->rxs_dmamap->dm_mapsize, 2198 BUS_DMASYNC_PREREAD); 2199 continue; 2200 } 2201 } 2202 #else 2203 /* 2204 * The SiS 900's receive buffers must be 4-byte aligned. 2205 * But this means that the data after the Ethernet header 2206 * is misaligned. We must allocate a new buffer and 2207 * copy the data, shifted forward 2 bytes. 2208 */ 2209 MGETHDR(m, M_DONTWAIT, MT_DATA); 2210 if (m == NULL) { 2211 dropit: 2212 ifp->if_ierrors++; 2213 SIP_INIT_RXDESC(sc, i); 2214 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2215 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2216 continue; 2217 } 2218 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2219 if (len > (MHLEN - 2)) { 2220 MCLGET(m, M_DONTWAIT); 2221 if ((m->m_flags & M_EXT) == 0) { 2222 m_freem(m); 2223 goto dropit; 2224 } 2225 } 2226 m->m_data += 2; 2227 2228 /* 2229 * Note that we use clusters for incoming frames, so the 2230 * buffer is virtually contiguous. 2231 */ 2232 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2233 2234 /* Allow the receive descriptor to continue using its mbuf. */ 2235 SIP_INIT_RXDESC(sc, i); 2236 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2237 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2238 #endif /* __NO_STRICT_ALIGNMENT */ 2239 2240 ifp->if_ipackets++; 2241 m->m_pkthdr.rcvif = ifp; 2242 m->m_pkthdr.len = m->m_len = len; 2243 2244 #if NBPFILTER > 0 2245 /* 2246 * Pass this up to any BPF listeners, but only 2247 * pass if up the stack if it's for us. 2248 */ 2249 if (ifp->if_bpf) 2250 bpf_mtap(ifp->if_bpf, m); 2251 #endif /* NBPFILTER > 0 */ 2252 2253 /* Pass it on. */ 2254 (*ifp->if_input)(ifp, m); 2255 } 2256 2257 /* Update the receive pointer. */ 2258 sc->sc_rxptr = i; 2259 } 2260 #endif /* DP83820 */ 2261 2262 /* 2263 * sip_tick: 2264 * 2265 * One second timer, used to tick the MII. 2266 */ 2267 static void 2268 sipcom_tick(void *arg) 2269 { 2270 struct sip_softc *sc = arg; 2271 int s; 2272 2273 s = splnet(); 2274 #ifdef SIP_EVENT_COUNTERS 2275 if (sc->sc_gigabit) { 2276 /* Read PAUSE related counts from MIB registers. */ 2277 sc->sc_ev_rxpause.ev_count += 2278 bus_space_read_4(sc->sc_st, sc->sc_sh, 2279 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2280 sc->sc_ev_txpause.ev_count += 2281 bus_space_read_4(sc->sc_st, sc->sc_sh, 2282 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2283 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2284 } 2285 #endif /* SIP_EVENT_COUNTERS */ 2286 mii_tick(&sc->sc_mii); 2287 splx(s); 2288 2289 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2290 } 2291 2292 /* 2293 * sip_reset: 2294 * 2295 * Perform a soft reset on the SiS 900. 2296 */ 2297 static bool 2298 sipcom_reset(struct sip_softc *sc) 2299 { 2300 bus_space_tag_t st = sc->sc_st; 2301 bus_space_handle_t sh = sc->sc_sh; 2302 int i; 2303 2304 bus_space_write_4(st, sh, SIP_IER, 0); 2305 bus_space_write_4(st, sh, SIP_IMR, 0); 2306 bus_space_write_4(st, sh, SIP_RFCR, 0); 2307 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2308 2309 for (i = 0; i < SIP_TIMEOUT; i++) { 2310 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2311 break; 2312 delay(2); 2313 } 2314 2315 if (i == SIP_TIMEOUT) { 2316 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2317 return false; 2318 } 2319 2320 delay(1000); 2321 2322 if (sc->sc_gigabit) { 2323 /* 2324 * Set the general purpose I/O bits. Do it here in case we 2325 * need to have GPIO set up to talk to the media interface. 2326 */ 2327 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2328 delay(1000); 2329 } 2330 return true; 2331 } 2332 2333 static void 2334 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2335 { 2336 u_int32_t reg; 2337 bus_space_tag_t st = sc->sc_st; 2338 bus_space_handle_t sh = sc->sc_sh; 2339 /* 2340 * Initialize the VLAN/IP receive control register. 2341 * We enable checksum computation on all incoming 2342 * packets, and do not reject packets w/ bad checksums. 2343 */ 2344 reg = 0; 2345 if (capenable & 2346 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2347 reg |= VRCR_IPEN; 2348 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2349 reg |= VRCR_VTDEN|VRCR_VTREN; 2350 bus_space_write_4(st, sh, SIP_VRCR, reg); 2351 2352 /* 2353 * Initialize the VLAN/IP transmit control register. 2354 * We enable outgoing checksum computation on a 2355 * per-packet basis. 2356 */ 2357 reg = 0; 2358 if (capenable & 2359 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2360 reg |= VTCR_PPCHK; 2361 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2362 reg |= VTCR_VPPTI; 2363 bus_space_write_4(st, sh, SIP_VTCR, reg); 2364 2365 /* 2366 * If we're using VLANs, initialize the VLAN data register. 2367 * To understand why we bswap the VLAN Ethertype, see section 2368 * 4.2.36 of the DP83820 manual. 2369 */ 2370 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2371 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2372 } 2373 2374 /* 2375 * sip_init: [ ifnet interface function ] 2376 * 2377 * Initialize the interface. Must be called at splnet(). 2378 */ 2379 static int 2380 sipcom_init(struct ifnet *ifp) 2381 { 2382 struct sip_softc *sc = ifp->if_softc; 2383 bus_space_tag_t st = sc->sc_st; 2384 bus_space_handle_t sh = sc->sc_sh; 2385 struct sip_txsoft *txs; 2386 struct sip_rxsoft *rxs; 2387 struct sip_desc *sipd; 2388 int i, error = 0; 2389 2390 if (!device_has_power(&sc->sc_dev)) 2391 return EBUSY; 2392 2393 /* 2394 * Cancel any pending I/O. 2395 */ 2396 sipcom_stop(ifp, 0); 2397 2398 /* 2399 * Reset the chip to a known state. 2400 */ 2401 if (!sipcom_reset(sc)) 2402 return EBUSY; 2403 2404 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2405 /* 2406 * DP83815 manual, page 78: 2407 * 4.4 Recommended Registers Configuration 2408 * For optimum performance of the DP83815, version noted 2409 * as DP83815CVNG (SRR = 203h), the listed register 2410 * modifications must be followed in sequence... 2411 * 2412 * It's not clear if this should be 302h or 203h because that 2413 * chip name is listed as SRR 302h in the description of the 2414 * SRR register. However, my revision 302h DP83815 on the 2415 * Netgear FA311 purchased in 02/2001 needs these settings 2416 * to avoid tons of errors in AcceptPerfectMatch (non- 2417 * IFF_PROMISC) mode. I do not know if other revisions need 2418 * this set or not. [briggs -- 09 March 2001] 2419 * 2420 * Note that only the low-order 12 bits of 0xe4 are documented 2421 * and that this sets reserved bits in that register. 2422 */ 2423 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2424 2425 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2426 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2427 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2428 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2429 2430 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2431 } 2432 2433 /* 2434 * Initialize the transmit descriptor ring. 2435 */ 2436 for (i = 0; i < sc->sc_ntxdesc; i++) { 2437 sipd = &sc->sc_txdescs[i]; 2438 memset(sipd, 0, sizeof(struct sip_desc)); 2439 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2440 } 2441 SIP_CDTXSYNC(sc, 0, sc->sc_ntxdesc, 2442 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2443 sc->sc_txfree = sc->sc_ntxdesc; 2444 sc->sc_txnext = 0; 2445 sc->sc_txwin = 0; 2446 2447 /* 2448 * Initialize the transmit job descriptors. 2449 */ 2450 SIMPLEQ_INIT(&sc->sc_txfreeq); 2451 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2452 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2453 txs = &sc->sc_txsoft[i]; 2454 txs->txs_mbuf = NULL; 2455 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2456 } 2457 2458 /* 2459 * Initialize the receive descriptor and receive job 2460 * descriptor rings. 2461 */ 2462 for (i = 0; i < sc->sc_nrxdesc; i++) { 2463 rxs = &sc->sc_rxsoft[i]; 2464 if (rxs->rxs_mbuf == NULL) { 2465 if ((error = SIP_DECL(add_rxbuf)(sc, i)) != 0) { 2466 printf("%s: unable to allocate or map rx " 2467 "buffer %d, error = %d\n", 2468 sc->sc_dev.dv_xname, i, error); 2469 /* 2470 * XXX Should attempt to run with fewer receive 2471 * XXX buffers instead of just failing. 2472 */ 2473 sipcom_rxdrain(sc); 2474 goto out; 2475 } 2476 } else 2477 SIP_INIT_RXDESC(sc, i); 2478 } 2479 sc->sc_rxptr = 0; 2480 sc->sc_rxdiscard = 0; 2481 SIP_RXCHAIN_RESET(sc); 2482 2483 /* 2484 * Set the configuration register; it's already initialized 2485 * in sip_attach(). 2486 */ 2487 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2488 2489 /* 2490 * Initialize the prototype TXCFG register. 2491 */ 2492 if (sc->sc_gigabit) { 2493 sc->sc_txcfg = TXCFG_MXDMA_512; 2494 sc->sc_rxcfg = RXCFG_MXDMA_512; 2495 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2496 SIP_SIS900_REV(sc, SIS_REV_960) || 2497 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2498 (sc->sc_cfg & CFG_EDBMASTEN)) { 2499 sc->sc_txcfg = TXCFG_MXDMA_64; 2500 sc->sc_rxcfg = RXCFG_MXDMA_64; 2501 } else { 2502 sc->sc_txcfg = TXCFG_MXDMA_512; 2503 sc->sc_rxcfg = RXCFG_MXDMA_512; 2504 } 2505 2506 sc->sc_txcfg |= TXCFG_ATP | 2507 (sc->sc_tx_fill_thresh << TXCFG_FLTH_SHIFT) | 2508 sc->sc_tx_drain_thresh; 2509 bus_space_write_4(st, sh, SIP_TXCFG, sc->sc_txcfg); 2510 2511 /* 2512 * Initialize the receive drain threshold if we have never 2513 * done so. 2514 */ 2515 if (sc->sc_rx_drain_thresh == 0) { 2516 /* 2517 * XXX This value should be tuned. This is set to the 2518 * maximum of 248 bytes, and we may be able to improve 2519 * performance by decreasing it (although we should never 2520 * set this value lower than 2; 14 bytes are required to 2521 * filter the packet). 2522 */ 2523 sc->sc_rx_drain_thresh = RXCFG_DRTH >> RXCFG_DRTH_SHIFT; 2524 } 2525 2526 /* 2527 * Initialize the prototype RXCFG register. 2528 */ 2529 sc->sc_rxcfg |= (sc->sc_rx_drain_thresh << RXCFG_DRTH_SHIFT); 2530 /* 2531 * Accept long packets (including FCS) so we can handle 2532 * 802.1q-tagged frames and jumbo frames properly. 2533 */ 2534 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2535 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2536 sc->sc_rxcfg |= RXCFG_ALP; 2537 2538 /* 2539 * Checksum offloading is disabled if the user selects an MTU 2540 * larger than 8109. (FreeBSD says 8152, but there is emperical 2541 * evidence that >8109 does not work on some boards, such as the 2542 * Planex GN-1000TE). 2543 */ 2544 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2545 (ifp->if_capenable & 2546 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2547 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2548 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2549 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2550 "disabled.\n", sc->sc_dev.dv_xname); 2551 ifp->if_capenable &= 2552 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2553 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2554 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2555 ifp->if_csum_flags_tx = 0; 2556 ifp->if_csum_flags_rx = 0; 2557 } 2558 2559 bus_space_write_4(st, sh, SIP_RXCFG, sc->sc_rxcfg); 2560 2561 if (sc->sc_gigabit) 2562 sipcom_dp83820_init(sc, ifp->if_capenable); 2563 2564 /* 2565 * Give the transmit and receive rings to the chip. 2566 */ 2567 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2568 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2569 2570 /* 2571 * Initialize the interrupt mask. 2572 */ 2573 sc->sc_imr = ISR_DPERR|ISR_SSERR|ISR_RMABT|ISR_RTABT|ISR_RXSOVR| 2574 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2575 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2576 2577 /* Set up the receive filter. */ 2578 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2579 2580 /* 2581 * Tune sc_rx_flow_thresh. 2582 * XXX "More than 8KB" is too short for jumbo frames. 2583 * XXX TODO: Threshold value should be user-settable. 2584 */ 2585 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2586 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2587 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2588 2589 /* 2590 * Set the current media. Do this after initializing the prototype 2591 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2592 * control. 2593 */ 2594 mii_mediachg(&sc->sc_mii); 2595 2596 /* 2597 * Set the interrupt hold-off timer to 100us. 2598 */ 2599 if (sc->sc_gigabit) 2600 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2601 2602 /* 2603 * Enable interrupts. 2604 */ 2605 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2606 2607 /* 2608 * Start the transmit and receive processes. 2609 */ 2610 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2611 2612 /* 2613 * Start the one second MII clock. 2614 */ 2615 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2616 2617 /* 2618 * ...all done! 2619 */ 2620 ifp->if_flags |= IFF_RUNNING; 2621 ifp->if_flags &= ~IFF_OACTIVE; 2622 sc->sc_if_flags = ifp->if_flags; 2623 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2624 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2625 sc->sc_prev.if_capenable = ifp->if_capenable; 2626 2627 out: 2628 if (error) 2629 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2630 return (error); 2631 } 2632 2633 /* 2634 * sip_drain: 2635 * 2636 * Drain the receive queue. 2637 */ 2638 static void 2639 sipcom_rxdrain(struct sip_softc *sc) 2640 { 2641 struct sip_rxsoft *rxs; 2642 int i; 2643 2644 for (i = 0; i < sc->sc_nrxdesc; i++) { 2645 rxs = &sc->sc_rxsoft[i]; 2646 if (rxs->rxs_mbuf != NULL) { 2647 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2648 m_freem(rxs->rxs_mbuf); 2649 rxs->rxs_mbuf = NULL; 2650 } 2651 } 2652 } 2653 2654 /* 2655 * sip_stop: [ ifnet interface function ] 2656 * 2657 * Stop transmission on the interface. 2658 */ 2659 static void 2660 sipcom_stop(struct ifnet *ifp, int disable) 2661 { 2662 struct sip_softc *sc = ifp->if_softc; 2663 bus_space_tag_t st = sc->sc_st; 2664 bus_space_handle_t sh = sc->sc_sh; 2665 struct sip_txsoft *txs; 2666 u_int32_t cmdsts = 0; /* DEBUG */ 2667 2668 /* 2669 * Stop the one second clock. 2670 */ 2671 callout_stop(&sc->sc_tick_ch); 2672 2673 /* Down the MII. */ 2674 mii_down(&sc->sc_mii); 2675 2676 /* 2677 * Disable interrupts. 2678 */ 2679 bus_space_write_4(st, sh, SIP_IER, 0); 2680 2681 /* 2682 * Stop receiver and transmitter. 2683 */ 2684 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2685 2686 /* 2687 * Release any queued transmit buffers. 2688 */ 2689 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2690 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2691 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2692 (le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts) & 2693 CMDSTS_INTR) == 0) 2694 printf("%s: sip_stop: last descriptor does not " 2695 "have INTR bit set\n", sc->sc_dev.dv_xname); 2696 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2697 #ifdef DIAGNOSTIC 2698 if (txs->txs_mbuf == NULL) { 2699 printf("%s: dirty txsoft with no mbuf chain\n", 2700 sc->sc_dev.dv_xname); 2701 panic("sip_stop"); 2702 } 2703 #endif 2704 cmdsts |= /* DEBUG */ 2705 le32toh(sc->sc_txdescs[txs->txs_lastdesc].sipd_cmdsts); 2706 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2707 m_freem(txs->txs_mbuf); 2708 txs->txs_mbuf = NULL; 2709 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2710 } 2711 2712 if (disable) 2713 sipcom_rxdrain(sc); 2714 2715 /* 2716 * Mark the interface down and cancel the watchdog timer. 2717 */ 2718 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2719 ifp->if_timer = 0; 2720 2721 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2722 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2723 printf("%s: sip_stop: no INTR bits set in dirty tx " 2724 "descriptors\n", sc->sc_dev.dv_xname); 2725 } 2726 2727 /* 2728 * sip_read_eeprom: 2729 * 2730 * Read data from the serial EEPROM. 2731 */ 2732 static void 2733 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2734 u_int16_t *data) 2735 { 2736 bus_space_tag_t st = sc->sc_st; 2737 bus_space_handle_t sh = sc->sc_sh; 2738 u_int16_t reg; 2739 int i, x; 2740 2741 for (i = 0; i < wordcnt; i++) { 2742 /* Send CHIP SELECT. */ 2743 reg = EROMAR_EECS; 2744 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2745 2746 /* Shift in the READ opcode. */ 2747 for (x = 3; x > 0; x--) { 2748 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2749 reg |= EROMAR_EEDI; 2750 else 2751 reg &= ~EROMAR_EEDI; 2752 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2753 bus_space_write_4(st, sh, SIP_EROMAR, 2754 reg | EROMAR_EESK); 2755 delay(4); 2756 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2757 delay(4); 2758 } 2759 2760 /* Shift in address. */ 2761 for (x = 6; x > 0; x--) { 2762 if ((word + i) & (1 << (x - 1))) 2763 reg |= EROMAR_EEDI; 2764 else 2765 reg &= ~EROMAR_EEDI; 2766 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2767 bus_space_write_4(st, sh, SIP_EROMAR, 2768 reg | EROMAR_EESK); 2769 delay(4); 2770 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2771 delay(4); 2772 } 2773 2774 /* Shift out data. */ 2775 reg = EROMAR_EECS; 2776 data[i] = 0; 2777 for (x = 16; x > 0; x--) { 2778 bus_space_write_4(st, sh, SIP_EROMAR, 2779 reg | EROMAR_EESK); 2780 delay(4); 2781 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2782 data[i] |= (1 << (x - 1)); 2783 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2784 delay(4); 2785 } 2786 2787 /* Clear CHIP SELECT. */ 2788 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2789 delay(4); 2790 } 2791 } 2792 2793 /* 2794 * sip_add_rxbuf: 2795 * 2796 * Add a receive buffer to the indicated descriptor. 2797 */ 2798 static int 2799 SIP_DECL(add_rxbuf)(struct sip_softc *sc, int idx) 2800 { 2801 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2802 struct mbuf *m; 2803 int error; 2804 2805 MGETHDR(m, M_DONTWAIT, MT_DATA); 2806 if (m == NULL) 2807 return (ENOBUFS); 2808 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2809 2810 MCLGET(m, M_DONTWAIT); 2811 if ((m->m_flags & M_EXT) == 0) { 2812 m_freem(m); 2813 return (ENOBUFS); 2814 } 2815 2816 /* XXX I don't believe this is necessary. --dyoung */ 2817 #if 0 || defined(DP83820) 2818 m->m_len = sc->sc_rxbuf_len; 2819 #endif /* DP83820 */ 2820 2821 if (rxs->rxs_mbuf != NULL) 2822 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2823 2824 rxs->rxs_mbuf = m; 2825 2826 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2827 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2828 BUS_DMA_READ|BUS_DMA_NOWAIT); 2829 if (error) { 2830 printf("%s: can't load rx DMA map %d, error = %d\n", 2831 sc->sc_dev.dv_xname, idx, error); 2832 panic("%s", __func__); /* XXX */ 2833 } 2834 2835 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2836 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2837 2838 SIP_INIT_RXDESC(sc, idx); 2839 2840 return (0); 2841 } 2842 2843 /* 2844 * sip_sis900_set_filter: 2845 * 2846 * Set up the receive filter. 2847 */ 2848 static void 2849 sipcom_sis900_set_filter(struct sip_softc *sc) 2850 { 2851 bus_space_tag_t st = sc->sc_st; 2852 bus_space_handle_t sh = sc->sc_sh; 2853 struct ethercom *ec = &sc->sc_ethercom; 2854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2855 struct ether_multi *enm; 2856 const u_int8_t *cp; 2857 struct ether_multistep step; 2858 u_int32_t crc, mchash[16]; 2859 2860 /* 2861 * Initialize the prototype RFCR. 2862 */ 2863 sc->sc_rfcr = RFCR_RFEN; 2864 if (ifp->if_flags & IFF_BROADCAST) 2865 sc->sc_rfcr |= RFCR_AAB; 2866 if (ifp->if_flags & IFF_PROMISC) { 2867 sc->sc_rfcr |= RFCR_AAP; 2868 goto allmulti; 2869 } 2870 2871 /* 2872 * Set up the multicast address filter by passing all multicast 2873 * addresses through a CRC generator, and then using the high-order 2874 * 6 bits as an index into the 128 bit multicast hash table (only 2875 * the lower 16 bits of each 32 bit multicast hash register are 2876 * valid). The high order bits select the register, while the 2877 * rest of the bits select the bit within the register. 2878 */ 2879 2880 memset(mchash, 0, sizeof(mchash)); 2881 2882 /* 2883 * SiS900 (at least SiS963) requires us to register the address of 2884 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 2885 */ 2886 crc = 0x0ed423f9; 2887 2888 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2889 SIP_SIS900_REV(sc, SIS_REV_960) || 2890 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2891 /* Just want the 8 most significant bits. */ 2892 crc >>= 24; 2893 } else { 2894 /* Just want the 7 most significant bits. */ 2895 crc >>= 25; 2896 } 2897 2898 /* Set the corresponding bit in the hash table. */ 2899 mchash[crc >> 4] |= 1 << (crc & 0xf); 2900 2901 ETHER_FIRST_MULTI(step, ec, enm); 2902 while (enm != NULL) { 2903 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2904 /* 2905 * We must listen to a range of multicast addresses. 2906 * For now, just accept all multicasts, rather than 2907 * trying to set only those filter bits needed to match 2908 * the range. (At this time, the only use of address 2909 * ranges is for IP multicast routing, for which the 2910 * range is big enough to require all bits set.) 2911 */ 2912 goto allmulti; 2913 } 2914 2915 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 2916 2917 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2918 SIP_SIS900_REV(sc, SIS_REV_960) || 2919 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2920 /* Just want the 8 most significant bits. */ 2921 crc >>= 24; 2922 } else { 2923 /* Just want the 7 most significant bits. */ 2924 crc >>= 25; 2925 } 2926 2927 /* Set the corresponding bit in the hash table. */ 2928 mchash[crc >> 4] |= 1 << (crc & 0xf); 2929 2930 ETHER_NEXT_MULTI(step, enm); 2931 } 2932 2933 ifp->if_flags &= ~IFF_ALLMULTI; 2934 goto setit; 2935 2936 allmulti: 2937 ifp->if_flags |= IFF_ALLMULTI; 2938 sc->sc_rfcr |= RFCR_AAM; 2939 2940 setit: 2941 #define FILTER_EMIT(addr, data) \ 2942 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 2943 delay(1); \ 2944 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 2945 delay(1) 2946 2947 /* 2948 * Disable receive filter, and program the node address. 2949 */ 2950 cp = CLLADDR(ifp->if_sadl); 2951 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 2952 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 2953 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 2954 2955 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 2956 /* 2957 * Program the multicast hash table. 2958 */ 2959 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 2960 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 2961 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 2962 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 2963 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 2964 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 2965 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 2966 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 2967 if (SIP_SIS900_REV(sc, SIS_REV_635) || 2968 SIP_SIS900_REV(sc, SIS_REV_960) || 2969 SIP_SIS900_REV(sc, SIS_REV_900B)) { 2970 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 2971 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 2972 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 2973 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 2974 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 2975 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 2976 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 2977 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 2978 } 2979 } 2980 #undef FILTER_EMIT 2981 2982 /* 2983 * Re-enable the receiver filter. 2984 */ 2985 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 2986 } 2987 2988 /* 2989 * sip_dp83815_set_filter: 2990 * 2991 * Set up the receive filter. 2992 */ 2993 static void 2994 sipcom_dp83815_set_filter(struct sip_softc *sc) 2995 { 2996 bus_space_tag_t st = sc->sc_st; 2997 bus_space_handle_t sh = sc->sc_sh; 2998 struct ethercom *ec = &sc->sc_ethercom; 2999 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3000 struct ether_multi *enm; 3001 const u_int8_t *cp; 3002 struct ether_multistep step; 3003 u_int32_t crc, hash, slot, bit; 3004 #define MCHASH_NWORDS_83820 128 3005 #define MCHASH_NWORDS_83815 32 3006 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3007 u_int16_t mchash[MCHASH_NWORDS]; 3008 int i; 3009 3010 /* 3011 * Initialize the prototype RFCR. 3012 * Enable the receive filter, and accept on 3013 * Perfect (destination address) Match 3014 * If IFF_BROADCAST, also accept all broadcast packets. 3015 * If IFF_PROMISC, accept all unicast packets (and later, set 3016 * IFF_ALLMULTI and accept all multicast, too). 3017 */ 3018 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3019 if (ifp->if_flags & IFF_BROADCAST) 3020 sc->sc_rfcr |= RFCR_AAB; 3021 if (ifp->if_flags & IFF_PROMISC) { 3022 sc->sc_rfcr |= RFCR_AAP; 3023 goto allmulti; 3024 } 3025 3026 /* 3027 * Set up the DP83820/DP83815 multicast address filter by 3028 * passing all multicast addresses through a CRC generator, 3029 * and then using the high-order 11/9 bits as an index into 3030 * the 2048/512 bit multicast hash table. The high-order 3031 * 7/5 bits select the slot, while the low-order 4 bits 3032 * select the bit within the slot. Note that only the low 3033 * 16-bits of each filter word are used, and there are 3034 * 128/32 filter words. 3035 */ 3036 3037 memset(mchash, 0, sizeof(mchash)); 3038 3039 ifp->if_flags &= ~IFF_ALLMULTI; 3040 ETHER_FIRST_MULTI(step, ec, enm); 3041 if (enm == NULL) 3042 goto setit; 3043 while (enm != NULL) { 3044 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3045 /* 3046 * We must listen to a range of multicast addresses. 3047 * For now, just accept all multicasts, rather than 3048 * trying to set only those filter bits needed to match 3049 * the range. (At this time, the only use of address 3050 * ranges is for IP multicast routing, for which the 3051 * range is big enough to require all bits set.) 3052 */ 3053 goto allmulti; 3054 } 3055 3056 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3057 3058 if (sc->sc_gigabit) { 3059 /* Just want the 11 most significant bits. */ 3060 hash = crc >> 21; 3061 } else { 3062 /* Just want the 9 most significant bits. */ 3063 hash = crc >> 23; 3064 } 3065 3066 slot = hash >> 4; 3067 bit = hash & 0xf; 3068 3069 /* Set the corresponding bit in the hash table. */ 3070 mchash[slot] |= 1 << bit; 3071 3072 ETHER_NEXT_MULTI(step, enm); 3073 } 3074 sc->sc_rfcr |= RFCR_MHEN; 3075 goto setit; 3076 3077 allmulti: 3078 ifp->if_flags |= IFF_ALLMULTI; 3079 sc->sc_rfcr |= RFCR_AAM; 3080 3081 setit: 3082 #define FILTER_EMIT(addr, data) \ 3083 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3084 delay(1); \ 3085 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3086 delay(1) 3087 3088 /* 3089 * Disable receive filter, and program the node address. 3090 */ 3091 cp = CLLADDR(ifp->if_sadl); 3092 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3093 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3094 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3095 3096 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3097 int nwords = 3098 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3099 /* 3100 * Program the multicast hash table. 3101 */ 3102 for (i = 0; i < nwords; i++) { 3103 FILTER_EMIT(RFCR_NS_RFADDR_FILTMEM + (i * 2), 3104 mchash[i]); 3105 } 3106 } 3107 #undef FILTER_EMIT 3108 #undef MCHASH_NWORDS 3109 #undef MCHASH_NWORDS_83815 3110 #undef MCHASH_NWORDS_83820 3111 3112 /* 3113 * Re-enable the receiver filter. 3114 */ 3115 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3116 } 3117 3118 /* 3119 * sip_dp83820_mii_readreg: [mii interface function] 3120 * 3121 * Read a PHY register on the MII of the DP83820. 3122 */ 3123 static int 3124 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3125 { 3126 struct sip_softc *sc = (void *) self; 3127 3128 if (sc->sc_cfg & CFG_TBI_EN) { 3129 bus_addr_t tbireg; 3130 int rv; 3131 3132 if (phy != 0) 3133 return (0); 3134 3135 switch (reg) { 3136 case MII_BMCR: tbireg = SIP_TBICR; break; 3137 case MII_BMSR: tbireg = SIP_TBISR; break; 3138 case MII_ANAR: tbireg = SIP_TANAR; break; 3139 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3140 case MII_ANER: tbireg = SIP_TANER; break; 3141 case MII_EXTSR: 3142 /* 3143 * Don't even bother reading the TESR register. 3144 * The manual documents that the device has 3145 * 1000baseX full/half capability, but the 3146 * register itself seems read back 0 on some 3147 * boards. Just hard-code the result. 3148 */ 3149 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3150 3151 default: 3152 return (0); 3153 } 3154 3155 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3156 if (tbireg == SIP_TBISR) { 3157 /* LINK and ACOMP are switched! */ 3158 int val = rv; 3159 3160 rv = 0; 3161 if (val & TBISR_MR_LINK_STATUS) 3162 rv |= BMSR_LINK; 3163 if (val & TBISR_MR_AN_COMPLETE) 3164 rv |= BMSR_ACOMP; 3165 3166 /* 3167 * The manual claims this register reads back 0 3168 * on hard and soft reset. But we want to let 3169 * the gentbi driver know that we support auto- 3170 * negotiation, so hard-code this bit in the 3171 * result. 3172 */ 3173 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3174 } 3175 3176 return (rv); 3177 } 3178 3179 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3180 } 3181 3182 /* 3183 * sip_dp83820_mii_writereg: [mii interface function] 3184 * 3185 * Write a PHY register on the MII of the DP83820. 3186 */ 3187 static void 3188 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3189 { 3190 struct sip_softc *sc = (void *) self; 3191 3192 if (sc->sc_cfg & CFG_TBI_EN) { 3193 bus_addr_t tbireg; 3194 3195 if (phy != 0) 3196 return; 3197 3198 switch (reg) { 3199 case MII_BMCR: tbireg = SIP_TBICR; break; 3200 case MII_ANAR: tbireg = SIP_TANAR; break; 3201 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3202 default: 3203 return; 3204 } 3205 3206 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3207 return; 3208 } 3209 3210 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3211 } 3212 3213 /* 3214 * sip_dp83820_mii_statchg: [mii interface function] 3215 * 3216 * Callback from MII layer when media changes. 3217 */ 3218 static void 3219 sipcom_dp83820_mii_statchg(struct device *self) 3220 { 3221 struct sip_softc *sc = (struct sip_softc *) self; 3222 struct mii_data *mii = &sc->sc_mii; 3223 u_int32_t cfg, pcr; 3224 3225 /* 3226 * Get flow control negotiation result. 3227 */ 3228 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3229 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3230 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3231 mii->mii_media_active &= ~IFM_ETH_FMASK; 3232 } 3233 3234 /* 3235 * Update TXCFG for full-duplex operation. 3236 */ 3237 if ((mii->mii_media_active & IFM_FDX) != 0) 3238 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3239 else 3240 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3241 3242 /* 3243 * Update RXCFG for full-duplex or loopback. 3244 */ 3245 if ((mii->mii_media_active & IFM_FDX) != 0 || 3246 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3247 sc->sc_rxcfg |= RXCFG_ATX; 3248 else 3249 sc->sc_rxcfg &= ~RXCFG_ATX; 3250 3251 /* 3252 * Update CFG for MII/GMII. 3253 */ 3254 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3255 cfg = sc->sc_cfg | CFG_MODE_1000; 3256 else 3257 cfg = sc->sc_cfg; 3258 3259 /* 3260 * 802.3x flow control. 3261 */ 3262 pcr = 0; 3263 if (sc->sc_flowflags & IFM_FLOW) { 3264 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3265 pcr |= sc->sc_rx_flow_thresh; 3266 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3267 pcr |= PCR_PSEN | PCR_PS_MCAST; 3268 } 3269 3270 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3271 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3272 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3273 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3274 } 3275 3276 /* 3277 * sip_mii_bitbang_read: [mii bit-bang interface function] 3278 * 3279 * Read the MII serial port for the MII bit-bang module. 3280 */ 3281 static u_int32_t 3282 sipcom_mii_bitbang_read(struct device *self) 3283 { 3284 struct sip_softc *sc = (void *) self; 3285 3286 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3287 } 3288 3289 /* 3290 * sip_mii_bitbang_write: [mii big-bang interface function] 3291 * 3292 * Write the MII serial port for the MII bit-bang module. 3293 */ 3294 static void 3295 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3296 { 3297 struct sip_softc *sc = (void *) self; 3298 3299 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3300 } 3301 3302 /* 3303 * sip_sis900_mii_readreg: [mii interface function] 3304 * 3305 * Read a PHY register on the MII. 3306 */ 3307 static int 3308 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3309 { 3310 struct sip_softc *sc = (struct sip_softc *) self; 3311 u_int32_t enphy; 3312 3313 /* 3314 * The PHY of recent SiS chipsets is accessed through bitbang 3315 * operations. 3316 */ 3317 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3318 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3319 phy, reg); 3320 3321 #ifndef SIS900_MII_RESTRICT 3322 /* 3323 * The SiS 900 has only an internal PHY on the MII. Only allow 3324 * MII address 0. 3325 */ 3326 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3327 return (0); 3328 #endif 3329 3330 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3331 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3332 ENPHY_RWCMD | ENPHY_ACCESS); 3333 do { 3334 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3335 } while (enphy & ENPHY_ACCESS); 3336 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3337 } 3338 3339 /* 3340 * sip_sis900_mii_writereg: [mii interface function] 3341 * 3342 * Write a PHY register on the MII. 3343 */ 3344 static void 3345 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3346 { 3347 struct sip_softc *sc = (struct sip_softc *) self; 3348 u_int32_t enphy; 3349 3350 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3351 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3352 phy, reg, val); 3353 return; 3354 } 3355 3356 #ifndef SIS900_MII_RESTRICT 3357 /* 3358 * The SiS 900 has only an internal PHY on the MII. Only allow 3359 * MII address 0. 3360 */ 3361 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3362 return; 3363 #endif 3364 3365 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3366 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3367 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3368 do { 3369 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3370 } while (enphy & ENPHY_ACCESS); 3371 } 3372 3373 /* 3374 * sip_sis900_mii_statchg: [mii interface function] 3375 * 3376 * Callback from MII layer when media changes. 3377 */ 3378 static void 3379 sipcom_sis900_mii_statchg(struct device *self) 3380 { 3381 struct sip_softc *sc = (struct sip_softc *) self; 3382 struct mii_data *mii = &sc->sc_mii; 3383 u_int32_t flowctl; 3384 3385 /* 3386 * Get flow control negotiation result. 3387 */ 3388 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3389 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3390 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3391 mii->mii_media_active &= ~IFM_ETH_FMASK; 3392 } 3393 3394 /* 3395 * Update TXCFG for full-duplex operation. 3396 */ 3397 if ((mii->mii_media_active & IFM_FDX) != 0) 3398 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3399 else 3400 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3401 3402 /* 3403 * Update RXCFG for full-duplex or loopback. 3404 */ 3405 if ((mii->mii_media_active & IFM_FDX) != 0 || 3406 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3407 sc->sc_rxcfg |= RXCFG_ATX; 3408 else 3409 sc->sc_rxcfg &= ~RXCFG_ATX; 3410 3411 /* 3412 * Update IMR for use of 802.3x flow control. 3413 */ 3414 if (sc->sc_flowflags & IFM_FLOW) { 3415 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3416 flowctl = FLOWCTL_FLOWEN; 3417 } else { 3418 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3419 flowctl = 0; 3420 } 3421 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3423 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3426 } 3427 3428 /* 3429 * sip_dp83815_mii_readreg: [mii interface function] 3430 * 3431 * Read a PHY register on the MII. 3432 */ 3433 static int 3434 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3435 { 3436 struct sip_softc *sc = (struct sip_softc *) self; 3437 u_int32_t val; 3438 3439 /* 3440 * The DP83815 only has an internal PHY. Only allow 3441 * MII address 0. 3442 */ 3443 if (phy != 0) 3444 return (0); 3445 3446 /* 3447 * Apparently, after a reset, the DP83815 can take a while 3448 * to respond. During this recovery period, the BMSR returns 3449 * a value of 0. Catch this -- it's not supposed to happen 3450 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3451 * PHY to come back to life. 3452 * 3453 * This works out because the BMSR is the first register 3454 * read during the PHY probe process. 3455 */ 3456 do { 3457 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3458 } while (reg == MII_BMSR && val == 0); 3459 3460 return (val & 0xffff); 3461 } 3462 3463 /* 3464 * sip_dp83815_mii_writereg: [mii interface function] 3465 * 3466 * Write a PHY register to the MII. 3467 */ 3468 static void 3469 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3470 { 3471 struct sip_softc *sc = (struct sip_softc *) self; 3472 3473 /* 3474 * The DP83815 only has an internal PHY. Only allow 3475 * MII address 0. 3476 */ 3477 if (phy != 0) 3478 return; 3479 3480 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3481 } 3482 3483 /* 3484 * sip_dp83815_mii_statchg: [mii interface function] 3485 * 3486 * Callback from MII layer when media changes. 3487 */ 3488 static void 3489 sipcom_dp83815_mii_statchg(struct device *self) 3490 { 3491 struct sip_softc *sc = (struct sip_softc *) self; 3492 3493 /* 3494 * Update TXCFG for full-duplex operation. 3495 */ 3496 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3497 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3498 else 3499 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3500 3501 /* 3502 * Update RXCFG for full-duplex or loopback. 3503 */ 3504 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3505 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3506 sc->sc_rxcfg |= RXCFG_ATX; 3507 else 3508 sc->sc_rxcfg &= ~RXCFG_ATX; 3509 3510 /* 3511 * XXX 802.3x flow control. 3512 */ 3513 3514 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXCFG, sc->sc_txcfg); 3515 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXCFG, sc->sc_rxcfg); 3516 3517 /* 3518 * Some DP83815s experience problems when used with short 3519 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3520 * sequence adjusts the DSP's signal attenuation to fix the 3521 * problem. 3522 */ 3523 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3524 uint32_t reg; 3525 3526 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3527 3528 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3529 reg &= 0x0fff; 3530 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3531 delay(100); 3532 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3533 reg &= 0x00ff; 3534 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3535 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3536 0x00e8); 3537 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3538 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3539 reg | 0x20); 3540 } 3541 3542 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3543 } 3544 } 3545 3546 static void 3547 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3548 const struct pci_attach_args *pa, u_int8_t *enaddr) 3549 { 3550 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3551 u_int8_t cksum, *e, match; 3552 int i; 3553 3554 /* 3555 * EEPROM data format for the DP83820 can be found in 3556 * the DP83820 manual, section 4.2.4. 3557 */ 3558 3559 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3560 3561 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3562 match = ~(match - 1); 3563 3564 cksum = 0x55; 3565 e = (u_int8_t *) eeprom_data; 3566 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3567 cksum += *e++; 3568 3569 if (cksum != match) 3570 printf("%s: Checksum (%x) mismatch (%x)", 3571 sc->sc_dev.dv_xname, cksum, match); 3572 3573 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3574 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3575 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3576 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3577 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3578 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3579 } 3580 3581 static void 3582 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3583 { 3584 int i; 3585 3586 /* 3587 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3588 * a reason, but I don't know it. 3589 */ 3590 for (i = 0; i < 10; i++) 3591 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3592 } 3593 3594 static void 3595 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3596 const struct pci_attach_args *pa, u_int8_t *enaddr) 3597 { 3598 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3599 3600 switch (sc->sc_rev) { 3601 case SIS_REV_630S: 3602 case SIS_REV_630E: 3603 case SIS_REV_630EA1: 3604 case SIS_REV_630ET: 3605 case SIS_REV_635: 3606 /* 3607 * The MAC address for the on-board Ethernet of 3608 * the SiS 630 chipset is in the NVRAM. Kick 3609 * the chip into re-loading it from NVRAM, and 3610 * read the MAC address out of the filter registers. 3611 */ 3612 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3613 3614 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3615 RFCR_RFADDR_NODE0); 3616 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3617 0xffff; 3618 3619 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3620 RFCR_RFADDR_NODE2); 3621 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3622 0xffff; 3623 3624 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3625 RFCR_RFADDR_NODE4); 3626 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3627 0xffff; 3628 break; 3629 3630 case SIS_REV_960: 3631 { 3632 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3633 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3634 3635 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3636 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3637 3638 int waittime, i; 3639 3640 /* Allow to read EEPROM from LAN. It is shared 3641 * between a 1394 controller and the NIC and each 3642 * time we access it, we need to set SIS_EECMD_REQ. 3643 */ 3644 SIS_SET_EROMAR(sc, EROMAR_REQ); 3645 3646 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3647 /* Force EEPROM to idle state. */ 3648 3649 /* 3650 * XXX-cube This is ugly. I'll look for docs about it. 3651 */ 3652 SIS_SET_EROMAR(sc, EROMAR_EECS); 3653 sipcom_sis900_eeprom_delay(sc); 3654 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3655 SIS_SET_EROMAR(sc, EROMAR_EESK); 3656 sipcom_sis900_eeprom_delay(sc); 3657 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3658 sipcom_sis900_eeprom_delay(sc); 3659 } 3660 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3661 sipcom_sis900_eeprom_delay(sc); 3662 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3663 3664 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3665 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3666 sizeof(myea) / sizeof(myea[0]), myea); 3667 break; 3668 } 3669 DELAY(1); 3670 } 3671 3672 /* 3673 * Set SIS_EECTL_CLK to high, so a other master 3674 * can operate on the i2c bus. 3675 */ 3676 SIS_SET_EROMAR(sc, EROMAR_EESK); 3677 3678 /* Refuse EEPROM access by LAN */ 3679 SIS_SET_EROMAR(sc, EROMAR_DONE); 3680 } break; 3681 3682 default: 3683 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3684 sizeof(myea) / sizeof(myea[0]), myea); 3685 } 3686 3687 enaddr[0] = myea[0] & 0xff; 3688 enaddr[1] = myea[0] >> 8; 3689 enaddr[2] = myea[1] & 0xff; 3690 enaddr[3] = myea[1] >> 8; 3691 enaddr[4] = myea[2] & 0xff; 3692 enaddr[5] = myea[2] >> 8; 3693 } 3694 3695 /* Table and macro to bit-reverse an octet. */ 3696 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3697 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3698 3699 static void 3700 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3701 const struct pci_attach_args *pa, u_int8_t *enaddr) 3702 { 3703 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3704 u_int8_t cksum, *e, match; 3705 int i; 3706 3707 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3708 sizeof(eeprom_data[0]), eeprom_data); 3709 3710 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3711 match = ~(match - 1); 3712 3713 cksum = 0x55; 3714 e = (u_int8_t *) eeprom_data; 3715 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3716 cksum += *e++; 3717 } 3718 if (cksum != match) { 3719 printf("%s: Checksum (%x) mismatch (%x)", 3720 sc->sc_dev.dv_xname, cksum, match); 3721 } 3722 3723 /* 3724 * Unrolled because it makes slightly more sense this way. 3725 * The DP83815 stores the MAC address in bit 0 of word 6 3726 * through bit 15 of word 8. 3727 */ 3728 ea = &eeprom_data[6]; 3729 enaddr[0] = ((*ea & 0x1) << 7); 3730 ea++; 3731 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3732 enaddr[1] = ((*ea & 0x1FE) >> 1); 3733 enaddr[2] = ((*ea & 0x1) << 7); 3734 ea++; 3735 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3736 enaddr[3] = ((*ea & 0x1FE) >> 1); 3737 enaddr[4] = ((*ea & 0x1) << 7); 3738 ea++; 3739 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3740 enaddr[5] = ((*ea & 0x1FE) >> 1); 3741 3742 /* 3743 * In case that's not weird enough, we also need to reverse 3744 * the bits in each byte. This all actually makes more sense 3745 * if you think about the EEPROM storage as an array of bits 3746 * being shifted into bytes, but that's not how we're looking 3747 * at it here... 3748 */ 3749 for (i = 0; i < 6 ;i++) 3750 enaddr[i] = bbr(enaddr[i]); 3751 } 3752 3753 /* 3754 * sip_mediastatus: [ifmedia interface function] 3755 * 3756 * Get the current interface media status. 3757 */ 3758 static void 3759 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3760 { 3761 struct sip_softc *sc = ifp->if_softc; 3762 3763 mii_pollstat(&sc->sc_mii); 3764 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3765 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3766 sc->sc_flowflags; 3767 } 3768 3769 /* 3770 * sip_mediachange: [ifmedia interface function] 3771 * 3772 * Set hardware to newly-selected media. 3773 */ 3774 static int 3775 sipcom_mediachange(struct ifnet *ifp) 3776 { 3777 struct sip_softc *sc = ifp->if_softc; 3778 3779 if (ifp->if_flags & IFF_UP) 3780 mii_mediachg(&sc->sc_mii); 3781 return (0); 3782 } 3783
Indexes created Tue Sep 30 11:09:46 GMT 2025