if_sip.c revision 1.122
1 /* $NetBSD: if_sip.c,v 1.122 2007/12/15 21:51:45 he Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.122 2007/12/15 21:51:45 he Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 /* 130 * Transmit descriptor list size. This is arbitrary, but allocate 131 * enough descriptors for 128 pending transmissions, and 8 segments 132 * per packet (64 for DP83820 for jumbo frames). 133 * 134 * This MUST work out to a power of 2. 135 */ 136 #define GSIP_NTXSEGS_ALLOC 16 137 #define SIP_NTXSEGS_ALLOC 8 138 139 #define SIP_TXQUEUELEN 256 140 #define MAX_SIP_NTXDESC \ 141 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer per incoming 145 * packet, so this logic is a little simpler. 146 * 147 * Actually, on the DP83820, we allow the packet to consume more than 148 * one buffer, in order to support jumbo Ethernet frames. In that 149 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 150 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 151 * so we'd better be quick about handling receive interrupts. 152 */ 153 #define GSIP_NRXDESC 256 154 #define SIP_NRXDESC 128 155 156 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 157 158 /* 159 * Control structures are DMA'd to the SiS900 chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct sip_control_data { 164 /* 165 * The transmit descriptors. 166 */ 167 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 168 169 /* 170 * The receive descriptors. 171 */ 172 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 173 }; 174 175 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 176 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 177 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 178 179 /* 180 * Software state for transmit jobs. 181 */ 182 struct sip_txsoft { 183 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t txs_dmamap; /* our DMA map */ 185 int txs_firstdesc; /* first descriptor in packet */ 186 int txs_lastdesc; /* last descriptor in packet */ 187 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 188 }; 189 190 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 191 192 /* 193 * Software state for receive jobs. 194 */ 195 struct sip_rxsoft { 196 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t rxs_dmamap; /* our DMA map */ 198 }; 199 200 enum sip_attach_stage { 201 SIP_ATTACH_FIN = 0 202 , SIP_ATTACH_CREATE_RXMAP 203 , SIP_ATTACH_CREATE_TXMAP 204 , SIP_ATTACH_LOAD_MAP 205 , SIP_ATTACH_CREATE_MAP 206 , SIP_ATTACH_MAP_MEM 207 , SIP_ATTACH_ALLOC_MEM 208 , SIP_ATTACH_INTR 209 , SIP_ATTACH_MAP 210 }; 211 212 /* 213 * Software state per device. 214 */ 215 struct sip_softc { 216 struct device sc_dev; /* generic device information */ 217 bus_space_tag_t sc_st; /* bus space tag */ 218 bus_space_handle_t sc_sh; /* bus space handle */ 219 bus_size_t sc_sz; /* bus space size */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t sc_pc; 222 bus_dma_segment_t sc_seg; 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_gigabit; /* 1: 83820, 0: other */ 228 int sc_rev; /* chip revision */ 229 230 void *sc_ih; /* interrupt cookie */ 231 232 struct mii_data sc_mii; /* MII/media information */ 233 234 callout_t sc_tick_ch; /* tick callout */ 235 236 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 237 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 238 239 /* 240 * Software state for transmit and receive descriptors. 241 */ 242 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 243 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 244 245 /* 246 * Control data structures. 247 */ 248 struct sip_control_data *sc_control_data; 249 #define sc_txdescs sc_control_data->scd_txdescs 250 #define sc_rxdescs sc_control_data->scd_rxdescs 251 252 #ifdef SIP_EVENT_COUNTERS 253 /* 254 * Event counters. 255 */ 256 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 257 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 258 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 259 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 260 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 261 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 262 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 263 struct evcnt sc_ev_rxpause; /* PAUSE received */ 264 /* DP83820 only */ 265 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* SIP_EVENT_COUNTERS */ 273 274 u_int32_t sc_txcfg; /* prototype TXCFG register */ 275 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 276 u_int32_t sc_imr; /* prototype IMR register */ 277 u_int32_t sc_rfcr; /* prototype RFCR register */ 278 279 u_int32_t sc_cfg; /* prototype CFG register */ 280 281 u_int32_t sc_gpior; /* prototype GPIOR register */ 282 283 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 284 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 285 286 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 287 288 int sc_flowflags; /* 802.3x flow control flags */ 289 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 290 int sc_paused; /* paused indication */ 291 292 int sc_txfree; /* number of free Tx descriptors */ 293 int sc_txnext; /* next ready Tx descriptor */ 294 int sc_txwin; /* Tx descriptors since last intr */ 295 296 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 297 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 298 299 /* values of interface state at last init */ 300 struct { 301 /* if_capenable */ 302 uint64_t if_capenable; 303 /* ec_capenable */ 304 int ec_capenable; 305 /* VLAN_ATTACHED */ 306 int is_vlan; 307 } sc_prev; 308 309 short sc_if_flags; 310 311 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 312 int sc_rxdiscard; 313 int sc_rxlen; 314 struct mbuf *sc_rxhead; 315 struct mbuf *sc_rxtail; 316 struct mbuf **sc_rxtailp; 317 318 int sc_ntxdesc; 319 int sc_ntxdesc_mask; 320 321 int sc_nrxdesc_mask; 322 323 const struct sip_parm { 324 const struct sip_regs { 325 int r_rxcfg; 326 int r_txcfg; 327 } p_regs; 328 329 const struct sip_bits { 330 uint32_t b_txcfg_mxdma_8; 331 uint32_t b_txcfg_mxdma_16; 332 uint32_t b_txcfg_mxdma_32; 333 uint32_t b_txcfg_mxdma_64; 334 uint32_t b_txcfg_mxdma_128; 335 uint32_t b_txcfg_mxdma_256; 336 uint32_t b_txcfg_mxdma_512; 337 uint32_t b_txcfg_flth_mask; 338 uint32_t b_txcfg_drth_mask; 339 340 uint32_t b_rxcfg_mxdma_8; 341 uint32_t b_rxcfg_mxdma_16; 342 uint32_t b_rxcfg_mxdma_32; 343 uint32_t b_rxcfg_mxdma_64; 344 uint32_t b_rxcfg_mxdma_128; 345 uint32_t b_rxcfg_mxdma_256; 346 uint32_t b_rxcfg_mxdma_512; 347 348 uint32_t b_isr_txrcmp; 349 uint32_t b_isr_rxrcmp; 350 uint32_t b_isr_dperr; 351 uint32_t b_isr_sserr; 352 uint32_t b_isr_rmabt; 353 uint32_t b_isr_rtabt; 354 355 uint32_t b_cmdsts_size_mask; 356 } p_bits; 357 int p_filtmem; 358 int p_rxbuf_len; 359 bus_size_t p_tx_dmamap_size; 360 int p_ntxsegs; 361 int p_ntxsegs_alloc; 362 int p_nrxdesc; 363 } *sc_parm; 364 365 void (*sc_rxintr)(struct sip_softc *); 366 367 #if NRND > 0 368 rndsource_element_t rnd_source; /* random source */ 369 #endif 370 }; 371 372 #define sc_bits sc_parm->p_bits 373 #define sc_regs sc_parm->p_regs 374 375 static const struct sip_parm sip_parm = { 376 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 377 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 378 , .p_tx_dmamap_size = MCLBYTES 379 , .p_ntxsegs = 16 380 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 381 , .p_nrxdesc = SIP_NRXDESC 382 , .p_bits = { 383 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 384 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 385 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 386 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 387 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 388 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 389 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 390 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 391 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 392 393 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 394 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 395 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 396 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 397 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 398 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 399 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 400 401 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 402 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 403 , .b_isr_dperr = 0x00800000 /* detected parity error */ 404 , .b_isr_sserr = 0x00400000 /* signalled system error */ 405 , .b_isr_rmabt = 0x00200000 /* received master abort */ 406 , .b_isr_rtabt = 0x00100000 /* received target abort */ 407 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 408 } 409 , .p_regs = { 410 .r_rxcfg = OTHER_SIP_RXCFG, 411 .r_txcfg = OTHER_SIP_TXCFG 412 } 413 }, gsip_parm = { 414 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 415 , .p_rxbuf_len = MCLBYTES - 8 416 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 417 , .p_ntxsegs = 64 418 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 419 , .p_nrxdesc = GSIP_NRXDESC 420 , .p_bits = { 421 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 422 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 423 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 424 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 425 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 426 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 427 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 428 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 429 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 430 431 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 432 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 433 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 434 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 435 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 436 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 437 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 438 439 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 440 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 441 , .b_isr_dperr = 0x00100000 /* detected parity error */ 442 , .b_isr_sserr = 0x00080000 /* signalled system error */ 443 , .b_isr_rmabt = 0x00040000 /* received master abort */ 444 , .b_isr_rtabt = 0x00020000 /* received target abort */ 445 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 446 } 447 , .p_regs = { 448 .r_rxcfg = DP83820_SIP_RXCFG, 449 .r_txcfg = DP83820_SIP_TXCFG 450 } 451 }; 452 453 static inline int 454 sip_nexttx(const struct sip_softc *sc, int x) 455 { 456 return (x + 1) & sc->sc_ntxdesc_mask; 457 } 458 459 static inline int 460 sip_nextrx(const struct sip_softc *sc, int x) 461 { 462 return (x + 1) & sc->sc_nrxdesc_mask; 463 } 464 465 /* 83820 only */ 466 #define SIP_RXCHAIN_RESET(sc) \ 467 do { \ 468 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 469 *(sc)->sc_rxtailp = NULL; \ 470 (sc)->sc_rxlen = 0; \ 471 } while (/*CONSTCOND*/0) 472 473 /* 83820 only */ 474 #define SIP_RXCHAIN_LINK(sc, m) \ 475 do { \ 476 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 477 (sc)->sc_rxtailp = &(m)->m_next; \ 478 } while (/*CONSTCOND*/0) 479 480 #ifdef SIP_EVENT_COUNTERS 481 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 482 #else 483 #define SIP_EVCNT_INCR(ev) /* nothing */ 484 #endif 485 486 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 487 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 488 489 #define SIP_CDTXSYNC(sc, x, n, ops) \ 490 do { \ 491 int __x, __n; \ 492 \ 493 __x = (x); \ 494 __n = (n); \ 495 \ 496 /* If it will wrap around, sync to the end of the ring. */ \ 497 if ((__x + __n) > sc->sc_ntxdesc) { \ 498 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 499 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 500 (sc->sc_ntxdesc - __x), (ops)); \ 501 __n -= (sc->sc_ntxdesc - __x); \ 502 __x = 0; \ 503 } \ 504 \ 505 /* Now sync whatever is left. */ \ 506 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 507 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 508 } while (0) 509 510 #define SIP_CDRXSYNC(sc, x, ops) \ 511 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 512 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 513 514 #if 0 515 #ifdef DP83820 516 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 #else 519 u_int32_t sipd_cmdsts; /* command/status word */ 520 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 521 #endif /* DP83820 */ 522 #endif /* 0 */ 523 524 static inline volatile uint32_t * 525 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 526 { 527 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 528 } 529 530 static inline volatile uint32_t * 531 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 532 { 533 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 534 } 535 536 static inline void 537 SIP_INIT_RXDESC(struct sip_softc *sc, int x) 538 { 539 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 540 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 541 542 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 543 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 544 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 545 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 546 sipd->sipd_extsts = 0; 547 SIP_CDRXSYNC(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 548 } 549 550 #define SIP_CHIP_VERS(sc, v, p, r) \ 551 ((sc)->sc_model->sip_vendor == (v) && \ 552 (sc)->sc_model->sip_product == (p) && \ 553 (sc)->sc_rev == (r)) 554 555 #define SIP_CHIP_MODEL(sc, v, p) \ 556 ((sc)->sc_model->sip_vendor == (v) && \ 557 (sc)->sc_model->sip_product == (p)) 558 559 #define SIP_SIS900_REV(sc, rev) \ 560 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 561 562 #define SIP_TIMEOUT 1000 563 564 static void sipcom_start(struct ifnet *); 565 static void sipcom_watchdog(struct ifnet *); 566 static int sipcom_ioctl(struct ifnet *, u_long, void *); 567 static int sipcom_init(struct ifnet *); 568 static void sipcom_stop(struct ifnet *, int); 569 570 static void sipcom_shutdown(void *); 571 572 static bool sipcom_reset(struct sip_softc *); 573 static void sipcom_rxdrain(struct sip_softc *); 574 static int sipcom_add_rxbuf(struct sip_softc *, int); 575 static void sipcom_read_eeprom(struct sip_softc *, int, int, 576 u_int16_t *); 577 static void sipcom_tick(void *); 578 579 static void sipcom_sis900_set_filter(struct sip_softc *); 580 static void sipcom_dp83815_set_filter(struct sip_softc *); 581 582 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 585 static void sipcom_sis900_read_macaddr(struct sip_softc *, 586 const struct pci_attach_args *, u_int8_t *); 587 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 588 const struct pci_attach_args *, u_int8_t *); 589 590 static int sipcom_intr(void *); 591 static void sipcom_txintr(struct sip_softc *); 592 static void sip_rxintr(struct sip_softc *); 593 static void gsip_rxintr(struct sip_softc *); 594 595 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 596 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 597 static void sipcom_dp83820_mii_statchg(struct device *); 598 599 static int sipcom_sis900_mii_readreg(struct device *, int, int); 600 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 601 static void sipcom_sis900_mii_statchg(struct device *); 602 603 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 604 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 605 static void sipcom_dp83815_mii_statchg(struct device *); 606 607 static int sipcom_mediachange(struct ifnet *); 608 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 609 610 static int sipcom_match(struct device *, struct cfdata *, void *); 611 static void sipcom_attach(struct device *, struct device *, void *); 612 static void sipcom_do_detach(device_t, enum sip_attach_stage); 613 static int sipcom_detach(device_t, int); 614 static bool sipcom_resume(device_t); 615 616 static int gsip_copy_small = 0; /* XXX make non-static! */ 617 #ifdef __NO_STRICT_ALIGNMENT 618 static int sip_copy_small = 0; /* XXX make non-static! */ 619 #endif 620 621 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 622 sipcom_match, sipcom_attach, sipcom_detach, NULL); 623 CFATTACH_DECL(sip, sizeof(struct sip_softc), 624 sipcom_match, sipcom_attach, sipcom_detach, NULL); 625 626 /* 627 * Descriptions of the variants of the SiS900. 628 */ 629 struct sip_variant { 630 int (*sipv_mii_readreg)(struct device *, int, int); 631 void (*sipv_mii_writereg)(struct device *, int, int, int); 632 void (*sipv_mii_statchg)(struct device *); 633 void (*sipv_set_filter)(struct sip_softc *); 634 void (*sipv_read_macaddr)(struct sip_softc *, 635 const struct pci_attach_args *, u_int8_t *); 636 }; 637 638 static u_int32_t sipcom_mii_bitbang_read(struct device *); 639 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 640 641 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 642 sipcom_mii_bitbang_read, 643 sipcom_mii_bitbang_write, 644 { 645 EROMAR_MDIO, /* MII_BIT_MDO */ 646 EROMAR_MDIO, /* MII_BIT_MDI */ 647 EROMAR_MDC, /* MII_BIT_MDC */ 648 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 649 0, /* MII_BIT_DIR_PHY_HOST */ 650 } 651 }; 652 653 static const struct sip_variant sipcom_variant_dp83820 = { 654 sipcom_dp83820_mii_readreg, 655 sipcom_dp83820_mii_writereg, 656 sipcom_dp83820_mii_statchg, 657 sipcom_dp83815_set_filter, 658 sipcom_dp83820_read_macaddr, 659 }; 660 661 static const struct sip_variant sipcom_variant_sis900 = { 662 sipcom_sis900_mii_readreg, 663 sipcom_sis900_mii_writereg, 664 sipcom_sis900_mii_statchg, 665 sipcom_sis900_set_filter, 666 sipcom_sis900_read_macaddr, 667 }; 668 669 static const struct sip_variant sipcom_variant_dp83815 = { 670 sipcom_dp83815_mii_readreg, 671 sipcom_dp83815_mii_writereg, 672 sipcom_dp83815_mii_statchg, 673 sipcom_dp83815_set_filter, 674 sipcom_dp83815_read_macaddr, 675 }; 676 677 678 /* 679 * Devices supported by this driver. 680 */ 681 static const struct sip_product { 682 pci_vendor_id_t sip_vendor; 683 pci_product_id_t sip_product; 684 const char *sip_name; 685 const struct sip_variant *sip_variant; 686 int sip_gigabit; 687 } sipcom_products[] = { 688 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 689 "NatSemi DP83820 Gigabit Ethernet", 690 &sipcom_variant_dp83820, 1 }, 691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 692 "SiS 900 10/100 Ethernet", 693 &sipcom_variant_sis900, 0 }, 694 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 695 "SiS 7016 10/100 Ethernet", 696 &sipcom_variant_sis900, 0 }, 697 698 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 699 "NatSemi DP83815 10/100 Ethernet", 700 &sipcom_variant_dp83815, 0 }, 701 702 { 0, 0, 703 NULL, 704 NULL, 0 }, 705 }; 706 707 static const struct sip_product * 708 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 709 { 710 const struct sip_product *sip; 711 712 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 713 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 714 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 715 sip->sip_gigabit == gigabit) 716 return sip; 717 } 718 return NULL; 719 } 720 721 /* 722 * I really hate stupid hardware vendors. There's a bit in the EEPROM 723 * which indicates if the card can do 64-bit data transfers. Unfortunately, 724 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 725 * which means we try to use 64-bit data transfers on those cards if we 726 * happen to be plugged into a 32-bit slot. 727 * 728 * What we do is use this table of cards known to be 64-bit cards. If 729 * you have a 64-bit card who's subsystem ID is not listed in this table, 730 * send the output of "pcictl dump ..." of the device to me so that your 731 * card will use the 64-bit data path when plugged into a 64-bit slot. 732 * 733 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 734 * June 30, 2002 735 */ 736 static int 737 sipcom_check_64bit(const struct pci_attach_args *pa) 738 { 739 static const struct { 740 pci_vendor_id_t c64_vendor; 741 pci_product_id_t c64_product; 742 } card64[] = { 743 /* Asante GigaNIX */ 744 { 0x128a, 0x0002 }, 745 746 /* Accton EN1407-T, Planex GN-1000TE */ 747 { 0x1113, 0x1407 }, 748 749 /* Netgear GA-621 */ 750 { 0x1385, 0x621a }, 751 752 /* SMC EZ Card */ 753 { 0x10b8, 0x9462 }, 754 755 { 0, 0} 756 }; 757 pcireg_t subsys; 758 int i; 759 760 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 761 762 for (i = 0; card64[i].c64_vendor != 0; i++) { 763 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 764 PCI_PRODUCT(subsys) == card64[i].c64_product) 765 return (1); 766 } 767 768 return (0); 769 } 770 771 static int 772 sipcom_match(struct device *parent, struct cfdata *cf, void *aux) 773 { 774 struct pci_attach_args *pa = aux; 775 776 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 777 return 1; 778 779 return 0; 780 } 781 782 static void 783 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 784 { 785 u_int32_t reg; 786 int i; 787 788 /* 789 * Cause the chip to load configuration data from the EEPROM. 790 */ 791 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 792 for (i = 0; i < 10000; i++) { 793 delay(10); 794 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 795 PTSCR_EELOAD_EN) == 0) 796 break; 797 } 798 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 799 PTSCR_EELOAD_EN) { 800 printf("%s: timeout loading configuration from EEPROM\n", 801 sc->sc_dev.dv_xname); 802 return; 803 } 804 805 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 806 807 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 808 if (reg & CFG_PCI64_DET) { 809 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 810 /* 811 * Check to see if this card is 64-bit. If so, enable 64-bit 812 * data transfers. 813 * 814 * We can't use the DATA64_EN bit in the EEPROM, because 815 * vendors of 32-bit cards fail to clear that bit in many 816 * cases (yet the card still detects that it's in a 64-bit 817 * slot; go figure). 818 */ 819 if (sipcom_check_64bit(pa)) { 820 sc->sc_cfg |= CFG_DATA64_EN; 821 printf(", using 64-bit data transfers"); 822 } 823 printf("\n"); 824 } 825 826 /* 827 * XXX Need some PCI flags indicating support for 828 * XXX 64-bit addressing. 829 */ 830 #if 0 831 if (reg & CFG_M64ADDR) 832 sc->sc_cfg |= CFG_M64ADDR; 833 if (reg & CFG_T64ADDR) 834 sc->sc_cfg |= CFG_T64ADDR; 835 #endif 836 837 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 838 const char *sep = ""; 839 printf("%s: using ", sc->sc_dev.dv_xname); 840 if (reg & CFG_EXT_125) { 841 sc->sc_cfg |= CFG_EXT_125; 842 printf("%s125MHz clock", sep); 843 sep = ", "; 844 } 845 if (reg & CFG_TBI_EN) { 846 sc->sc_cfg |= CFG_TBI_EN; 847 printf("%sten-bit interface", sep); 848 sep = ", "; 849 } 850 printf("\n"); 851 } 852 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 853 (reg & CFG_MRM_DIS) != 0) 854 sc->sc_cfg |= CFG_MRM_DIS; 855 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 856 (reg & CFG_MWI_DIS) != 0) 857 sc->sc_cfg |= CFG_MWI_DIS; 858 859 /* 860 * Use the extended descriptor format on the DP83820. This 861 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 862 * checksumming. 863 */ 864 sc->sc_cfg |= CFG_EXTSTS_EN; 865 } 866 867 static int 868 sipcom_detach(device_t self, int flags) 869 { 870 int s; 871 872 s = splnet(); 873 sipcom_do_detach(self, SIP_ATTACH_FIN); 874 splx(s); 875 876 return 0; 877 } 878 879 static void 880 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 881 { 882 int i; 883 struct sip_softc *sc = device_private(self); 884 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 885 886 /* 887 * Free any resources we've allocated during attach. 888 * Do this in reverse order and fall through. 889 */ 890 switch (stage) { 891 case SIP_ATTACH_FIN: 892 sipcom_stop(ifp, 1); 893 pmf_device_deregister(self); 894 #ifdef SIP_EVENT_COUNTERS 895 /* 896 * Attach event counters. 897 */ 898 evcnt_detach(&sc->sc_ev_txforceintr); 899 evcnt_detach(&sc->sc_ev_txdstall); 900 evcnt_detach(&sc->sc_ev_txsstall); 901 evcnt_detach(&sc->sc_ev_hiberr); 902 evcnt_detach(&sc->sc_ev_rxintr); 903 evcnt_detach(&sc->sc_ev_txiintr); 904 evcnt_detach(&sc->sc_ev_txdintr); 905 if (!sc->sc_gigabit) { 906 evcnt_detach(&sc->sc_ev_rxpause); 907 } else { 908 evcnt_detach(&sc->sc_ev_txudpsum); 909 evcnt_detach(&sc->sc_ev_txtcpsum); 910 evcnt_detach(&sc->sc_ev_txipsum); 911 evcnt_detach(&sc->sc_ev_rxudpsum); 912 evcnt_detach(&sc->sc_ev_rxtcpsum); 913 evcnt_detach(&sc->sc_ev_rxipsum); 914 evcnt_detach(&sc->sc_ev_txpause); 915 evcnt_detach(&sc->sc_ev_rxpause); 916 } 917 #endif /* SIP_EVENT_COUNTERS */ 918 919 #if NRND > 0 920 rnd_detach_source(&sc->rnd_source); 921 #endif 922 923 ether_ifdetach(ifp); 924 if_detach(ifp); 925 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 926 927 if (sc->sc_sdhook != NULL) 928 shutdownhook_disestablish(sc->sc_sdhook); 929 930 /*FALLTHROUGH*/ 931 case SIP_ATTACH_CREATE_RXMAP: 932 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 933 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 934 bus_dmamap_destroy(sc->sc_dmat, 935 sc->sc_rxsoft[i].rxs_dmamap); 936 } 937 /*FALLTHROUGH*/ 938 case SIP_ATTACH_CREATE_TXMAP: 939 for (i = 0; i < SIP_TXQUEUELEN; i++) { 940 if (sc->sc_txsoft[i].txs_dmamap != NULL) 941 bus_dmamap_destroy(sc->sc_dmat, 942 sc->sc_txsoft[i].txs_dmamap); 943 } 944 /*FALLTHROUGH*/ 945 case SIP_ATTACH_LOAD_MAP: 946 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 947 /*FALLTHROUGH*/ 948 case SIP_ATTACH_CREATE_MAP: 949 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 950 /*FALLTHROUGH*/ 951 case SIP_ATTACH_MAP_MEM: 952 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 953 sizeof(struct sip_control_data)); 954 /*FALLTHROUGH*/ 955 case SIP_ATTACH_ALLOC_MEM: 956 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 957 /* FALLTHROUGH*/ 958 case SIP_ATTACH_INTR: 959 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 960 /* FALLTHROUGH*/ 961 case SIP_ATTACH_MAP: 962 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 963 break; 964 default: 965 break; 966 } 967 return; 968 } 969 970 static bool 971 sipcom_resume(device_t self) 972 { 973 struct sip_softc *sc = device_private(self); 974 975 return sipcom_reset(sc); 976 } 977 978 static void 979 sipcom_attach(device_t parent, device_t self, void *aux) 980 { 981 struct sip_softc *sc = (struct sip_softc *) self; 982 struct pci_attach_args *pa = aux; 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 pci_chipset_tag_t pc = pa->pa_pc; 985 pci_intr_handle_t ih; 986 const char *intrstr = NULL; 987 bus_space_tag_t iot, memt; 988 bus_space_handle_t ioh, memh; 989 bus_size_t iosz, memsz; 990 int ioh_valid, memh_valid; 991 int i, rseg, error; 992 const struct sip_product *sip; 993 u_int8_t enaddr[ETHER_ADDR_LEN]; 994 pcireg_t pmreg; 995 pcireg_t memtype; 996 bus_size_t tx_dmamap_size; 997 int ntxsegs_alloc; 998 cfdata_t cf = device_cfdata(self); 999 1000 callout_init(&sc->sc_tick_ch, 0); 1001 1002 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1003 if (sip == NULL) { 1004 printf("\n"); 1005 panic("%s: impossible", __func__); 1006 } 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1027 1028 sc->sc_model = sip; 1029 1030 /* 1031 * XXX Work-around broken PXE firmware on some boards. 1032 * 1033 * The DP83815 shares an address decoder with the MEM BAR 1034 * and the ROM BAR. Make sure the ROM BAR is disabled, 1035 * so that memory mapped access works. 1036 */ 1037 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1038 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1039 ~PCI_MAPREG_ROM_ENABLE); 1040 1041 /* 1042 * Map the device. 1043 */ 1044 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1045 PCI_MAPREG_TYPE_IO, 0, 1046 &iot, &ioh, NULL, &iosz) == 0); 1047 if (sc->sc_gigabit) { 1048 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1049 switch (memtype) { 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1052 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1053 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1054 break; 1055 default: 1056 memh_valid = 0; 1057 } 1058 } else { 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1061 &memt, &memh, NULL, &memsz) == 0); 1062 } 1063 1064 if (memh_valid) { 1065 sc->sc_st = memt; 1066 sc->sc_sh = memh; 1067 sc->sc_sz = memsz; 1068 } else if (ioh_valid) { 1069 sc->sc_st = iot; 1070 sc->sc_sh = ioh; 1071 sc->sc_sz = iosz; 1072 } else { 1073 printf("%s: unable to map device registers\n", 1074 sc->sc_dev.dv_xname); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 pmreg | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1092 NULL)) && error != EOPNOTSUPP) { 1093 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 1094 error); 1095 return; 1096 } 1097 1098 /* 1099 * Map and establish our interrupt. 1100 */ 1101 if (pci_intr_map(pa, &ih)) { 1102 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 1103 return; 1104 } 1105 intrstr = pci_intr_string(pc, ih); 1106 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1107 if (sc->sc_ih == NULL) { 1108 printf("%s: unable to establish interrupt", 1109 sc->sc_dev.dv_xname); 1110 if (intrstr != NULL) 1111 printf(" at %s", intrstr); 1112 printf("\n"); 1113 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1114 } 1115 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1116 1117 SIMPLEQ_INIT(&sc->sc_txfreeq); 1118 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1119 1120 /* 1121 * Allocate the control data structures, and create and load the 1122 * DMA map for it. 1123 */ 1124 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1125 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1126 &rseg, 0)) != 0) { 1127 printf("%s: unable to allocate control data, error = %d\n", 1128 sc->sc_dev.dv_xname, error); 1129 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1133 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1134 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1135 printf("%s: unable to map control data, error = %d\n", 1136 sc->sc_dev.dv_xname, error); 1137 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1138 } 1139 1140 if ((error = bus_dmamap_create(sc->sc_dmat, 1141 sizeof(struct sip_control_data), 1, 1142 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1143 printf("%s: unable to create control data DMA map, " 1144 "error = %d\n", sc->sc_dev.dv_xname, error); 1145 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1146 } 1147 1148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1149 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1150 0)) != 0) { 1151 printf("%s: unable to load control data DMA map, error = %d\n", 1152 sc->sc_dev.dv_xname, error); 1153 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1154 } 1155 1156 /* 1157 * Create the transmit buffer DMA maps. 1158 */ 1159 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1160 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1161 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1162 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1163 printf("%s: unable to create tx DMA map %d, " 1164 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1165 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1166 } 1167 } 1168 1169 /* 1170 * Create the receive buffer DMA maps. 1171 */ 1172 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1173 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1174 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1175 printf("%s: unable to create rx DMA map %d, " 1176 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1177 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1178 } 1179 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1180 } 1181 1182 /* 1183 * Reset the chip to a known state. 1184 */ 1185 sipcom_reset(sc); 1186 1187 /* 1188 * Read the Ethernet address from the EEPROM. This might 1189 * also fetch other stuff from the EEPROM and stash it 1190 * in the softc. 1191 */ 1192 sc->sc_cfg = 0; 1193 if (!sc->sc_gigabit) { 1194 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1195 SIP_SIS900_REV(sc,SIS_REV_900B)) 1196 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1197 1198 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1199 SIP_SIS900_REV(sc,SIS_REV_960) || 1200 SIP_SIS900_REV(sc,SIS_REV_900B)) 1201 sc->sc_cfg |= 1202 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1203 CFG_EDBMASTEN); 1204 } 1205 1206 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1207 1208 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1209 ether_sprintf(enaddr)); 1210 1211 /* 1212 * Initialize the configuration register: aggressive PCI 1213 * bus request algorithm, default backoff, default OW timer, 1214 * default parity error detection. 1215 * 1216 * NOTE: "Big endian mode" is useless on the SiS900 and 1217 * friends -- it affects packet data, not descriptors. 1218 */ 1219 if (sc->sc_gigabit) 1220 sipcom_dp83820_attach(sc, pa); 1221 1222 /* 1223 * Initialize our media structures and probe the MII. 1224 */ 1225 sc->sc_mii.mii_ifp = ifp; 1226 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1227 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1228 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1229 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sipcom_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1244 } else 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 ether_ifattach(ifp, enaddr); 1287 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1288 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1289 sc->sc_prev.if_capenable = ifp->if_capenable; 1290 #if NRND > 0 1291 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1292 RND_TYPE_NET, 0); 1293 #endif 1294 1295 /* 1296 * The number of bytes that must be available in 1297 * the Tx FIFO before the bus master can DMA more 1298 * data into the FIFO. 1299 */ 1300 sc->sc_tx_fill_thresh = 64 / 32; 1301 1302 /* 1303 * Start at a drain threshold of 512 bytes. We will 1304 * increase it if a DMA underrun occurs. 1305 * 1306 * XXX The minimum value of this variable should be 1307 * tuned. We may be able to improve performance 1308 * by starting with a lower value. That, however, 1309 * may trash the first few outgoing packets if the 1310 * PCI bus is saturated. 1311 */ 1312 if (sc->sc_gigabit) 1313 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1314 else 1315 sc->sc_tx_drain_thresh = 1504 / 32; 1316 1317 /* 1318 * Initialize the Rx FIFO drain threshold. 1319 * 1320 * This is in units of 8 bytes. 1321 * 1322 * We should never set this value lower than 2; 14 bytes are 1323 * required to filter the packet. 1324 */ 1325 sc->sc_rx_drain_thresh = 128 / 8; 1326 1327 #ifdef SIP_EVENT_COUNTERS 1328 /* 1329 * Attach event counters. 1330 */ 1331 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1332 NULL, sc->sc_dev.dv_xname, "txsstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1334 NULL, sc->sc_dev.dv_xname, "txdstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1336 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1338 NULL, sc->sc_dev.dv_xname, "txdintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1340 NULL, sc->sc_dev.dv_xname, "txiintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1342 NULL, sc->sc_dev.dv_xname, "rxintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1344 NULL, sc->sc_dev.dv_xname, "hiberr"); 1345 if (!sc->sc_gigabit) { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1347 NULL, sc->sc_dev.dv_xname, "rxpause"); 1348 } else { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1350 NULL, sc->sc_dev.dv_xname, "rxpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1352 NULL, sc->sc_dev.dv_xname, "txpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1354 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1356 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1358 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1360 NULL, sc->sc_dev.dv_xname, "txipsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1362 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1364 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1365 } 1366 #endif /* SIP_EVENT_COUNTERS */ 1367 1368 if (!pmf_device_register(self, NULL, sipcom_resume)) 1369 aprint_error_dev(self, "couldn't establish power handler\n"); 1370 else 1371 pmf_class_network_register(self, ifp); 1372 1373 /* 1374 * Make sure the interface is shutdown during reboot. 1375 */ 1376 sc->sc_sdhook = shutdownhook_establish(sipcom_shutdown, sc); 1377 if (sc->sc_sdhook == NULL) 1378 printf("%s: WARNING: unable to establish shutdown hook\n", 1379 sc->sc_dev.dv_xname); 1380 } 1381 1382 /* 1383 * sip_shutdown: 1384 * 1385 * Make sure the interface is stopped at reboot time. 1386 */ 1387 static void 1388 sipcom_shutdown(void *arg) 1389 { 1390 struct sip_softc *sc = arg; 1391 1392 sipcom_stop(&sc->sc_ethercom.ec_if, 1); 1393 } 1394 1395 static inline void 1396 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1397 uint64_t capenable) 1398 { 1399 struct m_tag *mtag; 1400 u_int32_t extsts; 1401 #ifdef DEBUG 1402 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1403 #endif 1404 /* 1405 * If VLANs are enabled and the packet has a VLAN tag, set 1406 * up the descriptor to encapsulate the packet for us. 1407 * 1408 * This apparently has to be on the last descriptor of 1409 * the packet. 1410 */ 1411 1412 /* 1413 * Byte swapping is tricky. We need to provide the tag 1414 * in a network byte order. On a big-endian machine, 1415 * the byteorder is correct, but we need to swap it 1416 * anyway, because this will be undone by the outside 1417 * htole32(). That's why there must be an 1418 * unconditional swap instead of htons() inside. 1419 */ 1420 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1421 sc->sc_txdescs[lasttx].sipd_extsts |= 1422 htole32(EXTSTS_VPKT | 1423 (bswap16(VLAN_TAG_VALUE(mtag)) & 1424 EXTSTS_VTCI)); 1425 } 1426 1427 /* 1428 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1429 * checksumming, set up the descriptor to do this work 1430 * for us. 1431 * 1432 * This apparently has to be on the first descriptor of 1433 * the packet. 1434 * 1435 * Byte-swap constants so the compiler can optimize. 1436 */ 1437 extsts = 0; 1438 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1439 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1440 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1441 extsts |= htole32(EXTSTS_IPPKT); 1442 } 1443 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1444 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1445 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1446 extsts |= htole32(EXTSTS_TCPPKT); 1447 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1448 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1449 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1450 extsts |= htole32(EXTSTS_UDPPKT); 1451 } 1452 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1453 } 1454 1455 /* 1456 * sip_start: [ifnet interface function] 1457 * 1458 * Start packet transmission on the interface. 1459 */ 1460 static void 1461 sipcom_start(struct ifnet *ifp) 1462 { 1463 struct sip_softc *sc = ifp->if_softc; 1464 struct mbuf *m0; 1465 struct mbuf *m; 1466 struct sip_txsoft *txs; 1467 bus_dmamap_t dmamap; 1468 int error, nexttx, lasttx, seg; 1469 int ofree = sc->sc_txfree; 1470 #if 0 1471 int firsttx = sc->sc_txnext; 1472 #endif 1473 1474 /* 1475 * If we've been told to pause, don't transmit any more packets. 1476 */ 1477 if (!sc->sc_gigabit && sc->sc_paused) 1478 ifp->if_flags |= IFF_OACTIVE; 1479 1480 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1481 return; 1482 1483 /* 1484 * Loop through the send queue, setting up transmit descriptors 1485 * until we drain the queue, or use up all available transmit 1486 * descriptors. 1487 */ 1488 for (;;) { 1489 /* Get a work queue entry. */ 1490 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1491 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1492 break; 1493 } 1494 1495 /* 1496 * Grab a packet off the queue. 1497 */ 1498 IFQ_POLL(&ifp->if_snd, m0); 1499 if (m0 == NULL) 1500 break; 1501 m = NULL; 1502 1503 dmamap = txs->txs_dmamap; 1504 1505 /* 1506 * Load the DMA map. If this fails, the packet either 1507 * didn't fit in the alloted number of segments, or we 1508 * were short on resources. 1509 */ 1510 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1511 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1512 /* In the non-gigabit case, we'll copy and try again. */ 1513 if (error != 0 && !sc->sc_gigabit) { 1514 MGETHDR(m, M_DONTWAIT, MT_DATA); 1515 if (m == NULL) { 1516 printf("%s: unable to allocate Tx mbuf\n", 1517 sc->sc_dev.dv_xname); 1518 break; 1519 } 1520 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1521 if (m0->m_pkthdr.len > MHLEN) { 1522 MCLGET(m, M_DONTWAIT); 1523 if ((m->m_flags & M_EXT) == 0) { 1524 printf("%s: unable to allocate Tx " 1525 "cluster\n", sc->sc_dev.dv_xname); 1526 m_freem(m); 1527 break; 1528 } 1529 } 1530 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1531 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1532 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1533 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1534 if (error) { 1535 printf("%s: unable to load Tx buffer, " 1536 "error = %d\n", sc->sc_dev.dv_xname, error); 1537 break; 1538 } 1539 } else if (error == EFBIG) { 1540 /* 1541 * For the too-many-segments case, we simply 1542 * report an error and drop the packet, 1543 * since we can't sanely copy a jumbo packet 1544 * to a single buffer. 1545 */ 1546 printf("%s: Tx packet consumes too many " 1547 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1548 IFQ_DEQUEUE(&ifp->if_snd, m0); 1549 m_freem(m0); 1550 continue; 1551 } else if (error != 0) { 1552 /* 1553 * Short on resources, just stop for now. 1554 */ 1555 break; 1556 } 1557 1558 /* 1559 * Ensure we have enough descriptors free to describe 1560 * the packet. Note, we always reserve one descriptor 1561 * at the end of the ring as a termination point, to 1562 * prevent wrap-around. 1563 */ 1564 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1565 /* 1566 * Not enough free descriptors to transmit this 1567 * packet. We haven't committed anything yet, 1568 * so just unload the DMA map, put the packet 1569 * back on the queue, and punt. Notify the upper 1570 * layer that there are not more slots left. 1571 * 1572 * XXX We could allocate an mbuf and copy, but 1573 * XXX is it worth it? 1574 */ 1575 ifp->if_flags |= IFF_OACTIVE; 1576 bus_dmamap_unload(sc->sc_dmat, dmamap); 1577 if (m != NULL) 1578 m_freem(m); 1579 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1580 break; 1581 } 1582 1583 IFQ_DEQUEUE(&ifp->if_snd, m0); 1584 if (m != NULL) { 1585 m_freem(m0); 1586 m0 = m; 1587 } 1588 1589 /* 1590 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1591 */ 1592 1593 /* Sync the DMA map. */ 1594 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1595 BUS_DMASYNC_PREWRITE); 1596 1597 /* 1598 * Initialize the transmit descriptors. 1599 */ 1600 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1601 seg < dmamap->dm_nsegs; 1602 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1603 /* 1604 * If this is the first descriptor we're 1605 * enqueueing, don't set the OWN bit just 1606 * yet. That could cause a race condition. 1607 * We'll do it below. 1608 */ 1609 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1610 htole32(dmamap->dm_segs[seg].ds_addr); 1611 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1612 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1613 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1614 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1615 lasttx = nexttx; 1616 } 1617 1618 /* Clear the MORE bit on the last segment. */ 1619 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1620 htole32(~CMDSTS_MORE); 1621 1622 /* 1623 * If we're in the interrupt delay window, delay the 1624 * interrupt. 1625 */ 1626 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1627 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1628 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1629 htole32(CMDSTS_INTR); 1630 sc->sc_txwin = 0; 1631 } 1632 1633 if (sc->sc_gigabit) 1634 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1635 1636 /* Sync the descriptors we're using. */ 1637 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1638 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1639 1640 /* 1641 * The entire packet is set up. Give the first descrptor 1642 * to the chip now. 1643 */ 1644 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1645 htole32(CMDSTS_OWN); 1646 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1647 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1648 1649 /* 1650 * Store a pointer to the packet so we can free it later, 1651 * and remember what txdirty will be once the packet is 1652 * done. 1653 */ 1654 txs->txs_mbuf = m0; 1655 txs->txs_firstdesc = sc->sc_txnext; 1656 txs->txs_lastdesc = lasttx; 1657 1658 /* Advance the tx pointer. */ 1659 sc->sc_txfree -= dmamap->dm_nsegs; 1660 sc->sc_txnext = nexttx; 1661 1662 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1663 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1664 1665 #if NBPFILTER > 0 1666 /* 1667 * Pass the packet to any BPF listeners. 1668 */ 1669 if (ifp->if_bpf) 1670 bpf_mtap(ifp->if_bpf, m0); 1671 #endif /* NBPFILTER > 0 */ 1672 } 1673 1674 if (txs == NULL || sc->sc_txfree == 0) { 1675 /* No more slots left; notify upper layer. */ 1676 ifp->if_flags |= IFF_OACTIVE; 1677 } 1678 1679 if (sc->sc_txfree != ofree) { 1680 /* 1681 * Start the transmit process. Note, the manual says 1682 * that if there are no pending transmissions in the 1683 * chip's internal queue (indicated by TXE being clear), 1684 * then the driver software must set the TXDP to the 1685 * first descriptor to be transmitted. However, if we 1686 * do this, it causes serious performance degredation on 1687 * the DP83820 under load, not setting TXDP doesn't seem 1688 * to adversely affect the SiS 900 or DP83815. 1689 * 1690 * Well, I guess it wouldn't be the first time a manual 1691 * has lied -- and they could be speaking of the NULL- 1692 * terminated descriptor list case, rather than OWN- 1693 * terminated rings. 1694 */ 1695 #if 0 1696 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1697 CR_TXE) == 0) { 1698 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1699 SIP_CDTXADDR(sc, firsttx)); 1700 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1701 } 1702 #else 1703 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1704 #endif 1705 1706 /* Set a watchdog timer in case the chip flakes out. */ 1707 /* Gigabit autonegotiation takes 5 seconds. */ 1708 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1709 } 1710 } 1711 1712 /* 1713 * sip_watchdog: [ifnet interface function] 1714 * 1715 * Watchdog timer handler. 1716 */ 1717 static void 1718 sipcom_watchdog(struct ifnet *ifp) 1719 { 1720 struct sip_softc *sc = ifp->if_softc; 1721 1722 /* 1723 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1724 * If we get a timeout, try and sweep up transmit descriptors. 1725 * If we manage to sweep them all up, ignore the lack of 1726 * interrupt. 1727 */ 1728 sipcom_txintr(sc); 1729 1730 if (sc->sc_txfree != sc->sc_ntxdesc) { 1731 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1732 ifp->if_oerrors++; 1733 1734 /* Reset the interface. */ 1735 (void) sipcom_init(ifp); 1736 } else if (ifp->if_flags & IFF_DEBUG) 1737 printf("%s: recovered from device timeout\n", 1738 sc->sc_dev.dv_xname); 1739 1740 /* Try to get more packets going. */ 1741 sipcom_start(ifp); 1742 } 1743 1744 /* 1745 * sip_ioctl: [ifnet interface function] 1746 * 1747 * Handle control requests from the operator. 1748 */ 1749 static int 1750 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1751 { 1752 struct sip_softc *sc = ifp->if_softc; 1753 struct ifreq *ifr = (struct ifreq *)data; 1754 int s, error; 1755 1756 s = splnet(); 1757 1758 switch (cmd) { 1759 case SIOCSIFMEDIA: 1760 /* Flow control requires full-duplex mode. */ 1761 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1762 (ifr->ifr_media & IFM_FDX) == 0) 1763 ifr->ifr_media &= ~IFM_ETH_FMASK; 1764 1765 /* XXX */ 1766 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1767 ifr->ifr_media &= ~IFM_ETH_FMASK; 1768 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1769 if (sc->sc_gigabit && 1770 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1771 /* We can do both TXPAUSE and RXPAUSE. */ 1772 ifr->ifr_media |= 1773 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1774 } else if (ifr->ifr_media & IFM_FLOW) { 1775 /* 1776 * Both TXPAUSE and RXPAUSE must be set. 1777 * (SiS900 and DP83815 don't have PAUSE_ASYM 1778 * feature.) 1779 * 1780 * XXX Can SiS900 and DP83815 send PAUSE? 1781 */ 1782 ifr->ifr_media |= 1783 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1784 } 1785 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1786 } 1787 /* FALLTHROUGH */ 1788 case SIOCGIFMEDIA: 1789 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1790 break; 1791 case SIOCSIFFLAGS: 1792 /* If the interface is up and running, only modify the receive 1793 * filter when setting promiscuous or debug mode. Otherwise 1794 * fall through to ether_ioctl, which will reset the chip. 1795 */ 1796 1797 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1798 == (sc)->sc_ethercom.ec_capenable) \ 1799 && ((sc)->sc_prev.is_vlan == \ 1800 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1801 1802 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1803 1804 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1805 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1806 == (IFF_UP|IFF_RUNNING)) 1807 && ((ifp->if_flags & (~RESETIGN)) 1808 == (sc->sc_if_flags & (~RESETIGN))) 1809 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1810 /* Set up the receive filter. */ 1811 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1812 error = 0; 1813 break; 1814 #undef RESETIGN 1815 } 1816 /* FALLTHROUGH */ 1817 default: 1818 error = ether_ioctl(ifp, cmd, data); 1819 if (error == ENETRESET) { 1820 /* 1821 * Multicast list has changed; set the hardware filter 1822 * accordingly. 1823 */ 1824 if (ifp->if_flags & IFF_RUNNING) 1825 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1826 error = 0; 1827 } 1828 break; 1829 } 1830 1831 /* Try to get more packets going. */ 1832 sipcom_start(ifp); 1833 1834 sc->sc_if_flags = ifp->if_flags; 1835 splx(s); 1836 return (error); 1837 } 1838 1839 /* 1840 * sip_intr: 1841 * 1842 * Interrupt service routine. 1843 */ 1844 static int 1845 sipcom_intr(void *arg) 1846 { 1847 struct sip_softc *sc = arg; 1848 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1849 u_int32_t isr; 1850 int handled = 0; 1851 1852 /* Disable interrupts. */ 1853 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1854 1855 for (;;) { 1856 /* Reading clears interrupt. */ 1857 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1858 if ((isr & sc->sc_imr) == 0) 1859 break; 1860 1861 #if NRND > 0 1862 if (RND_ENABLED(&sc->rnd_source)) 1863 rnd_add_uint32(&sc->rnd_source, isr); 1864 #endif 1865 1866 handled = 1; 1867 1868 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1869 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1870 1871 /* Grab any new packets. */ 1872 (*sc->sc_rxintr)(sc); 1873 1874 if (isr & ISR_RXORN) { 1875 printf("%s: receive FIFO overrun\n", 1876 sc->sc_dev.dv_xname); 1877 1878 /* XXX adjust rx_drain_thresh? */ 1879 } 1880 1881 if (isr & ISR_RXIDLE) { 1882 printf("%s: receive ring overrun\n", 1883 sc->sc_dev.dv_xname); 1884 1885 /* Get the receive process going again. */ 1886 bus_space_write_4(sc->sc_st, sc->sc_sh, 1887 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1888 bus_space_write_4(sc->sc_st, sc->sc_sh, 1889 SIP_CR, CR_RXE); 1890 } 1891 } 1892 1893 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1894 #ifdef SIP_EVENT_COUNTERS 1895 if (isr & ISR_TXDESC) 1896 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1897 else if (isr & ISR_TXIDLE) 1898 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1899 #endif 1900 1901 /* Sweep up transmit descriptors. */ 1902 sipcom_txintr(sc); 1903 1904 if (isr & ISR_TXURN) { 1905 u_int32_t thresh; 1906 int txfifo_size = (sc->sc_gigabit) 1907 ? DP83820_SIP_TXFIFO_SIZE 1908 : OTHER_SIP_TXFIFO_SIZE; 1909 1910 printf("%s: transmit FIFO underrun", 1911 sc->sc_dev.dv_xname); 1912 thresh = sc->sc_tx_drain_thresh + 1; 1913 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1914 && (thresh * 32) <= (txfifo_size - 1915 (sc->sc_tx_fill_thresh * 32))) { 1916 printf("; increasing Tx drain " 1917 "threshold to %u bytes\n", 1918 thresh * 32); 1919 sc->sc_tx_drain_thresh = thresh; 1920 (void) sipcom_init(ifp); 1921 } else { 1922 (void) sipcom_init(ifp); 1923 printf("\n"); 1924 } 1925 } 1926 } 1927 1928 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1929 if (isr & ISR_PAUSE_ST) { 1930 sc->sc_paused = 1; 1931 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1932 ifp->if_flags |= IFF_OACTIVE; 1933 } 1934 if (isr & ISR_PAUSE_END) { 1935 sc->sc_paused = 0; 1936 ifp->if_flags &= ~IFF_OACTIVE; 1937 } 1938 } 1939 1940 if (isr & ISR_HIBERR) { 1941 int want_init = 0; 1942 1943 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1944 1945 #define PRINTERR(bit, str) \ 1946 do { \ 1947 if ((isr & (bit)) != 0) { \ 1948 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1949 printf("%s: %s\n", \ 1950 sc->sc_dev.dv_xname, str); \ 1951 want_init = 1; \ 1952 } \ 1953 } while (/*CONSTCOND*/0) 1954 1955 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1956 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1957 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1958 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1959 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1960 /* 1961 * Ignore: 1962 * Tx reset complete 1963 * Rx reset complete 1964 */ 1965 if (want_init) 1966 (void) sipcom_init(ifp); 1967 #undef PRINTERR 1968 } 1969 } 1970 1971 /* Re-enable interrupts. */ 1972 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1973 1974 /* Try to get more packets going. */ 1975 sipcom_start(ifp); 1976 1977 return (handled); 1978 } 1979 1980 /* 1981 * sip_txintr: 1982 * 1983 * Helper; handle transmit interrupts. 1984 */ 1985 static void 1986 sipcom_txintr(struct sip_softc *sc) 1987 { 1988 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1989 struct sip_txsoft *txs; 1990 u_int32_t cmdsts; 1991 1992 if (sc->sc_paused == 0) 1993 ifp->if_flags &= ~IFF_OACTIVE; 1994 1995 /* 1996 * Go through our Tx list and free mbufs for those 1997 * frames which have been transmitted. 1998 */ 1999 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2000 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2001 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2002 2003 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2004 if (cmdsts & CMDSTS_OWN) 2005 break; 2006 2007 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2008 2009 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2010 2011 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2012 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2013 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2014 m_freem(txs->txs_mbuf); 2015 txs->txs_mbuf = NULL; 2016 2017 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2018 2019 /* 2020 * Check for errors and collisions. 2021 */ 2022 if (cmdsts & 2023 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2024 ifp->if_oerrors++; 2025 if (cmdsts & CMDSTS_Tx_EC) 2026 ifp->if_collisions += 16; 2027 if (ifp->if_flags & IFF_DEBUG) { 2028 if (cmdsts & CMDSTS_Tx_ED) 2029 printf("%s: excessive deferral\n", 2030 sc->sc_dev.dv_xname); 2031 if (cmdsts & CMDSTS_Tx_EC) 2032 printf("%s: excessive collisions\n", 2033 sc->sc_dev.dv_xname); 2034 } 2035 } else { 2036 /* Packet was transmitted successfully. */ 2037 ifp->if_opackets++; 2038 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2039 } 2040 } 2041 2042 /* 2043 * If there are no more pending transmissions, cancel the watchdog 2044 * timer. 2045 */ 2046 if (txs == NULL) { 2047 ifp->if_timer = 0; 2048 sc->sc_txwin = 0; 2049 } 2050 } 2051 2052 /* 2053 * gsip_rxintr: 2054 * 2055 * Helper; handle receive interrupts on gigabit parts. 2056 */ 2057 static void 2058 gsip_rxintr(struct sip_softc *sc) 2059 { 2060 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2061 struct sip_rxsoft *rxs; 2062 struct mbuf *m; 2063 u_int32_t cmdsts, extsts; 2064 int i, len; 2065 2066 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2067 rxs = &sc->sc_rxsoft[i]; 2068 2069 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2070 2071 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2072 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2073 len = CMDSTS_SIZE(sc, cmdsts); 2074 2075 /* 2076 * NOTE: OWN is set if owned by _consumer_. We're the 2077 * consumer of the receive ring, so if the bit is clear, 2078 * we have processed all of the packets. 2079 */ 2080 if ((cmdsts & CMDSTS_OWN) == 0) { 2081 /* 2082 * We have processed all of the receive buffers. 2083 */ 2084 break; 2085 } 2086 2087 if (__predict_false(sc->sc_rxdiscard)) { 2088 SIP_INIT_RXDESC(sc, i); 2089 if ((cmdsts & CMDSTS_MORE) == 0) { 2090 /* Reset our state. */ 2091 sc->sc_rxdiscard = 0; 2092 } 2093 continue; 2094 } 2095 2096 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2097 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2098 2099 m = rxs->rxs_mbuf; 2100 2101 /* 2102 * Add a new receive buffer to the ring. 2103 */ 2104 if (sipcom_add_rxbuf(sc, i) != 0) { 2105 /* 2106 * Failed, throw away what we've done so 2107 * far, and discard the rest of the packet. 2108 */ 2109 ifp->if_ierrors++; 2110 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2111 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2112 SIP_INIT_RXDESC(sc, i); 2113 if (cmdsts & CMDSTS_MORE) 2114 sc->sc_rxdiscard = 1; 2115 if (sc->sc_rxhead != NULL) 2116 m_freem(sc->sc_rxhead); 2117 SIP_RXCHAIN_RESET(sc); 2118 continue; 2119 } 2120 2121 SIP_RXCHAIN_LINK(sc, m); 2122 2123 m->m_len = len; 2124 2125 /* 2126 * If this is not the end of the packet, keep 2127 * looking. 2128 */ 2129 if (cmdsts & CMDSTS_MORE) { 2130 sc->sc_rxlen += len; 2131 continue; 2132 } 2133 2134 /* 2135 * Okay, we have the entire packet now. The chip includes 2136 * the FCS, so we need to trim it. 2137 */ 2138 m->m_len -= ETHER_CRC_LEN; 2139 2140 *sc->sc_rxtailp = NULL; 2141 len = m->m_len + sc->sc_rxlen; 2142 m = sc->sc_rxhead; 2143 2144 SIP_RXCHAIN_RESET(sc); 2145 2146 /* 2147 * If an error occurred, update stats and drop the packet. 2148 */ 2149 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2150 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2151 ifp->if_ierrors++; 2152 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2153 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2154 /* Receive overrun handled elsewhere. */ 2155 printf("%s: receive descriptor error\n", 2156 sc->sc_dev.dv_xname); 2157 } 2158 #define PRINTERR(bit, str) \ 2159 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2160 (cmdsts & (bit)) != 0) \ 2161 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2162 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2163 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2164 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2165 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2166 #undef PRINTERR 2167 m_freem(m); 2168 continue; 2169 } 2170 2171 /* 2172 * If the packet is small enough to fit in a 2173 * single header mbuf, allocate one and copy 2174 * the data into it. This greatly reduces 2175 * memory consumption when we receive lots 2176 * of small packets. 2177 */ 2178 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2179 struct mbuf *nm; 2180 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2181 if (nm == NULL) { 2182 ifp->if_ierrors++; 2183 m_freem(m); 2184 continue; 2185 } 2186 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2187 nm->m_data += 2; 2188 nm->m_pkthdr.len = nm->m_len = len; 2189 m_copydata(m, 0, len, mtod(nm, void *)); 2190 m_freem(m); 2191 m = nm; 2192 } 2193 #ifndef __NO_STRICT_ALIGNMENT 2194 else { 2195 /* 2196 * The DP83820's receive buffers must be 4-byte 2197 * aligned. But this means that the data after 2198 * the Ethernet header is misaligned. To compensate, 2199 * we have artificially shortened the buffer size 2200 * in the descriptor, and we do an overlapping copy 2201 * of the data two bytes further in (in the first 2202 * buffer of the chain only). 2203 */ 2204 memmove(mtod(m, char *) + 2, mtod(m, void *), 2205 m->m_len); 2206 m->m_data += 2; 2207 } 2208 #endif /* ! __NO_STRICT_ALIGNMENT */ 2209 2210 /* 2211 * If VLANs are enabled, VLAN packets have been unwrapped 2212 * for us. Associate the tag with the packet. 2213 */ 2214 2215 /* 2216 * Again, byte swapping is tricky. Hardware provided 2217 * the tag in the network byte order, but extsts was 2218 * passed through le32toh() in the meantime. On a 2219 * big-endian machine, we need to swap it again. On a 2220 * little-endian machine, we need to convert from the 2221 * network to host byte order. This means that we must 2222 * swap it in any case, so unconditional swap instead 2223 * of htons() is used. 2224 */ 2225 if ((extsts & EXTSTS_VPKT) != 0) { 2226 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2227 continue); 2228 } 2229 2230 /* 2231 * Set the incoming checksum information for the 2232 * packet. 2233 */ 2234 if ((extsts & EXTSTS_IPPKT) != 0) { 2235 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2236 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2237 if (extsts & EXTSTS_Rx_IPERR) 2238 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2239 if (extsts & EXTSTS_TCPPKT) { 2240 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2241 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2242 if (extsts & EXTSTS_Rx_TCPERR) 2243 m->m_pkthdr.csum_flags |= 2244 M_CSUM_TCP_UDP_BAD; 2245 } else if (extsts & EXTSTS_UDPPKT) { 2246 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2247 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2248 if (extsts & EXTSTS_Rx_UDPERR) 2249 m->m_pkthdr.csum_flags |= 2250 M_CSUM_TCP_UDP_BAD; 2251 } 2252 } 2253 2254 ifp->if_ipackets++; 2255 m->m_pkthdr.rcvif = ifp; 2256 m->m_pkthdr.len = len; 2257 2258 #if NBPFILTER > 0 2259 /* 2260 * Pass this up to any BPF listeners, but only 2261 * pass if up the stack if it's for us. 2262 */ 2263 if (ifp->if_bpf) 2264 bpf_mtap(ifp->if_bpf, m); 2265 #endif /* NBPFILTER > 0 */ 2266 2267 /* Pass it on. */ 2268 (*ifp->if_input)(ifp, m); 2269 } 2270 2271 /* Update the receive pointer. */ 2272 sc->sc_rxptr = i; 2273 } 2274 2275 /* 2276 * sip_rxintr: 2277 * 2278 * Helper; handle receive interrupts on 10/100 parts. 2279 */ 2280 static void 2281 sip_rxintr(struct sip_softc *sc) 2282 { 2283 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2284 struct sip_rxsoft *rxs; 2285 struct mbuf *m; 2286 u_int32_t cmdsts; 2287 int i, len; 2288 2289 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2290 rxs = &sc->sc_rxsoft[i]; 2291 2292 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2293 2294 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2295 2296 /* 2297 * NOTE: OWN is set if owned by _consumer_. We're the 2298 * consumer of the receive ring, so if the bit is clear, 2299 * we have processed all of the packets. 2300 */ 2301 if ((cmdsts & CMDSTS_OWN) == 0) { 2302 /* 2303 * We have processed all of the receive buffers. 2304 */ 2305 break; 2306 } 2307 2308 /* 2309 * If any collisions were seen on the wire, count one. 2310 */ 2311 if (cmdsts & CMDSTS_Rx_COL) 2312 ifp->if_collisions++; 2313 2314 /* 2315 * If an error occurred, update stats, clear the status 2316 * word, and leave the packet buffer in place. It will 2317 * simply be reused the next time the ring comes around. 2318 */ 2319 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2320 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2321 ifp->if_ierrors++; 2322 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2323 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2324 /* Receive overrun handled elsewhere. */ 2325 printf("%s: receive descriptor error\n", 2326 sc->sc_dev.dv_xname); 2327 } 2328 #define PRINTERR(bit, str) \ 2329 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2330 (cmdsts & (bit)) != 0) \ 2331 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2332 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2333 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2334 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2335 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2336 #undef PRINTERR 2337 SIP_INIT_RXDESC(sc, i); 2338 continue; 2339 } 2340 2341 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2342 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2343 2344 /* 2345 * No errors; receive the packet. Note, the SiS 900 2346 * includes the CRC with every packet. 2347 */ 2348 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2349 2350 #ifdef __NO_STRICT_ALIGNMENT 2351 /* 2352 * If the packet is small enough to fit in a 2353 * single header mbuf, allocate one and copy 2354 * the data into it. This greatly reduces 2355 * memory consumption when we receive lots 2356 * of small packets. 2357 * 2358 * Otherwise, we add a new buffer to the receive 2359 * chain. If this fails, we drop the packet and 2360 * recycle the old buffer. 2361 */ 2362 if (sip_copy_small != 0 && len <= MHLEN) { 2363 MGETHDR(m, M_DONTWAIT, MT_DATA); 2364 if (m == NULL) 2365 goto dropit; 2366 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2367 memcpy(mtod(m, void *), 2368 mtod(rxs->rxs_mbuf, void *), len); 2369 SIP_INIT_RXDESC(sc, i); 2370 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2371 rxs->rxs_dmamap->dm_mapsize, 2372 BUS_DMASYNC_PREREAD); 2373 } else { 2374 m = rxs->rxs_mbuf; 2375 if (sipcom_add_rxbuf(sc, i) != 0) { 2376 dropit: 2377 ifp->if_ierrors++; 2378 SIP_INIT_RXDESC(sc, i); 2379 bus_dmamap_sync(sc->sc_dmat, 2380 rxs->rxs_dmamap, 0, 2381 rxs->rxs_dmamap->dm_mapsize, 2382 BUS_DMASYNC_PREREAD); 2383 continue; 2384 } 2385 } 2386 #else 2387 /* 2388 * The SiS 900's receive buffers must be 4-byte aligned. 2389 * But this means that the data after the Ethernet header 2390 * is misaligned. We must allocate a new buffer and 2391 * copy the data, shifted forward 2 bytes. 2392 */ 2393 MGETHDR(m, M_DONTWAIT, MT_DATA); 2394 if (m == NULL) { 2395 dropit: 2396 ifp->if_ierrors++; 2397 SIP_INIT_RXDESC(sc, i); 2398 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2399 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2400 continue; 2401 } 2402 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2403 if (len > (MHLEN - 2)) { 2404 MCLGET(m, M_DONTWAIT); 2405 if ((m->m_flags & M_EXT) == 0) { 2406 m_freem(m); 2407 goto dropit; 2408 } 2409 } 2410 m->m_data += 2; 2411 2412 /* 2413 * Note that we use clusters for incoming frames, so the 2414 * buffer is virtually contiguous. 2415 */ 2416 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2417 2418 /* Allow the receive descriptor to continue using its mbuf. */ 2419 SIP_INIT_RXDESC(sc, i); 2420 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2421 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2422 #endif /* __NO_STRICT_ALIGNMENT */ 2423 2424 ifp->if_ipackets++; 2425 m->m_pkthdr.rcvif = ifp; 2426 m->m_pkthdr.len = m->m_len = len; 2427 2428 #if NBPFILTER > 0 2429 /* 2430 * Pass this up to any BPF listeners, but only 2431 * pass if up the stack if it's for us. 2432 */ 2433 if (ifp->if_bpf) 2434 bpf_mtap(ifp->if_bpf, m); 2435 #endif /* NBPFILTER > 0 */ 2436 2437 /* Pass it on. */ 2438 (*ifp->if_input)(ifp, m); 2439 } 2440 2441 /* Update the receive pointer. */ 2442 sc->sc_rxptr = i; 2443 } 2444 2445 /* 2446 * sip_tick: 2447 * 2448 * One second timer, used to tick the MII. 2449 */ 2450 static void 2451 sipcom_tick(void *arg) 2452 { 2453 struct sip_softc *sc = arg; 2454 int s; 2455 2456 s = splnet(); 2457 #ifdef SIP_EVENT_COUNTERS 2458 if (sc->sc_gigabit) { 2459 /* Read PAUSE related counts from MIB registers. */ 2460 sc->sc_ev_rxpause.ev_count += 2461 bus_space_read_4(sc->sc_st, sc->sc_sh, 2462 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2463 sc->sc_ev_txpause.ev_count += 2464 bus_space_read_4(sc->sc_st, sc->sc_sh, 2465 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2466 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2467 } 2468 #endif /* SIP_EVENT_COUNTERS */ 2469 mii_tick(&sc->sc_mii); 2470 splx(s); 2471 2472 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2473 } 2474 2475 /* 2476 * sip_reset: 2477 * 2478 * Perform a soft reset on the SiS 900. 2479 */ 2480 static bool 2481 sipcom_reset(struct sip_softc *sc) 2482 { 2483 bus_space_tag_t st = sc->sc_st; 2484 bus_space_handle_t sh = sc->sc_sh; 2485 int i; 2486 2487 bus_space_write_4(st, sh, SIP_IER, 0); 2488 bus_space_write_4(st, sh, SIP_IMR, 0); 2489 bus_space_write_4(st, sh, SIP_RFCR, 0); 2490 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2491 2492 for (i = 0; i < SIP_TIMEOUT; i++) { 2493 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2494 break; 2495 delay(2); 2496 } 2497 2498 if (i == SIP_TIMEOUT) { 2499 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2500 return false; 2501 } 2502 2503 delay(1000); 2504 2505 if (sc->sc_gigabit) { 2506 /* 2507 * Set the general purpose I/O bits. Do it here in case we 2508 * need to have GPIO set up to talk to the media interface. 2509 */ 2510 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2511 delay(1000); 2512 } 2513 return true; 2514 } 2515 2516 static void 2517 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2518 { 2519 u_int32_t reg; 2520 bus_space_tag_t st = sc->sc_st; 2521 bus_space_handle_t sh = sc->sc_sh; 2522 /* 2523 * Initialize the VLAN/IP receive control register. 2524 * We enable checksum computation on all incoming 2525 * packets, and do not reject packets w/ bad checksums. 2526 */ 2527 reg = 0; 2528 if (capenable & 2529 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2530 reg |= VRCR_IPEN; 2531 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2532 reg |= VRCR_VTDEN|VRCR_VTREN; 2533 bus_space_write_4(st, sh, SIP_VRCR, reg); 2534 2535 /* 2536 * Initialize the VLAN/IP transmit control register. 2537 * We enable outgoing checksum computation on a 2538 * per-packet basis. 2539 */ 2540 reg = 0; 2541 if (capenable & 2542 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2543 reg |= VTCR_PPCHK; 2544 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2545 reg |= VTCR_VPPTI; 2546 bus_space_write_4(st, sh, SIP_VTCR, reg); 2547 2548 /* 2549 * If we're using VLANs, initialize the VLAN data register. 2550 * To understand why we bswap the VLAN Ethertype, see section 2551 * 4.2.36 of the DP83820 manual. 2552 */ 2553 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2554 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2555 } 2556 2557 /* 2558 * sip_init: [ ifnet interface function ] 2559 * 2560 * Initialize the interface. Must be called at splnet(). 2561 */ 2562 static int 2563 sipcom_init(struct ifnet *ifp) 2564 { 2565 struct sip_softc *sc = ifp->if_softc; 2566 bus_space_tag_t st = sc->sc_st; 2567 bus_space_handle_t sh = sc->sc_sh; 2568 struct sip_txsoft *txs; 2569 struct sip_rxsoft *rxs; 2570 struct sip_desc *sipd; 2571 int i, error = 0; 2572 2573 if (!device_has_power(&sc->sc_dev)) 2574 return EBUSY; 2575 2576 /* 2577 * Cancel any pending I/O. 2578 */ 2579 sipcom_stop(ifp, 0); 2580 2581 /* 2582 * Reset the chip to a known state. 2583 */ 2584 if (!sipcom_reset(sc)) 2585 return EBUSY; 2586 2587 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2588 /* 2589 * DP83815 manual, page 78: 2590 * 4.4 Recommended Registers Configuration 2591 * For optimum performance of the DP83815, version noted 2592 * as DP83815CVNG (SRR = 203h), the listed register 2593 * modifications must be followed in sequence... 2594 * 2595 * It's not clear if this should be 302h or 203h because that 2596 * chip name is listed as SRR 302h in the description of the 2597 * SRR register. However, my revision 302h DP83815 on the 2598 * Netgear FA311 purchased in 02/2001 needs these settings 2599 * to avoid tons of errors in AcceptPerfectMatch (non- 2600 * IFF_PROMISC) mode. I do not know if other revisions need 2601 * this set or not. [briggs -- 09 March 2001] 2602 * 2603 * Note that only the low-order 12 bits of 0xe4 are documented 2604 * and that this sets reserved bits in that register. 2605 */ 2606 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2607 2608 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2609 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2610 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2611 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2612 2613 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2614 } 2615 2616 /* 2617 * Initialize the transmit descriptor ring. 2618 */ 2619 for (i = 0; i < sc->sc_ntxdesc; i++) { 2620 sipd = &sc->sc_txdescs[i]; 2621 memset(sipd, 0, sizeof(struct sip_desc)); 2622 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2623 } 2624 SIP_CDTXSYNC(sc, 0, sc->sc_ntxdesc, 2625 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2626 sc->sc_txfree = sc->sc_ntxdesc; 2627 sc->sc_txnext = 0; 2628 sc->sc_txwin = 0; 2629 2630 /* 2631 * Initialize the transmit job descriptors. 2632 */ 2633 SIMPLEQ_INIT(&sc->sc_txfreeq); 2634 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2635 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2636 txs = &sc->sc_txsoft[i]; 2637 txs->txs_mbuf = NULL; 2638 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2639 } 2640 2641 /* 2642 * Initialize the receive descriptor and receive job 2643 * descriptor rings. 2644 */ 2645 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2646 rxs = &sc->sc_rxsoft[i]; 2647 if (rxs->rxs_mbuf == NULL) { 2648 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2649 printf("%s: unable to allocate or map rx " 2650 "buffer %d, error = %d\n", 2651 sc->sc_dev.dv_xname, i, error); 2652 /* 2653 * XXX Should attempt to run with fewer receive 2654 * XXX buffers instead of just failing. 2655 */ 2656 sipcom_rxdrain(sc); 2657 goto out; 2658 } 2659 } else 2660 SIP_INIT_RXDESC(sc, i); 2661 } 2662 sc->sc_rxptr = 0; 2663 sc->sc_rxdiscard = 0; 2664 SIP_RXCHAIN_RESET(sc); 2665 2666 /* 2667 * Set the configuration register; it's already initialized 2668 * in sip_attach(). 2669 */ 2670 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2671 2672 /* 2673 * Initialize the prototype TXCFG register. 2674 */ 2675 if (sc->sc_gigabit) { 2676 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2677 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2678 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2679 SIP_SIS900_REV(sc, SIS_REV_960) || 2680 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2681 (sc->sc_cfg & CFG_EDBMASTEN)) { 2682 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2683 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2684 } else { 2685 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2686 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2687 } 2688 2689 sc->sc_txcfg |= TXCFG_ATP | 2690 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2691 sc->sc_tx_drain_thresh; 2692 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2693 2694 /* 2695 * Initialize the receive drain threshold if we have never 2696 * done so. 2697 */ 2698 if (sc->sc_rx_drain_thresh == 0) { 2699 /* 2700 * XXX This value should be tuned. This is set to the 2701 * maximum of 248 bytes, and we may be able to improve 2702 * performance by decreasing it (although we should never 2703 * set this value lower than 2; 14 bytes are required to 2704 * filter the packet). 2705 */ 2706 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2707 } 2708 2709 /* 2710 * Initialize the prototype RXCFG register. 2711 */ 2712 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2713 /* 2714 * Accept long packets (including FCS) so we can handle 2715 * 802.1q-tagged frames and jumbo frames properly. 2716 */ 2717 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2718 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2719 sc->sc_rxcfg |= RXCFG_ALP; 2720 2721 /* 2722 * Checksum offloading is disabled if the user selects an MTU 2723 * larger than 8109. (FreeBSD says 8152, but there is emperical 2724 * evidence that >8109 does not work on some boards, such as the 2725 * Planex GN-1000TE). 2726 */ 2727 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2728 (ifp->if_capenable & 2729 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2730 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2731 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2732 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2733 "disabled.\n", sc->sc_dev.dv_xname); 2734 ifp->if_capenable &= 2735 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2736 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2737 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2738 ifp->if_csum_flags_tx = 0; 2739 ifp->if_csum_flags_rx = 0; 2740 } 2741 2742 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2743 2744 if (sc->sc_gigabit) 2745 sipcom_dp83820_init(sc, ifp->if_capenable); 2746 2747 /* 2748 * Give the transmit and receive rings to the chip. 2749 */ 2750 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2751 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2752 2753 /* 2754 * Initialize the interrupt mask. 2755 */ 2756 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2757 sc->sc_bits.b_isr_sserr | 2758 sc->sc_bits.b_isr_rmabt | 2759 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2760 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2761 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2762 2763 /* Set up the receive filter. */ 2764 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2765 2766 /* 2767 * Tune sc_rx_flow_thresh. 2768 * XXX "More than 8KB" is too short for jumbo frames. 2769 * XXX TODO: Threshold value should be user-settable. 2770 */ 2771 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2772 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2773 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2774 2775 /* 2776 * Set the current media. Do this after initializing the prototype 2777 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2778 * control. 2779 */ 2780 mii_mediachg(&sc->sc_mii); 2781 2782 /* 2783 * Set the interrupt hold-off timer to 100us. 2784 */ 2785 if (sc->sc_gigabit) 2786 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2787 2788 /* 2789 * Enable interrupts. 2790 */ 2791 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2792 2793 /* 2794 * Start the transmit and receive processes. 2795 */ 2796 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2797 2798 /* 2799 * Start the one second MII clock. 2800 */ 2801 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2802 2803 /* 2804 * ...all done! 2805 */ 2806 ifp->if_flags |= IFF_RUNNING; 2807 ifp->if_flags &= ~IFF_OACTIVE; 2808 sc->sc_if_flags = ifp->if_flags; 2809 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2810 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2811 sc->sc_prev.if_capenable = ifp->if_capenable; 2812 2813 out: 2814 if (error) 2815 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2816 return (error); 2817 } 2818 2819 /* 2820 * sip_drain: 2821 * 2822 * Drain the receive queue. 2823 */ 2824 static void 2825 sipcom_rxdrain(struct sip_softc *sc) 2826 { 2827 struct sip_rxsoft *rxs; 2828 int i; 2829 2830 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2831 rxs = &sc->sc_rxsoft[i]; 2832 if (rxs->rxs_mbuf != NULL) { 2833 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2834 m_freem(rxs->rxs_mbuf); 2835 rxs->rxs_mbuf = NULL; 2836 } 2837 } 2838 } 2839 2840 /* 2841 * sip_stop: [ ifnet interface function ] 2842 * 2843 * Stop transmission on the interface. 2844 */ 2845 static void 2846 sipcom_stop(struct ifnet *ifp, int disable) 2847 { 2848 struct sip_softc *sc = ifp->if_softc; 2849 bus_space_tag_t st = sc->sc_st; 2850 bus_space_handle_t sh = sc->sc_sh; 2851 struct sip_txsoft *txs; 2852 u_int32_t cmdsts = 0; /* DEBUG */ 2853 2854 /* 2855 * Stop the one second clock. 2856 */ 2857 callout_stop(&sc->sc_tick_ch); 2858 2859 /* Down the MII. */ 2860 mii_down(&sc->sc_mii); 2861 2862 /* 2863 * Disable interrupts. 2864 */ 2865 bus_space_write_4(st, sh, SIP_IER, 0); 2866 2867 /* 2868 * Stop receiver and transmitter. 2869 */ 2870 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2871 2872 /* 2873 * Release any queued transmit buffers. 2874 */ 2875 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2876 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2877 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2878 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2879 CMDSTS_INTR) == 0) 2880 printf("%s: sip_stop: last descriptor does not " 2881 "have INTR bit set\n", sc->sc_dev.dv_xname); 2882 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2883 #ifdef DIAGNOSTIC 2884 if (txs->txs_mbuf == NULL) { 2885 printf("%s: dirty txsoft with no mbuf chain\n", 2886 sc->sc_dev.dv_xname); 2887 panic("sip_stop"); 2888 } 2889 #endif 2890 cmdsts |= /* DEBUG */ 2891 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2892 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2893 m_freem(txs->txs_mbuf); 2894 txs->txs_mbuf = NULL; 2895 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2896 } 2897 2898 if (disable) 2899 sipcom_rxdrain(sc); 2900 2901 /* 2902 * Mark the interface down and cancel the watchdog timer. 2903 */ 2904 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2905 ifp->if_timer = 0; 2906 2907 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2908 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2909 printf("%s: sip_stop: no INTR bits set in dirty tx " 2910 "descriptors\n", sc->sc_dev.dv_xname); 2911 } 2912 2913 /* 2914 * sip_read_eeprom: 2915 * 2916 * Read data from the serial EEPROM. 2917 */ 2918 static void 2919 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2920 u_int16_t *data) 2921 { 2922 bus_space_tag_t st = sc->sc_st; 2923 bus_space_handle_t sh = sc->sc_sh; 2924 u_int16_t reg; 2925 int i, x; 2926 2927 for (i = 0; i < wordcnt; i++) { 2928 /* Send CHIP SELECT. */ 2929 reg = EROMAR_EECS; 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 2932 /* Shift in the READ opcode. */ 2933 for (x = 3; x > 0; x--) { 2934 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2935 reg |= EROMAR_EEDI; 2936 else 2937 reg &= ~EROMAR_EEDI; 2938 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2939 bus_space_write_4(st, sh, SIP_EROMAR, 2940 reg | EROMAR_EESK); 2941 delay(4); 2942 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2943 delay(4); 2944 } 2945 2946 /* Shift in address. */ 2947 for (x = 6; x > 0; x--) { 2948 if ((word + i) & (1 << (x - 1))) 2949 reg |= EROMAR_EEDI; 2950 else 2951 reg &= ~EROMAR_EEDI; 2952 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2953 bus_space_write_4(st, sh, SIP_EROMAR, 2954 reg | EROMAR_EESK); 2955 delay(4); 2956 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2957 delay(4); 2958 } 2959 2960 /* Shift out data. */ 2961 reg = EROMAR_EECS; 2962 data[i] = 0; 2963 for (x = 16; x > 0; x--) { 2964 bus_space_write_4(st, sh, SIP_EROMAR, 2965 reg | EROMAR_EESK); 2966 delay(4); 2967 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2968 data[i] |= (1 << (x - 1)); 2969 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2970 delay(4); 2971 } 2972 2973 /* Clear CHIP SELECT. */ 2974 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2975 delay(4); 2976 } 2977 } 2978 2979 /* 2980 * sipcom_add_rxbuf: 2981 * 2982 * Add a receive buffer to the indicated descriptor. 2983 */ 2984 static int 2985 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2986 { 2987 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2988 struct mbuf *m; 2989 int error; 2990 2991 MGETHDR(m, M_DONTWAIT, MT_DATA); 2992 if (m == NULL) 2993 return (ENOBUFS); 2994 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2995 2996 MCLGET(m, M_DONTWAIT); 2997 if ((m->m_flags & M_EXT) == 0) { 2998 m_freem(m); 2999 return (ENOBUFS); 3000 } 3001 3002 /* XXX I don't believe this is necessary. --dyoung */ 3003 if (sc->sc_gigabit) 3004 m->m_len = sc->sc_parm->p_rxbuf_len; 3005 3006 if (rxs->rxs_mbuf != NULL) 3007 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3008 3009 rxs->rxs_mbuf = m; 3010 3011 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3012 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3013 BUS_DMA_READ|BUS_DMA_NOWAIT); 3014 if (error) { 3015 printf("%s: can't load rx DMA map %d, error = %d\n", 3016 sc->sc_dev.dv_xname, idx, error); 3017 panic("%s", __func__); /* XXX */ 3018 } 3019 3020 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3021 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3022 3023 SIP_INIT_RXDESC(sc, idx); 3024 3025 return (0); 3026 } 3027 3028 /* 3029 * sip_sis900_set_filter: 3030 * 3031 * Set up the receive filter. 3032 */ 3033 static void 3034 sipcom_sis900_set_filter(struct sip_softc *sc) 3035 { 3036 bus_space_tag_t st = sc->sc_st; 3037 bus_space_handle_t sh = sc->sc_sh; 3038 struct ethercom *ec = &sc->sc_ethercom; 3039 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3040 struct ether_multi *enm; 3041 const u_int8_t *cp; 3042 struct ether_multistep step; 3043 u_int32_t crc, mchash[16]; 3044 3045 /* 3046 * Initialize the prototype RFCR. 3047 */ 3048 sc->sc_rfcr = RFCR_RFEN; 3049 if (ifp->if_flags & IFF_BROADCAST) 3050 sc->sc_rfcr |= RFCR_AAB; 3051 if (ifp->if_flags & IFF_PROMISC) { 3052 sc->sc_rfcr |= RFCR_AAP; 3053 goto allmulti; 3054 } 3055 3056 /* 3057 * Set up the multicast address filter by passing all multicast 3058 * addresses through a CRC generator, and then using the high-order 3059 * 6 bits as an index into the 128 bit multicast hash table (only 3060 * the lower 16 bits of each 32 bit multicast hash register are 3061 * valid). The high order bits select the register, while the 3062 * rest of the bits select the bit within the register. 3063 */ 3064 3065 memset(mchash, 0, sizeof(mchash)); 3066 3067 /* 3068 * SiS900 (at least SiS963) requires us to register the address of 3069 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3070 */ 3071 crc = 0x0ed423f9; 3072 3073 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3074 SIP_SIS900_REV(sc, SIS_REV_960) || 3075 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3076 /* Just want the 8 most significant bits. */ 3077 crc >>= 24; 3078 } else { 3079 /* Just want the 7 most significant bits. */ 3080 crc >>= 25; 3081 } 3082 3083 /* Set the corresponding bit in the hash table. */ 3084 mchash[crc >> 4] |= 1 << (crc & 0xf); 3085 3086 ETHER_FIRST_MULTI(step, ec, enm); 3087 while (enm != NULL) { 3088 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3089 /* 3090 * We must listen to a range of multicast addresses. 3091 * For now, just accept all multicasts, rather than 3092 * trying to set only those filter bits needed to match 3093 * the range. (At this time, the only use of address 3094 * ranges is for IP multicast routing, for which the 3095 * range is big enough to require all bits set.) 3096 */ 3097 goto allmulti; 3098 } 3099 3100 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3101 3102 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3103 SIP_SIS900_REV(sc, SIS_REV_960) || 3104 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3105 /* Just want the 8 most significant bits. */ 3106 crc >>= 24; 3107 } else { 3108 /* Just want the 7 most significant bits. */ 3109 crc >>= 25; 3110 } 3111 3112 /* Set the corresponding bit in the hash table. */ 3113 mchash[crc >> 4] |= 1 << (crc & 0xf); 3114 3115 ETHER_NEXT_MULTI(step, enm); 3116 } 3117 3118 ifp->if_flags &= ~IFF_ALLMULTI; 3119 goto setit; 3120 3121 allmulti: 3122 ifp->if_flags |= IFF_ALLMULTI; 3123 sc->sc_rfcr |= RFCR_AAM; 3124 3125 setit: 3126 #define FILTER_EMIT(addr, data) \ 3127 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3128 delay(1); \ 3129 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3130 delay(1) 3131 3132 /* 3133 * Disable receive filter, and program the node address. 3134 */ 3135 cp = CLLADDR(ifp->if_sadl); 3136 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3137 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3138 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3139 3140 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3141 /* 3142 * Program the multicast hash table. 3143 */ 3144 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3145 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3146 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3147 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3148 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3149 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3150 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3151 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3152 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3153 SIP_SIS900_REV(sc, SIS_REV_960) || 3154 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3155 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3156 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3157 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3158 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3159 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3160 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3161 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3162 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3163 } 3164 } 3165 #undef FILTER_EMIT 3166 3167 /* 3168 * Re-enable the receiver filter. 3169 */ 3170 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3171 } 3172 3173 /* 3174 * sip_dp83815_set_filter: 3175 * 3176 * Set up the receive filter. 3177 */ 3178 static void 3179 sipcom_dp83815_set_filter(struct sip_softc *sc) 3180 { 3181 bus_space_tag_t st = sc->sc_st; 3182 bus_space_handle_t sh = sc->sc_sh; 3183 struct ethercom *ec = &sc->sc_ethercom; 3184 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3185 struct ether_multi *enm; 3186 const u_int8_t *cp; 3187 struct ether_multistep step; 3188 u_int32_t crc, hash, slot, bit; 3189 #define MCHASH_NWORDS_83820 128 3190 #define MCHASH_NWORDS_83815 32 3191 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3192 u_int16_t mchash[MCHASH_NWORDS]; 3193 int i; 3194 3195 /* 3196 * Initialize the prototype RFCR. 3197 * Enable the receive filter, and accept on 3198 * Perfect (destination address) Match 3199 * If IFF_BROADCAST, also accept all broadcast packets. 3200 * If IFF_PROMISC, accept all unicast packets (and later, set 3201 * IFF_ALLMULTI and accept all multicast, too). 3202 */ 3203 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3204 if (ifp->if_flags & IFF_BROADCAST) 3205 sc->sc_rfcr |= RFCR_AAB; 3206 if (ifp->if_flags & IFF_PROMISC) { 3207 sc->sc_rfcr |= RFCR_AAP; 3208 goto allmulti; 3209 } 3210 3211 /* 3212 * Set up the DP83820/DP83815 multicast address filter by 3213 * passing all multicast addresses through a CRC generator, 3214 * and then using the high-order 11/9 bits as an index into 3215 * the 2048/512 bit multicast hash table. The high-order 3216 * 7/5 bits select the slot, while the low-order 4 bits 3217 * select the bit within the slot. Note that only the low 3218 * 16-bits of each filter word are used, and there are 3219 * 128/32 filter words. 3220 */ 3221 3222 memset(mchash, 0, sizeof(mchash)); 3223 3224 ifp->if_flags &= ~IFF_ALLMULTI; 3225 ETHER_FIRST_MULTI(step, ec, enm); 3226 if (enm == NULL) 3227 goto setit; 3228 while (enm != NULL) { 3229 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3230 /* 3231 * We must listen to a range of multicast addresses. 3232 * For now, just accept all multicasts, rather than 3233 * trying to set only those filter bits needed to match 3234 * the range. (At this time, the only use of address 3235 * ranges is for IP multicast routing, for which the 3236 * range is big enough to require all bits set.) 3237 */ 3238 goto allmulti; 3239 } 3240 3241 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3242 3243 if (sc->sc_gigabit) { 3244 /* Just want the 11 most significant bits. */ 3245 hash = crc >> 21; 3246 } else { 3247 /* Just want the 9 most significant bits. */ 3248 hash = crc >> 23; 3249 } 3250 3251 slot = hash >> 4; 3252 bit = hash & 0xf; 3253 3254 /* Set the corresponding bit in the hash table. */ 3255 mchash[slot] |= 1 << bit; 3256 3257 ETHER_NEXT_MULTI(step, enm); 3258 } 3259 sc->sc_rfcr |= RFCR_MHEN; 3260 goto setit; 3261 3262 allmulti: 3263 ifp->if_flags |= IFF_ALLMULTI; 3264 sc->sc_rfcr |= RFCR_AAM; 3265 3266 setit: 3267 #define FILTER_EMIT(addr, data) \ 3268 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3269 delay(1); \ 3270 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3271 delay(1) 3272 3273 /* 3274 * Disable receive filter, and program the node address. 3275 */ 3276 cp = CLLADDR(ifp->if_sadl); 3277 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3278 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3279 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3280 3281 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3282 int nwords = 3283 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3284 /* 3285 * Program the multicast hash table. 3286 */ 3287 for (i = 0; i < nwords; i++) { 3288 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3289 } 3290 } 3291 #undef FILTER_EMIT 3292 #undef MCHASH_NWORDS 3293 #undef MCHASH_NWORDS_83815 3294 #undef MCHASH_NWORDS_83820 3295 3296 /* 3297 * Re-enable the receiver filter. 3298 */ 3299 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3300 } 3301 3302 /* 3303 * sip_dp83820_mii_readreg: [mii interface function] 3304 * 3305 * Read a PHY register on the MII of the DP83820. 3306 */ 3307 static int 3308 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3309 { 3310 struct sip_softc *sc = (void *) self; 3311 3312 if (sc->sc_cfg & CFG_TBI_EN) { 3313 bus_addr_t tbireg; 3314 int rv; 3315 3316 if (phy != 0) 3317 return (0); 3318 3319 switch (reg) { 3320 case MII_BMCR: tbireg = SIP_TBICR; break; 3321 case MII_BMSR: tbireg = SIP_TBISR; break; 3322 case MII_ANAR: tbireg = SIP_TANAR; break; 3323 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3324 case MII_ANER: tbireg = SIP_TANER; break; 3325 case MII_EXTSR: 3326 /* 3327 * Don't even bother reading the TESR register. 3328 * The manual documents that the device has 3329 * 1000baseX full/half capability, but the 3330 * register itself seems read back 0 on some 3331 * boards. Just hard-code the result. 3332 */ 3333 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3334 3335 default: 3336 return (0); 3337 } 3338 3339 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3340 if (tbireg == SIP_TBISR) { 3341 /* LINK and ACOMP are switched! */ 3342 int val = rv; 3343 3344 rv = 0; 3345 if (val & TBISR_MR_LINK_STATUS) 3346 rv |= BMSR_LINK; 3347 if (val & TBISR_MR_AN_COMPLETE) 3348 rv |= BMSR_ACOMP; 3349 3350 /* 3351 * The manual claims this register reads back 0 3352 * on hard and soft reset. But we want to let 3353 * the gentbi driver know that we support auto- 3354 * negotiation, so hard-code this bit in the 3355 * result. 3356 */ 3357 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3358 } 3359 3360 return (rv); 3361 } 3362 3363 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3364 } 3365 3366 /* 3367 * sip_dp83820_mii_writereg: [mii interface function] 3368 * 3369 * Write a PHY register on the MII of the DP83820. 3370 */ 3371 static void 3372 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3373 { 3374 struct sip_softc *sc = (void *) self; 3375 3376 if (sc->sc_cfg & CFG_TBI_EN) { 3377 bus_addr_t tbireg; 3378 3379 if (phy != 0) 3380 return; 3381 3382 switch (reg) { 3383 case MII_BMCR: tbireg = SIP_TBICR; break; 3384 case MII_ANAR: tbireg = SIP_TANAR; break; 3385 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3386 default: 3387 return; 3388 } 3389 3390 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3391 return; 3392 } 3393 3394 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3395 } 3396 3397 /* 3398 * sip_dp83820_mii_statchg: [mii interface function] 3399 * 3400 * Callback from MII layer when media changes. 3401 */ 3402 static void 3403 sipcom_dp83820_mii_statchg(struct device *self) 3404 { 3405 struct sip_softc *sc = (struct sip_softc *) self; 3406 struct mii_data *mii = &sc->sc_mii; 3407 u_int32_t cfg, pcr; 3408 3409 /* 3410 * Get flow control negotiation result. 3411 */ 3412 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3413 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3414 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3415 mii->mii_media_active &= ~IFM_ETH_FMASK; 3416 } 3417 3418 /* 3419 * Update TXCFG for full-duplex operation. 3420 */ 3421 if ((mii->mii_media_active & IFM_FDX) != 0) 3422 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3423 else 3424 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3425 3426 /* 3427 * Update RXCFG for full-duplex or loopback. 3428 */ 3429 if ((mii->mii_media_active & IFM_FDX) != 0 || 3430 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3431 sc->sc_rxcfg |= RXCFG_ATX; 3432 else 3433 sc->sc_rxcfg &= ~RXCFG_ATX; 3434 3435 /* 3436 * Update CFG for MII/GMII. 3437 */ 3438 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3439 cfg = sc->sc_cfg | CFG_MODE_1000; 3440 else 3441 cfg = sc->sc_cfg; 3442 3443 /* 3444 * 802.3x flow control. 3445 */ 3446 pcr = 0; 3447 if (sc->sc_flowflags & IFM_FLOW) { 3448 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3449 pcr |= sc->sc_rx_flow_thresh; 3450 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3451 pcr |= PCR_PSEN | PCR_PS_MCAST; 3452 } 3453 3454 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3455 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3456 sc->sc_txcfg); 3457 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3458 sc->sc_rxcfg); 3459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3460 } 3461 3462 /* 3463 * sip_mii_bitbang_read: [mii bit-bang interface function] 3464 * 3465 * Read the MII serial port for the MII bit-bang module. 3466 */ 3467 static u_int32_t 3468 sipcom_mii_bitbang_read(struct device *self) 3469 { 3470 struct sip_softc *sc = (void *) self; 3471 3472 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3473 } 3474 3475 /* 3476 * sip_mii_bitbang_write: [mii big-bang interface function] 3477 * 3478 * Write the MII serial port for the MII bit-bang module. 3479 */ 3480 static void 3481 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3482 { 3483 struct sip_softc *sc = (void *) self; 3484 3485 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3486 } 3487 3488 /* 3489 * sip_sis900_mii_readreg: [mii interface function] 3490 * 3491 * Read a PHY register on the MII. 3492 */ 3493 static int 3494 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3495 { 3496 struct sip_softc *sc = (struct sip_softc *) self; 3497 u_int32_t enphy; 3498 3499 /* 3500 * The PHY of recent SiS chipsets is accessed through bitbang 3501 * operations. 3502 */ 3503 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3504 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3505 phy, reg); 3506 3507 #ifndef SIS900_MII_RESTRICT 3508 /* 3509 * The SiS 900 has only an internal PHY on the MII. Only allow 3510 * MII address 0. 3511 */ 3512 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3513 return (0); 3514 #endif 3515 3516 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3517 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3518 ENPHY_RWCMD | ENPHY_ACCESS); 3519 do { 3520 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3521 } while (enphy & ENPHY_ACCESS); 3522 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3523 } 3524 3525 /* 3526 * sip_sis900_mii_writereg: [mii interface function] 3527 * 3528 * Write a PHY register on the MII. 3529 */ 3530 static void 3531 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3532 { 3533 struct sip_softc *sc = (struct sip_softc *) self; 3534 u_int32_t enphy; 3535 3536 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3537 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3538 phy, reg, val); 3539 return; 3540 } 3541 3542 #ifndef SIS900_MII_RESTRICT 3543 /* 3544 * The SiS 900 has only an internal PHY on the MII. Only allow 3545 * MII address 0. 3546 */ 3547 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3548 return; 3549 #endif 3550 3551 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3552 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3553 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3554 do { 3555 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3556 } while (enphy & ENPHY_ACCESS); 3557 } 3558 3559 /* 3560 * sip_sis900_mii_statchg: [mii interface function] 3561 * 3562 * Callback from MII layer when media changes. 3563 */ 3564 static void 3565 sipcom_sis900_mii_statchg(struct device *self) 3566 { 3567 struct sip_softc *sc = (struct sip_softc *) self; 3568 struct mii_data *mii = &sc->sc_mii; 3569 u_int32_t flowctl; 3570 3571 /* 3572 * Get flow control negotiation result. 3573 */ 3574 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3575 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3576 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3577 mii->mii_media_active &= ~IFM_ETH_FMASK; 3578 } 3579 3580 /* 3581 * Update TXCFG for full-duplex operation. 3582 */ 3583 if ((mii->mii_media_active & IFM_FDX) != 0) 3584 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3585 else 3586 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3587 3588 /* 3589 * Update RXCFG for full-duplex or loopback. 3590 */ 3591 if ((mii->mii_media_active & IFM_FDX) != 0 || 3592 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3593 sc->sc_rxcfg |= RXCFG_ATX; 3594 else 3595 sc->sc_rxcfg &= ~RXCFG_ATX; 3596 3597 /* 3598 * Update IMR for use of 802.3x flow control. 3599 */ 3600 if (sc->sc_flowflags & IFM_FLOW) { 3601 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3602 flowctl = FLOWCTL_FLOWEN; 3603 } else { 3604 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3605 flowctl = 0; 3606 } 3607 3608 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3609 sc->sc_txcfg); 3610 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3611 sc->sc_rxcfg); 3612 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3613 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3614 } 3615 3616 /* 3617 * sip_dp83815_mii_readreg: [mii interface function] 3618 * 3619 * Read a PHY register on the MII. 3620 */ 3621 static int 3622 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3623 { 3624 struct sip_softc *sc = (struct sip_softc *) self; 3625 u_int32_t val; 3626 3627 /* 3628 * The DP83815 only has an internal PHY. Only allow 3629 * MII address 0. 3630 */ 3631 if (phy != 0) 3632 return (0); 3633 3634 /* 3635 * Apparently, after a reset, the DP83815 can take a while 3636 * to respond. During this recovery period, the BMSR returns 3637 * a value of 0. Catch this -- it's not supposed to happen 3638 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3639 * PHY to come back to life. 3640 * 3641 * This works out because the BMSR is the first register 3642 * read during the PHY probe process. 3643 */ 3644 do { 3645 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3646 } while (reg == MII_BMSR && val == 0); 3647 3648 return (val & 0xffff); 3649 } 3650 3651 /* 3652 * sip_dp83815_mii_writereg: [mii interface function] 3653 * 3654 * Write a PHY register to the MII. 3655 */ 3656 static void 3657 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3658 { 3659 struct sip_softc *sc = (struct sip_softc *) self; 3660 3661 /* 3662 * The DP83815 only has an internal PHY. Only allow 3663 * MII address 0. 3664 */ 3665 if (phy != 0) 3666 return; 3667 3668 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3669 } 3670 3671 /* 3672 * sip_dp83815_mii_statchg: [mii interface function] 3673 * 3674 * Callback from MII layer when media changes. 3675 */ 3676 static void 3677 sipcom_dp83815_mii_statchg(struct device *self) 3678 { 3679 struct sip_softc *sc = (struct sip_softc *) self; 3680 3681 /* 3682 * Update TXCFG for full-duplex operation. 3683 */ 3684 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3685 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3686 else 3687 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3688 3689 /* 3690 * Update RXCFG for full-duplex or loopback. 3691 */ 3692 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3693 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3694 sc->sc_rxcfg |= RXCFG_ATX; 3695 else 3696 sc->sc_rxcfg &= ~RXCFG_ATX; 3697 3698 /* 3699 * XXX 802.3x flow control. 3700 */ 3701 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3703 sc->sc_txcfg); 3704 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3705 sc->sc_rxcfg); 3706 3707 /* 3708 * Some DP83815s experience problems when used with short 3709 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3710 * sequence adjusts the DSP's signal attenuation to fix the 3711 * problem. 3712 */ 3713 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3714 uint32_t reg; 3715 3716 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3717 3718 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3719 reg &= 0x0fff; 3720 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3721 delay(100); 3722 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3723 reg &= 0x00ff; 3724 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3725 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3726 0x00e8); 3727 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3728 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3729 reg | 0x20); 3730 } 3731 3732 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3733 } 3734 } 3735 3736 static void 3737 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3738 const struct pci_attach_args *pa, u_int8_t *enaddr) 3739 { 3740 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3741 u_int8_t cksum, *e, match; 3742 int i; 3743 3744 /* 3745 * EEPROM data format for the DP83820 can be found in 3746 * the DP83820 manual, section 4.2.4. 3747 */ 3748 3749 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3750 3751 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3752 match = ~(match - 1); 3753 3754 cksum = 0x55; 3755 e = (u_int8_t *) eeprom_data; 3756 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3757 cksum += *e++; 3758 3759 if (cksum != match) 3760 printf("%s: Checksum (%x) mismatch (%x)", 3761 sc->sc_dev.dv_xname, cksum, match); 3762 3763 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3764 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3765 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3766 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3767 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3768 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3769 } 3770 3771 static void 3772 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3773 { 3774 int i; 3775 3776 /* 3777 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3778 * a reason, but I don't know it. 3779 */ 3780 for (i = 0; i < 10; i++) 3781 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3782 } 3783 3784 static void 3785 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3786 const struct pci_attach_args *pa, u_int8_t *enaddr) 3787 { 3788 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3789 3790 switch (sc->sc_rev) { 3791 case SIS_REV_630S: 3792 case SIS_REV_630E: 3793 case SIS_REV_630EA1: 3794 case SIS_REV_630ET: 3795 case SIS_REV_635: 3796 /* 3797 * The MAC address for the on-board Ethernet of 3798 * the SiS 630 chipset is in the NVRAM. Kick 3799 * the chip into re-loading it from NVRAM, and 3800 * read the MAC address out of the filter registers. 3801 */ 3802 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3803 3804 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3805 RFCR_RFADDR_NODE0); 3806 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3807 0xffff; 3808 3809 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3810 RFCR_RFADDR_NODE2); 3811 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3812 0xffff; 3813 3814 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3815 RFCR_RFADDR_NODE4); 3816 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3817 0xffff; 3818 break; 3819 3820 case SIS_REV_960: 3821 { 3822 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3823 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3824 3825 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3826 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3827 3828 int waittime, i; 3829 3830 /* Allow to read EEPROM from LAN. It is shared 3831 * between a 1394 controller and the NIC and each 3832 * time we access it, we need to set SIS_EECMD_REQ. 3833 */ 3834 SIS_SET_EROMAR(sc, EROMAR_REQ); 3835 3836 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3837 /* Force EEPROM to idle state. */ 3838 3839 /* 3840 * XXX-cube This is ugly. I'll look for docs about it. 3841 */ 3842 SIS_SET_EROMAR(sc, EROMAR_EECS); 3843 sipcom_sis900_eeprom_delay(sc); 3844 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3845 SIS_SET_EROMAR(sc, EROMAR_EESK); 3846 sipcom_sis900_eeprom_delay(sc); 3847 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3848 sipcom_sis900_eeprom_delay(sc); 3849 } 3850 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3851 sipcom_sis900_eeprom_delay(sc); 3852 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3853 3854 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3855 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3856 sizeof(myea) / sizeof(myea[0]), myea); 3857 break; 3858 } 3859 DELAY(1); 3860 } 3861 3862 /* 3863 * Set SIS_EECTL_CLK to high, so a other master 3864 * can operate on the i2c bus. 3865 */ 3866 SIS_SET_EROMAR(sc, EROMAR_EESK); 3867 3868 /* Refuse EEPROM access by LAN */ 3869 SIS_SET_EROMAR(sc, EROMAR_DONE); 3870 } break; 3871 3872 default: 3873 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3874 sizeof(myea) / sizeof(myea[0]), myea); 3875 } 3876 3877 enaddr[0] = myea[0] & 0xff; 3878 enaddr[1] = myea[0] >> 8; 3879 enaddr[2] = myea[1] & 0xff; 3880 enaddr[3] = myea[1] >> 8; 3881 enaddr[4] = myea[2] & 0xff; 3882 enaddr[5] = myea[2] >> 8; 3883 } 3884 3885 /* Table and macro to bit-reverse an octet. */ 3886 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3887 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3888 3889 static void 3890 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3891 const struct pci_attach_args *pa, u_int8_t *enaddr) 3892 { 3893 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3894 u_int8_t cksum, *e, match; 3895 int i; 3896 3897 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3898 sizeof(eeprom_data[0]), eeprom_data); 3899 3900 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3901 match = ~(match - 1); 3902 3903 cksum = 0x55; 3904 e = (u_int8_t *) eeprom_data; 3905 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3906 cksum += *e++; 3907 } 3908 if (cksum != match) { 3909 printf("%s: Checksum (%x) mismatch (%x)", 3910 sc->sc_dev.dv_xname, cksum, match); 3911 } 3912 3913 /* 3914 * Unrolled because it makes slightly more sense this way. 3915 * The DP83815 stores the MAC address in bit 0 of word 6 3916 * through bit 15 of word 8. 3917 */ 3918 ea = &eeprom_data[6]; 3919 enaddr[0] = ((*ea & 0x1) << 7); 3920 ea++; 3921 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3922 enaddr[1] = ((*ea & 0x1FE) >> 1); 3923 enaddr[2] = ((*ea & 0x1) << 7); 3924 ea++; 3925 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3926 enaddr[3] = ((*ea & 0x1FE) >> 1); 3927 enaddr[4] = ((*ea & 0x1) << 7); 3928 ea++; 3929 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3930 enaddr[5] = ((*ea & 0x1FE) >> 1); 3931 3932 /* 3933 * In case that's not weird enough, we also need to reverse 3934 * the bits in each byte. This all actually makes more sense 3935 * if you think about the EEPROM storage as an array of bits 3936 * being shifted into bytes, but that's not how we're looking 3937 * at it here... 3938 */ 3939 for (i = 0; i < 6 ;i++) 3940 enaddr[i] = bbr(enaddr[i]); 3941 } 3942 3943 /* 3944 * sip_mediastatus: [ifmedia interface function] 3945 * 3946 * Get the current interface media status. 3947 */ 3948 static void 3949 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3950 { 3951 struct sip_softc *sc = ifp->if_softc; 3952 3953 mii_pollstat(&sc->sc_mii); 3954 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3955 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3956 sc->sc_flowflags; 3957 } 3958 3959 /* 3960 * sip_mediachange: [ifmedia interface function] 3961 * 3962 * Set hardware to newly-selected media. 3963 */ 3964 static int 3965 sipcom_mediachange(struct ifnet *ifp) 3966 { 3967 struct sip_softc *sc = ifp->if_softc; 3968 3969 if (ifp->if_flags & IFF_UP) 3970 mii_mediachg(&sc->sc_mii); 3971 return (0); 3972 } 3973
Indexes created Tue Sep 30 11:09:46 GMT 2025