if_sip.c revision 1.123
1 /* $NetBSD: if_sip.c,v 1.123 2007/12/15 23:04:57 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.123 2007/12/15 23:04:57 dyoung Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 /* 130 * Transmit descriptor list size. This is arbitrary, but allocate 131 * enough descriptors for 128 pending transmissions, and 8 segments 132 * per packet (64 for DP83820 for jumbo frames). 133 * 134 * This MUST work out to a power of 2. 135 */ 136 #define GSIP_NTXSEGS_ALLOC 16 137 #define SIP_NTXSEGS_ALLOC 8 138 139 #define SIP_TXQUEUELEN 256 140 #define MAX_SIP_NTXDESC \ 141 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer per incoming 145 * packet, so this logic is a little simpler. 146 * 147 * Actually, on the DP83820, we allow the packet to consume more than 148 * one buffer, in order to support jumbo Ethernet frames. In that 149 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 150 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 151 * so we'd better be quick about handling receive interrupts. 152 */ 153 #define GSIP_NRXDESC 256 154 #define SIP_NRXDESC 128 155 156 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 157 158 /* 159 * Control structures are DMA'd to the SiS900 chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct sip_control_data { 164 /* 165 * The transmit descriptors. 166 */ 167 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 168 169 /* 170 * The receive descriptors. 171 */ 172 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 173 }; 174 175 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 176 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 177 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 178 179 /* 180 * Software state for transmit jobs. 181 */ 182 struct sip_txsoft { 183 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t txs_dmamap; /* our DMA map */ 185 int txs_firstdesc; /* first descriptor in packet */ 186 int txs_lastdesc; /* last descriptor in packet */ 187 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 188 }; 189 190 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 191 192 /* 193 * Software state for receive jobs. 194 */ 195 struct sip_rxsoft { 196 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t rxs_dmamap; /* our DMA map */ 198 }; 199 200 enum sip_attach_stage { 201 SIP_ATTACH_FIN = 0 202 , SIP_ATTACH_CREATE_RXMAP 203 , SIP_ATTACH_CREATE_TXMAP 204 , SIP_ATTACH_LOAD_MAP 205 , SIP_ATTACH_CREATE_MAP 206 , SIP_ATTACH_MAP_MEM 207 , SIP_ATTACH_ALLOC_MEM 208 , SIP_ATTACH_INTR 209 , SIP_ATTACH_MAP 210 }; 211 212 /* 213 * Software state per device. 214 */ 215 struct sip_softc { 216 struct device sc_dev; /* generic device information */ 217 bus_space_tag_t sc_st; /* bus space tag */ 218 bus_space_handle_t sc_sh; /* bus space handle */ 219 bus_size_t sc_sz; /* bus space size */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t sc_pc; 222 bus_dma_segment_t sc_seg; 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 void *sc_sdhook; /* shutdown hook */ 225 226 const struct sip_product *sc_model; /* which model are we? */ 227 int sc_gigabit; /* 1: 83820, 0: other */ 228 int sc_rev; /* chip revision */ 229 230 void *sc_ih; /* interrupt cookie */ 231 232 struct mii_data sc_mii; /* MII/media information */ 233 234 callout_t sc_tick_ch; /* tick callout */ 235 236 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 237 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 238 239 /* 240 * Software state for transmit and receive descriptors. 241 */ 242 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 243 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 244 245 /* 246 * Control data structures. 247 */ 248 struct sip_control_data *sc_control_data; 249 #define sc_txdescs sc_control_data->scd_txdescs 250 #define sc_rxdescs sc_control_data->scd_rxdescs 251 252 #ifdef SIP_EVENT_COUNTERS 253 /* 254 * Event counters. 255 */ 256 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 257 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 258 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 259 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 260 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 261 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 262 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 263 struct evcnt sc_ev_rxpause; /* PAUSE received */ 264 /* DP83820 only */ 265 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 266 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 267 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 268 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 269 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 270 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 271 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 272 #endif /* SIP_EVENT_COUNTERS */ 273 274 u_int32_t sc_txcfg; /* prototype TXCFG register */ 275 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 276 u_int32_t sc_imr; /* prototype IMR register */ 277 u_int32_t sc_rfcr; /* prototype RFCR register */ 278 279 u_int32_t sc_cfg; /* prototype CFG register */ 280 281 u_int32_t sc_gpior; /* prototype GPIOR register */ 282 283 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 284 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 285 286 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 287 288 int sc_flowflags; /* 802.3x flow control flags */ 289 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 290 int sc_paused; /* paused indication */ 291 292 int sc_txfree; /* number of free Tx descriptors */ 293 int sc_txnext; /* next ready Tx descriptor */ 294 int sc_txwin; /* Tx descriptors since last intr */ 295 296 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 297 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 298 299 /* values of interface state at last init */ 300 struct { 301 /* if_capenable */ 302 uint64_t if_capenable; 303 /* ec_capenable */ 304 int ec_capenable; 305 /* VLAN_ATTACHED */ 306 int is_vlan; 307 } sc_prev; 308 309 short sc_if_flags; 310 311 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 312 int sc_rxdiscard; 313 int sc_rxlen; 314 struct mbuf *sc_rxhead; 315 struct mbuf *sc_rxtail; 316 struct mbuf **sc_rxtailp; 317 318 int sc_ntxdesc; 319 int sc_ntxdesc_mask; 320 321 int sc_nrxdesc_mask; 322 323 const struct sip_parm { 324 const struct sip_regs { 325 int r_rxcfg; 326 int r_txcfg; 327 } p_regs; 328 329 const struct sip_bits { 330 uint32_t b_txcfg_mxdma_8; 331 uint32_t b_txcfg_mxdma_16; 332 uint32_t b_txcfg_mxdma_32; 333 uint32_t b_txcfg_mxdma_64; 334 uint32_t b_txcfg_mxdma_128; 335 uint32_t b_txcfg_mxdma_256; 336 uint32_t b_txcfg_mxdma_512; 337 uint32_t b_txcfg_flth_mask; 338 uint32_t b_txcfg_drth_mask; 339 340 uint32_t b_rxcfg_mxdma_8; 341 uint32_t b_rxcfg_mxdma_16; 342 uint32_t b_rxcfg_mxdma_32; 343 uint32_t b_rxcfg_mxdma_64; 344 uint32_t b_rxcfg_mxdma_128; 345 uint32_t b_rxcfg_mxdma_256; 346 uint32_t b_rxcfg_mxdma_512; 347 348 uint32_t b_isr_txrcmp; 349 uint32_t b_isr_rxrcmp; 350 uint32_t b_isr_dperr; 351 uint32_t b_isr_sserr; 352 uint32_t b_isr_rmabt; 353 uint32_t b_isr_rtabt; 354 355 uint32_t b_cmdsts_size_mask; 356 } p_bits; 357 int p_filtmem; 358 int p_rxbuf_len; 359 bus_size_t p_tx_dmamap_size; 360 int p_ntxsegs; 361 int p_ntxsegs_alloc; 362 int p_nrxdesc; 363 } *sc_parm; 364 365 void (*sc_rxintr)(struct sip_softc *); 366 367 #if NRND > 0 368 rndsource_element_t rnd_source; /* random source */ 369 #endif 370 }; 371 372 #define sc_bits sc_parm->p_bits 373 #define sc_regs sc_parm->p_regs 374 375 static const struct sip_parm sip_parm = { 376 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 377 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 378 , .p_tx_dmamap_size = MCLBYTES 379 , .p_ntxsegs = 16 380 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 381 , .p_nrxdesc = SIP_NRXDESC 382 , .p_bits = { 383 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 384 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 385 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 386 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 387 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 388 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 389 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 390 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 391 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 392 393 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 394 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 395 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 396 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 397 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 398 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 399 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 400 401 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 402 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 403 , .b_isr_dperr = 0x00800000 /* detected parity error */ 404 , .b_isr_sserr = 0x00400000 /* signalled system error */ 405 , .b_isr_rmabt = 0x00200000 /* received master abort */ 406 , .b_isr_rtabt = 0x00100000 /* received target abort */ 407 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 408 } 409 , .p_regs = { 410 .r_rxcfg = OTHER_SIP_RXCFG, 411 .r_txcfg = OTHER_SIP_TXCFG 412 } 413 }, gsip_parm = { 414 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 415 , .p_rxbuf_len = MCLBYTES - 8 416 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 417 , .p_ntxsegs = 64 418 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 419 , .p_nrxdesc = GSIP_NRXDESC 420 , .p_bits = { 421 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 422 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 423 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 424 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 425 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 426 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 427 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 428 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 429 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 430 431 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 432 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 433 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 434 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 435 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 436 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 437 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 438 439 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 440 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 441 , .b_isr_dperr = 0x00100000 /* detected parity error */ 442 , .b_isr_sserr = 0x00080000 /* signalled system error */ 443 , .b_isr_rmabt = 0x00040000 /* received master abort */ 444 , .b_isr_rtabt = 0x00020000 /* received target abort */ 445 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 446 } 447 , .p_regs = { 448 .r_rxcfg = DP83820_SIP_RXCFG, 449 .r_txcfg = DP83820_SIP_TXCFG 450 } 451 }; 452 453 static inline int 454 sip_nexttx(const struct sip_softc *sc, int x) 455 { 456 return (x + 1) & sc->sc_ntxdesc_mask; 457 } 458 459 static inline int 460 sip_nextrx(const struct sip_softc *sc, int x) 461 { 462 return (x + 1) & sc->sc_nrxdesc_mask; 463 } 464 465 /* 83820 only */ 466 #define SIP_RXCHAIN_RESET(sc) \ 467 do { \ 468 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 469 *(sc)->sc_rxtailp = NULL; \ 470 (sc)->sc_rxlen = 0; \ 471 } while (/*CONSTCOND*/0) 472 473 /* 83820 only */ 474 #define SIP_RXCHAIN_LINK(sc, m) \ 475 do { \ 476 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 477 (sc)->sc_rxtailp = &(m)->m_next; \ 478 } while (/*CONSTCOND*/0) 479 480 #ifdef SIP_EVENT_COUNTERS 481 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 482 #else 483 #define SIP_EVCNT_INCR(ev) /* nothing */ 484 #endif 485 486 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 487 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 488 489 #define SIP_CDTXSYNC(sc, x, n, ops) \ 490 do { \ 491 int __x, __n; \ 492 \ 493 __x = (x); \ 494 __n = (n); \ 495 \ 496 /* If it will wrap around, sync to the end of the ring. */ \ 497 if ((__x + __n) > sc->sc_ntxdesc) { \ 498 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 499 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * \ 500 (sc->sc_ntxdesc - __x), (ops)); \ 501 __n -= (sc->sc_ntxdesc - __x); \ 502 __x = 0; \ 503 } \ 504 \ 505 /* Now sync whatever is left. */ \ 506 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 507 SIP_CDTXOFF(__x), sizeof(struct sip_desc) * __n, (ops)); \ 508 } while (0) 509 510 #define SIP_CDRXSYNC(sc, x, ops) \ 511 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 512 SIP_CDRXOFF((x)), sizeof(struct sip_desc), (ops)) 513 514 #if 0 515 #ifdef DP83820 516 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 #else 519 u_int32_t sipd_cmdsts; /* command/status word */ 520 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 521 #endif /* DP83820 */ 522 #endif /* 0 */ 523 524 static inline volatile uint32_t * 525 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 526 { 527 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 528 } 529 530 static inline volatile uint32_t * 531 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 532 { 533 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 534 } 535 536 static inline void 537 SIP_INIT_RXDESC(struct sip_softc *sc, int x) 538 { 539 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 540 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 541 542 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 543 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 544 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 545 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 546 sipd->sipd_extsts = 0; 547 SIP_CDRXSYNC(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 548 } 549 550 #define SIP_CHIP_VERS(sc, v, p, r) \ 551 ((sc)->sc_model->sip_vendor == (v) && \ 552 (sc)->sc_model->sip_product == (p) && \ 553 (sc)->sc_rev == (r)) 554 555 #define SIP_CHIP_MODEL(sc, v, p) \ 556 ((sc)->sc_model->sip_vendor == (v) && \ 557 (sc)->sc_model->sip_product == (p)) 558 559 #define SIP_SIS900_REV(sc, rev) \ 560 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 561 562 #define SIP_TIMEOUT 1000 563 564 static void sipcom_start(struct ifnet *); 565 static void sipcom_watchdog(struct ifnet *); 566 static int sipcom_ioctl(struct ifnet *, u_long, void *); 567 static int sipcom_init(struct ifnet *); 568 static void sipcom_stop(struct ifnet *, int); 569 570 static void sipcom_shutdown(void *); 571 572 static bool sipcom_reset(struct sip_softc *); 573 static void sipcom_rxdrain(struct sip_softc *); 574 static int sipcom_add_rxbuf(struct sip_softc *, int); 575 static void sipcom_read_eeprom(struct sip_softc *, int, int, 576 u_int16_t *); 577 static void sipcom_tick(void *); 578 579 static void sipcom_sis900_set_filter(struct sip_softc *); 580 static void sipcom_dp83815_set_filter(struct sip_softc *); 581 582 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 585 static void sipcom_sis900_read_macaddr(struct sip_softc *, 586 const struct pci_attach_args *, u_int8_t *); 587 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 588 const struct pci_attach_args *, u_int8_t *); 589 590 static int sipcom_intr(void *); 591 static void sipcom_txintr(struct sip_softc *); 592 static void sip_rxintr(struct sip_softc *); 593 static void gsip_rxintr(struct sip_softc *); 594 595 static int sipcom_dp83820_mii_readreg(struct device *, int, int); 596 static void sipcom_dp83820_mii_writereg(struct device *, int, int, int); 597 static void sipcom_dp83820_mii_statchg(struct device *); 598 599 static int sipcom_sis900_mii_readreg(struct device *, int, int); 600 static void sipcom_sis900_mii_writereg(struct device *, int, int, int); 601 static void sipcom_sis900_mii_statchg(struct device *); 602 603 static int sipcom_dp83815_mii_readreg(struct device *, int, int); 604 static void sipcom_dp83815_mii_writereg(struct device *, int, int, int); 605 static void sipcom_dp83815_mii_statchg(struct device *); 606 607 static int sipcom_mediachange(struct ifnet *); 608 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 609 610 static int sipcom_match(struct device *, struct cfdata *, void *); 611 static void sipcom_attach(struct device *, struct device *, void *); 612 static void sipcom_do_detach(device_t, enum sip_attach_stage); 613 static int sipcom_detach(device_t, int); 614 static bool sipcom_resume(device_t); 615 616 int gsip_copy_small = 0; 617 int sip_copy_small = 0; 618 619 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 620 sipcom_match, sipcom_attach, sipcom_detach, NULL); 621 CFATTACH_DECL(sip, sizeof(struct sip_softc), 622 sipcom_match, sipcom_attach, sipcom_detach, NULL); 623 624 /* 625 * Descriptions of the variants of the SiS900. 626 */ 627 struct sip_variant { 628 int (*sipv_mii_readreg)(struct device *, int, int); 629 void (*sipv_mii_writereg)(struct device *, int, int, int); 630 void (*sipv_mii_statchg)(struct device *); 631 void (*sipv_set_filter)(struct sip_softc *); 632 void (*sipv_read_macaddr)(struct sip_softc *, 633 const struct pci_attach_args *, u_int8_t *); 634 }; 635 636 static u_int32_t sipcom_mii_bitbang_read(struct device *); 637 static void sipcom_mii_bitbang_write(struct device *, u_int32_t); 638 639 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 640 sipcom_mii_bitbang_read, 641 sipcom_mii_bitbang_write, 642 { 643 EROMAR_MDIO, /* MII_BIT_MDO */ 644 EROMAR_MDIO, /* MII_BIT_MDI */ 645 EROMAR_MDC, /* MII_BIT_MDC */ 646 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 647 0, /* MII_BIT_DIR_PHY_HOST */ 648 } 649 }; 650 651 static const struct sip_variant sipcom_variant_dp83820 = { 652 sipcom_dp83820_mii_readreg, 653 sipcom_dp83820_mii_writereg, 654 sipcom_dp83820_mii_statchg, 655 sipcom_dp83815_set_filter, 656 sipcom_dp83820_read_macaddr, 657 }; 658 659 static const struct sip_variant sipcom_variant_sis900 = { 660 sipcom_sis900_mii_readreg, 661 sipcom_sis900_mii_writereg, 662 sipcom_sis900_mii_statchg, 663 sipcom_sis900_set_filter, 664 sipcom_sis900_read_macaddr, 665 }; 666 667 static const struct sip_variant sipcom_variant_dp83815 = { 668 sipcom_dp83815_mii_readreg, 669 sipcom_dp83815_mii_writereg, 670 sipcom_dp83815_mii_statchg, 671 sipcom_dp83815_set_filter, 672 sipcom_dp83815_read_macaddr, 673 }; 674 675 676 /* 677 * Devices supported by this driver. 678 */ 679 static const struct sip_product { 680 pci_vendor_id_t sip_vendor; 681 pci_product_id_t sip_product; 682 const char *sip_name; 683 const struct sip_variant *sip_variant; 684 int sip_gigabit; 685 } sipcom_products[] = { 686 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 687 "NatSemi DP83820 Gigabit Ethernet", 688 &sipcom_variant_dp83820, 1 }, 689 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 690 "SiS 900 10/100 Ethernet", 691 &sipcom_variant_sis900, 0 }, 692 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 693 "SiS 7016 10/100 Ethernet", 694 &sipcom_variant_sis900, 0 }, 695 696 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 697 "NatSemi DP83815 10/100 Ethernet", 698 &sipcom_variant_dp83815, 0 }, 699 700 { 0, 0, 701 NULL, 702 NULL, 0 }, 703 }; 704 705 static const struct sip_product * 706 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 707 { 708 const struct sip_product *sip; 709 710 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 711 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 712 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 713 sip->sip_gigabit == gigabit) 714 return sip; 715 } 716 return NULL; 717 } 718 719 /* 720 * I really hate stupid hardware vendors. There's a bit in the EEPROM 721 * which indicates if the card can do 64-bit data transfers. Unfortunately, 722 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 723 * which means we try to use 64-bit data transfers on those cards if we 724 * happen to be plugged into a 32-bit slot. 725 * 726 * What we do is use this table of cards known to be 64-bit cards. If 727 * you have a 64-bit card who's subsystem ID is not listed in this table, 728 * send the output of "pcictl dump ..." of the device to me so that your 729 * card will use the 64-bit data path when plugged into a 64-bit slot. 730 * 731 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 732 * June 30, 2002 733 */ 734 static int 735 sipcom_check_64bit(const struct pci_attach_args *pa) 736 { 737 static const struct { 738 pci_vendor_id_t c64_vendor; 739 pci_product_id_t c64_product; 740 } card64[] = { 741 /* Asante GigaNIX */ 742 { 0x128a, 0x0002 }, 743 744 /* Accton EN1407-T, Planex GN-1000TE */ 745 { 0x1113, 0x1407 }, 746 747 /* Netgear GA-621 */ 748 { 0x1385, 0x621a }, 749 750 /* SMC EZ Card */ 751 { 0x10b8, 0x9462 }, 752 753 { 0, 0} 754 }; 755 pcireg_t subsys; 756 int i; 757 758 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 759 760 for (i = 0; card64[i].c64_vendor != 0; i++) { 761 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 762 PCI_PRODUCT(subsys) == card64[i].c64_product) 763 return (1); 764 } 765 766 return (0); 767 } 768 769 static int 770 sipcom_match(struct device *parent, struct cfdata *cf, void *aux) 771 { 772 struct pci_attach_args *pa = aux; 773 774 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 775 return 1; 776 777 return 0; 778 } 779 780 static void 781 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 782 { 783 u_int32_t reg; 784 int i; 785 786 /* 787 * Cause the chip to load configuration data from the EEPROM. 788 */ 789 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 790 for (i = 0; i < 10000; i++) { 791 delay(10); 792 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) == 0) 794 break; 795 } 796 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 797 PTSCR_EELOAD_EN) { 798 printf("%s: timeout loading configuration from EEPROM\n", 799 sc->sc_dev.dv_xname); 800 return; 801 } 802 803 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 804 805 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 806 if (reg & CFG_PCI64_DET) { 807 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 808 /* 809 * Check to see if this card is 64-bit. If so, enable 64-bit 810 * data transfers. 811 * 812 * We can't use the DATA64_EN bit in the EEPROM, because 813 * vendors of 32-bit cards fail to clear that bit in many 814 * cases (yet the card still detects that it's in a 64-bit 815 * slot; go figure). 816 */ 817 if (sipcom_check_64bit(pa)) { 818 sc->sc_cfg |= CFG_DATA64_EN; 819 printf(", using 64-bit data transfers"); 820 } 821 printf("\n"); 822 } 823 824 /* 825 * XXX Need some PCI flags indicating support for 826 * XXX 64-bit addressing. 827 */ 828 #if 0 829 if (reg & CFG_M64ADDR) 830 sc->sc_cfg |= CFG_M64ADDR; 831 if (reg & CFG_T64ADDR) 832 sc->sc_cfg |= CFG_T64ADDR; 833 #endif 834 835 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 836 const char *sep = ""; 837 printf("%s: using ", sc->sc_dev.dv_xname); 838 if (reg & CFG_EXT_125) { 839 sc->sc_cfg |= CFG_EXT_125; 840 printf("%s125MHz clock", sep); 841 sep = ", "; 842 } 843 if (reg & CFG_TBI_EN) { 844 sc->sc_cfg |= CFG_TBI_EN; 845 printf("%sten-bit interface", sep); 846 sep = ", "; 847 } 848 printf("\n"); 849 } 850 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 851 (reg & CFG_MRM_DIS) != 0) 852 sc->sc_cfg |= CFG_MRM_DIS; 853 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 854 (reg & CFG_MWI_DIS) != 0) 855 sc->sc_cfg |= CFG_MWI_DIS; 856 857 /* 858 * Use the extended descriptor format on the DP83820. This 859 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 860 * checksumming. 861 */ 862 sc->sc_cfg |= CFG_EXTSTS_EN; 863 } 864 865 static int 866 sipcom_detach(device_t self, int flags) 867 { 868 int s; 869 870 s = splnet(); 871 sipcom_do_detach(self, SIP_ATTACH_FIN); 872 splx(s); 873 874 return 0; 875 } 876 877 static void 878 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 879 { 880 int i; 881 struct sip_softc *sc = device_private(self); 882 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 883 884 /* 885 * Free any resources we've allocated during attach. 886 * Do this in reverse order and fall through. 887 */ 888 switch (stage) { 889 case SIP_ATTACH_FIN: 890 sipcom_stop(ifp, 1); 891 pmf_device_deregister(self); 892 #ifdef SIP_EVENT_COUNTERS 893 /* 894 * Attach event counters. 895 */ 896 evcnt_detach(&sc->sc_ev_txforceintr); 897 evcnt_detach(&sc->sc_ev_txdstall); 898 evcnt_detach(&sc->sc_ev_txsstall); 899 evcnt_detach(&sc->sc_ev_hiberr); 900 evcnt_detach(&sc->sc_ev_rxintr); 901 evcnt_detach(&sc->sc_ev_txiintr); 902 evcnt_detach(&sc->sc_ev_txdintr); 903 if (!sc->sc_gigabit) { 904 evcnt_detach(&sc->sc_ev_rxpause); 905 } else { 906 evcnt_detach(&sc->sc_ev_txudpsum); 907 evcnt_detach(&sc->sc_ev_txtcpsum); 908 evcnt_detach(&sc->sc_ev_txipsum); 909 evcnt_detach(&sc->sc_ev_rxudpsum); 910 evcnt_detach(&sc->sc_ev_rxtcpsum); 911 evcnt_detach(&sc->sc_ev_rxipsum); 912 evcnt_detach(&sc->sc_ev_txpause); 913 evcnt_detach(&sc->sc_ev_rxpause); 914 } 915 #endif /* SIP_EVENT_COUNTERS */ 916 917 #if NRND > 0 918 rnd_detach_source(&sc->rnd_source); 919 #endif 920 921 ether_ifdetach(ifp); 922 if_detach(ifp); 923 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 924 925 if (sc->sc_sdhook != NULL) 926 shutdownhook_disestablish(sc->sc_sdhook); 927 928 /*FALLTHROUGH*/ 929 case SIP_ATTACH_CREATE_RXMAP: 930 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 931 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 932 bus_dmamap_destroy(sc->sc_dmat, 933 sc->sc_rxsoft[i].rxs_dmamap); 934 } 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_CREATE_TXMAP: 937 for (i = 0; i < SIP_TXQUEUELEN; i++) { 938 if (sc->sc_txsoft[i].txs_dmamap != NULL) 939 bus_dmamap_destroy(sc->sc_dmat, 940 sc->sc_txsoft[i].txs_dmamap); 941 } 942 /*FALLTHROUGH*/ 943 case SIP_ATTACH_LOAD_MAP: 944 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 945 /*FALLTHROUGH*/ 946 case SIP_ATTACH_CREATE_MAP: 947 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_MAP_MEM: 950 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 951 sizeof(struct sip_control_data)); 952 /*FALLTHROUGH*/ 953 case SIP_ATTACH_ALLOC_MEM: 954 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 955 /* FALLTHROUGH*/ 956 case SIP_ATTACH_INTR: 957 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 958 /* FALLTHROUGH*/ 959 case SIP_ATTACH_MAP: 960 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 961 break; 962 default: 963 break; 964 } 965 return; 966 } 967 968 static bool 969 sipcom_resume(device_t self) 970 { 971 struct sip_softc *sc = device_private(self); 972 973 return sipcom_reset(sc); 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = (struct sip_softc *) self; 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t pmreg; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 998 callout_init(&sc->sc_tick_ch, 0); 999 1000 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1001 if (sip == NULL) { 1002 printf("\n"); 1003 panic("%s: impossible", __func__); 1004 } 1005 sc->sc_gigabit = sip->sip_gigabit; 1006 1007 sc->sc_pc = pc; 1008 1009 if (sc->sc_gigabit) { 1010 sc->sc_rxintr = gsip_rxintr; 1011 sc->sc_parm = &gsip_parm; 1012 } else { 1013 sc->sc_rxintr = sip_rxintr; 1014 sc->sc_parm = &sip_parm; 1015 } 1016 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1017 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1018 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1019 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1020 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1021 1022 sc->sc_rev = PCI_REVISION(pa->pa_class); 1023 1024 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1025 1026 sc->sc_model = sip; 1027 1028 /* 1029 * XXX Work-around broken PXE firmware on some boards. 1030 * 1031 * The DP83815 shares an address decoder with the MEM BAR 1032 * and the ROM BAR. Make sure the ROM BAR is disabled, 1033 * so that memory mapped access works. 1034 */ 1035 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1036 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1037 ~PCI_MAPREG_ROM_ENABLE); 1038 1039 /* 1040 * Map the device. 1041 */ 1042 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1043 PCI_MAPREG_TYPE_IO, 0, 1044 &iot, &ioh, NULL, &iosz) == 0); 1045 if (sc->sc_gigabit) { 1046 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1047 switch (memtype) { 1048 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1049 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1050 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1051 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1052 break; 1053 default: 1054 memh_valid = 0; 1055 } 1056 } else { 1057 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1058 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1059 &memt, &memh, NULL, &memsz) == 0); 1060 } 1061 1062 if (memh_valid) { 1063 sc->sc_st = memt; 1064 sc->sc_sh = memh; 1065 sc->sc_sz = memsz; 1066 } else if (ioh_valid) { 1067 sc->sc_st = iot; 1068 sc->sc_sh = ioh; 1069 sc->sc_sz = iosz; 1070 } else { 1071 printf("%s: unable to map device registers\n", 1072 sc->sc_dev.dv_xname); 1073 return; 1074 } 1075 1076 sc->sc_dmat = pa->pa_dmat; 1077 1078 /* 1079 * Make sure bus mastering is enabled. Also make sure 1080 * Write/Invalidate is enabled if we're allowed to use it. 1081 */ 1082 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1083 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1084 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1085 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1086 pmreg | PCI_COMMAND_MASTER_ENABLE); 1087 1088 /* power up chip */ 1089 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1090 NULL)) && error != EOPNOTSUPP) { 1091 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 1092 error); 1093 return; 1094 } 1095 1096 /* 1097 * Map and establish our interrupt. 1098 */ 1099 if (pci_intr_map(pa, &ih)) { 1100 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 1101 return; 1102 } 1103 intrstr = pci_intr_string(pc, ih); 1104 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1105 if (sc->sc_ih == NULL) { 1106 printf("%s: unable to establish interrupt", 1107 sc->sc_dev.dv_xname); 1108 if (intrstr != NULL) 1109 printf(" at %s", intrstr); 1110 printf("\n"); 1111 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1112 } 1113 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1114 1115 SIMPLEQ_INIT(&sc->sc_txfreeq); 1116 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1117 1118 /* 1119 * Allocate the control data structures, and create and load the 1120 * DMA map for it. 1121 */ 1122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1123 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1124 &rseg, 0)) != 0) { 1125 printf("%s: unable to allocate control data, error = %d\n", 1126 sc->sc_dev.dv_xname, error); 1127 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1128 } 1129 1130 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1131 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1132 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1133 printf("%s: unable to map control data, error = %d\n", 1134 sc->sc_dev.dv_xname, error); 1135 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1136 } 1137 1138 if ((error = bus_dmamap_create(sc->sc_dmat, 1139 sizeof(struct sip_control_data), 1, 1140 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1141 printf("%s: unable to create control data DMA map, " 1142 "error = %d\n", sc->sc_dev.dv_xname, error); 1143 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1144 } 1145 1146 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1147 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1148 0)) != 0) { 1149 printf("%s: unable to load control data DMA map, error = %d\n", 1150 sc->sc_dev.dv_xname, error); 1151 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1152 } 1153 1154 /* 1155 * Create the transmit buffer DMA maps. 1156 */ 1157 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1158 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1159 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1160 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1161 printf("%s: unable to create tx DMA map %d, " 1162 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1163 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1164 } 1165 } 1166 1167 /* 1168 * Create the receive buffer DMA maps. 1169 */ 1170 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1171 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1172 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1173 printf("%s: unable to create rx DMA map %d, " 1174 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1175 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1176 } 1177 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1178 } 1179 1180 /* 1181 * Reset the chip to a known state. 1182 */ 1183 sipcom_reset(sc); 1184 1185 /* 1186 * Read the Ethernet address from the EEPROM. This might 1187 * also fetch other stuff from the EEPROM and stash it 1188 * in the softc. 1189 */ 1190 sc->sc_cfg = 0; 1191 if (!sc->sc_gigabit) { 1192 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1193 SIP_SIS900_REV(sc,SIS_REV_900B)) 1194 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1195 1196 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1197 SIP_SIS900_REV(sc,SIS_REV_960) || 1198 SIP_SIS900_REV(sc,SIS_REV_900B)) 1199 sc->sc_cfg |= 1200 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1201 CFG_EDBMASTEN); 1202 } 1203 1204 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1205 1206 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1207 ether_sprintf(enaddr)); 1208 1209 /* 1210 * Initialize the configuration register: aggressive PCI 1211 * bus request algorithm, default backoff, default OW timer, 1212 * default parity error detection. 1213 * 1214 * NOTE: "Big endian mode" is useless on the SiS900 and 1215 * friends -- it affects packet data, not descriptors. 1216 */ 1217 if (sc->sc_gigabit) 1218 sipcom_dp83820_attach(sc, pa); 1219 1220 /* 1221 * Initialize our media structures and probe the MII. 1222 */ 1223 sc->sc_mii.mii_ifp = ifp; 1224 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1225 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1226 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1227 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, sipcom_mediachange, 1228 sipcom_mediastatus); 1229 1230 /* 1231 * XXX We cannot handle flow control on the DP83815. 1232 */ 1233 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1234 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1235 MII_OFFSET_ANY, 0); 1236 else 1237 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, MIIF_DOPAUSE); 1239 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1240 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1241 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1242 } else 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1244 1245 ifp = &sc->sc_ethercom.ec_if; 1246 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1247 ifp->if_softc = sc; 1248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1249 sc->sc_if_flags = ifp->if_flags; 1250 ifp->if_ioctl = sipcom_ioctl; 1251 ifp->if_start = sipcom_start; 1252 ifp->if_watchdog = sipcom_watchdog; 1253 ifp->if_init = sipcom_init; 1254 ifp->if_stop = sipcom_stop; 1255 IFQ_SET_READY(&ifp->if_snd); 1256 1257 /* 1258 * We can support 802.1Q VLAN-sized frames. 1259 */ 1260 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1261 1262 if (sc->sc_gigabit) { 1263 /* 1264 * And the DP83820 can do VLAN tagging in hardware, and 1265 * support the jumbo Ethernet MTU. 1266 */ 1267 sc->sc_ethercom.ec_capabilities |= 1268 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1269 1270 /* 1271 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1272 * in hardware. 1273 */ 1274 ifp->if_capabilities |= 1275 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1276 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1277 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1278 } 1279 1280 /* 1281 * Attach the interface. 1282 */ 1283 if_attach(ifp); 1284 ether_ifattach(ifp, enaddr); 1285 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1286 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1287 sc->sc_prev.if_capenable = ifp->if_capenable; 1288 #if NRND > 0 1289 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1290 RND_TYPE_NET, 0); 1291 #endif 1292 1293 /* 1294 * The number of bytes that must be available in 1295 * the Tx FIFO before the bus master can DMA more 1296 * data into the FIFO. 1297 */ 1298 sc->sc_tx_fill_thresh = 64 / 32; 1299 1300 /* 1301 * Start at a drain threshold of 512 bytes. We will 1302 * increase it if a DMA underrun occurs. 1303 * 1304 * XXX The minimum value of this variable should be 1305 * tuned. We may be able to improve performance 1306 * by starting with a lower value. That, however, 1307 * may trash the first few outgoing packets if the 1308 * PCI bus is saturated. 1309 */ 1310 if (sc->sc_gigabit) 1311 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1312 else 1313 sc->sc_tx_drain_thresh = 1504 / 32; 1314 1315 /* 1316 * Initialize the Rx FIFO drain threshold. 1317 * 1318 * This is in units of 8 bytes. 1319 * 1320 * We should never set this value lower than 2; 14 bytes are 1321 * required to filter the packet. 1322 */ 1323 sc->sc_rx_drain_thresh = 128 / 8; 1324 1325 #ifdef SIP_EVENT_COUNTERS 1326 /* 1327 * Attach event counters. 1328 */ 1329 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1330 NULL, sc->sc_dev.dv_xname, "txsstall"); 1331 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1332 NULL, sc->sc_dev.dv_xname, "txdstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1334 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1336 NULL, sc->sc_dev.dv_xname, "txdintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1338 NULL, sc->sc_dev.dv_xname, "txiintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1340 NULL, sc->sc_dev.dv_xname, "rxintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1342 NULL, sc->sc_dev.dv_xname, "hiberr"); 1343 if (!sc->sc_gigabit) { 1344 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1345 NULL, sc->sc_dev.dv_xname, "rxpause"); 1346 } else { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1348 NULL, sc->sc_dev.dv_xname, "rxpause"); 1349 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1350 NULL, sc->sc_dev.dv_xname, "txpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1352 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1354 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1356 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1358 NULL, sc->sc_dev.dv_xname, "txipsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1360 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1362 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1363 } 1364 #endif /* SIP_EVENT_COUNTERS */ 1365 1366 if (!pmf_device_register(self, NULL, sipcom_resume)) 1367 aprint_error_dev(self, "couldn't establish power handler\n"); 1368 else 1369 pmf_class_network_register(self, ifp); 1370 1371 /* 1372 * Make sure the interface is shutdown during reboot. 1373 */ 1374 sc->sc_sdhook = shutdownhook_establish(sipcom_shutdown, sc); 1375 if (sc->sc_sdhook == NULL) 1376 printf("%s: WARNING: unable to establish shutdown hook\n", 1377 sc->sc_dev.dv_xname); 1378 } 1379 1380 /* 1381 * sip_shutdown: 1382 * 1383 * Make sure the interface is stopped at reboot time. 1384 */ 1385 static void 1386 sipcom_shutdown(void *arg) 1387 { 1388 struct sip_softc *sc = arg; 1389 1390 sipcom_stop(&sc->sc_ethercom.ec_if, 1); 1391 } 1392 1393 static inline void 1394 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1395 uint64_t capenable) 1396 { 1397 struct m_tag *mtag; 1398 u_int32_t extsts; 1399 #ifdef DEBUG 1400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1401 #endif 1402 /* 1403 * If VLANs are enabled and the packet has a VLAN tag, set 1404 * up the descriptor to encapsulate the packet for us. 1405 * 1406 * This apparently has to be on the last descriptor of 1407 * the packet. 1408 */ 1409 1410 /* 1411 * Byte swapping is tricky. We need to provide the tag 1412 * in a network byte order. On a big-endian machine, 1413 * the byteorder is correct, but we need to swap it 1414 * anyway, because this will be undone by the outside 1415 * htole32(). That's why there must be an 1416 * unconditional swap instead of htons() inside. 1417 */ 1418 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1419 sc->sc_txdescs[lasttx].sipd_extsts |= 1420 htole32(EXTSTS_VPKT | 1421 (bswap16(VLAN_TAG_VALUE(mtag)) & 1422 EXTSTS_VTCI)); 1423 } 1424 1425 /* 1426 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1427 * checksumming, set up the descriptor to do this work 1428 * for us. 1429 * 1430 * This apparently has to be on the first descriptor of 1431 * the packet. 1432 * 1433 * Byte-swap constants so the compiler can optimize. 1434 */ 1435 extsts = 0; 1436 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1437 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1438 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1439 extsts |= htole32(EXTSTS_IPPKT); 1440 } 1441 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1442 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1443 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1444 extsts |= htole32(EXTSTS_TCPPKT); 1445 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1446 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1447 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1448 extsts |= htole32(EXTSTS_UDPPKT); 1449 } 1450 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1451 } 1452 1453 /* 1454 * sip_start: [ifnet interface function] 1455 * 1456 * Start packet transmission on the interface. 1457 */ 1458 static void 1459 sipcom_start(struct ifnet *ifp) 1460 { 1461 struct sip_softc *sc = ifp->if_softc; 1462 struct mbuf *m0; 1463 struct mbuf *m; 1464 struct sip_txsoft *txs; 1465 bus_dmamap_t dmamap; 1466 int error, nexttx, lasttx, seg; 1467 int ofree = sc->sc_txfree; 1468 #if 0 1469 int firsttx = sc->sc_txnext; 1470 #endif 1471 1472 /* 1473 * If we've been told to pause, don't transmit any more packets. 1474 */ 1475 if (!sc->sc_gigabit && sc->sc_paused) 1476 ifp->if_flags |= IFF_OACTIVE; 1477 1478 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1479 return; 1480 1481 /* 1482 * Loop through the send queue, setting up transmit descriptors 1483 * until we drain the queue, or use up all available transmit 1484 * descriptors. 1485 */ 1486 for (;;) { 1487 /* Get a work queue entry. */ 1488 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1489 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1490 break; 1491 } 1492 1493 /* 1494 * Grab a packet off the queue. 1495 */ 1496 IFQ_POLL(&ifp->if_snd, m0); 1497 if (m0 == NULL) 1498 break; 1499 m = NULL; 1500 1501 dmamap = txs->txs_dmamap; 1502 1503 /* 1504 * Load the DMA map. If this fails, the packet either 1505 * didn't fit in the alloted number of segments, or we 1506 * were short on resources. 1507 */ 1508 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1509 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1510 /* In the non-gigabit case, we'll copy and try again. */ 1511 if (error != 0 && !sc->sc_gigabit) { 1512 MGETHDR(m, M_DONTWAIT, MT_DATA); 1513 if (m == NULL) { 1514 printf("%s: unable to allocate Tx mbuf\n", 1515 sc->sc_dev.dv_xname); 1516 break; 1517 } 1518 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1519 if (m0->m_pkthdr.len > MHLEN) { 1520 MCLGET(m, M_DONTWAIT); 1521 if ((m->m_flags & M_EXT) == 0) { 1522 printf("%s: unable to allocate Tx " 1523 "cluster\n", sc->sc_dev.dv_xname); 1524 m_freem(m); 1525 break; 1526 } 1527 } 1528 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1529 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1530 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1531 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1532 if (error) { 1533 printf("%s: unable to load Tx buffer, " 1534 "error = %d\n", sc->sc_dev.dv_xname, error); 1535 break; 1536 } 1537 } else if (error == EFBIG) { 1538 /* 1539 * For the too-many-segments case, we simply 1540 * report an error and drop the packet, 1541 * since we can't sanely copy a jumbo packet 1542 * to a single buffer. 1543 */ 1544 printf("%s: Tx packet consumes too many " 1545 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1546 IFQ_DEQUEUE(&ifp->if_snd, m0); 1547 m_freem(m0); 1548 continue; 1549 } else if (error != 0) { 1550 /* 1551 * Short on resources, just stop for now. 1552 */ 1553 break; 1554 } 1555 1556 /* 1557 * Ensure we have enough descriptors free to describe 1558 * the packet. Note, we always reserve one descriptor 1559 * at the end of the ring as a termination point, to 1560 * prevent wrap-around. 1561 */ 1562 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1563 /* 1564 * Not enough free descriptors to transmit this 1565 * packet. We haven't committed anything yet, 1566 * so just unload the DMA map, put the packet 1567 * back on the queue, and punt. Notify the upper 1568 * layer that there are not more slots left. 1569 * 1570 * XXX We could allocate an mbuf and copy, but 1571 * XXX is it worth it? 1572 */ 1573 ifp->if_flags |= IFF_OACTIVE; 1574 bus_dmamap_unload(sc->sc_dmat, dmamap); 1575 if (m != NULL) 1576 m_freem(m); 1577 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1578 break; 1579 } 1580 1581 IFQ_DEQUEUE(&ifp->if_snd, m0); 1582 if (m != NULL) { 1583 m_freem(m0); 1584 m0 = m; 1585 } 1586 1587 /* 1588 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1589 */ 1590 1591 /* Sync the DMA map. */ 1592 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1593 BUS_DMASYNC_PREWRITE); 1594 1595 /* 1596 * Initialize the transmit descriptors. 1597 */ 1598 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1599 seg < dmamap->dm_nsegs; 1600 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1601 /* 1602 * If this is the first descriptor we're 1603 * enqueueing, don't set the OWN bit just 1604 * yet. That could cause a race condition. 1605 * We'll do it below. 1606 */ 1607 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1608 htole32(dmamap->dm_segs[seg].ds_addr); 1609 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1610 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1611 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1612 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1613 lasttx = nexttx; 1614 } 1615 1616 /* Clear the MORE bit on the last segment. */ 1617 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1618 htole32(~CMDSTS_MORE); 1619 1620 /* 1621 * If we're in the interrupt delay window, delay the 1622 * interrupt. 1623 */ 1624 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1625 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1626 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1627 htole32(CMDSTS_INTR); 1628 sc->sc_txwin = 0; 1629 } 1630 1631 if (sc->sc_gigabit) 1632 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1633 1634 /* Sync the descriptors we're using. */ 1635 SIP_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1636 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1637 1638 /* 1639 * The entire packet is set up. Give the first descrptor 1640 * to the chip now. 1641 */ 1642 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1643 htole32(CMDSTS_OWN); 1644 SIP_CDTXSYNC(sc, sc->sc_txnext, 1, 1645 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1646 1647 /* 1648 * Store a pointer to the packet so we can free it later, 1649 * and remember what txdirty will be once the packet is 1650 * done. 1651 */ 1652 txs->txs_mbuf = m0; 1653 txs->txs_firstdesc = sc->sc_txnext; 1654 txs->txs_lastdesc = lasttx; 1655 1656 /* Advance the tx pointer. */ 1657 sc->sc_txfree -= dmamap->dm_nsegs; 1658 sc->sc_txnext = nexttx; 1659 1660 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1661 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1662 1663 #if NBPFILTER > 0 1664 /* 1665 * Pass the packet to any BPF listeners. 1666 */ 1667 if (ifp->if_bpf) 1668 bpf_mtap(ifp->if_bpf, m0); 1669 #endif /* NBPFILTER > 0 */ 1670 } 1671 1672 if (txs == NULL || sc->sc_txfree == 0) { 1673 /* No more slots left; notify upper layer. */ 1674 ifp->if_flags |= IFF_OACTIVE; 1675 } 1676 1677 if (sc->sc_txfree != ofree) { 1678 /* 1679 * Start the transmit process. Note, the manual says 1680 * that if there are no pending transmissions in the 1681 * chip's internal queue (indicated by TXE being clear), 1682 * then the driver software must set the TXDP to the 1683 * first descriptor to be transmitted. However, if we 1684 * do this, it causes serious performance degredation on 1685 * the DP83820 under load, not setting TXDP doesn't seem 1686 * to adversely affect the SiS 900 or DP83815. 1687 * 1688 * Well, I guess it wouldn't be the first time a manual 1689 * has lied -- and they could be speaking of the NULL- 1690 * terminated descriptor list case, rather than OWN- 1691 * terminated rings. 1692 */ 1693 #if 0 1694 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1695 CR_TXE) == 0) { 1696 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1697 SIP_CDTXADDR(sc, firsttx)); 1698 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1699 } 1700 #else 1701 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1702 #endif 1703 1704 /* Set a watchdog timer in case the chip flakes out. */ 1705 /* Gigabit autonegotiation takes 5 seconds. */ 1706 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1707 } 1708 } 1709 1710 /* 1711 * sip_watchdog: [ifnet interface function] 1712 * 1713 * Watchdog timer handler. 1714 */ 1715 static void 1716 sipcom_watchdog(struct ifnet *ifp) 1717 { 1718 struct sip_softc *sc = ifp->if_softc; 1719 1720 /* 1721 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1722 * If we get a timeout, try and sweep up transmit descriptors. 1723 * If we manage to sweep them all up, ignore the lack of 1724 * interrupt. 1725 */ 1726 sipcom_txintr(sc); 1727 1728 if (sc->sc_txfree != sc->sc_ntxdesc) { 1729 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1730 ifp->if_oerrors++; 1731 1732 /* Reset the interface. */ 1733 (void) sipcom_init(ifp); 1734 } else if (ifp->if_flags & IFF_DEBUG) 1735 printf("%s: recovered from device timeout\n", 1736 sc->sc_dev.dv_xname); 1737 1738 /* Try to get more packets going. */ 1739 sipcom_start(ifp); 1740 } 1741 1742 /* 1743 * sip_ioctl: [ifnet interface function] 1744 * 1745 * Handle control requests from the operator. 1746 */ 1747 static int 1748 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1749 { 1750 struct sip_softc *sc = ifp->if_softc; 1751 struct ifreq *ifr = (struct ifreq *)data; 1752 int s, error; 1753 1754 s = splnet(); 1755 1756 switch (cmd) { 1757 case SIOCSIFMEDIA: 1758 /* Flow control requires full-duplex mode. */ 1759 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1760 (ifr->ifr_media & IFM_FDX) == 0) 1761 ifr->ifr_media &= ~IFM_ETH_FMASK; 1762 1763 /* XXX */ 1764 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1765 ifr->ifr_media &= ~IFM_ETH_FMASK; 1766 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1767 if (sc->sc_gigabit && 1768 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1769 /* We can do both TXPAUSE and RXPAUSE. */ 1770 ifr->ifr_media |= 1771 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1772 } else if (ifr->ifr_media & IFM_FLOW) { 1773 /* 1774 * Both TXPAUSE and RXPAUSE must be set. 1775 * (SiS900 and DP83815 don't have PAUSE_ASYM 1776 * feature.) 1777 * 1778 * XXX Can SiS900 and DP83815 send PAUSE? 1779 */ 1780 ifr->ifr_media |= 1781 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1782 } 1783 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1784 } 1785 /* FALLTHROUGH */ 1786 case SIOCGIFMEDIA: 1787 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1788 break; 1789 case SIOCSIFFLAGS: 1790 /* If the interface is up and running, only modify the receive 1791 * filter when setting promiscuous or debug mode. Otherwise 1792 * fall through to ether_ioctl, which will reset the chip. 1793 */ 1794 1795 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1796 == (sc)->sc_ethercom.ec_capenable) \ 1797 && ((sc)->sc_prev.is_vlan == \ 1798 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1799 1800 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1801 1802 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1803 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1804 == (IFF_UP|IFF_RUNNING)) 1805 && ((ifp->if_flags & (~RESETIGN)) 1806 == (sc->sc_if_flags & (~RESETIGN))) 1807 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1808 /* Set up the receive filter. */ 1809 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1810 error = 0; 1811 break; 1812 #undef RESETIGN 1813 } 1814 /* FALLTHROUGH */ 1815 default: 1816 error = ether_ioctl(ifp, cmd, data); 1817 if (error == ENETRESET) { 1818 /* 1819 * Multicast list has changed; set the hardware filter 1820 * accordingly. 1821 */ 1822 if (ifp->if_flags & IFF_RUNNING) 1823 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1824 error = 0; 1825 } 1826 break; 1827 } 1828 1829 /* Try to get more packets going. */ 1830 sipcom_start(ifp); 1831 1832 sc->sc_if_flags = ifp->if_flags; 1833 splx(s); 1834 return (error); 1835 } 1836 1837 /* 1838 * sip_intr: 1839 * 1840 * Interrupt service routine. 1841 */ 1842 static int 1843 sipcom_intr(void *arg) 1844 { 1845 struct sip_softc *sc = arg; 1846 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1847 u_int32_t isr; 1848 int handled = 0; 1849 1850 /* Disable interrupts. */ 1851 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1852 1853 for (;;) { 1854 /* Reading clears interrupt. */ 1855 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1856 if ((isr & sc->sc_imr) == 0) 1857 break; 1858 1859 #if NRND > 0 1860 if (RND_ENABLED(&sc->rnd_source)) 1861 rnd_add_uint32(&sc->rnd_source, isr); 1862 #endif 1863 1864 handled = 1; 1865 1866 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1867 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1868 1869 /* Grab any new packets. */ 1870 (*sc->sc_rxintr)(sc); 1871 1872 if (isr & ISR_RXORN) { 1873 printf("%s: receive FIFO overrun\n", 1874 sc->sc_dev.dv_xname); 1875 1876 /* XXX adjust rx_drain_thresh? */ 1877 } 1878 1879 if (isr & ISR_RXIDLE) { 1880 printf("%s: receive ring overrun\n", 1881 sc->sc_dev.dv_xname); 1882 1883 /* Get the receive process going again. */ 1884 bus_space_write_4(sc->sc_st, sc->sc_sh, 1885 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1886 bus_space_write_4(sc->sc_st, sc->sc_sh, 1887 SIP_CR, CR_RXE); 1888 } 1889 } 1890 1891 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1892 #ifdef SIP_EVENT_COUNTERS 1893 if (isr & ISR_TXDESC) 1894 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1895 else if (isr & ISR_TXIDLE) 1896 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1897 #endif 1898 1899 /* Sweep up transmit descriptors. */ 1900 sipcom_txintr(sc); 1901 1902 if (isr & ISR_TXURN) { 1903 u_int32_t thresh; 1904 int txfifo_size = (sc->sc_gigabit) 1905 ? DP83820_SIP_TXFIFO_SIZE 1906 : OTHER_SIP_TXFIFO_SIZE; 1907 1908 printf("%s: transmit FIFO underrun", 1909 sc->sc_dev.dv_xname); 1910 thresh = sc->sc_tx_drain_thresh + 1; 1911 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1912 && (thresh * 32) <= (txfifo_size - 1913 (sc->sc_tx_fill_thresh * 32))) { 1914 printf("; increasing Tx drain " 1915 "threshold to %u bytes\n", 1916 thresh * 32); 1917 sc->sc_tx_drain_thresh = thresh; 1918 (void) sipcom_init(ifp); 1919 } else { 1920 (void) sipcom_init(ifp); 1921 printf("\n"); 1922 } 1923 } 1924 } 1925 1926 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1927 if (isr & ISR_PAUSE_ST) { 1928 sc->sc_paused = 1; 1929 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1930 ifp->if_flags |= IFF_OACTIVE; 1931 } 1932 if (isr & ISR_PAUSE_END) { 1933 sc->sc_paused = 0; 1934 ifp->if_flags &= ~IFF_OACTIVE; 1935 } 1936 } 1937 1938 if (isr & ISR_HIBERR) { 1939 int want_init = 0; 1940 1941 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1942 1943 #define PRINTERR(bit, str) \ 1944 do { \ 1945 if ((isr & (bit)) != 0) { \ 1946 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1947 printf("%s: %s\n", \ 1948 sc->sc_dev.dv_xname, str); \ 1949 want_init = 1; \ 1950 } \ 1951 } while (/*CONSTCOND*/0) 1952 1953 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1954 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1955 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1956 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1957 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1958 /* 1959 * Ignore: 1960 * Tx reset complete 1961 * Rx reset complete 1962 */ 1963 if (want_init) 1964 (void) sipcom_init(ifp); 1965 #undef PRINTERR 1966 } 1967 } 1968 1969 /* Re-enable interrupts. */ 1970 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1971 1972 /* Try to get more packets going. */ 1973 sipcom_start(ifp); 1974 1975 return (handled); 1976 } 1977 1978 /* 1979 * sip_txintr: 1980 * 1981 * Helper; handle transmit interrupts. 1982 */ 1983 static void 1984 sipcom_txintr(struct sip_softc *sc) 1985 { 1986 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1987 struct sip_txsoft *txs; 1988 u_int32_t cmdsts; 1989 1990 if (sc->sc_paused == 0) 1991 ifp->if_flags &= ~IFF_OACTIVE; 1992 1993 /* 1994 * Go through our Tx list and free mbufs for those 1995 * frames which have been transmitted. 1996 */ 1997 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1998 SIP_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1999 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2000 2001 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2002 if (cmdsts & CMDSTS_OWN) 2003 break; 2004 2005 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2006 2007 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2008 2009 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2010 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2011 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2012 m_freem(txs->txs_mbuf); 2013 txs->txs_mbuf = NULL; 2014 2015 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2016 2017 /* 2018 * Check for errors and collisions. 2019 */ 2020 if (cmdsts & 2021 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2022 ifp->if_oerrors++; 2023 if (cmdsts & CMDSTS_Tx_EC) 2024 ifp->if_collisions += 16; 2025 if (ifp->if_flags & IFF_DEBUG) { 2026 if (cmdsts & CMDSTS_Tx_ED) 2027 printf("%s: excessive deferral\n", 2028 sc->sc_dev.dv_xname); 2029 if (cmdsts & CMDSTS_Tx_EC) 2030 printf("%s: excessive collisions\n", 2031 sc->sc_dev.dv_xname); 2032 } 2033 } else { 2034 /* Packet was transmitted successfully. */ 2035 ifp->if_opackets++; 2036 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2037 } 2038 } 2039 2040 /* 2041 * If there are no more pending transmissions, cancel the watchdog 2042 * timer. 2043 */ 2044 if (txs == NULL) { 2045 ifp->if_timer = 0; 2046 sc->sc_txwin = 0; 2047 } 2048 } 2049 2050 /* 2051 * gsip_rxintr: 2052 * 2053 * Helper; handle receive interrupts on gigabit parts. 2054 */ 2055 static void 2056 gsip_rxintr(struct sip_softc *sc) 2057 { 2058 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2059 struct sip_rxsoft *rxs; 2060 struct mbuf *m; 2061 u_int32_t cmdsts, extsts; 2062 int i, len; 2063 2064 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2065 rxs = &sc->sc_rxsoft[i]; 2066 2067 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2068 2069 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2070 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2071 len = CMDSTS_SIZE(sc, cmdsts); 2072 2073 /* 2074 * NOTE: OWN is set if owned by _consumer_. We're the 2075 * consumer of the receive ring, so if the bit is clear, 2076 * we have processed all of the packets. 2077 */ 2078 if ((cmdsts & CMDSTS_OWN) == 0) { 2079 /* 2080 * We have processed all of the receive buffers. 2081 */ 2082 break; 2083 } 2084 2085 if (__predict_false(sc->sc_rxdiscard)) { 2086 SIP_INIT_RXDESC(sc, i); 2087 if ((cmdsts & CMDSTS_MORE) == 0) { 2088 /* Reset our state. */ 2089 sc->sc_rxdiscard = 0; 2090 } 2091 continue; 2092 } 2093 2094 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2095 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2096 2097 m = rxs->rxs_mbuf; 2098 2099 /* 2100 * Add a new receive buffer to the ring. 2101 */ 2102 if (sipcom_add_rxbuf(sc, i) != 0) { 2103 /* 2104 * Failed, throw away what we've done so 2105 * far, and discard the rest of the packet. 2106 */ 2107 ifp->if_ierrors++; 2108 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2109 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2110 SIP_INIT_RXDESC(sc, i); 2111 if (cmdsts & CMDSTS_MORE) 2112 sc->sc_rxdiscard = 1; 2113 if (sc->sc_rxhead != NULL) 2114 m_freem(sc->sc_rxhead); 2115 SIP_RXCHAIN_RESET(sc); 2116 continue; 2117 } 2118 2119 SIP_RXCHAIN_LINK(sc, m); 2120 2121 m->m_len = len; 2122 2123 /* 2124 * If this is not the end of the packet, keep 2125 * looking. 2126 */ 2127 if (cmdsts & CMDSTS_MORE) { 2128 sc->sc_rxlen += len; 2129 continue; 2130 } 2131 2132 /* 2133 * Okay, we have the entire packet now. The chip includes 2134 * the FCS, so we need to trim it. 2135 */ 2136 m->m_len -= ETHER_CRC_LEN; 2137 2138 *sc->sc_rxtailp = NULL; 2139 len = m->m_len + sc->sc_rxlen; 2140 m = sc->sc_rxhead; 2141 2142 SIP_RXCHAIN_RESET(sc); 2143 2144 /* 2145 * If an error occurred, update stats and drop the packet. 2146 */ 2147 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2148 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2149 ifp->if_ierrors++; 2150 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2151 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2152 /* Receive overrun handled elsewhere. */ 2153 printf("%s: receive descriptor error\n", 2154 sc->sc_dev.dv_xname); 2155 } 2156 #define PRINTERR(bit, str) \ 2157 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2158 (cmdsts & (bit)) != 0) \ 2159 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2160 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2161 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2162 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2163 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2164 #undef PRINTERR 2165 m_freem(m); 2166 continue; 2167 } 2168 2169 /* 2170 * If the packet is small enough to fit in a 2171 * single header mbuf, allocate one and copy 2172 * the data into it. This greatly reduces 2173 * memory consumption when we receive lots 2174 * of small packets. 2175 */ 2176 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2177 struct mbuf *nm; 2178 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2179 if (nm == NULL) { 2180 ifp->if_ierrors++; 2181 m_freem(m); 2182 continue; 2183 } 2184 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2185 nm->m_data += 2; 2186 nm->m_pkthdr.len = nm->m_len = len; 2187 m_copydata(m, 0, len, mtod(nm, void *)); 2188 m_freem(m); 2189 m = nm; 2190 } 2191 #ifndef __NO_STRICT_ALIGNMENT 2192 else { 2193 /* 2194 * The DP83820's receive buffers must be 4-byte 2195 * aligned. But this means that the data after 2196 * the Ethernet header is misaligned. To compensate, 2197 * we have artificially shortened the buffer size 2198 * in the descriptor, and we do an overlapping copy 2199 * of the data two bytes further in (in the first 2200 * buffer of the chain only). 2201 */ 2202 memmove(mtod(m, char *) + 2, mtod(m, void *), 2203 m->m_len); 2204 m->m_data += 2; 2205 } 2206 #endif /* ! __NO_STRICT_ALIGNMENT */ 2207 2208 /* 2209 * If VLANs are enabled, VLAN packets have been unwrapped 2210 * for us. Associate the tag with the packet. 2211 */ 2212 2213 /* 2214 * Again, byte swapping is tricky. Hardware provided 2215 * the tag in the network byte order, but extsts was 2216 * passed through le32toh() in the meantime. On a 2217 * big-endian machine, we need to swap it again. On a 2218 * little-endian machine, we need to convert from the 2219 * network to host byte order. This means that we must 2220 * swap it in any case, so unconditional swap instead 2221 * of htons() is used. 2222 */ 2223 if ((extsts & EXTSTS_VPKT) != 0) { 2224 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2225 continue); 2226 } 2227 2228 /* 2229 * Set the incoming checksum information for the 2230 * packet. 2231 */ 2232 if ((extsts & EXTSTS_IPPKT) != 0) { 2233 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2234 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2235 if (extsts & EXTSTS_Rx_IPERR) 2236 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2237 if (extsts & EXTSTS_TCPPKT) { 2238 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2239 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2240 if (extsts & EXTSTS_Rx_TCPERR) 2241 m->m_pkthdr.csum_flags |= 2242 M_CSUM_TCP_UDP_BAD; 2243 } else if (extsts & EXTSTS_UDPPKT) { 2244 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2245 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2246 if (extsts & EXTSTS_Rx_UDPERR) 2247 m->m_pkthdr.csum_flags |= 2248 M_CSUM_TCP_UDP_BAD; 2249 } 2250 } 2251 2252 ifp->if_ipackets++; 2253 m->m_pkthdr.rcvif = ifp; 2254 m->m_pkthdr.len = len; 2255 2256 #if NBPFILTER > 0 2257 /* 2258 * Pass this up to any BPF listeners, but only 2259 * pass if up the stack if it's for us. 2260 */ 2261 if (ifp->if_bpf) 2262 bpf_mtap(ifp->if_bpf, m); 2263 #endif /* NBPFILTER > 0 */ 2264 2265 /* Pass it on. */ 2266 (*ifp->if_input)(ifp, m); 2267 } 2268 2269 /* Update the receive pointer. */ 2270 sc->sc_rxptr = i; 2271 } 2272 2273 /* 2274 * sip_rxintr: 2275 * 2276 * Helper; handle receive interrupts on 10/100 parts. 2277 */ 2278 static void 2279 sip_rxintr(struct sip_softc *sc) 2280 { 2281 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2282 struct sip_rxsoft *rxs; 2283 struct mbuf *m; 2284 u_int32_t cmdsts; 2285 int i, len; 2286 2287 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2288 rxs = &sc->sc_rxsoft[i]; 2289 2290 SIP_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2291 2292 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2293 2294 /* 2295 * NOTE: OWN is set if owned by _consumer_. We're the 2296 * consumer of the receive ring, so if the bit is clear, 2297 * we have processed all of the packets. 2298 */ 2299 if ((cmdsts & CMDSTS_OWN) == 0) { 2300 /* 2301 * We have processed all of the receive buffers. 2302 */ 2303 break; 2304 } 2305 2306 /* 2307 * If any collisions were seen on the wire, count one. 2308 */ 2309 if (cmdsts & CMDSTS_Rx_COL) 2310 ifp->if_collisions++; 2311 2312 /* 2313 * If an error occurred, update stats, clear the status 2314 * word, and leave the packet buffer in place. It will 2315 * simply be reused the next time the ring comes around. 2316 */ 2317 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2318 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2319 ifp->if_ierrors++; 2320 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2321 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2322 /* Receive overrun handled elsewhere. */ 2323 printf("%s: receive descriptor error\n", 2324 sc->sc_dev.dv_xname); 2325 } 2326 #define PRINTERR(bit, str) \ 2327 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2328 (cmdsts & (bit)) != 0) \ 2329 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2330 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2331 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2332 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2333 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2334 #undef PRINTERR 2335 SIP_INIT_RXDESC(sc, i); 2336 continue; 2337 } 2338 2339 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2340 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2341 2342 /* 2343 * No errors; receive the packet. Note, the SiS 900 2344 * includes the CRC with every packet. 2345 */ 2346 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2347 2348 #ifdef __NO_STRICT_ALIGNMENT 2349 /* 2350 * If the packet is small enough to fit in a 2351 * single header mbuf, allocate one and copy 2352 * the data into it. This greatly reduces 2353 * memory consumption when we receive lots 2354 * of small packets. 2355 * 2356 * Otherwise, we add a new buffer to the receive 2357 * chain. If this fails, we drop the packet and 2358 * recycle the old buffer. 2359 */ 2360 if (sip_copy_small != 0 && len <= MHLEN) { 2361 MGETHDR(m, M_DONTWAIT, MT_DATA); 2362 if (m == NULL) 2363 goto dropit; 2364 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2365 memcpy(mtod(m, void *), 2366 mtod(rxs->rxs_mbuf, void *), len); 2367 SIP_INIT_RXDESC(sc, i); 2368 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2369 rxs->rxs_dmamap->dm_mapsize, 2370 BUS_DMASYNC_PREREAD); 2371 } else { 2372 m = rxs->rxs_mbuf; 2373 if (sipcom_add_rxbuf(sc, i) != 0) { 2374 dropit: 2375 ifp->if_ierrors++; 2376 SIP_INIT_RXDESC(sc, i); 2377 bus_dmamap_sync(sc->sc_dmat, 2378 rxs->rxs_dmamap, 0, 2379 rxs->rxs_dmamap->dm_mapsize, 2380 BUS_DMASYNC_PREREAD); 2381 continue; 2382 } 2383 } 2384 #else 2385 /* 2386 * The SiS 900's receive buffers must be 4-byte aligned. 2387 * But this means that the data after the Ethernet header 2388 * is misaligned. We must allocate a new buffer and 2389 * copy the data, shifted forward 2 bytes. 2390 */ 2391 MGETHDR(m, M_DONTWAIT, MT_DATA); 2392 if (m == NULL) { 2393 dropit: 2394 ifp->if_ierrors++; 2395 SIP_INIT_RXDESC(sc, i); 2396 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2397 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2398 continue; 2399 } 2400 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2401 if (len > (MHLEN - 2)) { 2402 MCLGET(m, M_DONTWAIT); 2403 if ((m->m_flags & M_EXT) == 0) { 2404 m_freem(m); 2405 goto dropit; 2406 } 2407 } 2408 m->m_data += 2; 2409 2410 /* 2411 * Note that we use clusters for incoming frames, so the 2412 * buffer is virtually contiguous. 2413 */ 2414 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2415 2416 /* Allow the receive descriptor to continue using its mbuf. */ 2417 SIP_INIT_RXDESC(sc, i); 2418 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2419 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2420 #endif /* __NO_STRICT_ALIGNMENT */ 2421 2422 ifp->if_ipackets++; 2423 m->m_pkthdr.rcvif = ifp; 2424 m->m_pkthdr.len = m->m_len = len; 2425 2426 #if NBPFILTER > 0 2427 /* 2428 * Pass this up to any BPF listeners, but only 2429 * pass if up the stack if it's for us. 2430 */ 2431 if (ifp->if_bpf) 2432 bpf_mtap(ifp->if_bpf, m); 2433 #endif /* NBPFILTER > 0 */ 2434 2435 /* Pass it on. */ 2436 (*ifp->if_input)(ifp, m); 2437 } 2438 2439 /* Update the receive pointer. */ 2440 sc->sc_rxptr = i; 2441 } 2442 2443 /* 2444 * sip_tick: 2445 * 2446 * One second timer, used to tick the MII. 2447 */ 2448 static void 2449 sipcom_tick(void *arg) 2450 { 2451 struct sip_softc *sc = arg; 2452 int s; 2453 2454 s = splnet(); 2455 #ifdef SIP_EVENT_COUNTERS 2456 if (sc->sc_gigabit) { 2457 /* Read PAUSE related counts from MIB registers. */ 2458 sc->sc_ev_rxpause.ev_count += 2459 bus_space_read_4(sc->sc_st, sc->sc_sh, 2460 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2461 sc->sc_ev_txpause.ev_count += 2462 bus_space_read_4(sc->sc_st, sc->sc_sh, 2463 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2464 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2465 } 2466 #endif /* SIP_EVENT_COUNTERS */ 2467 mii_tick(&sc->sc_mii); 2468 splx(s); 2469 2470 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2471 } 2472 2473 /* 2474 * sip_reset: 2475 * 2476 * Perform a soft reset on the SiS 900. 2477 */ 2478 static bool 2479 sipcom_reset(struct sip_softc *sc) 2480 { 2481 bus_space_tag_t st = sc->sc_st; 2482 bus_space_handle_t sh = sc->sc_sh; 2483 int i; 2484 2485 bus_space_write_4(st, sh, SIP_IER, 0); 2486 bus_space_write_4(st, sh, SIP_IMR, 0); 2487 bus_space_write_4(st, sh, SIP_RFCR, 0); 2488 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2489 2490 for (i = 0; i < SIP_TIMEOUT; i++) { 2491 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2492 break; 2493 delay(2); 2494 } 2495 2496 if (i == SIP_TIMEOUT) { 2497 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2498 return false; 2499 } 2500 2501 delay(1000); 2502 2503 if (sc->sc_gigabit) { 2504 /* 2505 * Set the general purpose I/O bits. Do it here in case we 2506 * need to have GPIO set up to talk to the media interface. 2507 */ 2508 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2509 delay(1000); 2510 } 2511 return true; 2512 } 2513 2514 static void 2515 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2516 { 2517 u_int32_t reg; 2518 bus_space_tag_t st = sc->sc_st; 2519 bus_space_handle_t sh = sc->sc_sh; 2520 /* 2521 * Initialize the VLAN/IP receive control register. 2522 * We enable checksum computation on all incoming 2523 * packets, and do not reject packets w/ bad checksums. 2524 */ 2525 reg = 0; 2526 if (capenable & 2527 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2528 reg |= VRCR_IPEN; 2529 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2530 reg |= VRCR_VTDEN|VRCR_VTREN; 2531 bus_space_write_4(st, sh, SIP_VRCR, reg); 2532 2533 /* 2534 * Initialize the VLAN/IP transmit control register. 2535 * We enable outgoing checksum computation on a 2536 * per-packet basis. 2537 */ 2538 reg = 0; 2539 if (capenable & 2540 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2541 reg |= VTCR_PPCHK; 2542 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2543 reg |= VTCR_VPPTI; 2544 bus_space_write_4(st, sh, SIP_VTCR, reg); 2545 2546 /* 2547 * If we're using VLANs, initialize the VLAN data register. 2548 * To understand why we bswap the VLAN Ethertype, see section 2549 * 4.2.36 of the DP83820 manual. 2550 */ 2551 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2552 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2553 } 2554 2555 /* 2556 * sip_init: [ ifnet interface function ] 2557 * 2558 * Initialize the interface. Must be called at splnet(). 2559 */ 2560 static int 2561 sipcom_init(struct ifnet *ifp) 2562 { 2563 struct sip_softc *sc = ifp->if_softc; 2564 bus_space_tag_t st = sc->sc_st; 2565 bus_space_handle_t sh = sc->sc_sh; 2566 struct sip_txsoft *txs; 2567 struct sip_rxsoft *rxs; 2568 struct sip_desc *sipd; 2569 int i, error = 0; 2570 2571 if (!device_has_power(&sc->sc_dev)) 2572 return EBUSY; 2573 2574 /* 2575 * Cancel any pending I/O. 2576 */ 2577 sipcom_stop(ifp, 0); 2578 2579 /* 2580 * Reset the chip to a known state. 2581 */ 2582 if (!sipcom_reset(sc)) 2583 return EBUSY; 2584 2585 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2586 /* 2587 * DP83815 manual, page 78: 2588 * 4.4 Recommended Registers Configuration 2589 * For optimum performance of the DP83815, version noted 2590 * as DP83815CVNG (SRR = 203h), the listed register 2591 * modifications must be followed in sequence... 2592 * 2593 * It's not clear if this should be 302h or 203h because that 2594 * chip name is listed as SRR 302h in the description of the 2595 * SRR register. However, my revision 302h DP83815 on the 2596 * Netgear FA311 purchased in 02/2001 needs these settings 2597 * to avoid tons of errors in AcceptPerfectMatch (non- 2598 * IFF_PROMISC) mode. I do not know if other revisions need 2599 * this set or not. [briggs -- 09 March 2001] 2600 * 2601 * Note that only the low-order 12 bits of 0xe4 are documented 2602 * and that this sets reserved bits in that register. 2603 */ 2604 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2605 2606 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2607 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2608 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2609 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2610 2611 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2612 } 2613 2614 /* 2615 * Initialize the transmit descriptor ring. 2616 */ 2617 for (i = 0; i < sc->sc_ntxdesc; i++) { 2618 sipd = &sc->sc_txdescs[i]; 2619 memset(sipd, 0, sizeof(struct sip_desc)); 2620 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2621 } 2622 SIP_CDTXSYNC(sc, 0, sc->sc_ntxdesc, 2623 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2624 sc->sc_txfree = sc->sc_ntxdesc; 2625 sc->sc_txnext = 0; 2626 sc->sc_txwin = 0; 2627 2628 /* 2629 * Initialize the transmit job descriptors. 2630 */ 2631 SIMPLEQ_INIT(&sc->sc_txfreeq); 2632 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2633 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2634 txs = &sc->sc_txsoft[i]; 2635 txs->txs_mbuf = NULL; 2636 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2637 } 2638 2639 /* 2640 * Initialize the receive descriptor and receive job 2641 * descriptor rings. 2642 */ 2643 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2644 rxs = &sc->sc_rxsoft[i]; 2645 if (rxs->rxs_mbuf == NULL) { 2646 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2647 printf("%s: unable to allocate or map rx " 2648 "buffer %d, error = %d\n", 2649 sc->sc_dev.dv_xname, i, error); 2650 /* 2651 * XXX Should attempt to run with fewer receive 2652 * XXX buffers instead of just failing. 2653 */ 2654 sipcom_rxdrain(sc); 2655 goto out; 2656 } 2657 } else 2658 SIP_INIT_RXDESC(sc, i); 2659 } 2660 sc->sc_rxptr = 0; 2661 sc->sc_rxdiscard = 0; 2662 SIP_RXCHAIN_RESET(sc); 2663 2664 /* 2665 * Set the configuration register; it's already initialized 2666 * in sip_attach(). 2667 */ 2668 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2669 2670 /* 2671 * Initialize the prototype TXCFG register. 2672 */ 2673 if (sc->sc_gigabit) { 2674 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2675 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2676 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2677 SIP_SIS900_REV(sc, SIS_REV_960) || 2678 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2679 (sc->sc_cfg & CFG_EDBMASTEN)) { 2680 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2681 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2682 } else { 2683 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2684 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2685 } 2686 2687 sc->sc_txcfg |= TXCFG_ATP | 2688 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2689 sc->sc_tx_drain_thresh; 2690 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2691 2692 /* 2693 * Initialize the receive drain threshold if we have never 2694 * done so. 2695 */ 2696 if (sc->sc_rx_drain_thresh == 0) { 2697 /* 2698 * XXX This value should be tuned. This is set to the 2699 * maximum of 248 bytes, and we may be able to improve 2700 * performance by decreasing it (although we should never 2701 * set this value lower than 2; 14 bytes are required to 2702 * filter the packet). 2703 */ 2704 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2705 } 2706 2707 /* 2708 * Initialize the prototype RXCFG register. 2709 */ 2710 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2711 /* 2712 * Accept long packets (including FCS) so we can handle 2713 * 802.1q-tagged frames and jumbo frames properly. 2714 */ 2715 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2716 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2717 sc->sc_rxcfg |= RXCFG_ALP; 2718 2719 /* 2720 * Checksum offloading is disabled if the user selects an MTU 2721 * larger than 8109. (FreeBSD says 8152, but there is emperical 2722 * evidence that >8109 does not work on some boards, such as the 2723 * Planex GN-1000TE). 2724 */ 2725 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2726 (ifp->if_capenable & 2727 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2728 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2729 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2730 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2731 "disabled.\n", sc->sc_dev.dv_xname); 2732 ifp->if_capenable &= 2733 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2734 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2735 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2736 ifp->if_csum_flags_tx = 0; 2737 ifp->if_csum_flags_rx = 0; 2738 } 2739 2740 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2741 2742 if (sc->sc_gigabit) 2743 sipcom_dp83820_init(sc, ifp->if_capenable); 2744 2745 /* 2746 * Give the transmit and receive rings to the chip. 2747 */ 2748 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2749 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2750 2751 /* 2752 * Initialize the interrupt mask. 2753 */ 2754 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2755 sc->sc_bits.b_isr_sserr | 2756 sc->sc_bits.b_isr_rmabt | 2757 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2758 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2759 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2760 2761 /* Set up the receive filter. */ 2762 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2763 2764 /* 2765 * Tune sc_rx_flow_thresh. 2766 * XXX "More than 8KB" is too short for jumbo frames. 2767 * XXX TODO: Threshold value should be user-settable. 2768 */ 2769 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2770 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2771 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2772 2773 /* 2774 * Set the current media. Do this after initializing the prototype 2775 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2776 * control. 2777 */ 2778 mii_mediachg(&sc->sc_mii); 2779 2780 /* 2781 * Set the interrupt hold-off timer to 100us. 2782 */ 2783 if (sc->sc_gigabit) 2784 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2785 2786 /* 2787 * Enable interrupts. 2788 */ 2789 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2790 2791 /* 2792 * Start the transmit and receive processes. 2793 */ 2794 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2795 2796 /* 2797 * Start the one second MII clock. 2798 */ 2799 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2800 2801 /* 2802 * ...all done! 2803 */ 2804 ifp->if_flags |= IFF_RUNNING; 2805 ifp->if_flags &= ~IFF_OACTIVE; 2806 sc->sc_if_flags = ifp->if_flags; 2807 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2808 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2809 sc->sc_prev.if_capenable = ifp->if_capenable; 2810 2811 out: 2812 if (error) 2813 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2814 return (error); 2815 } 2816 2817 /* 2818 * sip_drain: 2819 * 2820 * Drain the receive queue. 2821 */ 2822 static void 2823 sipcom_rxdrain(struct sip_softc *sc) 2824 { 2825 struct sip_rxsoft *rxs; 2826 int i; 2827 2828 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2829 rxs = &sc->sc_rxsoft[i]; 2830 if (rxs->rxs_mbuf != NULL) { 2831 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2832 m_freem(rxs->rxs_mbuf); 2833 rxs->rxs_mbuf = NULL; 2834 } 2835 } 2836 } 2837 2838 /* 2839 * sip_stop: [ ifnet interface function ] 2840 * 2841 * Stop transmission on the interface. 2842 */ 2843 static void 2844 sipcom_stop(struct ifnet *ifp, int disable) 2845 { 2846 struct sip_softc *sc = ifp->if_softc; 2847 bus_space_tag_t st = sc->sc_st; 2848 bus_space_handle_t sh = sc->sc_sh; 2849 struct sip_txsoft *txs; 2850 u_int32_t cmdsts = 0; /* DEBUG */ 2851 2852 /* 2853 * Stop the one second clock. 2854 */ 2855 callout_stop(&sc->sc_tick_ch); 2856 2857 /* Down the MII. */ 2858 mii_down(&sc->sc_mii); 2859 2860 /* 2861 * Disable interrupts. 2862 */ 2863 bus_space_write_4(st, sh, SIP_IER, 0); 2864 2865 /* 2866 * Stop receiver and transmitter. 2867 */ 2868 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2869 2870 /* 2871 * Release any queued transmit buffers. 2872 */ 2873 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2874 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2875 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2876 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2877 CMDSTS_INTR) == 0) 2878 printf("%s: sip_stop: last descriptor does not " 2879 "have INTR bit set\n", sc->sc_dev.dv_xname); 2880 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2881 #ifdef DIAGNOSTIC 2882 if (txs->txs_mbuf == NULL) { 2883 printf("%s: dirty txsoft with no mbuf chain\n", 2884 sc->sc_dev.dv_xname); 2885 panic("sip_stop"); 2886 } 2887 #endif 2888 cmdsts |= /* DEBUG */ 2889 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2890 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2891 m_freem(txs->txs_mbuf); 2892 txs->txs_mbuf = NULL; 2893 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2894 } 2895 2896 if (disable) 2897 sipcom_rxdrain(sc); 2898 2899 /* 2900 * Mark the interface down and cancel the watchdog timer. 2901 */ 2902 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2903 ifp->if_timer = 0; 2904 2905 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2906 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2907 printf("%s: sip_stop: no INTR bits set in dirty tx " 2908 "descriptors\n", sc->sc_dev.dv_xname); 2909 } 2910 2911 /* 2912 * sip_read_eeprom: 2913 * 2914 * Read data from the serial EEPROM. 2915 */ 2916 static void 2917 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2918 u_int16_t *data) 2919 { 2920 bus_space_tag_t st = sc->sc_st; 2921 bus_space_handle_t sh = sc->sc_sh; 2922 u_int16_t reg; 2923 int i, x; 2924 2925 for (i = 0; i < wordcnt; i++) { 2926 /* Send CHIP SELECT. */ 2927 reg = EROMAR_EECS; 2928 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2929 2930 /* Shift in the READ opcode. */ 2931 for (x = 3; x > 0; x--) { 2932 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2933 reg |= EROMAR_EEDI; 2934 else 2935 reg &= ~EROMAR_EEDI; 2936 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2937 bus_space_write_4(st, sh, SIP_EROMAR, 2938 reg | EROMAR_EESK); 2939 delay(4); 2940 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2941 delay(4); 2942 } 2943 2944 /* Shift in address. */ 2945 for (x = 6; x > 0; x--) { 2946 if ((word + i) & (1 << (x - 1))) 2947 reg |= EROMAR_EEDI; 2948 else 2949 reg &= ~EROMAR_EEDI; 2950 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2951 bus_space_write_4(st, sh, SIP_EROMAR, 2952 reg | EROMAR_EESK); 2953 delay(4); 2954 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2955 delay(4); 2956 } 2957 2958 /* Shift out data. */ 2959 reg = EROMAR_EECS; 2960 data[i] = 0; 2961 for (x = 16; x > 0; x--) { 2962 bus_space_write_4(st, sh, SIP_EROMAR, 2963 reg | EROMAR_EESK); 2964 delay(4); 2965 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2966 data[i] |= (1 << (x - 1)); 2967 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2968 delay(4); 2969 } 2970 2971 /* Clear CHIP SELECT. */ 2972 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2973 delay(4); 2974 } 2975 } 2976 2977 /* 2978 * sipcom_add_rxbuf: 2979 * 2980 * Add a receive buffer to the indicated descriptor. 2981 */ 2982 static int 2983 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2984 { 2985 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2986 struct mbuf *m; 2987 int error; 2988 2989 MGETHDR(m, M_DONTWAIT, MT_DATA); 2990 if (m == NULL) 2991 return (ENOBUFS); 2992 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2993 2994 MCLGET(m, M_DONTWAIT); 2995 if ((m->m_flags & M_EXT) == 0) { 2996 m_freem(m); 2997 return (ENOBUFS); 2998 } 2999 3000 /* XXX I don't believe this is necessary. --dyoung */ 3001 if (sc->sc_gigabit) 3002 m->m_len = sc->sc_parm->p_rxbuf_len; 3003 3004 if (rxs->rxs_mbuf != NULL) 3005 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3006 3007 rxs->rxs_mbuf = m; 3008 3009 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3010 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3011 BUS_DMA_READ|BUS_DMA_NOWAIT); 3012 if (error) { 3013 printf("%s: can't load rx DMA map %d, error = %d\n", 3014 sc->sc_dev.dv_xname, idx, error); 3015 panic("%s", __func__); /* XXX */ 3016 } 3017 3018 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3019 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3020 3021 SIP_INIT_RXDESC(sc, idx); 3022 3023 return (0); 3024 } 3025 3026 /* 3027 * sip_sis900_set_filter: 3028 * 3029 * Set up the receive filter. 3030 */ 3031 static void 3032 sipcom_sis900_set_filter(struct sip_softc *sc) 3033 { 3034 bus_space_tag_t st = sc->sc_st; 3035 bus_space_handle_t sh = sc->sc_sh; 3036 struct ethercom *ec = &sc->sc_ethercom; 3037 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3038 struct ether_multi *enm; 3039 const u_int8_t *cp; 3040 struct ether_multistep step; 3041 u_int32_t crc, mchash[16]; 3042 3043 /* 3044 * Initialize the prototype RFCR. 3045 */ 3046 sc->sc_rfcr = RFCR_RFEN; 3047 if (ifp->if_flags & IFF_BROADCAST) 3048 sc->sc_rfcr |= RFCR_AAB; 3049 if (ifp->if_flags & IFF_PROMISC) { 3050 sc->sc_rfcr |= RFCR_AAP; 3051 goto allmulti; 3052 } 3053 3054 /* 3055 * Set up the multicast address filter by passing all multicast 3056 * addresses through a CRC generator, and then using the high-order 3057 * 6 bits as an index into the 128 bit multicast hash table (only 3058 * the lower 16 bits of each 32 bit multicast hash register are 3059 * valid). The high order bits select the register, while the 3060 * rest of the bits select the bit within the register. 3061 */ 3062 3063 memset(mchash, 0, sizeof(mchash)); 3064 3065 /* 3066 * SiS900 (at least SiS963) requires us to register the address of 3067 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3068 */ 3069 crc = 0x0ed423f9; 3070 3071 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3072 SIP_SIS900_REV(sc, SIS_REV_960) || 3073 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3074 /* Just want the 8 most significant bits. */ 3075 crc >>= 24; 3076 } else { 3077 /* Just want the 7 most significant bits. */ 3078 crc >>= 25; 3079 } 3080 3081 /* Set the corresponding bit in the hash table. */ 3082 mchash[crc >> 4] |= 1 << (crc & 0xf); 3083 3084 ETHER_FIRST_MULTI(step, ec, enm); 3085 while (enm != NULL) { 3086 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3087 /* 3088 * We must listen to a range of multicast addresses. 3089 * For now, just accept all multicasts, rather than 3090 * trying to set only those filter bits needed to match 3091 * the range. (At this time, the only use of address 3092 * ranges is for IP multicast routing, for which the 3093 * range is big enough to require all bits set.) 3094 */ 3095 goto allmulti; 3096 } 3097 3098 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3099 3100 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3101 SIP_SIS900_REV(sc, SIS_REV_960) || 3102 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3103 /* Just want the 8 most significant bits. */ 3104 crc >>= 24; 3105 } else { 3106 /* Just want the 7 most significant bits. */ 3107 crc >>= 25; 3108 } 3109 3110 /* Set the corresponding bit in the hash table. */ 3111 mchash[crc >> 4] |= 1 << (crc & 0xf); 3112 3113 ETHER_NEXT_MULTI(step, enm); 3114 } 3115 3116 ifp->if_flags &= ~IFF_ALLMULTI; 3117 goto setit; 3118 3119 allmulti: 3120 ifp->if_flags |= IFF_ALLMULTI; 3121 sc->sc_rfcr |= RFCR_AAM; 3122 3123 setit: 3124 #define FILTER_EMIT(addr, data) \ 3125 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3126 delay(1); \ 3127 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3128 delay(1) 3129 3130 /* 3131 * Disable receive filter, and program the node address. 3132 */ 3133 cp = CLLADDR(ifp->if_sadl); 3134 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3135 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3136 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3137 3138 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3139 /* 3140 * Program the multicast hash table. 3141 */ 3142 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3143 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3144 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3145 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3146 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3147 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3148 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3149 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3150 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3151 SIP_SIS900_REV(sc, SIS_REV_960) || 3152 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3153 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3154 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3155 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3156 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3157 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3158 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3159 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3160 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3161 } 3162 } 3163 #undef FILTER_EMIT 3164 3165 /* 3166 * Re-enable the receiver filter. 3167 */ 3168 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3169 } 3170 3171 /* 3172 * sip_dp83815_set_filter: 3173 * 3174 * Set up the receive filter. 3175 */ 3176 static void 3177 sipcom_dp83815_set_filter(struct sip_softc *sc) 3178 { 3179 bus_space_tag_t st = sc->sc_st; 3180 bus_space_handle_t sh = sc->sc_sh; 3181 struct ethercom *ec = &sc->sc_ethercom; 3182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3183 struct ether_multi *enm; 3184 const u_int8_t *cp; 3185 struct ether_multistep step; 3186 u_int32_t crc, hash, slot, bit; 3187 #define MCHASH_NWORDS_83820 128 3188 #define MCHASH_NWORDS_83815 32 3189 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3190 u_int16_t mchash[MCHASH_NWORDS]; 3191 int i; 3192 3193 /* 3194 * Initialize the prototype RFCR. 3195 * Enable the receive filter, and accept on 3196 * Perfect (destination address) Match 3197 * If IFF_BROADCAST, also accept all broadcast packets. 3198 * If IFF_PROMISC, accept all unicast packets (and later, set 3199 * IFF_ALLMULTI and accept all multicast, too). 3200 */ 3201 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3202 if (ifp->if_flags & IFF_BROADCAST) 3203 sc->sc_rfcr |= RFCR_AAB; 3204 if (ifp->if_flags & IFF_PROMISC) { 3205 sc->sc_rfcr |= RFCR_AAP; 3206 goto allmulti; 3207 } 3208 3209 /* 3210 * Set up the DP83820/DP83815 multicast address filter by 3211 * passing all multicast addresses through a CRC generator, 3212 * and then using the high-order 11/9 bits as an index into 3213 * the 2048/512 bit multicast hash table. The high-order 3214 * 7/5 bits select the slot, while the low-order 4 bits 3215 * select the bit within the slot. Note that only the low 3216 * 16-bits of each filter word are used, and there are 3217 * 128/32 filter words. 3218 */ 3219 3220 memset(mchash, 0, sizeof(mchash)); 3221 3222 ifp->if_flags &= ~IFF_ALLMULTI; 3223 ETHER_FIRST_MULTI(step, ec, enm); 3224 if (enm == NULL) 3225 goto setit; 3226 while (enm != NULL) { 3227 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3228 /* 3229 * We must listen to a range of multicast addresses. 3230 * For now, just accept all multicasts, rather than 3231 * trying to set only those filter bits needed to match 3232 * the range. (At this time, the only use of address 3233 * ranges is for IP multicast routing, for which the 3234 * range is big enough to require all bits set.) 3235 */ 3236 goto allmulti; 3237 } 3238 3239 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3240 3241 if (sc->sc_gigabit) { 3242 /* Just want the 11 most significant bits. */ 3243 hash = crc >> 21; 3244 } else { 3245 /* Just want the 9 most significant bits. */ 3246 hash = crc >> 23; 3247 } 3248 3249 slot = hash >> 4; 3250 bit = hash & 0xf; 3251 3252 /* Set the corresponding bit in the hash table. */ 3253 mchash[slot] |= 1 << bit; 3254 3255 ETHER_NEXT_MULTI(step, enm); 3256 } 3257 sc->sc_rfcr |= RFCR_MHEN; 3258 goto setit; 3259 3260 allmulti: 3261 ifp->if_flags |= IFF_ALLMULTI; 3262 sc->sc_rfcr |= RFCR_AAM; 3263 3264 setit: 3265 #define FILTER_EMIT(addr, data) \ 3266 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3267 delay(1); \ 3268 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3269 delay(1) 3270 3271 /* 3272 * Disable receive filter, and program the node address. 3273 */ 3274 cp = CLLADDR(ifp->if_sadl); 3275 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3276 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3277 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3278 3279 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3280 int nwords = 3281 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3282 /* 3283 * Program the multicast hash table. 3284 */ 3285 for (i = 0; i < nwords; i++) { 3286 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3287 } 3288 } 3289 #undef FILTER_EMIT 3290 #undef MCHASH_NWORDS 3291 #undef MCHASH_NWORDS_83815 3292 #undef MCHASH_NWORDS_83820 3293 3294 /* 3295 * Re-enable the receiver filter. 3296 */ 3297 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3298 } 3299 3300 /* 3301 * sip_dp83820_mii_readreg: [mii interface function] 3302 * 3303 * Read a PHY register on the MII of the DP83820. 3304 */ 3305 static int 3306 sipcom_dp83820_mii_readreg(struct device *self, int phy, int reg) 3307 { 3308 struct sip_softc *sc = (void *) self; 3309 3310 if (sc->sc_cfg & CFG_TBI_EN) { 3311 bus_addr_t tbireg; 3312 int rv; 3313 3314 if (phy != 0) 3315 return (0); 3316 3317 switch (reg) { 3318 case MII_BMCR: tbireg = SIP_TBICR; break; 3319 case MII_BMSR: tbireg = SIP_TBISR; break; 3320 case MII_ANAR: tbireg = SIP_TANAR; break; 3321 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3322 case MII_ANER: tbireg = SIP_TANER; break; 3323 case MII_EXTSR: 3324 /* 3325 * Don't even bother reading the TESR register. 3326 * The manual documents that the device has 3327 * 1000baseX full/half capability, but the 3328 * register itself seems read back 0 on some 3329 * boards. Just hard-code the result. 3330 */ 3331 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3332 3333 default: 3334 return (0); 3335 } 3336 3337 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3338 if (tbireg == SIP_TBISR) { 3339 /* LINK and ACOMP are switched! */ 3340 int val = rv; 3341 3342 rv = 0; 3343 if (val & TBISR_MR_LINK_STATUS) 3344 rv |= BMSR_LINK; 3345 if (val & TBISR_MR_AN_COMPLETE) 3346 rv |= BMSR_ACOMP; 3347 3348 /* 3349 * The manual claims this register reads back 0 3350 * on hard and soft reset. But we want to let 3351 * the gentbi driver know that we support auto- 3352 * negotiation, so hard-code this bit in the 3353 * result. 3354 */ 3355 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3356 } 3357 3358 return (rv); 3359 } 3360 3361 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3362 } 3363 3364 /* 3365 * sip_dp83820_mii_writereg: [mii interface function] 3366 * 3367 * Write a PHY register on the MII of the DP83820. 3368 */ 3369 static void 3370 sipcom_dp83820_mii_writereg(struct device *self, int phy, int reg, int val) 3371 { 3372 struct sip_softc *sc = (void *) self; 3373 3374 if (sc->sc_cfg & CFG_TBI_EN) { 3375 bus_addr_t tbireg; 3376 3377 if (phy != 0) 3378 return; 3379 3380 switch (reg) { 3381 case MII_BMCR: tbireg = SIP_TBICR; break; 3382 case MII_ANAR: tbireg = SIP_TANAR; break; 3383 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3384 default: 3385 return; 3386 } 3387 3388 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3389 return; 3390 } 3391 3392 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3393 } 3394 3395 /* 3396 * sip_dp83820_mii_statchg: [mii interface function] 3397 * 3398 * Callback from MII layer when media changes. 3399 */ 3400 static void 3401 sipcom_dp83820_mii_statchg(struct device *self) 3402 { 3403 struct sip_softc *sc = (struct sip_softc *) self; 3404 struct mii_data *mii = &sc->sc_mii; 3405 u_int32_t cfg, pcr; 3406 3407 /* 3408 * Get flow control negotiation result. 3409 */ 3410 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3411 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3412 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3413 mii->mii_media_active &= ~IFM_ETH_FMASK; 3414 } 3415 3416 /* 3417 * Update TXCFG for full-duplex operation. 3418 */ 3419 if ((mii->mii_media_active & IFM_FDX) != 0) 3420 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3421 else 3422 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3423 3424 /* 3425 * Update RXCFG for full-duplex or loopback. 3426 */ 3427 if ((mii->mii_media_active & IFM_FDX) != 0 || 3428 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3429 sc->sc_rxcfg |= RXCFG_ATX; 3430 else 3431 sc->sc_rxcfg &= ~RXCFG_ATX; 3432 3433 /* 3434 * Update CFG for MII/GMII. 3435 */ 3436 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3437 cfg = sc->sc_cfg | CFG_MODE_1000; 3438 else 3439 cfg = sc->sc_cfg; 3440 3441 /* 3442 * 802.3x flow control. 3443 */ 3444 pcr = 0; 3445 if (sc->sc_flowflags & IFM_FLOW) { 3446 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3447 pcr |= sc->sc_rx_flow_thresh; 3448 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3449 pcr |= PCR_PSEN | PCR_PS_MCAST; 3450 } 3451 3452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3453 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3454 sc->sc_txcfg); 3455 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3456 sc->sc_rxcfg); 3457 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3458 } 3459 3460 /* 3461 * sip_mii_bitbang_read: [mii bit-bang interface function] 3462 * 3463 * Read the MII serial port for the MII bit-bang module. 3464 */ 3465 static u_int32_t 3466 sipcom_mii_bitbang_read(struct device *self) 3467 { 3468 struct sip_softc *sc = (void *) self; 3469 3470 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3471 } 3472 3473 /* 3474 * sip_mii_bitbang_write: [mii big-bang interface function] 3475 * 3476 * Write the MII serial port for the MII bit-bang module. 3477 */ 3478 static void 3479 sipcom_mii_bitbang_write(struct device *self, u_int32_t val) 3480 { 3481 struct sip_softc *sc = (void *) self; 3482 3483 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3484 } 3485 3486 /* 3487 * sip_sis900_mii_readreg: [mii interface function] 3488 * 3489 * Read a PHY register on the MII. 3490 */ 3491 static int 3492 sipcom_sis900_mii_readreg(struct device *self, int phy, int reg) 3493 { 3494 struct sip_softc *sc = (struct sip_softc *) self; 3495 u_int32_t enphy; 3496 3497 /* 3498 * The PHY of recent SiS chipsets is accessed through bitbang 3499 * operations. 3500 */ 3501 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3502 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3503 phy, reg); 3504 3505 #ifndef SIS900_MII_RESTRICT 3506 /* 3507 * The SiS 900 has only an internal PHY on the MII. Only allow 3508 * MII address 0. 3509 */ 3510 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3511 return (0); 3512 #endif 3513 3514 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3515 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3516 ENPHY_RWCMD | ENPHY_ACCESS); 3517 do { 3518 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3519 } while (enphy & ENPHY_ACCESS); 3520 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3521 } 3522 3523 /* 3524 * sip_sis900_mii_writereg: [mii interface function] 3525 * 3526 * Write a PHY register on the MII. 3527 */ 3528 static void 3529 sipcom_sis900_mii_writereg(struct device *self, int phy, int reg, int val) 3530 { 3531 struct sip_softc *sc = (struct sip_softc *) self; 3532 u_int32_t enphy; 3533 3534 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3535 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3536 phy, reg, val); 3537 return; 3538 } 3539 3540 #ifndef SIS900_MII_RESTRICT 3541 /* 3542 * The SiS 900 has only an internal PHY on the MII. Only allow 3543 * MII address 0. 3544 */ 3545 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3546 return; 3547 #endif 3548 3549 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3550 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3551 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3552 do { 3553 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3554 } while (enphy & ENPHY_ACCESS); 3555 } 3556 3557 /* 3558 * sip_sis900_mii_statchg: [mii interface function] 3559 * 3560 * Callback from MII layer when media changes. 3561 */ 3562 static void 3563 sipcom_sis900_mii_statchg(struct device *self) 3564 { 3565 struct sip_softc *sc = (struct sip_softc *) self; 3566 struct mii_data *mii = &sc->sc_mii; 3567 u_int32_t flowctl; 3568 3569 /* 3570 * Get flow control negotiation result. 3571 */ 3572 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3573 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3574 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3575 mii->mii_media_active &= ~IFM_ETH_FMASK; 3576 } 3577 3578 /* 3579 * Update TXCFG for full-duplex operation. 3580 */ 3581 if ((mii->mii_media_active & IFM_FDX) != 0) 3582 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3583 else 3584 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3585 3586 /* 3587 * Update RXCFG for full-duplex or loopback. 3588 */ 3589 if ((mii->mii_media_active & IFM_FDX) != 0 || 3590 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3591 sc->sc_rxcfg |= RXCFG_ATX; 3592 else 3593 sc->sc_rxcfg &= ~RXCFG_ATX; 3594 3595 /* 3596 * Update IMR for use of 802.3x flow control. 3597 */ 3598 if (sc->sc_flowflags & IFM_FLOW) { 3599 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3600 flowctl = FLOWCTL_FLOWEN; 3601 } else { 3602 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3603 flowctl = 0; 3604 } 3605 3606 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3607 sc->sc_txcfg); 3608 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3609 sc->sc_rxcfg); 3610 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3611 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3612 } 3613 3614 /* 3615 * sip_dp83815_mii_readreg: [mii interface function] 3616 * 3617 * Read a PHY register on the MII. 3618 */ 3619 static int 3620 sipcom_dp83815_mii_readreg(struct device *self, int phy, int reg) 3621 { 3622 struct sip_softc *sc = (struct sip_softc *) self; 3623 u_int32_t val; 3624 3625 /* 3626 * The DP83815 only has an internal PHY. Only allow 3627 * MII address 0. 3628 */ 3629 if (phy != 0) 3630 return (0); 3631 3632 /* 3633 * Apparently, after a reset, the DP83815 can take a while 3634 * to respond. During this recovery period, the BMSR returns 3635 * a value of 0. Catch this -- it's not supposed to happen 3636 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3637 * PHY to come back to life. 3638 * 3639 * This works out because the BMSR is the first register 3640 * read during the PHY probe process. 3641 */ 3642 do { 3643 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3644 } while (reg == MII_BMSR && val == 0); 3645 3646 return (val & 0xffff); 3647 } 3648 3649 /* 3650 * sip_dp83815_mii_writereg: [mii interface function] 3651 * 3652 * Write a PHY register to the MII. 3653 */ 3654 static void 3655 sipcom_dp83815_mii_writereg(struct device *self, int phy, int reg, int val) 3656 { 3657 struct sip_softc *sc = (struct sip_softc *) self; 3658 3659 /* 3660 * The DP83815 only has an internal PHY. Only allow 3661 * MII address 0. 3662 */ 3663 if (phy != 0) 3664 return; 3665 3666 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3667 } 3668 3669 /* 3670 * sip_dp83815_mii_statchg: [mii interface function] 3671 * 3672 * Callback from MII layer when media changes. 3673 */ 3674 static void 3675 sipcom_dp83815_mii_statchg(struct device *self) 3676 { 3677 struct sip_softc *sc = (struct sip_softc *) self; 3678 3679 /* 3680 * Update TXCFG for full-duplex operation. 3681 */ 3682 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3683 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3684 else 3685 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3686 3687 /* 3688 * Update RXCFG for full-duplex or loopback. 3689 */ 3690 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3691 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3692 sc->sc_rxcfg |= RXCFG_ATX; 3693 else 3694 sc->sc_rxcfg &= ~RXCFG_ATX; 3695 3696 /* 3697 * XXX 802.3x flow control. 3698 */ 3699 3700 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3701 sc->sc_txcfg); 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3703 sc->sc_rxcfg); 3704 3705 /* 3706 * Some DP83815s experience problems when used with short 3707 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3708 * sequence adjusts the DSP's signal attenuation to fix the 3709 * problem. 3710 */ 3711 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3712 uint32_t reg; 3713 3714 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3715 3716 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3717 reg &= 0x0fff; 3718 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3719 delay(100); 3720 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3721 reg &= 0x00ff; 3722 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3723 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3724 0x00e8); 3725 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3726 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3727 reg | 0x20); 3728 } 3729 3730 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3731 } 3732 } 3733 3734 static void 3735 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3736 const struct pci_attach_args *pa, u_int8_t *enaddr) 3737 { 3738 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3739 u_int8_t cksum, *e, match; 3740 int i; 3741 3742 /* 3743 * EEPROM data format for the DP83820 can be found in 3744 * the DP83820 manual, section 4.2.4. 3745 */ 3746 3747 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3748 3749 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3750 match = ~(match - 1); 3751 3752 cksum = 0x55; 3753 e = (u_int8_t *) eeprom_data; 3754 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3755 cksum += *e++; 3756 3757 if (cksum != match) 3758 printf("%s: Checksum (%x) mismatch (%x)", 3759 sc->sc_dev.dv_xname, cksum, match); 3760 3761 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3762 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3763 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3764 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3765 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3766 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3767 } 3768 3769 static void 3770 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3771 { 3772 int i; 3773 3774 /* 3775 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3776 * a reason, but I don't know it. 3777 */ 3778 for (i = 0; i < 10; i++) 3779 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3780 } 3781 3782 static void 3783 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3784 const struct pci_attach_args *pa, u_int8_t *enaddr) 3785 { 3786 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3787 3788 switch (sc->sc_rev) { 3789 case SIS_REV_630S: 3790 case SIS_REV_630E: 3791 case SIS_REV_630EA1: 3792 case SIS_REV_630ET: 3793 case SIS_REV_635: 3794 /* 3795 * The MAC address for the on-board Ethernet of 3796 * the SiS 630 chipset is in the NVRAM. Kick 3797 * the chip into re-loading it from NVRAM, and 3798 * read the MAC address out of the filter registers. 3799 */ 3800 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3801 3802 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3803 RFCR_RFADDR_NODE0); 3804 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3805 0xffff; 3806 3807 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3808 RFCR_RFADDR_NODE2); 3809 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3810 0xffff; 3811 3812 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3813 RFCR_RFADDR_NODE4); 3814 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3815 0xffff; 3816 break; 3817 3818 case SIS_REV_960: 3819 { 3820 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3821 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3822 3823 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3824 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3825 3826 int waittime, i; 3827 3828 /* Allow to read EEPROM from LAN. It is shared 3829 * between a 1394 controller and the NIC and each 3830 * time we access it, we need to set SIS_EECMD_REQ. 3831 */ 3832 SIS_SET_EROMAR(sc, EROMAR_REQ); 3833 3834 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3835 /* Force EEPROM to idle state. */ 3836 3837 /* 3838 * XXX-cube This is ugly. I'll look for docs about it. 3839 */ 3840 SIS_SET_EROMAR(sc, EROMAR_EECS); 3841 sipcom_sis900_eeprom_delay(sc); 3842 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3843 SIS_SET_EROMAR(sc, EROMAR_EESK); 3844 sipcom_sis900_eeprom_delay(sc); 3845 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3846 sipcom_sis900_eeprom_delay(sc); 3847 } 3848 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3849 sipcom_sis900_eeprom_delay(sc); 3850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3851 3852 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3853 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3854 sizeof(myea) / sizeof(myea[0]), myea); 3855 break; 3856 } 3857 DELAY(1); 3858 } 3859 3860 /* 3861 * Set SIS_EECTL_CLK to high, so a other master 3862 * can operate on the i2c bus. 3863 */ 3864 SIS_SET_EROMAR(sc, EROMAR_EESK); 3865 3866 /* Refuse EEPROM access by LAN */ 3867 SIS_SET_EROMAR(sc, EROMAR_DONE); 3868 } break; 3869 3870 default: 3871 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3872 sizeof(myea) / sizeof(myea[0]), myea); 3873 } 3874 3875 enaddr[0] = myea[0] & 0xff; 3876 enaddr[1] = myea[0] >> 8; 3877 enaddr[2] = myea[1] & 0xff; 3878 enaddr[3] = myea[1] >> 8; 3879 enaddr[4] = myea[2] & 0xff; 3880 enaddr[5] = myea[2] >> 8; 3881 } 3882 3883 /* Table and macro to bit-reverse an octet. */ 3884 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3885 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3886 3887 static void 3888 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3889 const struct pci_attach_args *pa, u_int8_t *enaddr) 3890 { 3891 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3892 u_int8_t cksum, *e, match; 3893 int i; 3894 3895 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3896 sizeof(eeprom_data[0]), eeprom_data); 3897 3898 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3899 match = ~(match - 1); 3900 3901 cksum = 0x55; 3902 e = (u_int8_t *) eeprom_data; 3903 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3904 cksum += *e++; 3905 } 3906 if (cksum != match) { 3907 printf("%s: Checksum (%x) mismatch (%x)", 3908 sc->sc_dev.dv_xname, cksum, match); 3909 } 3910 3911 /* 3912 * Unrolled because it makes slightly more sense this way. 3913 * The DP83815 stores the MAC address in bit 0 of word 6 3914 * through bit 15 of word 8. 3915 */ 3916 ea = &eeprom_data[6]; 3917 enaddr[0] = ((*ea & 0x1) << 7); 3918 ea++; 3919 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3920 enaddr[1] = ((*ea & 0x1FE) >> 1); 3921 enaddr[2] = ((*ea & 0x1) << 7); 3922 ea++; 3923 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3924 enaddr[3] = ((*ea & 0x1FE) >> 1); 3925 enaddr[4] = ((*ea & 0x1) << 7); 3926 ea++; 3927 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3928 enaddr[5] = ((*ea & 0x1FE) >> 1); 3929 3930 /* 3931 * In case that's not weird enough, we also need to reverse 3932 * the bits in each byte. This all actually makes more sense 3933 * if you think about the EEPROM storage as an array of bits 3934 * being shifted into bytes, but that's not how we're looking 3935 * at it here... 3936 */ 3937 for (i = 0; i < 6 ;i++) 3938 enaddr[i] = bbr(enaddr[i]); 3939 } 3940 3941 /* 3942 * sip_mediastatus: [ifmedia interface function] 3943 * 3944 * Get the current interface media status. 3945 */ 3946 static void 3947 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3948 { 3949 struct sip_softc *sc = ifp->if_softc; 3950 3951 mii_pollstat(&sc->sc_mii); 3952 ifmr->ifm_status = sc->sc_mii.mii_media_status; 3953 ifmr->ifm_active = (sc->sc_mii.mii_media_active & ~IFM_ETH_FMASK) | 3954 sc->sc_flowflags; 3955 } 3956 3957 /* 3958 * sip_mediachange: [ifmedia interface function] 3959 * 3960 * Set hardware to newly-selected media. 3961 */ 3962 static int 3963 sipcom_mediachange(struct ifnet *ifp) 3964 { 3965 struct sip_softc *sc = ifp->if_softc; 3966 3967 if (ifp->if_flags & IFF_UP) 3968 mii_mediachg(&sc->sc_mii); 3969 return (0); 3970 } 3971
Indexes created Mon Sep 22 10:09:38 GMT 2025