if_sip.c revision 1.131
1 /* $NetBSD: if_sip.c,v 1.131 2008/03/21 07:47:43 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.131 2008/03/21 07:47:43 dyoung Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 /* 130 * Transmit descriptor list size. This is arbitrary, but allocate 131 * enough descriptors for 128 pending transmissions, and 8 segments 132 * per packet (64 for DP83820 for jumbo frames). 133 * 134 * This MUST work out to a power of 2. 135 */ 136 #define GSIP_NTXSEGS_ALLOC 16 137 #define SIP_NTXSEGS_ALLOC 8 138 139 #define SIP_TXQUEUELEN 256 140 #define MAX_SIP_NTXDESC \ 141 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer per incoming 145 * packet, so this logic is a little simpler. 146 * 147 * Actually, on the DP83820, we allow the packet to consume more than 148 * one buffer, in order to support jumbo Ethernet frames. In that 149 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 150 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 151 * so we'd better be quick about handling receive interrupts. 152 */ 153 #define GSIP_NRXDESC 256 154 #define SIP_NRXDESC 128 155 156 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 157 158 /* 159 * Control structures are DMA'd to the SiS900 chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct sip_control_data { 164 /* 165 * The transmit descriptors. 166 */ 167 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 168 169 /* 170 * The receive descriptors. 171 */ 172 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 173 }; 174 175 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 176 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 177 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 178 179 /* 180 * Software state for transmit jobs. 181 */ 182 struct sip_txsoft { 183 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t txs_dmamap; /* our DMA map */ 185 int txs_firstdesc; /* first descriptor in packet */ 186 int txs_lastdesc; /* last descriptor in packet */ 187 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 188 }; 189 190 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 191 192 /* 193 * Software state for receive jobs. 194 */ 195 struct sip_rxsoft { 196 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t rxs_dmamap; /* our DMA map */ 198 }; 199 200 enum sip_attach_stage { 201 SIP_ATTACH_FIN = 0 202 , SIP_ATTACH_CREATE_RXMAP 203 , SIP_ATTACH_CREATE_TXMAP 204 , SIP_ATTACH_LOAD_MAP 205 , SIP_ATTACH_CREATE_MAP 206 , SIP_ATTACH_MAP_MEM 207 , SIP_ATTACH_ALLOC_MEM 208 , SIP_ATTACH_INTR 209 , SIP_ATTACH_MAP 210 }; 211 212 /* 213 * Software state per device. 214 */ 215 struct sip_softc { 216 struct device sc_dev; /* generic device information */ 217 bus_space_tag_t sc_st; /* bus space tag */ 218 bus_space_handle_t sc_sh; /* bus space handle */ 219 bus_size_t sc_sz; /* bus space size */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t sc_pc; 222 bus_dma_segment_t sc_seg; 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 225 const struct sip_product *sc_model; /* which model are we? */ 226 int sc_gigabit; /* 1: 83820, 0: other */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 callout_t sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 262 struct evcnt sc_ev_rxpause; /* PAUSE received */ 263 /* DP83820 only */ 264 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 265 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 266 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 267 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 268 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 269 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 270 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 271 #endif /* SIP_EVENT_COUNTERS */ 272 273 u_int32_t sc_txcfg; /* prototype TXCFG register */ 274 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 275 u_int32_t sc_imr; /* prototype IMR register */ 276 u_int32_t sc_rfcr; /* prototype RFCR register */ 277 278 u_int32_t sc_cfg; /* prototype CFG register */ 279 280 u_int32_t sc_gpior; /* prototype GPIOR register */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flowflags; /* 802.3x flow control flags */ 288 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 289 int sc_paused; /* paused indication */ 290 291 int sc_txfree; /* number of free Tx descriptors */ 292 int sc_txnext; /* next ready Tx descriptor */ 293 int sc_txwin; /* Tx descriptors since last intr */ 294 295 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 296 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 297 298 /* values of interface state at last init */ 299 struct { 300 /* if_capenable */ 301 uint64_t if_capenable; 302 /* ec_capenable */ 303 int ec_capenable; 304 /* VLAN_ATTACHED */ 305 int is_vlan; 306 } sc_prev; 307 308 short sc_if_flags; 309 310 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 311 int sc_rxdiscard; 312 int sc_rxlen; 313 struct mbuf *sc_rxhead; 314 struct mbuf *sc_rxtail; 315 struct mbuf **sc_rxtailp; 316 317 int sc_ntxdesc; 318 int sc_ntxdesc_mask; 319 320 int sc_nrxdesc_mask; 321 322 const struct sip_parm { 323 const struct sip_regs { 324 int r_rxcfg; 325 int r_txcfg; 326 } p_regs; 327 328 const struct sip_bits { 329 uint32_t b_txcfg_mxdma_8; 330 uint32_t b_txcfg_mxdma_16; 331 uint32_t b_txcfg_mxdma_32; 332 uint32_t b_txcfg_mxdma_64; 333 uint32_t b_txcfg_mxdma_128; 334 uint32_t b_txcfg_mxdma_256; 335 uint32_t b_txcfg_mxdma_512; 336 uint32_t b_txcfg_flth_mask; 337 uint32_t b_txcfg_drth_mask; 338 339 uint32_t b_rxcfg_mxdma_8; 340 uint32_t b_rxcfg_mxdma_16; 341 uint32_t b_rxcfg_mxdma_32; 342 uint32_t b_rxcfg_mxdma_64; 343 uint32_t b_rxcfg_mxdma_128; 344 uint32_t b_rxcfg_mxdma_256; 345 uint32_t b_rxcfg_mxdma_512; 346 347 uint32_t b_isr_txrcmp; 348 uint32_t b_isr_rxrcmp; 349 uint32_t b_isr_dperr; 350 uint32_t b_isr_sserr; 351 uint32_t b_isr_rmabt; 352 uint32_t b_isr_rtabt; 353 354 uint32_t b_cmdsts_size_mask; 355 } p_bits; 356 int p_filtmem; 357 int p_rxbuf_len; 358 bus_size_t p_tx_dmamap_size; 359 int p_ntxsegs; 360 int p_ntxsegs_alloc; 361 int p_nrxdesc; 362 } *sc_parm; 363 364 void (*sc_rxintr)(struct sip_softc *); 365 366 #if NRND > 0 367 rndsource_element_t rnd_source; /* random source */ 368 #endif 369 }; 370 371 #define sc_bits sc_parm->p_bits 372 #define sc_regs sc_parm->p_regs 373 374 static const struct sip_parm sip_parm = { 375 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 376 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 377 , .p_tx_dmamap_size = MCLBYTES 378 , .p_ntxsegs = 16 379 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 380 , .p_nrxdesc = SIP_NRXDESC 381 , .p_bits = { 382 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 383 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 384 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 385 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 386 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 387 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 388 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 389 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 390 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 391 392 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 393 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 394 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 395 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 396 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 397 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 398 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 399 400 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 401 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 402 , .b_isr_dperr = 0x00800000 /* detected parity error */ 403 , .b_isr_sserr = 0x00400000 /* signalled system error */ 404 , .b_isr_rmabt = 0x00200000 /* received master abort */ 405 , .b_isr_rtabt = 0x00100000 /* received target abort */ 406 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 407 } 408 , .p_regs = { 409 .r_rxcfg = OTHER_SIP_RXCFG, 410 .r_txcfg = OTHER_SIP_TXCFG 411 } 412 }, gsip_parm = { 413 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 414 , .p_rxbuf_len = MCLBYTES - 8 415 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 416 , .p_ntxsegs = 64 417 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 418 , .p_nrxdesc = GSIP_NRXDESC 419 , .p_bits = { 420 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 421 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 422 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 423 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 424 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 425 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 426 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 427 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 428 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 429 430 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 431 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 432 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 433 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 434 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 435 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 436 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 437 438 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 439 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 440 , .b_isr_dperr = 0x00100000 /* detected parity error */ 441 , .b_isr_sserr = 0x00080000 /* signalled system error */ 442 , .b_isr_rmabt = 0x00040000 /* received master abort */ 443 , .b_isr_rtabt = 0x00020000 /* received target abort */ 444 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 445 } 446 , .p_regs = { 447 .r_rxcfg = DP83820_SIP_RXCFG, 448 .r_txcfg = DP83820_SIP_TXCFG 449 } 450 }; 451 452 static inline int 453 sip_nexttx(const struct sip_softc *sc, int x) 454 { 455 return (x + 1) & sc->sc_ntxdesc_mask; 456 } 457 458 static inline int 459 sip_nextrx(const struct sip_softc *sc, int x) 460 { 461 return (x + 1) & sc->sc_nrxdesc_mask; 462 } 463 464 /* 83820 only */ 465 static inline void 466 sip_rxchain_reset(struct sip_softc *sc) 467 { 468 sc->sc_rxtailp = &sc->sc_rxhead; 469 *sc->sc_rxtailp = NULL; 470 sc->sc_rxlen = 0; 471 } 472 473 /* 83820 only */ 474 static inline void 475 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 476 { 477 *sc->sc_rxtailp = sc->sc_rxtail = m; 478 sc->sc_rxtailp = &m->m_next; 479 } 480 481 #ifdef SIP_EVENT_COUNTERS 482 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 483 #else 484 #define SIP_EVCNT_INCR(ev) /* nothing */ 485 #endif 486 487 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 488 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 489 490 static inline void 491 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 492 { 493 int x, n; 494 495 x = x0; 496 n = n0; 497 498 /* If it will wrap around, sync to the end of the ring. */ 499 if (x + n > sc->sc_ntxdesc) { 500 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 501 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 502 (sc->sc_ntxdesc - x), ops); 503 n -= (sc->sc_ntxdesc - x); 504 x = 0; 505 } 506 507 /* Now sync whatever is left. */ 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 510 } 511 512 static inline void 513 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 514 { 515 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 516 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 517 } 518 519 #if 0 520 #ifdef DP83820 521 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 522 u_int32_t sipd_cmdsts; /* command/status word */ 523 #else 524 u_int32_t sipd_cmdsts; /* command/status word */ 525 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 526 #endif /* DP83820 */ 527 #endif /* 0 */ 528 529 static inline volatile uint32_t * 530 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 531 { 532 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 533 } 534 535 static inline volatile uint32_t * 536 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 537 { 538 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 539 } 540 541 static inline void 542 sip_init_rxdesc(struct sip_softc *sc, int x) 543 { 544 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 545 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 546 547 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 548 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 549 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 550 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 551 sipd->sipd_extsts = 0; 552 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 553 } 554 555 #define SIP_CHIP_VERS(sc, v, p, r) \ 556 ((sc)->sc_model->sip_vendor == (v) && \ 557 (sc)->sc_model->sip_product == (p) && \ 558 (sc)->sc_rev == (r)) 559 560 #define SIP_CHIP_MODEL(sc, v, p) \ 561 ((sc)->sc_model->sip_vendor == (v) && \ 562 (sc)->sc_model->sip_product == (p)) 563 564 #define SIP_SIS900_REV(sc, rev) \ 565 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 566 567 #define SIP_TIMEOUT 1000 568 569 static void sipcom_start(struct ifnet *); 570 static void sipcom_watchdog(struct ifnet *); 571 static int sipcom_ioctl(struct ifnet *, u_long, void *); 572 static int sipcom_init(struct ifnet *); 573 static void sipcom_stop(struct ifnet *, int); 574 575 static bool sipcom_reset(struct sip_softc *); 576 static void sipcom_rxdrain(struct sip_softc *); 577 static int sipcom_add_rxbuf(struct sip_softc *, int); 578 static void sipcom_read_eeprom(struct sip_softc *, int, int, 579 u_int16_t *); 580 static void sipcom_tick(void *); 581 582 static void sipcom_sis900_set_filter(struct sip_softc *); 583 static void sipcom_dp83815_set_filter(struct sip_softc *); 584 585 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 586 const struct pci_attach_args *, u_int8_t *); 587 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 588 static void sipcom_sis900_read_macaddr(struct sip_softc *, 589 const struct pci_attach_args *, u_int8_t *); 590 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 591 const struct pci_attach_args *, u_int8_t *); 592 593 static int sipcom_intr(void *); 594 static void sipcom_txintr(struct sip_softc *); 595 static void sip_rxintr(struct sip_softc *); 596 static void gsip_rxintr(struct sip_softc *); 597 598 static int sipcom_dp83820_mii_readreg(device_t, int, int); 599 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 600 static void sipcom_dp83820_mii_statchg(device_t); 601 602 static int sipcom_sis900_mii_readreg(device_t, int, int); 603 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 604 static void sipcom_sis900_mii_statchg(device_t); 605 606 static int sipcom_dp83815_mii_readreg(device_t, int, int); 607 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 608 static void sipcom_dp83815_mii_statchg(device_t); 609 610 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 611 612 static int sipcom_match(device_t, struct cfdata *, void *); 613 static void sipcom_attach(device_t, device_t, void *); 614 static void sipcom_do_detach(device_t, enum sip_attach_stage); 615 static int sipcom_detach(device_t, int); 616 static bool sipcom_resume(device_t PMF_FN_PROTO); 617 static bool sipcom_suspend(device_t PMF_FN_PROTO); 618 619 int gsip_copy_small = 0; 620 int sip_copy_small = 0; 621 622 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 623 sipcom_match, sipcom_attach, sipcom_detach, NULL); 624 CFATTACH_DECL(sip, sizeof(struct sip_softc), 625 sipcom_match, sipcom_attach, sipcom_detach, NULL); 626 627 /* 628 * Descriptions of the variants of the SiS900. 629 */ 630 struct sip_variant { 631 int (*sipv_mii_readreg)(device_t, int, int); 632 void (*sipv_mii_writereg)(device_t, int, int, int); 633 void (*sipv_mii_statchg)(device_t); 634 void (*sipv_set_filter)(struct sip_softc *); 635 void (*sipv_read_macaddr)(struct sip_softc *, 636 const struct pci_attach_args *, u_int8_t *); 637 }; 638 639 static u_int32_t sipcom_mii_bitbang_read(device_t); 640 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 641 642 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 643 sipcom_mii_bitbang_read, 644 sipcom_mii_bitbang_write, 645 { 646 EROMAR_MDIO, /* MII_BIT_MDO */ 647 EROMAR_MDIO, /* MII_BIT_MDI */ 648 EROMAR_MDC, /* MII_BIT_MDC */ 649 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 650 0, /* MII_BIT_DIR_PHY_HOST */ 651 } 652 }; 653 654 static const struct sip_variant sipcom_variant_dp83820 = { 655 sipcom_dp83820_mii_readreg, 656 sipcom_dp83820_mii_writereg, 657 sipcom_dp83820_mii_statchg, 658 sipcom_dp83815_set_filter, 659 sipcom_dp83820_read_macaddr, 660 }; 661 662 static const struct sip_variant sipcom_variant_sis900 = { 663 sipcom_sis900_mii_readreg, 664 sipcom_sis900_mii_writereg, 665 sipcom_sis900_mii_statchg, 666 sipcom_sis900_set_filter, 667 sipcom_sis900_read_macaddr, 668 }; 669 670 static const struct sip_variant sipcom_variant_dp83815 = { 671 sipcom_dp83815_mii_readreg, 672 sipcom_dp83815_mii_writereg, 673 sipcom_dp83815_mii_statchg, 674 sipcom_dp83815_set_filter, 675 sipcom_dp83815_read_macaddr, 676 }; 677 678 679 /* 680 * Devices supported by this driver. 681 */ 682 static const struct sip_product { 683 pci_vendor_id_t sip_vendor; 684 pci_product_id_t sip_product; 685 const char *sip_name; 686 const struct sip_variant *sip_variant; 687 int sip_gigabit; 688 } sipcom_products[] = { 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 690 "NatSemi DP83820 Gigabit Ethernet", 691 &sipcom_variant_dp83820, 1 }, 692 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 693 "SiS 900 10/100 Ethernet", 694 &sipcom_variant_sis900, 0 }, 695 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 696 "SiS 7016 10/100 Ethernet", 697 &sipcom_variant_sis900, 0 }, 698 699 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 700 "NatSemi DP83815 10/100 Ethernet", 701 &sipcom_variant_dp83815, 0 }, 702 703 { 0, 0, 704 NULL, 705 NULL, 0 }, 706 }; 707 708 static const struct sip_product * 709 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 710 { 711 const struct sip_product *sip; 712 713 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 714 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 715 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 716 sip->sip_gigabit == gigabit) 717 return sip; 718 } 719 return NULL; 720 } 721 722 /* 723 * I really hate stupid hardware vendors. There's a bit in the EEPROM 724 * which indicates if the card can do 64-bit data transfers. Unfortunately, 725 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 726 * which means we try to use 64-bit data transfers on those cards if we 727 * happen to be plugged into a 32-bit slot. 728 * 729 * What we do is use this table of cards known to be 64-bit cards. If 730 * you have a 64-bit card who's subsystem ID is not listed in this table, 731 * send the output of "pcictl dump ..." of the device to me so that your 732 * card will use the 64-bit data path when plugged into a 64-bit slot. 733 * 734 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 735 * June 30, 2002 736 */ 737 static int 738 sipcom_check_64bit(const struct pci_attach_args *pa) 739 { 740 static const struct { 741 pci_vendor_id_t c64_vendor; 742 pci_product_id_t c64_product; 743 } card64[] = { 744 /* Asante GigaNIX */ 745 { 0x128a, 0x0002 }, 746 747 /* Accton EN1407-T, Planex GN-1000TE */ 748 { 0x1113, 0x1407 }, 749 750 /* Netgear GA-621 */ 751 { 0x1385, 0x621a }, 752 753 /* SMC EZ Card */ 754 { 0x10b8, 0x9462 }, 755 756 { 0, 0} 757 }; 758 pcireg_t subsys; 759 int i; 760 761 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 762 763 for (i = 0; card64[i].c64_vendor != 0; i++) { 764 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 765 PCI_PRODUCT(subsys) == card64[i].c64_product) 766 return (1); 767 } 768 769 return (0); 770 } 771 772 static int 773 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 774 { 775 struct pci_attach_args *pa = aux; 776 777 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 778 return 1; 779 780 return 0; 781 } 782 783 static void 784 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 785 { 786 u_int32_t reg; 787 int i; 788 789 /* 790 * Cause the chip to load configuration data from the EEPROM. 791 */ 792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 793 for (i = 0; i < 10000; i++) { 794 delay(10); 795 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 796 PTSCR_EELOAD_EN) == 0) 797 break; 798 } 799 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 800 PTSCR_EELOAD_EN) { 801 printf("%s: timeout loading configuration from EEPROM\n", 802 sc->sc_dev.dv_xname); 803 return; 804 } 805 806 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 807 808 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 809 if (reg & CFG_PCI64_DET) { 810 printf("%s: 64-bit PCI slot detected", sc->sc_dev.dv_xname); 811 /* 812 * Check to see if this card is 64-bit. If so, enable 64-bit 813 * data transfers. 814 * 815 * We can't use the DATA64_EN bit in the EEPROM, because 816 * vendors of 32-bit cards fail to clear that bit in many 817 * cases (yet the card still detects that it's in a 64-bit 818 * slot; go figure). 819 */ 820 if (sipcom_check_64bit(pa)) { 821 sc->sc_cfg |= CFG_DATA64_EN; 822 printf(", using 64-bit data transfers"); 823 } 824 printf("\n"); 825 } 826 827 /* 828 * XXX Need some PCI flags indicating support for 829 * XXX 64-bit addressing. 830 */ 831 #if 0 832 if (reg & CFG_M64ADDR) 833 sc->sc_cfg |= CFG_M64ADDR; 834 if (reg & CFG_T64ADDR) 835 sc->sc_cfg |= CFG_T64ADDR; 836 #endif 837 838 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 839 const char *sep = ""; 840 printf("%s: using ", sc->sc_dev.dv_xname); 841 if (reg & CFG_EXT_125) { 842 sc->sc_cfg |= CFG_EXT_125; 843 printf("%s125MHz clock", sep); 844 sep = ", "; 845 } 846 if (reg & CFG_TBI_EN) { 847 sc->sc_cfg |= CFG_TBI_EN; 848 printf("%sten-bit interface", sep); 849 sep = ", "; 850 } 851 printf("\n"); 852 } 853 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 854 (reg & CFG_MRM_DIS) != 0) 855 sc->sc_cfg |= CFG_MRM_DIS; 856 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 857 (reg & CFG_MWI_DIS) != 0) 858 sc->sc_cfg |= CFG_MWI_DIS; 859 860 /* 861 * Use the extended descriptor format on the DP83820. This 862 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 863 * checksumming. 864 */ 865 sc->sc_cfg |= CFG_EXTSTS_EN; 866 } 867 868 static int 869 sipcom_detach(device_t self, int flags) 870 { 871 int s; 872 873 s = splnet(); 874 sipcom_do_detach(self, SIP_ATTACH_FIN); 875 splx(s); 876 877 return 0; 878 } 879 880 static void 881 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 882 { 883 int i; 884 struct sip_softc *sc = device_private(self); 885 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 886 887 /* 888 * Free any resources we've allocated during attach. 889 * Do this in reverse order and fall through. 890 */ 891 switch (stage) { 892 case SIP_ATTACH_FIN: 893 sipcom_stop(ifp, 1); 894 pmf_device_deregister(self); 895 #ifdef SIP_EVENT_COUNTERS 896 /* 897 * Attach event counters. 898 */ 899 evcnt_detach(&sc->sc_ev_txforceintr); 900 evcnt_detach(&sc->sc_ev_txdstall); 901 evcnt_detach(&sc->sc_ev_txsstall); 902 evcnt_detach(&sc->sc_ev_hiberr); 903 evcnt_detach(&sc->sc_ev_rxintr); 904 evcnt_detach(&sc->sc_ev_txiintr); 905 evcnt_detach(&sc->sc_ev_txdintr); 906 if (!sc->sc_gigabit) { 907 evcnt_detach(&sc->sc_ev_rxpause); 908 } else { 909 evcnt_detach(&sc->sc_ev_txudpsum); 910 evcnt_detach(&sc->sc_ev_txtcpsum); 911 evcnt_detach(&sc->sc_ev_txipsum); 912 evcnt_detach(&sc->sc_ev_rxudpsum); 913 evcnt_detach(&sc->sc_ev_rxtcpsum); 914 evcnt_detach(&sc->sc_ev_rxipsum); 915 evcnt_detach(&sc->sc_ev_txpause); 916 evcnt_detach(&sc->sc_ev_rxpause); 917 } 918 #endif /* SIP_EVENT_COUNTERS */ 919 920 #if NRND > 0 921 rnd_detach_source(&sc->rnd_source); 922 #endif 923 924 ether_ifdetach(ifp); 925 if_detach(ifp); 926 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 927 928 /*FALLTHROUGH*/ 929 case SIP_ATTACH_CREATE_RXMAP: 930 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 931 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 932 bus_dmamap_destroy(sc->sc_dmat, 933 sc->sc_rxsoft[i].rxs_dmamap); 934 } 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_CREATE_TXMAP: 937 for (i = 0; i < SIP_TXQUEUELEN; i++) { 938 if (sc->sc_txsoft[i].txs_dmamap != NULL) 939 bus_dmamap_destroy(sc->sc_dmat, 940 sc->sc_txsoft[i].txs_dmamap); 941 } 942 /*FALLTHROUGH*/ 943 case SIP_ATTACH_LOAD_MAP: 944 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 945 /*FALLTHROUGH*/ 946 case SIP_ATTACH_CREATE_MAP: 947 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_MAP_MEM: 950 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 951 sizeof(struct sip_control_data)); 952 /*FALLTHROUGH*/ 953 case SIP_ATTACH_ALLOC_MEM: 954 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 955 /* FALLTHROUGH*/ 956 case SIP_ATTACH_INTR: 957 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 958 /* FALLTHROUGH*/ 959 case SIP_ATTACH_MAP: 960 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 961 break; 962 default: 963 break; 964 } 965 return; 966 } 967 968 static bool 969 sipcom_resume(device_t self PMF_FN_ARGS) 970 { 971 struct sip_softc *sc = device_private(self); 972 973 return sipcom_reset(sc); 974 } 975 976 static bool 977 sipcom_suspend(device_t self PMF_FN_ARGS) 978 { 979 struct sip_softc *sc = device_private(self); 980 981 sipcom_rxdrain(sc); 982 return true; 983 } 984 985 static void 986 sipcom_attach(device_t parent, device_t self, void *aux) 987 { 988 struct sip_softc *sc = device_private(self); 989 struct pci_attach_args *pa = aux; 990 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 991 pci_chipset_tag_t pc = pa->pa_pc; 992 pci_intr_handle_t ih; 993 const char *intrstr = NULL; 994 bus_space_tag_t iot, memt; 995 bus_space_handle_t ioh, memh; 996 bus_size_t iosz, memsz; 997 int ioh_valid, memh_valid; 998 int i, rseg, error; 999 const struct sip_product *sip; 1000 u_int8_t enaddr[ETHER_ADDR_LEN]; 1001 pcireg_t pmreg; 1002 pcireg_t memtype; 1003 bus_size_t tx_dmamap_size; 1004 int ntxsegs_alloc; 1005 cfdata_t cf = device_cfdata(self); 1006 1007 callout_init(&sc->sc_tick_ch, 0); 1008 1009 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1010 if (sip == NULL) { 1011 printf("\n"); 1012 panic("%s: impossible", __func__); 1013 } 1014 sc->sc_gigabit = sip->sip_gigabit; 1015 1016 sc->sc_pc = pc; 1017 1018 if (sc->sc_gigabit) { 1019 sc->sc_rxintr = gsip_rxintr; 1020 sc->sc_parm = &gsip_parm; 1021 } else { 1022 sc->sc_rxintr = sip_rxintr; 1023 sc->sc_parm = &sip_parm; 1024 } 1025 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1026 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1027 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1028 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1029 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1030 1031 sc->sc_rev = PCI_REVISION(pa->pa_class); 1032 1033 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1034 1035 sc->sc_model = sip; 1036 1037 /* 1038 * XXX Work-around broken PXE firmware on some boards. 1039 * 1040 * The DP83815 shares an address decoder with the MEM BAR 1041 * and the ROM BAR. Make sure the ROM BAR is disabled, 1042 * so that memory mapped access works. 1043 */ 1044 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1045 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1046 ~PCI_MAPREG_ROM_ENABLE); 1047 1048 /* 1049 * Map the device. 1050 */ 1051 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1052 PCI_MAPREG_TYPE_IO, 0, 1053 &iot, &ioh, NULL, &iosz) == 0); 1054 if (sc->sc_gigabit) { 1055 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1056 switch (memtype) { 1057 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1058 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1061 break; 1062 default: 1063 memh_valid = 0; 1064 } 1065 } else { 1066 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1067 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1068 &memt, &memh, NULL, &memsz) == 0); 1069 } 1070 1071 if (memh_valid) { 1072 sc->sc_st = memt; 1073 sc->sc_sh = memh; 1074 sc->sc_sz = memsz; 1075 } else if (ioh_valid) { 1076 sc->sc_st = iot; 1077 sc->sc_sh = ioh; 1078 sc->sc_sz = iosz; 1079 } else { 1080 printf("%s: unable to map device registers\n", 1081 sc->sc_dev.dv_xname); 1082 return; 1083 } 1084 1085 sc->sc_dmat = pa->pa_dmat; 1086 1087 /* 1088 * Make sure bus mastering is enabled. Also make sure 1089 * Write/Invalidate is enabled if we're allowed to use it. 1090 */ 1091 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1092 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1093 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1094 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1095 pmreg | PCI_COMMAND_MASTER_ENABLE); 1096 1097 /* power up chip */ 1098 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 1099 error != EOPNOTSUPP) { 1100 aprint_error("%s: cannot activate %d\n", sc->sc_dev.dv_xname, 1101 error); 1102 return; 1103 } 1104 1105 /* 1106 * Map and establish our interrupt. 1107 */ 1108 if (pci_intr_map(pa, &ih)) { 1109 printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); 1110 return; 1111 } 1112 intrstr = pci_intr_string(pc, ih); 1113 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1114 if (sc->sc_ih == NULL) { 1115 printf("%s: unable to establish interrupt", 1116 sc->sc_dev.dv_xname); 1117 if (intrstr != NULL) 1118 printf(" at %s", intrstr); 1119 printf("\n"); 1120 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1121 } 1122 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1123 1124 SIMPLEQ_INIT(&sc->sc_txfreeq); 1125 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1126 1127 /* 1128 * Allocate the control data structures, and create and load the 1129 * DMA map for it. 1130 */ 1131 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1132 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1133 &rseg, 0)) != 0) { 1134 printf("%s: unable to allocate control data, error = %d\n", 1135 sc->sc_dev.dv_xname, error); 1136 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1137 } 1138 1139 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1140 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1141 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1142 printf("%s: unable to map control data, error = %d\n", 1143 sc->sc_dev.dv_xname, error); 1144 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1145 } 1146 1147 if ((error = bus_dmamap_create(sc->sc_dmat, 1148 sizeof(struct sip_control_data), 1, 1149 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1150 printf("%s: unable to create control data DMA map, " 1151 "error = %d\n", sc->sc_dev.dv_xname, error); 1152 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1153 } 1154 1155 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1156 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1157 0)) != 0) { 1158 printf("%s: unable to load control data DMA map, error = %d\n", 1159 sc->sc_dev.dv_xname, error); 1160 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1161 } 1162 1163 /* 1164 * Create the transmit buffer DMA maps. 1165 */ 1166 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1167 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1168 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1169 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1170 printf("%s: unable to create tx DMA map %d, " 1171 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1172 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1173 } 1174 } 1175 1176 /* 1177 * Create the receive buffer DMA maps. 1178 */ 1179 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1180 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1181 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1182 printf("%s: unable to create rx DMA map %d, " 1183 "error = %d\n", sc->sc_dev.dv_xname, i, error); 1184 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1185 } 1186 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1187 } 1188 1189 /* 1190 * Reset the chip to a known state. 1191 */ 1192 sipcom_reset(sc); 1193 1194 /* 1195 * Read the Ethernet address from the EEPROM. This might 1196 * also fetch other stuff from the EEPROM and stash it 1197 * in the softc. 1198 */ 1199 sc->sc_cfg = 0; 1200 if (!sc->sc_gigabit) { 1201 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1202 SIP_SIS900_REV(sc,SIS_REV_900B)) 1203 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1204 1205 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1206 SIP_SIS900_REV(sc,SIS_REV_960) || 1207 SIP_SIS900_REV(sc,SIS_REV_900B)) 1208 sc->sc_cfg |= 1209 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1210 CFG_EDBMASTEN); 1211 } 1212 1213 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1214 1215 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 1216 ether_sprintf(enaddr)); 1217 1218 /* 1219 * Initialize the configuration register: aggressive PCI 1220 * bus request algorithm, default backoff, default OW timer, 1221 * default parity error detection. 1222 * 1223 * NOTE: "Big endian mode" is useless on the SiS900 and 1224 * friends -- it affects packet data, not descriptors. 1225 */ 1226 if (sc->sc_gigabit) 1227 sipcom_dp83820_attach(sc, pa); 1228 1229 /* 1230 * Initialize our media structures and probe the MII. 1231 */ 1232 sc->sc_mii.mii_ifp = ifp; 1233 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1234 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1235 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1236 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1237 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1238 sipcom_mediastatus); 1239 1240 /* 1241 * XXX We cannot handle flow control on the DP83815. 1242 */ 1243 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1244 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1245 MII_OFFSET_ANY, 0); 1246 else 1247 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1248 MII_OFFSET_ANY, MIIF_DOPAUSE); 1249 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1250 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1251 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1252 } else 1253 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1254 1255 ifp = &sc->sc_ethercom.ec_if; 1256 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1257 ifp->if_softc = sc; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 sc->sc_if_flags = ifp->if_flags; 1260 ifp->if_ioctl = sipcom_ioctl; 1261 ifp->if_start = sipcom_start; 1262 ifp->if_watchdog = sipcom_watchdog; 1263 ifp->if_init = sipcom_init; 1264 ifp->if_stop = sipcom_stop; 1265 IFQ_SET_READY(&ifp->if_snd); 1266 1267 /* 1268 * We can support 802.1Q VLAN-sized frames. 1269 */ 1270 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1271 1272 if (sc->sc_gigabit) { 1273 /* 1274 * And the DP83820 can do VLAN tagging in hardware, and 1275 * support the jumbo Ethernet MTU. 1276 */ 1277 sc->sc_ethercom.ec_capabilities |= 1278 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1279 1280 /* 1281 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1282 * in hardware. 1283 */ 1284 ifp->if_capabilities |= 1285 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1286 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1287 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1288 } 1289 1290 /* 1291 * Attach the interface. 1292 */ 1293 if_attach(ifp); 1294 ether_ifattach(ifp, enaddr); 1295 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1296 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1297 sc->sc_prev.if_capenable = ifp->if_capenable; 1298 #if NRND > 0 1299 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 1300 RND_TYPE_NET, 0); 1301 #endif 1302 1303 /* 1304 * The number of bytes that must be available in 1305 * the Tx FIFO before the bus master can DMA more 1306 * data into the FIFO. 1307 */ 1308 sc->sc_tx_fill_thresh = 64 / 32; 1309 1310 /* 1311 * Start at a drain threshold of 512 bytes. We will 1312 * increase it if a DMA underrun occurs. 1313 * 1314 * XXX The minimum value of this variable should be 1315 * tuned. We may be able to improve performance 1316 * by starting with a lower value. That, however, 1317 * may trash the first few outgoing packets if the 1318 * PCI bus is saturated. 1319 */ 1320 if (sc->sc_gigabit) 1321 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1322 else 1323 sc->sc_tx_drain_thresh = 1504 / 32; 1324 1325 /* 1326 * Initialize the Rx FIFO drain threshold. 1327 * 1328 * This is in units of 8 bytes. 1329 * 1330 * We should never set this value lower than 2; 14 bytes are 1331 * required to filter the packet. 1332 */ 1333 sc->sc_rx_drain_thresh = 128 / 8; 1334 1335 #ifdef SIP_EVENT_COUNTERS 1336 /* 1337 * Attach event counters. 1338 */ 1339 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1340 NULL, sc->sc_dev.dv_xname, "txsstall"); 1341 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1342 NULL, sc->sc_dev.dv_xname, "txdstall"); 1343 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1344 NULL, sc->sc_dev.dv_xname, "txforceintr"); 1345 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1346 NULL, sc->sc_dev.dv_xname, "txdintr"); 1347 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1348 NULL, sc->sc_dev.dv_xname, "txiintr"); 1349 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1350 NULL, sc->sc_dev.dv_xname, "rxintr"); 1351 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1352 NULL, sc->sc_dev.dv_xname, "hiberr"); 1353 if (!sc->sc_gigabit) { 1354 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1355 NULL, sc->sc_dev.dv_xname, "rxpause"); 1356 } else { 1357 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1358 NULL, sc->sc_dev.dv_xname, "rxpause"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1360 NULL, sc->sc_dev.dv_xname, "txpause"); 1361 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1362 NULL, sc->sc_dev.dv_xname, "rxipsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1364 NULL, sc->sc_dev.dv_xname, "rxtcpsum"); 1365 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1366 NULL, sc->sc_dev.dv_xname, "rxudpsum"); 1367 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1368 NULL, sc->sc_dev.dv_xname, "txipsum"); 1369 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1370 NULL, sc->sc_dev.dv_xname, "txtcpsum"); 1371 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1372 NULL, sc->sc_dev.dv_xname, "txudpsum"); 1373 } 1374 #endif /* SIP_EVENT_COUNTERS */ 1375 1376 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1377 aprint_error_dev(self, "couldn't establish power handler\n"); 1378 else 1379 pmf_class_network_register(self, ifp); 1380 } 1381 1382 static inline void 1383 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1384 uint64_t capenable) 1385 { 1386 struct m_tag *mtag; 1387 u_int32_t extsts; 1388 #ifdef DEBUG 1389 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1390 #endif 1391 /* 1392 * If VLANs are enabled and the packet has a VLAN tag, set 1393 * up the descriptor to encapsulate the packet for us. 1394 * 1395 * This apparently has to be on the last descriptor of 1396 * the packet. 1397 */ 1398 1399 /* 1400 * Byte swapping is tricky. We need to provide the tag 1401 * in a network byte order. On a big-endian machine, 1402 * the byteorder is correct, but we need to swap it 1403 * anyway, because this will be undone by the outside 1404 * htole32(). That's why there must be an 1405 * unconditional swap instead of htons() inside. 1406 */ 1407 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1408 sc->sc_txdescs[lasttx].sipd_extsts |= 1409 htole32(EXTSTS_VPKT | 1410 (bswap16(VLAN_TAG_VALUE(mtag)) & 1411 EXTSTS_VTCI)); 1412 } 1413 1414 /* 1415 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1416 * checksumming, set up the descriptor to do this work 1417 * for us. 1418 * 1419 * This apparently has to be on the first descriptor of 1420 * the packet. 1421 * 1422 * Byte-swap constants so the compiler can optimize. 1423 */ 1424 extsts = 0; 1425 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1426 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1427 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1428 extsts |= htole32(EXTSTS_IPPKT); 1429 } 1430 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1431 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1432 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1433 extsts |= htole32(EXTSTS_TCPPKT); 1434 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1435 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1436 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1437 extsts |= htole32(EXTSTS_UDPPKT); 1438 } 1439 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1440 } 1441 1442 /* 1443 * sip_start: [ifnet interface function] 1444 * 1445 * Start packet transmission on the interface. 1446 */ 1447 static void 1448 sipcom_start(struct ifnet *ifp) 1449 { 1450 struct sip_softc *sc = ifp->if_softc; 1451 struct mbuf *m0; 1452 struct mbuf *m; 1453 struct sip_txsoft *txs; 1454 bus_dmamap_t dmamap; 1455 int error, nexttx, lasttx, seg; 1456 int ofree = sc->sc_txfree; 1457 #if 0 1458 int firsttx = sc->sc_txnext; 1459 #endif 1460 1461 /* 1462 * If we've been told to pause, don't transmit any more packets. 1463 */ 1464 if (!sc->sc_gigabit && sc->sc_paused) 1465 ifp->if_flags |= IFF_OACTIVE; 1466 1467 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1468 return; 1469 1470 /* 1471 * Loop through the send queue, setting up transmit descriptors 1472 * until we drain the queue, or use up all available transmit 1473 * descriptors. 1474 */ 1475 for (;;) { 1476 /* Get a work queue entry. */ 1477 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1478 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1479 break; 1480 } 1481 1482 /* 1483 * Grab a packet off the queue. 1484 */ 1485 IFQ_POLL(&ifp->if_snd, m0); 1486 if (m0 == NULL) 1487 break; 1488 m = NULL; 1489 1490 dmamap = txs->txs_dmamap; 1491 1492 /* 1493 * Load the DMA map. If this fails, the packet either 1494 * didn't fit in the alloted number of segments, or we 1495 * were short on resources. 1496 */ 1497 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1498 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1499 /* In the non-gigabit case, we'll copy and try again. */ 1500 if (error != 0 && !sc->sc_gigabit) { 1501 MGETHDR(m, M_DONTWAIT, MT_DATA); 1502 if (m == NULL) { 1503 printf("%s: unable to allocate Tx mbuf\n", 1504 sc->sc_dev.dv_xname); 1505 break; 1506 } 1507 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1508 if (m0->m_pkthdr.len > MHLEN) { 1509 MCLGET(m, M_DONTWAIT); 1510 if ((m->m_flags & M_EXT) == 0) { 1511 printf("%s: unable to allocate Tx " 1512 "cluster\n", sc->sc_dev.dv_xname); 1513 m_freem(m); 1514 break; 1515 } 1516 } 1517 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1518 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1519 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1520 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1521 if (error) { 1522 printf("%s: unable to load Tx buffer, " 1523 "error = %d\n", sc->sc_dev.dv_xname, error); 1524 break; 1525 } 1526 } else if (error == EFBIG) { 1527 /* 1528 * For the too-many-segments case, we simply 1529 * report an error and drop the packet, 1530 * since we can't sanely copy a jumbo packet 1531 * to a single buffer. 1532 */ 1533 printf("%s: Tx packet consumes too many " 1534 "DMA segments, dropping...\n", sc->sc_dev.dv_xname); 1535 IFQ_DEQUEUE(&ifp->if_snd, m0); 1536 m_freem(m0); 1537 continue; 1538 } else if (error != 0) { 1539 /* 1540 * Short on resources, just stop for now. 1541 */ 1542 break; 1543 } 1544 1545 /* 1546 * Ensure we have enough descriptors free to describe 1547 * the packet. Note, we always reserve one descriptor 1548 * at the end of the ring as a termination point, to 1549 * prevent wrap-around. 1550 */ 1551 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1552 /* 1553 * Not enough free descriptors to transmit this 1554 * packet. We haven't committed anything yet, 1555 * so just unload the DMA map, put the packet 1556 * back on the queue, and punt. Notify the upper 1557 * layer that there are not more slots left. 1558 * 1559 * XXX We could allocate an mbuf and copy, but 1560 * XXX is it worth it? 1561 */ 1562 ifp->if_flags |= IFF_OACTIVE; 1563 bus_dmamap_unload(sc->sc_dmat, dmamap); 1564 if (m != NULL) 1565 m_freem(m); 1566 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1567 break; 1568 } 1569 1570 IFQ_DEQUEUE(&ifp->if_snd, m0); 1571 if (m != NULL) { 1572 m_freem(m0); 1573 m0 = m; 1574 } 1575 1576 /* 1577 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1578 */ 1579 1580 /* Sync the DMA map. */ 1581 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1582 BUS_DMASYNC_PREWRITE); 1583 1584 /* 1585 * Initialize the transmit descriptors. 1586 */ 1587 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1588 seg < dmamap->dm_nsegs; 1589 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1590 /* 1591 * If this is the first descriptor we're 1592 * enqueueing, don't set the OWN bit just 1593 * yet. That could cause a race condition. 1594 * We'll do it below. 1595 */ 1596 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1597 htole32(dmamap->dm_segs[seg].ds_addr); 1598 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1599 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1600 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1601 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1602 lasttx = nexttx; 1603 } 1604 1605 /* Clear the MORE bit on the last segment. */ 1606 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1607 htole32(~CMDSTS_MORE); 1608 1609 /* 1610 * If we're in the interrupt delay window, delay the 1611 * interrupt. 1612 */ 1613 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1614 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1615 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1616 htole32(CMDSTS_INTR); 1617 sc->sc_txwin = 0; 1618 } 1619 1620 if (sc->sc_gigabit) 1621 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1622 1623 /* Sync the descriptors we're using. */ 1624 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1625 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1626 1627 /* 1628 * The entire packet is set up. Give the first descrptor 1629 * to the chip now. 1630 */ 1631 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1632 htole32(CMDSTS_OWN); 1633 sip_cdtxsync(sc, sc->sc_txnext, 1, 1634 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1635 1636 /* 1637 * Store a pointer to the packet so we can free it later, 1638 * and remember what txdirty will be once the packet is 1639 * done. 1640 */ 1641 txs->txs_mbuf = m0; 1642 txs->txs_firstdesc = sc->sc_txnext; 1643 txs->txs_lastdesc = lasttx; 1644 1645 /* Advance the tx pointer. */ 1646 sc->sc_txfree -= dmamap->dm_nsegs; 1647 sc->sc_txnext = nexttx; 1648 1649 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1650 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1651 1652 #if NBPFILTER > 0 1653 /* 1654 * Pass the packet to any BPF listeners. 1655 */ 1656 if (ifp->if_bpf) 1657 bpf_mtap(ifp->if_bpf, m0); 1658 #endif /* NBPFILTER > 0 */ 1659 } 1660 1661 if (txs == NULL || sc->sc_txfree == 0) { 1662 /* No more slots left; notify upper layer. */ 1663 ifp->if_flags |= IFF_OACTIVE; 1664 } 1665 1666 if (sc->sc_txfree != ofree) { 1667 /* 1668 * Start the transmit process. Note, the manual says 1669 * that if there are no pending transmissions in the 1670 * chip's internal queue (indicated by TXE being clear), 1671 * then the driver software must set the TXDP to the 1672 * first descriptor to be transmitted. However, if we 1673 * do this, it causes serious performance degredation on 1674 * the DP83820 under load, not setting TXDP doesn't seem 1675 * to adversely affect the SiS 900 or DP83815. 1676 * 1677 * Well, I guess it wouldn't be the first time a manual 1678 * has lied -- and they could be speaking of the NULL- 1679 * terminated descriptor list case, rather than OWN- 1680 * terminated rings. 1681 */ 1682 #if 0 1683 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1684 CR_TXE) == 0) { 1685 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1686 SIP_CDTXADDR(sc, firsttx)); 1687 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1688 } 1689 #else 1690 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1691 #endif 1692 1693 /* Set a watchdog timer in case the chip flakes out. */ 1694 /* Gigabit autonegotiation takes 5 seconds. */ 1695 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1696 } 1697 } 1698 1699 /* 1700 * sip_watchdog: [ifnet interface function] 1701 * 1702 * Watchdog timer handler. 1703 */ 1704 static void 1705 sipcom_watchdog(struct ifnet *ifp) 1706 { 1707 struct sip_softc *sc = ifp->if_softc; 1708 1709 /* 1710 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1711 * If we get a timeout, try and sweep up transmit descriptors. 1712 * If we manage to sweep them all up, ignore the lack of 1713 * interrupt. 1714 */ 1715 sipcom_txintr(sc); 1716 1717 if (sc->sc_txfree != sc->sc_ntxdesc) { 1718 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1719 ifp->if_oerrors++; 1720 1721 /* Reset the interface. */ 1722 (void) sipcom_init(ifp); 1723 } else if (ifp->if_flags & IFF_DEBUG) 1724 printf("%s: recovered from device timeout\n", 1725 sc->sc_dev.dv_xname); 1726 1727 /* Try to get more packets going. */ 1728 sipcom_start(ifp); 1729 } 1730 1731 /* 1732 * sip_ioctl: [ifnet interface function] 1733 * 1734 * Handle control requests from the operator. 1735 */ 1736 static int 1737 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1738 { 1739 struct sip_softc *sc = ifp->if_softc; 1740 struct ifreq *ifr = (struct ifreq *)data; 1741 int s, error; 1742 1743 s = splnet(); 1744 1745 switch (cmd) { 1746 case SIOCSIFMEDIA: 1747 /* Flow control requires full-duplex mode. */ 1748 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1749 (ifr->ifr_media & IFM_FDX) == 0) 1750 ifr->ifr_media &= ~IFM_ETH_FMASK; 1751 1752 /* XXX */ 1753 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1754 ifr->ifr_media &= ~IFM_ETH_FMASK; 1755 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1756 if (sc->sc_gigabit && 1757 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1758 /* We can do both TXPAUSE and RXPAUSE. */ 1759 ifr->ifr_media |= 1760 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1761 } else if (ifr->ifr_media & IFM_FLOW) { 1762 /* 1763 * Both TXPAUSE and RXPAUSE must be set. 1764 * (SiS900 and DP83815 don't have PAUSE_ASYM 1765 * feature.) 1766 * 1767 * XXX Can SiS900 and DP83815 send PAUSE? 1768 */ 1769 ifr->ifr_media |= 1770 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1771 } 1772 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1773 } 1774 goto ethioctl; 1775 case SIOCSIFFLAGS: 1776 /* If the interface is up and running, only modify the receive 1777 * filter when setting promiscuous or debug mode. Otherwise 1778 * fall through to ether_ioctl, which will reset the chip. 1779 */ 1780 1781 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1782 == (sc)->sc_ethercom.ec_capenable) \ 1783 && ((sc)->sc_prev.is_vlan == \ 1784 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1785 1786 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1787 1788 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1789 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1790 == (IFF_UP|IFF_RUNNING)) 1791 && ((ifp->if_flags & (~RESETIGN)) 1792 == (sc->sc_if_flags & (~RESETIGN))) 1793 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1794 /* Set up the receive filter. */ 1795 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1796 error = 0; 1797 break; 1798 #undef RESETIGN 1799 } 1800 /* FALLTHROUGH */ 1801 ethioctl: 1802 default: 1803 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1804 break; 1805 1806 error = 0; 1807 1808 if (cmd == SIOCSIFCAP) 1809 error = (*ifp->if_init)(ifp); 1810 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1811 ; 1812 else if (ifp->if_flags & IFF_RUNNING) { 1813 /* 1814 * Multicast list has changed; set the hardware filter 1815 * accordingly. 1816 */ 1817 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1818 } 1819 break; 1820 } 1821 1822 /* Try to get more packets going. */ 1823 sipcom_start(ifp); 1824 1825 sc->sc_if_flags = ifp->if_flags; 1826 splx(s); 1827 return (error); 1828 } 1829 1830 /* 1831 * sip_intr: 1832 * 1833 * Interrupt service routine. 1834 */ 1835 static int 1836 sipcom_intr(void *arg) 1837 { 1838 struct sip_softc *sc = arg; 1839 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1840 u_int32_t isr; 1841 int handled = 0; 1842 1843 /* Disable interrupts. */ 1844 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1845 1846 for (;;) { 1847 /* Reading clears interrupt. */ 1848 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1849 if ((isr & sc->sc_imr) == 0) 1850 break; 1851 1852 #if NRND > 0 1853 if (RND_ENABLED(&sc->rnd_source)) 1854 rnd_add_uint32(&sc->rnd_source, isr); 1855 #endif 1856 1857 handled = 1; 1858 1859 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1860 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1861 1862 /* Grab any new packets. */ 1863 (*sc->sc_rxintr)(sc); 1864 1865 if (isr & ISR_RXORN) { 1866 printf("%s: receive FIFO overrun\n", 1867 sc->sc_dev.dv_xname); 1868 1869 /* XXX adjust rx_drain_thresh? */ 1870 } 1871 1872 if (isr & ISR_RXIDLE) { 1873 printf("%s: receive ring overrun\n", 1874 sc->sc_dev.dv_xname); 1875 1876 /* Get the receive process going again. */ 1877 bus_space_write_4(sc->sc_st, sc->sc_sh, 1878 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1879 bus_space_write_4(sc->sc_st, sc->sc_sh, 1880 SIP_CR, CR_RXE); 1881 } 1882 } 1883 1884 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1885 #ifdef SIP_EVENT_COUNTERS 1886 if (isr & ISR_TXDESC) 1887 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1888 else if (isr & ISR_TXIDLE) 1889 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1890 #endif 1891 1892 /* Sweep up transmit descriptors. */ 1893 sipcom_txintr(sc); 1894 1895 if (isr & ISR_TXURN) { 1896 u_int32_t thresh; 1897 int txfifo_size = (sc->sc_gigabit) 1898 ? DP83820_SIP_TXFIFO_SIZE 1899 : OTHER_SIP_TXFIFO_SIZE; 1900 1901 printf("%s: transmit FIFO underrun", 1902 sc->sc_dev.dv_xname); 1903 thresh = sc->sc_tx_drain_thresh + 1; 1904 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1905 && (thresh * 32) <= (txfifo_size - 1906 (sc->sc_tx_fill_thresh * 32))) { 1907 printf("; increasing Tx drain " 1908 "threshold to %u bytes\n", 1909 thresh * 32); 1910 sc->sc_tx_drain_thresh = thresh; 1911 (void) sipcom_init(ifp); 1912 } else { 1913 (void) sipcom_init(ifp); 1914 printf("\n"); 1915 } 1916 } 1917 } 1918 1919 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1920 if (isr & ISR_PAUSE_ST) { 1921 sc->sc_paused = 1; 1922 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1923 ifp->if_flags |= IFF_OACTIVE; 1924 } 1925 if (isr & ISR_PAUSE_END) { 1926 sc->sc_paused = 0; 1927 ifp->if_flags &= ~IFF_OACTIVE; 1928 } 1929 } 1930 1931 if (isr & ISR_HIBERR) { 1932 int want_init = 0; 1933 1934 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1935 1936 #define PRINTERR(bit, str) \ 1937 do { \ 1938 if ((isr & (bit)) != 0) { \ 1939 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1940 printf("%s: %s\n", \ 1941 sc->sc_dev.dv_xname, str); \ 1942 want_init = 1; \ 1943 } \ 1944 } while (/*CONSTCOND*/0) 1945 1946 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1947 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1948 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1949 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1950 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1951 /* 1952 * Ignore: 1953 * Tx reset complete 1954 * Rx reset complete 1955 */ 1956 if (want_init) 1957 (void) sipcom_init(ifp); 1958 #undef PRINTERR 1959 } 1960 } 1961 1962 /* Re-enable interrupts. */ 1963 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1964 1965 /* Try to get more packets going. */ 1966 sipcom_start(ifp); 1967 1968 return (handled); 1969 } 1970 1971 /* 1972 * sip_txintr: 1973 * 1974 * Helper; handle transmit interrupts. 1975 */ 1976 static void 1977 sipcom_txintr(struct sip_softc *sc) 1978 { 1979 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1980 struct sip_txsoft *txs; 1981 u_int32_t cmdsts; 1982 1983 if (sc->sc_paused == 0) 1984 ifp->if_flags &= ~IFF_OACTIVE; 1985 1986 /* 1987 * Go through our Tx list and free mbufs for those 1988 * frames which have been transmitted. 1989 */ 1990 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1991 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1992 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1993 1994 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1995 if (cmdsts & CMDSTS_OWN) 1996 break; 1997 1998 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1999 2000 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2001 2002 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2003 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2004 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2005 m_freem(txs->txs_mbuf); 2006 txs->txs_mbuf = NULL; 2007 2008 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2009 2010 /* 2011 * Check for errors and collisions. 2012 */ 2013 if (cmdsts & 2014 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2015 ifp->if_oerrors++; 2016 if (cmdsts & CMDSTS_Tx_EC) 2017 ifp->if_collisions += 16; 2018 if (ifp->if_flags & IFF_DEBUG) { 2019 if (cmdsts & CMDSTS_Tx_ED) 2020 printf("%s: excessive deferral\n", 2021 sc->sc_dev.dv_xname); 2022 if (cmdsts & CMDSTS_Tx_EC) 2023 printf("%s: excessive collisions\n", 2024 sc->sc_dev.dv_xname); 2025 } 2026 } else { 2027 /* Packet was transmitted successfully. */ 2028 ifp->if_opackets++; 2029 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2030 } 2031 } 2032 2033 /* 2034 * If there are no more pending transmissions, cancel the watchdog 2035 * timer. 2036 */ 2037 if (txs == NULL) { 2038 ifp->if_timer = 0; 2039 sc->sc_txwin = 0; 2040 } 2041 } 2042 2043 /* 2044 * gsip_rxintr: 2045 * 2046 * Helper; handle receive interrupts on gigabit parts. 2047 */ 2048 static void 2049 gsip_rxintr(struct sip_softc *sc) 2050 { 2051 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2052 struct sip_rxsoft *rxs; 2053 struct mbuf *m; 2054 u_int32_t cmdsts, extsts; 2055 int i, len; 2056 2057 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2058 rxs = &sc->sc_rxsoft[i]; 2059 2060 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2061 2062 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2063 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2064 len = CMDSTS_SIZE(sc, cmdsts); 2065 2066 /* 2067 * NOTE: OWN is set if owned by _consumer_. We're the 2068 * consumer of the receive ring, so if the bit is clear, 2069 * we have processed all of the packets. 2070 */ 2071 if ((cmdsts & CMDSTS_OWN) == 0) { 2072 /* 2073 * We have processed all of the receive buffers. 2074 */ 2075 break; 2076 } 2077 2078 if (__predict_false(sc->sc_rxdiscard)) { 2079 sip_init_rxdesc(sc, i); 2080 if ((cmdsts & CMDSTS_MORE) == 0) { 2081 /* Reset our state. */ 2082 sc->sc_rxdiscard = 0; 2083 } 2084 continue; 2085 } 2086 2087 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2088 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2089 2090 m = rxs->rxs_mbuf; 2091 2092 /* 2093 * Add a new receive buffer to the ring. 2094 */ 2095 if (sipcom_add_rxbuf(sc, i) != 0) { 2096 /* 2097 * Failed, throw away what we've done so 2098 * far, and discard the rest of the packet. 2099 */ 2100 ifp->if_ierrors++; 2101 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2102 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2103 sip_init_rxdesc(sc, i); 2104 if (cmdsts & CMDSTS_MORE) 2105 sc->sc_rxdiscard = 1; 2106 if (sc->sc_rxhead != NULL) 2107 m_freem(sc->sc_rxhead); 2108 sip_rxchain_reset(sc); 2109 continue; 2110 } 2111 2112 sip_rxchain_link(sc, m); 2113 2114 m->m_len = len; 2115 2116 /* 2117 * If this is not the end of the packet, keep 2118 * looking. 2119 */ 2120 if (cmdsts & CMDSTS_MORE) { 2121 sc->sc_rxlen += len; 2122 continue; 2123 } 2124 2125 /* 2126 * Okay, we have the entire packet now. The chip includes 2127 * the FCS, so we need to trim it. 2128 */ 2129 m->m_len -= ETHER_CRC_LEN; 2130 2131 *sc->sc_rxtailp = NULL; 2132 len = m->m_len + sc->sc_rxlen; 2133 m = sc->sc_rxhead; 2134 2135 sip_rxchain_reset(sc); 2136 2137 /* 2138 * If an error occurred, update stats and drop the packet. 2139 */ 2140 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2141 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2142 ifp->if_ierrors++; 2143 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2144 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2145 /* Receive overrun handled elsewhere. */ 2146 printf("%s: receive descriptor error\n", 2147 sc->sc_dev.dv_xname); 2148 } 2149 #define PRINTERR(bit, str) \ 2150 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2151 (cmdsts & (bit)) != 0) \ 2152 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2153 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2154 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2155 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2156 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2157 #undef PRINTERR 2158 m_freem(m); 2159 continue; 2160 } 2161 2162 /* 2163 * If the packet is small enough to fit in a 2164 * single header mbuf, allocate one and copy 2165 * the data into it. This greatly reduces 2166 * memory consumption when we receive lots 2167 * of small packets. 2168 */ 2169 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2170 struct mbuf *nm; 2171 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2172 if (nm == NULL) { 2173 ifp->if_ierrors++; 2174 m_freem(m); 2175 continue; 2176 } 2177 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2178 nm->m_data += 2; 2179 nm->m_pkthdr.len = nm->m_len = len; 2180 m_copydata(m, 0, len, mtod(nm, void *)); 2181 m_freem(m); 2182 m = nm; 2183 } 2184 #ifndef __NO_STRICT_ALIGNMENT 2185 else { 2186 /* 2187 * The DP83820's receive buffers must be 4-byte 2188 * aligned. But this means that the data after 2189 * the Ethernet header is misaligned. To compensate, 2190 * we have artificially shortened the buffer size 2191 * in the descriptor, and we do an overlapping copy 2192 * of the data two bytes further in (in the first 2193 * buffer of the chain only). 2194 */ 2195 memmove(mtod(m, char *) + 2, mtod(m, void *), 2196 m->m_len); 2197 m->m_data += 2; 2198 } 2199 #endif /* ! __NO_STRICT_ALIGNMENT */ 2200 2201 /* 2202 * If VLANs are enabled, VLAN packets have been unwrapped 2203 * for us. Associate the tag with the packet. 2204 */ 2205 2206 /* 2207 * Again, byte swapping is tricky. Hardware provided 2208 * the tag in the network byte order, but extsts was 2209 * passed through le32toh() in the meantime. On a 2210 * big-endian machine, we need to swap it again. On a 2211 * little-endian machine, we need to convert from the 2212 * network to host byte order. This means that we must 2213 * swap it in any case, so unconditional swap instead 2214 * of htons() is used. 2215 */ 2216 if ((extsts & EXTSTS_VPKT) != 0) { 2217 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2218 continue); 2219 } 2220 2221 /* 2222 * Set the incoming checksum information for the 2223 * packet. 2224 */ 2225 if ((extsts & EXTSTS_IPPKT) != 0) { 2226 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2227 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2228 if (extsts & EXTSTS_Rx_IPERR) 2229 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2230 if (extsts & EXTSTS_TCPPKT) { 2231 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2232 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2233 if (extsts & EXTSTS_Rx_TCPERR) 2234 m->m_pkthdr.csum_flags |= 2235 M_CSUM_TCP_UDP_BAD; 2236 } else if (extsts & EXTSTS_UDPPKT) { 2237 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2238 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2239 if (extsts & EXTSTS_Rx_UDPERR) 2240 m->m_pkthdr.csum_flags |= 2241 M_CSUM_TCP_UDP_BAD; 2242 } 2243 } 2244 2245 ifp->if_ipackets++; 2246 m->m_pkthdr.rcvif = ifp; 2247 m->m_pkthdr.len = len; 2248 2249 #if NBPFILTER > 0 2250 /* 2251 * Pass this up to any BPF listeners, but only 2252 * pass if up the stack if it's for us. 2253 */ 2254 if (ifp->if_bpf) 2255 bpf_mtap(ifp->if_bpf, m); 2256 #endif /* NBPFILTER > 0 */ 2257 2258 /* Pass it on. */ 2259 (*ifp->if_input)(ifp, m); 2260 } 2261 2262 /* Update the receive pointer. */ 2263 sc->sc_rxptr = i; 2264 } 2265 2266 /* 2267 * sip_rxintr: 2268 * 2269 * Helper; handle receive interrupts on 10/100 parts. 2270 */ 2271 static void 2272 sip_rxintr(struct sip_softc *sc) 2273 { 2274 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2275 struct sip_rxsoft *rxs; 2276 struct mbuf *m; 2277 u_int32_t cmdsts; 2278 int i, len; 2279 2280 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2281 rxs = &sc->sc_rxsoft[i]; 2282 2283 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2284 2285 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2286 2287 /* 2288 * NOTE: OWN is set if owned by _consumer_. We're the 2289 * consumer of the receive ring, so if the bit is clear, 2290 * we have processed all of the packets. 2291 */ 2292 if ((cmdsts & CMDSTS_OWN) == 0) { 2293 /* 2294 * We have processed all of the receive buffers. 2295 */ 2296 break; 2297 } 2298 2299 /* 2300 * If any collisions were seen on the wire, count one. 2301 */ 2302 if (cmdsts & CMDSTS_Rx_COL) 2303 ifp->if_collisions++; 2304 2305 /* 2306 * If an error occurred, update stats, clear the status 2307 * word, and leave the packet buffer in place. It will 2308 * simply be reused the next time the ring comes around. 2309 */ 2310 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2311 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2312 ifp->if_ierrors++; 2313 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2314 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2315 /* Receive overrun handled elsewhere. */ 2316 printf("%s: receive descriptor error\n", 2317 sc->sc_dev.dv_xname); 2318 } 2319 #define PRINTERR(bit, str) \ 2320 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2321 (cmdsts & (bit)) != 0) \ 2322 printf("%s: %s\n", sc->sc_dev.dv_xname, str) 2323 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2324 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2325 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2326 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2327 #undef PRINTERR 2328 sip_init_rxdesc(sc, i); 2329 continue; 2330 } 2331 2332 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2333 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2334 2335 /* 2336 * No errors; receive the packet. Note, the SiS 900 2337 * includes the CRC with every packet. 2338 */ 2339 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2340 2341 #ifdef __NO_STRICT_ALIGNMENT 2342 /* 2343 * If the packet is small enough to fit in a 2344 * single header mbuf, allocate one and copy 2345 * the data into it. This greatly reduces 2346 * memory consumption when we receive lots 2347 * of small packets. 2348 * 2349 * Otherwise, we add a new buffer to the receive 2350 * chain. If this fails, we drop the packet and 2351 * recycle the old buffer. 2352 */ 2353 if (sip_copy_small != 0 && len <= MHLEN) { 2354 MGETHDR(m, M_DONTWAIT, MT_DATA); 2355 if (m == NULL) 2356 goto dropit; 2357 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2358 memcpy(mtod(m, void *), 2359 mtod(rxs->rxs_mbuf, void *), len); 2360 sip_init_rxdesc(sc, i); 2361 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2362 rxs->rxs_dmamap->dm_mapsize, 2363 BUS_DMASYNC_PREREAD); 2364 } else { 2365 m = rxs->rxs_mbuf; 2366 if (sipcom_add_rxbuf(sc, i) != 0) { 2367 dropit: 2368 ifp->if_ierrors++; 2369 sip_init_rxdesc(sc, i); 2370 bus_dmamap_sync(sc->sc_dmat, 2371 rxs->rxs_dmamap, 0, 2372 rxs->rxs_dmamap->dm_mapsize, 2373 BUS_DMASYNC_PREREAD); 2374 continue; 2375 } 2376 } 2377 #else 2378 /* 2379 * The SiS 900's receive buffers must be 4-byte aligned. 2380 * But this means that the data after the Ethernet header 2381 * is misaligned. We must allocate a new buffer and 2382 * copy the data, shifted forward 2 bytes. 2383 */ 2384 MGETHDR(m, M_DONTWAIT, MT_DATA); 2385 if (m == NULL) { 2386 dropit: 2387 ifp->if_ierrors++; 2388 sip_init_rxdesc(sc, i); 2389 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2390 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2391 continue; 2392 } 2393 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2394 if (len > (MHLEN - 2)) { 2395 MCLGET(m, M_DONTWAIT); 2396 if ((m->m_flags & M_EXT) == 0) { 2397 m_freem(m); 2398 goto dropit; 2399 } 2400 } 2401 m->m_data += 2; 2402 2403 /* 2404 * Note that we use clusters for incoming frames, so the 2405 * buffer is virtually contiguous. 2406 */ 2407 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2408 2409 /* Allow the receive descriptor to continue using its mbuf. */ 2410 sip_init_rxdesc(sc, i); 2411 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2412 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2413 #endif /* __NO_STRICT_ALIGNMENT */ 2414 2415 ifp->if_ipackets++; 2416 m->m_pkthdr.rcvif = ifp; 2417 m->m_pkthdr.len = m->m_len = len; 2418 2419 #if NBPFILTER > 0 2420 /* 2421 * Pass this up to any BPF listeners, but only 2422 * pass if up the stack if it's for us. 2423 */ 2424 if (ifp->if_bpf) 2425 bpf_mtap(ifp->if_bpf, m); 2426 #endif /* NBPFILTER > 0 */ 2427 2428 /* Pass it on. */ 2429 (*ifp->if_input)(ifp, m); 2430 } 2431 2432 /* Update the receive pointer. */ 2433 sc->sc_rxptr = i; 2434 } 2435 2436 /* 2437 * sip_tick: 2438 * 2439 * One second timer, used to tick the MII. 2440 */ 2441 static void 2442 sipcom_tick(void *arg) 2443 { 2444 struct sip_softc *sc = arg; 2445 int s; 2446 2447 s = splnet(); 2448 #ifdef SIP_EVENT_COUNTERS 2449 if (sc->sc_gigabit) { 2450 /* Read PAUSE related counts from MIB registers. */ 2451 sc->sc_ev_rxpause.ev_count += 2452 bus_space_read_4(sc->sc_st, sc->sc_sh, 2453 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2454 sc->sc_ev_txpause.ev_count += 2455 bus_space_read_4(sc->sc_st, sc->sc_sh, 2456 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2457 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2458 } 2459 #endif /* SIP_EVENT_COUNTERS */ 2460 mii_tick(&sc->sc_mii); 2461 splx(s); 2462 2463 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2464 } 2465 2466 /* 2467 * sip_reset: 2468 * 2469 * Perform a soft reset on the SiS 900. 2470 */ 2471 static bool 2472 sipcom_reset(struct sip_softc *sc) 2473 { 2474 bus_space_tag_t st = sc->sc_st; 2475 bus_space_handle_t sh = sc->sc_sh; 2476 int i; 2477 2478 bus_space_write_4(st, sh, SIP_IER, 0); 2479 bus_space_write_4(st, sh, SIP_IMR, 0); 2480 bus_space_write_4(st, sh, SIP_RFCR, 0); 2481 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2482 2483 for (i = 0; i < SIP_TIMEOUT; i++) { 2484 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2485 break; 2486 delay(2); 2487 } 2488 2489 if (i == SIP_TIMEOUT) { 2490 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 2491 return false; 2492 } 2493 2494 delay(1000); 2495 2496 if (sc->sc_gigabit) { 2497 /* 2498 * Set the general purpose I/O bits. Do it here in case we 2499 * need to have GPIO set up to talk to the media interface. 2500 */ 2501 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2502 delay(1000); 2503 } 2504 return true; 2505 } 2506 2507 static void 2508 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2509 { 2510 u_int32_t reg; 2511 bus_space_tag_t st = sc->sc_st; 2512 bus_space_handle_t sh = sc->sc_sh; 2513 /* 2514 * Initialize the VLAN/IP receive control register. 2515 * We enable checksum computation on all incoming 2516 * packets, and do not reject packets w/ bad checksums. 2517 */ 2518 reg = 0; 2519 if (capenable & 2520 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2521 reg |= VRCR_IPEN; 2522 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2523 reg |= VRCR_VTDEN|VRCR_VTREN; 2524 bus_space_write_4(st, sh, SIP_VRCR, reg); 2525 2526 /* 2527 * Initialize the VLAN/IP transmit control register. 2528 * We enable outgoing checksum computation on a 2529 * per-packet basis. 2530 */ 2531 reg = 0; 2532 if (capenable & 2533 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2534 reg |= VTCR_PPCHK; 2535 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2536 reg |= VTCR_VPPTI; 2537 bus_space_write_4(st, sh, SIP_VTCR, reg); 2538 2539 /* 2540 * If we're using VLANs, initialize the VLAN data register. 2541 * To understand why we bswap the VLAN Ethertype, see section 2542 * 4.2.36 of the DP83820 manual. 2543 */ 2544 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2545 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2546 } 2547 2548 /* 2549 * sip_init: [ ifnet interface function ] 2550 * 2551 * Initialize the interface. Must be called at splnet(). 2552 */ 2553 static int 2554 sipcom_init(struct ifnet *ifp) 2555 { 2556 struct sip_softc *sc = ifp->if_softc; 2557 bus_space_tag_t st = sc->sc_st; 2558 bus_space_handle_t sh = sc->sc_sh; 2559 struct sip_txsoft *txs; 2560 struct sip_rxsoft *rxs; 2561 struct sip_desc *sipd; 2562 int i, error = 0; 2563 2564 if (device_is_active(&sc->sc_dev)) { 2565 /* 2566 * Cancel any pending I/O. 2567 */ 2568 sipcom_stop(ifp, 0); 2569 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2570 return 0; 2571 2572 /* 2573 * Reset the chip to a known state. 2574 */ 2575 if (!sipcom_reset(sc)) 2576 return EBUSY; 2577 2578 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2579 /* 2580 * DP83815 manual, page 78: 2581 * 4.4 Recommended Registers Configuration 2582 * For optimum performance of the DP83815, version noted 2583 * as DP83815CVNG (SRR = 203h), the listed register 2584 * modifications must be followed in sequence... 2585 * 2586 * It's not clear if this should be 302h or 203h because that 2587 * chip name is listed as SRR 302h in the description of the 2588 * SRR register. However, my revision 302h DP83815 on the 2589 * Netgear FA311 purchased in 02/2001 needs these settings 2590 * to avoid tons of errors in AcceptPerfectMatch (non- 2591 * IFF_PROMISC) mode. I do not know if other revisions need 2592 * this set or not. [briggs -- 09 March 2001] 2593 * 2594 * Note that only the low-order 12 bits of 0xe4 are documented 2595 * and that this sets reserved bits in that register. 2596 */ 2597 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2598 2599 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2600 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2601 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2602 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2603 2604 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2605 } 2606 2607 /* 2608 * Initialize the transmit descriptor ring. 2609 */ 2610 for (i = 0; i < sc->sc_ntxdesc; i++) { 2611 sipd = &sc->sc_txdescs[i]; 2612 memset(sipd, 0, sizeof(struct sip_desc)); 2613 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2614 } 2615 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2616 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2617 sc->sc_txfree = sc->sc_ntxdesc; 2618 sc->sc_txnext = 0; 2619 sc->sc_txwin = 0; 2620 2621 /* 2622 * Initialize the transmit job descriptors. 2623 */ 2624 SIMPLEQ_INIT(&sc->sc_txfreeq); 2625 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2626 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2627 txs = &sc->sc_txsoft[i]; 2628 txs->txs_mbuf = NULL; 2629 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2630 } 2631 2632 /* 2633 * Initialize the receive descriptor and receive job 2634 * descriptor rings. 2635 */ 2636 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2637 rxs = &sc->sc_rxsoft[i]; 2638 if (rxs->rxs_mbuf == NULL) { 2639 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2640 printf("%s: unable to allocate or map rx " 2641 "buffer %d, error = %d\n", 2642 sc->sc_dev.dv_xname, i, error); 2643 /* 2644 * XXX Should attempt to run with fewer receive 2645 * XXX buffers instead of just failing. 2646 */ 2647 sipcom_rxdrain(sc); 2648 goto out; 2649 } 2650 } else 2651 sip_init_rxdesc(sc, i); 2652 } 2653 sc->sc_rxptr = 0; 2654 sc->sc_rxdiscard = 0; 2655 sip_rxchain_reset(sc); 2656 2657 /* 2658 * Set the configuration register; it's already initialized 2659 * in sip_attach(). 2660 */ 2661 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2662 2663 /* 2664 * Initialize the prototype TXCFG register. 2665 */ 2666 if (sc->sc_gigabit) { 2667 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2668 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2669 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2670 SIP_SIS900_REV(sc, SIS_REV_960) || 2671 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2672 (sc->sc_cfg & CFG_EDBMASTEN)) { 2673 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2674 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2675 } else { 2676 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2677 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2678 } 2679 2680 sc->sc_txcfg |= TXCFG_ATP | 2681 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2682 sc->sc_tx_drain_thresh; 2683 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2684 2685 /* 2686 * Initialize the receive drain threshold if we have never 2687 * done so. 2688 */ 2689 if (sc->sc_rx_drain_thresh == 0) { 2690 /* 2691 * XXX This value should be tuned. This is set to the 2692 * maximum of 248 bytes, and we may be able to improve 2693 * performance by decreasing it (although we should never 2694 * set this value lower than 2; 14 bytes are required to 2695 * filter the packet). 2696 */ 2697 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2698 } 2699 2700 /* 2701 * Initialize the prototype RXCFG register. 2702 */ 2703 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2704 /* 2705 * Accept long packets (including FCS) so we can handle 2706 * 802.1q-tagged frames and jumbo frames properly. 2707 */ 2708 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2709 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2710 sc->sc_rxcfg |= RXCFG_ALP; 2711 2712 /* 2713 * Checksum offloading is disabled if the user selects an MTU 2714 * larger than 8109. (FreeBSD says 8152, but there is emperical 2715 * evidence that >8109 does not work on some boards, such as the 2716 * Planex GN-1000TE). 2717 */ 2718 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2719 (ifp->if_capenable & 2720 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2721 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2722 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2723 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2724 "disabled.\n", sc->sc_dev.dv_xname); 2725 ifp->if_capenable &= 2726 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2727 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2728 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2729 ifp->if_csum_flags_tx = 0; 2730 ifp->if_csum_flags_rx = 0; 2731 } 2732 2733 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2734 2735 if (sc->sc_gigabit) 2736 sipcom_dp83820_init(sc, ifp->if_capenable); 2737 2738 /* 2739 * Give the transmit and receive rings to the chip. 2740 */ 2741 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2742 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2743 2744 /* 2745 * Initialize the interrupt mask. 2746 */ 2747 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2748 sc->sc_bits.b_isr_sserr | 2749 sc->sc_bits.b_isr_rmabt | 2750 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2751 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2752 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2753 2754 /* Set up the receive filter. */ 2755 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2756 2757 /* 2758 * Tune sc_rx_flow_thresh. 2759 * XXX "More than 8KB" is too short for jumbo frames. 2760 * XXX TODO: Threshold value should be user-settable. 2761 */ 2762 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2763 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2764 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2765 2766 /* 2767 * Set the current media. Do this after initializing the prototype 2768 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2769 * control. 2770 */ 2771 if ((error = ether_mediachange(ifp)) != 0) 2772 goto out; 2773 2774 /* 2775 * Set the interrupt hold-off timer to 100us. 2776 */ 2777 if (sc->sc_gigabit) 2778 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2779 2780 /* 2781 * Enable interrupts. 2782 */ 2783 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2784 2785 /* 2786 * Start the transmit and receive processes. 2787 */ 2788 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2789 2790 /* 2791 * Start the one second MII clock. 2792 */ 2793 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2794 2795 /* 2796 * ...all done! 2797 */ 2798 ifp->if_flags |= IFF_RUNNING; 2799 ifp->if_flags &= ~IFF_OACTIVE; 2800 sc->sc_if_flags = ifp->if_flags; 2801 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2802 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2803 sc->sc_prev.if_capenable = ifp->if_capenable; 2804 2805 out: 2806 if (error) 2807 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 2808 return (error); 2809 } 2810 2811 /* 2812 * sip_drain: 2813 * 2814 * Drain the receive queue. 2815 */ 2816 static void 2817 sipcom_rxdrain(struct sip_softc *sc) 2818 { 2819 struct sip_rxsoft *rxs; 2820 int i; 2821 2822 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2823 rxs = &sc->sc_rxsoft[i]; 2824 if (rxs->rxs_mbuf != NULL) { 2825 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2826 m_freem(rxs->rxs_mbuf); 2827 rxs->rxs_mbuf = NULL; 2828 } 2829 } 2830 } 2831 2832 /* 2833 * sip_stop: [ ifnet interface function ] 2834 * 2835 * Stop transmission on the interface. 2836 */ 2837 static void 2838 sipcom_stop(struct ifnet *ifp, int disable) 2839 { 2840 struct sip_softc *sc = ifp->if_softc; 2841 bus_space_tag_t st = sc->sc_st; 2842 bus_space_handle_t sh = sc->sc_sh; 2843 struct sip_txsoft *txs; 2844 u_int32_t cmdsts = 0; /* DEBUG */ 2845 2846 /* 2847 * Stop the one second clock. 2848 */ 2849 callout_stop(&sc->sc_tick_ch); 2850 2851 /* Down the MII. */ 2852 mii_down(&sc->sc_mii); 2853 2854 /* 2855 * Disable interrupts. 2856 */ 2857 bus_space_write_4(st, sh, SIP_IER, 0); 2858 2859 /* 2860 * Stop receiver and transmitter. 2861 */ 2862 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2863 2864 /* 2865 * Release any queued transmit buffers. 2866 */ 2867 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2868 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2869 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2870 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2871 CMDSTS_INTR) == 0) 2872 printf("%s: sip_stop: last descriptor does not " 2873 "have INTR bit set\n", sc->sc_dev.dv_xname); 2874 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2875 #ifdef DIAGNOSTIC 2876 if (txs->txs_mbuf == NULL) { 2877 printf("%s: dirty txsoft with no mbuf chain\n", 2878 sc->sc_dev.dv_xname); 2879 panic("sip_stop"); 2880 } 2881 #endif 2882 cmdsts |= /* DEBUG */ 2883 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2884 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2885 m_freem(txs->txs_mbuf); 2886 txs->txs_mbuf = NULL; 2887 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2888 } 2889 2890 /* 2891 * Mark the interface down and cancel the watchdog timer. 2892 */ 2893 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2894 ifp->if_timer = 0; 2895 2896 if (disable) 2897 pmf_device_suspend_self(&sc->sc_dev); 2898 2899 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2900 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2901 printf("%s: sip_stop: no INTR bits set in dirty tx " 2902 "descriptors\n", sc->sc_dev.dv_xname); 2903 } 2904 2905 /* 2906 * sip_read_eeprom: 2907 * 2908 * Read data from the serial EEPROM. 2909 */ 2910 static void 2911 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2912 u_int16_t *data) 2913 { 2914 bus_space_tag_t st = sc->sc_st; 2915 bus_space_handle_t sh = sc->sc_sh; 2916 u_int16_t reg; 2917 int i, x; 2918 2919 for (i = 0; i < wordcnt; i++) { 2920 /* Send CHIP SELECT. */ 2921 reg = EROMAR_EECS; 2922 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2923 2924 /* Shift in the READ opcode. */ 2925 for (x = 3; x > 0; x--) { 2926 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2927 reg |= EROMAR_EEDI; 2928 else 2929 reg &= ~EROMAR_EEDI; 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 bus_space_write_4(st, sh, SIP_EROMAR, 2932 reg | EROMAR_EESK); 2933 delay(4); 2934 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2935 delay(4); 2936 } 2937 2938 /* Shift in address. */ 2939 for (x = 6; x > 0; x--) { 2940 if ((word + i) & (1 << (x - 1))) 2941 reg |= EROMAR_EEDI; 2942 else 2943 reg &= ~EROMAR_EEDI; 2944 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2945 bus_space_write_4(st, sh, SIP_EROMAR, 2946 reg | EROMAR_EESK); 2947 delay(4); 2948 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2949 delay(4); 2950 } 2951 2952 /* Shift out data. */ 2953 reg = EROMAR_EECS; 2954 data[i] = 0; 2955 for (x = 16; x > 0; x--) { 2956 bus_space_write_4(st, sh, SIP_EROMAR, 2957 reg | EROMAR_EESK); 2958 delay(4); 2959 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2960 data[i] |= (1 << (x - 1)); 2961 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2962 delay(4); 2963 } 2964 2965 /* Clear CHIP SELECT. */ 2966 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2967 delay(4); 2968 } 2969 } 2970 2971 /* 2972 * sipcom_add_rxbuf: 2973 * 2974 * Add a receive buffer to the indicated descriptor. 2975 */ 2976 static int 2977 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2978 { 2979 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2980 struct mbuf *m; 2981 int error; 2982 2983 MGETHDR(m, M_DONTWAIT, MT_DATA); 2984 if (m == NULL) 2985 return (ENOBUFS); 2986 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2987 2988 MCLGET(m, M_DONTWAIT); 2989 if ((m->m_flags & M_EXT) == 0) { 2990 m_freem(m); 2991 return (ENOBUFS); 2992 } 2993 2994 /* XXX I don't believe this is necessary. --dyoung */ 2995 if (sc->sc_gigabit) 2996 m->m_len = sc->sc_parm->p_rxbuf_len; 2997 2998 if (rxs->rxs_mbuf != NULL) 2999 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3000 3001 rxs->rxs_mbuf = m; 3002 3003 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3004 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3005 BUS_DMA_READ|BUS_DMA_NOWAIT); 3006 if (error) { 3007 printf("%s: can't load rx DMA map %d, error = %d\n", 3008 sc->sc_dev.dv_xname, idx, error); 3009 panic("%s", __func__); /* XXX */ 3010 } 3011 3012 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3013 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3014 3015 sip_init_rxdesc(sc, idx); 3016 3017 return (0); 3018 } 3019 3020 /* 3021 * sip_sis900_set_filter: 3022 * 3023 * Set up the receive filter. 3024 */ 3025 static void 3026 sipcom_sis900_set_filter(struct sip_softc *sc) 3027 { 3028 bus_space_tag_t st = sc->sc_st; 3029 bus_space_handle_t sh = sc->sc_sh; 3030 struct ethercom *ec = &sc->sc_ethercom; 3031 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3032 struct ether_multi *enm; 3033 const u_int8_t *cp; 3034 struct ether_multistep step; 3035 u_int32_t crc, mchash[16]; 3036 3037 /* 3038 * Initialize the prototype RFCR. 3039 */ 3040 sc->sc_rfcr = RFCR_RFEN; 3041 if (ifp->if_flags & IFF_BROADCAST) 3042 sc->sc_rfcr |= RFCR_AAB; 3043 if (ifp->if_flags & IFF_PROMISC) { 3044 sc->sc_rfcr |= RFCR_AAP; 3045 goto allmulti; 3046 } 3047 3048 /* 3049 * Set up the multicast address filter by passing all multicast 3050 * addresses through a CRC generator, and then using the high-order 3051 * 6 bits as an index into the 128 bit multicast hash table (only 3052 * the lower 16 bits of each 32 bit multicast hash register are 3053 * valid). The high order bits select the register, while the 3054 * rest of the bits select the bit within the register. 3055 */ 3056 3057 memset(mchash, 0, sizeof(mchash)); 3058 3059 /* 3060 * SiS900 (at least SiS963) requires us to register the address of 3061 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3062 */ 3063 crc = 0x0ed423f9; 3064 3065 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3066 SIP_SIS900_REV(sc, SIS_REV_960) || 3067 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3068 /* Just want the 8 most significant bits. */ 3069 crc >>= 24; 3070 } else { 3071 /* Just want the 7 most significant bits. */ 3072 crc >>= 25; 3073 } 3074 3075 /* Set the corresponding bit in the hash table. */ 3076 mchash[crc >> 4] |= 1 << (crc & 0xf); 3077 3078 ETHER_FIRST_MULTI(step, ec, enm); 3079 while (enm != NULL) { 3080 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3081 /* 3082 * We must listen to a range of multicast addresses. 3083 * For now, just accept all multicasts, rather than 3084 * trying to set only those filter bits needed to match 3085 * the range. (At this time, the only use of address 3086 * ranges is for IP multicast routing, for which the 3087 * range is big enough to require all bits set.) 3088 */ 3089 goto allmulti; 3090 } 3091 3092 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3093 3094 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3095 SIP_SIS900_REV(sc, SIS_REV_960) || 3096 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3097 /* Just want the 8 most significant bits. */ 3098 crc >>= 24; 3099 } else { 3100 /* Just want the 7 most significant bits. */ 3101 crc >>= 25; 3102 } 3103 3104 /* Set the corresponding bit in the hash table. */ 3105 mchash[crc >> 4] |= 1 << (crc & 0xf); 3106 3107 ETHER_NEXT_MULTI(step, enm); 3108 } 3109 3110 ifp->if_flags &= ~IFF_ALLMULTI; 3111 goto setit; 3112 3113 allmulti: 3114 ifp->if_flags |= IFF_ALLMULTI; 3115 sc->sc_rfcr |= RFCR_AAM; 3116 3117 setit: 3118 #define FILTER_EMIT(addr, data) \ 3119 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3120 delay(1); \ 3121 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3122 delay(1) 3123 3124 /* 3125 * Disable receive filter, and program the node address. 3126 */ 3127 cp = CLLADDR(ifp->if_sadl); 3128 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3129 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3130 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3131 3132 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3133 /* 3134 * Program the multicast hash table. 3135 */ 3136 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3137 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3138 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3139 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3140 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3141 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3142 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3143 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3144 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3145 SIP_SIS900_REV(sc, SIS_REV_960) || 3146 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3147 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3148 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3149 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3150 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3151 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3152 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3153 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3154 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3155 } 3156 } 3157 #undef FILTER_EMIT 3158 3159 /* 3160 * Re-enable the receiver filter. 3161 */ 3162 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3163 } 3164 3165 /* 3166 * sip_dp83815_set_filter: 3167 * 3168 * Set up the receive filter. 3169 */ 3170 static void 3171 sipcom_dp83815_set_filter(struct sip_softc *sc) 3172 { 3173 bus_space_tag_t st = sc->sc_st; 3174 bus_space_handle_t sh = sc->sc_sh; 3175 struct ethercom *ec = &sc->sc_ethercom; 3176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3177 struct ether_multi *enm; 3178 const u_int8_t *cp; 3179 struct ether_multistep step; 3180 u_int32_t crc, hash, slot, bit; 3181 #define MCHASH_NWORDS_83820 128 3182 #define MCHASH_NWORDS_83815 32 3183 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3184 u_int16_t mchash[MCHASH_NWORDS]; 3185 int i; 3186 3187 /* 3188 * Initialize the prototype RFCR. 3189 * Enable the receive filter, and accept on 3190 * Perfect (destination address) Match 3191 * If IFF_BROADCAST, also accept all broadcast packets. 3192 * If IFF_PROMISC, accept all unicast packets (and later, set 3193 * IFF_ALLMULTI and accept all multicast, too). 3194 */ 3195 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3196 if (ifp->if_flags & IFF_BROADCAST) 3197 sc->sc_rfcr |= RFCR_AAB; 3198 if (ifp->if_flags & IFF_PROMISC) { 3199 sc->sc_rfcr |= RFCR_AAP; 3200 goto allmulti; 3201 } 3202 3203 /* 3204 * Set up the DP83820/DP83815 multicast address filter by 3205 * passing all multicast addresses through a CRC generator, 3206 * and then using the high-order 11/9 bits as an index into 3207 * the 2048/512 bit multicast hash table. The high-order 3208 * 7/5 bits select the slot, while the low-order 4 bits 3209 * select the bit within the slot. Note that only the low 3210 * 16-bits of each filter word are used, and there are 3211 * 128/32 filter words. 3212 */ 3213 3214 memset(mchash, 0, sizeof(mchash)); 3215 3216 ifp->if_flags &= ~IFF_ALLMULTI; 3217 ETHER_FIRST_MULTI(step, ec, enm); 3218 if (enm == NULL) 3219 goto setit; 3220 while (enm != NULL) { 3221 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3222 /* 3223 * We must listen to a range of multicast addresses. 3224 * For now, just accept all multicasts, rather than 3225 * trying to set only those filter bits needed to match 3226 * the range. (At this time, the only use of address 3227 * ranges is for IP multicast routing, for which the 3228 * range is big enough to require all bits set.) 3229 */ 3230 goto allmulti; 3231 } 3232 3233 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3234 3235 if (sc->sc_gigabit) { 3236 /* Just want the 11 most significant bits. */ 3237 hash = crc >> 21; 3238 } else { 3239 /* Just want the 9 most significant bits. */ 3240 hash = crc >> 23; 3241 } 3242 3243 slot = hash >> 4; 3244 bit = hash & 0xf; 3245 3246 /* Set the corresponding bit in the hash table. */ 3247 mchash[slot] |= 1 << bit; 3248 3249 ETHER_NEXT_MULTI(step, enm); 3250 } 3251 sc->sc_rfcr |= RFCR_MHEN; 3252 goto setit; 3253 3254 allmulti: 3255 ifp->if_flags |= IFF_ALLMULTI; 3256 sc->sc_rfcr |= RFCR_AAM; 3257 3258 setit: 3259 #define FILTER_EMIT(addr, data) \ 3260 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3261 delay(1); \ 3262 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3263 delay(1) 3264 3265 /* 3266 * Disable receive filter, and program the node address. 3267 */ 3268 cp = CLLADDR(ifp->if_sadl); 3269 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3270 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3271 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3272 3273 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3274 int nwords = 3275 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3276 /* 3277 * Program the multicast hash table. 3278 */ 3279 for (i = 0; i < nwords; i++) { 3280 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3281 } 3282 } 3283 #undef FILTER_EMIT 3284 #undef MCHASH_NWORDS 3285 #undef MCHASH_NWORDS_83815 3286 #undef MCHASH_NWORDS_83820 3287 3288 /* 3289 * Re-enable the receiver filter. 3290 */ 3291 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3292 } 3293 3294 /* 3295 * sip_dp83820_mii_readreg: [mii interface function] 3296 * 3297 * Read a PHY register on the MII of the DP83820. 3298 */ 3299 static int 3300 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3301 { 3302 struct sip_softc *sc = device_private(self); 3303 3304 if (sc->sc_cfg & CFG_TBI_EN) { 3305 bus_addr_t tbireg; 3306 int rv; 3307 3308 if (phy != 0) 3309 return (0); 3310 3311 switch (reg) { 3312 case MII_BMCR: tbireg = SIP_TBICR; break; 3313 case MII_BMSR: tbireg = SIP_TBISR; break; 3314 case MII_ANAR: tbireg = SIP_TANAR; break; 3315 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3316 case MII_ANER: tbireg = SIP_TANER; break; 3317 case MII_EXTSR: 3318 /* 3319 * Don't even bother reading the TESR register. 3320 * The manual documents that the device has 3321 * 1000baseX full/half capability, but the 3322 * register itself seems read back 0 on some 3323 * boards. Just hard-code the result. 3324 */ 3325 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3326 3327 default: 3328 return (0); 3329 } 3330 3331 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3332 if (tbireg == SIP_TBISR) { 3333 /* LINK and ACOMP are switched! */ 3334 int val = rv; 3335 3336 rv = 0; 3337 if (val & TBISR_MR_LINK_STATUS) 3338 rv |= BMSR_LINK; 3339 if (val & TBISR_MR_AN_COMPLETE) 3340 rv |= BMSR_ACOMP; 3341 3342 /* 3343 * The manual claims this register reads back 0 3344 * on hard and soft reset. But we want to let 3345 * the gentbi driver know that we support auto- 3346 * negotiation, so hard-code this bit in the 3347 * result. 3348 */ 3349 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3350 } 3351 3352 return (rv); 3353 } 3354 3355 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3356 } 3357 3358 /* 3359 * sip_dp83820_mii_writereg: [mii interface function] 3360 * 3361 * Write a PHY register on the MII of the DP83820. 3362 */ 3363 static void 3364 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3365 { 3366 struct sip_softc *sc = device_private(self); 3367 3368 if (sc->sc_cfg & CFG_TBI_EN) { 3369 bus_addr_t tbireg; 3370 3371 if (phy != 0) 3372 return; 3373 3374 switch (reg) { 3375 case MII_BMCR: tbireg = SIP_TBICR; break; 3376 case MII_ANAR: tbireg = SIP_TANAR; break; 3377 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3378 default: 3379 return; 3380 } 3381 3382 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3383 return; 3384 } 3385 3386 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3387 } 3388 3389 /* 3390 * sip_dp83820_mii_statchg: [mii interface function] 3391 * 3392 * Callback from MII layer when media changes. 3393 */ 3394 static void 3395 sipcom_dp83820_mii_statchg(device_t self) 3396 { 3397 struct sip_softc *sc = device_private(self); 3398 struct mii_data *mii = &sc->sc_mii; 3399 u_int32_t cfg, pcr; 3400 3401 /* 3402 * Get flow control negotiation result. 3403 */ 3404 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3405 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3406 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3407 mii->mii_media_active &= ~IFM_ETH_FMASK; 3408 } 3409 3410 /* 3411 * Update TXCFG for full-duplex operation. 3412 */ 3413 if ((mii->mii_media_active & IFM_FDX) != 0) 3414 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3415 else 3416 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3417 3418 /* 3419 * Update RXCFG for full-duplex or loopback. 3420 */ 3421 if ((mii->mii_media_active & IFM_FDX) != 0 || 3422 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3423 sc->sc_rxcfg |= RXCFG_ATX; 3424 else 3425 sc->sc_rxcfg &= ~RXCFG_ATX; 3426 3427 /* 3428 * Update CFG for MII/GMII. 3429 */ 3430 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3431 cfg = sc->sc_cfg | CFG_MODE_1000; 3432 else 3433 cfg = sc->sc_cfg; 3434 3435 /* 3436 * 802.3x flow control. 3437 */ 3438 pcr = 0; 3439 if (sc->sc_flowflags & IFM_FLOW) { 3440 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3441 pcr |= sc->sc_rx_flow_thresh; 3442 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3443 pcr |= PCR_PSEN | PCR_PS_MCAST; 3444 } 3445 3446 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3447 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3448 sc->sc_txcfg); 3449 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3450 sc->sc_rxcfg); 3451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3452 } 3453 3454 /* 3455 * sip_mii_bitbang_read: [mii bit-bang interface function] 3456 * 3457 * Read the MII serial port for the MII bit-bang module. 3458 */ 3459 static u_int32_t 3460 sipcom_mii_bitbang_read(device_t self) 3461 { 3462 struct sip_softc *sc = device_private(self); 3463 3464 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3465 } 3466 3467 /* 3468 * sip_mii_bitbang_write: [mii big-bang interface function] 3469 * 3470 * Write the MII serial port for the MII bit-bang module. 3471 */ 3472 static void 3473 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3474 { 3475 struct sip_softc *sc = device_private(self); 3476 3477 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3478 } 3479 3480 /* 3481 * sip_sis900_mii_readreg: [mii interface function] 3482 * 3483 * Read a PHY register on the MII. 3484 */ 3485 static int 3486 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3487 { 3488 struct sip_softc *sc = device_private(self); 3489 u_int32_t enphy; 3490 3491 /* 3492 * The PHY of recent SiS chipsets is accessed through bitbang 3493 * operations. 3494 */ 3495 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3496 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3497 phy, reg); 3498 3499 #ifndef SIS900_MII_RESTRICT 3500 /* 3501 * The SiS 900 has only an internal PHY on the MII. Only allow 3502 * MII address 0. 3503 */ 3504 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3505 return (0); 3506 #endif 3507 3508 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3509 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3510 ENPHY_RWCMD | ENPHY_ACCESS); 3511 do { 3512 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3513 } while (enphy & ENPHY_ACCESS); 3514 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3515 } 3516 3517 /* 3518 * sip_sis900_mii_writereg: [mii interface function] 3519 * 3520 * Write a PHY register on the MII. 3521 */ 3522 static void 3523 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3524 { 3525 struct sip_softc *sc = device_private(self); 3526 u_int32_t enphy; 3527 3528 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3529 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3530 phy, reg, val); 3531 return; 3532 } 3533 3534 #ifndef SIS900_MII_RESTRICT 3535 /* 3536 * The SiS 900 has only an internal PHY on the MII. Only allow 3537 * MII address 0. 3538 */ 3539 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3540 return; 3541 #endif 3542 3543 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3544 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3545 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3546 do { 3547 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3548 } while (enphy & ENPHY_ACCESS); 3549 } 3550 3551 /* 3552 * sip_sis900_mii_statchg: [mii interface function] 3553 * 3554 * Callback from MII layer when media changes. 3555 */ 3556 static void 3557 sipcom_sis900_mii_statchg(device_t self) 3558 { 3559 struct sip_softc *sc = device_private(self); 3560 struct mii_data *mii = &sc->sc_mii; 3561 u_int32_t flowctl; 3562 3563 /* 3564 * Get flow control negotiation result. 3565 */ 3566 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3567 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3568 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3569 mii->mii_media_active &= ~IFM_ETH_FMASK; 3570 } 3571 3572 /* 3573 * Update TXCFG for full-duplex operation. 3574 */ 3575 if ((mii->mii_media_active & IFM_FDX) != 0) 3576 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3577 else 3578 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3579 3580 /* 3581 * Update RXCFG for full-duplex or loopback. 3582 */ 3583 if ((mii->mii_media_active & IFM_FDX) != 0 || 3584 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3585 sc->sc_rxcfg |= RXCFG_ATX; 3586 else 3587 sc->sc_rxcfg &= ~RXCFG_ATX; 3588 3589 /* 3590 * Update IMR for use of 802.3x flow control. 3591 */ 3592 if (sc->sc_flowflags & IFM_FLOW) { 3593 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3594 flowctl = FLOWCTL_FLOWEN; 3595 } else { 3596 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3597 flowctl = 0; 3598 } 3599 3600 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3601 sc->sc_txcfg); 3602 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3603 sc->sc_rxcfg); 3604 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3605 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3606 } 3607 3608 /* 3609 * sip_dp83815_mii_readreg: [mii interface function] 3610 * 3611 * Read a PHY register on the MII. 3612 */ 3613 static int 3614 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3615 { 3616 struct sip_softc *sc = device_private(self); 3617 u_int32_t val; 3618 3619 /* 3620 * The DP83815 only has an internal PHY. Only allow 3621 * MII address 0. 3622 */ 3623 if (phy != 0) 3624 return (0); 3625 3626 /* 3627 * Apparently, after a reset, the DP83815 can take a while 3628 * to respond. During this recovery period, the BMSR returns 3629 * a value of 0. Catch this -- it's not supposed to happen 3630 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3631 * PHY to come back to life. 3632 * 3633 * This works out because the BMSR is the first register 3634 * read during the PHY probe process. 3635 */ 3636 do { 3637 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3638 } while (reg == MII_BMSR && val == 0); 3639 3640 return (val & 0xffff); 3641 } 3642 3643 /* 3644 * sip_dp83815_mii_writereg: [mii interface function] 3645 * 3646 * Write a PHY register to the MII. 3647 */ 3648 static void 3649 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3650 { 3651 struct sip_softc *sc = device_private(self); 3652 3653 /* 3654 * The DP83815 only has an internal PHY. Only allow 3655 * MII address 0. 3656 */ 3657 if (phy != 0) 3658 return; 3659 3660 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3661 } 3662 3663 /* 3664 * sip_dp83815_mii_statchg: [mii interface function] 3665 * 3666 * Callback from MII layer when media changes. 3667 */ 3668 static void 3669 sipcom_dp83815_mii_statchg(device_t self) 3670 { 3671 struct sip_softc *sc = device_private(self); 3672 3673 /* 3674 * Update TXCFG for full-duplex operation. 3675 */ 3676 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3677 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3678 else 3679 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3680 3681 /* 3682 * Update RXCFG for full-duplex or loopback. 3683 */ 3684 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3685 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3686 sc->sc_rxcfg |= RXCFG_ATX; 3687 else 3688 sc->sc_rxcfg &= ~RXCFG_ATX; 3689 3690 /* 3691 * XXX 802.3x flow control. 3692 */ 3693 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3695 sc->sc_txcfg); 3696 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3697 sc->sc_rxcfg); 3698 3699 /* 3700 * Some DP83815s experience problems when used with short 3701 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3702 * sequence adjusts the DSP's signal attenuation to fix the 3703 * problem. 3704 */ 3705 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3706 uint32_t reg; 3707 3708 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3709 3710 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3711 reg &= 0x0fff; 3712 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3713 delay(100); 3714 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3715 reg &= 0x00ff; 3716 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3717 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3718 0x00e8); 3719 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3720 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3721 reg | 0x20); 3722 } 3723 3724 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3725 } 3726 } 3727 3728 static void 3729 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3730 const struct pci_attach_args *pa, u_int8_t *enaddr) 3731 { 3732 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3733 u_int8_t cksum, *e, match; 3734 int i; 3735 3736 /* 3737 * EEPROM data format for the DP83820 can be found in 3738 * the DP83820 manual, section 4.2.4. 3739 */ 3740 3741 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3742 3743 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3744 match = ~(match - 1); 3745 3746 cksum = 0x55; 3747 e = (u_int8_t *) eeprom_data; 3748 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3749 cksum += *e++; 3750 3751 if (cksum != match) 3752 printf("%s: Checksum (%x) mismatch (%x)", 3753 sc->sc_dev.dv_xname, cksum, match); 3754 3755 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3756 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3757 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3758 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3759 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3760 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3761 } 3762 3763 static void 3764 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3765 { 3766 int i; 3767 3768 /* 3769 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3770 * a reason, but I don't know it. 3771 */ 3772 for (i = 0; i < 10; i++) 3773 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3774 } 3775 3776 static void 3777 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3778 const struct pci_attach_args *pa, u_int8_t *enaddr) 3779 { 3780 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3781 3782 switch (sc->sc_rev) { 3783 case SIS_REV_630S: 3784 case SIS_REV_630E: 3785 case SIS_REV_630EA1: 3786 case SIS_REV_630ET: 3787 case SIS_REV_635: 3788 /* 3789 * The MAC address for the on-board Ethernet of 3790 * the SiS 630 chipset is in the NVRAM. Kick 3791 * the chip into re-loading it from NVRAM, and 3792 * read the MAC address out of the filter registers. 3793 */ 3794 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3795 3796 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3797 RFCR_RFADDR_NODE0); 3798 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3799 0xffff; 3800 3801 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3802 RFCR_RFADDR_NODE2); 3803 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3804 0xffff; 3805 3806 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3807 RFCR_RFADDR_NODE4); 3808 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3809 0xffff; 3810 break; 3811 3812 case SIS_REV_960: 3813 { 3814 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3815 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3816 3817 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3818 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3819 3820 int waittime, i; 3821 3822 /* Allow to read EEPROM from LAN. It is shared 3823 * between a 1394 controller and the NIC and each 3824 * time we access it, we need to set SIS_EECMD_REQ. 3825 */ 3826 SIS_SET_EROMAR(sc, EROMAR_REQ); 3827 3828 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3829 /* Force EEPROM to idle state. */ 3830 3831 /* 3832 * XXX-cube This is ugly. I'll look for docs about it. 3833 */ 3834 SIS_SET_EROMAR(sc, EROMAR_EECS); 3835 sipcom_sis900_eeprom_delay(sc); 3836 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3837 SIS_SET_EROMAR(sc, EROMAR_EESK); 3838 sipcom_sis900_eeprom_delay(sc); 3839 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3840 sipcom_sis900_eeprom_delay(sc); 3841 } 3842 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3843 sipcom_sis900_eeprom_delay(sc); 3844 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3845 3846 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3847 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3848 sizeof(myea) / sizeof(myea[0]), myea); 3849 break; 3850 } 3851 DELAY(1); 3852 } 3853 3854 /* 3855 * Set SIS_EECTL_CLK to high, so a other master 3856 * can operate on the i2c bus. 3857 */ 3858 SIS_SET_EROMAR(sc, EROMAR_EESK); 3859 3860 /* Refuse EEPROM access by LAN */ 3861 SIS_SET_EROMAR(sc, EROMAR_DONE); 3862 } break; 3863 3864 default: 3865 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3866 sizeof(myea) / sizeof(myea[0]), myea); 3867 } 3868 3869 enaddr[0] = myea[0] & 0xff; 3870 enaddr[1] = myea[0] >> 8; 3871 enaddr[2] = myea[1] & 0xff; 3872 enaddr[3] = myea[1] >> 8; 3873 enaddr[4] = myea[2] & 0xff; 3874 enaddr[5] = myea[2] >> 8; 3875 } 3876 3877 /* Table and macro to bit-reverse an octet. */ 3878 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3879 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3880 3881 static void 3882 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3883 const struct pci_attach_args *pa, u_int8_t *enaddr) 3884 { 3885 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3886 u_int8_t cksum, *e, match; 3887 int i; 3888 3889 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3890 sizeof(eeprom_data[0]), eeprom_data); 3891 3892 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3893 match = ~(match - 1); 3894 3895 cksum = 0x55; 3896 e = (u_int8_t *) eeprom_data; 3897 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3898 cksum += *e++; 3899 } 3900 if (cksum != match) { 3901 printf("%s: Checksum (%x) mismatch (%x)", 3902 sc->sc_dev.dv_xname, cksum, match); 3903 } 3904 3905 /* 3906 * Unrolled because it makes slightly more sense this way. 3907 * The DP83815 stores the MAC address in bit 0 of word 6 3908 * through bit 15 of word 8. 3909 */ 3910 ea = &eeprom_data[6]; 3911 enaddr[0] = ((*ea & 0x1) << 7); 3912 ea++; 3913 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3914 enaddr[1] = ((*ea & 0x1FE) >> 1); 3915 enaddr[2] = ((*ea & 0x1) << 7); 3916 ea++; 3917 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3918 enaddr[3] = ((*ea & 0x1FE) >> 1); 3919 enaddr[4] = ((*ea & 0x1) << 7); 3920 ea++; 3921 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3922 enaddr[5] = ((*ea & 0x1FE) >> 1); 3923 3924 /* 3925 * In case that's not weird enough, we also need to reverse 3926 * the bits in each byte. This all actually makes more sense 3927 * if you think about the EEPROM storage as an array of bits 3928 * being shifted into bytes, but that's not how we're looking 3929 * at it here... 3930 */ 3931 for (i = 0; i < 6 ;i++) 3932 enaddr[i] = bbr(enaddr[i]); 3933 } 3934 3935 /* 3936 * sip_mediastatus: [ifmedia interface function] 3937 * 3938 * Get the current interface media status. 3939 */ 3940 static void 3941 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3942 { 3943 struct sip_softc *sc = ifp->if_softc; 3944 3945 ether_mediastatus(ifp, ifmr); 3946 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3947 sc->sc_flowflags; 3948 } 3949
Indexes created Mon Sep 22 13:09:51 GMT 2025