if_sip.c revision 1.132
1 /* $NetBSD: if_sip.c,v 1.132 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /*- 40 * Copyright (c) 1999 Network Computer, Inc. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of Network Computer, Inc. nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * Device driver for the Silicon Integrated Systems SiS 900, 70 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 71 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 72 * controllers. 73 * 74 * Originally written to support the SiS 900 by Jason R. Thorpe for 75 * Network Computer, Inc. 76 * 77 * TODO: 78 * 79 * - Reduce the Rx interrupt load. 80 */ 81 82 #include <sys/cdefs.h> 83 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.132 2008/04/10 19:13:37 cegger Exp $"); 84 85 #include "bpfilter.h" 86 #include "rnd.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/callout.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #include <sys/device.h> 98 #include <sys/queue.h> 99 100 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 101 102 #if NRND > 0 103 #include <sys/rnd.h> 104 #endif 105 106 #include <net/if.h> 107 #include <net/if_dl.h> 108 #include <net/if_media.h> 109 #include <net/if_ether.h> 110 111 #if NBPFILTER > 0 112 #include <net/bpf.h> 113 #endif 114 115 #include <sys/bus.h> 116 #include <sys/intr.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 #include <dev/mii/mii_bitbang.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 #include <dev/pci/pcidevs.h> 126 127 #include <dev/pci/if_sipreg.h> 128 129 /* 130 * Transmit descriptor list size. This is arbitrary, but allocate 131 * enough descriptors for 128 pending transmissions, and 8 segments 132 * per packet (64 for DP83820 for jumbo frames). 133 * 134 * This MUST work out to a power of 2. 135 */ 136 #define GSIP_NTXSEGS_ALLOC 16 137 #define SIP_NTXSEGS_ALLOC 8 138 139 #define SIP_TXQUEUELEN 256 140 #define MAX_SIP_NTXDESC \ 141 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 142 143 /* 144 * Receive descriptor list size. We have one Rx buffer per incoming 145 * packet, so this logic is a little simpler. 146 * 147 * Actually, on the DP83820, we allow the packet to consume more than 148 * one buffer, in order to support jumbo Ethernet frames. In that 149 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 150 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 151 * so we'd better be quick about handling receive interrupts. 152 */ 153 #define GSIP_NRXDESC 256 154 #define SIP_NRXDESC 128 155 156 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 157 158 /* 159 * Control structures are DMA'd to the SiS900 chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct sip_control_data { 164 /* 165 * The transmit descriptors. 166 */ 167 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 168 169 /* 170 * The receive descriptors. 171 */ 172 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 173 }; 174 175 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 176 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 177 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 178 179 /* 180 * Software state for transmit jobs. 181 */ 182 struct sip_txsoft { 183 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 184 bus_dmamap_t txs_dmamap; /* our DMA map */ 185 int txs_firstdesc; /* first descriptor in packet */ 186 int txs_lastdesc; /* last descriptor in packet */ 187 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 188 }; 189 190 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 191 192 /* 193 * Software state for receive jobs. 194 */ 195 struct sip_rxsoft { 196 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 197 bus_dmamap_t rxs_dmamap; /* our DMA map */ 198 }; 199 200 enum sip_attach_stage { 201 SIP_ATTACH_FIN = 0 202 , SIP_ATTACH_CREATE_RXMAP 203 , SIP_ATTACH_CREATE_TXMAP 204 , SIP_ATTACH_LOAD_MAP 205 , SIP_ATTACH_CREATE_MAP 206 , SIP_ATTACH_MAP_MEM 207 , SIP_ATTACH_ALLOC_MEM 208 , SIP_ATTACH_INTR 209 , SIP_ATTACH_MAP 210 }; 211 212 /* 213 * Software state per device. 214 */ 215 struct sip_softc { 216 struct device sc_dev; /* generic device information */ 217 bus_space_tag_t sc_st; /* bus space tag */ 218 bus_space_handle_t sc_sh; /* bus space handle */ 219 bus_size_t sc_sz; /* bus space size */ 220 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t sc_pc; 222 bus_dma_segment_t sc_seg; 223 struct ethercom sc_ethercom; /* ethernet common data */ 224 225 const struct sip_product *sc_model; /* which model are we? */ 226 int sc_gigabit; /* 1: 83820, 0: other */ 227 int sc_rev; /* chip revision */ 228 229 void *sc_ih; /* interrupt cookie */ 230 231 struct mii_data sc_mii; /* MII/media information */ 232 233 callout_t sc_tick_ch; /* tick callout */ 234 235 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 236 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 237 238 /* 239 * Software state for transmit and receive descriptors. 240 */ 241 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 242 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 243 244 /* 245 * Control data structures. 246 */ 247 struct sip_control_data *sc_control_data; 248 #define sc_txdescs sc_control_data->scd_txdescs 249 #define sc_rxdescs sc_control_data->scd_rxdescs 250 251 #ifdef SIP_EVENT_COUNTERS 252 /* 253 * Event counters. 254 */ 255 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 256 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 257 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 258 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 259 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 260 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 261 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 262 struct evcnt sc_ev_rxpause; /* PAUSE received */ 263 /* DP83820 only */ 264 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 265 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 266 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 267 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 268 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 269 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 270 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 271 #endif /* SIP_EVENT_COUNTERS */ 272 273 u_int32_t sc_txcfg; /* prototype TXCFG register */ 274 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 275 u_int32_t sc_imr; /* prototype IMR register */ 276 u_int32_t sc_rfcr; /* prototype RFCR register */ 277 278 u_int32_t sc_cfg; /* prototype CFG register */ 279 280 u_int32_t sc_gpior; /* prototype GPIOR register */ 281 282 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 283 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 284 285 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 286 287 int sc_flowflags; /* 802.3x flow control flags */ 288 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 289 int sc_paused; /* paused indication */ 290 291 int sc_txfree; /* number of free Tx descriptors */ 292 int sc_txnext; /* next ready Tx descriptor */ 293 int sc_txwin; /* Tx descriptors since last intr */ 294 295 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 296 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 297 298 /* values of interface state at last init */ 299 struct { 300 /* if_capenable */ 301 uint64_t if_capenable; 302 /* ec_capenable */ 303 int ec_capenable; 304 /* VLAN_ATTACHED */ 305 int is_vlan; 306 } sc_prev; 307 308 short sc_if_flags; 309 310 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 311 int sc_rxdiscard; 312 int sc_rxlen; 313 struct mbuf *sc_rxhead; 314 struct mbuf *sc_rxtail; 315 struct mbuf **sc_rxtailp; 316 317 int sc_ntxdesc; 318 int sc_ntxdesc_mask; 319 320 int sc_nrxdesc_mask; 321 322 const struct sip_parm { 323 const struct sip_regs { 324 int r_rxcfg; 325 int r_txcfg; 326 } p_regs; 327 328 const struct sip_bits { 329 uint32_t b_txcfg_mxdma_8; 330 uint32_t b_txcfg_mxdma_16; 331 uint32_t b_txcfg_mxdma_32; 332 uint32_t b_txcfg_mxdma_64; 333 uint32_t b_txcfg_mxdma_128; 334 uint32_t b_txcfg_mxdma_256; 335 uint32_t b_txcfg_mxdma_512; 336 uint32_t b_txcfg_flth_mask; 337 uint32_t b_txcfg_drth_mask; 338 339 uint32_t b_rxcfg_mxdma_8; 340 uint32_t b_rxcfg_mxdma_16; 341 uint32_t b_rxcfg_mxdma_32; 342 uint32_t b_rxcfg_mxdma_64; 343 uint32_t b_rxcfg_mxdma_128; 344 uint32_t b_rxcfg_mxdma_256; 345 uint32_t b_rxcfg_mxdma_512; 346 347 uint32_t b_isr_txrcmp; 348 uint32_t b_isr_rxrcmp; 349 uint32_t b_isr_dperr; 350 uint32_t b_isr_sserr; 351 uint32_t b_isr_rmabt; 352 uint32_t b_isr_rtabt; 353 354 uint32_t b_cmdsts_size_mask; 355 } p_bits; 356 int p_filtmem; 357 int p_rxbuf_len; 358 bus_size_t p_tx_dmamap_size; 359 int p_ntxsegs; 360 int p_ntxsegs_alloc; 361 int p_nrxdesc; 362 } *sc_parm; 363 364 void (*sc_rxintr)(struct sip_softc *); 365 366 #if NRND > 0 367 rndsource_element_t rnd_source; /* random source */ 368 #endif 369 }; 370 371 #define sc_bits sc_parm->p_bits 372 #define sc_regs sc_parm->p_regs 373 374 static const struct sip_parm sip_parm = { 375 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 376 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 377 , .p_tx_dmamap_size = MCLBYTES 378 , .p_ntxsegs = 16 379 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 380 , .p_nrxdesc = SIP_NRXDESC 381 , .p_bits = { 382 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 383 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 384 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 385 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 386 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 387 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 388 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 389 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 390 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 391 392 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 393 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 394 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 395 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 396 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 397 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 398 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 399 400 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 401 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 402 , .b_isr_dperr = 0x00800000 /* detected parity error */ 403 , .b_isr_sserr = 0x00400000 /* signalled system error */ 404 , .b_isr_rmabt = 0x00200000 /* received master abort */ 405 , .b_isr_rtabt = 0x00100000 /* received target abort */ 406 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 407 } 408 , .p_regs = { 409 .r_rxcfg = OTHER_SIP_RXCFG, 410 .r_txcfg = OTHER_SIP_TXCFG 411 } 412 }, gsip_parm = { 413 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 414 , .p_rxbuf_len = MCLBYTES - 8 415 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 416 , .p_ntxsegs = 64 417 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 418 , .p_nrxdesc = GSIP_NRXDESC 419 , .p_bits = { 420 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 421 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 422 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 423 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 424 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 425 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 426 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 427 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 428 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 429 430 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 431 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 432 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 433 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 434 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 435 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 436 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 437 438 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 439 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 440 , .b_isr_dperr = 0x00100000 /* detected parity error */ 441 , .b_isr_sserr = 0x00080000 /* signalled system error */ 442 , .b_isr_rmabt = 0x00040000 /* received master abort */ 443 , .b_isr_rtabt = 0x00020000 /* received target abort */ 444 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 445 } 446 , .p_regs = { 447 .r_rxcfg = DP83820_SIP_RXCFG, 448 .r_txcfg = DP83820_SIP_TXCFG 449 } 450 }; 451 452 static inline int 453 sip_nexttx(const struct sip_softc *sc, int x) 454 { 455 return (x + 1) & sc->sc_ntxdesc_mask; 456 } 457 458 static inline int 459 sip_nextrx(const struct sip_softc *sc, int x) 460 { 461 return (x + 1) & sc->sc_nrxdesc_mask; 462 } 463 464 /* 83820 only */ 465 static inline void 466 sip_rxchain_reset(struct sip_softc *sc) 467 { 468 sc->sc_rxtailp = &sc->sc_rxhead; 469 *sc->sc_rxtailp = NULL; 470 sc->sc_rxlen = 0; 471 } 472 473 /* 83820 only */ 474 static inline void 475 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 476 { 477 *sc->sc_rxtailp = sc->sc_rxtail = m; 478 sc->sc_rxtailp = &m->m_next; 479 } 480 481 #ifdef SIP_EVENT_COUNTERS 482 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 483 #else 484 #define SIP_EVCNT_INCR(ev) /* nothing */ 485 #endif 486 487 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 488 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 489 490 static inline void 491 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 492 { 493 int x, n; 494 495 x = x0; 496 n = n0; 497 498 /* If it will wrap around, sync to the end of the ring. */ 499 if (x + n > sc->sc_ntxdesc) { 500 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 501 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 502 (sc->sc_ntxdesc - x), ops); 503 n -= (sc->sc_ntxdesc - x); 504 x = 0; 505 } 506 507 /* Now sync whatever is left. */ 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 510 } 511 512 static inline void 513 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 514 { 515 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 516 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 517 } 518 519 #if 0 520 #ifdef DP83820 521 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 522 u_int32_t sipd_cmdsts; /* command/status word */ 523 #else 524 u_int32_t sipd_cmdsts; /* command/status word */ 525 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 526 #endif /* DP83820 */ 527 #endif /* 0 */ 528 529 static inline volatile uint32_t * 530 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 531 { 532 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 533 } 534 535 static inline volatile uint32_t * 536 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 537 { 538 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 539 } 540 541 static inline void 542 sip_init_rxdesc(struct sip_softc *sc, int x) 543 { 544 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 545 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 546 547 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 548 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 549 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 550 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 551 sipd->sipd_extsts = 0; 552 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 553 } 554 555 #define SIP_CHIP_VERS(sc, v, p, r) \ 556 ((sc)->sc_model->sip_vendor == (v) && \ 557 (sc)->sc_model->sip_product == (p) && \ 558 (sc)->sc_rev == (r)) 559 560 #define SIP_CHIP_MODEL(sc, v, p) \ 561 ((sc)->sc_model->sip_vendor == (v) && \ 562 (sc)->sc_model->sip_product == (p)) 563 564 #define SIP_SIS900_REV(sc, rev) \ 565 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 566 567 #define SIP_TIMEOUT 1000 568 569 static void sipcom_start(struct ifnet *); 570 static void sipcom_watchdog(struct ifnet *); 571 static int sipcom_ioctl(struct ifnet *, u_long, void *); 572 static int sipcom_init(struct ifnet *); 573 static void sipcom_stop(struct ifnet *, int); 574 575 static bool sipcom_reset(struct sip_softc *); 576 static void sipcom_rxdrain(struct sip_softc *); 577 static int sipcom_add_rxbuf(struct sip_softc *, int); 578 static void sipcom_read_eeprom(struct sip_softc *, int, int, 579 u_int16_t *); 580 static void sipcom_tick(void *); 581 582 static void sipcom_sis900_set_filter(struct sip_softc *); 583 static void sipcom_dp83815_set_filter(struct sip_softc *); 584 585 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 586 const struct pci_attach_args *, u_int8_t *); 587 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 588 static void sipcom_sis900_read_macaddr(struct sip_softc *, 589 const struct pci_attach_args *, u_int8_t *); 590 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 591 const struct pci_attach_args *, u_int8_t *); 592 593 static int sipcom_intr(void *); 594 static void sipcom_txintr(struct sip_softc *); 595 static void sip_rxintr(struct sip_softc *); 596 static void gsip_rxintr(struct sip_softc *); 597 598 static int sipcom_dp83820_mii_readreg(device_t, int, int); 599 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 600 static void sipcom_dp83820_mii_statchg(device_t); 601 602 static int sipcom_sis900_mii_readreg(device_t, int, int); 603 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 604 static void sipcom_sis900_mii_statchg(device_t); 605 606 static int sipcom_dp83815_mii_readreg(device_t, int, int); 607 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 608 static void sipcom_dp83815_mii_statchg(device_t); 609 610 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 611 612 static int sipcom_match(device_t, struct cfdata *, void *); 613 static void sipcom_attach(device_t, device_t, void *); 614 static void sipcom_do_detach(device_t, enum sip_attach_stage); 615 static int sipcom_detach(device_t, int); 616 static bool sipcom_resume(device_t PMF_FN_PROTO); 617 static bool sipcom_suspend(device_t PMF_FN_PROTO); 618 619 int gsip_copy_small = 0; 620 int sip_copy_small = 0; 621 622 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 623 sipcom_match, sipcom_attach, sipcom_detach, NULL); 624 CFATTACH_DECL(sip, sizeof(struct sip_softc), 625 sipcom_match, sipcom_attach, sipcom_detach, NULL); 626 627 /* 628 * Descriptions of the variants of the SiS900. 629 */ 630 struct sip_variant { 631 int (*sipv_mii_readreg)(device_t, int, int); 632 void (*sipv_mii_writereg)(device_t, int, int, int); 633 void (*sipv_mii_statchg)(device_t); 634 void (*sipv_set_filter)(struct sip_softc *); 635 void (*sipv_read_macaddr)(struct sip_softc *, 636 const struct pci_attach_args *, u_int8_t *); 637 }; 638 639 static u_int32_t sipcom_mii_bitbang_read(device_t); 640 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 641 642 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 643 sipcom_mii_bitbang_read, 644 sipcom_mii_bitbang_write, 645 { 646 EROMAR_MDIO, /* MII_BIT_MDO */ 647 EROMAR_MDIO, /* MII_BIT_MDI */ 648 EROMAR_MDC, /* MII_BIT_MDC */ 649 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 650 0, /* MII_BIT_DIR_PHY_HOST */ 651 } 652 }; 653 654 static const struct sip_variant sipcom_variant_dp83820 = { 655 sipcom_dp83820_mii_readreg, 656 sipcom_dp83820_mii_writereg, 657 sipcom_dp83820_mii_statchg, 658 sipcom_dp83815_set_filter, 659 sipcom_dp83820_read_macaddr, 660 }; 661 662 static const struct sip_variant sipcom_variant_sis900 = { 663 sipcom_sis900_mii_readreg, 664 sipcom_sis900_mii_writereg, 665 sipcom_sis900_mii_statchg, 666 sipcom_sis900_set_filter, 667 sipcom_sis900_read_macaddr, 668 }; 669 670 static const struct sip_variant sipcom_variant_dp83815 = { 671 sipcom_dp83815_mii_readreg, 672 sipcom_dp83815_mii_writereg, 673 sipcom_dp83815_mii_statchg, 674 sipcom_dp83815_set_filter, 675 sipcom_dp83815_read_macaddr, 676 }; 677 678 679 /* 680 * Devices supported by this driver. 681 */ 682 static const struct sip_product { 683 pci_vendor_id_t sip_vendor; 684 pci_product_id_t sip_product; 685 const char *sip_name; 686 const struct sip_variant *sip_variant; 687 int sip_gigabit; 688 } sipcom_products[] = { 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 690 "NatSemi DP83820 Gigabit Ethernet", 691 &sipcom_variant_dp83820, 1 }, 692 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 693 "SiS 900 10/100 Ethernet", 694 &sipcom_variant_sis900, 0 }, 695 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 696 "SiS 7016 10/100 Ethernet", 697 &sipcom_variant_sis900, 0 }, 698 699 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 700 "NatSemi DP83815 10/100 Ethernet", 701 &sipcom_variant_dp83815, 0 }, 702 703 { 0, 0, 704 NULL, 705 NULL, 0 }, 706 }; 707 708 static const struct sip_product * 709 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 710 { 711 const struct sip_product *sip; 712 713 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 714 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 715 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 716 sip->sip_gigabit == gigabit) 717 return sip; 718 } 719 return NULL; 720 } 721 722 /* 723 * I really hate stupid hardware vendors. There's a bit in the EEPROM 724 * which indicates if the card can do 64-bit data transfers. Unfortunately, 725 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 726 * which means we try to use 64-bit data transfers on those cards if we 727 * happen to be plugged into a 32-bit slot. 728 * 729 * What we do is use this table of cards known to be 64-bit cards. If 730 * you have a 64-bit card who's subsystem ID is not listed in this table, 731 * send the output of "pcictl dump ..." of the device to me so that your 732 * card will use the 64-bit data path when plugged into a 64-bit slot. 733 * 734 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 735 * June 30, 2002 736 */ 737 static int 738 sipcom_check_64bit(const struct pci_attach_args *pa) 739 { 740 static const struct { 741 pci_vendor_id_t c64_vendor; 742 pci_product_id_t c64_product; 743 } card64[] = { 744 /* Asante GigaNIX */ 745 { 0x128a, 0x0002 }, 746 747 /* Accton EN1407-T, Planex GN-1000TE */ 748 { 0x1113, 0x1407 }, 749 750 /* Netgear GA-621 */ 751 { 0x1385, 0x621a }, 752 753 /* SMC EZ Card */ 754 { 0x10b8, 0x9462 }, 755 756 { 0, 0} 757 }; 758 pcireg_t subsys; 759 int i; 760 761 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 762 763 for (i = 0; card64[i].c64_vendor != 0; i++) { 764 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 765 PCI_PRODUCT(subsys) == card64[i].c64_product) 766 return (1); 767 } 768 769 return (0); 770 } 771 772 static int 773 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 774 { 775 struct pci_attach_args *pa = aux; 776 777 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 778 return 1; 779 780 return 0; 781 } 782 783 static void 784 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 785 { 786 u_int32_t reg; 787 int i; 788 789 /* 790 * Cause the chip to load configuration data from the EEPROM. 791 */ 792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 793 for (i = 0; i < 10000; i++) { 794 delay(10); 795 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 796 PTSCR_EELOAD_EN) == 0) 797 break; 798 } 799 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 800 PTSCR_EELOAD_EN) { 801 printf("%s: timeout loading configuration from EEPROM\n", 802 device_xname(&sc->sc_dev)); 803 return; 804 } 805 806 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 807 808 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 809 if (reg & CFG_PCI64_DET) { 810 printf("%s: 64-bit PCI slot detected", device_xname(&sc->sc_dev)); 811 /* 812 * Check to see if this card is 64-bit. If so, enable 64-bit 813 * data transfers. 814 * 815 * We can't use the DATA64_EN bit in the EEPROM, because 816 * vendors of 32-bit cards fail to clear that bit in many 817 * cases (yet the card still detects that it's in a 64-bit 818 * slot; go figure). 819 */ 820 if (sipcom_check_64bit(pa)) { 821 sc->sc_cfg |= CFG_DATA64_EN; 822 printf(", using 64-bit data transfers"); 823 } 824 printf("\n"); 825 } 826 827 /* 828 * XXX Need some PCI flags indicating support for 829 * XXX 64-bit addressing. 830 */ 831 #if 0 832 if (reg & CFG_M64ADDR) 833 sc->sc_cfg |= CFG_M64ADDR; 834 if (reg & CFG_T64ADDR) 835 sc->sc_cfg |= CFG_T64ADDR; 836 #endif 837 838 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 839 const char *sep = ""; 840 printf("%s: using ", device_xname(&sc->sc_dev)); 841 if (reg & CFG_EXT_125) { 842 sc->sc_cfg |= CFG_EXT_125; 843 printf("%s125MHz clock", sep); 844 sep = ", "; 845 } 846 if (reg & CFG_TBI_EN) { 847 sc->sc_cfg |= CFG_TBI_EN; 848 printf("%sten-bit interface", sep); 849 sep = ", "; 850 } 851 printf("\n"); 852 } 853 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 854 (reg & CFG_MRM_DIS) != 0) 855 sc->sc_cfg |= CFG_MRM_DIS; 856 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 857 (reg & CFG_MWI_DIS) != 0) 858 sc->sc_cfg |= CFG_MWI_DIS; 859 860 /* 861 * Use the extended descriptor format on the DP83820. This 862 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 863 * checksumming. 864 */ 865 sc->sc_cfg |= CFG_EXTSTS_EN; 866 } 867 868 static int 869 sipcom_detach(device_t self, int flags) 870 { 871 int s; 872 873 s = splnet(); 874 sipcom_do_detach(self, SIP_ATTACH_FIN); 875 splx(s); 876 877 return 0; 878 } 879 880 static void 881 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 882 { 883 int i; 884 struct sip_softc *sc = device_private(self); 885 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 886 887 /* 888 * Free any resources we've allocated during attach. 889 * Do this in reverse order and fall through. 890 */ 891 switch (stage) { 892 case SIP_ATTACH_FIN: 893 sipcom_stop(ifp, 1); 894 pmf_device_deregister(self); 895 #ifdef SIP_EVENT_COUNTERS 896 /* 897 * Attach event counters. 898 */ 899 evcnt_detach(&sc->sc_ev_txforceintr); 900 evcnt_detach(&sc->sc_ev_txdstall); 901 evcnt_detach(&sc->sc_ev_txsstall); 902 evcnt_detach(&sc->sc_ev_hiberr); 903 evcnt_detach(&sc->sc_ev_rxintr); 904 evcnt_detach(&sc->sc_ev_txiintr); 905 evcnt_detach(&sc->sc_ev_txdintr); 906 if (!sc->sc_gigabit) { 907 evcnt_detach(&sc->sc_ev_rxpause); 908 } else { 909 evcnt_detach(&sc->sc_ev_txudpsum); 910 evcnt_detach(&sc->sc_ev_txtcpsum); 911 evcnt_detach(&sc->sc_ev_txipsum); 912 evcnt_detach(&sc->sc_ev_rxudpsum); 913 evcnt_detach(&sc->sc_ev_rxtcpsum); 914 evcnt_detach(&sc->sc_ev_rxipsum); 915 evcnt_detach(&sc->sc_ev_txpause); 916 evcnt_detach(&sc->sc_ev_rxpause); 917 } 918 #endif /* SIP_EVENT_COUNTERS */ 919 920 #if NRND > 0 921 rnd_detach_source(&sc->rnd_source); 922 #endif 923 924 ether_ifdetach(ifp); 925 if_detach(ifp); 926 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 927 928 /*FALLTHROUGH*/ 929 case SIP_ATTACH_CREATE_RXMAP: 930 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 931 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 932 bus_dmamap_destroy(sc->sc_dmat, 933 sc->sc_rxsoft[i].rxs_dmamap); 934 } 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_CREATE_TXMAP: 937 for (i = 0; i < SIP_TXQUEUELEN; i++) { 938 if (sc->sc_txsoft[i].txs_dmamap != NULL) 939 bus_dmamap_destroy(sc->sc_dmat, 940 sc->sc_txsoft[i].txs_dmamap); 941 } 942 /*FALLTHROUGH*/ 943 case SIP_ATTACH_LOAD_MAP: 944 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 945 /*FALLTHROUGH*/ 946 case SIP_ATTACH_CREATE_MAP: 947 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_MAP_MEM: 950 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 951 sizeof(struct sip_control_data)); 952 /*FALLTHROUGH*/ 953 case SIP_ATTACH_ALLOC_MEM: 954 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 955 /* FALLTHROUGH*/ 956 case SIP_ATTACH_INTR: 957 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 958 /* FALLTHROUGH*/ 959 case SIP_ATTACH_MAP: 960 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 961 break; 962 default: 963 break; 964 } 965 return; 966 } 967 968 static bool 969 sipcom_resume(device_t self PMF_FN_ARGS) 970 { 971 struct sip_softc *sc = device_private(self); 972 973 return sipcom_reset(sc); 974 } 975 976 static bool 977 sipcom_suspend(device_t self PMF_FN_ARGS) 978 { 979 struct sip_softc *sc = device_private(self); 980 981 sipcom_rxdrain(sc); 982 return true; 983 } 984 985 static void 986 sipcom_attach(device_t parent, device_t self, void *aux) 987 { 988 struct sip_softc *sc = device_private(self); 989 struct pci_attach_args *pa = aux; 990 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 991 pci_chipset_tag_t pc = pa->pa_pc; 992 pci_intr_handle_t ih; 993 const char *intrstr = NULL; 994 bus_space_tag_t iot, memt; 995 bus_space_handle_t ioh, memh; 996 bus_size_t iosz, memsz; 997 int ioh_valid, memh_valid; 998 int i, rseg, error; 999 const struct sip_product *sip; 1000 u_int8_t enaddr[ETHER_ADDR_LEN]; 1001 pcireg_t pmreg; 1002 pcireg_t memtype; 1003 bus_size_t tx_dmamap_size; 1004 int ntxsegs_alloc; 1005 cfdata_t cf = device_cfdata(self); 1006 1007 callout_init(&sc->sc_tick_ch, 0); 1008 1009 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1010 if (sip == NULL) { 1011 printf("\n"); 1012 panic("%s: impossible", __func__); 1013 } 1014 sc->sc_gigabit = sip->sip_gigabit; 1015 1016 sc->sc_pc = pc; 1017 1018 if (sc->sc_gigabit) { 1019 sc->sc_rxintr = gsip_rxintr; 1020 sc->sc_parm = &gsip_parm; 1021 } else { 1022 sc->sc_rxintr = sip_rxintr; 1023 sc->sc_parm = &sip_parm; 1024 } 1025 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1026 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1027 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1028 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1029 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1030 1031 sc->sc_rev = PCI_REVISION(pa->pa_class); 1032 1033 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1034 1035 sc->sc_model = sip; 1036 1037 /* 1038 * XXX Work-around broken PXE firmware on some boards. 1039 * 1040 * The DP83815 shares an address decoder with the MEM BAR 1041 * and the ROM BAR. Make sure the ROM BAR is disabled, 1042 * so that memory mapped access works. 1043 */ 1044 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1045 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1046 ~PCI_MAPREG_ROM_ENABLE); 1047 1048 /* 1049 * Map the device. 1050 */ 1051 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1052 PCI_MAPREG_TYPE_IO, 0, 1053 &iot, &ioh, NULL, &iosz) == 0); 1054 if (sc->sc_gigabit) { 1055 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1056 switch (memtype) { 1057 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1058 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1061 break; 1062 default: 1063 memh_valid = 0; 1064 } 1065 } else { 1066 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1067 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1068 &memt, &memh, NULL, &memsz) == 0); 1069 } 1070 1071 if (memh_valid) { 1072 sc->sc_st = memt; 1073 sc->sc_sh = memh; 1074 sc->sc_sz = memsz; 1075 } else if (ioh_valid) { 1076 sc->sc_st = iot; 1077 sc->sc_sh = ioh; 1078 sc->sc_sz = iosz; 1079 } else { 1080 printf("%s: unable to map device registers\n", 1081 device_xname(&sc->sc_dev)); 1082 return; 1083 } 1084 1085 sc->sc_dmat = pa->pa_dmat; 1086 1087 /* 1088 * Make sure bus mastering is enabled. Also make sure 1089 * Write/Invalidate is enabled if we're allowed to use it. 1090 */ 1091 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1092 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1093 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1094 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1095 pmreg | PCI_COMMAND_MASTER_ENABLE); 1096 1097 /* power up chip */ 1098 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 1099 error != EOPNOTSUPP) { 1100 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 1101 error); 1102 return; 1103 } 1104 1105 /* 1106 * Map and establish our interrupt. 1107 */ 1108 if (pci_intr_map(pa, &ih)) { 1109 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 1110 return; 1111 } 1112 intrstr = pci_intr_string(pc, ih); 1113 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1114 if (sc->sc_ih == NULL) { 1115 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 1116 if (intrstr != NULL) 1117 printf(" at %s", intrstr); 1118 printf("\n"); 1119 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1120 } 1121 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1122 1123 SIMPLEQ_INIT(&sc->sc_txfreeq); 1124 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1125 1126 /* 1127 * Allocate the control data structures, and create and load the 1128 * DMA map for it. 1129 */ 1130 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1131 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1132 &rseg, 0)) != 0) { 1133 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1134 error); 1135 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1136 } 1137 1138 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1139 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1140 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1141 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1142 error); 1143 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1144 } 1145 1146 if ((error = bus_dmamap_create(sc->sc_dmat, 1147 sizeof(struct sip_control_data), 1, 1148 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1149 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1150 "error = %d\n", error); 1151 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1152 } 1153 1154 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1155 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1156 0)) != 0) { 1157 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1158 error); 1159 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1160 } 1161 1162 /* 1163 * Create the transmit buffer DMA maps. 1164 */ 1165 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1166 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1167 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1168 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1169 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 1170 "error = %d\n", i, error); 1171 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1172 } 1173 } 1174 1175 /* 1176 * Create the receive buffer DMA maps. 1177 */ 1178 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1180 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1181 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 1182 "error = %d\n", i, error); 1183 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1184 } 1185 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1186 } 1187 1188 /* 1189 * Reset the chip to a known state. 1190 */ 1191 sipcom_reset(sc); 1192 1193 /* 1194 * Read the Ethernet address from the EEPROM. This might 1195 * also fetch other stuff from the EEPROM and stash it 1196 * in the softc. 1197 */ 1198 sc->sc_cfg = 0; 1199 if (!sc->sc_gigabit) { 1200 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1201 SIP_SIS900_REV(sc,SIS_REV_900B)) 1202 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1203 1204 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1205 SIP_SIS900_REV(sc,SIS_REV_960) || 1206 SIP_SIS900_REV(sc,SIS_REV_900B)) 1207 sc->sc_cfg |= 1208 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1209 CFG_EDBMASTEN); 1210 } 1211 1212 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1213 1214 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 1215 ether_sprintf(enaddr)); 1216 1217 /* 1218 * Initialize the configuration register: aggressive PCI 1219 * bus request algorithm, default backoff, default OW timer, 1220 * default parity error detection. 1221 * 1222 * NOTE: "Big endian mode" is useless on the SiS900 and 1223 * friends -- it affects packet data, not descriptors. 1224 */ 1225 if (sc->sc_gigabit) 1226 sipcom_dp83820_attach(sc, pa); 1227 1228 /* 1229 * Initialize our media structures and probe the MII. 1230 */ 1231 sc->sc_mii.mii_ifp = ifp; 1232 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1233 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1234 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1235 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1236 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1237 sipcom_mediastatus); 1238 1239 /* 1240 * XXX We cannot handle flow control on the DP83815. 1241 */ 1242 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1243 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1244 MII_OFFSET_ANY, 0); 1245 else 1246 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1247 MII_OFFSET_ANY, MIIF_DOPAUSE); 1248 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1249 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1250 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1251 } else 1252 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1253 1254 ifp = &sc->sc_ethercom.ec_if; 1255 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1256 ifp->if_softc = sc; 1257 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1258 sc->sc_if_flags = ifp->if_flags; 1259 ifp->if_ioctl = sipcom_ioctl; 1260 ifp->if_start = sipcom_start; 1261 ifp->if_watchdog = sipcom_watchdog; 1262 ifp->if_init = sipcom_init; 1263 ifp->if_stop = sipcom_stop; 1264 IFQ_SET_READY(&ifp->if_snd); 1265 1266 /* 1267 * We can support 802.1Q VLAN-sized frames. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1270 1271 if (sc->sc_gigabit) { 1272 /* 1273 * And the DP83820 can do VLAN tagging in hardware, and 1274 * support the jumbo Ethernet MTU. 1275 */ 1276 sc->sc_ethercom.ec_capabilities |= 1277 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1278 1279 /* 1280 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1281 * in hardware. 1282 */ 1283 ifp->if_capabilities |= 1284 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1285 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1286 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1287 } 1288 1289 /* 1290 * Attach the interface. 1291 */ 1292 if_attach(ifp); 1293 ether_ifattach(ifp, enaddr); 1294 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1295 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1296 sc->sc_prev.if_capenable = ifp->if_capenable; 1297 #if NRND > 0 1298 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 1299 RND_TYPE_NET, 0); 1300 #endif 1301 1302 /* 1303 * The number of bytes that must be available in 1304 * the Tx FIFO before the bus master can DMA more 1305 * data into the FIFO. 1306 */ 1307 sc->sc_tx_fill_thresh = 64 / 32; 1308 1309 /* 1310 * Start at a drain threshold of 512 bytes. We will 1311 * increase it if a DMA underrun occurs. 1312 * 1313 * XXX The minimum value of this variable should be 1314 * tuned. We may be able to improve performance 1315 * by starting with a lower value. That, however, 1316 * may trash the first few outgoing packets if the 1317 * PCI bus is saturated. 1318 */ 1319 if (sc->sc_gigabit) 1320 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1321 else 1322 sc->sc_tx_drain_thresh = 1504 / 32; 1323 1324 /* 1325 * Initialize the Rx FIFO drain threshold. 1326 * 1327 * This is in units of 8 bytes. 1328 * 1329 * We should never set this value lower than 2; 14 bytes are 1330 * required to filter the packet. 1331 */ 1332 sc->sc_rx_drain_thresh = 128 / 8; 1333 1334 #ifdef SIP_EVENT_COUNTERS 1335 /* 1336 * Attach event counters. 1337 */ 1338 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1339 NULL, device_xname(&sc->sc_dev), "txsstall"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1341 NULL, device_xname(&sc->sc_dev), "txdstall"); 1342 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(&sc->sc_dev), "txforceintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(&sc->sc_dev), "txdintr"); 1346 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1347 NULL, device_xname(&sc->sc_dev), "txiintr"); 1348 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1349 NULL, device_xname(&sc->sc_dev), "rxintr"); 1350 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1351 NULL, device_xname(&sc->sc_dev), "hiberr"); 1352 if (!sc->sc_gigabit) { 1353 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1354 NULL, device_xname(&sc->sc_dev), "rxpause"); 1355 } else { 1356 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1357 NULL, device_xname(&sc->sc_dev), "rxpause"); 1358 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1359 NULL, device_xname(&sc->sc_dev), "txpause"); 1360 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(&sc->sc_dev), "rxipsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 1366 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1367 NULL, device_xname(&sc->sc_dev), "txipsum"); 1368 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1369 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 1370 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1371 NULL, device_xname(&sc->sc_dev), "txudpsum"); 1372 } 1373 #endif /* SIP_EVENT_COUNTERS */ 1374 1375 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1376 aprint_error_dev(self, "couldn't establish power handler\n"); 1377 else 1378 pmf_class_network_register(self, ifp); 1379 } 1380 1381 static inline void 1382 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1383 uint64_t capenable) 1384 { 1385 struct m_tag *mtag; 1386 u_int32_t extsts; 1387 #ifdef DEBUG 1388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1389 #endif 1390 /* 1391 * If VLANs are enabled and the packet has a VLAN tag, set 1392 * up the descriptor to encapsulate the packet for us. 1393 * 1394 * This apparently has to be on the last descriptor of 1395 * the packet. 1396 */ 1397 1398 /* 1399 * Byte swapping is tricky. We need to provide the tag 1400 * in a network byte order. On a big-endian machine, 1401 * the byteorder is correct, but we need to swap it 1402 * anyway, because this will be undone by the outside 1403 * htole32(). That's why there must be an 1404 * unconditional swap instead of htons() inside. 1405 */ 1406 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1407 sc->sc_txdescs[lasttx].sipd_extsts |= 1408 htole32(EXTSTS_VPKT | 1409 (bswap16(VLAN_TAG_VALUE(mtag)) & 1410 EXTSTS_VTCI)); 1411 } 1412 1413 /* 1414 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1415 * checksumming, set up the descriptor to do this work 1416 * for us. 1417 * 1418 * This apparently has to be on the first descriptor of 1419 * the packet. 1420 * 1421 * Byte-swap constants so the compiler can optimize. 1422 */ 1423 extsts = 0; 1424 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1425 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1426 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1427 extsts |= htole32(EXTSTS_IPPKT); 1428 } 1429 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1430 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1431 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1432 extsts |= htole32(EXTSTS_TCPPKT); 1433 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1434 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1435 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1436 extsts |= htole32(EXTSTS_UDPPKT); 1437 } 1438 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1439 } 1440 1441 /* 1442 * sip_start: [ifnet interface function] 1443 * 1444 * Start packet transmission on the interface. 1445 */ 1446 static void 1447 sipcom_start(struct ifnet *ifp) 1448 { 1449 struct sip_softc *sc = ifp->if_softc; 1450 struct mbuf *m0; 1451 struct mbuf *m; 1452 struct sip_txsoft *txs; 1453 bus_dmamap_t dmamap; 1454 int error, nexttx, lasttx, seg; 1455 int ofree = sc->sc_txfree; 1456 #if 0 1457 int firsttx = sc->sc_txnext; 1458 #endif 1459 1460 /* 1461 * If we've been told to pause, don't transmit any more packets. 1462 */ 1463 if (!sc->sc_gigabit && sc->sc_paused) 1464 ifp->if_flags |= IFF_OACTIVE; 1465 1466 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1467 return; 1468 1469 /* 1470 * Loop through the send queue, setting up transmit descriptors 1471 * until we drain the queue, or use up all available transmit 1472 * descriptors. 1473 */ 1474 for (;;) { 1475 /* Get a work queue entry. */ 1476 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1477 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1478 break; 1479 } 1480 1481 /* 1482 * Grab a packet off the queue. 1483 */ 1484 IFQ_POLL(&ifp->if_snd, m0); 1485 if (m0 == NULL) 1486 break; 1487 m = NULL; 1488 1489 dmamap = txs->txs_dmamap; 1490 1491 /* 1492 * Load the DMA map. If this fails, the packet either 1493 * didn't fit in the alloted number of segments, or we 1494 * were short on resources. 1495 */ 1496 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1497 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1498 /* In the non-gigabit case, we'll copy and try again. */ 1499 if (error != 0 && !sc->sc_gigabit) { 1500 MGETHDR(m, M_DONTWAIT, MT_DATA); 1501 if (m == NULL) { 1502 printf("%s: unable to allocate Tx mbuf\n", 1503 device_xname(&sc->sc_dev)); 1504 break; 1505 } 1506 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1507 if (m0->m_pkthdr.len > MHLEN) { 1508 MCLGET(m, M_DONTWAIT); 1509 if ((m->m_flags & M_EXT) == 0) { 1510 printf("%s: unable to allocate Tx " 1511 "cluster\n", device_xname(&sc->sc_dev)); 1512 m_freem(m); 1513 break; 1514 } 1515 } 1516 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1517 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1518 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1519 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1520 if (error) { 1521 printf("%s: unable to load Tx buffer, " 1522 "error = %d\n", device_xname(&sc->sc_dev), error); 1523 break; 1524 } 1525 } else if (error == EFBIG) { 1526 /* 1527 * For the too-many-segments case, we simply 1528 * report an error and drop the packet, 1529 * since we can't sanely copy a jumbo packet 1530 * to a single buffer. 1531 */ 1532 printf("%s: Tx packet consumes too many " 1533 "DMA segments, dropping...\n", device_xname(&sc->sc_dev)); 1534 IFQ_DEQUEUE(&ifp->if_snd, m0); 1535 m_freem(m0); 1536 continue; 1537 } else if (error != 0) { 1538 /* 1539 * Short on resources, just stop for now. 1540 */ 1541 break; 1542 } 1543 1544 /* 1545 * Ensure we have enough descriptors free to describe 1546 * the packet. Note, we always reserve one descriptor 1547 * at the end of the ring as a termination point, to 1548 * prevent wrap-around. 1549 */ 1550 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1551 /* 1552 * Not enough free descriptors to transmit this 1553 * packet. We haven't committed anything yet, 1554 * so just unload the DMA map, put the packet 1555 * back on the queue, and punt. Notify the upper 1556 * layer that there are not more slots left. 1557 * 1558 * XXX We could allocate an mbuf and copy, but 1559 * XXX is it worth it? 1560 */ 1561 ifp->if_flags |= IFF_OACTIVE; 1562 bus_dmamap_unload(sc->sc_dmat, dmamap); 1563 if (m != NULL) 1564 m_freem(m); 1565 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1566 break; 1567 } 1568 1569 IFQ_DEQUEUE(&ifp->if_snd, m0); 1570 if (m != NULL) { 1571 m_freem(m0); 1572 m0 = m; 1573 } 1574 1575 /* 1576 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1577 */ 1578 1579 /* Sync the DMA map. */ 1580 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1581 BUS_DMASYNC_PREWRITE); 1582 1583 /* 1584 * Initialize the transmit descriptors. 1585 */ 1586 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1587 seg < dmamap->dm_nsegs; 1588 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1589 /* 1590 * If this is the first descriptor we're 1591 * enqueueing, don't set the OWN bit just 1592 * yet. That could cause a race condition. 1593 * We'll do it below. 1594 */ 1595 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1596 htole32(dmamap->dm_segs[seg].ds_addr); 1597 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1598 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1599 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1600 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1601 lasttx = nexttx; 1602 } 1603 1604 /* Clear the MORE bit on the last segment. */ 1605 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1606 htole32(~CMDSTS_MORE); 1607 1608 /* 1609 * If we're in the interrupt delay window, delay the 1610 * interrupt. 1611 */ 1612 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1613 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1614 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1615 htole32(CMDSTS_INTR); 1616 sc->sc_txwin = 0; 1617 } 1618 1619 if (sc->sc_gigabit) 1620 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1621 1622 /* Sync the descriptors we're using. */ 1623 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1624 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1625 1626 /* 1627 * The entire packet is set up. Give the first descrptor 1628 * to the chip now. 1629 */ 1630 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1631 htole32(CMDSTS_OWN); 1632 sip_cdtxsync(sc, sc->sc_txnext, 1, 1633 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1634 1635 /* 1636 * Store a pointer to the packet so we can free it later, 1637 * and remember what txdirty will be once the packet is 1638 * done. 1639 */ 1640 txs->txs_mbuf = m0; 1641 txs->txs_firstdesc = sc->sc_txnext; 1642 txs->txs_lastdesc = lasttx; 1643 1644 /* Advance the tx pointer. */ 1645 sc->sc_txfree -= dmamap->dm_nsegs; 1646 sc->sc_txnext = nexttx; 1647 1648 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1649 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1650 1651 #if NBPFILTER > 0 1652 /* 1653 * Pass the packet to any BPF listeners. 1654 */ 1655 if (ifp->if_bpf) 1656 bpf_mtap(ifp->if_bpf, m0); 1657 #endif /* NBPFILTER > 0 */ 1658 } 1659 1660 if (txs == NULL || sc->sc_txfree == 0) { 1661 /* No more slots left; notify upper layer. */ 1662 ifp->if_flags |= IFF_OACTIVE; 1663 } 1664 1665 if (sc->sc_txfree != ofree) { 1666 /* 1667 * Start the transmit process. Note, the manual says 1668 * that if there are no pending transmissions in the 1669 * chip's internal queue (indicated by TXE being clear), 1670 * then the driver software must set the TXDP to the 1671 * first descriptor to be transmitted. However, if we 1672 * do this, it causes serious performance degredation on 1673 * the DP83820 under load, not setting TXDP doesn't seem 1674 * to adversely affect the SiS 900 or DP83815. 1675 * 1676 * Well, I guess it wouldn't be the first time a manual 1677 * has lied -- and they could be speaking of the NULL- 1678 * terminated descriptor list case, rather than OWN- 1679 * terminated rings. 1680 */ 1681 #if 0 1682 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1683 CR_TXE) == 0) { 1684 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1685 SIP_CDTXADDR(sc, firsttx)); 1686 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1687 } 1688 #else 1689 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1690 #endif 1691 1692 /* Set a watchdog timer in case the chip flakes out. */ 1693 /* Gigabit autonegotiation takes 5 seconds. */ 1694 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1695 } 1696 } 1697 1698 /* 1699 * sip_watchdog: [ifnet interface function] 1700 * 1701 * Watchdog timer handler. 1702 */ 1703 static void 1704 sipcom_watchdog(struct ifnet *ifp) 1705 { 1706 struct sip_softc *sc = ifp->if_softc; 1707 1708 /* 1709 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1710 * If we get a timeout, try and sweep up transmit descriptors. 1711 * If we manage to sweep them all up, ignore the lack of 1712 * interrupt. 1713 */ 1714 sipcom_txintr(sc); 1715 1716 if (sc->sc_txfree != sc->sc_ntxdesc) { 1717 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1718 ifp->if_oerrors++; 1719 1720 /* Reset the interface. */ 1721 (void) sipcom_init(ifp); 1722 } else if (ifp->if_flags & IFF_DEBUG) 1723 printf("%s: recovered from device timeout\n", 1724 device_xname(&sc->sc_dev)); 1725 1726 /* Try to get more packets going. */ 1727 sipcom_start(ifp); 1728 } 1729 1730 /* 1731 * sip_ioctl: [ifnet interface function] 1732 * 1733 * Handle control requests from the operator. 1734 */ 1735 static int 1736 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1737 { 1738 struct sip_softc *sc = ifp->if_softc; 1739 struct ifreq *ifr = (struct ifreq *)data; 1740 int s, error; 1741 1742 s = splnet(); 1743 1744 switch (cmd) { 1745 case SIOCSIFMEDIA: 1746 /* Flow control requires full-duplex mode. */ 1747 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1748 (ifr->ifr_media & IFM_FDX) == 0) 1749 ifr->ifr_media &= ~IFM_ETH_FMASK; 1750 1751 /* XXX */ 1752 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1753 ifr->ifr_media &= ~IFM_ETH_FMASK; 1754 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1755 if (sc->sc_gigabit && 1756 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1757 /* We can do both TXPAUSE and RXPAUSE. */ 1758 ifr->ifr_media |= 1759 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1760 } else if (ifr->ifr_media & IFM_FLOW) { 1761 /* 1762 * Both TXPAUSE and RXPAUSE must be set. 1763 * (SiS900 and DP83815 don't have PAUSE_ASYM 1764 * feature.) 1765 * 1766 * XXX Can SiS900 and DP83815 send PAUSE? 1767 */ 1768 ifr->ifr_media |= 1769 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1770 } 1771 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1772 } 1773 goto ethioctl; 1774 case SIOCSIFFLAGS: 1775 /* If the interface is up and running, only modify the receive 1776 * filter when setting promiscuous or debug mode. Otherwise 1777 * fall through to ether_ioctl, which will reset the chip. 1778 */ 1779 1780 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1781 == (sc)->sc_ethercom.ec_capenable) \ 1782 && ((sc)->sc_prev.is_vlan == \ 1783 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1784 1785 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1786 1787 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1788 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1789 == (IFF_UP|IFF_RUNNING)) 1790 && ((ifp->if_flags & (~RESETIGN)) 1791 == (sc->sc_if_flags & (~RESETIGN))) 1792 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1793 /* Set up the receive filter. */ 1794 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1795 error = 0; 1796 break; 1797 #undef RESETIGN 1798 } 1799 /* FALLTHROUGH */ 1800 ethioctl: 1801 default: 1802 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1803 break; 1804 1805 error = 0; 1806 1807 if (cmd == SIOCSIFCAP) 1808 error = (*ifp->if_init)(ifp); 1809 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1810 ; 1811 else if (ifp->if_flags & IFF_RUNNING) { 1812 /* 1813 * Multicast list has changed; set the hardware filter 1814 * accordingly. 1815 */ 1816 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1817 } 1818 break; 1819 } 1820 1821 /* Try to get more packets going. */ 1822 sipcom_start(ifp); 1823 1824 sc->sc_if_flags = ifp->if_flags; 1825 splx(s); 1826 return (error); 1827 } 1828 1829 /* 1830 * sip_intr: 1831 * 1832 * Interrupt service routine. 1833 */ 1834 static int 1835 sipcom_intr(void *arg) 1836 { 1837 struct sip_softc *sc = arg; 1838 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1839 u_int32_t isr; 1840 int handled = 0; 1841 1842 /* Disable interrupts. */ 1843 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1844 1845 for (;;) { 1846 /* Reading clears interrupt. */ 1847 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1848 if ((isr & sc->sc_imr) == 0) 1849 break; 1850 1851 #if NRND > 0 1852 if (RND_ENABLED(&sc->rnd_source)) 1853 rnd_add_uint32(&sc->rnd_source, isr); 1854 #endif 1855 1856 handled = 1; 1857 1858 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1859 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1860 1861 /* Grab any new packets. */ 1862 (*sc->sc_rxintr)(sc); 1863 1864 if (isr & ISR_RXORN) { 1865 printf("%s: receive FIFO overrun\n", 1866 device_xname(&sc->sc_dev)); 1867 1868 /* XXX adjust rx_drain_thresh? */ 1869 } 1870 1871 if (isr & ISR_RXIDLE) { 1872 printf("%s: receive ring overrun\n", 1873 device_xname(&sc->sc_dev)); 1874 1875 /* Get the receive process going again. */ 1876 bus_space_write_4(sc->sc_st, sc->sc_sh, 1877 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1878 bus_space_write_4(sc->sc_st, sc->sc_sh, 1879 SIP_CR, CR_RXE); 1880 } 1881 } 1882 1883 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1884 #ifdef SIP_EVENT_COUNTERS 1885 if (isr & ISR_TXDESC) 1886 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1887 else if (isr & ISR_TXIDLE) 1888 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1889 #endif 1890 1891 /* Sweep up transmit descriptors. */ 1892 sipcom_txintr(sc); 1893 1894 if (isr & ISR_TXURN) { 1895 u_int32_t thresh; 1896 int txfifo_size = (sc->sc_gigabit) 1897 ? DP83820_SIP_TXFIFO_SIZE 1898 : OTHER_SIP_TXFIFO_SIZE; 1899 1900 printf("%s: transmit FIFO underrun", 1901 device_xname(&sc->sc_dev)); 1902 thresh = sc->sc_tx_drain_thresh + 1; 1903 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1904 && (thresh * 32) <= (txfifo_size - 1905 (sc->sc_tx_fill_thresh * 32))) { 1906 printf("; increasing Tx drain " 1907 "threshold to %u bytes\n", 1908 thresh * 32); 1909 sc->sc_tx_drain_thresh = thresh; 1910 (void) sipcom_init(ifp); 1911 } else { 1912 (void) sipcom_init(ifp); 1913 printf("\n"); 1914 } 1915 } 1916 } 1917 1918 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1919 if (isr & ISR_PAUSE_ST) { 1920 sc->sc_paused = 1; 1921 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1922 ifp->if_flags |= IFF_OACTIVE; 1923 } 1924 if (isr & ISR_PAUSE_END) { 1925 sc->sc_paused = 0; 1926 ifp->if_flags &= ~IFF_OACTIVE; 1927 } 1928 } 1929 1930 if (isr & ISR_HIBERR) { 1931 int want_init = 0; 1932 1933 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1934 1935 #define PRINTERR(bit, str) \ 1936 do { \ 1937 if ((isr & (bit)) != 0) { \ 1938 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1939 printf("%s: %s\n", \ 1940 device_xname(&sc->sc_dev), str); \ 1941 want_init = 1; \ 1942 } \ 1943 } while (/*CONSTCOND*/0) 1944 1945 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1946 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1947 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1948 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1949 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1950 /* 1951 * Ignore: 1952 * Tx reset complete 1953 * Rx reset complete 1954 */ 1955 if (want_init) 1956 (void) sipcom_init(ifp); 1957 #undef PRINTERR 1958 } 1959 } 1960 1961 /* Re-enable interrupts. */ 1962 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1963 1964 /* Try to get more packets going. */ 1965 sipcom_start(ifp); 1966 1967 return (handled); 1968 } 1969 1970 /* 1971 * sip_txintr: 1972 * 1973 * Helper; handle transmit interrupts. 1974 */ 1975 static void 1976 sipcom_txintr(struct sip_softc *sc) 1977 { 1978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1979 struct sip_txsoft *txs; 1980 u_int32_t cmdsts; 1981 1982 if (sc->sc_paused == 0) 1983 ifp->if_flags &= ~IFF_OACTIVE; 1984 1985 /* 1986 * Go through our Tx list and free mbufs for those 1987 * frames which have been transmitted. 1988 */ 1989 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1990 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1991 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1992 1993 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1994 if (cmdsts & CMDSTS_OWN) 1995 break; 1996 1997 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1998 1999 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2000 2001 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2002 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2003 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2004 m_freem(txs->txs_mbuf); 2005 txs->txs_mbuf = NULL; 2006 2007 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2008 2009 /* 2010 * Check for errors and collisions. 2011 */ 2012 if (cmdsts & 2013 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2014 ifp->if_oerrors++; 2015 if (cmdsts & CMDSTS_Tx_EC) 2016 ifp->if_collisions += 16; 2017 if (ifp->if_flags & IFF_DEBUG) { 2018 if (cmdsts & CMDSTS_Tx_ED) 2019 printf("%s: excessive deferral\n", 2020 device_xname(&sc->sc_dev)); 2021 if (cmdsts & CMDSTS_Tx_EC) 2022 printf("%s: excessive collisions\n", 2023 device_xname(&sc->sc_dev)); 2024 } 2025 } else { 2026 /* Packet was transmitted successfully. */ 2027 ifp->if_opackets++; 2028 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2029 } 2030 } 2031 2032 /* 2033 * If there are no more pending transmissions, cancel the watchdog 2034 * timer. 2035 */ 2036 if (txs == NULL) { 2037 ifp->if_timer = 0; 2038 sc->sc_txwin = 0; 2039 } 2040 } 2041 2042 /* 2043 * gsip_rxintr: 2044 * 2045 * Helper; handle receive interrupts on gigabit parts. 2046 */ 2047 static void 2048 gsip_rxintr(struct sip_softc *sc) 2049 { 2050 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2051 struct sip_rxsoft *rxs; 2052 struct mbuf *m; 2053 u_int32_t cmdsts, extsts; 2054 int i, len; 2055 2056 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2057 rxs = &sc->sc_rxsoft[i]; 2058 2059 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2060 2061 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2062 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2063 len = CMDSTS_SIZE(sc, cmdsts); 2064 2065 /* 2066 * NOTE: OWN is set if owned by _consumer_. We're the 2067 * consumer of the receive ring, so if the bit is clear, 2068 * we have processed all of the packets. 2069 */ 2070 if ((cmdsts & CMDSTS_OWN) == 0) { 2071 /* 2072 * We have processed all of the receive buffers. 2073 */ 2074 break; 2075 } 2076 2077 if (__predict_false(sc->sc_rxdiscard)) { 2078 sip_init_rxdesc(sc, i); 2079 if ((cmdsts & CMDSTS_MORE) == 0) { 2080 /* Reset our state. */ 2081 sc->sc_rxdiscard = 0; 2082 } 2083 continue; 2084 } 2085 2086 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2087 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2088 2089 m = rxs->rxs_mbuf; 2090 2091 /* 2092 * Add a new receive buffer to the ring. 2093 */ 2094 if (sipcom_add_rxbuf(sc, i) != 0) { 2095 /* 2096 * Failed, throw away what we've done so 2097 * far, and discard the rest of the packet. 2098 */ 2099 ifp->if_ierrors++; 2100 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2101 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2102 sip_init_rxdesc(sc, i); 2103 if (cmdsts & CMDSTS_MORE) 2104 sc->sc_rxdiscard = 1; 2105 if (sc->sc_rxhead != NULL) 2106 m_freem(sc->sc_rxhead); 2107 sip_rxchain_reset(sc); 2108 continue; 2109 } 2110 2111 sip_rxchain_link(sc, m); 2112 2113 m->m_len = len; 2114 2115 /* 2116 * If this is not the end of the packet, keep 2117 * looking. 2118 */ 2119 if (cmdsts & CMDSTS_MORE) { 2120 sc->sc_rxlen += len; 2121 continue; 2122 } 2123 2124 /* 2125 * Okay, we have the entire packet now. The chip includes 2126 * the FCS, so we need to trim it. 2127 */ 2128 m->m_len -= ETHER_CRC_LEN; 2129 2130 *sc->sc_rxtailp = NULL; 2131 len = m->m_len + sc->sc_rxlen; 2132 m = sc->sc_rxhead; 2133 2134 sip_rxchain_reset(sc); 2135 2136 /* 2137 * If an error occurred, update stats and drop the packet. 2138 */ 2139 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2140 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2141 ifp->if_ierrors++; 2142 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2143 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2144 /* Receive overrun handled elsewhere. */ 2145 printf("%s: receive descriptor error\n", 2146 device_xname(&sc->sc_dev)); 2147 } 2148 #define PRINTERR(bit, str) \ 2149 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2150 (cmdsts & (bit)) != 0) \ 2151 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2152 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2153 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2154 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2155 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2156 #undef PRINTERR 2157 m_freem(m); 2158 continue; 2159 } 2160 2161 /* 2162 * If the packet is small enough to fit in a 2163 * single header mbuf, allocate one and copy 2164 * the data into it. This greatly reduces 2165 * memory consumption when we receive lots 2166 * of small packets. 2167 */ 2168 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2169 struct mbuf *nm; 2170 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2171 if (nm == NULL) { 2172 ifp->if_ierrors++; 2173 m_freem(m); 2174 continue; 2175 } 2176 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2177 nm->m_data += 2; 2178 nm->m_pkthdr.len = nm->m_len = len; 2179 m_copydata(m, 0, len, mtod(nm, void *)); 2180 m_freem(m); 2181 m = nm; 2182 } 2183 #ifndef __NO_STRICT_ALIGNMENT 2184 else { 2185 /* 2186 * The DP83820's receive buffers must be 4-byte 2187 * aligned. But this means that the data after 2188 * the Ethernet header is misaligned. To compensate, 2189 * we have artificially shortened the buffer size 2190 * in the descriptor, and we do an overlapping copy 2191 * of the data two bytes further in (in the first 2192 * buffer of the chain only). 2193 */ 2194 memmove(mtod(m, char *) + 2, mtod(m, void *), 2195 m->m_len); 2196 m->m_data += 2; 2197 } 2198 #endif /* ! __NO_STRICT_ALIGNMENT */ 2199 2200 /* 2201 * If VLANs are enabled, VLAN packets have been unwrapped 2202 * for us. Associate the tag with the packet. 2203 */ 2204 2205 /* 2206 * Again, byte swapping is tricky. Hardware provided 2207 * the tag in the network byte order, but extsts was 2208 * passed through le32toh() in the meantime. On a 2209 * big-endian machine, we need to swap it again. On a 2210 * little-endian machine, we need to convert from the 2211 * network to host byte order. This means that we must 2212 * swap it in any case, so unconditional swap instead 2213 * of htons() is used. 2214 */ 2215 if ((extsts & EXTSTS_VPKT) != 0) { 2216 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2217 continue); 2218 } 2219 2220 /* 2221 * Set the incoming checksum information for the 2222 * packet. 2223 */ 2224 if ((extsts & EXTSTS_IPPKT) != 0) { 2225 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2226 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2227 if (extsts & EXTSTS_Rx_IPERR) 2228 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2229 if (extsts & EXTSTS_TCPPKT) { 2230 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2231 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2232 if (extsts & EXTSTS_Rx_TCPERR) 2233 m->m_pkthdr.csum_flags |= 2234 M_CSUM_TCP_UDP_BAD; 2235 } else if (extsts & EXTSTS_UDPPKT) { 2236 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2237 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2238 if (extsts & EXTSTS_Rx_UDPERR) 2239 m->m_pkthdr.csum_flags |= 2240 M_CSUM_TCP_UDP_BAD; 2241 } 2242 } 2243 2244 ifp->if_ipackets++; 2245 m->m_pkthdr.rcvif = ifp; 2246 m->m_pkthdr.len = len; 2247 2248 #if NBPFILTER > 0 2249 /* 2250 * Pass this up to any BPF listeners, but only 2251 * pass if up the stack if it's for us. 2252 */ 2253 if (ifp->if_bpf) 2254 bpf_mtap(ifp->if_bpf, m); 2255 #endif /* NBPFILTER > 0 */ 2256 2257 /* Pass it on. */ 2258 (*ifp->if_input)(ifp, m); 2259 } 2260 2261 /* Update the receive pointer. */ 2262 sc->sc_rxptr = i; 2263 } 2264 2265 /* 2266 * sip_rxintr: 2267 * 2268 * Helper; handle receive interrupts on 10/100 parts. 2269 */ 2270 static void 2271 sip_rxintr(struct sip_softc *sc) 2272 { 2273 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2274 struct sip_rxsoft *rxs; 2275 struct mbuf *m; 2276 u_int32_t cmdsts; 2277 int i, len; 2278 2279 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2280 rxs = &sc->sc_rxsoft[i]; 2281 2282 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2283 2284 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2285 2286 /* 2287 * NOTE: OWN is set if owned by _consumer_. We're the 2288 * consumer of the receive ring, so if the bit is clear, 2289 * we have processed all of the packets. 2290 */ 2291 if ((cmdsts & CMDSTS_OWN) == 0) { 2292 /* 2293 * We have processed all of the receive buffers. 2294 */ 2295 break; 2296 } 2297 2298 /* 2299 * If any collisions were seen on the wire, count one. 2300 */ 2301 if (cmdsts & CMDSTS_Rx_COL) 2302 ifp->if_collisions++; 2303 2304 /* 2305 * If an error occurred, update stats, clear the status 2306 * word, and leave the packet buffer in place. It will 2307 * simply be reused the next time the ring comes around. 2308 */ 2309 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2310 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2311 ifp->if_ierrors++; 2312 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2313 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2314 /* Receive overrun handled elsewhere. */ 2315 printf("%s: receive descriptor error\n", 2316 device_xname(&sc->sc_dev)); 2317 } 2318 #define PRINTERR(bit, str) \ 2319 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2320 (cmdsts & (bit)) != 0) \ 2321 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2322 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2323 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2324 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2325 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2326 #undef PRINTERR 2327 sip_init_rxdesc(sc, i); 2328 continue; 2329 } 2330 2331 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2332 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2333 2334 /* 2335 * No errors; receive the packet. Note, the SiS 900 2336 * includes the CRC with every packet. 2337 */ 2338 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2339 2340 #ifdef __NO_STRICT_ALIGNMENT 2341 /* 2342 * If the packet is small enough to fit in a 2343 * single header mbuf, allocate one and copy 2344 * the data into it. This greatly reduces 2345 * memory consumption when we receive lots 2346 * of small packets. 2347 * 2348 * Otherwise, we add a new buffer to the receive 2349 * chain. If this fails, we drop the packet and 2350 * recycle the old buffer. 2351 */ 2352 if (sip_copy_small != 0 && len <= MHLEN) { 2353 MGETHDR(m, M_DONTWAIT, MT_DATA); 2354 if (m == NULL) 2355 goto dropit; 2356 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2357 memcpy(mtod(m, void *), 2358 mtod(rxs->rxs_mbuf, void *), len); 2359 sip_init_rxdesc(sc, i); 2360 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2361 rxs->rxs_dmamap->dm_mapsize, 2362 BUS_DMASYNC_PREREAD); 2363 } else { 2364 m = rxs->rxs_mbuf; 2365 if (sipcom_add_rxbuf(sc, i) != 0) { 2366 dropit: 2367 ifp->if_ierrors++; 2368 sip_init_rxdesc(sc, i); 2369 bus_dmamap_sync(sc->sc_dmat, 2370 rxs->rxs_dmamap, 0, 2371 rxs->rxs_dmamap->dm_mapsize, 2372 BUS_DMASYNC_PREREAD); 2373 continue; 2374 } 2375 } 2376 #else 2377 /* 2378 * The SiS 900's receive buffers must be 4-byte aligned. 2379 * But this means that the data after the Ethernet header 2380 * is misaligned. We must allocate a new buffer and 2381 * copy the data, shifted forward 2 bytes. 2382 */ 2383 MGETHDR(m, M_DONTWAIT, MT_DATA); 2384 if (m == NULL) { 2385 dropit: 2386 ifp->if_ierrors++; 2387 sip_init_rxdesc(sc, i); 2388 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2389 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2390 continue; 2391 } 2392 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2393 if (len > (MHLEN - 2)) { 2394 MCLGET(m, M_DONTWAIT); 2395 if ((m->m_flags & M_EXT) == 0) { 2396 m_freem(m); 2397 goto dropit; 2398 } 2399 } 2400 m->m_data += 2; 2401 2402 /* 2403 * Note that we use clusters for incoming frames, so the 2404 * buffer is virtually contiguous. 2405 */ 2406 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2407 2408 /* Allow the receive descriptor to continue using its mbuf. */ 2409 sip_init_rxdesc(sc, i); 2410 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2411 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2412 #endif /* __NO_STRICT_ALIGNMENT */ 2413 2414 ifp->if_ipackets++; 2415 m->m_pkthdr.rcvif = ifp; 2416 m->m_pkthdr.len = m->m_len = len; 2417 2418 #if NBPFILTER > 0 2419 /* 2420 * Pass this up to any BPF listeners, but only 2421 * pass if up the stack if it's for us. 2422 */ 2423 if (ifp->if_bpf) 2424 bpf_mtap(ifp->if_bpf, m); 2425 #endif /* NBPFILTER > 0 */ 2426 2427 /* Pass it on. */ 2428 (*ifp->if_input)(ifp, m); 2429 } 2430 2431 /* Update the receive pointer. */ 2432 sc->sc_rxptr = i; 2433 } 2434 2435 /* 2436 * sip_tick: 2437 * 2438 * One second timer, used to tick the MII. 2439 */ 2440 static void 2441 sipcom_tick(void *arg) 2442 { 2443 struct sip_softc *sc = arg; 2444 int s; 2445 2446 s = splnet(); 2447 #ifdef SIP_EVENT_COUNTERS 2448 if (sc->sc_gigabit) { 2449 /* Read PAUSE related counts from MIB registers. */ 2450 sc->sc_ev_rxpause.ev_count += 2451 bus_space_read_4(sc->sc_st, sc->sc_sh, 2452 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2453 sc->sc_ev_txpause.ev_count += 2454 bus_space_read_4(sc->sc_st, sc->sc_sh, 2455 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2456 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2457 } 2458 #endif /* SIP_EVENT_COUNTERS */ 2459 mii_tick(&sc->sc_mii); 2460 splx(s); 2461 2462 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2463 } 2464 2465 /* 2466 * sip_reset: 2467 * 2468 * Perform a soft reset on the SiS 900. 2469 */ 2470 static bool 2471 sipcom_reset(struct sip_softc *sc) 2472 { 2473 bus_space_tag_t st = sc->sc_st; 2474 bus_space_handle_t sh = sc->sc_sh; 2475 int i; 2476 2477 bus_space_write_4(st, sh, SIP_IER, 0); 2478 bus_space_write_4(st, sh, SIP_IMR, 0); 2479 bus_space_write_4(st, sh, SIP_RFCR, 0); 2480 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2481 2482 for (i = 0; i < SIP_TIMEOUT; i++) { 2483 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2484 break; 2485 delay(2); 2486 } 2487 2488 if (i == SIP_TIMEOUT) { 2489 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 2490 return false; 2491 } 2492 2493 delay(1000); 2494 2495 if (sc->sc_gigabit) { 2496 /* 2497 * Set the general purpose I/O bits. Do it here in case we 2498 * need to have GPIO set up to talk to the media interface. 2499 */ 2500 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2501 delay(1000); 2502 } 2503 return true; 2504 } 2505 2506 static void 2507 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2508 { 2509 u_int32_t reg; 2510 bus_space_tag_t st = sc->sc_st; 2511 bus_space_handle_t sh = sc->sc_sh; 2512 /* 2513 * Initialize the VLAN/IP receive control register. 2514 * We enable checksum computation on all incoming 2515 * packets, and do not reject packets w/ bad checksums. 2516 */ 2517 reg = 0; 2518 if (capenable & 2519 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2520 reg |= VRCR_IPEN; 2521 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2522 reg |= VRCR_VTDEN|VRCR_VTREN; 2523 bus_space_write_4(st, sh, SIP_VRCR, reg); 2524 2525 /* 2526 * Initialize the VLAN/IP transmit control register. 2527 * We enable outgoing checksum computation on a 2528 * per-packet basis. 2529 */ 2530 reg = 0; 2531 if (capenable & 2532 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2533 reg |= VTCR_PPCHK; 2534 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2535 reg |= VTCR_VPPTI; 2536 bus_space_write_4(st, sh, SIP_VTCR, reg); 2537 2538 /* 2539 * If we're using VLANs, initialize the VLAN data register. 2540 * To understand why we bswap the VLAN Ethertype, see section 2541 * 4.2.36 of the DP83820 manual. 2542 */ 2543 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2544 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2545 } 2546 2547 /* 2548 * sip_init: [ ifnet interface function ] 2549 * 2550 * Initialize the interface. Must be called at splnet(). 2551 */ 2552 static int 2553 sipcom_init(struct ifnet *ifp) 2554 { 2555 struct sip_softc *sc = ifp->if_softc; 2556 bus_space_tag_t st = sc->sc_st; 2557 bus_space_handle_t sh = sc->sc_sh; 2558 struct sip_txsoft *txs; 2559 struct sip_rxsoft *rxs; 2560 struct sip_desc *sipd; 2561 int i, error = 0; 2562 2563 if (device_is_active(&sc->sc_dev)) { 2564 /* 2565 * Cancel any pending I/O. 2566 */ 2567 sipcom_stop(ifp, 0); 2568 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2569 return 0; 2570 2571 /* 2572 * Reset the chip to a known state. 2573 */ 2574 if (!sipcom_reset(sc)) 2575 return EBUSY; 2576 2577 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2578 /* 2579 * DP83815 manual, page 78: 2580 * 4.4 Recommended Registers Configuration 2581 * For optimum performance of the DP83815, version noted 2582 * as DP83815CVNG (SRR = 203h), the listed register 2583 * modifications must be followed in sequence... 2584 * 2585 * It's not clear if this should be 302h or 203h because that 2586 * chip name is listed as SRR 302h in the description of the 2587 * SRR register. However, my revision 302h DP83815 on the 2588 * Netgear FA311 purchased in 02/2001 needs these settings 2589 * to avoid tons of errors in AcceptPerfectMatch (non- 2590 * IFF_PROMISC) mode. I do not know if other revisions need 2591 * this set or not. [briggs -- 09 March 2001] 2592 * 2593 * Note that only the low-order 12 bits of 0xe4 are documented 2594 * and that this sets reserved bits in that register. 2595 */ 2596 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2597 2598 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2599 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2600 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2601 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2602 2603 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2604 } 2605 2606 /* 2607 * Initialize the transmit descriptor ring. 2608 */ 2609 for (i = 0; i < sc->sc_ntxdesc; i++) { 2610 sipd = &sc->sc_txdescs[i]; 2611 memset(sipd, 0, sizeof(struct sip_desc)); 2612 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2613 } 2614 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2615 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2616 sc->sc_txfree = sc->sc_ntxdesc; 2617 sc->sc_txnext = 0; 2618 sc->sc_txwin = 0; 2619 2620 /* 2621 * Initialize the transmit job descriptors. 2622 */ 2623 SIMPLEQ_INIT(&sc->sc_txfreeq); 2624 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2625 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2626 txs = &sc->sc_txsoft[i]; 2627 txs->txs_mbuf = NULL; 2628 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2629 } 2630 2631 /* 2632 * Initialize the receive descriptor and receive job 2633 * descriptor rings. 2634 */ 2635 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2636 rxs = &sc->sc_rxsoft[i]; 2637 if (rxs->rxs_mbuf == NULL) { 2638 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2639 printf("%s: unable to allocate or map rx " 2640 "buffer %d, error = %d\n", 2641 device_xname(&sc->sc_dev), i, error); 2642 /* 2643 * XXX Should attempt to run with fewer receive 2644 * XXX buffers instead of just failing. 2645 */ 2646 sipcom_rxdrain(sc); 2647 goto out; 2648 } 2649 } else 2650 sip_init_rxdesc(sc, i); 2651 } 2652 sc->sc_rxptr = 0; 2653 sc->sc_rxdiscard = 0; 2654 sip_rxchain_reset(sc); 2655 2656 /* 2657 * Set the configuration register; it's already initialized 2658 * in sip_attach(). 2659 */ 2660 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2661 2662 /* 2663 * Initialize the prototype TXCFG register. 2664 */ 2665 if (sc->sc_gigabit) { 2666 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2667 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2668 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2669 SIP_SIS900_REV(sc, SIS_REV_960) || 2670 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2671 (sc->sc_cfg & CFG_EDBMASTEN)) { 2672 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2673 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2674 } else { 2675 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2676 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2677 } 2678 2679 sc->sc_txcfg |= TXCFG_ATP | 2680 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2681 sc->sc_tx_drain_thresh; 2682 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2683 2684 /* 2685 * Initialize the receive drain threshold if we have never 2686 * done so. 2687 */ 2688 if (sc->sc_rx_drain_thresh == 0) { 2689 /* 2690 * XXX This value should be tuned. This is set to the 2691 * maximum of 248 bytes, and we may be able to improve 2692 * performance by decreasing it (although we should never 2693 * set this value lower than 2; 14 bytes are required to 2694 * filter the packet). 2695 */ 2696 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2697 } 2698 2699 /* 2700 * Initialize the prototype RXCFG register. 2701 */ 2702 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2703 /* 2704 * Accept long packets (including FCS) so we can handle 2705 * 802.1q-tagged frames and jumbo frames properly. 2706 */ 2707 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2708 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2709 sc->sc_rxcfg |= RXCFG_ALP; 2710 2711 /* 2712 * Checksum offloading is disabled if the user selects an MTU 2713 * larger than 8109. (FreeBSD says 8152, but there is emperical 2714 * evidence that >8109 does not work on some boards, such as the 2715 * Planex GN-1000TE). 2716 */ 2717 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2718 (ifp->if_capenable & 2719 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2720 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2721 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2722 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2723 "disabled.\n", device_xname(&sc->sc_dev)); 2724 ifp->if_capenable &= 2725 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2726 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2727 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2728 ifp->if_csum_flags_tx = 0; 2729 ifp->if_csum_flags_rx = 0; 2730 } 2731 2732 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2733 2734 if (sc->sc_gigabit) 2735 sipcom_dp83820_init(sc, ifp->if_capenable); 2736 2737 /* 2738 * Give the transmit and receive rings to the chip. 2739 */ 2740 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2741 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2742 2743 /* 2744 * Initialize the interrupt mask. 2745 */ 2746 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2747 sc->sc_bits.b_isr_sserr | 2748 sc->sc_bits.b_isr_rmabt | 2749 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2750 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2751 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2752 2753 /* Set up the receive filter. */ 2754 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2755 2756 /* 2757 * Tune sc_rx_flow_thresh. 2758 * XXX "More than 8KB" is too short for jumbo frames. 2759 * XXX TODO: Threshold value should be user-settable. 2760 */ 2761 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2762 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2763 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2764 2765 /* 2766 * Set the current media. Do this after initializing the prototype 2767 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2768 * control. 2769 */ 2770 if ((error = ether_mediachange(ifp)) != 0) 2771 goto out; 2772 2773 /* 2774 * Set the interrupt hold-off timer to 100us. 2775 */ 2776 if (sc->sc_gigabit) 2777 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2778 2779 /* 2780 * Enable interrupts. 2781 */ 2782 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2783 2784 /* 2785 * Start the transmit and receive processes. 2786 */ 2787 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2788 2789 /* 2790 * Start the one second MII clock. 2791 */ 2792 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2793 2794 /* 2795 * ...all done! 2796 */ 2797 ifp->if_flags |= IFF_RUNNING; 2798 ifp->if_flags &= ~IFF_OACTIVE; 2799 sc->sc_if_flags = ifp->if_flags; 2800 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2801 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2802 sc->sc_prev.if_capenable = ifp->if_capenable; 2803 2804 out: 2805 if (error) 2806 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2807 return (error); 2808 } 2809 2810 /* 2811 * sip_drain: 2812 * 2813 * Drain the receive queue. 2814 */ 2815 static void 2816 sipcom_rxdrain(struct sip_softc *sc) 2817 { 2818 struct sip_rxsoft *rxs; 2819 int i; 2820 2821 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2822 rxs = &sc->sc_rxsoft[i]; 2823 if (rxs->rxs_mbuf != NULL) { 2824 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2825 m_freem(rxs->rxs_mbuf); 2826 rxs->rxs_mbuf = NULL; 2827 } 2828 } 2829 } 2830 2831 /* 2832 * sip_stop: [ ifnet interface function ] 2833 * 2834 * Stop transmission on the interface. 2835 */ 2836 static void 2837 sipcom_stop(struct ifnet *ifp, int disable) 2838 { 2839 struct sip_softc *sc = ifp->if_softc; 2840 bus_space_tag_t st = sc->sc_st; 2841 bus_space_handle_t sh = sc->sc_sh; 2842 struct sip_txsoft *txs; 2843 u_int32_t cmdsts = 0; /* DEBUG */ 2844 2845 /* 2846 * Stop the one second clock. 2847 */ 2848 callout_stop(&sc->sc_tick_ch); 2849 2850 /* Down the MII. */ 2851 mii_down(&sc->sc_mii); 2852 2853 /* 2854 * Disable interrupts. 2855 */ 2856 bus_space_write_4(st, sh, SIP_IER, 0); 2857 2858 /* 2859 * Stop receiver and transmitter. 2860 */ 2861 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2862 2863 /* 2864 * Release any queued transmit buffers. 2865 */ 2866 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2867 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2868 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2869 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2870 CMDSTS_INTR) == 0) 2871 printf("%s: sip_stop: last descriptor does not " 2872 "have INTR bit set\n", device_xname(&sc->sc_dev)); 2873 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2874 #ifdef DIAGNOSTIC 2875 if (txs->txs_mbuf == NULL) { 2876 printf("%s: dirty txsoft with no mbuf chain\n", 2877 device_xname(&sc->sc_dev)); 2878 panic("sip_stop"); 2879 } 2880 #endif 2881 cmdsts |= /* DEBUG */ 2882 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2883 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2884 m_freem(txs->txs_mbuf); 2885 txs->txs_mbuf = NULL; 2886 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2887 } 2888 2889 /* 2890 * Mark the interface down and cancel the watchdog timer. 2891 */ 2892 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2893 ifp->if_timer = 0; 2894 2895 if (disable) 2896 pmf_device_suspend_self(&sc->sc_dev); 2897 2898 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2899 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2900 printf("%s: sip_stop: no INTR bits set in dirty tx " 2901 "descriptors\n", device_xname(&sc->sc_dev)); 2902 } 2903 2904 /* 2905 * sip_read_eeprom: 2906 * 2907 * Read data from the serial EEPROM. 2908 */ 2909 static void 2910 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2911 u_int16_t *data) 2912 { 2913 bus_space_tag_t st = sc->sc_st; 2914 bus_space_handle_t sh = sc->sc_sh; 2915 u_int16_t reg; 2916 int i, x; 2917 2918 for (i = 0; i < wordcnt; i++) { 2919 /* Send CHIP SELECT. */ 2920 reg = EROMAR_EECS; 2921 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2922 2923 /* Shift in the READ opcode. */ 2924 for (x = 3; x > 0; x--) { 2925 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2926 reg |= EROMAR_EEDI; 2927 else 2928 reg &= ~EROMAR_EEDI; 2929 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2930 bus_space_write_4(st, sh, SIP_EROMAR, 2931 reg | EROMAR_EESK); 2932 delay(4); 2933 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2934 delay(4); 2935 } 2936 2937 /* Shift in address. */ 2938 for (x = 6; x > 0; x--) { 2939 if ((word + i) & (1 << (x - 1))) 2940 reg |= EROMAR_EEDI; 2941 else 2942 reg &= ~EROMAR_EEDI; 2943 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2944 bus_space_write_4(st, sh, SIP_EROMAR, 2945 reg | EROMAR_EESK); 2946 delay(4); 2947 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2948 delay(4); 2949 } 2950 2951 /* Shift out data. */ 2952 reg = EROMAR_EECS; 2953 data[i] = 0; 2954 for (x = 16; x > 0; x--) { 2955 bus_space_write_4(st, sh, SIP_EROMAR, 2956 reg | EROMAR_EESK); 2957 delay(4); 2958 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2959 data[i] |= (1 << (x - 1)); 2960 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2961 delay(4); 2962 } 2963 2964 /* Clear CHIP SELECT. */ 2965 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2966 delay(4); 2967 } 2968 } 2969 2970 /* 2971 * sipcom_add_rxbuf: 2972 * 2973 * Add a receive buffer to the indicated descriptor. 2974 */ 2975 static int 2976 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2977 { 2978 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2979 struct mbuf *m; 2980 int error; 2981 2982 MGETHDR(m, M_DONTWAIT, MT_DATA); 2983 if (m == NULL) 2984 return (ENOBUFS); 2985 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2986 2987 MCLGET(m, M_DONTWAIT); 2988 if ((m->m_flags & M_EXT) == 0) { 2989 m_freem(m); 2990 return (ENOBUFS); 2991 } 2992 2993 /* XXX I don't believe this is necessary. --dyoung */ 2994 if (sc->sc_gigabit) 2995 m->m_len = sc->sc_parm->p_rxbuf_len; 2996 2997 if (rxs->rxs_mbuf != NULL) 2998 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2999 3000 rxs->rxs_mbuf = m; 3001 3002 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3003 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3004 BUS_DMA_READ|BUS_DMA_NOWAIT); 3005 if (error) { 3006 printf("%s: can't load rx DMA map %d, error = %d\n", 3007 device_xname(&sc->sc_dev), idx, error); 3008 panic("%s", __func__); /* XXX */ 3009 } 3010 3011 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3012 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3013 3014 sip_init_rxdesc(sc, idx); 3015 3016 return (0); 3017 } 3018 3019 /* 3020 * sip_sis900_set_filter: 3021 * 3022 * Set up the receive filter. 3023 */ 3024 static void 3025 sipcom_sis900_set_filter(struct sip_softc *sc) 3026 { 3027 bus_space_tag_t st = sc->sc_st; 3028 bus_space_handle_t sh = sc->sc_sh; 3029 struct ethercom *ec = &sc->sc_ethercom; 3030 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3031 struct ether_multi *enm; 3032 const u_int8_t *cp; 3033 struct ether_multistep step; 3034 u_int32_t crc, mchash[16]; 3035 3036 /* 3037 * Initialize the prototype RFCR. 3038 */ 3039 sc->sc_rfcr = RFCR_RFEN; 3040 if (ifp->if_flags & IFF_BROADCAST) 3041 sc->sc_rfcr |= RFCR_AAB; 3042 if (ifp->if_flags & IFF_PROMISC) { 3043 sc->sc_rfcr |= RFCR_AAP; 3044 goto allmulti; 3045 } 3046 3047 /* 3048 * Set up the multicast address filter by passing all multicast 3049 * addresses through a CRC generator, and then using the high-order 3050 * 6 bits as an index into the 128 bit multicast hash table (only 3051 * the lower 16 bits of each 32 bit multicast hash register are 3052 * valid). The high order bits select the register, while the 3053 * rest of the bits select the bit within the register. 3054 */ 3055 3056 memset(mchash, 0, sizeof(mchash)); 3057 3058 /* 3059 * SiS900 (at least SiS963) requires us to register the address of 3060 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3061 */ 3062 crc = 0x0ed423f9; 3063 3064 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3065 SIP_SIS900_REV(sc, SIS_REV_960) || 3066 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3067 /* Just want the 8 most significant bits. */ 3068 crc >>= 24; 3069 } else { 3070 /* Just want the 7 most significant bits. */ 3071 crc >>= 25; 3072 } 3073 3074 /* Set the corresponding bit in the hash table. */ 3075 mchash[crc >> 4] |= 1 << (crc & 0xf); 3076 3077 ETHER_FIRST_MULTI(step, ec, enm); 3078 while (enm != NULL) { 3079 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3080 /* 3081 * We must listen to a range of multicast addresses. 3082 * For now, just accept all multicasts, rather than 3083 * trying to set only those filter bits needed to match 3084 * the range. (At this time, the only use of address 3085 * ranges is for IP multicast routing, for which the 3086 * range is big enough to require all bits set.) 3087 */ 3088 goto allmulti; 3089 } 3090 3091 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3092 3093 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3094 SIP_SIS900_REV(sc, SIS_REV_960) || 3095 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3096 /* Just want the 8 most significant bits. */ 3097 crc >>= 24; 3098 } else { 3099 /* Just want the 7 most significant bits. */ 3100 crc >>= 25; 3101 } 3102 3103 /* Set the corresponding bit in the hash table. */ 3104 mchash[crc >> 4] |= 1 << (crc & 0xf); 3105 3106 ETHER_NEXT_MULTI(step, enm); 3107 } 3108 3109 ifp->if_flags &= ~IFF_ALLMULTI; 3110 goto setit; 3111 3112 allmulti: 3113 ifp->if_flags |= IFF_ALLMULTI; 3114 sc->sc_rfcr |= RFCR_AAM; 3115 3116 setit: 3117 #define FILTER_EMIT(addr, data) \ 3118 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3119 delay(1); \ 3120 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3121 delay(1) 3122 3123 /* 3124 * Disable receive filter, and program the node address. 3125 */ 3126 cp = CLLADDR(ifp->if_sadl); 3127 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3128 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3129 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3130 3131 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3132 /* 3133 * Program the multicast hash table. 3134 */ 3135 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3136 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3137 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3138 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3139 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3140 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3141 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3142 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3143 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3144 SIP_SIS900_REV(sc, SIS_REV_960) || 3145 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3146 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3147 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3148 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3149 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3150 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3151 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3152 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3153 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3154 } 3155 } 3156 #undef FILTER_EMIT 3157 3158 /* 3159 * Re-enable the receiver filter. 3160 */ 3161 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3162 } 3163 3164 /* 3165 * sip_dp83815_set_filter: 3166 * 3167 * Set up the receive filter. 3168 */ 3169 static void 3170 sipcom_dp83815_set_filter(struct sip_softc *sc) 3171 { 3172 bus_space_tag_t st = sc->sc_st; 3173 bus_space_handle_t sh = sc->sc_sh; 3174 struct ethercom *ec = &sc->sc_ethercom; 3175 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3176 struct ether_multi *enm; 3177 const u_int8_t *cp; 3178 struct ether_multistep step; 3179 u_int32_t crc, hash, slot, bit; 3180 #define MCHASH_NWORDS_83820 128 3181 #define MCHASH_NWORDS_83815 32 3182 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3183 u_int16_t mchash[MCHASH_NWORDS]; 3184 int i; 3185 3186 /* 3187 * Initialize the prototype RFCR. 3188 * Enable the receive filter, and accept on 3189 * Perfect (destination address) Match 3190 * If IFF_BROADCAST, also accept all broadcast packets. 3191 * If IFF_PROMISC, accept all unicast packets (and later, set 3192 * IFF_ALLMULTI and accept all multicast, too). 3193 */ 3194 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3195 if (ifp->if_flags & IFF_BROADCAST) 3196 sc->sc_rfcr |= RFCR_AAB; 3197 if (ifp->if_flags & IFF_PROMISC) { 3198 sc->sc_rfcr |= RFCR_AAP; 3199 goto allmulti; 3200 } 3201 3202 /* 3203 * Set up the DP83820/DP83815 multicast address filter by 3204 * passing all multicast addresses through a CRC generator, 3205 * and then using the high-order 11/9 bits as an index into 3206 * the 2048/512 bit multicast hash table. The high-order 3207 * 7/5 bits select the slot, while the low-order 4 bits 3208 * select the bit within the slot. Note that only the low 3209 * 16-bits of each filter word are used, and there are 3210 * 128/32 filter words. 3211 */ 3212 3213 memset(mchash, 0, sizeof(mchash)); 3214 3215 ifp->if_flags &= ~IFF_ALLMULTI; 3216 ETHER_FIRST_MULTI(step, ec, enm); 3217 if (enm == NULL) 3218 goto setit; 3219 while (enm != NULL) { 3220 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3221 /* 3222 * We must listen to a range of multicast addresses. 3223 * For now, just accept all multicasts, rather than 3224 * trying to set only those filter bits needed to match 3225 * the range. (At this time, the only use of address 3226 * ranges is for IP multicast routing, for which the 3227 * range is big enough to require all bits set.) 3228 */ 3229 goto allmulti; 3230 } 3231 3232 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3233 3234 if (sc->sc_gigabit) { 3235 /* Just want the 11 most significant bits. */ 3236 hash = crc >> 21; 3237 } else { 3238 /* Just want the 9 most significant bits. */ 3239 hash = crc >> 23; 3240 } 3241 3242 slot = hash >> 4; 3243 bit = hash & 0xf; 3244 3245 /* Set the corresponding bit in the hash table. */ 3246 mchash[slot] |= 1 << bit; 3247 3248 ETHER_NEXT_MULTI(step, enm); 3249 } 3250 sc->sc_rfcr |= RFCR_MHEN; 3251 goto setit; 3252 3253 allmulti: 3254 ifp->if_flags |= IFF_ALLMULTI; 3255 sc->sc_rfcr |= RFCR_AAM; 3256 3257 setit: 3258 #define FILTER_EMIT(addr, data) \ 3259 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3260 delay(1); \ 3261 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3262 delay(1) 3263 3264 /* 3265 * Disable receive filter, and program the node address. 3266 */ 3267 cp = CLLADDR(ifp->if_sadl); 3268 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3269 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3270 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3271 3272 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3273 int nwords = 3274 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3275 /* 3276 * Program the multicast hash table. 3277 */ 3278 for (i = 0; i < nwords; i++) { 3279 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3280 } 3281 } 3282 #undef FILTER_EMIT 3283 #undef MCHASH_NWORDS 3284 #undef MCHASH_NWORDS_83815 3285 #undef MCHASH_NWORDS_83820 3286 3287 /* 3288 * Re-enable the receiver filter. 3289 */ 3290 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3291 } 3292 3293 /* 3294 * sip_dp83820_mii_readreg: [mii interface function] 3295 * 3296 * Read a PHY register on the MII of the DP83820. 3297 */ 3298 static int 3299 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3300 { 3301 struct sip_softc *sc = device_private(self); 3302 3303 if (sc->sc_cfg & CFG_TBI_EN) { 3304 bus_addr_t tbireg; 3305 int rv; 3306 3307 if (phy != 0) 3308 return (0); 3309 3310 switch (reg) { 3311 case MII_BMCR: tbireg = SIP_TBICR; break; 3312 case MII_BMSR: tbireg = SIP_TBISR; break; 3313 case MII_ANAR: tbireg = SIP_TANAR; break; 3314 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3315 case MII_ANER: tbireg = SIP_TANER; break; 3316 case MII_EXTSR: 3317 /* 3318 * Don't even bother reading the TESR register. 3319 * The manual documents that the device has 3320 * 1000baseX full/half capability, but the 3321 * register itself seems read back 0 on some 3322 * boards. Just hard-code the result. 3323 */ 3324 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3325 3326 default: 3327 return (0); 3328 } 3329 3330 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3331 if (tbireg == SIP_TBISR) { 3332 /* LINK and ACOMP are switched! */ 3333 int val = rv; 3334 3335 rv = 0; 3336 if (val & TBISR_MR_LINK_STATUS) 3337 rv |= BMSR_LINK; 3338 if (val & TBISR_MR_AN_COMPLETE) 3339 rv |= BMSR_ACOMP; 3340 3341 /* 3342 * The manual claims this register reads back 0 3343 * on hard and soft reset. But we want to let 3344 * the gentbi driver know that we support auto- 3345 * negotiation, so hard-code this bit in the 3346 * result. 3347 */ 3348 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3349 } 3350 3351 return (rv); 3352 } 3353 3354 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3355 } 3356 3357 /* 3358 * sip_dp83820_mii_writereg: [mii interface function] 3359 * 3360 * Write a PHY register on the MII of the DP83820. 3361 */ 3362 static void 3363 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3364 { 3365 struct sip_softc *sc = device_private(self); 3366 3367 if (sc->sc_cfg & CFG_TBI_EN) { 3368 bus_addr_t tbireg; 3369 3370 if (phy != 0) 3371 return; 3372 3373 switch (reg) { 3374 case MII_BMCR: tbireg = SIP_TBICR; break; 3375 case MII_ANAR: tbireg = SIP_TANAR; break; 3376 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3377 default: 3378 return; 3379 } 3380 3381 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3382 return; 3383 } 3384 3385 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3386 } 3387 3388 /* 3389 * sip_dp83820_mii_statchg: [mii interface function] 3390 * 3391 * Callback from MII layer when media changes. 3392 */ 3393 static void 3394 sipcom_dp83820_mii_statchg(device_t self) 3395 { 3396 struct sip_softc *sc = device_private(self); 3397 struct mii_data *mii = &sc->sc_mii; 3398 u_int32_t cfg, pcr; 3399 3400 /* 3401 * Get flow control negotiation result. 3402 */ 3403 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3404 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3405 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3406 mii->mii_media_active &= ~IFM_ETH_FMASK; 3407 } 3408 3409 /* 3410 * Update TXCFG for full-duplex operation. 3411 */ 3412 if ((mii->mii_media_active & IFM_FDX) != 0) 3413 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3414 else 3415 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3416 3417 /* 3418 * Update RXCFG for full-duplex or loopback. 3419 */ 3420 if ((mii->mii_media_active & IFM_FDX) != 0 || 3421 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3422 sc->sc_rxcfg |= RXCFG_ATX; 3423 else 3424 sc->sc_rxcfg &= ~RXCFG_ATX; 3425 3426 /* 3427 * Update CFG for MII/GMII. 3428 */ 3429 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3430 cfg = sc->sc_cfg | CFG_MODE_1000; 3431 else 3432 cfg = sc->sc_cfg; 3433 3434 /* 3435 * 802.3x flow control. 3436 */ 3437 pcr = 0; 3438 if (sc->sc_flowflags & IFM_FLOW) { 3439 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3440 pcr |= sc->sc_rx_flow_thresh; 3441 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3442 pcr |= PCR_PSEN | PCR_PS_MCAST; 3443 } 3444 3445 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3446 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3447 sc->sc_txcfg); 3448 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3449 sc->sc_rxcfg); 3450 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3451 } 3452 3453 /* 3454 * sip_mii_bitbang_read: [mii bit-bang interface function] 3455 * 3456 * Read the MII serial port for the MII bit-bang module. 3457 */ 3458 static u_int32_t 3459 sipcom_mii_bitbang_read(device_t self) 3460 { 3461 struct sip_softc *sc = device_private(self); 3462 3463 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3464 } 3465 3466 /* 3467 * sip_mii_bitbang_write: [mii big-bang interface function] 3468 * 3469 * Write the MII serial port for the MII bit-bang module. 3470 */ 3471 static void 3472 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3473 { 3474 struct sip_softc *sc = device_private(self); 3475 3476 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3477 } 3478 3479 /* 3480 * sip_sis900_mii_readreg: [mii interface function] 3481 * 3482 * Read a PHY register on the MII. 3483 */ 3484 static int 3485 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3486 { 3487 struct sip_softc *sc = device_private(self); 3488 u_int32_t enphy; 3489 3490 /* 3491 * The PHY of recent SiS chipsets is accessed through bitbang 3492 * operations. 3493 */ 3494 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3495 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3496 phy, reg); 3497 3498 #ifndef SIS900_MII_RESTRICT 3499 /* 3500 * The SiS 900 has only an internal PHY on the MII. Only allow 3501 * MII address 0. 3502 */ 3503 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3504 return (0); 3505 #endif 3506 3507 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3508 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3509 ENPHY_RWCMD | ENPHY_ACCESS); 3510 do { 3511 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3512 } while (enphy & ENPHY_ACCESS); 3513 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3514 } 3515 3516 /* 3517 * sip_sis900_mii_writereg: [mii interface function] 3518 * 3519 * Write a PHY register on the MII. 3520 */ 3521 static void 3522 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3523 { 3524 struct sip_softc *sc = device_private(self); 3525 u_int32_t enphy; 3526 3527 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3528 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3529 phy, reg, val); 3530 return; 3531 } 3532 3533 #ifndef SIS900_MII_RESTRICT 3534 /* 3535 * The SiS 900 has only an internal PHY on the MII. Only allow 3536 * MII address 0. 3537 */ 3538 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3539 return; 3540 #endif 3541 3542 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3543 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3544 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3545 do { 3546 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3547 } while (enphy & ENPHY_ACCESS); 3548 } 3549 3550 /* 3551 * sip_sis900_mii_statchg: [mii interface function] 3552 * 3553 * Callback from MII layer when media changes. 3554 */ 3555 static void 3556 sipcom_sis900_mii_statchg(device_t self) 3557 { 3558 struct sip_softc *sc = device_private(self); 3559 struct mii_data *mii = &sc->sc_mii; 3560 u_int32_t flowctl; 3561 3562 /* 3563 * Get flow control negotiation result. 3564 */ 3565 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3566 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3567 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3568 mii->mii_media_active &= ~IFM_ETH_FMASK; 3569 } 3570 3571 /* 3572 * Update TXCFG for full-duplex operation. 3573 */ 3574 if ((mii->mii_media_active & IFM_FDX) != 0) 3575 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3576 else 3577 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3578 3579 /* 3580 * Update RXCFG for full-duplex or loopback. 3581 */ 3582 if ((mii->mii_media_active & IFM_FDX) != 0 || 3583 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3584 sc->sc_rxcfg |= RXCFG_ATX; 3585 else 3586 sc->sc_rxcfg &= ~RXCFG_ATX; 3587 3588 /* 3589 * Update IMR for use of 802.3x flow control. 3590 */ 3591 if (sc->sc_flowflags & IFM_FLOW) { 3592 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3593 flowctl = FLOWCTL_FLOWEN; 3594 } else { 3595 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3596 flowctl = 0; 3597 } 3598 3599 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3600 sc->sc_txcfg); 3601 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3602 sc->sc_rxcfg); 3603 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3604 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3605 } 3606 3607 /* 3608 * sip_dp83815_mii_readreg: [mii interface function] 3609 * 3610 * Read a PHY register on the MII. 3611 */ 3612 static int 3613 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3614 { 3615 struct sip_softc *sc = device_private(self); 3616 u_int32_t val; 3617 3618 /* 3619 * The DP83815 only has an internal PHY. Only allow 3620 * MII address 0. 3621 */ 3622 if (phy != 0) 3623 return (0); 3624 3625 /* 3626 * Apparently, after a reset, the DP83815 can take a while 3627 * to respond. During this recovery period, the BMSR returns 3628 * a value of 0. Catch this -- it's not supposed to happen 3629 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3630 * PHY to come back to life. 3631 * 3632 * This works out because the BMSR is the first register 3633 * read during the PHY probe process. 3634 */ 3635 do { 3636 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3637 } while (reg == MII_BMSR && val == 0); 3638 3639 return (val & 0xffff); 3640 } 3641 3642 /* 3643 * sip_dp83815_mii_writereg: [mii interface function] 3644 * 3645 * Write a PHY register to the MII. 3646 */ 3647 static void 3648 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3649 { 3650 struct sip_softc *sc = device_private(self); 3651 3652 /* 3653 * The DP83815 only has an internal PHY. Only allow 3654 * MII address 0. 3655 */ 3656 if (phy != 0) 3657 return; 3658 3659 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3660 } 3661 3662 /* 3663 * sip_dp83815_mii_statchg: [mii interface function] 3664 * 3665 * Callback from MII layer when media changes. 3666 */ 3667 static void 3668 sipcom_dp83815_mii_statchg(device_t self) 3669 { 3670 struct sip_softc *sc = device_private(self); 3671 3672 /* 3673 * Update TXCFG for full-duplex operation. 3674 */ 3675 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3676 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3677 else 3678 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3679 3680 /* 3681 * Update RXCFG for full-duplex or loopback. 3682 */ 3683 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3684 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3685 sc->sc_rxcfg |= RXCFG_ATX; 3686 else 3687 sc->sc_rxcfg &= ~RXCFG_ATX; 3688 3689 /* 3690 * XXX 802.3x flow control. 3691 */ 3692 3693 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3694 sc->sc_txcfg); 3695 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3696 sc->sc_rxcfg); 3697 3698 /* 3699 * Some DP83815s experience problems when used with short 3700 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3701 * sequence adjusts the DSP's signal attenuation to fix the 3702 * problem. 3703 */ 3704 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3705 uint32_t reg; 3706 3707 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3708 3709 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3710 reg &= 0x0fff; 3711 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3712 delay(100); 3713 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3714 reg &= 0x00ff; 3715 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3716 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3717 0x00e8); 3718 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3719 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3720 reg | 0x20); 3721 } 3722 3723 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3724 } 3725 } 3726 3727 static void 3728 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3729 const struct pci_attach_args *pa, u_int8_t *enaddr) 3730 { 3731 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3732 u_int8_t cksum, *e, match; 3733 int i; 3734 3735 /* 3736 * EEPROM data format for the DP83820 can be found in 3737 * the DP83820 manual, section 4.2.4. 3738 */ 3739 3740 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3741 3742 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3743 match = ~(match - 1); 3744 3745 cksum = 0x55; 3746 e = (u_int8_t *) eeprom_data; 3747 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3748 cksum += *e++; 3749 3750 if (cksum != match) 3751 printf("%s: Checksum (%x) mismatch (%x)", 3752 device_xname(&sc->sc_dev), cksum, match); 3753 3754 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3755 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3756 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3757 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3758 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3759 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3760 } 3761 3762 static void 3763 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3764 { 3765 int i; 3766 3767 /* 3768 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3769 * a reason, but I don't know it. 3770 */ 3771 for (i = 0; i < 10; i++) 3772 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3773 } 3774 3775 static void 3776 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3777 const struct pci_attach_args *pa, u_int8_t *enaddr) 3778 { 3779 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3780 3781 switch (sc->sc_rev) { 3782 case SIS_REV_630S: 3783 case SIS_REV_630E: 3784 case SIS_REV_630EA1: 3785 case SIS_REV_630ET: 3786 case SIS_REV_635: 3787 /* 3788 * The MAC address for the on-board Ethernet of 3789 * the SiS 630 chipset is in the NVRAM. Kick 3790 * the chip into re-loading it from NVRAM, and 3791 * read the MAC address out of the filter registers. 3792 */ 3793 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3794 3795 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3796 RFCR_RFADDR_NODE0); 3797 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3798 0xffff; 3799 3800 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3801 RFCR_RFADDR_NODE2); 3802 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3803 0xffff; 3804 3805 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3806 RFCR_RFADDR_NODE4); 3807 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3808 0xffff; 3809 break; 3810 3811 case SIS_REV_960: 3812 { 3813 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3814 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3815 3816 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3817 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3818 3819 int waittime, i; 3820 3821 /* Allow to read EEPROM from LAN. It is shared 3822 * between a 1394 controller and the NIC and each 3823 * time we access it, we need to set SIS_EECMD_REQ. 3824 */ 3825 SIS_SET_EROMAR(sc, EROMAR_REQ); 3826 3827 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3828 /* Force EEPROM to idle state. */ 3829 3830 /* 3831 * XXX-cube This is ugly. I'll look for docs about it. 3832 */ 3833 SIS_SET_EROMAR(sc, EROMAR_EECS); 3834 sipcom_sis900_eeprom_delay(sc); 3835 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3836 SIS_SET_EROMAR(sc, EROMAR_EESK); 3837 sipcom_sis900_eeprom_delay(sc); 3838 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3839 sipcom_sis900_eeprom_delay(sc); 3840 } 3841 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3842 sipcom_sis900_eeprom_delay(sc); 3843 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3844 3845 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3846 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3847 sizeof(myea) / sizeof(myea[0]), myea); 3848 break; 3849 } 3850 DELAY(1); 3851 } 3852 3853 /* 3854 * Set SIS_EECTL_CLK to high, so a other master 3855 * can operate on the i2c bus. 3856 */ 3857 SIS_SET_EROMAR(sc, EROMAR_EESK); 3858 3859 /* Refuse EEPROM access by LAN */ 3860 SIS_SET_EROMAR(sc, EROMAR_DONE); 3861 } break; 3862 3863 default: 3864 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3865 sizeof(myea) / sizeof(myea[0]), myea); 3866 } 3867 3868 enaddr[0] = myea[0] & 0xff; 3869 enaddr[1] = myea[0] >> 8; 3870 enaddr[2] = myea[1] & 0xff; 3871 enaddr[3] = myea[1] >> 8; 3872 enaddr[4] = myea[2] & 0xff; 3873 enaddr[5] = myea[2] >> 8; 3874 } 3875 3876 /* Table and macro to bit-reverse an octet. */ 3877 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3878 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3879 3880 static void 3881 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3882 const struct pci_attach_args *pa, u_int8_t *enaddr) 3883 { 3884 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3885 u_int8_t cksum, *e, match; 3886 int i; 3887 3888 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3889 sizeof(eeprom_data[0]), eeprom_data); 3890 3891 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3892 match = ~(match - 1); 3893 3894 cksum = 0x55; 3895 e = (u_int8_t *) eeprom_data; 3896 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3897 cksum += *e++; 3898 } 3899 if (cksum != match) { 3900 printf("%s: Checksum (%x) mismatch (%x)", 3901 device_xname(&sc->sc_dev), cksum, match); 3902 } 3903 3904 /* 3905 * Unrolled because it makes slightly more sense this way. 3906 * The DP83815 stores the MAC address in bit 0 of word 6 3907 * through bit 15 of word 8. 3908 */ 3909 ea = &eeprom_data[6]; 3910 enaddr[0] = ((*ea & 0x1) << 7); 3911 ea++; 3912 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3913 enaddr[1] = ((*ea & 0x1FE) >> 1); 3914 enaddr[2] = ((*ea & 0x1) << 7); 3915 ea++; 3916 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3917 enaddr[3] = ((*ea & 0x1FE) >> 1); 3918 enaddr[4] = ((*ea & 0x1) << 7); 3919 ea++; 3920 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3921 enaddr[5] = ((*ea & 0x1FE) >> 1); 3922 3923 /* 3924 * In case that's not weird enough, we also need to reverse 3925 * the bits in each byte. This all actually makes more sense 3926 * if you think about the EEPROM storage as an array of bits 3927 * being shifted into bytes, but that's not how we're looking 3928 * at it here... 3929 */ 3930 for (i = 0; i < 6 ;i++) 3931 enaddr[i] = bbr(enaddr[i]); 3932 } 3933 3934 /* 3935 * sip_mediastatus: [ifmedia interface function] 3936 * 3937 * Get the current interface media status. 3938 */ 3939 static void 3940 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3941 { 3942 struct sip_softc *sc = ifp->if_softc; 3943 3944 ether_mediastatus(ifp, ifmr); 3945 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3946 sc->sc_flowflags; 3947 } 3948
Indexes created Mon Sep 22 10:09:38 GMT 2025