if_sip.c revision 1.132.2.1
1 /* $NetBSD: if_sip.c,v 1.132.2.1 2008/05/18 12:34:20 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.132.2.1 2008/05/18 12:34:20 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/queue.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #include <sys/bus.h> 109 #include <sys/intr.h> 110 #include <machine/endian.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 #include <dev/mii/mii_bitbang.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_sipreg.h> 121 122 /* 123 * Transmit descriptor list size. This is arbitrary, but allocate 124 * enough descriptors for 128 pending transmissions, and 8 segments 125 * per packet (64 for DP83820 for jumbo frames). 126 * 127 * This MUST work out to a power of 2. 128 */ 129 #define GSIP_NTXSEGS_ALLOC 16 130 #define SIP_NTXSEGS_ALLOC 8 131 132 #define SIP_TXQUEUELEN 256 133 #define MAX_SIP_NTXDESC \ 134 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 135 136 /* 137 * Receive descriptor list size. We have one Rx buffer per incoming 138 * packet, so this logic is a little simpler. 139 * 140 * Actually, on the DP83820, we allow the packet to consume more than 141 * one buffer, in order to support jumbo Ethernet frames. In that 142 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 143 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 144 * so we'd better be quick about handling receive interrupts. 145 */ 146 #define GSIP_NRXDESC 256 147 #define SIP_NRXDESC 128 148 149 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 150 151 /* 152 * Control structures are DMA'd to the SiS900 chip. We allocate them in 153 * a single clump that maps to a single DMA segment to make several things 154 * easier. 155 */ 156 struct sip_control_data { 157 /* 158 * The transmit descriptors. 159 */ 160 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 161 162 /* 163 * The receive descriptors. 164 */ 165 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 166 }; 167 168 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 169 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 170 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 171 172 /* 173 * Software state for transmit jobs. 174 */ 175 struct sip_txsoft { 176 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 177 bus_dmamap_t txs_dmamap; /* our DMA map */ 178 int txs_firstdesc; /* first descriptor in packet */ 179 int txs_lastdesc; /* last descriptor in packet */ 180 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 181 }; 182 183 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 184 185 /* 186 * Software state for receive jobs. 187 */ 188 struct sip_rxsoft { 189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t rxs_dmamap; /* our DMA map */ 191 }; 192 193 enum sip_attach_stage { 194 SIP_ATTACH_FIN = 0 195 , SIP_ATTACH_CREATE_RXMAP 196 , SIP_ATTACH_CREATE_TXMAP 197 , SIP_ATTACH_LOAD_MAP 198 , SIP_ATTACH_CREATE_MAP 199 , SIP_ATTACH_MAP_MEM 200 , SIP_ATTACH_ALLOC_MEM 201 , SIP_ATTACH_INTR 202 , SIP_ATTACH_MAP 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static void sipcom_start(struct ifnet *); 563 static void sipcom_watchdog(struct ifnet *); 564 static int sipcom_ioctl(struct ifnet *, u_long, void *); 565 static int sipcom_init(struct ifnet *); 566 static void sipcom_stop(struct ifnet *, int); 567 568 static bool sipcom_reset(struct sip_softc *); 569 static void sipcom_rxdrain(struct sip_softc *); 570 static int sipcom_add_rxbuf(struct sip_softc *, int); 571 static void sipcom_read_eeprom(struct sip_softc *, int, int, 572 u_int16_t *); 573 static void sipcom_tick(void *); 574 575 static void sipcom_sis900_set_filter(struct sip_softc *); 576 static void sipcom_dp83815_set_filter(struct sip_softc *); 577 578 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 581 static void sipcom_sis900_read_macaddr(struct sip_softc *, 582 const struct pci_attach_args *, u_int8_t *); 583 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 584 const struct pci_attach_args *, u_int8_t *); 585 586 static int sipcom_intr(void *); 587 static void sipcom_txintr(struct sip_softc *); 588 static void sip_rxintr(struct sip_softc *); 589 static void gsip_rxintr(struct sip_softc *); 590 591 static int sipcom_dp83820_mii_readreg(device_t, int, int); 592 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 593 static void sipcom_dp83820_mii_statchg(device_t); 594 595 static int sipcom_sis900_mii_readreg(device_t, int, int); 596 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 597 static void sipcom_sis900_mii_statchg(device_t); 598 599 static int sipcom_dp83815_mii_readreg(device_t, int, int); 600 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 601 static void sipcom_dp83815_mii_statchg(device_t); 602 603 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 604 605 static int sipcom_match(device_t, struct cfdata *, void *); 606 static void sipcom_attach(device_t, device_t, void *); 607 static void sipcom_do_detach(device_t, enum sip_attach_stage); 608 static int sipcom_detach(device_t, int); 609 static bool sipcom_resume(device_t PMF_FN_PROTO); 610 static bool sipcom_suspend(device_t PMF_FN_PROTO); 611 612 int gsip_copy_small = 0; 613 int sip_copy_small = 0; 614 615 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 616 sipcom_match, sipcom_attach, sipcom_detach, NULL); 617 CFATTACH_DECL(sip, sizeof(struct sip_softc), 618 sipcom_match, sipcom_attach, sipcom_detach, NULL); 619 620 /* 621 * Descriptions of the variants of the SiS900. 622 */ 623 struct sip_variant { 624 int (*sipv_mii_readreg)(device_t, int, int); 625 void (*sipv_mii_writereg)(device_t, int, int, int); 626 void (*sipv_mii_statchg)(device_t); 627 void (*sipv_set_filter)(struct sip_softc *); 628 void (*sipv_read_macaddr)(struct sip_softc *, 629 const struct pci_attach_args *, u_int8_t *); 630 }; 631 632 static u_int32_t sipcom_mii_bitbang_read(device_t); 633 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 634 635 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 636 sipcom_mii_bitbang_read, 637 sipcom_mii_bitbang_write, 638 { 639 EROMAR_MDIO, /* MII_BIT_MDO */ 640 EROMAR_MDIO, /* MII_BIT_MDI */ 641 EROMAR_MDC, /* MII_BIT_MDC */ 642 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 643 0, /* MII_BIT_DIR_PHY_HOST */ 644 } 645 }; 646 647 static const struct sip_variant sipcom_variant_dp83820 = { 648 sipcom_dp83820_mii_readreg, 649 sipcom_dp83820_mii_writereg, 650 sipcom_dp83820_mii_statchg, 651 sipcom_dp83815_set_filter, 652 sipcom_dp83820_read_macaddr, 653 }; 654 655 static const struct sip_variant sipcom_variant_sis900 = { 656 sipcom_sis900_mii_readreg, 657 sipcom_sis900_mii_writereg, 658 sipcom_sis900_mii_statchg, 659 sipcom_sis900_set_filter, 660 sipcom_sis900_read_macaddr, 661 }; 662 663 static const struct sip_variant sipcom_variant_dp83815 = { 664 sipcom_dp83815_mii_readreg, 665 sipcom_dp83815_mii_writereg, 666 sipcom_dp83815_mii_statchg, 667 sipcom_dp83815_set_filter, 668 sipcom_dp83815_read_macaddr, 669 }; 670 671 672 /* 673 * Devices supported by this driver. 674 */ 675 static const struct sip_product { 676 pci_vendor_id_t sip_vendor; 677 pci_product_id_t sip_product; 678 const char *sip_name; 679 const struct sip_variant *sip_variant; 680 int sip_gigabit; 681 } sipcom_products[] = { 682 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 683 "NatSemi DP83820 Gigabit Ethernet", 684 &sipcom_variant_dp83820, 1 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 686 "SiS 900 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 689 "SiS 7016 10/100 Ethernet", 690 &sipcom_variant_sis900, 0 }, 691 692 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 693 "NatSemi DP83815 10/100 Ethernet", 694 &sipcom_variant_dp83815, 0 }, 695 696 { 0, 0, 697 NULL, 698 NULL, 0 }, 699 }; 700 701 static const struct sip_product * 702 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 703 { 704 const struct sip_product *sip; 705 706 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 707 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 708 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 709 sip->sip_gigabit == gigabit) 710 return sip; 711 } 712 return NULL; 713 } 714 715 /* 716 * I really hate stupid hardware vendors. There's a bit in the EEPROM 717 * which indicates if the card can do 64-bit data transfers. Unfortunately, 718 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 719 * which means we try to use 64-bit data transfers on those cards if we 720 * happen to be plugged into a 32-bit slot. 721 * 722 * What we do is use this table of cards known to be 64-bit cards. If 723 * you have a 64-bit card who's subsystem ID is not listed in this table, 724 * send the output of "pcictl dump ..." of the device to me so that your 725 * card will use the 64-bit data path when plugged into a 64-bit slot. 726 * 727 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 728 * June 30, 2002 729 */ 730 static int 731 sipcom_check_64bit(const struct pci_attach_args *pa) 732 { 733 static const struct { 734 pci_vendor_id_t c64_vendor; 735 pci_product_id_t c64_product; 736 } card64[] = { 737 /* Asante GigaNIX */ 738 { 0x128a, 0x0002 }, 739 740 /* Accton EN1407-T, Planex GN-1000TE */ 741 { 0x1113, 0x1407 }, 742 743 /* Netgear GA-621 */ 744 { 0x1385, 0x621a }, 745 746 /* SMC EZ Card */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(&sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(&sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(&sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 #if NRND > 0 914 rnd_detach_source(&sc->rnd_source); 915 #endif 916 917 ether_ifdetach(ifp); 918 if_detach(ifp); 919 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 920 921 /*FALLTHROUGH*/ 922 case SIP_ATTACH_CREATE_RXMAP: 923 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 924 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 925 bus_dmamap_destroy(sc->sc_dmat, 926 sc->sc_rxsoft[i].rxs_dmamap); 927 } 928 /*FALLTHROUGH*/ 929 case SIP_ATTACH_CREATE_TXMAP: 930 for (i = 0; i < SIP_TXQUEUELEN; i++) { 931 if (sc->sc_txsoft[i].txs_dmamap != NULL) 932 bus_dmamap_destroy(sc->sc_dmat, 933 sc->sc_txsoft[i].txs_dmamap); 934 } 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_LOAD_MAP: 937 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 938 /*FALLTHROUGH*/ 939 case SIP_ATTACH_CREATE_MAP: 940 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_MAP_MEM: 943 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 944 sizeof(struct sip_control_data)); 945 /*FALLTHROUGH*/ 946 case SIP_ATTACH_ALLOC_MEM: 947 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 948 /* FALLTHROUGH*/ 949 case SIP_ATTACH_INTR: 950 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 951 /* FALLTHROUGH*/ 952 case SIP_ATTACH_MAP: 953 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 954 break; 955 default: 956 break; 957 } 958 return; 959 } 960 961 static bool 962 sipcom_resume(device_t self PMF_FN_ARGS) 963 { 964 struct sip_softc *sc = device_private(self); 965 966 return sipcom_reset(sc); 967 } 968 969 static bool 970 sipcom_suspend(device_t self PMF_FN_ARGS) 971 { 972 struct sip_softc *sc = device_private(self); 973 974 sipcom_rxdrain(sc); 975 return true; 976 } 977 978 static void 979 sipcom_attach(device_t parent, device_t self, void *aux) 980 { 981 struct sip_softc *sc = device_private(self); 982 struct pci_attach_args *pa = aux; 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 pci_chipset_tag_t pc = pa->pa_pc; 985 pci_intr_handle_t ih; 986 const char *intrstr = NULL; 987 bus_space_tag_t iot, memt; 988 bus_space_handle_t ioh, memh; 989 bus_size_t iosz, memsz; 990 int ioh_valid, memh_valid; 991 int i, rseg, error; 992 const struct sip_product *sip; 993 u_int8_t enaddr[ETHER_ADDR_LEN]; 994 pcireg_t csr; 995 pcireg_t memtype; 996 bus_size_t tx_dmamap_size; 997 int ntxsegs_alloc; 998 cfdata_t cf = device_cfdata(self); 999 1000 callout_init(&sc->sc_tick_ch, 0); 1001 1002 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1003 if (sip == NULL) { 1004 printf("\n"); 1005 panic("%s: impossible", __func__); 1006 } 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1027 1028 sc->sc_model = sip; 1029 1030 /* 1031 * XXX Work-around broken PXE firmware on some boards. 1032 * 1033 * The DP83815 shares an address decoder with the MEM BAR 1034 * and the ROM BAR. Make sure the ROM BAR is disabled, 1035 * so that memory mapped access works. 1036 */ 1037 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1038 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1039 ~PCI_MAPREG_ROM_ENABLE); 1040 1041 /* 1042 * Map the device. 1043 */ 1044 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1045 PCI_MAPREG_TYPE_IO, 0, 1046 &iot, &ioh, NULL, &iosz) == 0); 1047 if (sc->sc_gigabit) { 1048 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1049 switch (memtype) { 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1052 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1053 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1054 break; 1055 default: 1056 memh_valid = 0; 1057 } 1058 } else { 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1061 &memt, &memh, NULL, &memsz) == 0); 1062 } 1063 1064 if (memh_valid) { 1065 sc->sc_st = memt; 1066 sc->sc_sh = memh; 1067 sc->sc_sz = memsz; 1068 } else if (ioh_valid) { 1069 sc->sc_st = iot; 1070 sc->sc_sh = ioh; 1071 sc->sc_sz = iosz; 1072 } else { 1073 printf("%s: unable to map device registers\n", 1074 device_xname(&sc->sc_dev)); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 csr | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1092 if (error != 0 && error != EOPNOTSUPP) { 1093 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 1094 return; 1095 } 1096 1097 /* 1098 * Map and establish our interrupt. 1099 */ 1100 if (pci_intr_map(pa, &ih)) { 1101 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 1102 return; 1103 } 1104 intrstr = pci_intr_string(pc, ih); 1105 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1106 if (sc->sc_ih == NULL) { 1107 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 1108 if (intrstr != NULL) 1109 printf(" at %s", intrstr); 1110 printf("\n"); 1111 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1112 } 1113 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1114 1115 SIMPLEQ_INIT(&sc->sc_txfreeq); 1116 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1117 1118 /* 1119 * Allocate the control data structures, and create and load the 1120 * DMA map for it. 1121 */ 1122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1123 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1124 &rseg, 0)) != 0) { 1125 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1126 error); 1127 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1128 } 1129 1130 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1131 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1132 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1133 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1134 error); 1135 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1136 } 1137 1138 if ((error = bus_dmamap_create(sc->sc_dmat, 1139 sizeof(struct sip_control_data), 1, 1140 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1141 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1142 "error = %d\n", error); 1143 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1144 } 1145 1146 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1147 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1148 0)) != 0) { 1149 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1150 error); 1151 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1152 } 1153 1154 /* 1155 * Create the transmit buffer DMA maps. 1156 */ 1157 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1158 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1159 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1160 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1161 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 1162 "error = %d\n", i, error); 1163 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1164 } 1165 } 1166 1167 /* 1168 * Create the receive buffer DMA maps. 1169 */ 1170 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1171 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1172 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1173 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 1174 "error = %d\n", i, error); 1175 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1176 } 1177 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1178 } 1179 1180 /* 1181 * Reset the chip to a known state. 1182 */ 1183 sipcom_reset(sc); 1184 1185 /* 1186 * Read the Ethernet address from the EEPROM. This might 1187 * also fetch other stuff from the EEPROM and stash it 1188 * in the softc. 1189 */ 1190 sc->sc_cfg = 0; 1191 if (!sc->sc_gigabit) { 1192 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1193 SIP_SIS900_REV(sc,SIS_REV_900B)) 1194 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1195 1196 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1197 SIP_SIS900_REV(sc,SIS_REV_960) || 1198 SIP_SIS900_REV(sc,SIS_REV_900B)) 1199 sc->sc_cfg |= 1200 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1201 CFG_EDBMASTEN); 1202 } 1203 1204 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1205 1206 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 1207 ether_sprintf(enaddr)); 1208 1209 /* 1210 * Initialize the configuration register: aggressive PCI 1211 * bus request algorithm, default backoff, default OW timer, 1212 * default parity error detection. 1213 * 1214 * NOTE: "Big endian mode" is useless on the SiS900 and 1215 * friends -- it affects packet data, not descriptors. 1216 */ 1217 if (sc->sc_gigabit) 1218 sipcom_dp83820_attach(sc, pa); 1219 1220 /* 1221 * Initialize our media structures and probe the MII. 1222 */ 1223 sc->sc_mii.mii_ifp = ifp; 1224 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1225 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1226 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1227 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1228 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1229 sipcom_mediastatus); 1230 1231 /* 1232 * XXX We cannot handle flow control on the DP83815. 1233 */ 1234 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1235 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1236 MII_OFFSET_ANY, 0); 1237 else 1238 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1239 MII_OFFSET_ANY, MIIF_DOPAUSE); 1240 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1241 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1242 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1243 } else 1244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1245 1246 ifp = &sc->sc_ethercom.ec_if; 1247 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1248 ifp->if_softc = sc; 1249 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1250 sc->sc_if_flags = ifp->if_flags; 1251 ifp->if_ioctl = sipcom_ioctl; 1252 ifp->if_start = sipcom_start; 1253 ifp->if_watchdog = sipcom_watchdog; 1254 ifp->if_init = sipcom_init; 1255 ifp->if_stop = sipcom_stop; 1256 IFQ_SET_READY(&ifp->if_snd); 1257 1258 /* 1259 * We can support 802.1Q VLAN-sized frames. 1260 */ 1261 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1262 1263 if (sc->sc_gigabit) { 1264 /* 1265 * And the DP83820 can do VLAN tagging in hardware, and 1266 * support the jumbo Ethernet MTU. 1267 */ 1268 sc->sc_ethercom.ec_capabilities |= 1269 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1270 1271 /* 1272 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1273 * in hardware. 1274 */ 1275 ifp->if_capabilities |= 1276 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1277 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1278 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1279 } 1280 1281 /* 1282 * Attach the interface. 1283 */ 1284 if_attach(ifp); 1285 ether_ifattach(ifp, enaddr); 1286 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1287 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1288 sc->sc_prev.if_capenable = ifp->if_capenable; 1289 #if NRND > 0 1290 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 1291 RND_TYPE_NET, 0); 1292 #endif 1293 1294 /* 1295 * The number of bytes that must be available in 1296 * the Tx FIFO before the bus master can DMA more 1297 * data into the FIFO. 1298 */ 1299 sc->sc_tx_fill_thresh = 64 / 32; 1300 1301 /* 1302 * Start at a drain threshold of 512 bytes. We will 1303 * increase it if a DMA underrun occurs. 1304 * 1305 * XXX The minimum value of this variable should be 1306 * tuned. We may be able to improve performance 1307 * by starting with a lower value. That, however, 1308 * may trash the first few outgoing packets if the 1309 * PCI bus is saturated. 1310 */ 1311 if (sc->sc_gigabit) 1312 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1313 else 1314 sc->sc_tx_drain_thresh = 1504 / 32; 1315 1316 /* 1317 * Initialize the Rx FIFO drain threshold. 1318 * 1319 * This is in units of 8 bytes. 1320 * 1321 * We should never set this value lower than 2; 14 bytes are 1322 * required to filter the packet. 1323 */ 1324 sc->sc_rx_drain_thresh = 128 / 8; 1325 1326 #ifdef SIP_EVENT_COUNTERS 1327 /* 1328 * Attach event counters. 1329 */ 1330 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1331 NULL, device_xname(&sc->sc_dev), "txsstall"); 1332 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(&sc->sc_dev), "txdstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1335 NULL, device_xname(&sc->sc_dev), "txforceintr"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(&sc->sc_dev), "txdintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(&sc->sc_dev), "txiintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(&sc->sc_dev), "rxintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(&sc->sc_dev), "hiberr"); 1344 if (!sc->sc_gigabit) { 1345 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1346 NULL, device_xname(&sc->sc_dev), "rxpause"); 1347 } else { 1348 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1349 NULL, device_xname(&sc->sc_dev), "rxpause"); 1350 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(&sc->sc_dev), "txpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1353 NULL, device_xname(&sc->sc_dev), "rxipsum"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(&sc->sc_dev), "txipsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(&sc->sc_dev), "txudpsum"); 1364 } 1365 #endif /* SIP_EVENT_COUNTERS */ 1366 1367 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1368 aprint_error_dev(self, "couldn't establish power handler\n"); 1369 else 1370 pmf_class_network_register(self, ifp); 1371 } 1372 1373 static inline void 1374 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1375 uint64_t capenable) 1376 { 1377 struct m_tag *mtag; 1378 u_int32_t extsts; 1379 #ifdef DEBUG 1380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1381 #endif 1382 /* 1383 * If VLANs are enabled and the packet has a VLAN tag, set 1384 * up the descriptor to encapsulate the packet for us. 1385 * 1386 * This apparently has to be on the last descriptor of 1387 * the packet. 1388 */ 1389 1390 /* 1391 * Byte swapping is tricky. We need to provide the tag 1392 * in a network byte order. On a big-endian machine, 1393 * the byteorder is correct, but we need to swap it 1394 * anyway, because this will be undone by the outside 1395 * htole32(). That's why there must be an 1396 * unconditional swap instead of htons() inside. 1397 */ 1398 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1399 sc->sc_txdescs[lasttx].sipd_extsts |= 1400 htole32(EXTSTS_VPKT | 1401 (bswap16(VLAN_TAG_VALUE(mtag)) & 1402 EXTSTS_VTCI)); 1403 } 1404 1405 /* 1406 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1407 * checksumming, set up the descriptor to do this work 1408 * for us. 1409 * 1410 * This apparently has to be on the first descriptor of 1411 * the packet. 1412 * 1413 * Byte-swap constants so the compiler can optimize. 1414 */ 1415 extsts = 0; 1416 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1417 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1418 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1419 extsts |= htole32(EXTSTS_IPPKT); 1420 } 1421 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1422 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1423 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1424 extsts |= htole32(EXTSTS_TCPPKT); 1425 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1426 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1427 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1428 extsts |= htole32(EXTSTS_UDPPKT); 1429 } 1430 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1431 } 1432 1433 /* 1434 * sip_start: [ifnet interface function] 1435 * 1436 * Start packet transmission on the interface. 1437 */ 1438 static void 1439 sipcom_start(struct ifnet *ifp) 1440 { 1441 struct sip_softc *sc = ifp->if_softc; 1442 struct mbuf *m0; 1443 struct mbuf *m; 1444 struct sip_txsoft *txs; 1445 bus_dmamap_t dmamap; 1446 int error, nexttx, lasttx, seg; 1447 int ofree = sc->sc_txfree; 1448 #if 0 1449 int firsttx = sc->sc_txnext; 1450 #endif 1451 1452 /* 1453 * If we've been told to pause, don't transmit any more packets. 1454 */ 1455 if (!sc->sc_gigabit && sc->sc_paused) 1456 ifp->if_flags |= IFF_OACTIVE; 1457 1458 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1459 return; 1460 1461 /* 1462 * Loop through the send queue, setting up transmit descriptors 1463 * until we drain the queue, or use up all available transmit 1464 * descriptors. 1465 */ 1466 for (;;) { 1467 /* Get a work queue entry. */ 1468 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1469 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1470 break; 1471 } 1472 1473 /* 1474 * Grab a packet off the queue. 1475 */ 1476 IFQ_POLL(&ifp->if_snd, m0); 1477 if (m0 == NULL) 1478 break; 1479 m = NULL; 1480 1481 dmamap = txs->txs_dmamap; 1482 1483 /* 1484 * Load the DMA map. If this fails, the packet either 1485 * didn't fit in the alloted number of segments, or we 1486 * were short on resources. 1487 */ 1488 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1489 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1490 /* In the non-gigabit case, we'll copy and try again. */ 1491 if (error != 0 && !sc->sc_gigabit) { 1492 MGETHDR(m, M_DONTWAIT, MT_DATA); 1493 if (m == NULL) { 1494 printf("%s: unable to allocate Tx mbuf\n", 1495 device_xname(&sc->sc_dev)); 1496 break; 1497 } 1498 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1499 if (m0->m_pkthdr.len > MHLEN) { 1500 MCLGET(m, M_DONTWAIT); 1501 if ((m->m_flags & M_EXT) == 0) { 1502 printf("%s: unable to allocate Tx " 1503 "cluster\n", device_xname(&sc->sc_dev)); 1504 m_freem(m); 1505 break; 1506 } 1507 } 1508 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1509 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1510 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1511 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1512 if (error) { 1513 printf("%s: unable to load Tx buffer, " 1514 "error = %d\n", device_xname(&sc->sc_dev), error); 1515 break; 1516 } 1517 } else if (error == EFBIG) { 1518 /* 1519 * For the too-many-segments case, we simply 1520 * report an error and drop the packet, 1521 * since we can't sanely copy a jumbo packet 1522 * to a single buffer. 1523 */ 1524 printf("%s: Tx packet consumes too many " 1525 "DMA segments, dropping...\n", device_xname(&sc->sc_dev)); 1526 IFQ_DEQUEUE(&ifp->if_snd, m0); 1527 m_freem(m0); 1528 continue; 1529 } else if (error != 0) { 1530 /* 1531 * Short on resources, just stop for now. 1532 */ 1533 break; 1534 } 1535 1536 /* 1537 * Ensure we have enough descriptors free to describe 1538 * the packet. Note, we always reserve one descriptor 1539 * at the end of the ring as a termination point, to 1540 * prevent wrap-around. 1541 */ 1542 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1543 /* 1544 * Not enough free descriptors to transmit this 1545 * packet. We haven't committed anything yet, 1546 * so just unload the DMA map, put the packet 1547 * back on the queue, and punt. Notify the upper 1548 * layer that there are not more slots left. 1549 * 1550 * XXX We could allocate an mbuf and copy, but 1551 * XXX is it worth it? 1552 */ 1553 ifp->if_flags |= IFF_OACTIVE; 1554 bus_dmamap_unload(sc->sc_dmat, dmamap); 1555 if (m != NULL) 1556 m_freem(m); 1557 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1558 break; 1559 } 1560 1561 IFQ_DEQUEUE(&ifp->if_snd, m0); 1562 if (m != NULL) { 1563 m_freem(m0); 1564 m0 = m; 1565 } 1566 1567 /* 1568 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1569 */ 1570 1571 /* Sync the DMA map. */ 1572 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1573 BUS_DMASYNC_PREWRITE); 1574 1575 /* 1576 * Initialize the transmit descriptors. 1577 */ 1578 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1579 seg < dmamap->dm_nsegs; 1580 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1581 /* 1582 * If this is the first descriptor we're 1583 * enqueueing, don't set the OWN bit just 1584 * yet. That could cause a race condition. 1585 * We'll do it below. 1586 */ 1587 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1588 htole32(dmamap->dm_segs[seg].ds_addr); 1589 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1591 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1592 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1593 lasttx = nexttx; 1594 } 1595 1596 /* Clear the MORE bit on the last segment. */ 1597 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1598 htole32(~CMDSTS_MORE); 1599 1600 /* 1601 * If we're in the interrupt delay window, delay the 1602 * interrupt. 1603 */ 1604 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1605 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1606 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1607 htole32(CMDSTS_INTR); 1608 sc->sc_txwin = 0; 1609 } 1610 1611 if (sc->sc_gigabit) 1612 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1613 1614 /* Sync the descriptors we're using. */ 1615 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1616 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1617 1618 /* 1619 * The entire packet is set up. Give the first descrptor 1620 * to the chip now. 1621 */ 1622 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1623 htole32(CMDSTS_OWN); 1624 sip_cdtxsync(sc, sc->sc_txnext, 1, 1625 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1626 1627 /* 1628 * Store a pointer to the packet so we can free it later, 1629 * and remember what txdirty will be once the packet is 1630 * done. 1631 */ 1632 txs->txs_mbuf = m0; 1633 txs->txs_firstdesc = sc->sc_txnext; 1634 txs->txs_lastdesc = lasttx; 1635 1636 /* Advance the tx pointer. */ 1637 sc->sc_txfree -= dmamap->dm_nsegs; 1638 sc->sc_txnext = nexttx; 1639 1640 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1641 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1642 1643 #if NBPFILTER > 0 1644 /* 1645 * Pass the packet to any BPF listeners. 1646 */ 1647 if (ifp->if_bpf) 1648 bpf_mtap(ifp->if_bpf, m0); 1649 #endif /* NBPFILTER > 0 */ 1650 } 1651 1652 if (txs == NULL || sc->sc_txfree == 0) { 1653 /* No more slots left; notify upper layer. */ 1654 ifp->if_flags |= IFF_OACTIVE; 1655 } 1656 1657 if (sc->sc_txfree != ofree) { 1658 /* 1659 * Start the transmit process. Note, the manual says 1660 * that if there are no pending transmissions in the 1661 * chip's internal queue (indicated by TXE being clear), 1662 * then the driver software must set the TXDP to the 1663 * first descriptor to be transmitted. However, if we 1664 * do this, it causes serious performance degredation on 1665 * the DP83820 under load, not setting TXDP doesn't seem 1666 * to adversely affect the SiS 900 or DP83815. 1667 * 1668 * Well, I guess it wouldn't be the first time a manual 1669 * has lied -- and they could be speaking of the NULL- 1670 * terminated descriptor list case, rather than OWN- 1671 * terminated rings. 1672 */ 1673 #if 0 1674 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1675 CR_TXE) == 0) { 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1677 SIP_CDTXADDR(sc, firsttx)); 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1679 } 1680 #else 1681 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1682 #endif 1683 1684 /* Set a watchdog timer in case the chip flakes out. */ 1685 /* Gigabit autonegotiation takes 5 seconds. */ 1686 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1687 } 1688 } 1689 1690 /* 1691 * sip_watchdog: [ifnet interface function] 1692 * 1693 * Watchdog timer handler. 1694 */ 1695 static void 1696 sipcom_watchdog(struct ifnet *ifp) 1697 { 1698 struct sip_softc *sc = ifp->if_softc; 1699 1700 /* 1701 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1702 * If we get a timeout, try and sweep up transmit descriptors. 1703 * If we manage to sweep them all up, ignore the lack of 1704 * interrupt. 1705 */ 1706 sipcom_txintr(sc); 1707 1708 if (sc->sc_txfree != sc->sc_ntxdesc) { 1709 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1710 ifp->if_oerrors++; 1711 1712 /* Reset the interface. */ 1713 (void) sipcom_init(ifp); 1714 } else if (ifp->if_flags & IFF_DEBUG) 1715 printf("%s: recovered from device timeout\n", 1716 device_xname(&sc->sc_dev)); 1717 1718 /* Try to get more packets going. */ 1719 sipcom_start(ifp); 1720 } 1721 1722 /* 1723 * sip_ioctl: [ifnet interface function] 1724 * 1725 * Handle control requests from the operator. 1726 */ 1727 static int 1728 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1729 { 1730 struct sip_softc *sc = ifp->if_softc; 1731 struct ifreq *ifr = (struct ifreq *)data; 1732 int s, error; 1733 1734 s = splnet(); 1735 1736 switch (cmd) { 1737 case SIOCSIFMEDIA: 1738 /* Flow control requires full-duplex mode. */ 1739 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1740 (ifr->ifr_media & IFM_FDX) == 0) 1741 ifr->ifr_media &= ~IFM_ETH_FMASK; 1742 1743 /* XXX */ 1744 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1745 ifr->ifr_media &= ~IFM_ETH_FMASK; 1746 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1747 if (sc->sc_gigabit && 1748 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1749 /* We can do both TXPAUSE and RXPAUSE. */ 1750 ifr->ifr_media |= 1751 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1752 } else if (ifr->ifr_media & IFM_FLOW) { 1753 /* 1754 * Both TXPAUSE and RXPAUSE must be set. 1755 * (SiS900 and DP83815 don't have PAUSE_ASYM 1756 * feature.) 1757 * 1758 * XXX Can SiS900 and DP83815 send PAUSE? 1759 */ 1760 ifr->ifr_media |= 1761 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1762 } 1763 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1764 } 1765 goto ethioctl; 1766 case SIOCSIFFLAGS: 1767 /* If the interface is up and running, only modify the receive 1768 * filter when setting promiscuous or debug mode. Otherwise 1769 * fall through to ether_ioctl, which will reset the chip. 1770 */ 1771 1772 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1773 == (sc)->sc_ethercom.ec_capenable) \ 1774 && ((sc)->sc_prev.is_vlan == \ 1775 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1776 1777 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1778 1779 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1780 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1781 == (IFF_UP|IFF_RUNNING)) 1782 && ((ifp->if_flags & (~RESETIGN)) 1783 == (sc->sc_if_flags & (~RESETIGN))) 1784 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1785 /* Set up the receive filter. */ 1786 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1787 error = 0; 1788 break; 1789 #undef RESETIGN 1790 } 1791 /* FALLTHROUGH */ 1792 ethioctl: 1793 default: 1794 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1795 break; 1796 1797 error = 0; 1798 1799 if (cmd == SIOCSIFCAP) 1800 error = (*ifp->if_init)(ifp); 1801 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1802 ; 1803 else if (ifp->if_flags & IFF_RUNNING) { 1804 /* 1805 * Multicast list has changed; set the hardware filter 1806 * accordingly. 1807 */ 1808 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1809 } 1810 break; 1811 } 1812 1813 /* Try to get more packets going. */ 1814 sipcom_start(ifp); 1815 1816 sc->sc_if_flags = ifp->if_flags; 1817 splx(s); 1818 return (error); 1819 } 1820 1821 /* 1822 * sip_intr: 1823 * 1824 * Interrupt service routine. 1825 */ 1826 static int 1827 sipcom_intr(void *arg) 1828 { 1829 struct sip_softc *sc = arg; 1830 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1831 u_int32_t isr; 1832 int handled = 0; 1833 1834 if (!device_is_active(&sc->sc_dev)) 1835 return 0; 1836 1837 /* Disable interrupts. */ 1838 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1839 1840 for (;;) { 1841 /* Reading clears interrupt. */ 1842 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1843 if ((isr & sc->sc_imr) == 0) 1844 break; 1845 1846 #if NRND > 0 1847 if (RND_ENABLED(&sc->rnd_source)) 1848 rnd_add_uint32(&sc->rnd_source, isr); 1849 #endif 1850 1851 handled = 1; 1852 1853 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1854 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1855 1856 /* Grab any new packets. */ 1857 (*sc->sc_rxintr)(sc); 1858 1859 if (isr & ISR_RXORN) { 1860 printf("%s: receive FIFO overrun\n", 1861 device_xname(&sc->sc_dev)); 1862 1863 /* XXX adjust rx_drain_thresh? */ 1864 } 1865 1866 if (isr & ISR_RXIDLE) { 1867 printf("%s: receive ring overrun\n", 1868 device_xname(&sc->sc_dev)); 1869 1870 /* Get the receive process going again. */ 1871 bus_space_write_4(sc->sc_st, sc->sc_sh, 1872 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1873 bus_space_write_4(sc->sc_st, sc->sc_sh, 1874 SIP_CR, CR_RXE); 1875 } 1876 } 1877 1878 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1879 #ifdef SIP_EVENT_COUNTERS 1880 if (isr & ISR_TXDESC) 1881 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1882 else if (isr & ISR_TXIDLE) 1883 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1884 #endif 1885 1886 /* Sweep up transmit descriptors. */ 1887 sipcom_txintr(sc); 1888 1889 if (isr & ISR_TXURN) { 1890 u_int32_t thresh; 1891 int txfifo_size = (sc->sc_gigabit) 1892 ? DP83820_SIP_TXFIFO_SIZE 1893 : OTHER_SIP_TXFIFO_SIZE; 1894 1895 printf("%s: transmit FIFO underrun", 1896 device_xname(&sc->sc_dev)); 1897 thresh = sc->sc_tx_drain_thresh + 1; 1898 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1899 && (thresh * 32) <= (txfifo_size - 1900 (sc->sc_tx_fill_thresh * 32))) { 1901 printf("; increasing Tx drain " 1902 "threshold to %u bytes\n", 1903 thresh * 32); 1904 sc->sc_tx_drain_thresh = thresh; 1905 (void) sipcom_init(ifp); 1906 } else { 1907 (void) sipcom_init(ifp); 1908 printf("\n"); 1909 } 1910 } 1911 } 1912 1913 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1914 if (isr & ISR_PAUSE_ST) { 1915 sc->sc_paused = 1; 1916 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1917 ifp->if_flags |= IFF_OACTIVE; 1918 } 1919 if (isr & ISR_PAUSE_END) { 1920 sc->sc_paused = 0; 1921 ifp->if_flags &= ~IFF_OACTIVE; 1922 } 1923 } 1924 1925 if (isr & ISR_HIBERR) { 1926 int want_init = 0; 1927 1928 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1929 1930 #define PRINTERR(bit, str) \ 1931 do { \ 1932 if ((isr & (bit)) != 0) { \ 1933 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1934 printf("%s: %s\n", \ 1935 device_xname(&sc->sc_dev), str); \ 1936 want_init = 1; \ 1937 } \ 1938 } while (/*CONSTCOND*/0) 1939 1940 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1941 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1942 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1943 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1944 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1945 /* 1946 * Ignore: 1947 * Tx reset complete 1948 * Rx reset complete 1949 */ 1950 if (want_init) 1951 (void) sipcom_init(ifp); 1952 #undef PRINTERR 1953 } 1954 } 1955 1956 /* Re-enable interrupts. */ 1957 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1958 1959 /* Try to get more packets going. */ 1960 sipcom_start(ifp); 1961 1962 return (handled); 1963 } 1964 1965 /* 1966 * sip_txintr: 1967 * 1968 * Helper; handle transmit interrupts. 1969 */ 1970 static void 1971 sipcom_txintr(struct sip_softc *sc) 1972 { 1973 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1974 struct sip_txsoft *txs; 1975 u_int32_t cmdsts; 1976 1977 if (sc->sc_paused == 0) 1978 ifp->if_flags &= ~IFF_OACTIVE; 1979 1980 /* 1981 * Go through our Tx list and free mbufs for those 1982 * frames which have been transmitted. 1983 */ 1984 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1985 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1986 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1987 1988 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1989 if (cmdsts & CMDSTS_OWN) 1990 break; 1991 1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1993 1994 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1995 1996 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1997 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1998 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1999 m_freem(txs->txs_mbuf); 2000 txs->txs_mbuf = NULL; 2001 2002 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2003 2004 /* 2005 * Check for errors and collisions. 2006 */ 2007 if (cmdsts & 2008 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2009 ifp->if_oerrors++; 2010 if (cmdsts & CMDSTS_Tx_EC) 2011 ifp->if_collisions += 16; 2012 if (ifp->if_flags & IFF_DEBUG) { 2013 if (cmdsts & CMDSTS_Tx_ED) 2014 printf("%s: excessive deferral\n", 2015 device_xname(&sc->sc_dev)); 2016 if (cmdsts & CMDSTS_Tx_EC) 2017 printf("%s: excessive collisions\n", 2018 device_xname(&sc->sc_dev)); 2019 } 2020 } else { 2021 /* Packet was transmitted successfully. */ 2022 ifp->if_opackets++; 2023 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2024 } 2025 } 2026 2027 /* 2028 * If there are no more pending transmissions, cancel the watchdog 2029 * timer. 2030 */ 2031 if (txs == NULL) { 2032 ifp->if_timer = 0; 2033 sc->sc_txwin = 0; 2034 } 2035 } 2036 2037 /* 2038 * gsip_rxintr: 2039 * 2040 * Helper; handle receive interrupts on gigabit parts. 2041 */ 2042 static void 2043 gsip_rxintr(struct sip_softc *sc) 2044 { 2045 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2046 struct sip_rxsoft *rxs; 2047 struct mbuf *m; 2048 u_int32_t cmdsts, extsts; 2049 int i, len; 2050 2051 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2052 rxs = &sc->sc_rxsoft[i]; 2053 2054 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2055 2056 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2057 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2058 len = CMDSTS_SIZE(sc, cmdsts); 2059 2060 /* 2061 * NOTE: OWN is set if owned by _consumer_. We're the 2062 * consumer of the receive ring, so if the bit is clear, 2063 * we have processed all of the packets. 2064 */ 2065 if ((cmdsts & CMDSTS_OWN) == 0) { 2066 /* 2067 * We have processed all of the receive buffers. 2068 */ 2069 break; 2070 } 2071 2072 if (__predict_false(sc->sc_rxdiscard)) { 2073 sip_init_rxdesc(sc, i); 2074 if ((cmdsts & CMDSTS_MORE) == 0) { 2075 /* Reset our state. */ 2076 sc->sc_rxdiscard = 0; 2077 } 2078 continue; 2079 } 2080 2081 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2082 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2083 2084 m = rxs->rxs_mbuf; 2085 2086 /* 2087 * Add a new receive buffer to the ring. 2088 */ 2089 if (sipcom_add_rxbuf(sc, i) != 0) { 2090 /* 2091 * Failed, throw away what we've done so 2092 * far, and discard the rest of the packet. 2093 */ 2094 ifp->if_ierrors++; 2095 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2096 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2097 sip_init_rxdesc(sc, i); 2098 if (cmdsts & CMDSTS_MORE) 2099 sc->sc_rxdiscard = 1; 2100 if (sc->sc_rxhead != NULL) 2101 m_freem(sc->sc_rxhead); 2102 sip_rxchain_reset(sc); 2103 continue; 2104 } 2105 2106 sip_rxchain_link(sc, m); 2107 2108 m->m_len = len; 2109 2110 /* 2111 * If this is not the end of the packet, keep 2112 * looking. 2113 */ 2114 if (cmdsts & CMDSTS_MORE) { 2115 sc->sc_rxlen += len; 2116 continue; 2117 } 2118 2119 /* 2120 * Okay, we have the entire packet now. The chip includes 2121 * the FCS, so we need to trim it. 2122 */ 2123 m->m_len -= ETHER_CRC_LEN; 2124 2125 *sc->sc_rxtailp = NULL; 2126 len = m->m_len + sc->sc_rxlen; 2127 m = sc->sc_rxhead; 2128 2129 sip_rxchain_reset(sc); 2130 2131 /* 2132 * If an error occurred, update stats and drop the packet. 2133 */ 2134 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2135 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2136 ifp->if_ierrors++; 2137 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2138 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2139 /* Receive overrun handled elsewhere. */ 2140 printf("%s: receive descriptor error\n", 2141 device_xname(&sc->sc_dev)); 2142 } 2143 #define PRINTERR(bit, str) \ 2144 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2145 (cmdsts & (bit)) != 0) \ 2146 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2147 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2148 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2149 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2150 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2151 #undef PRINTERR 2152 m_freem(m); 2153 continue; 2154 } 2155 2156 /* 2157 * If the packet is small enough to fit in a 2158 * single header mbuf, allocate one and copy 2159 * the data into it. This greatly reduces 2160 * memory consumption when we receive lots 2161 * of small packets. 2162 */ 2163 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2164 struct mbuf *nm; 2165 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2166 if (nm == NULL) { 2167 ifp->if_ierrors++; 2168 m_freem(m); 2169 continue; 2170 } 2171 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2172 nm->m_data += 2; 2173 nm->m_pkthdr.len = nm->m_len = len; 2174 m_copydata(m, 0, len, mtod(nm, void *)); 2175 m_freem(m); 2176 m = nm; 2177 } 2178 #ifndef __NO_STRICT_ALIGNMENT 2179 else { 2180 /* 2181 * The DP83820's receive buffers must be 4-byte 2182 * aligned. But this means that the data after 2183 * the Ethernet header is misaligned. To compensate, 2184 * we have artificially shortened the buffer size 2185 * in the descriptor, and we do an overlapping copy 2186 * of the data two bytes further in (in the first 2187 * buffer of the chain only). 2188 */ 2189 memmove(mtod(m, char *) + 2, mtod(m, void *), 2190 m->m_len); 2191 m->m_data += 2; 2192 } 2193 #endif /* ! __NO_STRICT_ALIGNMENT */ 2194 2195 /* 2196 * If VLANs are enabled, VLAN packets have been unwrapped 2197 * for us. Associate the tag with the packet. 2198 */ 2199 2200 /* 2201 * Again, byte swapping is tricky. Hardware provided 2202 * the tag in the network byte order, but extsts was 2203 * passed through le32toh() in the meantime. On a 2204 * big-endian machine, we need to swap it again. On a 2205 * little-endian machine, we need to convert from the 2206 * network to host byte order. This means that we must 2207 * swap it in any case, so unconditional swap instead 2208 * of htons() is used. 2209 */ 2210 if ((extsts & EXTSTS_VPKT) != 0) { 2211 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2212 continue); 2213 } 2214 2215 /* 2216 * Set the incoming checksum information for the 2217 * packet. 2218 */ 2219 if ((extsts & EXTSTS_IPPKT) != 0) { 2220 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2221 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2222 if (extsts & EXTSTS_Rx_IPERR) 2223 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2224 if (extsts & EXTSTS_TCPPKT) { 2225 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2226 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2227 if (extsts & EXTSTS_Rx_TCPERR) 2228 m->m_pkthdr.csum_flags |= 2229 M_CSUM_TCP_UDP_BAD; 2230 } else if (extsts & EXTSTS_UDPPKT) { 2231 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2232 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2233 if (extsts & EXTSTS_Rx_UDPERR) 2234 m->m_pkthdr.csum_flags |= 2235 M_CSUM_TCP_UDP_BAD; 2236 } 2237 } 2238 2239 ifp->if_ipackets++; 2240 m->m_pkthdr.rcvif = ifp; 2241 m->m_pkthdr.len = len; 2242 2243 #if NBPFILTER > 0 2244 /* 2245 * Pass this up to any BPF listeners, but only 2246 * pass if up the stack if it's for us. 2247 */ 2248 if (ifp->if_bpf) 2249 bpf_mtap(ifp->if_bpf, m); 2250 #endif /* NBPFILTER > 0 */ 2251 2252 /* Pass it on. */ 2253 (*ifp->if_input)(ifp, m); 2254 } 2255 2256 /* Update the receive pointer. */ 2257 sc->sc_rxptr = i; 2258 } 2259 2260 /* 2261 * sip_rxintr: 2262 * 2263 * Helper; handle receive interrupts on 10/100 parts. 2264 */ 2265 static void 2266 sip_rxintr(struct sip_softc *sc) 2267 { 2268 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2269 struct sip_rxsoft *rxs; 2270 struct mbuf *m; 2271 u_int32_t cmdsts; 2272 int i, len; 2273 2274 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2275 rxs = &sc->sc_rxsoft[i]; 2276 2277 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2278 2279 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2280 2281 /* 2282 * NOTE: OWN is set if owned by _consumer_. We're the 2283 * consumer of the receive ring, so if the bit is clear, 2284 * we have processed all of the packets. 2285 */ 2286 if ((cmdsts & CMDSTS_OWN) == 0) { 2287 /* 2288 * We have processed all of the receive buffers. 2289 */ 2290 break; 2291 } 2292 2293 /* 2294 * If any collisions were seen on the wire, count one. 2295 */ 2296 if (cmdsts & CMDSTS_Rx_COL) 2297 ifp->if_collisions++; 2298 2299 /* 2300 * If an error occurred, update stats, clear the status 2301 * word, and leave the packet buffer in place. It will 2302 * simply be reused the next time the ring comes around. 2303 */ 2304 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2305 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2306 ifp->if_ierrors++; 2307 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2308 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2309 /* Receive overrun handled elsewhere. */ 2310 printf("%s: receive descriptor error\n", 2311 device_xname(&sc->sc_dev)); 2312 } 2313 #define PRINTERR(bit, str) \ 2314 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2315 (cmdsts & (bit)) != 0) \ 2316 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2317 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2318 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2319 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2320 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2321 #undef PRINTERR 2322 sip_init_rxdesc(sc, i); 2323 continue; 2324 } 2325 2326 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2327 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2328 2329 /* 2330 * No errors; receive the packet. Note, the SiS 900 2331 * includes the CRC with every packet. 2332 */ 2333 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2334 2335 #ifdef __NO_STRICT_ALIGNMENT 2336 /* 2337 * If the packet is small enough to fit in a 2338 * single header mbuf, allocate one and copy 2339 * the data into it. This greatly reduces 2340 * memory consumption when we receive lots 2341 * of small packets. 2342 * 2343 * Otherwise, we add a new buffer to the receive 2344 * chain. If this fails, we drop the packet and 2345 * recycle the old buffer. 2346 */ 2347 if (sip_copy_small != 0 && len <= MHLEN) { 2348 MGETHDR(m, M_DONTWAIT, MT_DATA); 2349 if (m == NULL) 2350 goto dropit; 2351 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2352 memcpy(mtod(m, void *), 2353 mtod(rxs->rxs_mbuf, void *), len); 2354 sip_init_rxdesc(sc, i); 2355 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2356 rxs->rxs_dmamap->dm_mapsize, 2357 BUS_DMASYNC_PREREAD); 2358 } else { 2359 m = rxs->rxs_mbuf; 2360 if (sipcom_add_rxbuf(sc, i) != 0) { 2361 dropit: 2362 ifp->if_ierrors++; 2363 sip_init_rxdesc(sc, i); 2364 bus_dmamap_sync(sc->sc_dmat, 2365 rxs->rxs_dmamap, 0, 2366 rxs->rxs_dmamap->dm_mapsize, 2367 BUS_DMASYNC_PREREAD); 2368 continue; 2369 } 2370 } 2371 #else 2372 /* 2373 * The SiS 900's receive buffers must be 4-byte aligned. 2374 * But this means that the data after the Ethernet header 2375 * is misaligned. We must allocate a new buffer and 2376 * copy the data, shifted forward 2 bytes. 2377 */ 2378 MGETHDR(m, M_DONTWAIT, MT_DATA); 2379 if (m == NULL) { 2380 dropit: 2381 ifp->if_ierrors++; 2382 sip_init_rxdesc(sc, i); 2383 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2384 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2385 continue; 2386 } 2387 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2388 if (len > (MHLEN - 2)) { 2389 MCLGET(m, M_DONTWAIT); 2390 if ((m->m_flags & M_EXT) == 0) { 2391 m_freem(m); 2392 goto dropit; 2393 } 2394 } 2395 m->m_data += 2; 2396 2397 /* 2398 * Note that we use clusters for incoming frames, so the 2399 * buffer is virtually contiguous. 2400 */ 2401 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2402 2403 /* Allow the receive descriptor to continue using its mbuf. */ 2404 sip_init_rxdesc(sc, i); 2405 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2406 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2407 #endif /* __NO_STRICT_ALIGNMENT */ 2408 2409 ifp->if_ipackets++; 2410 m->m_pkthdr.rcvif = ifp; 2411 m->m_pkthdr.len = m->m_len = len; 2412 2413 #if NBPFILTER > 0 2414 /* 2415 * Pass this up to any BPF listeners, but only 2416 * pass if up the stack if it's for us. 2417 */ 2418 if (ifp->if_bpf) 2419 bpf_mtap(ifp->if_bpf, m); 2420 #endif /* NBPFILTER > 0 */ 2421 2422 /* Pass it on. */ 2423 (*ifp->if_input)(ifp, m); 2424 } 2425 2426 /* Update the receive pointer. */ 2427 sc->sc_rxptr = i; 2428 } 2429 2430 /* 2431 * sip_tick: 2432 * 2433 * One second timer, used to tick the MII. 2434 */ 2435 static void 2436 sipcom_tick(void *arg) 2437 { 2438 struct sip_softc *sc = arg; 2439 int s; 2440 2441 s = splnet(); 2442 #ifdef SIP_EVENT_COUNTERS 2443 if (sc->sc_gigabit) { 2444 /* Read PAUSE related counts from MIB registers. */ 2445 sc->sc_ev_rxpause.ev_count += 2446 bus_space_read_4(sc->sc_st, sc->sc_sh, 2447 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2448 sc->sc_ev_txpause.ev_count += 2449 bus_space_read_4(sc->sc_st, sc->sc_sh, 2450 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2451 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2452 } 2453 #endif /* SIP_EVENT_COUNTERS */ 2454 mii_tick(&sc->sc_mii); 2455 splx(s); 2456 2457 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2458 } 2459 2460 /* 2461 * sip_reset: 2462 * 2463 * Perform a soft reset on the SiS 900. 2464 */ 2465 static bool 2466 sipcom_reset(struct sip_softc *sc) 2467 { 2468 bus_space_tag_t st = sc->sc_st; 2469 bus_space_handle_t sh = sc->sc_sh; 2470 int i; 2471 2472 bus_space_write_4(st, sh, SIP_IER, 0); 2473 bus_space_write_4(st, sh, SIP_IMR, 0); 2474 bus_space_write_4(st, sh, SIP_RFCR, 0); 2475 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2476 2477 for (i = 0; i < SIP_TIMEOUT; i++) { 2478 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2479 break; 2480 delay(2); 2481 } 2482 2483 if (i == SIP_TIMEOUT) { 2484 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 2485 return false; 2486 } 2487 2488 delay(1000); 2489 2490 if (sc->sc_gigabit) { 2491 /* 2492 * Set the general purpose I/O bits. Do it here in case we 2493 * need to have GPIO set up to talk to the media interface. 2494 */ 2495 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2496 delay(1000); 2497 } 2498 return true; 2499 } 2500 2501 static void 2502 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2503 { 2504 u_int32_t reg; 2505 bus_space_tag_t st = sc->sc_st; 2506 bus_space_handle_t sh = sc->sc_sh; 2507 /* 2508 * Initialize the VLAN/IP receive control register. 2509 * We enable checksum computation on all incoming 2510 * packets, and do not reject packets w/ bad checksums. 2511 */ 2512 reg = 0; 2513 if (capenable & 2514 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2515 reg |= VRCR_IPEN; 2516 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2517 reg |= VRCR_VTDEN|VRCR_VTREN; 2518 bus_space_write_4(st, sh, SIP_VRCR, reg); 2519 2520 /* 2521 * Initialize the VLAN/IP transmit control register. 2522 * We enable outgoing checksum computation on a 2523 * per-packet basis. 2524 */ 2525 reg = 0; 2526 if (capenable & 2527 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2528 reg |= VTCR_PPCHK; 2529 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2530 reg |= VTCR_VPPTI; 2531 bus_space_write_4(st, sh, SIP_VTCR, reg); 2532 2533 /* 2534 * If we're using VLANs, initialize the VLAN data register. 2535 * To understand why we bswap the VLAN Ethertype, see section 2536 * 4.2.36 of the DP83820 manual. 2537 */ 2538 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2539 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2540 } 2541 2542 /* 2543 * sip_init: [ ifnet interface function ] 2544 * 2545 * Initialize the interface. Must be called at splnet(). 2546 */ 2547 static int 2548 sipcom_init(struct ifnet *ifp) 2549 { 2550 struct sip_softc *sc = ifp->if_softc; 2551 bus_space_tag_t st = sc->sc_st; 2552 bus_space_handle_t sh = sc->sc_sh; 2553 struct sip_txsoft *txs; 2554 struct sip_rxsoft *rxs; 2555 struct sip_desc *sipd; 2556 int i, error = 0; 2557 2558 if (device_is_active(&sc->sc_dev)) { 2559 /* 2560 * Cancel any pending I/O. 2561 */ 2562 sipcom_stop(ifp, 0); 2563 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2564 return 0; 2565 2566 /* 2567 * Reset the chip to a known state. 2568 */ 2569 if (!sipcom_reset(sc)) 2570 return EBUSY; 2571 2572 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2573 /* 2574 * DP83815 manual, page 78: 2575 * 4.4 Recommended Registers Configuration 2576 * For optimum performance of the DP83815, version noted 2577 * as DP83815CVNG (SRR = 203h), the listed register 2578 * modifications must be followed in sequence... 2579 * 2580 * It's not clear if this should be 302h or 203h because that 2581 * chip name is listed as SRR 302h in the description of the 2582 * SRR register. However, my revision 302h DP83815 on the 2583 * Netgear FA311 purchased in 02/2001 needs these settings 2584 * to avoid tons of errors in AcceptPerfectMatch (non- 2585 * IFF_PROMISC) mode. I do not know if other revisions need 2586 * this set or not. [briggs -- 09 March 2001] 2587 * 2588 * Note that only the low-order 12 bits of 0xe4 are documented 2589 * and that this sets reserved bits in that register. 2590 */ 2591 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2592 2593 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2594 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2595 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2596 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2597 2598 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2599 } 2600 2601 /* 2602 * Initialize the transmit descriptor ring. 2603 */ 2604 for (i = 0; i < sc->sc_ntxdesc; i++) { 2605 sipd = &sc->sc_txdescs[i]; 2606 memset(sipd, 0, sizeof(struct sip_desc)); 2607 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2608 } 2609 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2610 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2611 sc->sc_txfree = sc->sc_ntxdesc; 2612 sc->sc_txnext = 0; 2613 sc->sc_txwin = 0; 2614 2615 /* 2616 * Initialize the transmit job descriptors. 2617 */ 2618 SIMPLEQ_INIT(&sc->sc_txfreeq); 2619 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2620 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2621 txs = &sc->sc_txsoft[i]; 2622 txs->txs_mbuf = NULL; 2623 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2624 } 2625 2626 /* 2627 * Initialize the receive descriptor and receive job 2628 * descriptor rings. 2629 */ 2630 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2631 rxs = &sc->sc_rxsoft[i]; 2632 if (rxs->rxs_mbuf == NULL) { 2633 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2634 printf("%s: unable to allocate or map rx " 2635 "buffer %d, error = %d\n", 2636 device_xname(&sc->sc_dev), i, error); 2637 /* 2638 * XXX Should attempt to run with fewer receive 2639 * XXX buffers instead of just failing. 2640 */ 2641 sipcom_rxdrain(sc); 2642 goto out; 2643 } 2644 } else 2645 sip_init_rxdesc(sc, i); 2646 } 2647 sc->sc_rxptr = 0; 2648 sc->sc_rxdiscard = 0; 2649 sip_rxchain_reset(sc); 2650 2651 /* 2652 * Set the configuration register; it's already initialized 2653 * in sip_attach(). 2654 */ 2655 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2656 2657 /* 2658 * Initialize the prototype TXCFG register. 2659 */ 2660 if (sc->sc_gigabit) { 2661 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2662 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2663 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2664 SIP_SIS900_REV(sc, SIS_REV_960) || 2665 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2666 (sc->sc_cfg & CFG_EDBMASTEN)) { 2667 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2668 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2669 } else { 2670 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2671 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2672 } 2673 2674 sc->sc_txcfg |= TXCFG_ATP | 2675 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2676 sc->sc_tx_drain_thresh; 2677 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2678 2679 /* 2680 * Initialize the receive drain threshold if we have never 2681 * done so. 2682 */ 2683 if (sc->sc_rx_drain_thresh == 0) { 2684 /* 2685 * XXX This value should be tuned. This is set to the 2686 * maximum of 248 bytes, and we may be able to improve 2687 * performance by decreasing it (although we should never 2688 * set this value lower than 2; 14 bytes are required to 2689 * filter the packet). 2690 */ 2691 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2692 } 2693 2694 /* 2695 * Initialize the prototype RXCFG register. 2696 */ 2697 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2698 /* 2699 * Accept long packets (including FCS) so we can handle 2700 * 802.1q-tagged frames and jumbo frames properly. 2701 */ 2702 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2703 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2704 sc->sc_rxcfg |= RXCFG_ALP; 2705 2706 /* 2707 * Checksum offloading is disabled if the user selects an MTU 2708 * larger than 8109. (FreeBSD says 8152, but there is emperical 2709 * evidence that >8109 does not work on some boards, such as the 2710 * Planex GN-1000TE). 2711 */ 2712 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2713 (ifp->if_capenable & 2714 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2715 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2716 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2717 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2718 "disabled.\n", device_xname(&sc->sc_dev)); 2719 ifp->if_capenable &= 2720 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2721 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2722 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2723 ifp->if_csum_flags_tx = 0; 2724 ifp->if_csum_flags_rx = 0; 2725 } 2726 2727 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2728 2729 if (sc->sc_gigabit) 2730 sipcom_dp83820_init(sc, ifp->if_capenable); 2731 2732 /* 2733 * Give the transmit and receive rings to the chip. 2734 */ 2735 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2736 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2737 2738 /* 2739 * Initialize the interrupt mask. 2740 */ 2741 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2742 sc->sc_bits.b_isr_sserr | 2743 sc->sc_bits.b_isr_rmabt | 2744 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2745 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2746 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2747 2748 /* Set up the receive filter. */ 2749 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2750 2751 /* 2752 * Tune sc_rx_flow_thresh. 2753 * XXX "More than 8KB" is too short for jumbo frames. 2754 * XXX TODO: Threshold value should be user-settable. 2755 */ 2756 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2757 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2758 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2759 2760 /* 2761 * Set the current media. Do this after initializing the prototype 2762 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2763 * control. 2764 */ 2765 if ((error = ether_mediachange(ifp)) != 0) 2766 goto out; 2767 2768 /* 2769 * Set the interrupt hold-off timer to 100us. 2770 */ 2771 if (sc->sc_gigabit) 2772 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2773 2774 /* 2775 * Enable interrupts. 2776 */ 2777 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2778 2779 /* 2780 * Start the transmit and receive processes. 2781 */ 2782 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2783 2784 /* 2785 * Start the one second MII clock. 2786 */ 2787 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2788 2789 /* 2790 * ...all done! 2791 */ 2792 ifp->if_flags |= IFF_RUNNING; 2793 ifp->if_flags &= ~IFF_OACTIVE; 2794 sc->sc_if_flags = ifp->if_flags; 2795 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2796 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2797 sc->sc_prev.if_capenable = ifp->if_capenable; 2798 2799 out: 2800 if (error) 2801 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2802 return (error); 2803 } 2804 2805 /* 2806 * sip_drain: 2807 * 2808 * Drain the receive queue. 2809 */ 2810 static void 2811 sipcom_rxdrain(struct sip_softc *sc) 2812 { 2813 struct sip_rxsoft *rxs; 2814 int i; 2815 2816 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2817 rxs = &sc->sc_rxsoft[i]; 2818 if (rxs->rxs_mbuf != NULL) { 2819 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2820 m_freem(rxs->rxs_mbuf); 2821 rxs->rxs_mbuf = NULL; 2822 } 2823 } 2824 } 2825 2826 /* 2827 * sip_stop: [ ifnet interface function ] 2828 * 2829 * Stop transmission on the interface. 2830 */ 2831 static void 2832 sipcom_stop(struct ifnet *ifp, int disable) 2833 { 2834 struct sip_softc *sc = ifp->if_softc; 2835 bus_space_tag_t st = sc->sc_st; 2836 bus_space_handle_t sh = sc->sc_sh; 2837 struct sip_txsoft *txs; 2838 u_int32_t cmdsts = 0; /* DEBUG */ 2839 2840 /* 2841 * Stop the one second clock. 2842 */ 2843 callout_stop(&sc->sc_tick_ch); 2844 2845 /* Down the MII. */ 2846 mii_down(&sc->sc_mii); 2847 2848 /* 2849 * Disable interrupts. 2850 */ 2851 bus_space_write_4(st, sh, SIP_IER, 0); 2852 2853 /* 2854 * Stop receiver and transmitter. 2855 */ 2856 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2857 2858 /* 2859 * Release any queued transmit buffers. 2860 */ 2861 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2862 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2863 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2864 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2865 CMDSTS_INTR) == 0) 2866 printf("%s: sip_stop: last descriptor does not " 2867 "have INTR bit set\n", device_xname(&sc->sc_dev)); 2868 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2869 #ifdef DIAGNOSTIC 2870 if (txs->txs_mbuf == NULL) { 2871 printf("%s: dirty txsoft with no mbuf chain\n", 2872 device_xname(&sc->sc_dev)); 2873 panic("sip_stop"); 2874 } 2875 #endif 2876 cmdsts |= /* DEBUG */ 2877 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2878 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2879 m_freem(txs->txs_mbuf); 2880 txs->txs_mbuf = NULL; 2881 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2882 } 2883 2884 /* 2885 * Mark the interface down and cancel the watchdog timer. 2886 */ 2887 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2888 ifp->if_timer = 0; 2889 2890 if (disable) 2891 pmf_device_suspend_self(&sc->sc_dev); 2892 2893 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2894 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2895 printf("%s: sip_stop: no INTR bits set in dirty tx " 2896 "descriptors\n", device_xname(&sc->sc_dev)); 2897 } 2898 2899 /* 2900 * sip_read_eeprom: 2901 * 2902 * Read data from the serial EEPROM. 2903 */ 2904 static void 2905 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2906 u_int16_t *data) 2907 { 2908 bus_space_tag_t st = sc->sc_st; 2909 bus_space_handle_t sh = sc->sc_sh; 2910 u_int16_t reg; 2911 int i, x; 2912 2913 for (i = 0; i < wordcnt; i++) { 2914 /* Send CHIP SELECT. */ 2915 reg = EROMAR_EECS; 2916 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2917 2918 /* Shift in the READ opcode. */ 2919 for (x = 3; x > 0; x--) { 2920 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2921 reg |= EROMAR_EEDI; 2922 else 2923 reg &= ~EROMAR_EEDI; 2924 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2925 bus_space_write_4(st, sh, SIP_EROMAR, 2926 reg | EROMAR_EESK); 2927 delay(4); 2928 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2929 delay(4); 2930 } 2931 2932 /* Shift in address. */ 2933 for (x = 6; x > 0; x--) { 2934 if ((word + i) & (1 << (x - 1))) 2935 reg |= EROMAR_EEDI; 2936 else 2937 reg &= ~EROMAR_EEDI; 2938 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2939 bus_space_write_4(st, sh, SIP_EROMAR, 2940 reg | EROMAR_EESK); 2941 delay(4); 2942 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2943 delay(4); 2944 } 2945 2946 /* Shift out data. */ 2947 reg = EROMAR_EECS; 2948 data[i] = 0; 2949 for (x = 16; x > 0; x--) { 2950 bus_space_write_4(st, sh, SIP_EROMAR, 2951 reg | EROMAR_EESK); 2952 delay(4); 2953 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2954 data[i] |= (1 << (x - 1)); 2955 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2956 delay(4); 2957 } 2958 2959 /* Clear CHIP SELECT. */ 2960 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2961 delay(4); 2962 } 2963 } 2964 2965 /* 2966 * sipcom_add_rxbuf: 2967 * 2968 * Add a receive buffer to the indicated descriptor. 2969 */ 2970 static int 2971 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2972 { 2973 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2974 struct mbuf *m; 2975 int error; 2976 2977 MGETHDR(m, M_DONTWAIT, MT_DATA); 2978 if (m == NULL) 2979 return (ENOBUFS); 2980 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2981 2982 MCLGET(m, M_DONTWAIT); 2983 if ((m->m_flags & M_EXT) == 0) { 2984 m_freem(m); 2985 return (ENOBUFS); 2986 } 2987 2988 /* XXX I don't believe this is necessary. --dyoung */ 2989 if (sc->sc_gigabit) 2990 m->m_len = sc->sc_parm->p_rxbuf_len; 2991 2992 if (rxs->rxs_mbuf != NULL) 2993 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2994 2995 rxs->rxs_mbuf = m; 2996 2997 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2998 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2999 BUS_DMA_READ|BUS_DMA_NOWAIT); 3000 if (error) { 3001 printf("%s: can't load rx DMA map %d, error = %d\n", 3002 device_xname(&sc->sc_dev), idx, error); 3003 panic("%s", __func__); /* XXX */ 3004 } 3005 3006 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3007 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3008 3009 sip_init_rxdesc(sc, idx); 3010 3011 return (0); 3012 } 3013 3014 /* 3015 * sip_sis900_set_filter: 3016 * 3017 * Set up the receive filter. 3018 */ 3019 static void 3020 sipcom_sis900_set_filter(struct sip_softc *sc) 3021 { 3022 bus_space_tag_t st = sc->sc_st; 3023 bus_space_handle_t sh = sc->sc_sh; 3024 struct ethercom *ec = &sc->sc_ethercom; 3025 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3026 struct ether_multi *enm; 3027 const u_int8_t *cp; 3028 struct ether_multistep step; 3029 u_int32_t crc, mchash[16]; 3030 3031 /* 3032 * Initialize the prototype RFCR. 3033 */ 3034 sc->sc_rfcr = RFCR_RFEN; 3035 if (ifp->if_flags & IFF_BROADCAST) 3036 sc->sc_rfcr |= RFCR_AAB; 3037 if (ifp->if_flags & IFF_PROMISC) { 3038 sc->sc_rfcr |= RFCR_AAP; 3039 goto allmulti; 3040 } 3041 3042 /* 3043 * Set up the multicast address filter by passing all multicast 3044 * addresses through a CRC generator, and then using the high-order 3045 * 6 bits as an index into the 128 bit multicast hash table (only 3046 * the lower 16 bits of each 32 bit multicast hash register are 3047 * valid). The high order bits select the register, while the 3048 * rest of the bits select the bit within the register. 3049 */ 3050 3051 memset(mchash, 0, sizeof(mchash)); 3052 3053 /* 3054 * SiS900 (at least SiS963) requires us to register the address of 3055 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3056 */ 3057 crc = 0x0ed423f9; 3058 3059 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3060 SIP_SIS900_REV(sc, SIS_REV_960) || 3061 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3062 /* Just want the 8 most significant bits. */ 3063 crc >>= 24; 3064 } else { 3065 /* Just want the 7 most significant bits. */ 3066 crc >>= 25; 3067 } 3068 3069 /* Set the corresponding bit in the hash table. */ 3070 mchash[crc >> 4] |= 1 << (crc & 0xf); 3071 3072 ETHER_FIRST_MULTI(step, ec, enm); 3073 while (enm != NULL) { 3074 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3075 /* 3076 * We must listen to a range of multicast addresses. 3077 * For now, just accept all multicasts, rather than 3078 * trying to set only those filter bits needed to match 3079 * the range. (At this time, the only use of address 3080 * ranges is for IP multicast routing, for which the 3081 * range is big enough to require all bits set.) 3082 */ 3083 goto allmulti; 3084 } 3085 3086 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3087 3088 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3089 SIP_SIS900_REV(sc, SIS_REV_960) || 3090 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3091 /* Just want the 8 most significant bits. */ 3092 crc >>= 24; 3093 } else { 3094 /* Just want the 7 most significant bits. */ 3095 crc >>= 25; 3096 } 3097 3098 /* Set the corresponding bit in the hash table. */ 3099 mchash[crc >> 4] |= 1 << (crc & 0xf); 3100 3101 ETHER_NEXT_MULTI(step, enm); 3102 } 3103 3104 ifp->if_flags &= ~IFF_ALLMULTI; 3105 goto setit; 3106 3107 allmulti: 3108 ifp->if_flags |= IFF_ALLMULTI; 3109 sc->sc_rfcr |= RFCR_AAM; 3110 3111 setit: 3112 #define FILTER_EMIT(addr, data) \ 3113 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3114 delay(1); \ 3115 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3116 delay(1) 3117 3118 /* 3119 * Disable receive filter, and program the node address. 3120 */ 3121 cp = CLLADDR(ifp->if_sadl); 3122 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3123 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3124 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3125 3126 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3127 /* 3128 * Program the multicast hash table. 3129 */ 3130 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3131 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3132 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3133 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3134 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3135 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3136 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3137 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3138 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3139 SIP_SIS900_REV(sc, SIS_REV_960) || 3140 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3141 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3142 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3143 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3144 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3145 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3146 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3147 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3148 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3149 } 3150 } 3151 #undef FILTER_EMIT 3152 3153 /* 3154 * Re-enable the receiver filter. 3155 */ 3156 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3157 } 3158 3159 /* 3160 * sip_dp83815_set_filter: 3161 * 3162 * Set up the receive filter. 3163 */ 3164 static void 3165 sipcom_dp83815_set_filter(struct sip_softc *sc) 3166 { 3167 bus_space_tag_t st = sc->sc_st; 3168 bus_space_handle_t sh = sc->sc_sh; 3169 struct ethercom *ec = &sc->sc_ethercom; 3170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3171 struct ether_multi *enm; 3172 const u_int8_t *cp; 3173 struct ether_multistep step; 3174 u_int32_t crc, hash, slot, bit; 3175 #define MCHASH_NWORDS_83820 128 3176 #define MCHASH_NWORDS_83815 32 3177 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3178 u_int16_t mchash[MCHASH_NWORDS]; 3179 int i; 3180 3181 /* 3182 * Initialize the prototype RFCR. 3183 * Enable the receive filter, and accept on 3184 * Perfect (destination address) Match 3185 * If IFF_BROADCAST, also accept all broadcast packets. 3186 * If IFF_PROMISC, accept all unicast packets (and later, set 3187 * IFF_ALLMULTI and accept all multicast, too). 3188 */ 3189 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3190 if (ifp->if_flags & IFF_BROADCAST) 3191 sc->sc_rfcr |= RFCR_AAB; 3192 if (ifp->if_flags & IFF_PROMISC) { 3193 sc->sc_rfcr |= RFCR_AAP; 3194 goto allmulti; 3195 } 3196 3197 /* 3198 * Set up the DP83820/DP83815 multicast address filter by 3199 * passing all multicast addresses through a CRC generator, 3200 * and then using the high-order 11/9 bits as an index into 3201 * the 2048/512 bit multicast hash table. The high-order 3202 * 7/5 bits select the slot, while the low-order 4 bits 3203 * select the bit within the slot. Note that only the low 3204 * 16-bits of each filter word are used, and there are 3205 * 128/32 filter words. 3206 */ 3207 3208 memset(mchash, 0, sizeof(mchash)); 3209 3210 ifp->if_flags &= ~IFF_ALLMULTI; 3211 ETHER_FIRST_MULTI(step, ec, enm); 3212 if (enm == NULL) 3213 goto setit; 3214 while (enm != NULL) { 3215 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3216 /* 3217 * We must listen to a range of multicast addresses. 3218 * For now, just accept all multicasts, rather than 3219 * trying to set only those filter bits needed to match 3220 * the range. (At this time, the only use of address 3221 * ranges is for IP multicast routing, for which the 3222 * range is big enough to require all bits set.) 3223 */ 3224 goto allmulti; 3225 } 3226 3227 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3228 3229 if (sc->sc_gigabit) { 3230 /* Just want the 11 most significant bits. */ 3231 hash = crc >> 21; 3232 } else { 3233 /* Just want the 9 most significant bits. */ 3234 hash = crc >> 23; 3235 } 3236 3237 slot = hash >> 4; 3238 bit = hash & 0xf; 3239 3240 /* Set the corresponding bit in the hash table. */ 3241 mchash[slot] |= 1 << bit; 3242 3243 ETHER_NEXT_MULTI(step, enm); 3244 } 3245 sc->sc_rfcr |= RFCR_MHEN; 3246 goto setit; 3247 3248 allmulti: 3249 ifp->if_flags |= IFF_ALLMULTI; 3250 sc->sc_rfcr |= RFCR_AAM; 3251 3252 setit: 3253 #define FILTER_EMIT(addr, data) \ 3254 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3255 delay(1); \ 3256 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3257 delay(1) 3258 3259 /* 3260 * Disable receive filter, and program the node address. 3261 */ 3262 cp = CLLADDR(ifp->if_sadl); 3263 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3264 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3265 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3266 3267 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3268 int nwords = 3269 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3270 /* 3271 * Program the multicast hash table. 3272 */ 3273 for (i = 0; i < nwords; i++) { 3274 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3275 } 3276 } 3277 #undef FILTER_EMIT 3278 #undef MCHASH_NWORDS 3279 #undef MCHASH_NWORDS_83815 3280 #undef MCHASH_NWORDS_83820 3281 3282 /* 3283 * Re-enable the receiver filter. 3284 */ 3285 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3286 } 3287 3288 /* 3289 * sip_dp83820_mii_readreg: [mii interface function] 3290 * 3291 * Read a PHY register on the MII of the DP83820. 3292 */ 3293 static int 3294 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3295 { 3296 struct sip_softc *sc = device_private(self); 3297 3298 if (sc->sc_cfg & CFG_TBI_EN) { 3299 bus_addr_t tbireg; 3300 int rv; 3301 3302 if (phy != 0) 3303 return (0); 3304 3305 switch (reg) { 3306 case MII_BMCR: tbireg = SIP_TBICR; break; 3307 case MII_BMSR: tbireg = SIP_TBISR; break; 3308 case MII_ANAR: tbireg = SIP_TANAR; break; 3309 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3310 case MII_ANER: tbireg = SIP_TANER; break; 3311 case MII_EXTSR: 3312 /* 3313 * Don't even bother reading the TESR register. 3314 * The manual documents that the device has 3315 * 1000baseX full/half capability, but the 3316 * register itself seems read back 0 on some 3317 * boards. Just hard-code the result. 3318 */ 3319 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3320 3321 default: 3322 return (0); 3323 } 3324 3325 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3326 if (tbireg == SIP_TBISR) { 3327 /* LINK and ACOMP are switched! */ 3328 int val = rv; 3329 3330 rv = 0; 3331 if (val & TBISR_MR_LINK_STATUS) 3332 rv |= BMSR_LINK; 3333 if (val & TBISR_MR_AN_COMPLETE) 3334 rv |= BMSR_ACOMP; 3335 3336 /* 3337 * The manual claims this register reads back 0 3338 * on hard and soft reset. But we want to let 3339 * the gentbi driver know that we support auto- 3340 * negotiation, so hard-code this bit in the 3341 * result. 3342 */ 3343 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3344 } 3345 3346 return (rv); 3347 } 3348 3349 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3350 } 3351 3352 /* 3353 * sip_dp83820_mii_writereg: [mii interface function] 3354 * 3355 * Write a PHY register on the MII of the DP83820. 3356 */ 3357 static void 3358 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3359 { 3360 struct sip_softc *sc = device_private(self); 3361 3362 if (sc->sc_cfg & CFG_TBI_EN) { 3363 bus_addr_t tbireg; 3364 3365 if (phy != 0) 3366 return; 3367 3368 switch (reg) { 3369 case MII_BMCR: tbireg = SIP_TBICR; break; 3370 case MII_ANAR: tbireg = SIP_TANAR; break; 3371 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3372 default: 3373 return; 3374 } 3375 3376 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3377 return; 3378 } 3379 3380 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3381 } 3382 3383 /* 3384 * sip_dp83820_mii_statchg: [mii interface function] 3385 * 3386 * Callback from MII layer when media changes. 3387 */ 3388 static void 3389 sipcom_dp83820_mii_statchg(device_t self) 3390 { 3391 struct sip_softc *sc = device_private(self); 3392 struct mii_data *mii = &sc->sc_mii; 3393 u_int32_t cfg, pcr; 3394 3395 /* 3396 * Get flow control negotiation result. 3397 */ 3398 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3399 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3400 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3401 mii->mii_media_active &= ~IFM_ETH_FMASK; 3402 } 3403 3404 /* 3405 * Update TXCFG for full-duplex operation. 3406 */ 3407 if ((mii->mii_media_active & IFM_FDX) != 0) 3408 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3409 else 3410 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3411 3412 /* 3413 * Update RXCFG for full-duplex or loopback. 3414 */ 3415 if ((mii->mii_media_active & IFM_FDX) != 0 || 3416 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3417 sc->sc_rxcfg |= RXCFG_ATX; 3418 else 3419 sc->sc_rxcfg &= ~RXCFG_ATX; 3420 3421 /* 3422 * Update CFG for MII/GMII. 3423 */ 3424 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3425 cfg = sc->sc_cfg | CFG_MODE_1000; 3426 else 3427 cfg = sc->sc_cfg; 3428 3429 /* 3430 * 802.3x flow control. 3431 */ 3432 pcr = 0; 3433 if (sc->sc_flowflags & IFM_FLOW) { 3434 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3435 pcr |= sc->sc_rx_flow_thresh; 3436 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3437 pcr |= PCR_PSEN | PCR_PS_MCAST; 3438 } 3439 3440 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3441 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3442 sc->sc_txcfg); 3443 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3444 sc->sc_rxcfg); 3445 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3446 } 3447 3448 /* 3449 * sip_mii_bitbang_read: [mii bit-bang interface function] 3450 * 3451 * Read the MII serial port for the MII bit-bang module. 3452 */ 3453 static u_int32_t 3454 sipcom_mii_bitbang_read(device_t self) 3455 { 3456 struct sip_softc *sc = device_private(self); 3457 3458 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3459 } 3460 3461 /* 3462 * sip_mii_bitbang_write: [mii big-bang interface function] 3463 * 3464 * Write the MII serial port for the MII bit-bang module. 3465 */ 3466 static void 3467 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3468 { 3469 struct sip_softc *sc = device_private(self); 3470 3471 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3472 } 3473 3474 /* 3475 * sip_sis900_mii_readreg: [mii interface function] 3476 * 3477 * Read a PHY register on the MII. 3478 */ 3479 static int 3480 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3481 { 3482 struct sip_softc *sc = device_private(self); 3483 u_int32_t enphy; 3484 3485 /* 3486 * The PHY of recent SiS chipsets is accessed through bitbang 3487 * operations. 3488 */ 3489 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3490 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3491 phy, reg); 3492 3493 #ifndef SIS900_MII_RESTRICT 3494 /* 3495 * The SiS 900 has only an internal PHY on the MII. Only allow 3496 * MII address 0. 3497 */ 3498 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3499 return (0); 3500 #endif 3501 3502 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3503 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3504 ENPHY_RWCMD | ENPHY_ACCESS); 3505 do { 3506 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3507 } while (enphy & ENPHY_ACCESS); 3508 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3509 } 3510 3511 /* 3512 * sip_sis900_mii_writereg: [mii interface function] 3513 * 3514 * Write a PHY register on the MII. 3515 */ 3516 static void 3517 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3518 { 3519 struct sip_softc *sc = device_private(self); 3520 u_int32_t enphy; 3521 3522 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3523 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3524 phy, reg, val); 3525 return; 3526 } 3527 3528 #ifndef SIS900_MII_RESTRICT 3529 /* 3530 * The SiS 900 has only an internal PHY on the MII. Only allow 3531 * MII address 0. 3532 */ 3533 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3534 return; 3535 #endif 3536 3537 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3538 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3539 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3540 do { 3541 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3542 } while (enphy & ENPHY_ACCESS); 3543 } 3544 3545 /* 3546 * sip_sis900_mii_statchg: [mii interface function] 3547 * 3548 * Callback from MII layer when media changes. 3549 */ 3550 static void 3551 sipcom_sis900_mii_statchg(device_t self) 3552 { 3553 struct sip_softc *sc = device_private(self); 3554 struct mii_data *mii = &sc->sc_mii; 3555 u_int32_t flowctl; 3556 3557 /* 3558 * Get flow control negotiation result. 3559 */ 3560 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3561 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3562 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3563 mii->mii_media_active &= ~IFM_ETH_FMASK; 3564 } 3565 3566 /* 3567 * Update TXCFG for full-duplex operation. 3568 */ 3569 if ((mii->mii_media_active & IFM_FDX) != 0) 3570 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3571 else 3572 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3573 3574 /* 3575 * Update RXCFG for full-duplex or loopback. 3576 */ 3577 if ((mii->mii_media_active & IFM_FDX) != 0 || 3578 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3579 sc->sc_rxcfg |= RXCFG_ATX; 3580 else 3581 sc->sc_rxcfg &= ~RXCFG_ATX; 3582 3583 /* 3584 * Update IMR for use of 802.3x flow control. 3585 */ 3586 if (sc->sc_flowflags & IFM_FLOW) { 3587 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3588 flowctl = FLOWCTL_FLOWEN; 3589 } else { 3590 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3591 flowctl = 0; 3592 } 3593 3594 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3595 sc->sc_txcfg); 3596 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3597 sc->sc_rxcfg); 3598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3599 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3600 } 3601 3602 /* 3603 * sip_dp83815_mii_readreg: [mii interface function] 3604 * 3605 * Read a PHY register on the MII. 3606 */ 3607 static int 3608 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3609 { 3610 struct sip_softc *sc = device_private(self); 3611 u_int32_t val; 3612 3613 /* 3614 * The DP83815 only has an internal PHY. Only allow 3615 * MII address 0. 3616 */ 3617 if (phy != 0) 3618 return (0); 3619 3620 /* 3621 * Apparently, after a reset, the DP83815 can take a while 3622 * to respond. During this recovery period, the BMSR returns 3623 * a value of 0. Catch this -- it's not supposed to happen 3624 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3625 * PHY to come back to life. 3626 * 3627 * This works out because the BMSR is the first register 3628 * read during the PHY probe process. 3629 */ 3630 do { 3631 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3632 } while (reg == MII_BMSR && val == 0); 3633 3634 return (val & 0xffff); 3635 } 3636 3637 /* 3638 * sip_dp83815_mii_writereg: [mii interface function] 3639 * 3640 * Write a PHY register to the MII. 3641 */ 3642 static void 3643 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3644 { 3645 struct sip_softc *sc = device_private(self); 3646 3647 /* 3648 * The DP83815 only has an internal PHY. Only allow 3649 * MII address 0. 3650 */ 3651 if (phy != 0) 3652 return; 3653 3654 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3655 } 3656 3657 /* 3658 * sip_dp83815_mii_statchg: [mii interface function] 3659 * 3660 * Callback from MII layer when media changes. 3661 */ 3662 static void 3663 sipcom_dp83815_mii_statchg(device_t self) 3664 { 3665 struct sip_softc *sc = device_private(self); 3666 3667 /* 3668 * Update TXCFG for full-duplex operation. 3669 */ 3670 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3671 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3672 else 3673 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3674 3675 /* 3676 * Update RXCFG for full-duplex or loopback. 3677 */ 3678 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3679 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3680 sc->sc_rxcfg |= RXCFG_ATX; 3681 else 3682 sc->sc_rxcfg &= ~RXCFG_ATX; 3683 3684 /* 3685 * XXX 802.3x flow control. 3686 */ 3687 3688 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3689 sc->sc_txcfg); 3690 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3691 sc->sc_rxcfg); 3692 3693 /* 3694 * Some DP83815s experience problems when used with short 3695 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3696 * sequence adjusts the DSP's signal attenuation to fix the 3697 * problem. 3698 */ 3699 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3700 uint32_t reg; 3701 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3703 3704 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3705 reg &= 0x0fff; 3706 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3707 delay(100); 3708 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3709 reg &= 0x00ff; 3710 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3711 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3712 0x00e8); 3713 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3714 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3715 reg | 0x20); 3716 } 3717 3718 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3719 } 3720 } 3721 3722 static void 3723 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3724 const struct pci_attach_args *pa, u_int8_t *enaddr) 3725 { 3726 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3727 u_int8_t cksum, *e, match; 3728 int i; 3729 3730 /* 3731 * EEPROM data format for the DP83820 can be found in 3732 * the DP83820 manual, section 4.2.4. 3733 */ 3734 3735 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3736 3737 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3738 match = ~(match - 1); 3739 3740 cksum = 0x55; 3741 e = (u_int8_t *) eeprom_data; 3742 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3743 cksum += *e++; 3744 3745 if (cksum != match) 3746 printf("%s: Checksum (%x) mismatch (%x)", 3747 device_xname(&sc->sc_dev), cksum, match); 3748 3749 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3750 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3751 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3752 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3753 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3754 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3755 } 3756 3757 static void 3758 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3759 { 3760 int i; 3761 3762 /* 3763 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3764 * a reason, but I don't know it. 3765 */ 3766 for (i = 0; i < 10; i++) 3767 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3768 } 3769 3770 static void 3771 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3772 const struct pci_attach_args *pa, u_int8_t *enaddr) 3773 { 3774 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3775 3776 switch (sc->sc_rev) { 3777 case SIS_REV_630S: 3778 case SIS_REV_630E: 3779 case SIS_REV_630EA1: 3780 case SIS_REV_630ET: 3781 case SIS_REV_635: 3782 /* 3783 * The MAC address for the on-board Ethernet of 3784 * the SiS 630 chipset is in the NVRAM. Kick 3785 * the chip into re-loading it from NVRAM, and 3786 * read the MAC address out of the filter registers. 3787 */ 3788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3789 3790 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3791 RFCR_RFADDR_NODE0); 3792 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3793 0xffff; 3794 3795 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3796 RFCR_RFADDR_NODE2); 3797 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3798 0xffff; 3799 3800 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3801 RFCR_RFADDR_NODE4); 3802 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3803 0xffff; 3804 break; 3805 3806 case SIS_REV_960: 3807 { 3808 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3809 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3810 3811 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3812 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3813 3814 int waittime, i; 3815 3816 /* Allow to read EEPROM from LAN. It is shared 3817 * between a 1394 controller and the NIC and each 3818 * time we access it, we need to set SIS_EECMD_REQ. 3819 */ 3820 SIS_SET_EROMAR(sc, EROMAR_REQ); 3821 3822 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3823 /* Force EEPROM to idle state. */ 3824 3825 /* 3826 * XXX-cube This is ugly. I'll look for docs about it. 3827 */ 3828 SIS_SET_EROMAR(sc, EROMAR_EECS); 3829 sipcom_sis900_eeprom_delay(sc); 3830 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3831 SIS_SET_EROMAR(sc, EROMAR_EESK); 3832 sipcom_sis900_eeprom_delay(sc); 3833 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3834 sipcom_sis900_eeprom_delay(sc); 3835 } 3836 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3837 sipcom_sis900_eeprom_delay(sc); 3838 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3839 3840 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3841 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3842 sizeof(myea) / sizeof(myea[0]), myea); 3843 break; 3844 } 3845 DELAY(1); 3846 } 3847 3848 /* 3849 * Set SIS_EECTL_CLK to high, so a other master 3850 * can operate on the i2c bus. 3851 */ 3852 SIS_SET_EROMAR(sc, EROMAR_EESK); 3853 3854 /* Refuse EEPROM access by LAN */ 3855 SIS_SET_EROMAR(sc, EROMAR_DONE); 3856 } break; 3857 3858 default: 3859 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3860 sizeof(myea) / sizeof(myea[0]), myea); 3861 } 3862 3863 enaddr[0] = myea[0] & 0xff; 3864 enaddr[1] = myea[0] >> 8; 3865 enaddr[2] = myea[1] & 0xff; 3866 enaddr[3] = myea[1] >> 8; 3867 enaddr[4] = myea[2] & 0xff; 3868 enaddr[5] = myea[2] >> 8; 3869 } 3870 3871 /* Table and macro to bit-reverse an octet. */ 3872 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3873 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3874 3875 static void 3876 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3877 const struct pci_attach_args *pa, u_int8_t *enaddr) 3878 { 3879 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3880 u_int8_t cksum, *e, match; 3881 int i; 3882 3883 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3884 sizeof(eeprom_data[0]), eeprom_data); 3885 3886 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3887 match = ~(match - 1); 3888 3889 cksum = 0x55; 3890 e = (u_int8_t *) eeprom_data; 3891 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3892 cksum += *e++; 3893 } 3894 if (cksum != match) { 3895 printf("%s: Checksum (%x) mismatch (%x)", 3896 device_xname(&sc->sc_dev), cksum, match); 3897 } 3898 3899 /* 3900 * Unrolled because it makes slightly more sense this way. 3901 * The DP83815 stores the MAC address in bit 0 of word 6 3902 * through bit 15 of word 8. 3903 */ 3904 ea = &eeprom_data[6]; 3905 enaddr[0] = ((*ea & 0x1) << 7); 3906 ea++; 3907 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3908 enaddr[1] = ((*ea & 0x1FE) >> 1); 3909 enaddr[2] = ((*ea & 0x1) << 7); 3910 ea++; 3911 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3912 enaddr[3] = ((*ea & 0x1FE) >> 1); 3913 enaddr[4] = ((*ea & 0x1) << 7); 3914 ea++; 3915 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3916 enaddr[5] = ((*ea & 0x1FE) >> 1); 3917 3918 /* 3919 * In case that's not weird enough, we also need to reverse 3920 * the bits in each byte. This all actually makes more sense 3921 * if you think about the EEPROM storage as an array of bits 3922 * being shifted into bytes, but that's not how we're looking 3923 * at it here... 3924 */ 3925 for (i = 0; i < 6 ;i++) 3926 enaddr[i] = bbr(enaddr[i]); 3927 } 3928 3929 /* 3930 * sip_mediastatus: [ifmedia interface function] 3931 * 3932 * Get the current interface media status. 3933 */ 3934 static void 3935 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3936 { 3937 struct sip_softc *sc = ifp->if_softc; 3938 3939 ether_mediastatus(ifp, ifmr); 3940 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3941 sc->sc_flowflags; 3942 } 3943
Indexes created Tue Sep 30 11:09:46 GMT 2025