if_sip.c revision 1.132.4.2
1 /* $NetBSD: if_sip.c,v 1.132.4.2 2009/05/04 08:12:57 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.132.4.2 2009/05/04 08:12:57 yamt Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/queue.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #include <sys/bus.h> 109 #include <sys/intr.h> 110 #include <machine/endian.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 #include <dev/mii/mii_bitbang.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_sipreg.h> 121 122 /* 123 * Transmit descriptor list size. This is arbitrary, but allocate 124 * enough descriptors for 128 pending transmissions, and 8 segments 125 * per packet (64 for DP83820 for jumbo frames). 126 * 127 * This MUST work out to a power of 2. 128 */ 129 #define GSIP_NTXSEGS_ALLOC 16 130 #define SIP_NTXSEGS_ALLOC 8 131 132 #define SIP_TXQUEUELEN 256 133 #define MAX_SIP_NTXDESC \ 134 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 135 136 /* 137 * Receive descriptor list size. We have one Rx buffer per incoming 138 * packet, so this logic is a little simpler. 139 * 140 * Actually, on the DP83820, we allow the packet to consume more than 141 * one buffer, in order to support jumbo Ethernet frames. In that 142 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 143 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 144 * so we'd better be quick about handling receive interrupts. 145 */ 146 #define GSIP_NRXDESC 256 147 #define SIP_NRXDESC 128 148 149 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 150 151 /* 152 * Control structures are DMA'd to the SiS900 chip. We allocate them in 153 * a single clump that maps to a single DMA segment to make several things 154 * easier. 155 */ 156 struct sip_control_data { 157 /* 158 * The transmit descriptors. 159 */ 160 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 161 162 /* 163 * The receive descriptors. 164 */ 165 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 166 }; 167 168 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 169 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 170 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 171 172 /* 173 * Software state for transmit jobs. 174 */ 175 struct sip_txsoft { 176 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 177 bus_dmamap_t txs_dmamap; /* our DMA map */ 178 int txs_firstdesc; /* first descriptor in packet */ 179 int txs_lastdesc; /* last descriptor in packet */ 180 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 181 }; 182 183 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 184 185 /* 186 * Software state for receive jobs. 187 */ 188 struct sip_rxsoft { 189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t rxs_dmamap; /* our DMA map */ 191 }; 192 193 enum sip_attach_stage { 194 SIP_ATTACH_FIN = 0 195 , SIP_ATTACH_CREATE_RXMAP 196 , SIP_ATTACH_CREATE_TXMAP 197 , SIP_ATTACH_LOAD_MAP 198 , SIP_ATTACH_CREATE_MAP 199 , SIP_ATTACH_MAP_MEM 200 , SIP_ATTACH_ALLOC_MEM 201 , SIP_ATTACH_INTR 202 , SIP_ATTACH_MAP 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static int sip_ifflags_cb(struct ethercom *); 563 static void sipcom_start(struct ifnet *); 564 static void sipcom_watchdog(struct ifnet *); 565 static int sipcom_ioctl(struct ifnet *, u_long, void *); 566 static int sipcom_init(struct ifnet *); 567 static void sipcom_stop(struct ifnet *, int); 568 569 static bool sipcom_reset(struct sip_softc *); 570 static void sipcom_rxdrain(struct sip_softc *); 571 static int sipcom_add_rxbuf(struct sip_softc *, int); 572 static void sipcom_read_eeprom(struct sip_softc *, int, int, 573 u_int16_t *); 574 static void sipcom_tick(void *); 575 576 static void sipcom_sis900_set_filter(struct sip_softc *); 577 static void sipcom_dp83815_set_filter(struct sip_softc *); 578 579 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 580 const struct pci_attach_args *, u_int8_t *); 581 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 582 static void sipcom_sis900_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 585 const struct pci_attach_args *, u_int8_t *); 586 587 static int sipcom_intr(void *); 588 static void sipcom_txintr(struct sip_softc *); 589 static void sip_rxintr(struct sip_softc *); 590 static void gsip_rxintr(struct sip_softc *); 591 592 static int sipcom_dp83820_mii_readreg(device_t, int, int); 593 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 594 static void sipcom_dp83820_mii_statchg(device_t); 595 596 static int sipcom_sis900_mii_readreg(device_t, int, int); 597 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 598 static void sipcom_sis900_mii_statchg(device_t); 599 600 static int sipcom_dp83815_mii_readreg(device_t, int, int); 601 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 602 static void sipcom_dp83815_mii_statchg(device_t); 603 604 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 605 606 static int sipcom_match(device_t, struct cfdata *, void *); 607 static void sipcom_attach(device_t, device_t, void *); 608 static void sipcom_do_detach(device_t, enum sip_attach_stage); 609 static int sipcom_detach(device_t, int); 610 static bool sipcom_resume(device_t PMF_FN_PROTO); 611 static bool sipcom_suspend(device_t PMF_FN_PROTO); 612 613 int gsip_copy_small = 0; 614 int sip_copy_small = 0; 615 616 CFATTACH_DECL3(gsip, sizeof(struct sip_softc), 617 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 618 DVF_DETACH_SHUTDOWN); 619 CFATTACH_DECL3(sip, sizeof(struct sip_softc), 620 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 621 DVF_DETACH_SHUTDOWN); 622 623 /* 624 * Descriptions of the variants of the SiS900. 625 */ 626 struct sip_variant { 627 int (*sipv_mii_readreg)(device_t, int, int); 628 void (*sipv_mii_writereg)(device_t, int, int, int); 629 void (*sipv_mii_statchg)(device_t); 630 void (*sipv_set_filter)(struct sip_softc *); 631 void (*sipv_read_macaddr)(struct sip_softc *, 632 const struct pci_attach_args *, u_int8_t *); 633 }; 634 635 static u_int32_t sipcom_mii_bitbang_read(device_t); 636 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 637 638 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 639 sipcom_mii_bitbang_read, 640 sipcom_mii_bitbang_write, 641 { 642 EROMAR_MDIO, /* MII_BIT_MDO */ 643 EROMAR_MDIO, /* MII_BIT_MDI */ 644 EROMAR_MDC, /* MII_BIT_MDC */ 645 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 646 0, /* MII_BIT_DIR_PHY_HOST */ 647 } 648 }; 649 650 static const struct sip_variant sipcom_variant_dp83820 = { 651 sipcom_dp83820_mii_readreg, 652 sipcom_dp83820_mii_writereg, 653 sipcom_dp83820_mii_statchg, 654 sipcom_dp83815_set_filter, 655 sipcom_dp83820_read_macaddr, 656 }; 657 658 static const struct sip_variant sipcom_variant_sis900 = { 659 sipcom_sis900_mii_readreg, 660 sipcom_sis900_mii_writereg, 661 sipcom_sis900_mii_statchg, 662 sipcom_sis900_set_filter, 663 sipcom_sis900_read_macaddr, 664 }; 665 666 static const struct sip_variant sipcom_variant_dp83815 = { 667 sipcom_dp83815_mii_readreg, 668 sipcom_dp83815_mii_writereg, 669 sipcom_dp83815_mii_statchg, 670 sipcom_dp83815_set_filter, 671 sipcom_dp83815_read_macaddr, 672 }; 673 674 675 /* 676 * Devices supported by this driver. 677 */ 678 static const struct sip_product { 679 pci_vendor_id_t sip_vendor; 680 pci_product_id_t sip_product; 681 const char *sip_name; 682 const struct sip_variant *sip_variant; 683 int sip_gigabit; 684 } sipcom_products[] = { 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 686 "NatSemi DP83820 Gigabit Ethernet", 687 &sipcom_variant_dp83820, 1 }, 688 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 689 "SiS 900 10/100 Ethernet", 690 &sipcom_variant_sis900, 0 }, 691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 692 "SiS 7016 10/100 Ethernet", 693 &sipcom_variant_sis900, 0 }, 694 695 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 696 "NatSemi DP83815 10/100 Ethernet", 697 &sipcom_variant_dp83815, 0 }, 698 699 { 0, 0, 700 NULL, 701 NULL, 0 }, 702 }; 703 704 static const struct sip_product * 705 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 706 { 707 const struct sip_product *sip; 708 709 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 710 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 711 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 712 sip->sip_gigabit == gigabit) 713 return sip; 714 } 715 return NULL; 716 } 717 718 /* 719 * I really hate stupid hardware vendors. There's a bit in the EEPROM 720 * which indicates if the card can do 64-bit data transfers. Unfortunately, 721 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 722 * which means we try to use 64-bit data transfers on those cards if we 723 * happen to be plugged into a 32-bit slot. 724 * 725 * What we do is use this table of cards known to be 64-bit cards. If 726 * you have a 64-bit card who's subsystem ID is not listed in this table, 727 * send the output of "pcictl dump ..." of the device to me so that your 728 * card will use the 64-bit data path when plugged into a 64-bit slot. 729 * 730 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 731 * June 30, 2002 732 */ 733 static int 734 sipcom_check_64bit(const struct pci_attach_args *pa) 735 { 736 static const struct { 737 pci_vendor_id_t c64_vendor; 738 pci_product_id_t c64_product; 739 } card64[] = { 740 /* Asante GigaNIX */ 741 { 0x128a, 0x0002 }, 742 743 /* Accton EN1407-T, Planex GN-1000TE */ 744 { 0x1113, 0x1407 }, 745 746 /* Netgear GA-621 */ 747 { 0x1385, 0x621a }, 748 749 /* SMC EZ Card */ 750 { 0x10b8, 0x9462 }, 751 752 { 0, 0} 753 }; 754 pcireg_t subsys; 755 int i; 756 757 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 758 759 for (i = 0; card64[i].c64_vendor != 0; i++) { 760 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 761 PCI_PRODUCT(subsys) == card64[i].c64_product) 762 return (1); 763 } 764 765 return (0); 766 } 767 768 static int 769 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 770 { 771 struct pci_attach_args *pa = aux; 772 773 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 774 return 1; 775 776 return 0; 777 } 778 779 static void 780 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 781 { 782 u_int32_t reg; 783 int i; 784 785 /* 786 * Cause the chip to load configuration data from the EEPROM. 787 */ 788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 789 for (i = 0; i < 10000; i++) { 790 delay(10); 791 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 792 PTSCR_EELOAD_EN) == 0) 793 break; 794 } 795 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 796 PTSCR_EELOAD_EN) { 797 printf("%s: timeout loading configuration from EEPROM\n", 798 device_xname(&sc->sc_dev)); 799 return; 800 } 801 802 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 803 804 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 805 if (reg & CFG_PCI64_DET) { 806 printf("%s: 64-bit PCI slot detected", device_xname(&sc->sc_dev)); 807 /* 808 * Check to see if this card is 64-bit. If so, enable 64-bit 809 * data transfers. 810 * 811 * We can't use the DATA64_EN bit in the EEPROM, because 812 * vendors of 32-bit cards fail to clear that bit in many 813 * cases (yet the card still detects that it's in a 64-bit 814 * slot; go figure). 815 */ 816 if (sipcom_check_64bit(pa)) { 817 sc->sc_cfg |= CFG_DATA64_EN; 818 printf(", using 64-bit data transfers"); 819 } 820 printf("\n"); 821 } 822 823 /* 824 * XXX Need some PCI flags indicating support for 825 * XXX 64-bit addressing. 826 */ 827 #if 0 828 if (reg & CFG_M64ADDR) 829 sc->sc_cfg |= CFG_M64ADDR; 830 if (reg & CFG_T64ADDR) 831 sc->sc_cfg |= CFG_T64ADDR; 832 #endif 833 834 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 835 const char *sep = ""; 836 printf("%s: using ", device_xname(&sc->sc_dev)); 837 if (reg & CFG_EXT_125) { 838 sc->sc_cfg |= CFG_EXT_125; 839 printf("%s125MHz clock", sep); 840 sep = ", "; 841 } 842 if (reg & CFG_TBI_EN) { 843 sc->sc_cfg |= CFG_TBI_EN; 844 printf("%sten-bit interface", sep); 845 sep = ", "; 846 } 847 printf("\n"); 848 } 849 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 850 (reg & CFG_MRM_DIS) != 0) 851 sc->sc_cfg |= CFG_MRM_DIS; 852 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 853 (reg & CFG_MWI_DIS) != 0) 854 sc->sc_cfg |= CFG_MWI_DIS; 855 856 /* 857 * Use the extended descriptor format on the DP83820. This 858 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 859 * checksumming. 860 */ 861 sc->sc_cfg |= CFG_EXTSTS_EN; 862 } 863 864 static int 865 sipcom_detach(device_t self, int flags) 866 { 867 int s; 868 869 s = splnet(); 870 sipcom_do_detach(self, SIP_ATTACH_FIN); 871 splx(s); 872 873 return 0; 874 } 875 876 static void 877 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 878 { 879 int i; 880 struct sip_softc *sc = device_private(self); 881 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 882 883 /* 884 * Free any resources we've allocated during attach. 885 * Do this in reverse order and fall through. 886 */ 887 switch (stage) { 888 case SIP_ATTACH_FIN: 889 sipcom_stop(ifp, 1); 890 pmf_device_deregister(self); 891 #ifdef SIP_EVENT_COUNTERS 892 /* 893 * Attach event counters. 894 */ 895 evcnt_detach(&sc->sc_ev_txforceintr); 896 evcnt_detach(&sc->sc_ev_txdstall); 897 evcnt_detach(&sc->sc_ev_txsstall); 898 evcnt_detach(&sc->sc_ev_hiberr); 899 evcnt_detach(&sc->sc_ev_rxintr); 900 evcnt_detach(&sc->sc_ev_txiintr); 901 evcnt_detach(&sc->sc_ev_txdintr); 902 if (!sc->sc_gigabit) { 903 evcnt_detach(&sc->sc_ev_rxpause); 904 } else { 905 evcnt_detach(&sc->sc_ev_txudpsum); 906 evcnt_detach(&sc->sc_ev_txtcpsum); 907 evcnt_detach(&sc->sc_ev_txipsum); 908 evcnt_detach(&sc->sc_ev_rxudpsum); 909 evcnt_detach(&sc->sc_ev_rxtcpsum); 910 evcnt_detach(&sc->sc_ev_rxipsum); 911 evcnt_detach(&sc->sc_ev_txpause); 912 evcnt_detach(&sc->sc_ev_rxpause); 913 } 914 #endif /* SIP_EVENT_COUNTERS */ 915 916 #if NRND > 0 917 rnd_detach_source(&sc->rnd_source); 918 #endif 919 920 ether_ifdetach(ifp); 921 if_detach(ifp); 922 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 923 924 /*FALLTHROUGH*/ 925 case SIP_ATTACH_CREATE_RXMAP: 926 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 927 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 928 bus_dmamap_destroy(sc->sc_dmat, 929 sc->sc_rxsoft[i].rxs_dmamap); 930 } 931 /*FALLTHROUGH*/ 932 case SIP_ATTACH_CREATE_TXMAP: 933 for (i = 0; i < SIP_TXQUEUELEN; i++) { 934 if (sc->sc_txsoft[i].txs_dmamap != NULL) 935 bus_dmamap_destroy(sc->sc_dmat, 936 sc->sc_txsoft[i].txs_dmamap); 937 } 938 /*FALLTHROUGH*/ 939 case SIP_ATTACH_LOAD_MAP: 940 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_CREATE_MAP: 943 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 944 /*FALLTHROUGH*/ 945 case SIP_ATTACH_MAP_MEM: 946 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 947 sizeof(struct sip_control_data)); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_ALLOC_MEM: 950 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 951 /* FALLTHROUGH*/ 952 case SIP_ATTACH_INTR: 953 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 954 /* FALLTHROUGH*/ 955 case SIP_ATTACH_MAP: 956 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 957 break; 958 default: 959 break; 960 } 961 return; 962 } 963 964 static bool 965 sipcom_resume(device_t self PMF_FN_ARGS) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 return sipcom_reset(sc); 970 } 971 972 static bool 973 sipcom_suspend(device_t self PMF_FN_ARGS) 974 { 975 struct sip_softc *sc = device_private(self); 976 977 sipcom_rxdrain(sc); 978 return true; 979 } 980 981 static void 982 sipcom_attach(device_t parent, device_t self, void *aux) 983 { 984 struct sip_softc *sc = device_private(self); 985 struct pci_attach_args *pa = aux; 986 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 987 pci_chipset_tag_t pc = pa->pa_pc; 988 pci_intr_handle_t ih; 989 const char *intrstr = NULL; 990 bus_space_tag_t iot, memt; 991 bus_space_handle_t ioh, memh; 992 bus_size_t iosz, memsz; 993 int ioh_valid, memh_valid; 994 int i, rseg, error; 995 const struct sip_product *sip; 996 u_int8_t enaddr[ETHER_ADDR_LEN]; 997 pcireg_t csr; 998 pcireg_t memtype; 999 bus_size_t tx_dmamap_size; 1000 int ntxsegs_alloc; 1001 cfdata_t cf = device_cfdata(self); 1002 1003 callout_init(&sc->sc_tick_ch, 0); 1004 1005 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1006 if (sip == NULL) { 1007 printf("\n"); 1008 panic("%s: impossible", __func__); 1009 } 1010 sc->sc_gigabit = sip->sip_gigabit; 1011 1012 sc->sc_pc = pc; 1013 1014 if (sc->sc_gigabit) { 1015 sc->sc_rxintr = gsip_rxintr; 1016 sc->sc_parm = &gsip_parm; 1017 } else { 1018 sc->sc_rxintr = sip_rxintr; 1019 sc->sc_parm = &sip_parm; 1020 } 1021 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1022 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1023 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1024 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1025 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1026 1027 sc->sc_rev = PCI_REVISION(pa->pa_class); 1028 1029 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1030 1031 sc->sc_model = sip; 1032 1033 /* 1034 * XXX Work-around broken PXE firmware on some boards. 1035 * 1036 * The DP83815 shares an address decoder with the MEM BAR 1037 * and the ROM BAR. Make sure the ROM BAR is disabled, 1038 * so that memory mapped access works. 1039 */ 1040 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1041 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1042 ~PCI_MAPREG_ROM_ENABLE); 1043 1044 /* 1045 * Map the device. 1046 */ 1047 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1048 PCI_MAPREG_TYPE_IO, 0, 1049 &iot, &ioh, NULL, &iosz) == 0); 1050 if (sc->sc_gigabit) { 1051 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1052 switch (memtype) { 1053 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1054 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1055 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1056 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1057 break; 1058 default: 1059 memh_valid = 0; 1060 } 1061 } else { 1062 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1063 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1064 &memt, &memh, NULL, &memsz) == 0); 1065 } 1066 1067 if (memh_valid) { 1068 sc->sc_st = memt; 1069 sc->sc_sh = memh; 1070 sc->sc_sz = memsz; 1071 } else if (ioh_valid) { 1072 sc->sc_st = iot; 1073 sc->sc_sh = ioh; 1074 sc->sc_sz = iosz; 1075 } else { 1076 printf("%s: unable to map device registers\n", 1077 device_xname(&sc->sc_dev)); 1078 return; 1079 } 1080 1081 sc->sc_dmat = pa->pa_dmat; 1082 1083 /* 1084 * Make sure bus mastering is enabled. Also make sure 1085 * Write/Invalidate is enabled if we're allowed to use it. 1086 */ 1087 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1088 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1089 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1090 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1091 csr | PCI_COMMAND_MASTER_ENABLE); 1092 1093 /* power up chip */ 1094 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1095 if (error != 0 && error != EOPNOTSUPP) { 1096 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 1097 return; 1098 } 1099 1100 /* 1101 * Map and establish our interrupt. 1102 */ 1103 if (pci_intr_map(pa, &ih)) { 1104 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 1105 return; 1106 } 1107 intrstr = pci_intr_string(pc, ih); 1108 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1109 if (sc->sc_ih == NULL) { 1110 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 1111 if (intrstr != NULL) 1112 printf(" at %s", intrstr); 1113 printf("\n"); 1114 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1115 } 1116 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1117 1118 SIMPLEQ_INIT(&sc->sc_txfreeq); 1119 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1120 1121 /* 1122 * Allocate the control data structures, and create and load the 1123 * DMA map for it. 1124 */ 1125 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1126 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1127 &rseg, 0)) != 0) { 1128 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1129 error); 1130 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1131 } 1132 1133 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1134 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1135 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1136 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1137 error); 1138 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1139 } 1140 1141 if ((error = bus_dmamap_create(sc->sc_dmat, 1142 sizeof(struct sip_control_data), 1, 1143 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1144 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1145 "error = %d\n", error); 1146 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1147 } 1148 1149 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1150 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1151 0)) != 0) { 1152 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1153 error); 1154 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1155 } 1156 1157 /* 1158 * Create the transmit buffer DMA maps. 1159 */ 1160 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1161 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1162 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1163 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1164 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 1165 "error = %d\n", i, error); 1166 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1167 } 1168 } 1169 1170 /* 1171 * Create the receive buffer DMA maps. 1172 */ 1173 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1174 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1175 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1176 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 1177 "error = %d\n", i, error); 1178 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1179 } 1180 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1181 } 1182 1183 /* 1184 * Reset the chip to a known state. 1185 */ 1186 sipcom_reset(sc); 1187 1188 /* 1189 * Read the Ethernet address from the EEPROM. This might 1190 * also fetch other stuff from the EEPROM and stash it 1191 * in the softc. 1192 */ 1193 sc->sc_cfg = 0; 1194 if (!sc->sc_gigabit) { 1195 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1196 SIP_SIS900_REV(sc,SIS_REV_900B)) 1197 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1198 1199 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1200 SIP_SIS900_REV(sc,SIS_REV_960) || 1201 SIP_SIS900_REV(sc,SIS_REV_900B)) 1202 sc->sc_cfg |= 1203 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1204 CFG_EDBMASTEN); 1205 } 1206 1207 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1208 1209 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 1210 ether_sprintf(enaddr)); 1211 1212 /* 1213 * Initialize the configuration register: aggressive PCI 1214 * bus request algorithm, default backoff, default OW timer, 1215 * default parity error detection. 1216 * 1217 * NOTE: "Big endian mode" is useless on the SiS900 and 1218 * friends -- it affects packet data, not descriptors. 1219 */ 1220 if (sc->sc_gigabit) 1221 sipcom_dp83820_attach(sc, pa); 1222 1223 /* 1224 * Initialize our media structures and probe the MII. 1225 */ 1226 sc->sc_mii.mii_ifp = ifp; 1227 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1228 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1229 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1230 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1231 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1232 sipcom_mediastatus); 1233 1234 /* 1235 * XXX We cannot handle flow control on the DP83815. 1236 */ 1237 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1238 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1239 MII_OFFSET_ANY, 0); 1240 else 1241 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1242 MII_OFFSET_ANY, MIIF_DOPAUSE); 1243 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1244 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1246 } else 1247 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1248 1249 ifp = &sc->sc_ethercom.ec_if; 1250 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1251 ifp->if_softc = sc; 1252 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1253 sc->sc_if_flags = ifp->if_flags; 1254 ifp->if_ioctl = sipcom_ioctl; 1255 ifp->if_start = sipcom_start; 1256 ifp->if_watchdog = sipcom_watchdog; 1257 ifp->if_init = sipcom_init; 1258 ifp->if_stop = sipcom_stop; 1259 IFQ_SET_READY(&ifp->if_snd); 1260 1261 /* 1262 * We can support 802.1Q VLAN-sized frames. 1263 */ 1264 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1265 1266 if (sc->sc_gigabit) { 1267 /* 1268 * And the DP83820 can do VLAN tagging in hardware, and 1269 * support the jumbo Ethernet MTU. 1270 */ 1271 sc->sc_ethercom.ec_capabilities |= 1272 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1273 1274 /* 1275 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1276 * in hardware. 1277 */ 1278 ifp->if_capabilities |= 1279 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1280 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1281 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1282 } 1283 1284 /* 1285 * Attach the interface. 1286 */ 1287 if_attach(ifp); 1288 ether_ifattach(ifp, enaddr); 1289 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1290 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1291 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1292 sc->sc_prev.if_capenable = ifp->if_capenable; 1293 #if NRND > 0 1294 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 1295 RND_TYPE_NET, 0); 1296 #endif 1297 1298 /* 1299 * The number of bytes that must be available in 1300 * the Tx FIFO before the bus master can DMA more 1301 * data into the FIFO. 1302 */ 1303 sc->sc_tx_fill_thresh = 64 / 32; 1304 1305 /* 1306 * Start at a drain threshold of 512 bytes. We will 1307 * increase it if a DMA underrun occurs. 1308 * 1309 * XXX The minimum value of this variable should be 1310 * tuned. We may be able to improve performance 1311 * by starting with a lower value. That, however, 1312 * may trash the first few outgoing packets if the 1313 * PCI bus is saturated. 1314 */ 1315 if (sc->sc_gigabit) 1316 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1317 else 1318 sc->sc_tx_drain_thresh = 1504 / 32; 1319 1320 /* 1321 * Initialize the Rx FIFO drain threshold. 1322 * 1323 * This is in units of 8 bytes. 1324 * 1325 * We should never set this value lower than 2; 14 bytes are 1326 * required to filter the packet. 1327 */ 1328 sc->sc_rx_drain_thresh = 128 / 8; 1329 1330 #ifdef SIP_EVENT_COUNTERS 1331 /* 1332 * Attach event counters. 1333 */ 1334 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1335 NULL, device_xname(&sc->sc_dev), "txsstall"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1337 NULL, device_xname(&sc->sc_dev), "txdstall"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(&sc->sc_dev), "txforceintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(&sc->sc_dev), "txdintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(&sc->sc_dev), "txiintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(&sc->sc_dev), "rxintr"); 1346 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1347 NULL, device_xname(&sc->sc_dev), "hiberr"); 1348 if (!sc->sc_gigabit) { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1350 NULL, device_xname(&sc->sc_dev), "rxpause"); 1351 } else { 1352 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1353 NULL, device_xname(&sc->sc_dev), "rxpause"); 1354 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1355 NULL, device_xname(&sc->sc_dev), "txpause"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(&sc->sc_dev), "rxipsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(&sc->sc_dev), "txipsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 1366 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1367 NULL, device_xname(&sc->sc_dev), "txudpsum"); 1368 } 1369 #endif /* SIP_EVENT_COUNTERS */ 1370 1371 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1372 aprint_error_dev(self, "couldn't establish power handler\n"); 1373 else 1374 pmf_class_network_register(self, ifp); 1375 } 1376 1377 static inline void 1378 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1379 uint64_t capenable) 1380 { 1381 struct m_tag *mtag; 1382 u_int32_t extsts; 1383 #ifdef DEBUG 1384 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1385 #endif 1386 /* 1387 * If VLANs are enabled and the packet has a VLAN tag, set 1388 * up the descriptor to encapsulate the packet for us. 1389 * 1390 * This apparently has to be on the last descriptor of 1391 * the packet. 1392 */ 1393 1394 /* 1395 * Byte swapping is tricky. We need to provide the tag 1396 * in a network byte order. On a big-endian machine, 1397 * the byteorder is correct, but we need to swap it 1398 * anyway, because this will be undone by the outside 1399 * htole32(). That's why there must be an 1400 * unconditional swap instead of htons() inside. 1401 */ 1402 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1403 sc->sc_txdescs[lasttx].sipd_extsts |= 1404 htole32(EXTSTS_VPKT | 1405 (bswap16(VLAN_TAG_VALUE(mtag)) & 1406 EXTSTS_VTCI)); 1407 } 1408 1409 /* 1410 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1411 * checksumming, set up the descriptor to do this work 1412 * for us. 1413 * 1414 * This apparently has to be on the first descriptor of 1415 * the packet. 1416 * 1417 * Byte-swap constants so the compiler can optimize. 1418 */ 1419 extsts = 0; 1420 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1421 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1422 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1423 extsts |= htole32(EXTSTS_IPPKT); 1424 } 1425 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1426 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1427 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1428 extsts |= htole32(EXTSTS_TCPPKT); 1429 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1430 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1431 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1432 extsts |= htole32(EXTSTS_UDPPKT); 1433 } 1434 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1435 } 1436 1437 /* 1438 * sip_start: [ifnet interface function] 1439 * 1440 * Start packet transmission on the interface. 1441 */ 1442 static void 1443 sipcom_start(struct ifnet *ifp) 1444 { 1445 struct sip_softc *sc = ifp->if_softc; 1446 struct mbuf *m0; 1447 struct mbuf *m; 1448 struct sip_txsoft *txs; 1449 bus_dmamap_t dmamap; 1450 int error, nexttx, lasttx, seg; 1451 int ofree = sc->sc_txfree; 1452 #if 0 1453 int firsttx = sc->sc_txnext; 1454 #endif 1455 1456 /* 1457 * If we've been told to pause, don't transmit any more packets. 1458 */ 1459 if (!sc->sc_gigabit && sc->sc_paused) 1460 ifp->if_flags |= IFF_OACTIVE; 1461 1462 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1463 return; 1464 1465 /* 1466 * Loop through the send queue, setting up transmit descriptors 1467 * until we drain the queue, or use up all available transmit 1468 * descriptors. 1469 */ 1470 for (;;) { 1471 /* Get a work queue entry. */ 1472 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1473 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1474 break; 1475 } 1476 1477 /* 1478 * Grab a packet off the queue. 1479 */ 1480 IFQ_POLL(&ifp->if_snd, m0); 1481 if (m0 == NULL) 1482 break; 1483 m = NULL; 1484 1485 dmamap = txs->txs_dmamap; 1486 1487 /* 1488 * Load the DMA map. If this fails, the packet either 1489 * didn't fit in the alloted number of segments, or we 1490 * were short on resources. 1491 */ 1492 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1493 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1494 /* In the non-gigabit case, we'll copy and try again. */ 1495 if (error != 0 && !sc->sc_gigabit) { 1496 MGETHDR(m, M_DONTWAIT, MT_DATA); 1497 if (m == NULL) { 1498 printf("%s: unable to allocate Tx mbuf\n", 1499 device_xname(&sc->sc_dev)); 1500 break; 1501 } 1502 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1503 if (m0->m_pkthdr.len > MHLEN) { 1504 MCLGET(m, M_DONTWAIT); 1505 if ((m->m_flags & M_EXT) == 0) { 1506 printf("%s: unable to allocate Tx " 1507 "cluster\n", device_xname(&sc->sc_dev)); 1508 m_freem(m); 1509 break; 1510 } 1511 } 1512 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1513 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1514 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1515 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1516 if (error) { 1517 printf("%s: unable to load Tx buffer, " 1518 "error = %d\n", device_xname(&sc->sc_dev), error); 1519 break; 1520 } 1521 } else if (error == EFBIG) { 1522 /* 1523 * For the too-many-segments case, we simply 1524 * report an error and drop the packet, 1525 * since we can't sanely copy a jumbo packet 1526 * to a single buffer. 1527 */ 1528 printf("%s: Tx packet consumes too many " 1529 "DMA segments, dropping...\n", device_xname(&sc->sc_dev)); 1530 IFQ_DEQUEUE(&ifp->if_snd, m0); 1531 m_freem(m0); 1532 continue; 1533 } else if (error != 0) { 1534 /* 1535 * Short on resources, just stop for now. 1536 */ 1537 break; 1538 } 1539 1540 /* 1541 * Ensure we have enough descriptors free to describe 1542 * the packet. Note, we always reserve one descriptor 1543 * at the end of the ring as a termination point, to 1544 * prevent wrap-around. 1545 */ 1546 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1547 /* 1548 * Not enough free descriptors to transmit this 1549 * packet. We haven't committed anything yet, 1550 * so just unload the DMA map, put the packet 1551 * back on the queue, and punt. Notify the upper 1552 * layer that there are not more slots left. 1553 * 1554 * XXX We could allocate an mbuf and copy, but 1555 * XXX is it worth it? 1556 */ 1557 ifp->if_flags |= IFF_OACTIVE; 1558 bus_dmamap_unload(sc->sc_dmat, dmamap); 1559 if (m != NULL) 1560 m_freem(m); 1561 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1562 break; 1563 } 1564 1565 IFQ_DEQUEUE(&ifp->if_snd, m0); 1566 if (m != NULL) { 1567 m_freem(m0); 1568 m0 = m; 1569 } 1570 1571 /* 1572 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1573 */ 1574 1575 /* Sync the DMA map. */ 1576 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1577 BUS_DMASYNC_PREWRITE); 1578 1579 /* 1580 * Initialize the transmit descriptors. 1581 */ 1582 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1583 seg < dmamap->dm_nsegs; 1584 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1585 /* 1586 * If this is the first descriptor we're 1587 * enqueueing, don't set the OWN bit just 1588 * yet. That could cause a race condition. 1589 * We'll do it below. 1590 */ 1591 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1592 htole32(dmamap->dm_segs[seg].ds_addr); 1593 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1594 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1595 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1596 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1597 lasttx = nexttx; 1598 } 1599 1600 /* Clear the MORE bit on the last segment. */ 1601 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1602 htole32(~CMDSTS_MORE); 1603 1604 /* 1605 * If we're in the interrupt delay window, delay the 1606 * interrupt. 1607 */ 1608 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1609 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1610 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1611 htole32(CMDSTS_INTR); 1612 sc->sc_txwin = 0; 1613 } 1614 1615 if (sc->sc_gigabit) 1616 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1617 1618 /* Sync the descriptors we're using. */ 1619 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1620 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1621 1622 /* 1623 * The entire packet is set up. Give the first descrptor 1624 * to the chip now. 1625 */ 1626 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1627 htole32(CMDSTS_OWN); 1628 sip_cdtxsync(sc, sc->sc_txnext, 1, 1629 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1630 1631 /* 1632 * Store a pointer to the packet so we can free it later, 1633 * and remember what txdirty will be once the packet is 1634 * done. 1635 */ 1636 txs->txs_mbuf = m0; 1637 txs->txs_firstdesc = sc->sc_txnext; 1638 txs->txs_lastdesc = lasttx; 1639 1640 /* Advance the tx pointer. */ 1641 sc->sc_txfree -= dmamap->dm_nsegs; 1642 sc->sc_txnext = nexttx; 1643 1644 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1645 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1646 1647 #if NBPFILTER > 0 1648 /* 1649 * Pass the packet to any BPF listeners. 1650 */ 1651 if (ifp->if_bpf) 1652 bpf_mtap(ifp->if_bpf, m0); 1653 #endif /* NBPFILTER > 0 */ 1654 } 1655 1656 if (txs == NULL || sc->sc_txfree == 0) { 1657 /* No more slots left; notify upper layer. */ 1658 ifp->if_flags |= IFF_OACTIVE; 1659 } 1660 1661 if (sc->sc_txfree != ofree) { 1662 /* 1663 * Start the transmit process. Note, the manual says 1664 * that if there are no pending transmissions in the 1665 * chip's internal queue (indicated by TXE being clear), 1666 * then the driver software must set the TXDP to the 1667 * first descriptor to be transmitted. However, if we 1668 * do this, it causes serious performance degredation on 1669 * the DP83820 under load, not setting TXDP doesn't seem 1670 * to adversely affect the SiS 900 or DP83815. 1671 * 1672 * Well, I guess it wouldn't be the first time a manual 1673 * has lied -- and they could be speaking of the NULL- 1674 * terminated descriptor list case, rather than OWN- 1675 * terminated rings. 1676 */ 1677 #if 0 1678 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1679 CR_TXE) == 0) { 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1681 SIP_CDTXADDR(sc, firsttx)); 1682 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1683 } 1684 #else 1685 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1686 #endif 1687 1688 /* Set a watchdog timer in case the chip flakes out. */ 1689 /* Gigabit autonegotiation takes 5 seconds. */ 1690 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1691 } 1692 } 1693 1694 /* 1695 * sip_watchdog: [ifnet interface function] 1696 * 1697 * Watchdog timer handler. 1698 */ 1699 static void 1700 sipcom_watchdog(struct ifnet *ifp) 1701 { 1702 struct sip_softc *sc = ifp->if_softc; 1703 1704 /* 1705 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1706 * If we get a timeout, try and sweep up transmit descriptors. 1707 * If we manage to sweep them all up, ignore the lack of 1708 * interrupt. 1709 */ 1710 sipcom_txintr(sc); 1711 1712 if (sc->sc_txfree != sc->sc_ntxdesc) { 1713 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1714 ifp->if_oerrors++; 1715 1716 /* Reset the interface. */ 1717 (void) sipcom_init(ifp); 1718 } else if (ifp->if_flags & IFF_DEBUG) 1719 printf("%s: recovered from device timeout\n", 1720 device_xname(&sc->sc_dev)); 1721 1722 /* Try to get more packets going. */ 1723 sipcom_start(ifp); 1724 } 1725 1726 /* If the interface is up and running, only modify the receive 1727 * filter when setting promiscuous or debug mode. Otherwise fall 1728 * through to ether_ioctl, which will reset the chip. 1729 */ 1730 static int 1731 sip_ifflags_cb(struct ethercom *ec) 1732 { 1733 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1734 == (sc)->sc_ethercom.ec_capenable) \ 1735 && ((sc)->sc_prev.is_vlan == \ 1736 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1737 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1738 struct ifnet *ifp = &ec->ec_if; 1739 struct sip_softc *sc = ifp->if_softc; 1740 int change = ifp->if_flags ^ sc->sc_if_flags; 1741 1742 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1743 !COMPARE_IC(sc, ifp)) 1744 return ENETRESET; 1745 /* Set up the receive filter. */ 1746 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1747 return 0; 1748 } 1749 1750 /* 1751 * sip_ioctl: [ifnet interface function] 1752 * 1753 * Handle control requests from the operator. 1754 */ 1755 static int 1756 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1757 { 1758 struct sip_softc *sc = ifp->if_softc; 1759 struct ifreq *ifr = (struct ifreq *)data; 1760 int s, error; 1761 1762 s = splnet(); 1763 1764 switch (cmd) { 1765 case SIOCSIFMEDIA: 1766 /* Flow control requires full-duplex mode. */ 1767 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1768 (ifr->ifr_media & IFM_FDX) == 0) 1769 ifr->ifr_media &= ~IFM_ETH_FMASK; 1770 1771 /* XXX */ 1772 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1773 ifr->ifr_media &= ~IFM_ETH_FMASK; 1774 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1775 if (sc->sc_gigabit && 1776 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1777 /* We can do both TXPAUSE and RXPAUSE. */ 1778 ifr->ifr_media |= 1779 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1780 } else if (ifr->ifr_media & IFM_FLOW) { 1781 /* 1782 * Both TXPAUSE and RXPAUSE must be set. 1783 * (SiS900 and DP83815 don't have PAUSE_ASYM 1784 * feature.) 1785 * 1786 * XXX Can SiS900 and DP83815 send PAUSE? 1787 */ 1788 ifr->ifr_media |= 1789 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1790 } 1791 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1792 } 1793 /*FALLTHROUGH*/ 1794 default: 1795 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1796 break; 1797 1798 error = 0; 1799 1800 if (cmd == SIOCSIFCAP) 1801 error = (*ifp->if_init)(ifp); 1802 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1803 ; 1804 else if (ifp->if_flags & IFF_RUNNING) { 1805 /* 1806 * Multicast list has changed; set the hardware filter 1807 * accordingly. 1808 */ 1809 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1810 } 1811 break; 1812 } 1813 1814 /* Try to get more packets going. */ 1815 sipcom_start(ifp); 1816 1817 sc->sc_if_flags = ifp->if_flags; 1818 splx(s); 1819 return (error); 1820 } 1821 1822 /* 1823 * sip_intr: 1824 * 1825 * Interrupt service routine. 1826 */ 1827 static int 1828 sipcom_intr(void *arg) 1829 { 1830 struct sip_softc *sc = arg; 1831 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1832 u_int32_t isr; 1833 int handled = 0; 1834 1835 if (!device_is_active(&sc->sc_dev)) 1836 return 0; 1837 1838 /* Disable interrupts. */ 1839 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1840 1841 for (;;) { 1842 /* Reading clears interrupt. */ 1843 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1844 if ((isr & sc->sc_imr) == 0) 1845 break; 1846 1847 #if NRND > 0 1848 if (RND_ENABLED(&sc->rnd_source)) 1849 rnd_add_uint32(&sc->rnd_source, isr); 1850 #endif 1851 1852 handled = 1; 1853 1854 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1855 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1856 1857 /* Grab any new packets. */ 1858 (*sc->sc_rxintr)(sc); 1859 1860 if (isr & ISR_RXORN) { 1861 printf("%s: receive FIFO overrun\n", 1862 device_xname(&sc->sc_dev)); 1863 1864 /* XXX adjust rx_drain_thresh? */ 1865 } 1866 1867 if (isr & ISR_RXIDLE) { 1868 printf("%s: receive ring overrun\n", 1869 device_xname(&sc->sc_dev)); 1870 1871 /* Get the receive process going again. */ 1872 bus_space_write_4(sc->sc_st, sc->sc_sh, 1873 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1874 bus_space_write_4(sc->sc_st, sc->sc_sh, 1875 SIP_CR, CR_RXE); 1876 } 1877 } 1878 1879 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1880 #ifdef SIP_EVENT_COUNTERS 1881 if (isr & ISR_TXDESC) 1882 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1883 else if (isr & ISR_TXIDLE) 1884 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1885 #endif 1886 1887 /* Sweep up transmit descriptors. */ 1888 sipcom_txintr(sc); 1889 1890 if (isr & ISR_TXURN) { 1891 u_int32_t thresh; 1892 int txfifo_size = (sc->sc_gigabit) 1893 ? DP83820_SIP_TXFIFO_SIZE 1894 : OTHER_SIP_TXFIFO_SIZE; 1895 1896 printf("%s: transmit FIFO underrun", 1897 device_xname(&sc->sc_dev)); 1898 thresh = sc->sc_tx_drain_thresh + 1; 1899 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1900 && (thresh * 32) <= (txfifo_size - 1901 (sc->sc_tx_fill_thresh * 32))) { 1902 printf("; increasing Tx drain " 1903 "threshold to %u bytes\n", 1904 thresh * 32); 1905 sc->sc_tx_drain_thresh = thresh; 1906 (void) sipcom_init(ifp); 1907 } else { 1908 (void) sipcom_init(ifp); 1909 printf("\n"); 1910 } 1911 } 1912 } 1913 1914 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1915 if (isr & ISR_PAUSE_ST) { 1916 sc->sc_paused = 1; 1917 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1918 ifp->if_flags |= IFF_OACTIVE; 1919 } 1920 if (isr & ISR_PAUSE_END) { 1921 sc->sc_paused = 0; 1922 ifp->if_flags &= ~IFF_OACTIVE; 1923 } 1924 } 1925 1926 if (isr & ISR_HIBERR) { 1927 int want_init = 0; 1928 1929 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1930 1931 #define PRINTERR(bit, str) \ 1932 do { \ 1933 if ((isr & (bit)) != 0) { \ 1934 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1935 printf("%s: %s\n", \ 1936 device_xname(&sc->sc_dev), str); \ 1937 want_init = 1; \ 1938 } \ 1939 } while (/*CONSTCOND*/0) 1940 1941 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1942 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1943 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1944 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1945 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1946 /* 1947 * Ignore: 1948 * Tx reset complete 1949 * Rx reset complete 1950 */ 1951 if (want_init) 1952 (void) sipcom_init(ifp); 1953 #undef PRINTERR 1954 } 1955 } 1956 1957 /* Re-enable interrupts. */ 1958 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1959 1960 /* Try to get more packets going. */ 1961 sipcom_start(ifp); 1962 1963 return (handled); 1964 } 1965 1966 /* 1967 * sip_txintr: 1968 * 1969 * Helper; handle transmit interrupts. 1970 */ 1971 static void 1972 sipcom_txintr(struct sip_softc *sc) 1973 { 1974 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1975 struct sip_txsoft *txs; 1976 u_int32_t cmdsts; 1977 1978 if (sc->sc_paused == 0) 1979 ifp->if_flags &= ~IFF_OACTIVE; 1980 1981 /* 1982 * Go through our Tx list and free mbufs for those 1983 * frames which have been transmitted. 1984 */ 1985 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1986 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1987 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1988 1989 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1990 if (cmdsts & CMDSTS_OWN) 1991 break; 1992 1993 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1994 1995 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1996 1997 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1998 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1999 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2000 m_freem(txs->txs_mbuf); 2001 txs->txs_mbuf = NULL; 2002 2003 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2004 2005 /* 2006 * Check for errors and collisions. 2007 */ 2008 if (cmdsts & 2009 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2010 ifp->if_oerrors++; 2011 if (cmdsts & CMDSTS_Tx_EC) 2012 ifp->if_collisions += 16; 2013 if (ifp->if_flags & IFF_DEBUG) { 2014 if (cmdsts & CMDSTS_Tx_ED) 2015 printf("%s: excessive deferral\n", 2016 device_xname(&sc->sc_dev)); 2017 if (cmdsts & CMDSTS_Tx_EC) 2018 printf("%s: excessive collisions\n", 2019 device_xname(&sc->sc_dev)); 2020 } 2021 } else { 2022 /* Packet was transmitted successfully. */ 2023 ifp->if_opackets++; 2024 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2025 } 2026 } 2027 2028 /* 2029 * If there are no more pending transmissions, cancel the watchdog 2030 * timer. 2031 */ 2032 if (txs == NULL) { 2033 ifp->if_timer = 0; 2034 sc->sc_txwin = 0; 2035 } 2036 } 2037 2038 /* 2039 * gsip_rxintr: 2040 * 2041 * Helper; handle receive interrupts on gigabit parts. 2042 */ 2043 static void 2044 gsip_rxintr(struct sip_softc *sc) 2045 { 2046 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2047 struct sip_rxsoft *rxs; 2048 struct mbuf *m; 2049 u_int32_t cmdsts, extsts; 2050 int i, len; 2051 2052 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2053 rxs = &sc->sc_rxsoft[i]; 2054 2055 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2056 2057 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2058 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2059 len = CMDSTS_SIZE(sc, cmdsts); 2060 2061 /* 2062 * NOTE: OWN is set if owned by _consumer_. We're the 2063 * consumer of the receive ring, so if the bit is clear, 2064 * we have processed all of the packets. 2065 */ 2066 if ((cmdsts & CMDSTS_OWN) == 0) { 2067 /* 2068 * We have processed all of the receive buffers. 2069 */ 2070 break; 2071 } 2072 2073 if (__predict_false(sc->sc_rxdiscard)) { 2074 sip_init_rxdesc(sc, i); 2075 if ((cmdsts & CMDSTS_MORE) == 0) { 2076 /* Reset our state. */ 2077 sc->sc_rxdiscard = 0; 2078 } 2079 continue; 2080 } 2081 2082 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2083 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2084 2085 m = rxs->rxs_mbuf; 2086 2087 /* 2088 * Add a new receive buffer to the ring. 2089 */ 2090 if (sipcom_add_rxbuf(sc, i) != 0) { 2091 /* 2092 * Failed, throw away what we've done so 2093 * far, and discard the rest of the packet. 2094 */ 2095 ifp->if_ierrors++; 2096 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2097 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2098 sip_init_rxdesc(sc, i); 2099 if (cmdsts & CMDSTS_MORE) 2100 sc->sc_rxdiscard = 1; 2101 if (sc->sc_rxhead != NULL) 2102 m_freem(sc->sc_rxhead); 2103 sip_rxchain_reset(sc); 2104 continue; 2105 } 2106 2107 sip_rxchain_link(sc, m); 2108 2109 m->m_len = len; 2110 2111 /* 2112 * If this is not the end of the packet, keep 2113 * looking. 2114 */ 2115 if (cmdsts & CMDSTS_MORE) { 2116 sc->sc_rxlen += len; 2117 continue; 2118 } 2119 2120 /* 2121 * Okay, we have the entire packet now. The chip includes 2122 * the FCS, so we need to trim it. 2123 */ 2124 m->m_len -= ETHER_CRC_LEN; 2125 2126 *sc->sc_rxtailp = NULL; 2127 len = m->m_len + sc->sc_rxlen; 2128 m = sc->sc_rxhead; 2129 2130 sip_rxchain_reset(sc); 2131 2132 /* 2133 * If an error occurred, update stats and drop the packet. 2134 */ 2135 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2136 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2137 ifp->if_ierrors++; 2138 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2139 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2140 /* Receive overrun handled elsewhere. */ 2141 printf("%s: receive descriptor error\n", 2142 device_xname(&sc->sc_dev)); 2143 } 2144 #define PRINTERR(bit, str) \ 2145 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2146 (cmdsts & (bit)) != 0) \ 2147 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2148 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2149 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2150 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2151 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2152 #undef PRINTERR 2153 m_freem(m); 2154 continue; 2155 } 2156 2157 /* 2158 * If the packet is small enough to fit in a 2159 * single header mbuf, allocate one and copy 2160 * the data into it. This greatly reduces 2161 * memory consumption when we receive lots 2162 * of small packets. 2163 */ 2164 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2165 struct mbuf *nm; 2166 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2167 if (nm == NULL) { 2168 ifp->if_ierrors++; 2169 m_freem(m); 2170 continue; 2171 } 2172 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2173 nm->m_data += 2; 2174 nm->m_pkthdr.len = nm->m_len = len; 2175 m_copydata(m, 0, len, mtod(nm, void *)); 2176 m_freem(m); 2177 m = nm; 2178 } 2179 #ifndef __NO_STRICT_ALIGNMENT 2180 else { 2181 /* 2182 * The DP83820's receive buffers must be 4-byte 2183 * aligned. But this means that the data after 2184 * the Ethernet header is misaligned. To compensate, 2185 * we have artificially shortened the buffer size 2186 * in the descriptor, and we do an overlapping copy 2187 * of the data two bytes further in (in the first 2188 * buffer of the chain only). 2189 */ 2190 memmove(mtod(m, char *) + 2, mtod(m, void *), 2191 m->m_len); 2192 m->m_data += 2; 2193 } 2194 #endif /* ! __NO_STRICT_ALIGNMENT */ 2195 2196 /* 2197 * If VLANs are enabled, VLAN packets have been unwrapped 2198 * for us. Associate the tag with the packet. 2199 */ 2200 2201 /* 2202 * Again, byte swapping is tricky. Hardware provided 2203 * the tag in the network byte order, but extsts was 2204 * passed through le32toh() in the meantime. On a 2205 * big-endian machine, we need to swap it again. On a 2206 * little-endian machine, we need to convert from the 2207 * network to host byte order. This means that we must 2208 * swap it in any case, so unconditional swap instead 2209 * of htons() is used. 2210 */ 2211 if ((extsts & EXTSTS_VPKT) != 0) { 2212 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2213 continue); 2214 } 2215 2216 /* 2217 * Set the incoming checksum information for the 2218 * packet. 2219 */ 2220 if ((extsts & EXTSTS_IPPKT) != 0) { 2221 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2222 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2223 if (extsts & EXTSTS_Rx_IPERR) 2224 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2225 if (extsts & EXTSTS_TCPPKT) { 2226 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2227 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2228 if (extsts & EXTSTS_Rx_TCPERR) 2229 m->m_pkthdr.csum_flags |= 2230 M_CSUM_TCP_UDP_BAD; 2231 } else if (extsts & EXTSTS_UDPPKT) { 2232 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2233 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2234 if (extsts & EXTSTS_Rx_UDPERR) 2235 m->m_pkthdr.csum_flags |= 2236 M_CSUM_TCP_UDP_BAD; 2237 } 2238 } 2239 2240 ifp->if_ipackets++; 2241 m->m_pkthdr.rcvif = ifp; 2242 m->m_pkthdr.len = len; 2243 2244 #if NBPFILTER > 0 2245 /* 2246 * Pass this up to any BPF listeners, but only 2247 * pass if up the stack if it's for us. 2248 */ 2249 if (ifp->if_bpf) 2250 bpf_mtap(ifp->if_bpf, m); 2251 #endif /* NBPFILTER > 0 */ 2252 2253 /* Pass it on. */ 2254 (*ifp->if_input)(ifp, m); 2255 } 2256 2257 /* Update the receive pointer. */ 2258 sc->sc_rxptr = i; 2259 } 2260 2261 /* 2262 * sip_rxintr: 2263 * 2264 * Helper; handle receive interrupts on 10/100 parts. 2265 */ 2266 static void 2267 sip_rxintr(struct sip_softc *sc) 2268 { 2269 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2270 struct sip_rxsoft *rxs; 2271 struct mbuf *m; 2272 u_int32_t cmdsts; 2273 int i, len; 2274 2275 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2276 rxs = &sc->sc_rxsoft[i]; 2277 2278 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2279 2280 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2281 2282 /* 2283 * NOTE: OWN is set if owned by _consumer_. We're the 2284 * consumer of the receive ring, so if the bit is clear, 2285 * we have processed all of the packets. 2286 */ 2287 if ((cmdsts & CMDSTS_OWN) == 0) { 2288 /* 2289 * We have processed all of the receive buffers. 2290 */ 2291 break; 2292 } 2293 2294 /* 2295 * If any collisions were seen on the wire, count one. 2296 */ 2297 if (cmdsts & CMDSTS_Rx_COL) 2298 ifp->if_collisions++; 2299 2300 /* 2301 * If an error occurred, update stats, clear the status 2302 * word, and leave the packet buffer in place. It will 2303 * simply be reused the next time the ring comes around. 2304 */ 2305 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2306 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2307 ifp->if_ierrors++; 2308 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2309 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2310 /* Receive overrun handled elsewhere. */ 2311 printf("%s: receive descriptor error\n", 2312 device_xname(&sc->sc_dev)); 2313 } 2314 #define PRINTERR(bit, str) \ 2315 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2316 (cmdsts & (bit)) != 0) \ 2317 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2318 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2319 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2320 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2321 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2322 #undef PRINTERR 2323 sip_init_rxdesc(sc, i); 2324 continue; 2325 } 2326 2327 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2328 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2329 2330 /* 2331 * No errors; receive the packet. Note, the SiS 900 2332 * includes the CRC with every packet. 2333 */ 2334 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2335 2336 #ifdef __NO_STRICT_ALIGNMENT 2337 /* 2338 * If the packet is small enough to fit in a 2339 * single header mbuf, allocate one and copy 2340 * the data into it. This greatly reduces 2341 * memory consumption when we receive lots 2342 * of small packets. 2343 * 2344 * Otherwise, we add a new buffer to the receive 2345 * chain. If this fails, we drop the packet and 2346 * recycle the old buffer. 2347 */ 2348 if (sip_copy_small != 0 && len <= MHLEN) { 2349 MGETHDR(m, M_DONTWAIT, MT_DATA); 2350 if (m == NULL) 2351 goto dropit; 2352 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2353 memcpy(mtod(m, void *), 2354 mtod(rxs->rxs_mbuf, void *), len); 2355 sip_init_rxdesc(sc, i); 2356 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2357 rxs->rxs_dmamap->dm_mapsize, 2358 BUS_DMASYNC_PREREAD); 2359 } else { 2360 m = rxs->rxs_mbuf; 2361 if (sipcom_add_rxbuf(sc, i) != 0) { 2362 dropit: 2363 ifp->if_ierrors++; 2364 sip_init_rxdesc(sc, i); 2365 bus_dmamap_sync(sc->sc_dmat, 2366 rxs->rxs_dmamap, 0, 2367 rxs->rxs_dmamap->dm_mapsize, 2368 BUS_DMASYNC_PREREAD); 2369 continue; 2370 } 2371 } 2372 #else 2373 /* 2374 * The SiS 900's receive buffers must be 4-byte aligned. 2375 * But this means that the data after the Ethernet header 2376 * is misaligned. We must allocate a new buffer and 2377 * copy the data, shifted forward 2 bytes. 2378 */ 2379 MGETHDR(m, M_DONTWAIT, MT_DATA); 2380 if (m == NULL) { 2381 dropit: 2382 ifp->if_ierrors++; 2383 sip_init_rxdesc(sc, i); 2384 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2385 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2386 continue; 2387 } 2388 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2389 if (len > (MHLEN - 2)) { 2390 MCLGET(m, M_DONTWAIT); 2391 if ((m->m_flags & M_EXT) == 0) { 2392 m_freem(m); 2393 goto dropit; 2394 } 2395 } 2396 m->m_data += 2; 2397 2398 /* 2399 * Note that we use clusters for incoming frames, so the 2400 * buffer is virtually contiguous. 2401 */ 2402 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2403 2404 /* Allow the receive descriptor to continue using its mbuf. */ 2405 sip_init_rxdesc(sc, i); 2406 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2407 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2408 #endif /* __NO_STRICT_ALIGNMENT */ 2409 2410 ifp->if_ipackets++; 2411 m->m_pkthdr.rcvif = ifp; 2412 m->m_pkthdr.len = m->m_len = len; 2413 2414 #if NBPFILTER > 0 2415 /* 2416 * Pass this up to any BPF listeners, but only 2417 * pass if up the stack if it's for us. 2418 */ 2419 if (ifp->if_bpf) 2420 bpf_mtap(ifp->if_bpf, m); 2421 #endif /* NBPFILTER > 0 */ 2422 2423 /* Pass it on. */ 2424 (*ifp->if_input)(ifp, m); 2425 } 2426 2427 /* Update the receive pointer. */ 2428 sc->sc_rxptr = i; 2429 } 2430 2431 /* 2432 * sip_tick: 2433 * 2434 * One second timer, used to tick the MII. 2435 */ 2436 static void 2437 sipcom_tick(void *arg) 2438 { 2439 struct sip_softc *sc = arg; 2440 int s; 2441 2442 s = splnet(); 2443 #ifdef SIP_EVENT_COUNTERS 2444 if (sc->sc_gigabit) { 2445 /* Read PAUSE related counts from MIB registers. */ 2446 sc->sc_ev_rxpause.ev_count += 2447 bus_space_read_4(sc->sc_st, sc->sc_sh, 2448 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2449 sc->sc_ev_txpause.ev_count += 2450 bus_space_read_4(sc->sc_st, sc->sc_sh, 2451 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2453 } 2454 #endif /* SIP_EVENT_COUNTERS */ 2455 mii_tick(&sc->sc_mii); 2456 splx(s); 2457 2458 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2459 } 2460 2461 /* 2462 * sip_reset: 2463 * 2464 * Perform a soft reset on the SiS 900. 2465 */ 2466 static bool 2467 sipcom_reset(struct sip_softc *sc) 2468 { 2469 bus_space_tag_t st = sc->sc_st; 2470 bus_space_handle_t sh = sc->sc_sh; 2471 int i; 2472 2473 bus_space_write_4(st, sh, SIP_IER, 0); 2474 bus_space_write_4(st, sh, SIP_IMR, 0); 2475 bus_space_write_4(st, sh, SIP_RFCR, 0); 2476 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2477 2478 for (i = 0; i < SIP_TIMEOUT; i++) { 2479 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2480 break; 2481 delay(2); 2482 } 2483 2484 if (i == SIP_TIMEOUT) { 2485 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 2486 return false; 2487 } 2488 2489 delay(1000); 2490 2491 if (sc->sc_gigabit) { 2492 /* 2493 * Set the general purpose I/O bits. Do it here in case we 2494 * need to have GPIO set up to talk to the media interface. 2495 */ 2496 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2497 delay(1000); 2498 } 2499 return true; 2500 } 2501 2502 static void 2503 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2504 { 2505 u_int32_t reg; 2506 bus_space_tag_t st = sc->sc_st; 2507 bus_space_handle_t sh = sc->sc_sh; 2508 /* 2509 * Initialize the VLAN/IP receive control register. 2510 * We enable checksum computation on all incoming 2511 * packets, and do not reject packets w/ bad checksums. 2512 */ 2513 reg = 0; 2514 if (capenable & 2515 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2516 reg |= VRCR_IPEN; 2517 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2518 reg |= VRCR_VTDEN|VRCR_VTREN; 2519 bus_space_write_4(st, sh, SIP_VRCR, reg); 2520 2521 /* 2522 * Initialize the VLAN/IP transmit control register. 2523 * We enable outgoing checksum computation on a 2524 * per-packet basis. 2525 */ 2526 reg = 0; 2527 if (capenable & 2528 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2529 reg |= VTCR_PPCHK; 2530 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2531 reg |= VTCR_VPPTI; 2532 bus_space_write_4(st, sh, SIP_VTCR, reg); 2533 2534 /* 2535 * If we're using VLANs, initialize the VLAN data register. 2536 * To understand why we bswap the VLAN Ethertype, see section 2537 * 4.2.36 of the DP83820 manual. 2538 */ 2539 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2540 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2541 } 2542 2543 /* 2544 * sip_init: [ ifnet interface function ] 2545 * 2546 * Initialize the interface. Must be called at splnet(). 2547 */ 2548 static int 2549 sipcom_init(struct ifnet *ifp) 2550 { 2551 struct sip_softc *sc = ifp->if_softc; 2552 bus_space_tag_t st = sc->sc_st; 2553 bus_space_handle_t sh = sc->sc_sh; 2554 struct sip_txsoft *txs; 2555 struct sip_rxsoft *rxs; 2556 struct sip_desc *sipd; 2557 int i, error = 0; 2558 2559 if (device_is_active(&sc->sc_dev)) { 2560 /* 2561 * Cancel any pending I/O. 2562 */ 2563 sipcom_stop(ifp, 0); 2564 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2565 return 0; 2566 2567 /* 2568 * Reset the chip to a known state. 2569 */ 2570 if (!sipcom_reset(sc)) 2571 return EBUSY; 2572 2573 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2574 /* 2575 * DP83815 manual, page 78: 2576 * 4.4 Recommended Registers Configuration 2577 * For optimum performance of the DP83815, version noted 2578 * as DP83815CVNG (SRR = 203h), the listed register 2579 * modifications must be followed in sequence... 2580 * 2581 * It's not clear if this should be 302h or 203h because that 2582 * chip name is listed as SRR 302h in the description of the 2583 * SRR register. However, my revision 302h DP83815 on the 2584 * Netgear FA311 purchased in 02/2001 needs these settings 2585 * to avoid tons of errors in AcceptPerfectMatch (non- 2586 * IFF_PROMISC) mode. I do not know if other revisions need 2587 * this set or not. [briggs -- 09 March 2001] 2588 * 2589 * Note that only the low-order 12 bits of 0xe4 are documented 2590 * and that this sets reserved bits in that register. 2591 */ 2592 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2593 2594 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2595 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2596 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2597 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2598 2599 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2600 } 2601 2602 /* 2603 * Initialize the transmit descriptor ring. 2604 */ 2605 for (i = 0; i < sc->sc_ntxdesc; i++) { 2606 sipd = &sc->sc_txdescs[i]; 2607 memset(sipd, 0, sizeof(struct sip_desc)); 2608 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2609 } 2610 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2611 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2612 sc->sc_txfree = sc->sc_ntxdesc; 2613 sc->sc_txnext = 0; 2614 sc->sc_txwin = 0; 2615 2616 /* 2617 * Initialize the transmit job descriptors. 2618 */ 2619 SIMPLEQ_INIT(&sc->sc_txfreeq); 2620 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2621 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2622 txs = &sc->sc_txsoft[i]; 2623 txs->txs_mbuf = NULL; 2624 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2625 } 2626 2627 /* 2628 * Initialize the receive descriptor and receive job 2629 * descriptor rings. 2630 */ 2631 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2632 rxs = &sc->sc_rxsoft[i]; 2633 if (rxs->rxs_mbuf == NULL) { 2634 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2635 printf("%s: unable to allocate or map rx " 2636 "buffer %d, error = %d\n", 2637 device_xname(&sc->sc_dev), i, error); 2638 /* 2639 * XXX Should attempt to run with fewer receive 2640 * XXX buffers instead of just failing. 2641 */ 2642 sipcom_rxdrain(sc); 2643 goto out; 2644 } 2645 } else 2646 sip_init_rxdesc(sc, i); 2647 } 2648 sc->sc_rxptr = 0; 2649 sc->sc_rxdiscard = 0; 2650 sip_rxchain_reset(sc); 2651 2652 /* 2653 * Set the configuration register; it's already initialized 2654 * in sip_attach(). 2655 */ 2656 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2657 2658 /* 2659 * Initialize the prototype TXCFG register. 2660 */ 2661 if (sc->sc_gigabit) { 2662 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2663 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2664 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2665 SIP_SIS900_REV(sc, SIS_REV_960) || 2666 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2667 (sc->sc_cfg & CFG_EDBMASTEN)) { 2668 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2669 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2670 } else { 2671 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2672 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2673 } 2674 2675 sc->sc_txcfg |= TXCFG_ATP | 2676 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2677 sc->sc_tx_drain_thresh; 2678 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2679 2680 /* 2681 * Initialize the receive drain threshold if we have never 2682 * done so. 2683 */ 2684 if (sc->sc_rx_drain_thresh == 0) { 2685 /* 2686 * XXX This value should be tuned. This is set to the 2687 * maximum of 248 bytes, and we may be able to improve 2688 * performance by decreasing it (although we should never 2689 * set this value lower than 2; 14 bytes are required to 2690 * filter the packet). 2691 */ 2692 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2693 } 2694 2695 /* 2696 * Initialize the prototype RXCFG register. 2697 */ 2698 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2699 /* 2700 * Accept long packets (including FCS) so we can handle 2701 * 802.1q-tagged frames and jumbo frames properly. 2702 */ 2703 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2704 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2705 sc->sc_rxcfg |= RXCFG_ALP; 2706 2707 /* 2708 * Checksum offloading is disabled if the user selects an MTU 2709 * larger than 8109. (FreeBSD says 8152, but there is emperical 2710 * evidence that >8109 does not work on some boards, such as the 2711 * Planex GN-1000TE). 2712 */ 2713 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2714 (ifp->if_capenable & 2715 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2716 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2717 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2718 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2719 "disabled.\n", device_xname(&sc->sc_dev)); 2720 ifp->if_capenable &= 2721 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2722 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2723 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2724 ifp->if_csum_flags_tx = 0; 2725 ifp->if_csum_flags_rx = 0; 2726 } 2727 2728 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2729 2730 if (sc->sc_gigabit) 2731 sipcom_dp83820_init(sc, ifp->if_capenable); 2732 2733 /* 2734 * Give the transmit and receive rings to the chip. 2735 */ 2736 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2737 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2738 2739 /* 2740 * Initialize the interrupt mask. 2741 */ 2742 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2743 sc->sc_bits.b_isr_sserr | 2744 sc->sc_bits.b_isr_rmabt | 2745 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2746 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2747 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2748 2749 /* Set up the receive filter. */ 2750 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2751 2752 /* 2753 * Tune sc_rx_flow_thresh. 2754 * XXX "More than 8KB" is too short for jumbo frames. 2755 * XXX TODO: Threshold value should be user-settable. 2756 */ 2757 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2758 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2759 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2760 2761 /* 2762 * Set the current media. Do this after initializing the prototype 2763 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2764 * control. 2765 */ 2766 if ((error = ether_mediachange(ifp)) != 0) 2767 goto out; 2768 2769 /* 2770 * Set the interrupt hold-off timer to 100us. 2771 */ 2772 if (sc->sc_gigabit) 2773 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2774 2775 /* 2776 * Enable interrupts. 2777 */ 2778 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2779 2780 /* 2781 * Start the transmit and receive processes. 2782 */ 2783 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2784 2785 /* 2786 * Start the one second MII clock. 2787 */ 2788 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2789 2790 /* 2791 * ...all done! 2792 */ 2793 ifp->if_flags |= IFF_RUNNING; 2794 ifp->if_flags &= ~IFF_OACTIVE; 2795 sc->sc_if_flags = ifp->if_flags; 2796 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2797 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2798 sc->sc_prev.if_capenable = ifp->if_capenable; 2799 2800 out: 2801 if (error) 2802 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2803 return (error); 2804 } 2805 2806 /* 2807 * sip_drain: 2808 * 2809 * Drain the receive queue. 2810 */ 2811 static void 2812 sipcom_rxdrain(struct sip_softc *sc) 2813 { 2814 struct sip_rxsoft *rxs; 2815 int i; 2816 2817 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2818 rxs = &sc->sc_rxsoft[i]; 2819 if (rxs->rxs_mbuf != NULL) { 2820 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2821 m_freem(rxs->rxs_mbuf); 2822 rxs->rxs_mbuf = NULL; 2823 } 2824 } 2825 } 2826 2827 /* 2828 * sip_stop: [ ifnet interface function ] 2829 * 2830 * Stop transmission on the interface. 2831 */ 2832 static void 2833 sipcom_stop(struct ifnet *ifp, int disable) 2834 { 2835 struct sip_softc *sc = ifp->if_softc; 2836 bus_space_tag_t st = sc->sc_st; 2837 bus_space_handle_t sh = sc->sc_sh; 2838 struct sip_txsoft *txs; 2839 u_int32_t cmdsts = 0; /* DEBUG */ 2840 2841 /* 2842 * Stop the one second clock. 2843 */ 2844 callout_stop(&sc->sc_tick_ch); 2845 2846 /* Down the MII. */ 2847 mii_down(&sc->sc_mii); 2848 2849 if (device_is_active(&sc->sc_dev)) { 2850 /* 2851 * Disable interrupts. 2852 */ 2853 bus_space_write_4(st, sh, SIP_IER, 0); 2854 2855 /* 2856 * Stop receiver and transmitter. 2857 */ 2858 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2859 } 2860 2861 /* 2862 * Release any queued transmit buffers. 2863 */ 2864 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2865 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2866 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2867 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2868 CMDSTS_INTR) == 0) 2869 printf("%s: sip_stop: last descriptor does not " 2870 "have INTR bit set\n", device_xname(&sc->sc_dev)); 2871 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2872 #ifdef DIAGNOSTIC 2873 if (txs->txs_mbuf == NULL) { 2874 printf("%s: dirty txsoft with no mbuf chain\n", 2875 device_xname(&sc->sc_dev)); 2876 panic("sip_stop"); 2877 } 2878 #endif 2879 cmdsts |= /* DEBUG */ 2880 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2881 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2882 m_freem(txs->txs_mbuf); 2883 txs->txs_mbuf = NULL; 2884 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2885 } 2886 2887 /* 2888 * Mark the interface down and cancel the watchdog timer. 2889 */ 2890 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2891 ifp->if_timer = 0; 2892 2893 if (disable) 2894 pmf_device_suspend_self(&sc->sc_dev); 2895 2896 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2897 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2898 printf("%s: sip_stop: no INTR bits set in dirty tx " 2899 "descriptors\n", device_xname(&sc->sc_dev)); 2900 } 2901 2902 /* 2903 * sip_read_eeprom: 2904 * 2905 * Read data from the serial EEPROM. 2906 */ 2907 static void 2908 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2909 u_int16_t *data) 2910 { 2911 bus_space_tag_t st = sc->sc_st; 2912 bus_space_handle_t sh = sc->sc_sh; 2913 u_int16_t reg; 2914 int i, x; 2915 2916 for (i = 0; i < wordcnt; i++) { 2917 /* Send CHIP SELECT. */ 2918 reg = EROMAR_EECS; 2919 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2920 2921 /* Shift in the READ opcode. */ 2922 for (x = 3; x > 0; x--) { 2923 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2924 reg |= EROMAR_EEDI; 2925 else 2926 reg &= ~EROMAR_EEDI; 2927 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2928 bus_space_write_4(st, sh, SIP_EROMAR, 2929 reg | EROMAR_EESK); 2930 delay(4); 2931 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2932 delay(4); 2933 } 2934 2935 /* Shift in address. */ 2936 for (x = 6; x > 0; x--) { 2937 if ((word + i) & (1 << (x - 1))) 2938 reg |= EROMAR_EEDI; 2939 else 2940 reg &= ~EROMAR_EEDI; 2941 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2942 bus_space_write_4(st, sh, SIP_EROMAR, 2943 reg | EROMAR_EESK); 2944 delay(4); 2945 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2946 delay(4); 2947 } 2948 2949 /* Shift out data. */ 2950 reg = EROMAR_EECS; 2951 data[i] = 0; 2952 for (x = 16; x > 0; x--) { 2953 bus_space_write_4(st, sh, SIP_EROMAR, 2954 reg | EROMAR_EESK); 2955 delay(4); 2956 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2957 data[i] |= (1 << (x - 1)); 2958 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2959 delay(4); 2960 } 2961 2962 /* Clear CHIP SELECT. */ 2963 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2964 delay(4); 2965 } 2966 } 2967 2968 /* 2969 * sipcom_add_rxbuf: 2970 * 2971 * Add a receive buffer to the indicated descriptor. 2972 */ 2973 static int 2974 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2975 { 2976 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2977 struct mbuf *m; 2978 int error; 2979 2980 MGETHDR(m, M_DONTWAIT, MT_DATA); 2981 if (m == NULL) 2982 return (ENOBUFS); 2983 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2984 2985 MCLGET(m, M_DONTWAIT); 2986 if ((m->m_flags & M_EXT) == 0) { 2987 m_freem(m); 2988 return (ENOBUFS); 2989 } 2990 2991 /* XXX I don't believe this is necessary. --dyoung */ 2992 if (sc->sc_gigabit) 2993 m->m_len = sc->sc_parm->p_rxbuf_len; 2994 2995 if (rxs->rxs_mbuf != NULL) 2996 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2997 2998 rxs->rxs_mbuf = m; 2999 3000 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3001 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3002 BUS_DMA_READ|BUS_DMA_NOWAIT); 3003 if (error) { 3004 printf("%s: can't load rx DMA map %d, error = %d\n", 3005 device_xname(&sc->sc_dev), idx, error); 3006 panic("%s", __func__); /* XXX */ 3007 } 3008 3009 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3010 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3011 3012 sip_init_rxdesc(sc, idx); 3013 3014 return (0); 3015 } 3016 3017 /* 3018 * sip_sis900_set_filter: 3019 * 3020 * Set up the receive filter. 3021 */ 3022 static void 3023 sipcom_sis900_set_filter(struct sip_softc *sc) 3024 { 3025 bus_space_tag_t st = sc->sc_st; 3026 bus_space_handle_t sh = sc->sc_sh; 3027 struct ethercom *ec = &sc->sc_ethercom; 3028 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3029 struct ether_multi *enm; 3030 const u_int8_t *cp; 3031 struct ether_multistep step; 3032 u_int32_t crc, mchash[16]; 3033 3034 /* 3035 * Initialize the prototype RFCR. 3036 */ 3037 sc->sc_rfcr = RFCR_RFEN; 3038 if (ifp->if_flags & IFF_BROADCAST) 3039 sc->sc_rfcr |= RFCR_AAB; 3040 if (ifp->if_flags & IFF_PROMISC) { 3041 sc->sc_rfcr |= RFCR_AAP; 3042 goto allmulti; 3043 } 3044 3045 /* 3046 * Set up the multicast address filter by passing all multicast 3047 * addresses through a CRC generator, and then using the high-order 3048 * 6 bits as an index into the 128 bit multicast hash table (only 3049 * the lower 16 bits of each 32 bit multicast hash register are 3050 * valid). The high order bits select the register, while the 3051 * rest of the bits select the bit within the register. 3052 */ 3053 3054 memset(mchash, 0, sizeof(mchash)); 3055 3056 /* 3057 * SiS900 (at least SiS963) requires us to register the address of 3058 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3059 */ 3060 crc = 0x0ed423f9; 3061 3062 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3063 SIP_SIS900_REV(sc, SIS_REV_960) || 3064 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3065 /* Just want the 8 most significant bits. */ 3066 crc >>= 24; 3067 } else { 3068 /* Just want the 7 most significant bits. */ 3069 crc >>= 25; 3070 } 3071 3072 /* Set the corresponding bit in the hash table. */ 3073 mchash[crc >> 4] |= 1 << (crc & 0xf); 3074 3075 ETHER_FIRST_MULTI(step, ec, enm); 3076 while (enm != NULL) { 3077 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3078 /* 3079 * We must listen to a range of multicast addresses. 3080 * For now, just accept all multicasts, rather than 3081 * trying to set only those filter bits needed to match 3082 * the range. (At this time, the only use of address 3083 * ranges is for IP multicast routing, for which the 3084 * range is big enough to require all bits set.) 3085 */ 3086 goto allmulti; 3087 } 3088 3089 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3090 3091 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3092 SIP_SIS900_REV(sc, SIS_REV_960) || 3093 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3094 /* Just want the 8 most significant bits. */ 3095 crc >>= 24; 3096 } else { 3097 /* Just want the 7 most significant bits. */ 3098 crc >>= 25; 3099 } 3100 3101 /* Set the corresponding bit in the hash table. */ 3102 mchash[crc >> 4] |= 1 << (crc & 0xf); 3103 3104 ETHER_NEXT_MULTI(step, enm); 3105 } 3106 3107 ifp->if_flags &= ~IFF_ALLMULTI; 3108 goto setit; 3109 3110 allmulti: 3111 ifp->if_flags |= IFF_ALLMULTI; 3112 sc->sc_rfcr |= RFCR_AAM; 3113 3114 setit: 3115 #define FILTER_EMIT(addr, data) \ 3116 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3117 delay(1); \ 3118 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3119 delay(1) 3120 3121 /* 3122 * Disable receive filter, and program the node address. 3123 */ 3124 cp = CLLADDR(ifp->if_sadl); 3125 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3126 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3127 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3128 3129 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3130 /* 3131 * Program the multicast hash table. 3132 */ 3133 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3134 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3135 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3136 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3137 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3138 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3139 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3140 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3141 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3142 SIP_SIS900_REV(sc, SIS_REV_960) || 3143 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3144 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3145 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3146 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3147 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3148 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3149 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3150 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3151 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3152 } 3153 } 3154 #undef FILTER_EMIT 3155 3156 /* 3157 * Re-enable the receiver filter. 3158 */ 3159 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3160 } 3161 3162 /* 3163 * sip_dp83815_set_filter: 3164 * 3165 * Set up the receive filter. 3166 */ 3167 static void 3168 sipcom_dp83815_set_filter(struct sip_softc *sc) 3169 { 3170 bus_space_tag_t st = sc->sc_st; 3171 bus_space_handle_t sh = sc->sc_sh; 3172 struct ethercom *ec = &sc->sc_ethercom; 3173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3174 struct ether_multi *enm; 3175 const u_int8_t *cp; 3176 struct ether_multistep step; 3177 u_int32_t crc, hash, slot, bit; 3178 #define MCHASH_NWORDS_83820 128 3179 #define MCHASH_NWORDS_83815 32 3180 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3181 u_int16_t mchash[MCHASH_NWORDS]; 3182 int i; 3183 3184 /* 3185 * Initialize the prototype RFCR. 3186 * Enable the receive filter, and accept on 3187 * Perfect (destination address) Match 3188 * If IFF_BROADCAST, also accept all broadcast packets. 3189 * If IFF_PROMISC, accept all unicast packets (and later, set 3190 * IFF_ALLMULTI and accept all multicast, too). 3191 */ 3192 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3193 if (ifp->if_flags & IFF_BROADCAST) 3194 sc->sc_rfcr |= RFCR_AAB; 3195 if (ifp->if_flags & IFF_PROMISC) { 3196 sc->sc_rfcr |= RFCR_AAP; 3197 goto allmulti; 3198 } 3199 3200 /* 3201 * Set up the DP83820/DP83815 multicast address filter by 3202 * passing all multicast addresses through a CRC generator, 3203 * and then using the high-order 11/9 bits as an index into 3204 * the 2048/512 bit multicast hash table. The high-order 3205 * 7/5 bits select the slot, while the low-order 4 bits 3206 * select the bit within the slot. Note that only the low 3207 * 16-bits of each filter word are used, and there are 3208 * 128/32 filter words. 3209 */ 3210 3211 memset(mchash, 0, sizeof(mchash)); 3212 3213 ifp->if_flags &= ~IFF_ALLMULTI; 3214 ETHER_FIRST_MULTI(step, ec, enm); 3215 if (enm == NULL) 3216 goto setit; 3217 while (enm != NULL) { 3218 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3219 /* 3220 * We must listen to a range of multicast addresses. 3221 * For now, just accept all multicasts, rather than 3222 * trying to set only those filter bits needed to match 3223 * the range. (At this time, the only use of address 3224 * ranges is for IP multicast routing, for which the 3225 * range is big enough to require all bits set.) 3226 */ 3227 goto allmulti; 3228 } 3229 3230 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3231 3232 if (sc->sc_gigabit) { 3233 /* Just want the 11 most significant bits. */ 3234 hash = crc >> 21; 3235 } else { 3236 /* Just want the 9 most significant bits. */ 3237 hash = crc >> 23; 3238 } 3239 3240 slot = hash >> 4; 3241 bit = hash & 0xf; 3242 3243 /* Set the corresponding bit in the hash table. */ 3244 mchash[slot] |= 1 << bit; 3245 3246 ETHER_NEXT_MULTI(step, enm); 3247 } 3248 sc->sc_rfcr |= RFCR_MHEN; 3249 goto setit; 3250 3251 allmulti: 3252 ifp->if_flags |= IFF_ALLMULTI; 3253 sc->sc_rfcr |= RFCR_AAM; 3254 3255 setit: 3256 #define FILTER_EMIT(addr, data) \ 3257 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3258 delay(1); \ 3259 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3260 delay(1) 3261 3262 /* 3263 * Disable receive filter, and program the node address. 3264 */ 3265 cp = CLLADDR(ifp->if_sadl); 3266 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3267 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3268 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3269 3270 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3271 int nwords = 3272 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3273 /* 3274 * Program the multicast hash table. 3275 */ 3276 for (i = 0; i < nwords; i++) { 3277 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3278 } 3279 } 3280 #undef FILTER_EMIT 3281 #undef MCHASH_NWORDS 3282 #undef MCHASH_NWORDS_83815 3283 #undef MCHASH_NWORDS_83820 3284 3285 /* 3286 * Re-enable the receiver filter. 3287 */ 3288 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3289 } 3290 3291 /* 3292 * sip_dp83820_mii_readreg: [mii interface function] 3293 * 3294 * Read a PHY register on the MII of the DP83820. 3295 */ 3296 static int 3297 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3298 { 3299 struct sip_softc *sc = device_private(self); 3300 3301 if (sc->sc_cfg & CFG_TBI_EN) { 3302 bus_addr_t tbireg; 3303 int rv; 3304 3305 if (phy != 0) 3306 return (0); 3307 3308 switch (reg) { 3309 case MII_BMCR: tbireg = SIP_TBICR; break; 3310 case MII_BMSR: tbireg = SIP_TBISR; break; 3311 case MII_ANAR: tbireg = SIP_TANAR; break; 3312 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3313 case MII_ANER: tbireg = SIP_TANER; break; 3314 case MII_EXTSR: 3315 /* 3316 * Don't even bother reading the TESR register. 3317 * The manual documents that the device has 3318 * 1000baseX full/half capability, but the 3319 * register itself seems read back 0 on some 3320 * boards. Just hard-code the result. 3321 */ 3322 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3323 3324 default: 3325 return (0); 3326 } 3327 3328 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3329 if (tbireg == SIP_TBISR) { 3330 /* LINK and ACOMP are switched! */ 3331 int val = rv; 3332 3333 rv = 0; 3334 if (val & TBISR_MR_LINK_STATUS) 3335 rv |= BMSR_LINK; 3336 if (val & TBISR_MR_AN_COMPLETE) 3337 rv |= BMSR_ACOMP; 3338 3339 /* 3340 * The manual claims this register reads back 0 3341 * on hard and soft reset. But we want to let 3342 * the gentbi driver know that we support auto- 3343 * negotiation, so hard-code this bit in the 3344 * result. 3345 */ 3346 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3347 } 3348 3349 return (rv); 3350 } 3351 3352 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3353 } 3354 3355 /* 3356 * sip_dp83820_mii_writereg: [mii interface function] 3357 * 3358 * Write a PHY register on the MII of the DP83820. 3359 */ 3360 static void 3361 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3362 { 3363 struct sip_softc *sc = device_private(self); 3364 3365 if (sc->sc_cfg & CFG_TBI_EN) { 3366 bus_addr_t tbireg; 3367 3368 if (phy != 0) 3369 return; 3370 3371 switch (reg) { 3372 case MII_BMCR: tbireg = SIP_TBICR; break; 3373 case MII_ANAR: tbireg = SIP_TANAR; break; 3374 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3375 default: 3376 return; 3377 } 3378 3379 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3380 return; 3381 } 3382 3383 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3384 } 3385 3386 /* 3387 * sip_dp83820_mii_statchg: [mii interface function] 3388 * 3389 * Callback from MII layer when media changes. 3390 */ 3391 static void 3392 sipcom_dp83820_mii_statchg(device_t self) 3393 { 3394 struct sip_softc *sc = device_private(self); 3395 struct mii_data *mii = &sc->sc_mii; 3396 u_int32_t cfg, pcr; 3397 3398 /* 3399 * Get flow control negotiation result. 3400 */ 3401 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3402 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3403 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3404 mii->mii_media_active &= ~IFM_ETH_FMASK; 3405 } 3406 3407 /* 3408 * Update TXCFG for full-duplex operation. 3409 */ 3410 if ((mii->mii_media_active & IFM_FDX) != 0) 3411 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3412 else 3413 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3414 3415 /* 3416 * Update RXCFG for full-duplex or loopback. 3417 */ 3418 if ((mii->mii_media_active & IFM_FDX) != 0 || 3419 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3420 sc->sc_rxcfg |= RXCFG_ATX; 3421 else 3422 sc->sc_rxcfg &= ~RXCFG_ATX; 3423 3424 /* 3425 * Update CFG for MII/GMII. 3426 */ 3427 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3428 cfg = sc->sc_cfg | CFG_MODE_1000; 3429 else 3430 cfg = sc->sc_cfg; 3431 3432 /* 3433 * 802.3x flow control. 3434 */ 3435 pcr = 0; 3436 if (sc->sc_flowflags & IFM_FLOW) { 3437 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3438 pcr |= sc->sc_rx_flow_thresh; 3439 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3440 pcr |= PCR_PSEN | PCR_PS_MCAST; 3441 } 3442 3443 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3444 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3445 sc->sc_txcfg); 3446 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3447 sc->sc_rxcfg); 3448 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3449 } 3450 3451 /* 3452 * sip_mii_bitbang_read: [mii bit-bang interface function] 3453 * 3454 * Read the MII serial port for the MII bit-bang module. 3455 */ 3456 static u_int32_t 3457 sipcom_mii_bitbang_read(device_t self) 3458 { 3459 struct sip_softc *sc = device_private(self); 3460 3461 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3462 } 3463 3464 /* 3465 * sip_mii_bitbang_write: [mii big-bang interface function] 3466 * 3467 * Write the MII serial port for the MII bit-bang module. 3468 */ 3469 static void 3470 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3471 { 3472 struct sip_softc *sc = device_private(self); 3473 3474 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3475 } 3476 3477 /* 3478 * sip_sis900_mii_readreg: [mii interface function] 3479 * 3480 * Read a PHY register on the MII. 3481 */ 3482 static int 3483 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3484 { 3485 struct sip_softc *sc = device_private(self); 3486 u_int32_t enphy; 3487 3488 /* 3489 * The PHY of recent SiS chipsets is accessed through bitbang 3490 * operations. 3491 */ 3492 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3493 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3494 phy, reg); 3495 3496 #ifndef SIS900_MII_RESTRICT 3497 /* 3498 * The SiS 900 has only an internal PHY on the MII. Only allow 3499 * MII address 0. 3500 */ 3501 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3502 return (0); 3503 #endif 3504 3505 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3506 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3507 ENPHY_RWCMD | ENPHY_ACCESS); 3508 do { 3509 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3510 } while (enphy & ENPHY_ACCESS); 3511 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3512 } 3513 3514 /* 3515 * sip_sis900_mii_writereg: [mii interface function] 3516 * 3517 * Write a PHY register on the MII. 3518 */ 3519 static void 3520 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3521 { 3522 struct sip_softc *sc = device_private(self); 3523 u_int32_t enphy; 3524 3525 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3526 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3527 phy, reg, val); 3528 return; 3529 } 3530 3531 #ifndef SIS900_MII_RESTRICT 3532 /* 3533 * The SiS 900 has only an internal PHY on the MII. Only allow 3534 * MII address 0. 3535 */ 3536 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3537 return; 3538 #endif 3539 3540 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3541 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3542 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3543 do { 3544 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3545 } while (enphy & ENPHY_ACCESS); 3546 } 3547 3548 /* 3549 * sip_sis900_mii_statchg: [mii interface function] 3550 * 3551 * Callback from MII layer when media changes. 3552 */ 3553 static void 3554 sipcom_sis900_mii_statchg(device_t self) 3555 { 3556 struct sip_softc *sc = device_private(self); 3557 struct mii_data *mii = &sc->sc_mii; 3558 u_int32_t flowctl; 3559 3560 /* 3561 * Get flow control negotiation result. 3562 */ 3563 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3564 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3565 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3566 mii->mii_media_active &= ~IFM_ETH_FMASK; 3567 } 3568 3569 /* 3570 * Update TXCFG for full-duplex operation. 3571 */ 3572 if ((mii->mii_media_active & IFM_FDX) != 0) 3573 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3574 else 3575 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3576 3577 /* 3578 * Update RXCFG for full-duplex or loopback. 3579 */ 3580 if ((mii->mii_media_active & IFM_FDX) != 0 || 3581 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3582 sc->sc_rxcfg |= RXCFG_ATX; 3583 else 3584 sc->sc_rxcfg &= ~RXCFG_ATX; 3585 3586 /* 3587 * Update IMR for use of 802.3x flow control. 3588 */ 3589 if (sc->sc_flowflags & IFM_FLOW) { 3590 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3591 flowctl = FLOWCTL_FLOWEN; 3592 } else { 3593 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3594 flowctl = 0; 3595 } 3596 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3598 sc->sc_txcfg); 3599 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3600 sc->sc_rxcfg); 3601 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3602 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3603 } 3604 3605 /* 3606 * sip_dp83815_mii_readreg: [mii interface function] 3607 * 3608 * Read a PHY register on the MII. 3609 */ 3610 static int 3611 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3612 { 3613 struct sip_softc *sc = device_private(self); 3614 u_int32_t val; 3615 3616 /* 3617 * The DP83815 only has an internal PHY. Only allow 3618 * MII address 0. 3619 */ 3620 if (phy != 0) 3621 return (0); 3622 3623 /* 3624 * Apparently, after a reset, the DP83815 can take a while 3625 * to respond. During this recovery period, the BMSR returns 3626 * a value of 0. Catch this -- it's not supposed to happen 3627 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3628 * PHY to come back to life. 3629 * 3630 * This works out because the BMSR is the first register 3631 * read during the PHY probe process. 3632 */ 3633 do { 3634 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3635 } while (reg == MII_BMSR && val == 0); 3636 3637 return (val & 0xffff); 3638 } 3639 3640 /* 3641 * sip_dp83815_mii_writereg: [mii interface function] 3642 * 3643 * Write a PHY register to the MII. 3644 */ 3645 static void 3646 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3647 { 3648 struct sip_softc *sc = device_private(self); 3649 3650 /* 3651 * The DP83815 only has an internal PHY. Only allow 3652 * MII address 0. 3653 */ 3654 if (phy != 0) 3655 return; 3656 3657 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3658 } 3659 3660 /* 3661 * sip_dp83815_mii_statchg: [mii interface function] 3662 * 3663 * Callback from MII layer when media changes. 3664 */ 3665 static void 3666 sipcom_dp83815_mii_statchg(device_t self) 3667 { 3668 struct sip_softc *sc = device_private(self); 3669 3670 /* 3671 * Update TXCFG for full-duplex operation. 3672 */ 3673 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3674 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3675 else 3676 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3677 3678 /* 3679 * Update RXCFG for full-duplex or loopback. 3680 */ 3681 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3682 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3683 sc->sc_rxcfg |= RXCFG_ATX; 3684 else 3685 sc->sc_rxcfg &= ~RXCFG_ATX; 3686 3687 /* 3688 * XXX 802.3x flow control. 3689 */ 3690 3691 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3692 sc->sc_txcfg); 3693 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3694 sc->sc_rxcfg); 3695 3696 /* 3697 * Some DP83815s experience problems when used with short 3698 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3699 * sequence adjusts the DSP's signal attenuation to fix the 3700 * problem. 3701 */ 3702 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3703 uint32_t reg; 3704 3705 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3706 3707 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3708 reg &= 0x0fff; 3709 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3710 delay(100); 3711 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3712 reg &= 0x00ff; 3713 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3714 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3715 0x00e8); 3716 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3717 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3718 reg | 0x20); 3719 } 3720 3721 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3722 } 3723 } 3724 3725 static void 3726 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3727 const struct pci_attach_args *pa, u_int8_t *enaddr) 3728 { 3729 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3730 u_int8_t cksum, *e, match; 3731 int i; 3732 3733 /* 3734 * EEPROM data format for the DP83820 can be found in 3735 * the DP83820 manual, section 4.2.4. 3736 */ 3737 3738 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3739 3740 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3741 match = ~(match - 1); 3742 3743 cksum = 0x55; 3744 e = (u_int8_t *) eeprom_data; 3745 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3746 cksum += *e++; 3747 3748 if (cksum != match) 3749 printf("%s: Checksum (%x) mismatch (%x)", 3750 device_xname(&sc->sc_dev), cksum, match); 3751 3752 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3753 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3754 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3755 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3756 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3757 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3758 } 3759 3760 static void 3761 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3762 { 3763 int i; 3764 3765 /* 3766 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3767 * a reason, but I don't know it. 3768 */ 3769 for (i = 0; i < 10; i++) 3770 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3771 } 3772 3773 static void 3774 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3775 const struct pci_attach_args *pa, u_int8_t *enaddr) 3776 { 3777 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3778 3779 switch (sc->sc_rev) { 3780 case SIS_REV_630S: 3781 case SIS_REV_630E: 3782 case SIS_REV_630EA1: 3783 case SIS_REV_630ET: 3784 case SIS_REV_635: 3785 /* 3786 * The MAC address for the on-board Ethernet of 3787 * the SiS 630 chipset is in the NVRAM. Kick 3788 * the chip into re-loading it from NVRAM, and 3789 * read the MAC address out of the filter registers. 3790 */ 3791 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3792 3793 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3794 RFCR_RFADDR_NODE0); 3795 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3796 0xffff; 3797 3798 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3799 RFCR_RFADDR_NODE2); 3800 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3801 0xffff; 3802 3803 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3804 RFCR_RFADDR_NODE4); 3805 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3806 0xffff; 3807 break; 3808 3809 case SIS_REV_960: 3810 { 3811 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3812 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3813 3814 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3815 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3816 3817 int waittime, i; 3818 3819 /* Allow to read EEPROM from LAN. It is shared 3820 * between a 1394 controller and the NIC and each 3821 * time we access it, we need to set SIS_EECMD_REQ. 3822 */ 3823 SIS_SET_EROMAR(sc, EROMAR_REQ); 3824 3825 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3826 /* Force EEPROM to idle state. */ 3827 3828 /* 3829 * XXX-cube This is ugly. I'll look for docs about it. 3830 */ 3831 SIS_SET_EROMAR(sc, EROMAR_EECS); 3832 sipcom_sis900_eeprom_delay(sc); 3833 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3834 SIS_SET_EROMAR(sc, EROMAR_EESK); 3835 sipcom_sis900_eeprom_delay(sc); 3836 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3837 sipcom_sis900_eeprom_delay(sc); 3838 } 3839 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3840 sipcom_sis900_eeprom_delay(sc); 3841 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3842 3843 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3844 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3845 sizeof(myea) / sizeof(myea[0]), myea); 3846 break; 3847 } 3848 DELAY(1); 3849 } 3850 3851 /* 3852 * Set SIS_EECTL_CLK to high, so a other master 3853 * can operate on the i2c bus. 3854 */ 3855 SIS_SET_EROMAR(sc, EROMAR_EESK); 3856 3857 /* Refuse EEPROM access by LAN */ 3858 SIS_SET_EROMAR(sc, EROMAR_DONE); 3859 } break; 3860 3861 default: 3862 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3863 sizeof(myea) / sizeof(myea[0]), myea); 3864 } 3865 3866 enaddr[0] = myea[0] & 0xff; 3867 enaddr[1] = myea[0] >> 8; 3868 enaddr[2] = myea[1] & 0xff; 3869 enaddr[3] = myea[1] >> 8; 3870 enaddr[4] = myea[2] & 0xff; 3871 enaddr[5] = myea[2] >> 8; 3872 } 3873 3874 /* Table and macro to bit-reverse an octet. */ 3875 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3876 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3877 3878 static void 3879 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3880 const struct pci_attach_args *pa, u_int8_t *enaddr) 3881 { 3882 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3883 u_int8_t cksum, *e, match; 3884 int i; 3885 3886 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3887 sizeof(eeprom_data[0]), eeprom_data); 3888 3889 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3890 match = ~(match - 1); 3891 3892 cksum = 0x55; 3893 e = (u_int8_t *) eeprom_data; 3894 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3895 cksum += *e++; 3896 } 3897 if (cksum != match) { 3898 printf("%s: Checksum (%x) mismatch (%x)", 3899 device_xname(&sc->sc_dev), cksum, match); 3900 } 3901 3902 /* 3903 * Unrolled because it makes slightly more sense this way. 3904 * The DP83815 stores the MAC address in bit 0 of word 6 3905 * through bit 15 of word 8. 3906 */ 3907 ea = &eeprom_data[6]; 3908 enaddr[0] = ((*ea & 0x1) << 7); 3909 ea++; 3910 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3911 enaddr[1] = ((*ea & 0x1FE) >> 1); 3912 enaddr[2] = ((*ea & 0x1) << 7); 3913 ea++; 3914 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3915 enaddr[3] = ((*ea & 0x1FE) >> 1); 3916 enaddr[4] = ((*ea & 0x1) << 7); 3917 ea++; 3918 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3919 enaddr[5] = ((*ea & 0x1FE) >> 1); 3920 3921 /* 3922 * In case that's not weird enough, we also need to reverse 3923 * the bits in each byte. This all actually makes more sense 3924 * if you think about the EEPROM storage as an array of bits 3925 * being shifted into bytes, but that's not how we're looking 3926 * at it here... 3927 */ 3928 for (i = 0; i < 6 ;i++) 3929 enaddr[i] = bbr(enaddr[i]); 3930 } 3931 3932 /* 3933 * sip_mediastatus: [ifmedia interface function] 3934 * 3935 * Get the current interface media status. 3936 */ 3937 static void 3938 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3939 { 3940 struct sip_softc *sc = ifp->if_softc; 3941 3942 if (!device_is_active(&sc->sc_dev)) { 3943 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3944 ifmr->ifm_status = 0; 3945 return; 3946 } 3947 ether_mediastatus(ifp, ifmr); 3948 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3949 sc->sc_flowflags; 3950 } 3951
Indexes created Tue Sep 30 11:09:46 GMT 2025