if_sip.c revision 1.132.4.5
1 /* $NetBSD: if_sip.c,v 1.132.4.5 2010/03/11 15:03:47 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.132.4.5 2010/03/11 15:03:47 yamt Exp $"); 77 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #include <net/bpf.h> 104 105 #include <sys/bus.h> 106 #include <sys/intr.h> 107 #include <machine/endian.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 #include <dev/mii/mii_bitbang.h> 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/pci/if_sipreg.h> 118 119 /* 120 * Transmit descriptor list size. This is arbitrary, but allocate 121 * enough descriptors for 128 pending transmissions, and 8 segments 122 * per packet (64 for DP83820 for jumbo frames). 123 * 124 * This MUST work out to a power of 2. 125 */ 126 #define GSIP_NTXSEGS_ALLOC 16 127 #define SIP_NTXSEGS_ALLOC 8 128 129 #define SIP_TXQUEUELEN 256 130 #define MAX_SIP_NTXDESC \ 131 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 132 133 /* 134 * Receive descriptor list size. We have one Rx buffer per incoming 135 * packet, so this logic is a little simpler. 136 * 137 * Actually, on the DP83820, we allow the packet to consume more than 138 * one buffer, in order to support jumbo Ethernet frames. In that 139 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 140 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 141 * so we'd better be quick about handling receive interrupts. 142 */ 143 #define GSIP_NRXDESC 256 144 #define SIP_NRXDESC 128 145 146 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 147 148 /* 149 * Control structures are DMA'd to the SiS900 chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct sip_control_data { 154 /* 155 * The transmit descriptors. 156 */ 157 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 158 159 /* 160 * The receive descriptors. 161 */ 162 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 163 }; 164 165 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 166 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 167 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct sip_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 178 }; 179 180 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 181 182 /* 183 * Software state for receive jobs. 184 */ 185 struct sip_rxsoft { 186 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 187 bus_dmamap_t rxs_dmamap; /* our DMA map */ 188 }; 189 190 enum sip_attach_stage { 191 SIP_ATTACH_FIN = 0 192 , SIP_ATTACH_CREATE_RXMAP 193 , SIP_ATTACH_CREATE_TXMAP 194 , SIP_ATTACH_LOAD_MAP 195 , SIP_ATTACH_CREATE_MAP 196 , SIP_ATTACH_MAP_MEM 197 , SIP_ATTACH_ALLOC_MEM 198 , SIP_ATTACH_INTR 199 , SIP_ATTACH_MAP 200 }; 201 202 /* 203 * Software state per device. 204 */ 205 struct sip_softc { 206 device_t sc_dev; /* generic device information */ 207 device_suspensor_t sc_suspensor; 208 pmf_qual_t sc_qual; 209 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static int sip_ifflags_cb(struct ethercom *); 563 static void sipcom_start(struct ifnet *); 564 static void sipcom_watchdog(struct ifnet *); 565 static int sipcom_ioctl(struct ifnet *, u_long, void *); 566 static int sipcom_init(struct ifnet *); 567 static void sipcom_stop(struct ifnet *, int); 568 569 static bool sipcom_reset(struct sip_softc *); 570 static void sipcom_rxdrain(struct sip_softc *); 571 static int sipcom_add_rxbuf(struct sip_softc *, int); 572 static void sipcom_read_eeprom(struct sip_softc *, int, int, 573 u_int16_t *); 574 static void sipcom_tick(void *); 575 576 static void sipcom_sis900_set_filter(struct sip_softc *); 577 static void sipcom_dp83815_set_filter(struct sip_softc *); 578 579 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 580 const struct pci_attach_args *, u_int8_t *); 581 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 582 static void sipcom_sis900_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 585 const struct pci_attach_args *, u_int8_t *); 586 587 static int sipcom_intr(void *); 588 static void sipcom_txintr(struct sip_softc *); 589 static void sip_rxintr(struct sip_softc *); 590 static void gsip_rxintr(struct sip_softc *); 591 592 static int sipcom_dp83820_mii_readreg(device_t, int, int); 593 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 594 static void sipcom_dp83820_mii_statchg(device_t); 595 596 static int sipcom_sis900_mii_readreg(device_t, int, int); 597 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 598 static void sipcom_sis900_mii_statchg(device_t); 599 600 static int sipcom_dp83815_mii_readreg(device_t, int, int); 601 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 602 static void sipcom_dp83815_mii_statchg(device_t); 603 604 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 605 606 static int sipcom_match(device_t, cfdata_t, void *); 607 static void sipcom_attach(device_t, device_t, void *); 608 static void sipcom_do_detach(device_t, enum sip_attach_stage); 609 static int sipcom_detach(device_t, int); 610 static bool sipcom_resume(device_t, const pmf_qual_t *); 611 static bool sipcom_suspend(device_t, const pmf_qual_t *); 612 613 int gsip_copy_small = 0; 614 int sip_copy_small = 0; 615 616 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 617 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 618 DVF_DETACH_SHUTDOWN); 619 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 620 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 621 DVF_DETACH_SHUTDOWN); 622 623 /* 624 * Descriptions of the variants of the SiS900. 625 */ 626 struct sip_variant { 627 int (*sipv_mii_readreg)(device_t, int, int); 628 void (*sipv_mii_writereg)(device_t, int, int, int); 629 void (*sipv_mii_statchg)(device_t); 630 void (*sipv_set_filter)(struct sip_softc *); 631 void (*sipv_read_macaddr)(struct sip_softc *, 632 const struct pci_attach_args *, u_int8_t *); 633 }; 634 635 static u_int32_t sipcom_mii_bitbang_read(device_t); 636 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 637 638 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 639 sipcom_mii_bitbang_read, 640 sipcom_mii_bitbang_write, 641 { 642 EROMAR_MDIO, /* MII_BIT_MDO */ 643 EROMAR_MDIO, /* MII_BIT_MDI */ 644 EROMAR_MDC, /* MII_BIT_MDC */ 645 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 646 0, /* MII_BIT_DIR_PHY_HOST */ 647 } 648 }; 649 650 static const struct sip_variant sipcom_variant_dp83820 = { 651 sipcom_dp83820_mii_readreg, 652 sipcom_dp83820_mii_writereg, 653 sipcom_dp83820_mii_statchg, 654 sipcom_dp83815_set_filter, 655 sipcom_dp83820_read_macaddr, 656 }; 657 658 static const struct sip_variant sipcom_variant_sis900 = { 659 sipcom_sis900_mii_readreg, 660 sipcom_sis900_mii_writereg, 661 sipcom_sis900_mii_statchg, 662 sipcom_sis900_set_filter, 663 sipcom_sis900_read_macaddr, 664 }; 665 666 static const struct sip_variant sipcom_variant_dp83815 = { 667 sipcom_dp83815_mii_readreg, 668 sipcom_dp83815_mii_writereg, 669 sipcom_dp83815_mii_statchg, 670 sipcom_dp83815_set_filter, 671 sipcom_dp83815_read_macaddr, 672 }; 673 674 675 /* 676 * Devices supported by this driver. 677 */ 678 static const struct sip_product { 679 pci_vendor_id_t sip_vendor; 680 pci_product_id_t sip_product; 681 const char *sip_name; 682 const struct sip_variant *sip_variant; 683 int sip_gigabit; 684 } sipcom_products[] = { 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 686 "NatSemi DP83820 Gigabit Ethernet", 687 &sipcom_variant_dp83820, 1 }, 688 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 689 "SiS 900 10/100 Ethernet", 690 &sipcom_variant_sis900, 0 }, 691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 692 "SiS 7016 10/100 Ethernet", 693 &sipcom_variant_sis900, 0 }, 694 695 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 696 "NatSemi DP83815 10/100 Ethernet", 697 &sipcom_variant_dp83815, 0 }, 698 699 { 0, 0, 700 NULL, 701 NULL, 0 }, 702 }; 703 704 static const struct sip_product * 705 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 706 { 707 const struct sip_product *sip; 708 709 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 710 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 711 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 712 sip->sip_gigabit == gigabit) 713 return sip; 714 } 715 return NULL; 716 } 717 718 /* 719 * I really hate stupid hardware vendors. There's a bit in the EEPROM 720 * which indicates if the card can do 64-bit data transfers. Unfortunately, 721 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 722 * which means we try to use 64-bit data transfers on those cards if we 723 * happen to be plugged into a 32-bit slot. 724 * 725 * What we do is use this table of cards known to be 64-bit cards. If 726 * you have a 64-bit card who's subsystem ID is not listed in this table, 727 * send the output of "pcictl dump ..." of the device to me so that your 728 * card will use the 64-bit data path when plugged into a 64-bit slot. 729 * 730 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 731 * June 30, 2002 732 */ 733 static int 734 sipcom_check_64bit(const struct pci_attach_args *pa) 735 { 736 static const struct { 737 pci_vendor_id_t c64_vendor; 738 pci_product_id_t c64_product; 739 } card64[] = { 740 /* Asante GigaNIX */ 741 { 0x128a, 0x0002 }, 742 743 /* Accton EN1407-T, Planex GN-1000TE */ 744 { 0x1113, 0x1407 }, 745 746 /* Netgear GA-621 */ 747 { 0x1385, 0x621a }, 748 749 /* SMC EZ Card */ 750 { 0x10b8, 0x9462 }, 751 752 { 0, 0} 753 }; 754 pcireg_t subsys; 755 int i; 756 757 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 758 759 for (i = 0; card64[i].c64_vendor != 0; i++) { 760 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 761 PCI_PRODUCT(subsys) == card64[i].c64_product) 762 return (1); 763 } 764 765 return (0); 766 } 767 768 static int 769 sipcom_match(device_t parent, cfdata_t cf, void *aux) 770 { 771 struct pci_attach_args *pa = aux; 772 773 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 774 return 1; 775 776 return 0; 777 } 778 779 static void 780 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 781 { 782 u_int32_t reg; 783 int i; 784 785 /* 786 * Cause the chip to load configuration data from the EEPROM. 787 */ 788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 789 for (i = 0; i < 10000; i++) { 790 delay(10); 791 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 792 PTSCR_EELOAD_EN) == 0) 793 break; 794 } 795 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 796 PTSCR_EELOAD_EN) { 797 printf("%s: timeout loading configuration from EEPROM\n", 798 device_xname(sc->sc_dev)); 799 return; 800 } 801 802 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 803 804 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 805 if (reg & CFG_PCI64_DET) { 806 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 807 /* 808 * Check to see if this card is 64-bit. If so, enable 64-bit 809 * data transfers. 810 * 811 * We can't use the DATA64_EN bit in the EEPROM, because 812 * vendors of 32-bit cards fail to clear that bit in many 813 * cases (yet the card still detects that it's in a 64-bit 814 * slot; go figure). 815 */ 816 if (sipcom_check_64bit(pa)) { 817 sc->sc_cfg |= CFG_DATA64_EN; 818 printf(", using 64-bit data transfers"); 819 } 820 printf("\n"); 821 } 822 823 /* 824 * XXX Need some PCI flags indicating support for 825 * XXX 64-bit addressing. 826 */ 827 #if 0 828 if (reg & CFG_M64ADDR) 829 sc->sc_cfg |= CFG_M64ADDR; 830 if (reg & CFG_T64ADDR) 831 sc->sc_cfg |= CFG_T64ADDR; 832 #endif 833 834 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 835 const char *sep = ""; 836 printf("%s: using ", device_xname(sc->sc_dev)); 837 if (reg & CFG_EXT_125) { 838 sc->sc_cfg |= CFG_EXT_125; 839 printf("%s125MHz clock", sep); 840 sep = ", "; 841 } 842 if (reg & CFG_TBI_EN) { 843 sc->sc_cfg |= CFG_TBI_EN; 844 printf("%sten-bit interface", sep); 845 sep = ", "; 846 } 847 printf("\n"); 848 } 849 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 850 (reg & CFG_MRM_DIS) != 0) 851 sc->sc_cfg |= CFG_MRM_DIS; 852 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 853 (reg & CFG_MWI_DIS) != 0) 854 sc->sc_cfg |= CFG_MWI_DIS; 855 856 /* 857 * Use the extended descriptor format on the DP83820. This 858 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 859 * checksumming. 860 */ 861 sc->sc_cfg |= CFG_EXTSTS_EN; 862 } 863 864 static int 865 sipcom_detach(device_t self, int flags) 866 { 867 int s; 868 869 s = splnet(); 870 sipcom_do_detach(self, SIP_ATTACH_FIN); 871 splx(s); 872 873 return 0; 874 } 875 876 static void 877 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 878 { 879 int i; 880 struct sip_softc *sc = device_private(self); 881 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 882 883 /* 884 * Free any resources we've allocated during attach. 885 * Do this in reverse order and fall through. 886 */ 887 switch (stage) { 888 case SIP_ATTACH_FIN: 889 sipcom_stop(ifp, 1); 890 pmf_device_deregister(self); 891 #ifdef SIP_EVENT_COUNTERS 892 /* 893 * Attach event counters. 894 */ 895 evcnt_detach(&sc->sc_ev_txforceintr); 896 evcnt_detach(&sc->sc_ev_txdstall); 897 evcnt_detach(&sc->sc_ev_txsstall); 898 evcnt_detach(&sc->sc_ev_hiberr); 899 evcnt_detach(&sc->sc_ev_rxintr); 900 evcnt_detach(&sc->sc_ev_txiintr); 901 evcnt_detach(&sc->sc_ev_txdintr); 902 if (!sc->sc_gigabit) { 903 evcnt_detach(&sc->sc_ev_rxpause); 904 } else { 905 evcnt_detach(&sc->sc_ev_txudpsum); 906 evcnt_detach(&sc->sc_ev_txtcpsum); 907 evcnt_detach(&sc->sc_ev_txipsum); 908 evcnt_detach(&sc->sc_ev_rxudpsum); 909 evcnt_detach(&sc->sc_ev_rxtcpsum); 910 evcnt_detach(&sc->sc_ev_rxipsum); 911 evcnt_detach(&sc->sc_ev_txpause); 912 evcnt_detach(&sc->sc_ev_rxpause); 913 } 914 #endif /* SIP_EVENT_COUNTERS */ 915 916 #if NRND > 0 917 rnd_detach_source(&sc->rnd_source); 918 #endif 919 920 ether_ifdetach(ifp); 921 if_detach(ifp); 922 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 923 924 /*FALLTHROUGH*/ 925 case SIP_ATTACH_CREATE_RXMAP: 926 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 927 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 928 bus_dmamap_destroy(sc->sc_dmat, 929 sc->sc_rxsoft[i].rxs_dmamap); 930 } 931 /*FALLTHROUGH*/ 932 case SIP_ATTACH_CREATE_TXMAP: 933 for (i = 0; i < SIP_TXQUEUELEN; i++) { 934 if (sc->sc_txsoft[i].txs_dmamap != NULL) 935 bus_dmamap_destroy(sc->sc_dmat, 936 sc->sc_txsoft[i].txs_dmamap); 937 } 938 /*FALLTHROUGH*/ 939 case SIP_ATTACH_LOAD_MAP: 940 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_CREATE_MAP: 943 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 944 /*FALLTHROUGH*/ 945 case SIP_ATTACH_MAP_MEM: 946 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 947 sizeof(struct sip_control_data)); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_ALLOC_MEM: 950 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 951 /* FALLTHROUGH*/ 952 case SIP_ATTACH_INTR: 953 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 954 /* FALLTHROUGH*/ 955 case SIP_ATTACH_MAP: 956 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 957 break; 958 default: 959 break; 960 } 961 return; 962 } 963 964 static bool 965 sipcom_resume(device_t self, const pmf_qual_t *qual) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 return sipcom_reset(sc); 970 } 971 972 static bool 973 sipcom_suspend(device_t self, const pmf_qual_t *qual) 974 { 975 struct sip_softc *sc = device_private(self); 976 977 sipcom_rxdrain(sc); 978 return true; 979 } 980 981 static void 982 sipcom_attach(device_t parent, device_t self, void *aux) 983 { 984 struct sip_softc *sc = device_private(self); 985 struct pci_attach_args *pa = aux; 986 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 987 pci_chipset_tag_t pc = pa->pa_pc; 988 pci_intr_handle_t ih; 989 const char *intrstr = NULL; 990 bus_space_tag_t iot, memt; 991 bus_space_handle_t ioh, memh; 992 bus_size_t iosz, memsz; 993 int ioh_valid, memh_valid; 994 int i, rseg, error; 995 const struct sip_product *sip; 996 u_int8_t enaddr[ETHER_ADDR_LEN]; 997 pcireg_t csr; 998 pcireg_t memtype; 999 bus_size_t tx_dmamap_size; 1000 int ntxsegs_alloc; 1001 cfdata_t cf = device_cfdata(self); 1002 1003 callout_init(&sc->sc_tick_ch, 0); 1004 1005 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1006 if (sip == NULL) { 1007 printf("\n"); 1008 panic("%s: impossible", __func__); 1009 } 1010 sc->sc_dev = self; 1011 sc->sc_gigabit = sip->sip_gigabit; 1012 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1013 sc->sc_pc = pc; 1014 1015 if (sc->sc_gigabit) { 1016 sc->sc_rxintr = gsip_rxintr; 1017 sc->sc_parm = &gsip_parm; 1018 } else { 1019 sc->sc_rxintr = sip_rxintr; 1020 sc->sc_parm = &sip_parm; 1021 } 1022 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1023 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1024 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1025 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1026 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1027 1028 sc->sc_rev = PCI_REVISION(pa->pa_class); 1029 1030 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1031 1032 sc->sc_model = sip; 1033 1034 /* 1035 * XXX Work-around broken PXE firmware on some boards. 1036 * 1037 * The DP83815 shares an address decoder with the MEM BAR 1038 * and the ROM BAR. Make sure the ROM BAR is disabled, 1039 * so that memory mapped access works. 1040 */ 1041 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1042 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1043 ~PCI_MAPREG_ROM_ENABLE); 1044 1045 /* 1046 * Map the device. 1047 */ 1048 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1049 PCI_MAPREG_TYPE_IO, 0, 1050 &iot, &ioh, NULL, &iosz) == 0); 1051 if (sc->sc_gigabit) { 1052 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1053 switch (memtype) { 1054 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1055 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1056 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1057 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1058 break; 1059 default: 1060 memh_valid = 0; 1061 } 1062 } else { 1063 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1064 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1065 &memt, &memh, NULL, &memsz) == 0); 1066 } 1067 1068 if (memh_valid) { 1069 sc->sc_st = memt; 1070 sc->sc_sh = memh; 1071 sc->sc_sz = memsz; 1072 } else if (ioh_valid) { 1073 sc->sc_st = iot; 1074 sc->sc_sh = ioh; 1075 sc->sc_sz = iosz; 1076 } else { 1077 printf("%s: unable to map device registers\n", 1078 device_xname(sc->sc_dev)); 1079 return; 1080 } 1081 1082 sc->sc_dmat = pa->pa_dmat; 1083 1084 /* 1085 * Make sure bus mastering is enabled. Also make sure 1086 * Write/Invalidate is enabled if we're allowed to use it. 1087 */ 1088 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1089 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1090 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1091 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1092 csr | PCI_COMMAND_MASTER_ENABLE); 1093 1094 /* power up chip */ 1095 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1096 if (error != 0 && error != EOPNOTSUPP) { 1097 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1098 return; 1099 } 1100 1101 /* 1102 * Map and establish our interrupt. 1103 */ 1104 if (pci_intr_map(pa, &ih)) { 1105 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1106 return; 1107 } 1108 intrstr = pci_intr_string(pc, ih); 1109 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1110 if (sc->sc_ih == NULL) { 1111 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1112 if (intrstr != NULL) 1113 aprint_error(" at %s", intrstr); 1114 aprint_error("\n"); 1115 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1116 } 1117 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1118 1119 SIMPLEQ_INIT(&sc->sc_txfreeq); 1120 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1121 1122 /* 1123 * Allocate the control data structures, and create and load the 1124 * DMA map for it. 1125 */ 1126 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1127 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1128 &rseg, 0)) != 0) { 1129 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1130 error); 1131 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1132 } 1133 1134 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1135 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1136 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1137 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1138 error); 1139 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1140 } 1141 1142 if ((error = bus_dmamap_create(sc->sc_dmat, 1143 sizeof(struct sip_control_data), 1, 1144 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1145 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1146 "error = %d\n", error); 1147 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1148 } 1149 1150 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1151 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1152 0)) != 0) { 1153 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1154 error); 1155 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1156 } 1157 1158 /* 1159 * Create the transmit buffer DMA maps. 1160 */ 1161 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1162 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1163 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1164 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1165 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1166 "error = %d\n", i, error); 1167 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1168 } 1169 } 1170 1171 /* 1172 * Create the receive buffer DMA maps. 1173 */ 1174 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1175 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1176 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1177 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1178 "error = %d\n", i, error); 1179 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1180 } 1181 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1182 } 1183 1184 /* 1185 * Reset the chip to a known state. 1186 */ 1187 sipcom_reset(sc); 1188 1189 /* 1190 * Read the Ethernet address from the EEPROM. This might 1191 * also fetch other stuff from the EEPROM and stash it 1192 * in the softc. 1193 */ 1194 sc->sc_cfg = 0; 1195 if (!sc->sc_gigabit) { 1196 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1197 SIP_SIS900_REV(sc,SIS_REV_900B)) 1198 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1199 1200 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1201 SIP_SIS900_REV(sc,SIS_REV_960) || 1202 SIP_SIS900_REV(sc,SIS_REV_900B)) 1203 sc->sc_cfg |= 1204 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1205 CFG_EDBMASTEN); 1206 } 1207 1208 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1209 1210 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1211 ether_sprintf(enaddr)); 1212 1213 /* 1214 * Initialize the configuration register: aggressive PCI 1215 * bus request algorithm, default backoff, default OW timer, 1216 * default parity error detection. 1217 * 1218 * NOTE: "Big endian mode" is useless on the SiS900 and 1219 * friends -- it affects packet data, not descriptors. 1220 */ 1221 if (sc->sc_gigabit) 1222 sipcom_dp83820_attach(sc, pa); 1223 1224 /* 1225 * Initialize our media structures and probe the MII. 1226 */ 1227 sc->sc_mii.mii_ifp = ifp; 1228 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1229 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1230 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1231 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1232 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1233 sipcom_mediastatus); 1234 1235 /* 1236 * XXX We cannot handle flow control on the DP83815. 1237 */ 1238 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1239 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, 0); 1241 else 1242 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1243 MII_OFFSET_ANY, MIIF_DOPAUSE); 1244 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1245 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1247 } else 1248 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1249 1250 ifp = &sc->sc_ethercom.ec_if; 1251 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1252 ifp->if_softc = sc; 1253 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1254 sc->sc_if_flags = ifp->if_flags; 1255 ifp->if_ioctl = sipcom_ioctl; 1256 ifp->if_start = sipcom_start; 1257 ifp->if_watchdog = sipcom_watchdog; 1258 ifp->if_init = sipcom_init; 1259 ifp->if_stop = sipcom_stop; 1260 IFQ_SET_READY(&ifp->if_snd); 1261 1262 /* 1263 * We can support 802.1Q VLAN-sized frames. 1264 */ 1265 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1266 1267 if (sc->sc_gigabit) { 1268 /* 1269 * And the DP83820 can do VLAN tagging in hardware, and 1270 * support the jumbo Ethernet MTU. 1271 */ 1272 sc->sc_ethercom.ec_capabilities |= 1273 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1274 1275 /* 1276 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1277 * in hardware. 1278 */ 1279 ifp->if_capabilities |= 1280 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1281 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1282 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1283 } 1284 1285 /* 1286 * Attach the interface. 1287 */ 1288 if_attach(ifp); 1289 ether_ifattach(ifp, enaddr); 1290 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1291 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1292 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1293 sc->sc_prev.if_capenable = ifp->if_capenable; 1294 #if NRND > 0 1295 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1296 RND_TYPE_NET, 0); 1297 #endif 1298 1299 /* 1300 * The number of bytes that must be available in 1301 * the Tx FIFO before the bus master can DMA more 1302 * data into the FIFO. 1303 */ 1304 sc->sc_tx_fill_thresh = 64 / 32; 1305 1306 /* 1307 * Start at a drain threshold of 512 bytes. We will 1308 * increase it if a DMA underrun occurs. 1309 * 1310 * XXX The minimum value of this variable should be 1311 * tuned. We may be able to improve performance 1312 * by starting with a lower value. That, however, 1313 * may trash the first few outgoing packets if the 1314 * PCI bus is saturated. 1315 */ 1316 if (sc->sc_gigabit) 1317 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1318 else 1319 sc->sc_tx_drain_thresh = 1504 / 32; 1320 1321 /* 1322 * Initialize the Rx FIFO drain threshold. 1323 * 1324 * This is in units of 8 bytes. 1325 * 1326 * We should never set this value lower than 2; 14 bytes are 1327 * required to filter the packet. 1328 */ 1329 sc->sc_rx_drain_thresh = 128 / 8; 1330 1331 #ifdef SIP_EVENT_COUNTERS 1332 /* 1333 * Attach event counters. 1334 */ 1335 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1336 NULL, device_xname(sc->sc_dev), "txsstall"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1338 NULL, device_xname(sc->sc_dev), "txdstall"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txforceintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "txdintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "txiintr"); 1345 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1346 NULL, device_xname(sc->sc_dev), "rxintr"); 1347 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1348 NULL, device_xname(sc->sc_dev), "hiberr"); 1349 if (!sc->sc_gigabit) { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1351 NULL, device_xname(sc->sc_dev), "rxpause"); 1352 } else { 1353 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxpause"); 1355 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "txpause"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxipsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txipsum"); 1365 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1366 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1367 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1368 NULL, device_xname(sc->sc_dev), "txudpsum"); 1369 } 1370 #endif /* SIP_EVENT_COUNTERS */ 1371 1372 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1373 pmf_class_network_register(self, ifp); 1374 else 1375 aprint_error_dev(self, "couldn't establish power handler\n"); 1376 } 1377 1378 static inline void 1379 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1380 uint64_t capenable) 1381 { 1382 struct m_tag *mtag; 1383 u_int32_t extsts; 1384 #ifdef DEBUG 1385 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1386 #endif 1387 /* 1388 * If VLANs are enabled and the packet has a VLAN tag, set 1389 * up the descriptor to encapsulate the packet for us. 1390 * 1391 * This apparently has to be on the last descriptor of 1392 * the packet. 1393 */ 1394 1395 /* 1396 * Byte swapping is tricky. We need to provide the tag 1397 * in a network byte order. On a big-endian machine, 1398 * the byteorder is correct, but we need to swap it 1399 * anyway, because this will be undone by the outside 1400 * htole32(). That's why there must be an 1401 * unconditional swap instead of htons() inside. 1402 */ 1403 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1404 sc->sc_txdescs[lasttx].sipd_extsts |= 1405 htole32(EXTSTS_VPKT | 1406 (bswap16(VLAN_TAG_VALUE(mtag)) & 1407 EXTSTS_VTCI)); 1408 } 1409 1410 /* 1411 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1412 * checksumming, set up the descriptor to do this work 1413 * for us. 1414 * 1415 * This apparently has to be on the first descriptor of 1416 * the packet. 1417 * 1418 * Byte-swap constants so the compiler can optimize. 1419 */ 1420 extsts = 0; 1421 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1422 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1423 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1424 extsts |= htole32(EXTSTS_IPPKT); 1425 } 1426 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1429 extsts |= htole32(EXTSTS_TCPPKT); 1430 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1431 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1432 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1433 extsts |= htole32(EXTSTS_UDPPKT); 1434 } 1435 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1436 } 1437 1438 /* 1439 * sip_start: [ifnet interface function] 1440 * 1441 * Start packet transmission on the interface. 1442 */ 1443 static void 1444 sipcom_start(struct ifnet *ifp) 1445 { 1446 struct sip_softc *sc = ifp->if_softc; 1447 struct mbuf *m0; 1448 struct mbuf *m; 1449 struct sip_txsoft *txs; 1450 bus_dmamap_t dmamap; 1451 int error, nexttx, lasttx, seg; 1452 int ofree = sc->sc_txfree; 1453 #if 0 1454 int firsttx = sc->sc_txnext; 1455 #endif 1456 1457 /* 1458 * If we've been told to pause, don't transmit any more packets. 1459 */ 1460 if (!sc->sc_gigabit && sc->sc_paused) 1461 ifp->if_flags |= IFF_OACTIVE; 1462 1463 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1464 return; 1465 1466 /* 1467 * Loop through the send queue, setting up transmit descriptors 1468 * until we drain the queue, or use up all available transmit 1469 * descriptors. 1470 */ 1471 for (;;) { 1472 /* Get a work queue entry. */ 1473 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1474 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1475 break; 1476 } 1477 1478 /* 1479 * Grab a packet off the queue. 1480 */ 1481 IFQ_POLL(&ifp->if_snd, m0); 1482 if (m0 == NULL) 1483 break; 1484 m = NULL; 1485 1486 dmamap = txs->txs_dmamap; 1487 1488 /* 1489 * Load the DMA map. If this fails, the packet either 1490 * didn't fit in the alloted number of segments, or we 1491 * were short on resources. 1492 */ 1493 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1494 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1495 /* In the non-gigabit case, we'll copy and try again. */ 1496 if (error != 0 && !sc->sc_gigabit) { 1497 MGETHDR(m, M_DONTWAIT, MT_DATA); 1498 if (m == NULL) { 1499 printf("%s: unable to allocate Tx mbuf\n", 1500 device_xname(sc->sc_dev)); 1501 break; 1502 } 1503 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1504 if (m0->m_pkthdr.len > MHLEN) { 1505 MCLGET(m, M_DONTWAIT); 1506 if ((m->m_flags & M_EXT) == 0) { 1507 printf("%s: unable to allocate Tx " 1508 "cluster\n", device_xname(sc->sc_dev)); 1509 m_freem(m); 1510 break; 1511 } 1512 } 1513 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1514 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1515 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1516 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1517 if (error) { 1518 printf("%s: unable to load Tx buffer, " 1519 "error = %d\n", device_xname(sc->sc_dev), error); 1520 break; 1521 } 1522 } else if (error == EFBIG) { 1523 /* 1524 * For the too-many-segments case, we simply 1525 * report an error and drop the packet, 1526 * since we can't sanely copy a jumbo packet 1527 * to a single buffer. 1528 */ 1529 printf("%s: Tx packet consumes too many " 1530 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1531 IFQ_DEQUEUE(&ifp->if_snd, m0); 1532 m_freem(m0); 1533 continue; 1534 } else if (error != 0) { 1535 /* 1536 * Short on resources, just stop for now. 1537 */ 1538 break; 1539 } 1540 1541 /* 1542 * Ensure we have enough descriptors free to describe 1543 * the packet. Note, we always reserve one descriptor 1544 * at the end of the ring as a termination point, to 1545 * prevent wrap-around. 1546 */ 1547 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1548 /* 1549 * Not enough free descriptors to transmit this 1550 * packet. We haven't committed anything yet, 1551 * so just unload the DMA map, put the packet 1552 * back on the queue, and punt. Notify the upper 1553 * layer that there are not more slots left. 1554 * 1555 * XXX We could allocate an mbuf and copy, but 1556 * XXX is it worth it? 1557 */ 1558 ifp->if_flags |= IFF_OACTIVE; 1559 bus_dmamap_unload(sc->sc_dmat, dmamap); 1560 if (m != NULL) 1561 m_freem(m); 1562 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1563 break; 1564 } 1565 1566 IFQ_DEQUEUE(&ifp->if_snd, m0); 1567 if (m != NULL) { 1568 m_freem(m0); 1569 m0 = m; 1570 } 1571 1572 /* 1573 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1574 */ 1575 1576 /* Sync the DMA map. */ 1577 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1578 BUS_DMASYNC_PREWRITE); 1579 1580 /* 1581 * Initialize the transmit descriptors. 1582 */ 1583 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1584 seg < dmamap->dm_nsegs; 1585 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1586 /* 1587 * If this is the first descriptor we're 1588 * enqueueing, don't set the OWN bit just 1589 * yet. That could cause a race condition. 1590 * We'll do it below. 1591 */ 1592 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1593 htole32(dmamap->dm_segs[seg].ds_addr); 1594 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1595 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1596 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1597 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1598 lasttx = nexttx; 1599 } 1600 1601 /* Clear the MORE bit on the last segment. */ 1602 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1603 htole32(~CMDSTS_MORE); 1604 1605 /* 1606 * If we're in the interrupt delay window, delay the 1607 * interrupt. 1608 */ 1609 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1610 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1611 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1612 htole32(CMDSTS_INTR); 1613 sc->sc_txwin = 0; 1614 } 1615 1616 if (sc->sc_gigabit) 1617 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1618 1619 /* Sync the descriptors we're using. */ 1620 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1621 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1622 1623 /* 1624 * The entire packet is set up. Give the first descrptor 1625 * to the chip now. 1626 */ 1627 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1628 htole32(CMDSTS_OWN); 1629 sip_cdtxsync(sc, sc->sc_txnext, 1, 1630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1631 1632 /* 1633 * Store a pointer to the packet so we can free it later, 1634 * and remember what txdirty will be once the packet is 1635 * done. 1636 */ 1637 txs->txs_mbuf = m0; 1638 txs->txs_firstdesc = sc->sc_txnext; 1639 txs->txs_lastdesc = lasttx; 1640 1641 /* Advance the tx pointer. */ 1642 sc->sc_txfree -= dmamap->dm_nsegs; 1643 sc->sc_txnext = nexttx; 1644 1645 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1646 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1647 1648 /* 1649 * Pass the packet to any BPF listeners. 1650 */ 1651 if (ifp->if_bpf) 1652 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 1653 } 1654 1655 if (txs == NULL || sc->sc_txfree == 0) { 1656 /* No more slots left; notify upper layer. */ 1657 ifp->if_flags |= IFF_OACTIVE; 1658 } 1659 1660 if (sc->sc_txfree != ofree) { 1661 /* 1662 * Start the transmit process. Note, the manual says 1663 * that if there are no pending transmissions in the 1664 * chip's internal queue (indicated by TXE being clear), 1665 * then the driver software must set the TXDP to the 1666 * first descriptor to be transmitted. However, if we 1667 * do this, it causes serious performance degredation on 1668 * the DP83820 under load, not setting TXDP doesn't seem 1669 * to adversely affect the SiS 900 or DP83815. 1670 * 1671 * Well, I guess it wouldn't be the first time a manual 1672 * has lied -- and they could be speaking of the NULL- 1673 * terminated descriptor list case, rather than OWN- 1674 * terminated rings. 1675 */ 1676 #if 0 1677 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1678 CR_TXE) == 0) { 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1680 SIP_CDTXADDR(sc, firsttx)); 1681 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1682 } 1683 #else 1684 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1685 #endif 1686 1687 /* Set a watchdog timer in case the chip flakes out. */ 1688 /* Gigabit autonegotiation takes 5 seconds. */ 1689 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1690 } 1691 } 1692 1693 /* 1694 * sip_watchdog: [ifnet interface function] 1695 * 1696 * Watchdog timer handler. 1697 */ 1698 static void 1699 sipcom_watchdog(struct ifnet *ifp) 1700 { 1701 struct sip_softc *sc = ifp->if_softc; 1702 1703 /* 1704 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1705 * If we get a timeout, try and sweep up transmit descriptors. 1706 * If we manage to sweep them all up, ignore the lack of 1707 * interrupt. 1708 */ 1709 sipcom_txintr(sc); 1710 1711 if (sc->sc_txfree != sc->sc_ntxdesc) { 1712 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1713 ifp->if_oerrors++; 1714 1715 /* Reset the interface. */ 1716 (void) sipcom_init(ifp); 1717 } else if (ifp->if_flags & IFF_DEBUG) 1718 printf("%s: recovered from device timeout\n", 1719 device_xname(sc->sc_dev)); 1720 1721 /* Try to get more packets going. */ 1722 sipcom_start(ifp); 1723 } 1724 1725 /* If the interface is up and running, only modify the receive 1726 * filter when setting promiscuous or debug mode. Otherwise fall 1727 * through to ether_ioctl, which will reset the chip. 1728 */ 1729 static int 1730 sip_ifflags_cb(struct ethercom *ec) 1731 { 1732 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1733 == (sc)->sc_ethercom.ec_capenable) \ 1734 && ((sc)->sc_prev.is_vlan == \ 1735 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1736 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1737 struct ifnet *ifp = &ec->ec_if; 1738 struct sip_softc *sc = ifp->if_softc; 1739 int change = ifp->if_flags ^ sc->sc_if_flags; 1740 1741 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1742 !COMPARE_IC(sc, ifp)) 1743 return ENETRESET; 1744 /* Set up the receive filter. */ 1745 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1746 return 0; 1747 } 1748 1749 /* 1750 * sip_ioctl: [ifnet interface function] 1751 * 1752 * Handle control requests from the operator. 1753 */ 1754 static int 1755 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1756 { 1757 struct sip_softc *sc = ifp->if_softc; 1758 struct ifreq *ifr = (struct ifreq *)data; 1759 int s, error; 1760 1761 s = splnet(); 1762 1763 switch (cmd) { 1764 case SIOCSIFMEDIA: 1765 /* Flow control requires full-duplex mode. */ 1766 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1767 (ifr->ifr_media & IFM_FDX) == 0) 1768 ifr->ifr_media &= ~IFM_ETH_FMASK; 1769 1770 /* XXX */ 1771 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1772 ifr->ifr_media &= ~IFM_ETH_FMASK; 1773 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1774 if (sc->sc_gigabit && 1775 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1776 /* We can do both TXPAUSE and RXPAUSE. */ 1777 ifr->ifr_media |= 1778 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1779 } else if (ifr->ifr_media & IFM_FLOW) { 1780 /* 1781 * Both TXPAUSE and RXPAUSE must be set. 1782 * (SiS900 and DP83815 don't have PAUSE_ASYM 1783 * feature.) 1784 * 1785 * XXX Can SiS900 and DP83815 send PAUSE? 1786 */ 1787 ifr->ifr_media |= 1788 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1789 } 1790 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1791 } 1792 /*FALLTHROUGH*/ 1793 default: 1794 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1795 break; 1796 1797 error = 0; 1798 1799 if (cmd == SIOCSIFCAP) 1800 error = (*ifp->if_init)(ifp); 1801 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1802 ; 1803 else if (ifp->if_flags & IFF_RUNNING) { 1804 /* 1805 * Multicast list has changed; set the hardware filter 1806 * accordingly. 1807 */ 1808 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1809 } 1810 break; 1811 } 1812 1813 /* Try to get more packets going. */ 1814 sipcom_start(ifp); 1815 1816 sc->sc_if_flags = ifp->if_flags; 1817 splx(s); 1818 return (error); 1819 } 1820 1821 /* 1822 * sip_intr: 1823 * 1824 * Interrupt service routine. 1825 */ 1826 static int 1827 sipcom_intr(void *arg) 1828 { 1829 struct sip_softc *sc = arg; 1830 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1831 u_int32_t isr; 1832 int handled = 0; 1833 1834 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1835 return 0; 1836 1837 /* Disable interrupts. */ 1838 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1839 1840 for (;;) { 1841 /* Reading clears interrupt. */ 1842 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1843 if ((isr & sc->sc_imr) == 0) 1844 break; 1845 1846 #if NRND > 0 1847 if (RND_ENABLED(&sc->rnd_source)) 1848 rnd_add_uint32(&sc->rnd_source, isr); 1849 #endif 1850 1851 handled = 1; 1852 1853 if ((ifp->if_flags & IFF_RUNNING) == 0) 1854 break; 1855 1856 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1857 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1858 1859 /* Grab any new packets. */ 1860 (*sc->sc_rxintr)(sc); 1861 1862 if (isr & ISR_RXORN) { 1863 printf("%s: receive FIFO overrun\n", 1864 device_xname(sc->sc_dev)); 1865 1866 /* XXX adjust rx_drain_thresh? */ 1867 } 1868 1869 if (isr & ISR_RXIDLE) { 1870 printf("%s: receive ring overrun\n", 1871 device_xname(sc->sc_dev)); 1872 1873 /* Get the receive process going again. */ 1874 bus_space_write_4(sc->sc_st, sc->sc_sh, 1875 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1876 bus_space_write_4(sc->sc_st, sc->sc_sh, 1877 SIP_CR, CR_RXE); 1878 } 1879 } 1880 1881 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1882 #ifdef SIP_EVENT_COUNTERS 1883 if (isr & ISR_TXDESC) 1884 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1885 else if (isr & ISR_TXIDLE) 1886 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1887 #endif 1888 1889 /* Sweep up transmit descriptors. */ 1890 sipcom_txintr(sc); 1891 1892 if (isr & ISR_TXURN) { 1893 u_int32_t thresh; 1894 int txfifo_size = (sc->sc_gigabit) 1895 ? DP83820_SIP_TXFIFO_SIZE 1896 : OTHER_SIP_TXFIFO_SIZE; 1897 1898 printf("%s: transmit FIFO underrun", 1899 device_xname(sc->sc_dev)); 1900 thresh = sc->sc_tx_drain_thresh + 1; 1901 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1902 && (thresh * 32) <= (txfifo_size - 1903 (sc->sc_tx_fill_thresh * 32))) { 1904 printf("; increasing Tx drain " 1905 "threshold to %u bytes\n", 1906 thresh * 32); 1907 sc->sc_tx_drain_thresh = thresh; 1908 (void) sipcom_init(ifp); 1909 } else { 1910 (void) sipcom_init(ifp); 1911 printf("\n"); 1912 } 1913 } 1914 } 1915 1916 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1917 if (isr & ISR_PAUSE_ST) { 1918 sc->sc_paused = 1; 1919 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1920 ifp->if_flags |= IFF_OACTIVE; 1921 } 1922 if (isr & ISR_PAUSE_END) { 1923 sc->sc_paused = 0; 1924 ifp->if_flags &= ~IFF_OACTIVE; 1925 } 1926 } 1927 1928 if (isr & ISR_HIBERR) { 1929 int want_init = 0; 1930 1931 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1932 1933 #define PRINTERR(bit, str) \ 1934 do { \ 1935 if ((isr & (bit)) != 0) { \ 1936 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1937 printf("%s: %s\n", \ 1938 device_xname(sc->sc_dev), str); \ 1939 want_init = 1; \ 1940 } \ 1941 } while (/*CONSTCOND*/0) 1942 1943 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1944 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1945 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1946 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1947 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1948 /* 1949 * Ignore: 1950 * Tx reset complete 1951 * Rx reset complete 1952 */ 1953 if (want_init) 1954 (void) sipcom_init(ifp); 1955 #undef PRINTERR 1956 } 1957 } 1958 1959 /* Re-enable interrupts. */ 1960 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1961 1962 /* Try to get more packets going. */ 1963 sipcom_start(ifp); 1964 1965 return (handled); 1966 } 1967 1968 /* 1969 * sip_txintr: 1970 * 1971 * Helper; handle transmit interrupts. 1972 */ 1973 static void 1974 sipcom_txintr(struct sip_softc *sc) 1975 { 1976 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1977 struct sip_txsoft *txs; 1978 u_int32_t cmdsts; 1979 1980 if (sc->sc_paused == 0) 1981 ifp->if_flags &= ~IFF_OACTIVE; 1982 1983 /* 1984 * Go through our Tx list and free mbufs for those 1985 * frames which have been transmitted. 1986 */ 1987 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1988 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1989 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1990 1991 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1992 if (cmdsts & CMDSTS_OWN) 1993 break; 1994 1995 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1996 1997 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1998 1999 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2000 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2001 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2002 m_freem(txs->txs_mbuf); 2003 txs->txs_mbuf = NULL; 2004 2005 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2006 2007 /* 2008 * Check for errors and collisions. 2009 */ 2010 if (cmdsts & 2011 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2012 ifp->if_oerrors++; 2013 if (cmdsts & CMDSTS_Tx_EC) 2014 ifp->if_collisions += 16; 2015 if (ifp->if_flags & IFF_DEBUG) { 2016 if (cmdsts & CMDSTS_Tx_ED) 2017 printf("%s: excessive deferral\n", 2018 device_xname(sc->sc_dev)); 2019 if (cmdsts & CMDSTS_Tx_EC) 2020 printf("%s: excessive collisions\n", 2021 device_xname(sc->sc_dev)); 2022 } 2023 } else { 2024 /* Packet was transmitted successfully. */ 2025 ifp->if_opackets++; 2026 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2027 } 2028 } 2029 2030 /* 2031 * If there are no more pending transmissions, cancel the watchdog 2032 * timer. 2033 */ 2034 if (txs == NULL) { 2035 ifp->if_timer = 0; 2036 sc->sc_txwin = 0; 2037 } 2038 } 2039 2040 /* 2041 * gsip_rxintr: 2042 * 2043 * Helper; handle receive interrupts on gigabit parts. 2044 */ 2045 static void 2046 gsip_rxintr(struct sip_softc *sc) 2047 { 2048 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2049 struct sip_rxsoft *rxs; 2050 struct mbuf *m; 2051 u_int32_t cmdsts, extsts; 2052 int i, len; 2053 2054 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2055 rxs = &sc->sc_rxsoft[i]; 2056 2057 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2058 2059 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2060 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2061 len = CMDSTS_SIZE(sc, cmdsts); 2062 2063 /* 2064 * NOTE: OWN is set if owned by _consumer_. We're the 2065 * consumer of the receive ring, so if the bit is clear, 2066 * we have processed all of the packets. 2067 */ 2068 if ((cmdsts & CMDSTS_OWN) == 0) { 2069 /* 2070 * We have processed all of the receive buffers. 2071 */ 2072 break; 2073 } 2074 2075 if (__predict_false(sc->sc_rxdiscard)) { 2076 sip_init_rxdesc(sc, i); 2077 if ((cmdsts & CMDSTS_MORE) == 0) { 2078 /* Reset our state. */ 2079 sc->sc_rxdiscard = 0; 2080 } 2081 continue; 2082 } 2083 2084 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2085 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2086 2087 m = rxs->rxs_mbuf; 2088 2089 /* 2090 * Add a new receive buffer to the ring. 2091 */ 2092 if (sipcom_add_rxbuf(sc, i) != 0) { 2093 /* 2094 * Failed, throw away what we've done so 2095 * far, and discard the rest of the packet. 2096 */ 2097 ifp->if_ierrors++; 2098 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2099 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2100 sip_init_rxdesc(sc, i); 2101 if (cmdsts & CMDSTS_MORE) 2102 sc->sc_rxdiscard = 1; 2103 if (sc->sc_rxhead != NULL) 2104 m_freem(sc->sc_rxhead); 2105 sip_rxchain_reset(sc); 2106 continue; 2107 } 2108 2109 sip_rxchain_link(sc, m); 2110 2111 m->m_len = len; 2112 2113 /* 2114 * If this is not the end of the packet, keep 2115 * looking. 2116 */ 2117 if (cmdsts & CMDSTS_MORE) { 2118 sc->sc_rxlen += len; 2119 continue; 2120 } 2121 2122 /* 2123 * Okay, we have the entire packet now. The chip includes 2124 * the FCS, so we need to trim it. 2125 */ 2126 m->m_len -= ETHER_CRC_LEN; 2127 2128 *sc->sc_rxtailp = NULL; 2129 len = m->m_len + sc->sc_rxlen; 2130 m = sc->sc_rxhead; 2131 2132 sip_rxchain_reset(sc); 2133 2134 /* 2135 * If an error occurred, update stats and drop the packet. 2136 */ 2137 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2138 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2139 ifp->if_ierrors++; 2140 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2141 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2142 /* Receive overrun handled elsewhere. */ 2143 printf("%s: receive descriptor error\n", 2144 device_xname(sc->sc_dev)); 2145 } 2146 #define PRINTERR(bit, str) \ 2147 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2148 (cmdsts & (bit)) != 0) \ 2149 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2150 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2151 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2152 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2153 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2154 #undef PRINTERR 2155 m_freem(m); 2156 continue; 2157 } 2158 2159 /* 2160 * If the packet is small enough to fit in a 2161 * single header mbuf, allocate one and copy 2162 * the data into it. This greatly reduces 2163 * memory consumption when we receive lots 2164 * of small packets. 2165 */ 2166 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2167 struct mbuf *nm; 2168 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2169 if (nm == NULL) { 2170 ifp->if_ierrors++; 2171 m_freem(m); 2172 continue; 2173 } 2174 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2175 nm->m_data += 2; 2176 nm->m_pkthdr.len = nm->m_len = len; 2177 m_copydata(m, 0, len, mtod(nm, void *)); 2178 m_freem(m); 2179 m = nm; 2180 } 2181 #ifndef __NO_STRICT_ALIGNMENT 2182 else { 2183 /* 2184 * The DP83820's receive buffers must be 4-byte 2185 * aligned. But this means that the data after 2186 * the Ethernet header is misaligned. To compensate, 2187 * we have artificially shortened the buffer size 2188 * in the descriptor, and we do an overlapping copy 2189 * of the data two bytes further in (in the first 2190 * buffer of the chain only). 2191 */ 2192 memmove(mtod(m, char *) + 2, mtod(m, void *), 2193 m->m_len); 2194 m->m_data += 2; 2195 } 2196 #endif /* ! __NO_STRICT_ALIGNMENT */ 2197 2198 /* 2199 * If VLANs are enabled, VLAN packets have been unwrapped 2200 * for us. Associate the tag with the packet. 2201 */ 2202 2203 /* 2204 * Again, byte swapping is tricky. Hardware provided 2205 * the tag in the network byte order, but extsts was 2206 * passed through le32toh() in the meantime. On a 2207 * big-endian machine, we need to swap it again. On a 2208 * little-endian machine, we need to convert from the 2209 * network to host byte order. This means that we must 2210 * swap it in any case, so unconditional swap instead 2211 * of htons() is used. 2212 */ 2213 if ((extsts & EXTSTS_VPKT) != 0) { 2214 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2215 continue); 2216 } 2217 2218 /* 2219 * Set the incoming checksum information for the 2220 * packet. 2221 */ 2222 if ((extsts & EXTSTS_IPPKT) != 0) { 2223 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2224 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2225 if (extsts & EXTSTS_Rx_IPERR) 2226 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2227 if (extsts & EXTSTS_TCPPKT) { 2228 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2229 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2230 if (extsts & EXTSTS_Rx_TCPERR) 2231 m->m_pkthdr.csum_flags |= 2232 M_CSUM_TCP_UDP_BAD; 2233 } else if (extsts & EXTSTS_UDPPKT) { 2234 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2235 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2236 if (extsts & EXTSTS_Rx_UDPERR) 2237 m->m_pkthdr.csum_flags |= 2238 M_CSUM_TCP_UDP_BAD; 2239 } 2240 } 2241 2242 ifp->if_ipackets++; 2243 m->m_pkthdr.rcvif = ifp; 2244 m->m_pkthdr.len = len; 2245 2246 /* 2247 * Pass this up to any BPF listeners, but only 2248 * pass if up the stack if it's for us. 2249 */ 2250 if (ifp->if_bpf) 2251 bpf_ops->bpf_mtap(ifp->if_bpf, m); 2252 2253 /* Pass it on. */ 2254 (*ifp->if_input)(ifp, m); 2255 } 2256 2257 /* Update the receive pointer. */ 2258 sc->sc_rxptr = i; 2259 } 2260 2261 /* 2262 * sip_rxintr: 2263 * 2264 * Helper; handle receive interrupts on 10/100 parts. 2265 */ 2266 static void 2267 sip_rxintr(struct sip_softc *sc) 2268 { 2269 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2270 struct sip_rxsoft *rxs; 2271 struct mbuf *m; 2272 u_int32_t cmdsts; 2273 int i, len; 2274 2275 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2276 rxs = &sc->sc_rxsoft[i]; 2277 2278 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2279 2280 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2281 2282 /* 2283 * NOTE: OWN is set if owned by _consumer_. We're the 2284 * consumer of the receive ring, so if the bit is clear, 2285 * we have processed all of the packets. 2286 */ 2287 if ((cmdsts & CMDSTS_OWN) == 0) { 2288 /* 2289 * We have processed all of the receive buffers. 2290 */ 2291 break; 2292 } 2293 2294 /* 2295 * If any collisions were seen on the wire, count one. 2296 */ 2297 if (cmdsts & CMDSTS_Rx_COL) 2298 ifp->if_collisions++; 2299 2300 /* 2301 * If an error occurred, update stats, clear the status 2302 * word, and leave the packet buffer in place. It will 2303 * simply be reused the next time the ring comes around. 2304 */ 2305 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2306 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2307 ifp->if_ierrors++; 2308 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2309 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2310 /* Receive overrun handled elsewhere. */ 2311 printf("%s: receive descriptor error\n", 2312 device_xname(sc->sc_dev)); 2313 } 2314 #define PRINTERR(bit, str) \ 2315 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2316 (cmdsts & (bit)) != 0) \ 2317 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2318 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2319 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2320 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2321 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2322 #undef PRINTERR 2323 sip_init_rxdesc(sc, i); 2324 continue; 2325 } 2326 2327 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2328 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2329 2330 /* 2331 * No errors; receive the packet. Note, the SiS 900 2332 * includes the CRC with every packet. 2333 */ 2334 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2335 2336 #ifdef __NO_STRICT_ALIGNMENT 2337 /* 2338 * If the packet is small enough to fit in a 2339 * single header mbuf, allocate one and copy 2340 * the data into it. This greatly reduces 2341 * memory consumption when we receive lots 2342 * of small packets. 2343 * 2344 * Otherwise, we add a new buffer to the receive 2345 * chain. If this fails, we drop the packet and 2346 * recycle the old buffer. 2347 */ 2348 if (sip_copy_small != 0 && len <= MHLEN) { 2349 MGETHDR(m, M_DONTWAIT, MT_DATA); 2350 if (m == NULL) 2351 goto dropit; 2352 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2353 memcpy(mtod(m, void *), 2354 mtod(rxs->rxs_mbuf, void *), len); 2355 sip_init_rxdesc(sc, i); 2356 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2357 rxs->rxs_dmamap->dm_mapsize, 2358 BUS_DMASYNC_PREREAD); 2359 } else { 2360 m = rxs->rxs_mbuf; 2361 if (sipcom_add_rxbuf(sc, i) != 0) { 2362 dropit: 2363 ifp->if_ierrors++; 2364 sip_init_rxdesc(sc, i); 2365 bus_dmamap_sync(sc->sc_dmat, 2366 rxs->rxs_dmamap, 0, 2367 rxs->rxs_dmamap->dm_mapsize, 2368 BUS_DMASYNC_PREREAD); 2369 continue; 2370 } 2371 } 2372 #else 2373 /* 2374 * The SiS 900's receive buffers must be 4-byte aligned. 2375 * But this means that the data after the Ethernet header 2376 * is misaligned. We must allocate a new buffer and 2377 * copy the data, shifted forward 2 bytes. 2378 */ 2379 MGETHDR(m, M_DONTWAIT, MT_DATA); 2380 if (m == NULL) { 2381 dropit: 2382 ifp->if_ierrors++; 2383 sip_init_rxdesc(sc, i); 2384 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2385 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2386 continue; 2387 } 2388 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2389 if (len > (MHLEN - 2)) { 2390 MCLGET(m, M_DONTWAIT); 2391 if ((m->m_flags & M_EXT) == 0) { 2392 m_freem(m); 2393 goto dropit; 2394 } 2395 } 2396 m->m_data += 2; 2397 2398 /* 2399 * Note that we use clusters for incoming frames, so the 2400 * buffer is virtually contiguous. 2401 */ 2402 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2403 2404 /* Allow the receive descriptor to continue using its mbuf. */ 2405 sip_init_rxdesc(sc, i); 2406 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2407 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2408 #endif /* __NO_STRICT_ALIGNMENT */ 2409 2410 ifp->if_ipackets++; 2411 m->m_pkthdr.rcvif = ifp; 2412 m->m_pkthdr.len = m->m_len = len; 2413 2414 /* 2415 * Pass this up to any BPF listeners, but only 2416 * pass if up the stack if it's for us. 2417 */ 2418 if (ifp->if_bpf) 2419 bpf_ops->bpf_mtap(ifp->if_bpf, m); 2420 2421 /* Pass it on. */ 2422 (*ifp->if_input)(ifp, m); 2423 } 2424 2425 /* Update the receive pointer. */ 2426 sc->sc_rxptr = i; 2427 } 2428 2429 /* 2430 * sip_tick: 2431 * 2432 * One second timer, used to tick the MII. 2433 */ 2434 static void 2435 sipcom_tick(void *arg) 2436 { 2437 struct sip_softc *sc = arg; 2438 int s; 2439 2440 s = splnet(); 2441 #ifdef SIP_EVENT_COUNTERS 2442 if (sc->sc_gigabit) { 2443 /* Read PAUSE related counts from MIB registers. */ 2444 sc->sc_ev_rxpause.ev_count += 2445 bus_space_read_4(sc->sc_st, sc->sc_sh, 2446 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2447 sc->sc_ev_txpause.ev_count += 2448 bus_space_read_4(sc->sc_st, sc->sc_sh, 2449 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2450 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2451 } 2452 #endif /* SIP_EVENT_COUNTERS */ 2453 mii_tick(&sc->sc_mii); 2454 splx(s); 2455 2456 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2457 } 2458 2459 /* 2460 * sip_reset: 2461 * 2462 * Perform a soft reset on the SiS 900. 2463 */ 2464 static bool 2465 sipcom_reset(struct sip_softc *sc) 2466 { 2467 bus_space_tag_t st = sc->sc_st; 2468 bus_space_handle_t sh = sc->sc_sh; 2469 int i; 2470 2471 bus_space_write_4(st, sh, SIP_IER, 0); 2472 bus_space_write_4(st, sh, SIP_IMR, 0); 2473 bus_space_write_4(st, sh, SIP_RFCR, 0); 2474 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2475 2476 for (i = 0; i < SIP_TIMEOUT; i++) { 2477 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2478 break; 2479 delay(2); 2480 } 2481 2482 if (i == SIP_TIMEOUT) { 2483 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2484 return false; 2485 } 2486 2487 delay(1000); 2488 2489 if (sc->sc_gigabit) { 2490 /* 2491 * Set the general purpose I/O bits. Do it here in case we 2492 * need to have GPIO set up to talk to the media interface. 2493 */ 2494 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2495 delay(1000); 2496 } 2497 return true; 2498 } 2499 2500 static void 2501 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2502 { 2503 u_int32_t reg; 2504 bus_space_tag_t st = sc->sc_st; 2505 bus_space_handle_t sh = sc->sc_sh; 2506 /* 2507 * Initialize the VLAN/IP receive control register. 2508 * We enable checksum computation on all incoming 2509 * packets, and do not reject packets w/ bad checksums. 2510 */ 2511 reg = 0; 2512 if (capenable & 2513 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2514 reg |= VRCR_IPEN; 2515 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2516 reg |= VRCR_VTDEN|VRCR_VTREN; 2517 bus_space_write_4(st, sh, SIP_VRCR, reg); 2518 2519 /* 2520 * Initialize the VLAN/IP transmit control register. 2521 * We enable outgoing checksum computation on a 2522 * per-packet basis. 2523 */ 2524 reg = 0; 2525 if (capenable & 2526 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2527 reg |= VTCR_PPCHK; 2528 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2529 reg |= VTCR_VPPTI; 2530 bus_space_write_4(st, sh, SIP_VTCR, reg); 2531 2532 /* 2533 * If we're using VLANs, initialize the VLAN data register. 2534 * To understand why we bswap the VLAN Ethertype, see section 2535 * 4.2.36 of the DP83820 manual. 2536 */ 2537 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2538 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2539 } 2540 2541 /* 2542 * sip_init: [ ifnet interface function ] 2543 * 2544 * Initialize the interface. Must be called at splnet(). 2545 */ 2546 static int 2547 sipcom_init(struct ifnet *ifp) 2548 { 2549 struct sip_softc *sc = ifp->if_softc; 2550 bus_space_tag_t st = sc->sc_st; 2551 bus_space_handle_t sh = sc->sc_sh; 2552 struct sip_txsoft *txs; 2553 struct sip_rxsoft *rxs; 2554 struct sip_desc *sipd; 2555 int i, error = 0; 2556 2557 if (device_is_active(sc->sc_dev)) { 2558 /* 2559 * Cancel any pending I/O. 2560 */ 2561 sipcom_stop(ifp, 0); 2562 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2563 !device_is_active(sc->sc_dev)) 2564 return 0; 2565 2566 /* 2567 * Reset the chip to a known state. 2568 */ 2569 if (!sipcom_reset(sc)) 2570 return EBUSY; 2571 2572 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2573 /* 2574 * DP83815 manual, page 78: 2575 * 4.4 Recommended Registers Configuration 2576 * For optimum performance of the DP83815, version noted 2577 * as DP83815CVNG (SRR = 203h), the listed register 2578 * modifications must be followed in sequence... 2579 * 2580 * It's not clear if this should be 302h or 203h because that 2581 * chip name is listed as SRR 302h in the description of the 2582 * SRR register. However, my revision 302h DP83815 on the 2583 * Netgear FA311 purchased in 02/2001 needs these settings 2584 * to avoid tons of errors in AcceptPerfectMatch (non- 2585 * IFF_PROMISC) mode. I do not know if other revisions need 2586 * this set or not. [briggs -- 09 March 2001] 2587 * 2588 * Note that only the low-order 12 bits of 0xe4 are documented 2589 * and that this sets reserved bits in that register. 2590 */ 2591 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2592 2593 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2594 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2595 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2596 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2597 2598 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2599 } 2600 2601 /* 2602 * Initialize the transmit descriptor ring. 2603 */ 2604 for (i = 0; i < sc->sc_ntxdesc; i++) { 2605 sipd = &sc->sc_txdescs[i]; 2606 memset(sipd, 0, sizeof(struct sip_desc)); 2607 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2608 } 2609 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2610 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2611 sc->sc_txfree = sc->sc_ntxdesc; 2612 sc->sc_txnext = 0; 2613 sc->sc_txwin = 0; 2614 2615 /* 2616 * Initialize the transmit job descriptors. 2617 */ 2618 SIMPLEQ_INIT(&sc->sc_txfreeq); 2619 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2620 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2621 txs = &sc->sc_txsoft[i]; 2622 txs->txs_mbuf = NULL; 2623 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2624 } 2625 2626 /* 2627 * Initialize the receive descriptor and receive job 2628 * descriptor rings. 2629 */ 2630 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2631 rxs = &sc->sc_rxsoft[i]; 2632 if (rxs->rxs_mbuf == NULL) { 2633 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2634 printf("%s: unable to allocate or map rx " 2635 "buffer %d, error = %d\n", 2636 device_xname(sc->sc_dev), i, error); 2637 /* 2638 * XXX Should attempt to run with fewer receive 2639 * XXX buffers instead of just failing. 2640 */ 2641 sipcom_rxdrain(sc); 2642 goto out; 2643 } 2644 } else 2645 sip_init_rxdesc(sc, i); 2646 } 2647 sc->sc_rxptr = 0; 2648 sc->sc_rxdiscard = 0; 2649 sip_rxchain_reset(sc); 2650 2651 /* 2652 * Set the configuration register; it's already initialized 2653 * in sip_attach(). 2654 */ 2655 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2656 2657 /* 2658 * Initialize the prototype TXCFG register. 2659 */ 2660 if (sc->sc_gigabit) { 2661 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2662 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2663 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2664 SIP_SIS900_REV(sc, SIS_REV_960) || 2665 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2666 (sc->sc_cfg & CFG_EDBMASTEN)) { 2667 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2668 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2669 } else { 2670 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2671 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2672 } 2673 2674 sc->sc_txcfg |= TXCFG_ATP | 2675 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2676 sc->sc_tx_drain_thresh; 2677 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2678 2679 /* 2680 * Initialize the receive drain threshold if we have never 2681 * done so. 2682 */ 2683 if (sc->sc_rx_drain_thresh == 0) { 2684 /* 2685 * XXX This value should be tuned. This is set to the 2686 * maximum of 248 bytes, and we may be able to improve 2687 * performance by decreasing it (although we should never 2688 * set this value lower than 2; 14 bytes are required to 2689 * filter the packet). 2690 */ 2691 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2692 } 2693 2694 /* 2695 * Initialize the prototype RXCFG register. 2696 */ 2697 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2698 /* 2699 * Accept long packets (including FCS) so we can handle 2700 * 802.1q-tagged frames and jumbo frames properly. 2701 */ 2702 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2703 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2704 sc->sc_rxcfg |= RXCFG_ALP; 2705 2706 /* 2707 * Checksum offloading is disabled if the user selects an MTU 2708 * larger than 8109. (FreeBSD says 8152, but there is emperical 2709 * evidence that >8109 does not work on some boards, such as the 2710 * Planex GN-1000TE). 2711 */ 2712 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2713 (ifp->if_capenable & 2714 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2715 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2716 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2717 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2718 "disabled.\n", device_xname(sc->sc_dev)); 2719 ifp->if_capenable &= 2720 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2721 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2722 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2723 ifp->if_csum_flags_tx = 0; 2724 ifp->if_csum_flags_rx = 0; 2725 } 2726 2727 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2728 2729 if (sc->sc_gigabit) 2730 sipcom_dp83820_init(sc, ifp->if_capenable); 2731 2732 /* 2733 * Give the transmit and receive rings to the chip. 2734 */ 2735 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2736 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2737 2738 /* 2739 * Initialize the interrupt mask. 2740 */ 2741 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2742 sc->sc_bits.b_isr_sserr | 2743 sc->sc_bits.b_isr_rmabt | 2744 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2745 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2746 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2747 2748 /* Set up the receive filter. */ 2749 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2750 2751 /* 2752 * Tune sc_rx_flow_thresh. 2753 * XXX "More than 8KB" is too short for jumbo frames. 2754 * XXX TODO: Threshold value should be user-settable. 2755 */ 2756 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2757 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2758 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2759 2760 /* 2761 * Set the current media. Do this after initializing the prototype 2762 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2763 * control. 2764 */ 2765 if ((error = ether_mediachange(ifp)) != 0) 2766 goto out; 2767 2768 /* 2769 * Set the interrupt hold-off timer to 100us. 2770 */ 2771 if (sc->sc_gigabit) 2772 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2773 2774 /* 2775 * Enable interrupts. 2776 */ 2777 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2778 2779 /* 2780 * Start the transmit and receive processes. 2781 */ 2782 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2783 2784 /* 2785 * Start the one second MII clock. 2786 */ 2787 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2788 2789 /* 2790 * ...all done! 2791 */ 2792 ifp->if_flags |= IFF_RUNNING; 2793 ifp->if_flags &= ~IFF_OACTIVE; 2794 sc->sc_if_flags = ifp->if_flags; 2795 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2796 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2797 sc->sc_prev.if_capenable = ifp->if_capenable; 2798 2799 out: 2800 if (error) 2801 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2802 return (error); 2803 } 2804 2805 /* 2806 * sip_drain: 2807 * 2808 * Drain the receive queue. 2809 */ 2810 static void 2811 sipcom_rxdrain(struct sip_softc *sc) 2812 { 2813 struct sip_rxsoft *rxs; 2814 int i; 2815 2816 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2817 rxs = &sc->sc_rxsoft[i]; 2818 if (rxs->rxs_mbuf != NULL) { 2819 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2820 m_freem(rxs->rxs_mbuf); 2821 rxs->rxs_mbuf = NULL; 2822 } 2823 } 2824 } 2825 2826 /* 2827 * sip_stop: [ ifnet interface function ] 2828 * 2829 * Stop transmission on the interface. 2830 */ 2831 static void 2832 sipcom_stop(struct ifnet *ifp, int disable) 2833 { 2834 struct sip_softc *sc = ifp->if_softc; 2835 bus_space_tag_t st = sc->sc_st; 2836 bus_space_handle_t sh = sc->sc_sh; 2837 struct sip_txsoft *txs; 2838 u_int32_t cmdsts = 0; /* DEBUG */ 2839 2840 /* 2841 * Stop the one second clock. 2842 */ 2843 callout_stop(&sc->sc_tick_ch); 2844 2845 /* Down the MII. */ 2846 mii_down(&sc->sc_mii); 2847 2848 if (device_is_active(sc->sc_dev)) { 2849 /* 2850 * Disable interrupts. 2851 */ 2852 bus_space_write_4(st, sh, SIP_IER, 0); 2853 2854 /* 2855 * Stop receiver and transmitter. 2856 */ 2857 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2858 } 2859 2860 /* 2861 * Release any queued transmit buffers. 2862 */ 2863 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2864 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2865 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2866 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2867 CMDSTS_INTR) == 0) 2868 printf("%s: sip_stop: last descriptor does not " 2869 "have INTR bit set\n", device_xname(sc->sc_dev)); 2870 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2871 #ifdef DIAGNOSTIC 2872 if (txs->txs_mbuf == NULL) { 2873 printf("%s: dirty txsoft with no mbuf chain\n", 2874 device_xname(sc->sc_dev)); 2875 panic("sip_stop"); 2876 } 2877 #endif 2878 cmdsts |= /* DEBUG */ 2879 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2880 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2881 m_freem(txs->txs_mbuf); 2882 txs->txs_mbuf = NULL; 2883 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2884 } 2885 2886 /* 2887 * Mark the interface down and cancel the watchdog timer. 2888 */ 2889 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2890 ifp->if_timer = 0; 2891 2892 if (disable) 2893 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2894 2895 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2896 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2897 printf("%s: sip_stop: no INTR bits set in dirty tx " 2898 "descriptors\n", device_xname(sc->sc_dev)); 2899 } 2900 2901 /* 2902 * sip_read_eeprom: 2903 * 2904 * Read data from the serial EEPROM. 2905 */ 2906 static void 2907 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2908 u_int16_t *data) 2909 { 2910 bus_space_tag_t st = sc->sc_st; 2911 bus_space_handle_t sh = sc->sc_sh; 2912 u_int16_t reg; 2913 int i, x; 2914 2915 for (i = 0; i < wordcnt; i++) { 2916 /* Send CHIP SELECT. */ 2917 reg = EROMAR_EECS; 2918 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2919 2920 /* Shift in the READ opcode. */ 2921 for (x = 3; x > 0; x--) { 2922 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2923 reg |= EROMAR_EEDI; 2924 else 2925 reg &= ~EROMAR_EEDI; 2926 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2927 bus_space_write_4(st, sh, SIP_EROMAR, 2928 reg | EROMAR_EESK); 2929 delay(4); 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 delay(4); 2932 } 2933 2934 /* Shift in address. */ 2935 for (x = 6; x > 0; x--) { 2936 if ((word + i) & (1 << (x - 1))) 2937 reg |= EROMAR_EEDI; 2938 else 2939 reg &= ~EROMAR_EEDI; 2940 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2941 bus_space_write_4(st, sh, SIP_EROMAR, 2942 reg | EROMAR_EESK); 2943 delay(4); 2944 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2945 delay(4); 2946 } 2947 2948 /* Shift out data. */ 2949 reg = EROMAR_EECS; 2950 data[i] = 0; 2951 for (x = 16; x > 0; x--) { 2952 bus_space_write_4(st, sh, SIP_EROMAR, 2953 reg | EROMAR_EESK); 2954 delay(4); 2955 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2956 data[i] |= (1 << (x - 1)); 2957 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2958 delay(4); 2959 } 2960 2961 /* Clear CHIP SELECT. */ 2962 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2963 delay(4); 2964 } 2965 } 2966 2967 /* 2968 * sipcom_add_rxbuf: 2969 * 2970 * Add a receive buffer to the indicated descriptor. 2971 */ 2972 static int 2973 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2974 { 2975 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2976 struct mbuf *m; 2977 int error; 2978 2979 MGETHDR(m, M_DONTWAIT, MT_DATA); 2980 if (m == NULL) 2981 return (ENOBUFS); 2982 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2983 2984 MCLGET(m, M_DONTWAIT); 2985 if ((m->m_flags & M_EXT) == 0) { 2986 m_freem(m); 2987 return (ENOBUFS); 2988 } 2989 2990 /* XXX I don't believe this is necessary. --dyoung */ 2991 if (sc->sc_gigabit) 2992 m->m_len = sc->sc_parm->p_rxbuf_len; 2993 2994 if (rxs->rxs_mbuf != NULL) 2995 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2996 2997 rxs->rxs_mbuf = m; 2998 2999 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3000 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3001 BUS_DMA_READ|BUS_DMA_NOWAIT); 3002 if (error) { 3003 printf("%s: can't load rx DMA map %d, error = %d\n", 3004 device_xname(sc->sc_dev), idx, error); 3005 panic("%s", __func__); /* XXX */ 3006 } 3007 3008 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3009 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3010 3011 sip_init_rxdesc(sc, idx); 3012 3013 return (0); 3014 } 3015 3016 /* 3017 * sip_sis900_set_filter: 3018 * 3019 * Set up the receive filter. 3020 */ 3021 static void 3022 sipcom_sis900_set_filter(struct sip_softc *sc) 3023 { 3024 bus_space_tag_t st = sc->sc_st; 3025 bus_space_handle_t sh = sc->sc_sh; 3026 struct ethercom *ec = &sc->sc_ethercom; 3027 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3028 struct ether_multi *enm; 3029 const u_int8_t *cp; 3030 struct ether_multistep step; 3031 u_int32_t crc, mchash[16]; 3032 3033 /* 3034 * Initialize the prototype RFCR. 3035 */ 3036 sc->sc_rfcr = RFCR_RFEN; 3037 if (ifp->if_flags & IFF_BROADCAST) 3038 sc->sc_rfcr |= RFCR_AAB; 3039 if (ifp->if_flags & IFF_PROMISC) { 3040 sc->sc_rfcr |= RFCR_AAP; 3041 goto allmulti; 3042 } 3043 3044 /* 3045 * Set up the multicast address filter by passing all multicast 3046 * addresses through a CRC generator, and then using the high-order 3047 * 6 bits as an index into the 128 bit multicast hash table (only 3048 * the lower 16 bits of each 32 bit multicast hash register are 3049 * valid). The high order bits select the register, while the 3050 * rest of the bits select the bit within the register. 3051 */ 3052 3053 memset(mchash, 0, sizeof(mchash)); 3054 3055 /* 3056 * SiS900 (at least SiS963) requires us to register the address of 3057 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3058 */ 3059 crc = 0x0ed423f9; 3060 3061 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3062 SIP_SIS900_REV(sc, SIS_REV_960) || 3063 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3064 /* Just want the 8 most significant bits. */ 3065 crc >>= 24; 3066 } else { 3067 /* Just want the 7 most significant bits. */ 3068 crc >>= 25; 3069 } 3070 3071 /* Set the corresponding bit in the hash table. */ 3072 mchash[crc >> 4] |= 1 << (crc & 0xf); 3073 3074 ETHER_FIRST_MULTI(step, ec, enm); 3075 while (enm != NULL) { 3076 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3077 /* 3078 * We must listen to a range of multicast addresses. 3079 * For now, just accept all multicasts, rather than 3080 * trying to set only those filter bits needed to match 3081 * the range. (At this time, the only use of address 3082 * ranges is for IP multicast routing, for which the 3083 * range is big enough to require all bits set.) 3084 */ 3085 goto allmulti; 3086 } 3087 3088 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3089 3090 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3091 SIP_SIS900_REV(sc, SIS_REV_960) || 3092 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3093 /* Just want the 8 most significant bits. */ 3094 crc >>= 24; 3095 } else { 3096 /* Just want the 7 most significant bits. */ 3097 crc >>= 25; 3098 } 3099 3100 /* Set the corresponding bit in the hash table. */ 3101 mchash[crc >> 4] |= 1 << (crc & 0xf); 3102 3103 ETHER_NEXT_MULTI(step, enm); 3104 } 3105 3106 ifp->if_flags &= ~IFF_ALLMULTI; 3107 goto setit; 3108 3109 allmulti: 3110 ifp->if_flags |= IFF_ALLMULTI; 3111 sc->sc_rfcr |= RFCR_AAM; 3112 3113 setit: 3114 #define FILTER_EMIT(addr, data) \ 3115 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3116 delay(1); \ 3117 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3118 delay(1) 3119 3120 /* 3121 * Disable receive filter, and program the node address. 3122 */ 3123 cp = CLLADDR(ifp->if_sadl); 3124 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3125 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3126 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3127 3128 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3129 /* 3130 * Program the multicast hash table. 3131 */ 3132 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3133 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3134 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3135 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3136 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3137 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3138 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3139 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3140 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3141 SIP_SIS900_REV(sc, SIS_REV_960) || 3142 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3143 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3144 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3145 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3146 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3147 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3148 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3149 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3150 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3151 } 3152 } 3153 #undef FILTER_EMIT 3154 3155 /* 3156 * Re-enable the receiver filter. 3157 */ 3158 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3159 } 3160 3161 /* 3162 * sip_dp83815_set_filter: 3163 * 3164 * Set up the receive filter. 3165 */ 3166 static void 3167 sipcom_dp83815_set_filter(struct sip_softc *sc) 3168 { 3169 bus_space_tag_t st = sc->sc_st; 3170 bus_space_handle_t sh = sc->sc_sh; 3171 struct ethercom *ec = &sc->sc_ethercom; 3172 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3173 struct ether_multi *enm; 3174 const u_int8_t *cp; 3175 struct ether_multistep step; 3176 u_int32_t crc, hash, slot, bit; 3177 #define MCHASH_NWORDS_83820 128 3178 #define MCHASH_NWORDS_83815 32 3179 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3180 u_int16_t mchash[MCHASH_NWORDS]; 3181 int i; 3182 3183 /* 3184 * Initialize the prototype RFCR. 3185 * Enable the receive filter, and accept on 3186 * Perfect (destination address) Match 3187 * If IFF_BROADCAST, also accept all broadcast packets. 3188 * If IFF_PROMISC, accept all unicast packets (and later, set 3189 * IFF_ALLMULTI and accept all multicast, too). 3190 */ 3191 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3192 if (ifp->if_flags & IFF_BROADCAST) 3193 sc->sc_rfcr |= RFCR_AAB; 3194 if (ifp->if_flags & IFF_PROMISC) { 3195 sc->sc_rfcr |= RFCR_AAP; 3196 goto allmulti; 3197 } 3198 3199 /* 3200 * Set up the DP83820/DP83815 multicast address filter by 3201 * passing all multicast addresses through a CRC generator, 3202 * and then using the high-order 11/9 bits as an index into 3203 * the 2048/512 bit multicast hash table. The high-order 3204 * 7/5 bits select the slot, while the low-order 4 bits 3205 * select the bit within the slot. Note that only the low 3206 * 16-bits of each filter word are used, and there are 3207 * 128/32 filter words. 3208 */ 3209 3210 memset(mchash, 0, sizeof(mchash)); 3211 3212 ifp->if_flags &= ~IFF_ALLMULTI; 3213 ETHER_FIRST_MULTI(step, ec, enm); 3214 if (enm == NULL) 3215 goto setit; 3216 while (enm != NULL) { 3217 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3218 /* 3219 * We must listen to a range of multicast addresses. 3220 * For now, just accept all multicasts, rather than 3221 * trying to set only those filter bits needed to match 3222 * the range. (At this time, the only use of address 3223 * ranges is for IP multicast routing, for which the 3224 * range is big enough to require all bits set.) 3225 */ 3226 goto allmulti; 3227 } 3228 3229 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3230 3231 if (sc->sc_gigabit) { 3232 /* Just want the 11 most significant bits. */ 3233 hash = crc >> 21; 3234 } else { 3235 /* Just want the 9 most significant bits. */ 3236 hash = crc >> 23; 3237 } 3238 3239 slot = hash >> 4; 3240 bit = hash & 0xf; 3241 3242 /* Set the corresponding bit in the hash table. */ 3243 mchash[slot] |= 1 << bit; 3244 3245 ETHER_NEXT_MULTI(step, enm); 3246 } 3247 sc->sc_rfcr |= RFCR_MHEN; 3248 goto setit; 3249 3250 allmulti: 3251 ifp->if_flags |= IFF_ALLMULTI; 3252 sc->sc_rfcr |= RFCR_AAM; 3253 3254 setit: 3255 #define FILTER_EMIT(addr, data) \ 3256 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3257 delay(1); \ 3258 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3259 delay(1) 3260 3261 /* 3262 * Disable receive filter, and program the node address. 3263 */ 3264 cp = CLLADDR(ifp->if_sadl); 3265 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3266 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3267 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3268 3269 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3270 int nwords = 3271 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3272 /* 3273 * Program the multicast hash table. 3274 */ 3275 for (i = 0; i < nwords; i++) { 3276 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3277 } 3278 } 3279 #undef FILTER_EMIT 3280 #undef MCHASH_NWORDS 3281 #undef MCHASH_NWORDS_83815 3282 #undef MCHASH_NWORDS_83820 3283 3284 /* 3285 * Re-enable the receiver filter. 3286 */ 3287 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3288 } 3289 3290 /* 3291 * sip_dp83820_mii_readreg: [mii interface function] 3292 * 3293 * Read a PHY register on the MII of the DP83820. 3294 */ 3295 static int 3296 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3297 { 3298 struct sip_softc *sc = device_private(self); 3299 3300 if (sc->sc_cfg & CFG_TBI_EN) { 3301 bus_addr_t tbireg; 3302 int rv; 3303 3304 if (phy != 0) 3305 return (0); 3306 3307 switch (reg) { 3308 case MII_BMCR: tbireg = SIP_TBICR; break; 3309 case MII_BMSR: tbireg = SIP_TBISR; break; 3310 case MII_ANAR: tbireg = SIP_TANAR; break; 3311 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3312 case MII_ANER: tbireg = SIP_TANER; break; 3313 case MII_EXTSR: 3314 /* 3315 * Don't even bother reading the TESR register. 3316 * The manual documents that the device has 3317 * 1000baseX full/half capability, but the 3318 * register itself seems read back 0 on some 3319 * boards. Just hard-code the result. 3320 */ 3321 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3322 3323 default: 3324 return (0); 3325 } 3326 3327 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3328 if (tbireg == SIP_TBISR) { 3329 /* LINK and ACOMP are switched! */ 3330 int val = rv; 3331 3332 rv = 0; 3333 if (val & TBISR_MR_LINK_STATUS) 3334 rv |= BMSR_LINK; 3335 if (val & TBISR_MR_AN_COMPLETE) 3336 rv |= BMSR_ACOMP; 3337 3338 /* 3339 * The manual claims this register reads back 0 3340 * on hard and soft reset. But we want to let 3341 * the gentbi driver know that we support auto- 3342 * negotiation, so hard-code this bit in the 3343 * result. 3344 */ 3345 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3346 } 3347 3348 return (rv); 3349 } 3350 3351 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3352 } 3353 3354 /* 3355 * sip_dp83820_mii_writereg: [mii interface function] 3356 * 3357 * Write a PHY register on the MII of the DP83820. 3358 */ 3359 static void 3360 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3361 { 3362 struct sip_softc *sc = device_private(self); 3363 3364 if (sc->sc_cfg & CFG_TBI_EN) { 3365 bus_addr_t tbireg; 3366 3367 if (phy != 0) 3368 return; 3369 3370 switch (reg) { 3371 case MII_BMCR: tbireg = SIP_TBICR; break; 3372 case MII_ANAR: tbireg = SIP_TANAR; break; 3373 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3374 default: 3375 return; 3376 } 3377 3378 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3379 return; 3380 } 3381 3382 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3383 } 3384 3385 /* 3386 * sip_dp83820_mii_statchg: [mii interface function] 3387 * 3388 * Callback from MII layer when media changes. 3389 */ 3390 static void 3391 sipcom_dp83820_mii_statchg(device_t self) 3392 { 3393 struct sip_softc *sc = device_private(self); 3394 struct mii_data *mii = &sc->sc_mii; 3395 u_int32_t cfg, pcr; 3396 3397 /* 3398 * Get flow control negotiation result. 3399 */ 3400 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3401 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3402 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3403 mii->mii_media_active &= ~IFM_ETH_FMASK; 3404 } 3405 3406 /* 3407 * Update TXCFG for full-duplex operation. 3408 */ 3409 if ((mii->mii_media_active & IFM_FDX) != 0) 3410 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3411 else 3412 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3413 3414 /* 3415 * Update RXCFG for full-duplex or loopback. 3416 */ 3417 if ((mii->mii_media_active & IFM_FDX) != 0 || 3418 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3419 sc->sc_rxcfg |= RXCFG_ATX; 3420 else 3421 sc->sc_rxcfg &= ~RXCFG_ATX; 3422 3423 /* 3424 * Update CFG for MII/GMII. 3425 */ 3426 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3427 cfg = sc->sc_cfg | CFG_MODE_1000; 3428 else 3429 cfg = sc->sc_cfg; 3430 3431 /* 3432 * 802.3x flow control. 3433 */ 3434 pcr = 0; 3435 if (sc->sc_flowflags & IFM_FLOW) { 3436 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3437 pcr |= sc->sc_rx_flow_thresh; 3438 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3439 pcr |= PCR_PSEN | PCR_PS_MCAST; 3440 } 3441 3442 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3443 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3444 sc->sc_txcfg); 3445 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3446 sc->sc_rxcfg); 3447 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3448 } 3449 3450 /* 3451 * sip_mii_bitbang_read: [mii bit-bang interface function] 3452 * 3453 * Read the MII serial port for the MII bit-bang module. 3454 */ 3455 static u_int32_t 3456 sipcom_mii_bitbang_read(device_t self) 3457 { 3458 struct sip_softc *sc = device_private(self); 3459 3460 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3461 } 3462 3463 /* 3464 * sip_mii_bitbang_write: [mii big-bang interface function] 3465 * 3466 * Write the MII serial port for the MII bit-bang module. 3467 */ 3468 static void 3469 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3470 { 3471 struct sip_softc *sc = device_private(self); 3472 3473 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3474 } 3475 3476 /* 3477 * sip_sis900_mii_readreg: [mii interface function] 3478 * 3479 * Read a PHY register on the MII. 3480 */ 3481 static int 3482 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3483 { 3484 struct sip_softc *sc = device_private(self); 3485 u_int32_t enphy; 3486 3487 /* 3488 * The PHY of recent SiS chipsets is accessed through bitbang 3489 * operations. 3490 */ 3491 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3492 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3493 phy, reg); 3494 3495 #ifndef SIS900_MII_RESTRICT 3496 /* 3497 * The SiS 900 has only an internal PHY on the MII. Only allow 3498 * MII address 0. 3499 */ 3500 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3501 return (0); 3502 #endif 3503 3504 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3505 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3506 ENPHY_RWCMD | ENPHY_ACCESS); 3507 do { 3508 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3509 } while (enphy & ENPHY_ACCESS); 3510 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3511 } 3512 3513 /* 3514 * sip_sis900_mii_writereg: [mii interface function] 3515 * 3516 * Write a PHY register on the MII. 3517 */ 3518 static void 3519 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3520 { 3521 struct sip_softc *sc = device_private(self); 3522 u_int32_t enphy; 3523 3524 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3525 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3526 phy, reg, val); 3527 return; 3528 } 3529 3530 #ifndef SIS900_MII_RESTRICT 3531 /* 3532 * The SiS 900 has only an internal PHY on the MII. Only allow 3533 * MII address 0. 3534 */ 3535 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3536 return; 3537 #endif 3538 3539 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3540 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3541 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3542 do { 3543 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3544 } while (enphy & ENPHY_ACCESS); 3545 } 3546 3547 /* 3548 * sip_sis900_mii_statchg: [mii interface function] 3549 * 3550 * Callback from MII layer when media changes. 3551 */ 3552 static void 3553 sipcom_sis900_mii_statchg(device_t self) 3554 { 3555 struct sip_softc *sc = device_private(self); 3556 struct mii_data *mii = &sc->sc_mii; 3557 u_int32_t flowctl; 3558 3559 /* 3560 * Get flow control negotiation result. 3561 */ 3562 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3563 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3564 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3565 mii->mii_media_active &= ~IFM_ETH_FMASK; 3566 } 3567 3568 /* 3569 * Update TXCFG for full-duplex operation. 3570 */ 3571 if ((mii->mii_media_active & IFM_FDX) != 0) 3572 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3573 else 3574 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3575 3576 /* 3577 * Update RXCFG for full-duplex or loopback. 3578 */ 3579 if ((mii->mii_media_active & IFM_FDX) != 0 || 3580 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3581 sc->sc_rxcfg |= RXCFG_ATX; 3582 else 3583 sc->sc_rxcfg &= ~RXCFG_ATX; 3584 3585 /* 3586 * Update IMR for use of 802.3x flow control. 3587 */ 3588 if (sc->sc_flowflags & IFM_FLOW) { 3589 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3590 flowctl = FLOWCTL_FLOWEN; 3591 } else { 3592 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3593 flowctl = 0; 3594 } 3595 3596 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3597 sc->sc_txcfg); 3598 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3599 sc->sc_rxcfg); 3600 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3601 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3602 } 3603 3604 /* 3605 * sip_dp83815_mii_readreg: [mii interface function] 3606 * 3607 * Read a PHY register on the MII. 3608 */ 3609 static int 3610 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3611 { 3612 struct sip_softc *sc = device_private(self); 3613 u_int32_t val; 3614 3615 /* 3616 * The DP83815 only has an internal PHY. Only allow 3617 * MII address 0. 3618 */ 3619 if (phy != 0) 3620 return (0); 3621 3622 /* 3623 * Apparently, after a reset, the DP83815 can take a while 3624 * to respond. During this recovery period, the BMSR returns 3625 * a value of 0. Catch this -- it's not supposed to happen 3626 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3627 * PHY to come back to life. 3628 * 3629 * This works out because the BMSR is the first register 3630 * read during the PHY probe process. 3631 */ 3632 do { 3633 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3634 } while (reg == MII_BMSR && val == 0); 3635 3636 return (val & 0xffff); 3637 } 3638 3639 /* 3640 * sip_dp83815_mii_writereg: [mii interface function] 3641 * 3642 * Write a PHY register to the MII. 3643 */ 3644 static void 3645 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3646 { 3647 struct sip_softc *sc = device_private(self); 3648 3649 /* 3650 * The DP83815 only has an internal PHY. Only allow 3651 * MII address 0. 3652 */ 3653 if (phy != 0) 3654 return; 3655 3656 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3657 } 3658 3659 /* 3660 * sip_dp83815_mii_statchg: [mii interface function] 3661 * 3662 * Callback from MII layer when media changes. 3663 */ 3664 static void 3665 sipcom_dp83815_mii_statchg(device_t self) 3666 { 3667 struct sip_softc *sc = device_private(self); 3668 3669 /* 3670 * Update TXCFG for full-duplex operation. 3671 */ 3672 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3673 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3674 else 3675 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3676 3677 /* 3678 * Update RXCFG for full-duplex or loopback. 3679 */ 3680 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3681 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3682 sc->sc_rxcfg |= RXCFG_ATX; 3683 else 3684 sc->sc_rxcfg &= ~RXCFG_ATX; 3685 3686 /* 3687 * XXX 802.3x flow control. 3688 */ 3689 3690 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3691 sc->sc_txcfg); 3692 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3693 sc->sc_rxcfg); 3694 3695 /* 3696 * Some DP83815s experience problems when used with short 3697 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3698 * sequence adjusts the DSP's signal attenuation to fix the 3699 * problem. 3700 */ 3701 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3702 uint32_t reg; 3703 3704 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3705 3706 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3707 reg &= 0x0fff; 3708 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3709 delay(100); 3710 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3711 reg &= 0x00ff; 3712 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3713 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3714 0x00e8); 3715 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3716 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3717 reg | 0x20); 3718 } 3719 3720 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3721 } 3722 } 3723 3724 static void 3725 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3726 const struct pci_attach_args *pa, u_int8_t *enaddr) 3727 { 3728 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3729 u_int8_t cksum, *e, match; 3730 int i; 3731 3732 /* 3733 * EEPROM data format for the DP83820 can be found in 3734 * the DP83820 manual, section 4.2.4. 3735 */ 3736 3737 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3738 3739 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3740 match = ~(match - 1); 3741 3742 cksum = 0x55; 3743 e = (u_int8_t *) eeprom_data; 3744 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3745 cksum += *e++; 3746 3747 if (cksum != match) 3748 printf("%s: Checksum (%x) mismatch (%x)", 3749 device_xname(sc->sc_dev), cksum, match); 3750 3751 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3752 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3753 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3754 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3755 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3756 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3757 } 3758 3759 static void 3760 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3761 { 3762 int i; 3763 3764 /* 3765 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3766 * a reason, but I don't know it. 3767 */ 3768 for (i = 0; i < 10; i++) 3769 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3770 } 3771 3772 static void 3773 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3774 const struct pci_attach_args *pa, u_int8_t *enaddr) 3775 { 3776 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3777 3778 switch (sc->sc_rev) { 3779 case SIS_REV_630S: 3780 case SIS_REV_630E: 3781 case SIS_REV_630EA1: 3782 case SIS_REV_630ET: 3783 case SIS_REV_635: 3784 /* 3785 * The MAC address for the on-board Ethernet of 3786 * the SiS 630 chipset is in the NVRAM. Kick 3787 * the chip into re-loading it from NVRAM, and 3788 * read the MAC address out of the filter registers. 3789 */ 3790 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3791 3792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3793 RFCR_RFADDR_NODE0); 3794 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3795 0xffff; 3796 3797 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3798 RFCR_RFADDR_NODE2); 3799 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3800 0xffff; 3801 3802 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3803 RFCR_RFADDR_NODE4); 3804 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3805 0xffff; 3806 break; 3807 3808 case SIS_REV_960: 3809 { 3810 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3811 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3812 3813 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3814 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3815 3816 int waittime, i; 3817 3818 /* Allow to read EEPROM from LAN. It is shared 3819 * between a 1394 controller and the NIC and each 3820 * time we access it, we need to set SIS_EECMD_REQ. 3821 */ 3822 SIS_SET_EROMAR(sc, EROMAR_REQ); 3823 3824 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3825 /* Force EEPROM to idle state. */ 3826 3827 /* 3828 * XXX-cube This is ugly. I'll look for docs about it. 3829 */ 3830 SIS_SET_EROMAR(sc, EROMAR_EECS); 3831 sipcom_sis900_eeprom_delay(sc); 3832 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3833 SIS_SET_EROMAR(sc, EROMAR_EESK); 3834 sipcom_sis900_eeprom_delay(sc); 3835 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3836 sipcom_sis900_eeprom_delay(sc); 3837 } 3838 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3839 sipcom_sis900_eeprom_delay(sc); 3840 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3841 3842 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3843 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3844 sizeof(myea) / sizeof(myea[0]), myea); 3845 break; 3846 } 3847 DELAY(1); 3848 } 3849 3850 /* 3851 * Set SIS_EECTL_CLK to high, so a other master 3852 * can operate on the i2c bus. 3853 */ 3854 SIS_SET_EROMAR(sc, EROMAR_EESK); 3855 3856 /* Refuse EEPROM access by LAN */ 3857 SIS_SET_EROMAR(sc, EROMAR_DONE); 3858 } break; 3859 3860 default: 3861 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3862 sizeof(myea) / sizeof(myea[0]), myea); 3863 } 3864 3865 enaddr[0] = myea[0] & 0xff; 3866 enaddr[1] = myea[0] >> 8; 3867 enaddr[2] = myea[1] & 0xff; 3868 enaddr[3] = myea[1] >> 8; 3869 enaddr[4] = myea[2] & 0xff; 3870 enaddr[5] = myea[2] >> 8; 3871 } 3872 3873 /* Table and macro to bit-reverse an octet. */ 3874 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3875 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3876 3877 static void 3878 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3879 const struct pci_attach_args *pa, u_int8_t *enaddr) 3880 { 3881 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3882 u_int8_t cksum, *e, match; 3883 int i; 3884 3885 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3886 sizeof(eeprom_data[0]), eeprom_data); 3887 3888 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3889 match = ~(match - 1); 3890 3891 cksum = 0x55; 3892 e = (u_int8_t *) eeprom_data; 3893 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3894 cksum += *e++; 3895 } 3896 if (cksum != match) { 3897 printf("%s: Checksum (%x) mismatch (%x)", 3898 device_xname(sc->sc_dev), cksum, match); 3899 } 3900 3901 /* 3902 * Unrolled because it makes slightly more sense this way. 3903 * The DP83815 stores the MAC address in bit 0 of word 6 3904 * through bit 15 of word 8. 3905 */ 3906 ea = &eeprom_data[6]; 3907 enaddr[0] = ((*ea & 0x1) << 7); 3908 ea++; 3909 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3910 enaddr[1] = ((*ea & 0x1FE) >> 1); 3911 enaddr[2] = ((*ea & 0x1) << 7); 3912 ea++; 3913 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3914 enaddr[3] = ((*ea & 0x1FE) >> 1); 3915 enaddr[4] = ((*ea & 0x1) << 7); 3916 ea++; 3917 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3918 enaddr[5] = ((*ea & 0x1FE) >> 1); 3919 3920 /* 3921 * In case that's not weird enough, we also need to reverse 3922 * the bits in each byte. This all actually makes more sense 3923 * if you think about the EEPROM storage as an array of bits 3924 * being shifted into bytes, but that's not how we're looking 3925 * at it here... 3926 */ 3927 for (i = 0; i < 6 ;i++) 3928 enaddr[i] = bbr(enaddr[i]); 3929 } 3930 3931 /* 3932 * sip_mediastatus: [ifmedia interface function] 3933 * 3934 * Get the current interface media status. 3935 */ 3936 static void 3937 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3938 { 3939 struct sip_softc *sc = ifp->if_softc; 3940 3941 if (!device_is_active(sc->sc_dev)) { 3942 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3943 ifmr->ifm_status = 0; 3944 return; 3945 } 3946 ether_mediastatus(ifp, ifmr); 3947 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3948 sc->sc_flowflags; 3949 } 3950
Indexes created Tue Sep 30 11:09:46 GMT 2025