if_sip.c revision 1.133
1 /* $NetBSD: if_sip.c,v 1.133 2008/04/28 20:23:55 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.133 2008/04/28 20:23:55 martin Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/queue.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #include <sys/bus.h> 109 #include <sys/intr.h> 110 #include <machine/endian.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 #include <dev/mii/mii_bitbang.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_sipreg.h> 121 122 /* 123 * Transmit descriptor list size. This is arbitrary, but allocate 124 * enough descriptors for 128 pending transmissions, and 8 segments 125 * per packet (64 for DP83820 for jumbo frames). 126 * 127 * This MUST work out to a power of 2. 128 */ 129 #define GSIP_NTXSEGS_ALLOC 16 130 #define SIP_NTXSEGS_ALLOC 8 131 132 #define SIP_TXQUEUELEN 256 133 #define MAX_SIP_NTXDESC \ 134 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 135 136 /* 137 * Receive descriptor list size. We have one Rx buffer per incoming 138 * packet, so this logic is a little simpler. 139 * 140 * Actually, on the DP83820, we allow the packet to consume more than 141 * one buffer, in order to support jumbo Ethernet frames. In that 142 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 143 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 144 * so we'd better be quick about handling receive interrupts. 145 */ 146 #define GSIP_NRXDESC 256 147 #define SIP_NRXDESC 128 148 149 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 150 151 /* 152 * Control structures are DMA'd to the SiS900 chip. We allocate them in 153 * a single clump that maps to a single DMA segment to make several things 154 * easier. 155 */ 156 struct sip_control_data { 157 /* 158 * The transmit descriptors. 159 */ 160 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 161 162 /* 163 * The receive descriptors. 164 */ 165 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 166 }; 167 168 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 169 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 170 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 171 172 /* 173 * Software state for transmit jobs. 174 */ 175 struct sip_txsoft { 176 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 177 bus_dmamap_t txs_dmamap; /* our DMA map */ 178 int txs_firstdesc; /* first descriptor in packet */ 179 int txs_lastdesc; /* last descriptor in packet */ 180 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 181 }; 182 183 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 184 185 /* 186 * Software state for receive jobs. 187 */ 188 struct sip_rxsoft { 189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t rxs_dmamap; /* our DMA map */ 191 }; 192 193 enum sip_attach_stage { 194 SIP_ATTACH_FIN = 0 195 , SIP_ATTACH_CREATE_RXMAP 196 , SIP_ATTACH_CREATE_TXMAP 197 , SIP_ATTACH_LOAD_MAP 198 , SIP_ATTACH_CREATE_MAP 199 , SIP_ATTACH_MAP_MEM 200 , SIP_ATTACH_ALLOC_MEM 201 , SIP_ATTACH_INTR 202 , SIP_ATTACH_MAP 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static void sipcom_start(struct ifnet *); 563 static void sipcom_watchdog(struct ifnet *); 564 static int sipcom_ioctl(struct ifnet *, u_long, void *); 565 static int sipcom_init(struct ifnet *); 566 static void sipcom_stop(struct ifnet *, int); 567 568 static bool sipcom_reset(struct sip_softc *); 569 static void sipcom_rxdrain(struct sip_softc *); 570 static int sipcom_add_rxbuf(struct sip_softc *, int); 571 static void sipcom_read_eeprom(struct sip_softc *, int, int, 572 u_int16_t *); 573 static void sipcom_tick(void *); 574 575 static void sipcom_sis900_set_filter(struct sip_softc *); 576 static void sipcom_dp83815_set_filter(struct sip_softc *); 577 578 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 581 static void sipcom_sis900_read_macaddr(struct sip_softc *, 582 const struct pci_attach_args *, u_int8_t *); 583 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 584 const struct pci_attach_args *, u_int8_t *); 585 586 static int sipcom_intr(void *); 587 static void sipcom_txintr(struct sip_softc *); 588 static void sip_rxintr(struct sip_softc *); 589 static void gsip_rxintr(struct sip_softc *); 590 591 static int sipcom_dp83820_mii_readreg(device_t, int, int); 592 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 593 static void sipcom_dp83820_mii_statchg(device_t); 594 595 static int sipcom_sis900_mii_readreg(device_t, int, int); 596 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 597 static void sipcom_sis900_mii_statchg(device_t); 598 599 static int sipcom_dp83815_mii_readreg(device_t, int, int); 600 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 601 static void sipcom_dp83815_mii_statchg(device_t); 602 603 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 604 605 static int sipcom_match(device_t, struct cfdata *, void *); 606 static void sipcom_attach(device_t, device_t, void *); 607 static void sipcom_do_detach(device_t, enum sip_attach_stage); 608 static int sipcom_detach(device_t, int); 609 static bool sipcom_resume(device_t PMF_FN_PROTO); 610 static bool sipcom_suspend(device_t PMF_FN_PROTO); 611 612 int gsip_copy_small = 0; 613 int sip_copy_small = 0; 614 615 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 616 sipcom_match, sipcom_attach, sipcom_detach, NULL); 617 CFATTACH_DECL(sip, sizeof(struct sip_softc), 618 sipcom_match, sipcom_attach, sipcom_detach, NULL); 619 620 /* 621 * Descriptions of the variants of the SiS900. 622 */ 623 struct sip_variant { 624 int (*sipv_mii_readreg)(device_t, int, int); 625 void (*sipv_mii_writereg)(device_t, int, int, int); 626 void (*sipv_mii_statchg)(device_t); 627 void (*sipv_set_filter)(struct sip_softc *); 628 void (*sipv_read_macaddr)(struct sip_softc *, 629 const struct pci_attach_args *, u_int8_t *); 630 }; 631 632 static u_int32_t sipcom_mii_bitbang_read(device_t); 633 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 634 635 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 636 sipcom_mii_bitbang_read, 637 sipcom_mii_bitbang_write, 638 { 639 EROMAR_MDIO, /* MII_BIT_MDO */ 640 EROMAR_MDIO, /* MII_BIT_MDI */ 641 EROMAR_MDC, /* MII_BIT_MDC */ 642 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 643 0, /* MII_BIT_DIR_PHY_HOST */ 644 } 645 }; 646 647 static const struct sip_variant sipcom_variant_dp83820 = { 648 sipcom_dp83820_mii_readreg, 649 sipcom_dp83820_mii_writereg, 650 sipcom_dp83820_mii_statchg, 651 sipcom_dp83815_set_filter, 652 sipcom_dp83820_read_macaddr, 653 }; 654 655 static const struct sip_variant sipcom_variant_sis900 = { 656 sipcom_sis900_mii_readreg, 657 sipcom_sis900_mii_writereg, 658 sipcom_sis900_mii_statchg, 659 sipcom_sis900_set_filter, 660 sipcom_sis900_read_macaddr, 661 }; 662 663 static const struct sip_variant sipcom_variant_dp83815 = { 664 sipcom_dp83815_mii_readreg, 665 sipcom_dp83815_mii_writereg, 666 sipcom_dp83815_mii_statchg, 667 sipcom_dp83815_set_filter, 668 sipcom_dp83815_read_macaddr, 669 }; 670 671 672 /* 673 * Devices supported by this driver. 674 */ 675 static const struct sip_product { 676 pci_vendor_id_t sip_vendor; 677 pci_product_id_t sip_product; 678 const char *sip_name; 679 const struct sip_variant *sip_variant; 680 int sip_gigabit; 681 } sipcom_products[] = { 682 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 683 "NatSemi DP83820 Gigabit Ethernet", 684 &sipcom_variant_dp83820, 1 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 686 "SiS 900 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 689 "SiS 7016 10/100 Ethernet", 690 &sipcom_variant_sis900, 0 }, 691 692 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 693 "NatSemi DP83815 10/100 Ethernet", 694 &sipcom_variant_dp83815, 0 }, 695 696 { 0, 0, 697 NULL, 698 NULL, 0 }, 699 }; 700 701 static const struct sip_product * 702 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 703 { 704 const struct sip_product *sip; 705 706 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 707 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 708 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 709 sip->sip_gigabit == gigabit) 710 return sip; 711 } 712 return NULL; 713 } 714 715 /* 716 * I really hate stupid hardware vendors. There's a bit in the EEPROM 717 * which indicates if the card can do 64-bit data transfers. Unfortunately, 718 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 719 * which means we try to use 64-bit data transfers on those cards if we 720 * happen to be plugged into a 32-bit slot. 721 * 722 * What we do is use this table of cards known to be 64-bit cards. If 723 * you have a 64-bit card who's subsystem ID is not listed in this table, 724 * send the output of "pcictl dump ..." of the device to me so that your 725 * card will use the 64-bit data path when plugged into a 64-bit slot. 726 * 727 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 728 * June 30, 2002 729 */ 730 static int 731 sipcom_check_64bit(const struct pci_attach_args *pa) 732 { 733 static const struct { 734 pci_vendor_id_t c64_vendor; 735 pci_product_id_t c64_product; 736 } card64[] = { 737 /* Asante GigaNIX */ 738 { 0x128a, 0x0002 }, 739 740 /* Accton EN1407-T, Planex GN-1000TE */ 741 { 0x1113, 0x1407 }, 742 743 /* Netgear GA-621 */ 744 { 0x1385, 0x621a }, 745 746 /* SMC EZ Card */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(&sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(&sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(&sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 #if NRND > 0 914 rnd_detach_source(&sc->rnd_source); 915 #endif 916 917 ether_ifdetach(ifp); 918 if_detach(ifp); 919 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 920 921 /*FALLTHROUGH*/ 922 case SIP_ATTACH_CREATE_RXMAP: 923 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 924 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 925 bus_dmamap_destroy(sc->sc_dmat, 926 sc->sc_rxsoft[i].rxs_dmamap); 927 } 928 /*FALLTHROUGH*/ 929 case SIP_ATTACH_CREATE_TXMAP: 930 for (i = 0; i < SIP_TXQUEUELEN; i++) { 931 if (sc->sc_txsoft[i].txs_dmamap != NULL) 932 bus_dmamap_destroy(sc->sc_dmat, 933 sc->sc_txsoft[i].txs_dmamap); 934 } 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_LOAD_MAP: 937 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 938 /*FALLTHROUGH*/ 939 case SIP_ATTACH_CREATE_MAP: 940 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_MAP_MEM: 943 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 944 sizeof(struct sip_control_data)); 945 /*FALLTHROUGH*/ 946 case SIP_ATTACH_ALLOC_MEM: 947 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 948 /* FALLTHROUGH*/ 949 case SIP_ATTACH_INTR: 950 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 951 /* FALLTHROUGH*/ 952 case SIP_ATTACH_MAP: 953 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 954 break; 955 default: 956 break; 957 } 958 return; 959 } 960 961 static bool 962 sipcom_resume(device_t self PMF_FN_ARGS) 963 { 964 struct sip_softc *sc = device_private(self); 965 966 return sipcom_reset(sc); 967 } 968 969 static bool 970 sipcom_suspend(device_t self PMF_FN_ARGS) 971 { 972 struct sip_softc *sc = device_private(self); 973 974 sipcom_rxdrain(sc); 975 return true; 976 } 977 978 static void 979 sipcom_attach(device_t parent, device_t self, void *aux) 980 { 981 struct sip_softc *sc = device_private(self); 982 struct pci_attach_args *pa = aux; 983 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 984 pci_chipset_tag_t pc = pa->pa_pc; 985 pci_intr_handle_t ih; 986 const char *intrstr = NULL; 987 bus_space_tag_t iot, memt; 988 bus_space_handle_t ioh, memh; 989 bus_size_t iosz, memsz; 990 int ioh_valid, memh_valid; 991 int i, rseg, error; 992 const struct sip_product *sip; 993 u_int8_t enaddr[ETHER_ADDR_LEN]; 994 pcireg_t pmreg; 995 pcireg_t memtype; 996 bus_size_t tx_dmamap_size; 997 int ntxsegs_alloc; 998 cfdata_t cf = device_cfdata(self); 999 1000 callout_init(&sc->sc_tick_ch, 0); 1001 1002 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1003 if (sip == NULL) { 1004 printf("\n"); 1005 panic("%s: impossible", __func__); 1006 } 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1027 1028 sc->sc_model = sip; 1029 1030 /* 1031 * XXX Work-around broken PXE firmware on some boards. 1032 * 1033 * The DP83815 shares an address decoder with the MEM BAR 1034 * and the ROM BAR. Make sure the ROM BAR is disabled, 1035 * so that memory mapped access works. 1036 */ 1037 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1038 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1039 ~PCI_MAPREG_ROM_ENABLE); 1040 1041 /* 1042 * Map the device. 1043 */ 1044 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1045 PCI_MAPREG_TYPE_IO, 0, 1046 &iot, &ioh, NULL, &iosz) == 0); 1047 if (sc->sc_gigabit) { 1048 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1049 switch (memtype) { 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1052 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1053 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1054 break; 1055 default: 1056 memh_valid = 0; 1057 } 1058 } else { 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1061 &memt, &memh, NULL, &memsz) == 0); 1062 } 1063 1064 if (memh_valid) { 1065 sc->sc_st = memt; 1066 sc->sc_sh = memh; 1067 sc->sc_sz = memsz; 1068 } else if (ioh_valid) { 1069 sc->sc_st = iot; 1070 sc->sc_sh = ioh; 1071 sc->sc_sz = iosz; 1072 } else { 1073 printf("%s: unable to map device registers\n", 1074 device_xname(&sc->sc_dev)); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 pmreg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 pmreg |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 pmreg | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) && 1092 error != EOPNOTSUPP) { 1093 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", 1094 error); 1095 return; 1096 } 1097 1098 /* 1099 * Map and establish our interrupt. 1100 */ 1101 if (pci_intr_map(pa, &ih)) { 1102 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 1103 return; 1104 } 1105 intrstr = pci_intr_string(pc, ih); 1106 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1107 if (sc->sc_ih == NULL) { 1108 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 1109 if (intrstr != NULL) 1110 printf(" at %s", intrstr); 1111 printf("\n"); 1112 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1113 } 1114 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1115 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 1119 /* 1120 * Allocate the control data structures, and create and load the 1121 * DMA map for it. 1122 */ 1123 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1124 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1125 &rseg, 0)) != 0) { 1126 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1127 error); 1128 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1129 } 1130 1131 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1132 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1133 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1134 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1135 error); 1136 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->sc_dmat, 1140 sizeof(struct sip_control_data), 1, 1141 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1142 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1143 "error = %d\n", error); 1144 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1148 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1149 0)) != 0) { 1150 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1151 error); 1152 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1153 } 1154 1155 /* 1156 * Create the transmit buffer DMA maps. 1157 */ 1158 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1159 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1160 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1161 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1162 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 1163 "error = %d\n", i, error); 1164 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1165 } 1166 } 1167 1168 /* 1169 * Create the receive buffer DMA maps. 1170 */ 1171 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1172 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1173 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1174 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 1175 "error = %d\n", i, error); 1176 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1177 } 1178 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1179 } 1180 1181 /* 1182 * Reset the chip to a known state. 1183 */ 1184 sipcom_reset(sc); 1185 1186 /* 1187 * Read the Ethernet address from the EEPROM. This might 1188 * also fetch other stuff from the EEPROM and stash it 1189 * in the softc. 1190 */ 1191 sc->sc_cfg = 0; 1192 if (!sc->sc_gigabit) { 1193 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1194 SIP_SIS900_REV(sc,SIS_REV_900B)) 1195 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1196 1197 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1198 SIP_SIS900_REV(sc,SIS_REV_960) || 1199 SIP_SIS900_REV(sc,SIS_REV_900B)) 1200 sc->sc_cfg |= 1201 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1202 CFG_EDBMASTEN); 1203 } 1204 1205 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1206 1207 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 1208 ether_sprintf(enaddr)); 1209 1210 /* 1211 * Initialize the configuration register: aggressive PCI 1212 * bus request algorithm, default backoff, default OW timer, 1213 * default parity error detection. 1214 * 1215 * NOTE: "Big endian mode" is useless on the SiS900 and 1216 * friends -- it affects packet data, not descriptors. 1217 */ 1218 if (sc->sc_gigabit) 1219 sipcom_dp83820_attach(sc, pa); 1220 1221 /* 1222 * Initialize our media structures and probe the MII. 1223 */ 1224 sc->sc_mii.mii_ifp = ifp; 1225 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1226 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1227 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1228 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1229 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1244 } else 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 ether_ifattach(ifp, enaddr); 1287 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1288 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1289 sc->sc_prev.if_capenable = ifp->if_capenable; 1290 #if NRND > 0 1291 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 1292 RND_TYPE_NET, 0); 1293 #endif 1294 1295 /* 1296 * The number of bytes that must be available in 1297 * the Tx FIFO before the bus master can DMA more 1298 * data into the FIFO. 1299 */ 1300 sc->sc_tx_fill_thresh = 64 / 32; 1301 1302 /* 1303 * Start at a drain threshold of 512 bytes. We will 1304 * increase it if a DMA underrun occurs. 1305 * 1306 * XXX The minimum value of this variable should be 1307 * tuned. We may be able to improve performance 1308 * by starting with a lower value. That, however, 1309 * may trash the first few outgoing packets if the 1310 * PCI bus is saturated. 1311 */ 1312 if (sc->sc_gigabit) 1313 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1314 else 1315 sc->sc_tx_drain_thresh = 1504 / 32; 1316 1317 /* 1318 * Initialize the Rx FIFO drain threshold. 1319 * 1320 * This is in units of 8 bytes. 1321 * 1322 * We should never set this value lower than 2; 14 bytes are 1323 * required to filter the packet. 1324 */ 1325 sc->sc_rx_drain_thresh = 128 / 8; 1326 1327 #ifdef SIP_EVENT_COUNTERS 1328 /* 1329 * Attach event counters. 1330 */ 1331 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1332 NULL, device_xname(&sc->sc_dev), "txsstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1334 NULL, device_xname(&sc->sc_dev), "txdstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(&sc->sc_dev), "txforceintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(&sc->sc_dev), "txdintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(&sc->sc_dev), "txiintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(&sc->sc_dev), "rxintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(&sc->sc_dev), "hiberr"); 1345 if (!sc->sc_gigabit) { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1347 NULL, device_xname(&sc->sc_dev), "rxpause"); 1348 } else { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1350 NULL, device_xname(&sc->sc_dev), "rxpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1352 NULL, device_xname(&sc->sc_dev), "txpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(&sc->sc_dev), "rxipsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(&sc->sc_dev), "txipsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(&sc->sc_dev), "txudpsum"); 1365 } 1366 #endif /* SIP_EVENT_COUNTERS */ 1367 1368 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1369 aprint_error_dev(self, "couldn't establish power handler\n"); 1370 else 1371 pmf_class_network_register(self, ifp); 1372 } 1373 1374 static inline void 1375 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1376 uint64_t capenable) 1377 { 1378 struct m_tag *mtag; 1379 u_int32_t extsts; 1380 #ifdef DEBUG 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 #endif 1383 /* 1384 * If VLANs are enabled and the packet has a VLAN tag, set 1385 * up the descriptor to encapsulate the packet for us. 1386 * 1387 * This apparently has to be on the last descriptor of 1388 * the packet. 1389 */ 1390 1391 /* 1392 * Byte swapping is tricky. We need to provide the tag 1393 * in a network byte order. On a big-endian machine, 1394 * the byteorder is correct, but we need to swap it 1395 * anyway, because this will be undone by the outside 1396 * htole32(). That's why there must be an 1397 * unconditional swap instead of htons() inside. 1398 */ 1399 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1400 sc->sc_txdescs[lasttx].sipd_extsts |= 1401 htole32(EXTSTS_VPKT | 1402 (bswap16(VLAN_TAG_VALUE(mtag)) & 1403 EXTSTS_VTCI)); 1404 } 1405 1406 /* 1407 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1408 * checksumming, set up the descriptor to do this work 1409 * for us. 1410 * 1411 * This apparently has to be on the first descriptor of 1412 * the packet. 1413 * 1414 * Byte-swap constants so the compiler can optimize. 1415 */ 1416 extsts = 0; 1417 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1418 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1419 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1420 extsts |= htole32(EXTSTS_IPPKT); 1421 } 1422 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1425 extsts |= htole32(EXTSTS_TCPPKT); 1426 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1429 extsts |= htole32(EXTSTS_UDPPKT); 1430 } 1431 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1432 } 1433 1434 /* 1435 * sip_start: [ifnet interface function] 1436 * 1437 * Start packet transmission on the interface. 1438 */ 1439 static void 1440 sipcom_start(struct ifnet *ifp) 1441 { 1442 struct sip_softc *sc = ifp->if_softc; 1443 struct mbuf *m0; 1444 struct mbuf *m; 1445 struct sip_txsoft *txs; 1446 bus_dmamap_t dmamap; 1447 int error, nexttx, lasttx, seg; 1448 int ofree = sc->sc_txfree; 1449 #if 0 1450 int firsttx = sc->sc_txnext; 1451 #endif 1452 1453 /* 1454 * If we've been told to pause, don't transmit any more packets. 1455 */ 1456 if (!sc->sc_gigabit && sc->sc_paused) 1457 ifp->if_flags |= IFF_OACTIVE; 1458 1459 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1460 return; 1461 1462 /* 1463 * Loop through the send queue, setting up transmit descriptors 1464 * until we drain the queue, or use up all available transmit 1465 * descriptors. 1466 */ 1467 for (;;) { 1468 /* Get a work queue entry. */ 1469 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1470 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1471 break; 1472 } 1473 1474 /* 1475 * Grab a packet off the queue. 1476 */ 1477 IFQ_POLL(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 m = NULL; 1481 1482 dmamap = txs->txs_dmamap; 1483 1484 /* 1485 * Load the DMA map. If this fails, the packet either 1486 * didn't fit in the alloted number of segments, or we 1487 * were short on resources. 1488 */ 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1490 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1491 /* In the non-gigabit case, we'll copy and try again. */ 1492 if (error != 0 && !sc->sc_gigabit) { 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) { 1495 printf("%s: unable to allocate Tx mbuf\n", 1496 device_xname(&sc->sc_dev)); 1497 break; 1498 } 1499 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1500 if (m0->m_pkthdr.len > MHLEN) { 1501 MCLGET(m, M_DONTWAIT); 1502 if ((m->m_flags & M_EXT) == 0) { 1503 printf("%s: unable to allocate Tx " 1504 "cluster\n", device_xname(&sc->sc_dev)); 1505 m_freem(m); 1506 break; 1507 } 1508 } 1509 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1510 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1511 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1512 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1513 if (error) { 1514 printf("%s: unable to load Tx buffer, " 1515 "error = %d\n", device_xname(&sc->sc_dev), error); 1516 break; 1517 } 1518 } else if (error == EFBIG) { 1519 /* 1520 * For the too-many-segments case, we simply 1521 * report an error and drop the packet, 1522 * since we can't sanely copy a jumbo packet 1523 * to a single buffer. 1524 */ 1525 printf("%s: Tx packet consumes too many " 1526 "DMA segments, dropping...\n", device_xname(&sc->sc_dev)); 1527 IFQ_DEQUEUE(&ifp->if_snd, m0); 1528 m_freem(m0); 1529 continue; 1530 } else if (error != 0) { 1531 /* 1532 * Short on resources, just stop for now. 1533 */ 1534 break; 1535 } 1536 1537 /* 1538 * Ensure we have enough descriptors free to describe 1539 * the packet. Note, we always reserve one descriptor 1540 * at the end of the ring as a termination point, to 1541 * prevent wrap-around. 1542 */ 1543 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1544 /* 1545 * Not enough free descriptors to transmit this 1546 * packet. We haven't committed anything yet, 1547 * so just unload the DMA map, put the packet 1548 * back on the queue, and punt. Notify the upper 1549 * layer that there are not more slots left. 1550 * 1551 * XXX We could allocate an mbuf and copy, but 1552 * XXX is it worth it? 1553 */ 1554 ifp->if_flags |= IFF_OACTIVE; 1555 bus_dmamap_unload(sc->sc_dmat, dmamap); 1556 if (m != NULL) 1557 m_freem(m); 1558 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1559 break; 1560 } 1561 1562 IFQ_DEQUEUE(&ifp->if_snd, m0); 1563 if (m != NULL) { 1564 m_freem(m0); 1565 m0 = m; 1566 } 1567 1568 /* 1569 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1570 */ 1571 1572 /* Sync the DMA map. */ 1573 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1574 BUS_DMASYNC_PREWRITE); 1575 1576 /* 1577 * Initialize the transmit descriptors. 1578 */ 1579 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1580 seg < dmamap->dm_nsegs; 1581 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1582 /* 1583 * If this is the first descriptor we're 1584 * enqueueing, don't set the OWN bit just 1585 * yet. That could cause a race condition. 1586 * We'll do it below. 1587 */ 1588 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1589 htole32(dmamap->dm_segs[seg].ds_addr); 1590 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1591 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1592 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1593 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1594 lasttx = nexttx; 1595 } 1596 1597 /* Clear the MORE bit on the last segment. */ 1598 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1599 htole32(~CMDSTS_MORE); 1600 1601 /* 1602 * If we're in the interrupt delay window, delay the 1603 * interrupt. 1604 */ 1605 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1606 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1607 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1608 htole32(CMDSTS_INTR); 1609 sc->sc_txwin = 0; 1610 } 1611 1612 if (sc->sc_gigabit) 1613 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1614 1615 /* Sync the descriptors we're using. */ 1616 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1617 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1618 1619 /* 1620 * The entire packet is set up. Give the first descrptor 1621 * to the chip now. 1622 */ 1623 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1624 htole32(CMDSTS_OWN); 1625 sip_cdtxsync(sc, sc->sc_txnext, 1, 1626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1627 1628 /* 1629 * Store a pointer to the packet so we can free it later, 1630 * and remember what txdirty will be once the packet is 1631 * done. 1632 */ 1633 txs->txs_mbuf = m0; 1634 txs->txs_firstdesc = sc->sc_txnext; 1635 txs->txs_lastdesc = lasttx; 1636 1637 /* Advance the tx pointer. */ 1638 sc->sc_txfree -= dmamap->dm_nsegs; 1639 sc->sc_txnext = nexttx; 1640 1641 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1642 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1643 1644 #if NBPFILTER > 0 1645 /* 1646 * Pass the packet to any BPF listeners. 1647 */ 1648 if (ifp->if_bpf) 1649 bpf_mtap(ifp->if_bpf, m0); 1650 #endif /* NBPFILTER > 0 */ 1651 } 1652 1653 if (txs == NULL || sc->sc_txfree == 0) { 1654 /* No more slots left; notify upper layer. */ 1655 ifp->if_flags |= IFF_OACTIVE; 1656 } 1657 1658 if (sc->sc_txfree != ofree) { 1659 /* 1660 * Start the transmit process. Note, the manual says 1661 * that if there are no pending transmissions in the 1662 * chip's internal queue (indicated by TXE being clear), 1663 * then the driver software must set the TXDP to the 1664 * first descriptor to be transmitted. However, if we 1665 * do this, it causes serious performance degredation on 1666 * the DP83820 under load, not setting TXDP doesn't seem 1667 * to adversely affect the SiS 900 or DP83815. 1668 * 1669 * Well, I guess it wouldn't be the first time a manual 1670 * has lied -- and they could be speaking of the NULL- 1671 * terminated descriptor list case, rather than OWN- 1672 * terminated rings. 1673 */ 1674 #if 0 1675 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1676 CR_TXE) == 0) { 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1678 SIP_CDTXADDR(sc, firsttx)); 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1680 } 1681 #else 1682 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1683 #endif 1684 1685 /* Set a watchdog timer in case the chip flakes out. */ 1686 /* Gigabit autonegotiation takes 5 seconds. */ 1687 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1688 } 1689 } 1690 1691 /* 1692 * sip_watchdog: [ifnet interface function] 1693 * 1694 * Watchdog timer handler. 1695 */ 1696 static void 1697 sipcom_watchdog(struct ifnet *ifp) 1698 { 1699 struct sip_softc *sc = ifp->if_softc; 1700 1701 /* 1702 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1703 * If we get a timeout, try and sweep up transmit descriptors. 1704 * If we manage to sweep them all up, ignore the lack of 1705 * interrupt. 1706 */ 1707 sipcom_txintr(sc); 1708 1709 if (sc->sc_txfree != sc->sc_ntxdesc) { 1710 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1711 ifp->if_oerrors++; 1712 1713 /* Reset the interface. */ 1714 (void) sipcom_init(ifp); 1715 } else if (ifp->if_flags & IFF_DEBUG) 1716 printf("%s: recovered from device timeout\n", 1717 device_xname(&sc->sc_dev)); 1718 1719 /* Try to get more packets going. */ 1720 sipcom_start(ifp); 1721 } 1722 1723 /* 1724 * sip_ioctl: [ifnet interface function] 1725 * 1726 * Handle control requests from the operator. 1727 */ 1728 static int 1729 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1730 { 1731 struct sip_softc *sc = ifp->if_softc; 1732 struct ifreq *ifr = (struct ifreq *)data; 1733 int s, error; 1734 1735 s = splnet(); 1736 1737 switch (cmd) { 1738 case SIOCSIFMEDIA: 1739 /* Flow control requires full-duplex mode. */ 1740 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1741 (ifr->ifr_media & IFM_FDX) == 0) 1742 ifr->ifr_media &= ~IFM_ETH_FMASK; 1743 1744 /* XXX */ 1745 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1746 ifr->ifr_media &= ~IFM_ETH_FMASK; 1747 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1748 if (sc->sc_gigabit && 1749 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1750 /* We can do both TXPAUSE and RXPAUSE. */ 1751 ifr->ifr_media |= 1752 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1753 } else if (ifr->ifr_media & IFM_FLOW) { 1754 /* 1755 * Both TXPAUSE and RXPAUSE must be set. 1756 * (SiS900 and DP83815 don't have PAUSE_ASYM 1757 * feature.) 1758 * 1759 * XXX Can SiS900 and DP83815 send PAUSE? 1760 */ 1761 ifr->ifr_media |= 1762 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1763 } 1764 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1765 } 1766 goto ethioctl; 1767 case SIOCSIFFLAGS: 1768 /* If the interface is up and running, only modify the receive 1769 * filter when setting promiscuous or debug mode. Otherwise 1770 * fall through to ether_ioctl, which will reset the chip. 1771 */ 1772 1773 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1774 == (sc)->sc_ethercom.ec_capenable) \ 1775 && ((sc)->sc_prev.is_vlan == \ 1776 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1777 1778 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1779 1780 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1781 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1782 == (IFF_UP|IFF_RUNNING)) 1783 && ((ifp->if_flags & (~RESETIGN)) 1784 == (sc->sc_if_flags & (~RESETIGN))) 1785 && COMPARE_EC(sc) && COMPARE_IC(sc, ifp)) { 1786 /* Set up the receive filter. */ 1787 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1788 error = 0; 1789 break; 1790 #undef RESETIGN 1791 } 1792 /* FALLTHROUGH */ 1793 ethioctl: 1794 default: 1795 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1796 break; 1797 1798 error = 0; 1799 1800 if (cmd == SIOCSIFCAP) 1801 error = (*ifp->if_init)(ifp); 1802 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1803 ; 1804 else if (ifp->if_flags & IFF_RUNNING) { 1805 /* 1806 * Multicast list has changed; set the hardware filter 1807 * accordingly. 1808 */ 1809 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1810 } 1811 break; 1812 } 1813 1814 /* Try to get more packets going. */ 1815 sipcom_start(ifp); 1816 1817 sc->sc_if_flags = ifp->if_flags; 1818 splx(s); 1819 return (error); 1820 } 1821 1822 /* 1823 * sip_intr: 1824 * 1825 * Interrupt service routine. 1826 */ 1827 static int 1828 sipcom_intr(void *arg) 1829 { 1830 struct sip_softc *sc = arg; 1831 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1832 u_int32_t isr; 1833 int handled = 0; 1834 1835 /* Disable interrupts. */ 1836 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1837 1838 for (;;) { 1839 /* Reading clears interrupt. */ 1840 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1841 if ((isr & sc->sc_imr) == 0) 1842 break; 1843 1844 #if NRND > 0 1845 if (RND_ENABLED(&sc->rnd_source)) 1846 rnd_add_uint32(&sc->rnd_source, isr); 1847 #endif 1848 1849 handled = 1; 1850 1851 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1852 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1853 1854 /* Grab any new packets. */ 1855 (*sc->sc_rxintr)(sc); 1856 1857 if (isr & ISR_RXORN) { 1858 printf("%s: receive FIFO overrun\n", 1859 device_xname(&sc->sc_dev)); 1860 1861 /* XXX adjust rx_drain_thresh? */ 1862 } 1863 1864 if (isr & ISR_RXIDLE) { 1865 printf("%s: receive ring overrun\n", 1866 device_xname(&sc->sc_dev)); 1867 1868 /* Get the receive process going again. */ 1869 bus_space_write_4(sc->sc_st, sc->sc_sh, 1870 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1871 bus_space_write_4(sc->sc_st, sc->sc_sh, 1872 SIP_CR, CR_RXE); 1873 } 1874 } 1875 1876 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1877 #ifdef SIP_EVENT_COUNTERS 1878 if (isr & ISR_TXDESC) 1879 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1880 else if (isr & ISR_TXIDLE) 1881 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1882 #endif 1883 1884 /* Sweep up transmit descriptors. */ 1885 sipcom_txintr(sc); 1886 1887 if (isr & ISR_TXURN) { 1888 u_int32_t thresh; 1889 int txfifo_size = (sc->sc_gigabit) 1890 ? DP83820_SIP_TXFIFO_SIZE 1891 : OTHER_SIP_TXFIFO_SIZE; 1892 1893 printf("%s: transmit FIFO underrun", 1894 device_xname(&sc->sc_dev)); 1895 thresh = sc->sc_tx_drain_thresh + 1; 1896 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1897 && (thresh * 32) <= (txfifo_size - 1898 (sc->sc_tx_fill_thresh * 32))) { 1899 printf("; increasing Tx drain " 1900 "threshold to %u bytes\n", 1901 thresh * 32); 1902 sc->sc_tx_drain_thresh = thresh; 1903 (void) sipcom_init(ifp); 1904 } else { 1905 (void) sipcom_init(ifp); 1906 printf("\n"); 1907 } 1908 } 1909 } 1910 1911 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1912 if (isr & ISR_PAUSE_ST) { 1913 sc->sc_paused = 1; 1914 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1915 ifp->if_flags |= IFF_OACTIVE; 1916 } 1917 if (isr & ISR_PAUSE_END) { 1918 sc->sc_paused = 0; 1919 ifp->if_flags &= ~IFF_OACTIVE; 1920 } 1921 } 1922 1923 if (isr & ISR_HIBERR) { 1924 int want_init = 0; 1925 1926 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1927 1928 #define PRINTERR(bit, str) \ 1929 do { \ 1930 if ((isr & (bit)) != 0) { \ 1931 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1932 printf("%s: %s\n", \ 1933 device_xname(&sc->sc_dev), str); \ 1934 want_init = 1; \ 1935 } \ 1936 } while (/*CONSTCOND*/0) 1937 1938 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1939 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1940 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1941 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1942 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1943 /* 1944 * Ignore: 1945 * Tx reset complete 1946 * Rx reset complete 1947 */ 1948 if (want_init) 1949 (void) sipcom_init(ifp); 1950 #undef PRINTERR 1951 } 1952 } 1953 1954 /* Re-enable interrupts. */ 1955 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1956 1957 /* Try to get more packets going. */ 1958 sipcom_start(ifp); 1959 1960 return (handled); 1961 } 1962 1963 /* 1964 * sip_txintr: 1965 * 1966 * Helper; handle transmit interrupts. 1967 */ 1968 static void 1969 sipcom_txintr(struct sip_softc *sc) 1970 { 1971 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1972 struct sip_txsoft *txs; 1973 u_int32_t cmdsts; 1974 1975 if (sc->sc_paused == 0) 1976 ifp->if_flags &= ~IFF_OACTIVE; 1977 1978 /* 1979 * Go through our Tx list and free mbufs for those 1980 * frames which have been transmitted. 1981 */ 1982 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1983 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1984 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1985 1986 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1987 if (cmdsts & CMDSTS_OWN) 1988 break; 1989 1990 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1991 1992 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1993 1994 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1995 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1996 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1997 m_freem(txs->txs_mbuf); 1998 txs->txs_mbuf = NULL; 1999 2000 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2001 2002 /* 2003 * Check for errors and collisions. 2004 */ 2005 if (cmdsts & 2006 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2007 ifp->if_oerrors++; 2008 if (cmdsts & CMDSTS_Tx_EC) 2009 ifp->if_collisions += 16; 2010 if (ifp->if_flags & IFF_DEBUG) { 2011 if (cmdsts & CMDSTS_Tx_ED) 2012 printf("%s: excessive deferral\n", 2013 device_xname(&sc->sc_dev)); 2014 if (cmdsts & CMDSTS_Tx_EC) 2015 printf("%s: excessive collisions\n", 2016 device_xname(&sc->sc_dev)); 2017 } 2018 } else { 2019 /* Packet was transmitted successfully. */ 2020 ifp->if_opackets++; 2021 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2022 } 2023 } 2024 2025 /* 2026 * If there are no more pending transmissions, cancel the watchdog 2027 * timer. 2028 */ 2029 if (txs == NULL) { 2030 ifp->if_timer = 0; 2031 sc->sc_txwin = 0; 2032 } 2033 } 2034 2035 /* 2036 * gsip_rxintr: 2037 * 2038 * Helper; handle receive interrupts on gigabit parts. 2039 */ 2040 static void 2041 gsip_rxintr(struct sip_softc *sc) 2042 { 2043 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2044 struct sip_rxsoft *rxs; 2045 struct mbuf *m; 2046 u_int32_t cmdsts, extsts; 2047 int i, len; 2048 2049 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2050 rxs = &sc->sc_rxsoft[i]; 2051 2052 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2053 2054 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2055 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2056 len = CMDSTS_SIZE(sc, cmdsts); 2057 2058 /* 2059 * NOTE: OWN is set if owned by _consumer_. We're the 2060 * consumer of the receive ring, so if the bit is clear, 2061 * we have processed all of the packets. 2062 */ 2063 if ((cmdsts & CMDSTS_OWN) == 0) { 2064 /* 2065 * We have processed all of the receive buffers. 2066 */ 2067 break; 2068 } 2069 2070 if (__predict_false(sc->sc_rxdiscard)) { 2071 sip_init_rxdesc(sc, i); 2072 if ((cmdsts & CMDSTS_MORE) == 0) { 2073 /* Reset our state. */ 2074 sc->sc_rxdiscard = 0; 2075 } 2076 continue; 2077 } 2078 2079 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2080 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2081 2082 m = rxs->rxs_mbuf; 2083 2084 /* 2085 * Add a new receive buffer to the ring. 2086 */ 2087 if (sipcom_add_rxbuf(sc, i) != 0) { 2088 /* 2089 * Failed, throw away what we've done so 2090 * far, and discard the rest of the packet. 2091 */ 2092 ifp->if_ierrors++; 2093 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2094 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2095 sip_init_rxdesc(sc, i); 2096 if (cmdsts & CMDSTS_MORE) 2097 sc->sc_rxdiscard = 1; 2098 if (sc->sc_rxhead != NULL) 2099 m_freem(sc->sc_rxhead); 2100 sip_rxchain_reset(sc); 2101 continue; 2102 } 2103 2104 sip_rxchain_link(sc, m); 2105 2106 m->m_len = len; 2107 2108 /* 2109 * If this is not the end of the packet, keep 2110 * looking. 2111 */ 2112 if (cmdsts & CMDSTS_MORE) { 2113 sc->sc_rxlen += len; 2114 continue; 2115 } 2116 2117 /* 2118 * Okay, we have the entire packet now. The chip includes 2119 * the FCS, so we need to trim it. 2120 */ 2121 m->m_len -= ETHER_CRC_LEN; 2122 2123 *sc->sc_rxtailp = NULL; 2124 len = m->m_len + sc->sc_rxlen; 2125 m = sc->sc_rxhead; 2126 2127 sip_rxchain_reset(sc); 2128 2129 /* 2130 * If an error occurred, update stats and drop the packet. 2131 */ 2132 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2133 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2134 ifp->if_ierrors++; 2135 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2136 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2137 /* Receive overrun handled elsewhere. */ 2138 printf("%s: receive descriptor error\n", 2139 device_xname(&sc->sc_dev)); 2140 } 2141 #define PRINTERR(bit, str) \ 2142 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2143 (cmdsts & (bit)) != 0) \ 2144 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2145 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2146 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2147 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2148 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2149 #undef PRINTERR 2150 m_freem(m); 2151 continue; 2152 } 2153 2154 /* 2155 * If the packet is small enough to fit in a 2156 * single header mbuf, allocate one and copy 2157 * the data into it. This greatly reduces 2158 * memory consumption when we receive lots 2159 * of small packets. 2160 */ 2161 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2162 struct mbuf *nm; 2163 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2164 if (nm == NULL) { 2165 ifp->if_ierrors++; 2166 m_freem(m); 2167 continue; 2168 } 2169 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2170 nm->m_data += 2; 2171 nm->m_pkthdr.len = nm->m_len = len; 2172 m_copydata(m, 0, len, mtod(nm, void *)); 2173 m_freem(m); 2174 m = nm; 2175 } 2176 #ifndef __NO_STRICT_ALIGNMENT 2177 else { 2178 /* 2179 * The DP83820's receive buffers must be 4-byte 2180 * aligned. But this means that the data after 2181 * the Ethernet header is misaligned. To compensate, 2182 * we have artificially shortened the buffer size 2183 * in the descriptor, and we do an overlapping copy 2184 * of the data two bytes further in (in the first 2185 * buffer of the chain only). 2186 */ 2187 memmove(mtod(m, char *) + 2, mtod(m, void *), 2188 m->m_len); 2189 m->m_data += 2; 2190 } 2191 #endif /* ! __NO_STRICT_ALIGNMENT */ 2192 2193 /* 2194 * If VLANs are enabled, VLAN packets have been unwrapped 2195 * for us. Associate the tag with the packet. 2196 */ 2197 2198 /* 2199 * Again, byte swapping is tricky. Hardware provided 2200 * the tag in the network byte order, but extsts was 2201 * passed through le32toh() in the meantime. On a 2202 * big-endian machine, we need to swap it again. On a 2203 * little-endian machine, we need to convert from the 2204 * network to host byte order. This means that we must 2205 * swap it in any case, so unconditional swap instead 2206 * of htons() is used. 2207 */ 2208 if ((extsts & EXTSTS_VPKT) != 0) { 2209 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2210 continue); 2211 } 2212 2213 /* 2214 * Set the incoming checksum information for the 2215 * packet. 2216 */ 2217 if ((extsts & EXTSTS_IPPKT) != 0) { 2218 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2219 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2220 if (extsts & EXTSTS_Rx_IPERR) 2221 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2222 if (extsts & EXTSTS_TCPPKT) { 2223 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2224 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2225 if (extsts & EXTSTS_Rx_TCPERR) 2226 m->m_pkthdr.csum_flags |= 2227 M_CSUM_TCP_UDP_BAD; 2228 } else if (extsts & EXTSTS_UDPPKT) { 2229 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2230 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2231 if (extsts & EXTSTS_Rx_UDPERR) 2232 m->m_pkthdr.csum_flags |= 2233 M_CSUM_TCP_UDP_BAD; 2234 } 2235 } 2236 2237 ifp->if_ipackets++; 2238 m->m_pkthdr.rcvif = ifp; 2239 m->m_pkthdr.len = len; 2240 2241 #if NBPFILTER > 0 2242 /* 2243 * Pass this up to any BPF listeners, but only 2244 * pass if up the stack if it's for us. 2245 */ 2246 if (ifp->if_bpf) 2247 bpf_mtap(ifp->if_bpf, m); 2248 #endif /* NBPFILTER > 0 */ 2249 2250 /* Pass it on. */ 2251 (*ifp->if_input)(ifp, m); 2252 } 2253 2254 /* Update the receive pointer. */ 2255 sc->sc_rxptr = i; 2256 } 2257 2258 /* 2259 * sip_rxintr: 2260 * 2261 * Helper; handle receive interrupts on 10/100 parts. 2262 */ 2263 static void 2264 sip_rxintr(struct sip_softc *sc) 2265 { 2266 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2267 struct sip_rxsoft *rxs; 2268 struct mbuf *m; 2269 u_int32_t cmdsts; 2270 int i, len; 2271 2272 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2273 rxs = &sc->sc_rxsoft[i]; 2274 2275 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2276 2277 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2278 2279 /* 2280 * NOTE: OWN is set if owned by _consumer_. We're the 2281 * consumer of the receive ring, so if the bit is clear, 2282 * we have processed all of the packets. 2283 */ 2284 if ((cmdsts & CMDSTS_OWN) == 0) { 2285 /* 2286 * We have processed all of the receive buffers. 2287 */ 2288 break; 2289 } 2290 2291 /* 2292 * If any collisions were seen on the wire, count one. 2293 */ 2294 if (cmdsts & CMDSTS_Rx_COL) 2295 ifp->if_collisions++; 2296 2297 /* 2298 * If an error occurred, update stats, clear the status 2299 * word, and leave the packet buffer in place. It will 2300 * simply be reused the next time the ring comes around. 2301 */ 2302 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2303 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2304 ifp->if_ierrors++; 2305 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2306 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2307 /* Receive overrun handled elsewhere. */ 2308 printf("%s: receive descriptor error\n", 2309 device_xname(&sc->sc_dev)); 2310 } 2311 #define PRINTERR(bit, str) \ 2312 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2313 (cmdsts & (bit)) != 0) \ 2314 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2315 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2316 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2317 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2318 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2319 #undef PRINTERR 2320 sip_init_rxdesc(sc, i); 2321 continue; 2322 } 2323 2324 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2325 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2326 2327 /* 2328 * No errors; receive the packet. Note, the SiS 900 2329 * includes the CRC with every packet. 2330 */ 2331 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2332 2333 #ifdef __NO_STRICT_ALIGNMENT 2334 /* 2335 * If the packet is small enough to fit in a 2336 * single header mbuf, allocate one and copy 2337 * the data into it. This greatly reduces 2338 * memory consumption when we receive lots 2339 * of small packets. 2340 * 2341 * Otherwise, we add a new buffer to the receive 2342 * chain. If this fails, we drop the packet and 2343 * recycle the old buffer. 2344 */ 2345 if (sip_copy_small != 0 && len <= MHLEN) { 2346 MGETHDR(m, M_DONTWAIT, MT_DATA); 2347 if (m == NULL) 2348 goto dropit; 2349 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2350 memcpy(mtod(m, void *), 2351 mtod(rxs->rxs_mbuf, void *), len); 2352 sip_init_rxdesc(sc, i); 2353 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2354 rxs->rxs_dmamap->dm_mapsize, 2355 BUS_DMASYNC_PREREAD); 2356 } else { 2357 m = rxs->rxs_mbuf; 2358 if (sipcom_add_rxbuf(sc, i) != 0) { 2359 dropit: 2360 ifp->if_ierrors++; 2361 sip_init_rxdesc(sc, i); 2362 bus_dmamap_sync(sc->sc_dmat, 2363 rxs->rxs_dmamap, 0, 2364 rxs->rxs_dmamap->dm_mapsize, 2365 BUS_DMASYNC_PREREAD); 2366 continue; 2367 } 2368 } 2369 #else 2370 /* 2371 * The SiS 900's receive buffers must be 4-byte aligned. 2372 * But this means that the data after the Ethernet header 2373 * is misaligned. We must allocate a new buffer and 2374 * copy the data, shifted forward 2 bytes. 2375 */ 2376 MGETHDR(m, M_DONTWAIT, MT_DATA); 2377 if (m == NULL) { 2378 dropit: 2379 ifp->if_ierrors++; 2380 sip_init_rxdesc(sc, i); 2381 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2382 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2383 continue; 2384 } 2385 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2386 if (len > (MHLEN - 2)) { 2387 MCLGET(m, M_DONTWAIT); 2388 if ((m->m_flags & M_EXT) == 0) { 2389 m_freem(m); 2390 goto dropit; 2391 } 2392 } 2393 m->m_data += 2; 2394 2395 /* 2396 * Note that we use clusters for incoming frames, so the 2397 * buffer is virtually contiguous. 2398 */ 2399 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2400 2401 /* Allow the receive descriptor to continue using its mbuf. */ 2402 sip_init_rxdesc(sc, i); 2403 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2404 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2405 #endif /* __NO_STRICT_ALIGNMENT */ 2406 2407 ifp->if_ipackets++; 2408 m->m_pkthdr.rcvif = ifp; 2409 m->m_pkthdr.len = m->m_len = len; 2410 2411 #if NBPFILTER > 0 2412 /* 2413 * Pass this up to any BPF listeners, but only 2414 * pass if up the stack if it's for us. 2415 */ 2416 if (ifp->if_bpf) 2417 bpf_mtap(ifp->if_bpf, m); 2418 #endif /* NBPFILTER > 0 */ 2419 2420 /* Pass it on. */ 2421 (*ifp->if_input)(ifp, m); 2422 } 2423 2424 /* Update the receive pointer. */ 2425 sc->sc_rxptr = i; 2426 } 2427 2428 /* 2429 * sip_tick: 2430 * 2431 * One second timer, used to tick the MII. 2432 */ 2433 static void 2434 sipcom_tick(void *arg) 2435 { 2436 struct sip_softc *sc = arg; 2437 int s; 2438 2439 s = splnet(); 2440 #ifdef SIP_EVENT_COUNTERS 2441 if (sc->sc_gigabit) { 2442 /* Read PAUSE related counts from MIB registers. */ 2443 sc->sc_ev_rxpause.ev_count += 2444 bus_space_read_4(sc->sc_st, sc->sc_sh, 2445 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2446 sc->sc_ev_txpause.ev_count += 2447 bus_space_read_4(sc->sc_st, sc->sc_sh, 2448 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2449 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2450 } 2451 #endif /* SIP_EVENT_COUNTERS */ 2452 mii_tick(&sc->sc_mii); 2453 splx(s); 2454 2455 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2456 } 2457 2458 /* 2459 * sip_reset: 2460 * 2461 * Perform a soft reset on the SiS 900. 2462 */ 2463 static bool 2464 sipcom_reset(struct sip_softc *sc) 2465 { 2466 bus_space_tag_t st = sc->sc_st; 2467 bus_space_handle_t sh = sc->sc_sh; 2468 int i; 2469 2470 bus_space_write_4(st, sh, SIP_IER, 0); 2471 bus_space_write_4(st, sh, SIP_IMR, 0); 2472 bus_space_write_4(st, sh, SIP_RFCR, 0); 2473 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2474 2475 for (i = 0; i < SIP_TIMEOUT; i++) { 2476 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2477 break; 2478 delay(2); 2479 } 2480 2481 if (i == SIP_TIMEOUT) { 2482 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 2483 return false; 2484 } 2485 2486 delay(1000); 2487 2488 if (sc->sc_gigabit) { 2489 /* 2490 * Set the general purpose I/O bits. Do it here in case we 2491 * need to have GPIO set up to talk to the media interface. 2492 */ 2493 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2494 delay(1000); 2495 } 2496 return true; 2497 } 2498 2499 static void 2500 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2501 { 2502 u_int32_t reg; 2503 bus_space_tag_t st = sc->sc_st; 2504 bus_space_handle_t sh = sc->sc_sh; 2505 /* 2506 * Initialize the VLAN/IP receive control register. 2507 * We enable checksum computation on all incoming 2508 * packets, and do not reject packets w/ bad checksums. 2509 */ 2510 reg = 0; 2511 if (capenable & 2512 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2513 reg |= VRCR_IPEN; 2514 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2515 reg |= VRCR_VTDEN|VRCR_VTREN; 2516 bus_space_write_4(st, sh, SIP_VRCR, reg); 2517 2518 /* 2519 * Initialize the VLAN/IP transmit control register. 2520 * We enable outgoing checksum computation on a 2521 * per-packet basis. 2522 */ 2523 reg = 0; 2524 if (capenable & 2525 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2526 reg |= VTCR_PPCHK; 2527 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2528 reg |= VTCR_VPPTI; 2529 bus_space_write_4(st, sh, SIP_VTCR, reg); 2530 2531 /* 2532 * If we're using VLANs, initialize the VLAN data register. 2533 * To understand why we bswap the VLAN Ethertype, see section 2534 * 4.2.36 of the DP83820 manual. 2535 */ 2536 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2537 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2538 } 2539 2540 /* 2541 * sip_init: [ ifnet interface function ] 2542 * 2543 * Initialize the interface. Must be called at splnet(). 2544 */ 2545 static int 2546 sipcom_init(struct ifnet *ifp) 2547 { 2548 struct sip_softc *sc = ifp->if_softc; 2549 bus_space_tag_t st = sc->sc_st; 2550 bus_space_handle_t sh = sc->sc_sh; 2551 struct sip_txsoft *txs; 2552 struct sip_rxsoft *rxs; 2553 struct sip_desc *sipd; 2554 int i, error = 0; 2555 2556 if (device_is_active(&sc->sc_dev)) { 2557 /* 2558 * Cancel any pending I/O. 2559 */ 2560 sipcom_stop(ifp, 0); 2561 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2562 return 0; 2563 2564 /* 2565 * Reset the chip to a known state. 2566 */ 2567 if (!sipcom_reset(sc)) 2568 return EBUSY; 2569 2570 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2571 /* 2572 * DP83815 manual, page 78: 2573 * 4.4 Recommended Registers Configuration 2574 * For optimum performance of the DP83815, version noted 2575 * as DP83815CVNG (SRR = 203h), the listed register 2576 * modifications must be followed in sequence... 2577 * 2578 * It's not clear if this should be 302h or 203h because that 2579 * chip name is listed as SRR 302h in the description of the 2580 * SRR register. However, my revision 302h DP83815 on the 2581 * Netgear FA311 purchased in 02/2001 needs these settings 2582 * to avoid tons of errors in AcceptPerfectMatch (non- 2583 * IFF_PROMISC) mode. I do not know if other revisions need 2584 * this set or not. [briggs -- 09 March 2001] 2585 * 2586 * Note that only the low-order 12 bits of 0xe4 are documented 2587 * and that this sets reserved bits in that register. 2588 */ 2589 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2590 2591 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2592 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2593 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2594 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2595 2596 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2597 } 2598 2599 /* 2600 * Initialize the transmit descriptor ring. 2601 */ 2602 for (i = 0; i < sc->sc_ntxdesc; i++) { 2603 sipd = &sc->sc_txdescs[i]; 2604 memset(sipd, 0, sizeof(struct sip_desc)); 2605 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2606 } 2607 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2608 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2609 sc->sc_txfree = sc->sc_ntxdesc; 2610 sc->sc_txnext = 0; 2611 sc->sc_txwin = 0; 2612 2613 /* 2614 * Initialize the transmit job descriptors. 2615 */ 2616 SIMPLEQ_INIT(&sc->sc_txfreeq); 2617 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2618 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2619 txs = &sc->sc_txsoft[i]; 2620 txs->txs_mbuf = NULL; 2621 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2622 } 2623 2624 /* 2625 * Initialize the receive descriptor and receive job 2626 * descriptor rings. 2627 */ 2628 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2629 rxs = &sc->sc_rxsoft[i]; 2630 if (rxs->rxs_mbuf == NULL) { 2631 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2632 printf("%s: unable to allocate or map rx " 2633 "buffer %d, error = %d\n", 2634 device_xname(&sc->sc_dev), i, error); 2635 /* 2636 * XXX Should attempt to run with fewer receive 2637 * XXX buffers instead of just failing. 2638 */ 2639 sipcom_rxdrain(sc); 2640 goto out; 2641 } 2642 } else 2643 sip_init_rxdesc(sc, i); 2644 } 2645 sc->sc_rxptr = 0; 2646 sc->sc_rxdiscard = 0; 2647 sip_rxchain_reset(sc); 2648 2649 /* 2650 * Set the configuration register; it's already initialized 2651 * in sip_attach(). 2652 */ 2653 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2654 2655 /* 2656 * Initialize the prototype TXCFG register. 2657 */ 2658 if (sc->sc_gigabit) { 2659 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2660 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2661 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2662 SIP_SIS900_REV(sc, SIS_REV_960) || 2663 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2664 (sc->sc_cfg & CFG_EDBMASTEN)) { 2665 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2666 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2667 } else { 2668 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2669 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2670 } 2671 2672 sc->sc_txcfg |= TXCFG_ATP | 2673 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2674 sc->sc_tx_drain_thresh; 2675 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2676 2677 /* 2678 * Initialize the receive drain threshold if we have never 2679 * done so. 2680 */ 2681 if (sc->sc_rx_drain_thresh == 0) { 2682 /* 2683 * XXX This value should be tuned. This is set to the 2684 * maximum of 248 bytes, and we may be able to improve 2685 * performance by decreasing it (although we should never 2686 * set this value lower than 2; 14 bytes are required to 2687 * filter the packet). 2688 */ 2689 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2690 } 2691 2692 /* 2693 * Initialize the prototype RXCFG register. 2694 */ 2695 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2696 /* 2697 * Accept long packets (including FCS) so we can handle 2698 * 802.1q-tagged frames and jumbo frames properly. 2699 */ 2700 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2701 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2702 sc->sc_rxcfg |= RXCFG_ALP; 2703 2704 /* 2705 * Checksum offloading is disabled if the user selects an MTU 2706 * larger than 8109. (FreeBSD says 8152, but there is emperical 2707 * evidence that >8109 does not work on some boards, such as the 2708 * Planex GN-1000TE). 2709 */ 2710 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2711 (ifp->if_capenable & 2712 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2713 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2714 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2715 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2716 "disabled.\n", device_xname(&sc->sc_dev)); 2717 ifp->if_capenable &= 2718 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2719 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2720 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2721 ifp->if_csum_flags_tx = 0; 2722 ifp->if_csum_flags_rx = 0; 2723 } 2724 2725 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2726 2727 if (sc->sc_gigabit) 2728 sipcom_dp83820_init(sc, ifp->if_capenable); 2729 2730 /* 2731 * Give the transmit and receive rings to the chip. 2732 */ 2733 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2734 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2735 2736 /* 2737 * Initialize the interrupt mask. 2738 */ 2739 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2740 sc->sc_bits.b_isr_sserr | 2741 sc->sc_bits.b_isr_rmabt | 2742 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2743 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2744 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2745 2746 /* Set up the receive filter. */ 2747 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2748 2749 /* 2750 * Tune sc_rx_flow_thresh. 2751 * XXX "More than 8KB" is too short for jumbo frames. 2752 * XXX TODO: Threshold value should be user-settable. 2753 */ 2754 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2755 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2756 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2757 2758 /* 2759 * Set the current media. Do this after initializing the prototype 2760 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2761 * control. 2762 */ 2763 if ((error = ether_mediachange(ifp)) != 0) 2764 goto out; 2765 2766 /* 2767 * Set the interrupt hold-off timer to 100us. 2768 */ 2769 if (sc->sc_gigabit) 2770 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2771 2772 /* 2773 * Enable interrupts. 2774 */ 2775 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2776 2777 /* 2778 * Start the transmit and receive processes. 2779 */ 2780 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2781 2782 /* 2783 * Start the one second MII clock. 2784 */ 2785 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2786 2787 /* 2788 * ...all done! 2789 */ 2790 ifp->if_flags |= IFF_RUNNING; 2791 ifp->if_flags &= ~IFF_OACTIVE; 2792 sc->sc_if_flags = ifp->if_flags; 2793 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2794 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2795 sc->sc_prev.if_capenable = ifp->if_capenable; 2796 2797 out: 2798 if (error) 2799 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2800 return (error); 2801 } 2802 2803 /* 2804 * sip_drain: 2805 * 2806 * Drain the receive queue. 2807 */ 2808 static void 2809 sipcom_rxdrain(struct sip_softc *sc) 2810 { 2811 struct sip_rxsoft *rxs; 2812 int i; 2813 2814 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2815 rxs = &sc->sc_rxsoft[i]; 2816 if (rxs->rxs_mbuf != NULL) { 2817 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2818 m_freem(rxs->rxs_mbuf); 2819 rxs->rxs_mbuf = NULL; 2820 } 2821 } 2822 } 2823 2824 /* 2825 * sip_stop: [ ifnet interface function ] 2826 * 2827 * Stop transmission on the interface. 2828 */ 2829 static void 2830 sipcom_stop(struct ifnet *ifp, int disable) 2831 { 2832 struct sip_softc *sc = ifp->if_softc; 2833 bus_space_tag_t st = sc->sc_st; 2834 bus_space_handle_t sh = sc->sc_sh; 2835 struct sip_txsoft *txs; 2836 u_int32_t cmdsts = 0; /* DEBUG */ 2837 2838 /* 2839 * Stop the one second clock. 2840 */ 2841 callout_stop(&sc->sc_tick_ch); 2842 2843 /* Down the MII. */ 2844 mii_down(&sc->sc_mii); 2845 2846 /* 2847 * Disable interrupts. 2848 */ 2849 bus_space_write_4(st, sh, SIP_IER, 0); 2850 2851 /* 2852 * Stop receiver and transmitter. 2853 */ 2854 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2855 2856 /* 2857 * Release any queued transmit buffers. 2858 */ 2859 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2860 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2861 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2862 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2863 CMDSTS_INTR) == 0) 2864 printf("%s: sip_stop: last descriptor does not " 2865 "have INTR bit set\n", device_xname(&sc->sc_dev)); 2866 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2867 #ifdef DIAGNOSTIC 2868 if (txs->txs_mbuf == NULL) { 2869 printf("%s: dirty txsoft with no mbuf chain\n", 2870 device_xname(&sc->sc_dev)); 2871 panic("sip_stop"); 2872 } 2873 #endif 2874 cmdsts |= /* DEBUG */ 2875 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2876 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2877 m_freem(txs->txs_mbuf); 2878 txs->txs_mbuf = NULL; 2879 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2880 } 2881 2882 /* 2883 * Mark the interface down and cancel the watchdog timer. 2884 */ 2885 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2886 ifp->if_timer = 0; 2887 2888 if (disable) 2889 pmf_device_suspend_self(&sc->sc_dev); 2890 2891 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2892 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2893 printf("%s: sip_stop: no INTR bits set in dirty tx " 2894 "descriptors\n", device_xname(&sc->sc_dev)); 2895 } 2896 2897 /* 2898 * sip_read_eeprom: 2899 * 2900 * Read data from the serial EEPROM. 2901 */ 2902 static void 2903 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2904 u_int16_t *data) 2905 { 2906 bus_space_tag_t st = sc->sc_st; 2907 bus_space_handle_t sh = sc->sc_sh; 2908 u_int16_t reg; 2909 int i, x; 2910 2911 for (i = 0; i < wordcnt; i++) { 2912 /* Send CHIP SELECT. */ 2913 reg = EROMAR_EECS; 2914 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2915 2916 /* Shift in the READ opcode. */ 2917 for (x = 3; x > 0; x--) { 2918 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2919 reg |= EROMAR_EEDI; 2920 else 2921 reg &= ~EROMAR_EEDI; 2922 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2923 bus_space_write_4(st, sh, SIP_EROMAR, 2924 reg | EROMAR_EESK); 2925 delay(4); 2926 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2927 delay(4); 2928 } 2929 2930 /* Shift in address. */ 2931 for (x = 6; x > 0; x--) { 2932 if ((word + i) & (1 << (x - 1))) 2933 reg |= EROMAR_EEDI; 2934 else 2935 reg &= ~EROMAR_EEDI; 2936 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2937 bus_space_write_4(st, sh, SIP_EROMAR, 2938 reg | EROMAR_EESK); 2939 delay(4); 2940 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2941 delay(4); 2942 } 2943 2944 /* Shift out data. */ 2945 reg = EROMAR_EECS; 2946 data[i] = 0; 2947 for (x = 16; x > 0; x--) { 2948 bus_space_write_4(st, sh, SIP_EROMAR, 2949 reg | EROMAR_EESK); 2950 delay(4); 2951 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2952 data[i] |= (1 << (x - 1)); 2953 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2954 delay(4); 2955 } 2956 2957 /* Clear CHIP SELECT. */ 2958 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2959 delay(4); 2960 } 2961 } 2962 2963 /* 2964 * sipcom_add_rxbuf: 2965 * 2966 * Add a receive buffer to the indicated descriptor. 2967 */ 2968 static int 2969 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2970 { 2971 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2972 struct mbuf *m; 2973 int error; 2974 2975 MGETHDR(m, M_DONTWAIT, MT_DATA); 2976 if (m == NULL) 2977 return (ENOBUFS); 2978 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2979 2980 MCLGET(m, M_DONTWAIT); 2981 if ((m->m_flags & M_EXT) == 0) { 2982 m_freem(m); 2983 return (ENOBUFS); 2984 } 2985 2986 /* XXX I don't believe this is necessary. --dyoung */ 2987 if (sc->sc_gigabit) 2988 m->m_len = sc->sc_parm->p_rxbuf_len; 2989 2990 if (rxs->rxs_mbuf != NULL) 2991 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2992 2993 rxs->rxs_mbuf = m; 2994 2995 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2996 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2997 BUS_DMA_READ|BUS_DMA_NOWAIT); 2998 if (error) { 2999 printf("%s: can't load rx DMA map %d, error = %d\n", 3000 device_xname(&sc->sc_dev), idx, error); 3001 panic("%s", __func__); /* XXX */ 3002 } 3003 3004 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3005 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3006 3007 sip_init_rxdesc(sc, idx); 3008 3009 return (0); 3010 } 3011 3012 /* 3013 * sip_sis900_set_filter: 3014 * 3015 * Set up the receive filter. 3016 */ 3017 static void 3018 sipcom_sis900_set_filter(struct sip_softc *sc) 3019 { 3020 bus_space_tag_t st = sc->sc_st; 3021 bus_space_handle_t sh = sc->sc_sh; 3022 struct ethercom *ec = &sc->sc_ethercom; 3023 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3024 struct ether_multi *enm; 3025 const u_int8_t *cp; 3026 struct ether_multistep step; 3027 u_int32_t crc, mchash[16]; 3028 3029 /* 3030 * Initialize the prototype RFCR. 3031 */ 3032 sc->sc_rfcr = RFCR_RFEN; 3033 if (ifp->if_flags & IFF_BROADCAST) 3034 sc->sc_rfcr |= RFCR_AAB; 3035 if (ifp->if_flags & IFF_PROMISC) { 3036 sc->sc_rfcr |= RFCR_AAP; 3037 goto allmulti; 3038 } 3039 3040 /* 3041 * Set up the multicast address filter by passing all multicast 3042 * addresses through a CRC generator, and then using the high-order 3043 * 6 bits as an index into the 128 bit multicast hash table (only 3044 * the lower 16 bits of each 32 bit multicast hash register are 3045 * valid). The high order bits select the register, while the 3046 * rest of the bits select the bit within the register. 3047 */ 3048 3049 memset(mchash, 0, sizeof(mchash)); 3050 3051 /* 3052 * SiS900 (at least SiS963) requires us to register the address of 3053 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3054 */ 3055 crc = 0x0ed423f9; 3056 3057 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3058 SIP_SIS900_REV(sc, SIS_REV_960) || 3059 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3060 /* Just want the 8 most significant bits. */ 3061 crc >>= 24; 3062 } else { 3063 /* Just want the 7 most significant bits. */ 3064 crc >>= 25; 3065 } 3066 3067 /* Set the corresponding bit in the hash table. */ 3068 mchash[crc >> 4] |= 1 << (crc & 0xf); 3069 3070 ETHER_FIRST_MULTI(step, ec, enm); 3071 while (enm != NULL) { 3072 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3073 /* 3074 * We must listen to a range of multicast addresses. 3075 * For now, just accept all multicasts, rather than 3076 * trying to set only those filter bits needed to match 3077 * the range. (At this time, the only use of address 3078 * ranges is for IP multicast routing, for which the 3079 * range is big enough to require all bits set.) 3080 */ 3081 goto allmulti; 3082 } 3083 3084 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3085 3086 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3087 SIP_SIS900_REV(sc, SIS_REV_960) || 3088 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3089 /* Just want the 8 most significant bits. */ 3090 crc >>= 24; 3091 } else { 3092 /* Just want the 7 most significant bits. */ 3093 crc >>= 25; 3094 } 3095 3096 /* Set the corresponding bit in the hash table. */ 3097 mchash[crc >> 4] |= 1 << (crc & 0xf); 3098 3099 ETHER_NEXT_MULTI(step, enm); 3100 } 3101 3102 ifp->if_flags &= ~IFF_ALLMULTI; 3103 goto setit; 3104 3105 allmulti: 3106 ifp->if_flags |= IFF_ALLMULTI; 3107 sc->sc_rfcr |= RFCR_AAM; 3108 3109 setit: 3110 #define FILTER_EMIT(addr, data) \ 3111 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3112 delay(1); \ 3113 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3114 delay(1) 3115 3116 /* 3117 * Disable receive filter, and program the node address. 3118 */ 3119 cp = CLLADDR(ifp->if_sadl); 3120 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3121 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3122 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3123 3124 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3125 /* 3126 * Program the multicast hash table. 3127 */ 3128 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3129 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3130 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3131 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3132 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3133 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3134 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3135 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3136 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3137 SIP_SIS900_REV(sc, SIS_REV_960) || 3138 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3139 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3140 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3141 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3142 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3143 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3144 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3145 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3146 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3147 } 3148 } 3149 #undef FILTER_EMIT 3150 3151 /* 3152 * Re-enable the receiver filter. 3153 */ 3154 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3155 } 3156 3157 /* 3158 * sip_dp83815_set_filter: 3159 * 3160 * Set up the receive filter. 3161 */ 3162 static void 3163 sipcom_dp83815_set_filter(struct sip_softc *sc) 3164 { 3165 bus_space_tag_t st = sc->sc_st; 3166 bus_space_handle_t sh = sc->sc_sh; 3167 struct ethercom *ec = &sc->sc_ethercom; 3168 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3169 struct ether_multi *enm; 3170 const u_int8_t *cp; 3171 struct ether_multistep step; 3172 u_int32_t crc, hash, slot, bit; 3173 #define MCHASH_NWORDS_83820 128 3174 #define MCHASH_NWORDS_83815 32 3175 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3176 u_int16_t mchash[MCHASH_NWORDS]; 3177 int i; 3178 3179 /* 3180 * Initialize the prototype RFCR. 3181 * Enable the receive filter, and accept on 3182 * Perfect (destination address) Match 3183 * If IFF_BROADCAST, also accept all broadcast packets. 3184 * If IFF_PROMISC, accept all unicast packets (and later, set 3185 * IFF_ALLMULTI and accept all multicast, too). 3186 */ 3187 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3188 if (ifp->if_flags & IFF_BROADCAST) 3189 sc->sc_rfcr |= RFCR_AAB; 3190 if (ifp->if_flags & IFF_PROMISC) { 3191 sc->sc_rfcr |= RFCR_AAP; 3192 goto allmulti; 3193 } 3194 3195 /* 3196 * Set up the DP83820/DP83815 multicast address filter by 3197 * passing all multicast addresses through a CRC generator, 3198 * and then using the high-order 11/9 bits as an index into 3199 * the 2048/512 bit multicast hash table. The high-order 3200 * 7/5 bits select the slot, while the low-order 4 bits 3201 * select the bit within the slot. Note that only the low 3202 * 16-bits of each filter word are used, and there are 3203 * 128/32 filter words. 3204 */ 3205 3206 memset(mchash, 0, sizeof(mchash)); 3207 3208 ifp->if_flags &= ~IFF_ALLMULTI; 3209 ETHER_FIRST_MULTI(step, ec, enm); 3210 if (enm == NULL) 3211 goto setit; 3212 while (enm != NULL) { 3213 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3214 /* 3215 * We must listen to a range of multicast addresses. 3216 * For now, just accept all multicasts, rather than 3217 * trying to set only those filter bits needed to match 3218 * the range. (At this time, the only use of address 3219 * ranges is for IP multicast routing, for which the 3220 * range is big enough to require all bits set.) 3221 */ 3222 goto allmulti; 3223 } 3224 3225 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3226 3227 if (sc->sc_gigabit) { 3228 /* Just want the 11 most significant bits. */ 3229 hash = crc >> 21; 3230 } else { 3231 /* Just want the 9 most significant bits. */ 3232 hash = crc >> 23; 3233 } 3234 3235 slot = hash >> 4; 3236 bit = hash & 0xf; 3237 3238 /* Set the corresponding bit in the hash table. */ 3239 mchash[slot] |= 1 << bit; 3240 3241 ETHER_NEXT_MULTI(step, enm); 3242 } 3243 sc->sc_rfcr |= RFCR_MHEN; 3244 goto setit; 3245 3246 allmulti: 3247 ifp->if_flags |= IFF_ALLMULTI; 3248 sc->sc_rfcr |= RFCR_AAM; 3249 3250 setit: 3251 #define FILTER_EMIT(addr, data) \ 3252 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3253 delay(1); \ 3254 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3255 delay(1) 3256 3257 /* 3258 * Disable receive filter, and program the node address. 3259 */ 3260 cp = CLLADDR(ifp->if_sadl); 3261 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3262 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3263 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3264 3265 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3266 int nwords = 3267 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3268 /* 3269 * Program the multicast hash table. 3270 */ 3271 for (i = 0; i < nwords; i++) { 3272 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3273 } 3274 } 3275 #undef FILTER_EMIT 3276 #undef MCHASH_NWORDS 3277 #undef MCHASH_NWORDS_83815 3278 #undef MCHASH_NWORDS_83820 3279 3280 /* 3281 * Re-enable the receiver filter. 3282 */ 3283 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3284 } 3285 3286 /* 3287 * sip_dp83820_mii_readreg: [mii interface function] 3288 * 3289 * Read a PHY register on the MII of the DP83820. 3290 */ 3291 static int 3292 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3293 { 3294 struct sip_softc *sc = device_private(self); 3295 3296 if (sc->sc_cfg & CFG_TBI_EN) { 3297 bus_addr_t tbireg; 3298 int rv; 3299 3300 if (phy != 0) 3301 return (0); 3302 3303 switch (reg) { 3304 case MII_BMCR: tbireg = SIP_TBICR; break; 3305 case MII_BMSR: tbireg = SIP_TBISR; break; 3306 case MII_ANAR: tbireg = SIP_TANAR; break; 3307 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3308 case MII_ANER: tbireg = SIP_TANER; break; 3309 case MII_EXTSR: 3310 /* 3311 * Don't even bother reading the TESR register. 3312 * The manual documents that the device has 3313 * 1000baseX full/half capability, but the 3314 * register itself seems read back 0 on some 3315 * boards. Just hard-code the result. 3316 */ 3317 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3318 3319 default: 3320 return (0); 3321 } 3322 3323 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3324 if (tbireg == SIP_TBISR) { 3325 /* LINK and ACOMP are switched! */ 3326 int val = rv; 3327 3328 rv = 0; 3329 if (val & TBISR_MR_LINK_STATUS) 3330 rv |= BMSR_LINK; 3331 if (val & TBISR_MR_AN_COMPLETE) 3332 rv |= BMSR_ACOMP; 3333 3334 /* 3335 * The manual claims this register reads back 0 3336 * on hard and soft reset. But we want to let 3337 * the gentbi driver know that we support auto- 3338 * negotiation, so hard-code this bit in the 3339 * result. 3340 */ 3341 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3342 } 3343 3344 return (rv); 3345 } 3346 3347 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3348 } 3349 3350 /* 3351 * sip_dp83820_mii_writereg: [mii interface function] 3352 * 3353 * Write a PHY register on the MII of the DP83820. 3354 */ 3355 static void 3356 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3357 { 3358 struct sip_softc *sc = device_private(self); 3359 3360 if (sc->sc_cfg & CFG_TBI_EN) { 3361 bus_addr_t tbireg; 3362 3363 if (phy != 0) 3364 return; 3365 3366 switch (reg) { 3367 case MII_BMCR: tbireg = SIP_TBICR; break; 3368 case MII_ANAR: tbireg = SIP_TANAR; break; 3369 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3370 default: 3371 return; 3372 } 3373 3374 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3375 return; 3376 } 3377 3378 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3379 } 3380 3381 /* 3382 * sip_dp83820_mii_statchg: [mii interface function] 3383 * 3384 * Callback from MII layer when media changes. 3385 */ 3386 static void 3387 sipcom_dp83820_mii_statchg(device_t self) 3388 { 3389 struct sip_softc *sc = device_private(self); 3390 struct mii_data *mii = &sc->sc_mii; 3391 u_int32_t cfg, pcr; 3392 3393 /* 3394 * Get flow control negotiation result. 3395 */ 3396 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3397 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3398 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3399 mii->mii_media_active &= ~IFM_ETH_FMASK; 3400 } 3401 3402 /* 3403 * Update TXCFG for full-duplex operation. 3404 */ 3405 if ((mii->mii_media_active & IFM_FDX) != 0) 3406 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3407 else 3408 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3409 3410 /* 3411 * Update RXCFG for full-duplex or loopback. 3412 */ 3413 if ((mii->mii_media_active & IFM_FDX) != 0 || 3414 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3415 sc->sc_rxcfg |= RXCFG_ATX; 3416 else 3417 sc->sc_rxcfg &= ~RXCFG_ATX; 3418 3419 /* 3420 * Update CFG for MII/GMII. 3421 */ 3422 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3423 cfg = sc->sc_cfg | CFG_MODE_1000; 3424 else 3425 cfg = sc->sc_cfg; 3426 3427 /* 3428 * 802.3x flow control. 3429 */ 3430 pcr = 0; 3431 if (sc->sc_flowflags & IFM_FLOW) { 3432 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3433 pcr |= sc->sc_rx_flow_thresh; 3434 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3435 pcr |= PCR_PSEN | PCR_PS_MCAST; 3436 } 3437 3438 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3439 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3440 sc->sc_txcfg); 3441 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3442 sc->sc_rxcfg); 3443 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3444 } 3445 3446 /* 3447 * sip_mii_bitbang_read: [mii bit-bang interface function] 3448 * 3449 * Read the MII serial port for the MII bit-bang module. 3450 */ 3451 static u_int32_t 3452 sipcom_mii_bitbang_read(device_t self) 3453 { 3454 struct sip_softc *sc = device_private(self); 3455 3456 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3457 } 3458 3459 /* 3460 * sip_mii_bitbang_write: [mii big-bang interface function] 3461 * 3462 * Write the MII serial port for the MII bit-bang module. 3463 */ 3464 static void 3465 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3466 { 3467 struct sip_softc *sc = device_private(self); 3468 3469 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3470 } 3471 3472 /* 3473 * sip_sis900_mii_readreg: [mii interface function] 3474 * 3475 * Read a PHY register on the MII. 3476 */ 3477 static int 3478 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3479 { 3480 struct sip_softc *sc = device_private(self); 3481 u_int32_t enphy; 3482 3483 /* 3484 * The PHY of recent SiS chipsets is accessed through bitbang 3485 * operations. 3486 */ 3487 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3488 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3489 phy, reg); 3490 3491 #ifndef SIS900_MII_RESTRICT 3492 /* 3493 * The SiS 900 has only an internal PHY on the MII. Only allow 3494 * MII address 0. 3495 */ 3496 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3497 return (0); 3498 #endif 3499 3500 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3501 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3502 ENPHY_RWCMD | ENPHY_ACCESS); 3503 do { 3504 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3505 } while (enphy & ENPHY_ACCESS); 3506 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3507 } 3508 3509 /* 3510 * sip_sis900_mii_writereg: [mii interface function] 3511 * 3512 * Write a PHY register on the MII. 3513 */ 3514 static void 3515 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3516 { 3517 struct sip_softc *sc = device_private(self); 3518 u_int32_t enphy; 3519 3520 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3521 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3522 phy, reg, val); 3523 return; 3524 } 3525 3526 #ifndef SIS900_MII_RESTRICT 3527 /* 3528 * The SiS 900 has only an internal PHY on the MII. Only allow 3529 * MII address 0. 3530 */ 3531 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3532 return; 3533 #endif 3534 3535 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3536 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3537 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3538 do { 3539 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3540 } while (enphy & ENPHY_ACCESS); 3541 } 3542 3543 /* 3544 * sip_sis900_mii_statchg: [mii interface function] 3545 * 3546 * Callback from MII layer when media changes. 3547 */ 3548 static void 3549 sipcom_sis900_mii_statchg(device_t self) 3550 { 3551 struct sip_softc *sc = device_private(self); 3552 struct mii_data *mii = &sc->sc_mii; 3553 u_int32_t flowctl; 3554 3555 /* 3556 * Get flow control negotiation result. 3557 */ 3558 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3559 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3560 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3561 mii->mii_media_active &= ~IFM_ETH_FMASK; 3562 } 3563 3564 /* 3565 * Update TXCFG for full-duplex operation. 3566 */ 3567 if ((mii->mii_media_active & IFM_FDX) != 0) 3568 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3569 else 3570 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3571 3572 /* 3573 * Update RXCFG for full-duplex or loopback. 3574 */ 3575 if ((mii->mii_media_active & IFM_FDX) != 0 || 3576 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3577 sc->sc_rxcfg |= RXCFG_ATX; 3578 else 3579 sc->sc_rxcfg &= ~RXCFG_ATX; 3580 3581 /* 3582 * Update IMR for use of 802.3x flow control. 3583 */ 3584 if (sc->sc_flowflags & IFM_FLOW) { 3585 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3586 flowctl = FLOWCTL_FLOWEN; 3587 } else { 3588 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3589 flowctl = 0; 3590 } 3591 3592 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3593 sc->sc_txcfg); 3594 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3595 sc->sc_rxcfg); 3596 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3598 } 3599 3600 /* 3601 * sip_dp83815_mii_readreg: [mii interface function] 3602 * 3603 * Read a PHY register on the MII. 3604 */ 3605 static int 3606 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3607 { 3608 struct sip_softc *sc = device_private(self); 3609 u_int32_t val; 3610 3611 /* 3612 * The DP83815 only has an internal PHY. Only allow 3613 * MII address 0. 3614 */ 3615 if (phy != 0) 3616 return (0); 3617 3618 /* 3619 * Apparently, after a reset, the DP83815 can take a while 3620 * to respond. During this recovery period, the BMSR returns 3621 * a value of 0. Catch this -- it's not supposed to happen 3622 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3623 * PHY to come back to life. 3624 * 3625 * This works out because the BMSR is the first register 3626 * read during the PHY probe process. 3627 */ 3628 do { 3629 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3630 } while (reg == MII_BMSR && val == 0); 3631 3632 return (val & 0xffff); 3633 } 3634 3635 /* 3636 * sip_dp83815_mii_writereg: [mii interface function] 3637 * 3638 * Write a PHY register to the MII. 3639 */ 3640 static void 3641 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3642 { 3643 struct sip_softc *sc = device_private(self); 3644 3645 /* 3646 * The DP83815 only has an internal PHY. Only allow 3647 * MII address 0. 3648 */ 3649 if (phy != 0) 3650 return; 3651 3652 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3653 } 3654 3655 /* 3656 * sip_dp83815_mii_statchg: [mii interface function] 3657 * 3658 * Callback from MII layer when media changes. 3659 */ 3660 static void 3661 sipcom_dp83815_mii_statchg(device_t self) 3662 { 3663 struct sip_softc *sc = device_private(self); 3664 3665 /* 3666 * Update TXCFG for full-duplex operation. 3667 */ 3668 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3669 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3670 else 3671 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3672 3673 /* 3674 * Update RXCFG for full-duplex or loopback. 3675 */ 3676 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3677 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3678 sc->sc_rxcfg |= RXCFG_ATX; 3679 else 3680 sc->sc_rxcfg &= ~RXCFG_ATX; 3681 3682 /* 3683 * XXX 802.3x flow control. 3684 */ 3685 3686 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3687 sc->sc_txcfg); 3688 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3689 sc->sc_rxcfg); 3690 3691 /* 3692 * Some DP83815s experience problems when used with short 3693 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3694 * sequence adjusts the DSP's signal attenuation to fix the 3695 * problem. 3696 */ 3697 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3698 uint32_t reg; 3699 3700 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3701 3702 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3703 reg &= 0x0fff; 3704 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3705 delay(100); 3706 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3707 reg &= 0x00ff; 3708 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3709 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3710 0x00e8); 3711 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3712 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3713 reg | 0x20); 3714 } 3715 3716 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3717 } 3718 } 3719 3720 static void 3721 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3722 const struct pci_attach_args *pa, u_int8_t *enaddr) 3723 { 3724 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3725 u_int8_t cksum, *e, match; 3726 int i; 3727 3728 /* 3729 * EEPROM data format for the DP83820 can be found in 3730 * the DP83820 manual, section 4.2.4. 3731 */ 3732 3733 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3734 3735 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3736 match = ~(match - 1); 3737 3738 cksum = 0x55; 3739 e = (u_int8_t *) eeprom_data; 3740 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3741 cksum += *e++; 3742 3743 if (cksum != match) 3744 printf("%s: Checksum (%x) mismatch (%x)", 3745 device_xname(&sc->sc_dev), cksum, match); 3746 3747 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3748 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3749 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3750 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3751 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3752 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3753 } 3754 3755 static void 3756 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3757 { 3758 int i; 3759 3760 /* 3761 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3762 * a reason, but I don't know it. 3763 */ 3764 for (i = 0; i < 10; i++) 3765 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3766 } 3767 3768 static void 3769 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3770 const struct pci_attach_args *pa, u_int8_t *enaddr) 3771 { 3772 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3773 3774 switch (sc->sc_rev) { 3775 case SIS_REV_630S: 3776 case SIS_REV_630E: 3777 case SIS_REV_630EA1: 3778 case SIS_REV_630ET: 3779 case SIS_REV_635: 3780 /* 3781 * The MAC address for the on-board Ethernet of 3782 * the SiS 630 chipset is in the NVRAM. Kick 3783 * the chip into re-loading it from NVRAM, and 3784 * read the MAC address out of the filter registers. 3785 */ 3786 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3787 3788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3789 RFCR_RFADDR_NODE0); 3790 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3791 0xffff; 3792 3793 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3794 RFCR_RFADDR_NODE2); 3795 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3796 0xffff; 3797 3798 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3799 RFCR_RFADDR_NODE4); 3800 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3801 0xffff; 3802 break; 3803 3804 case SIS_REV_960: 3805 { 3806 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3807 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3808 3809 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3810 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3811 3812 int waittime, i; 3813 3814 /* Allow to read EEPROM from LAN. It is shared 3815 * between a 1394 controller and the NIC and each 3816 * time we access it, we need to set SIS_EECMD_REQ. 3817 */ 3818 SIS_SET_EROMAR(sc, EROMAR_REQ); 3819 3820 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3821 /* Force EEPROM to idle state. */ 3822 3823 /* 3824 * XXX-cube This is ugly. I'll look for docs about it. 3825 */ 3826 SIS_SET_EROMAR(sc, EROMAR_EECS); 3827 sipcom_sis900_eeprom_delay(sc); 3828 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3829 SIS_SET_EROMAR(sc, EROMAR_EESK); 3830 sipcom_sis900_eeprom_delay(sc); 3831 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3832 sipcom_sis900_eeprom_delay(sc); 3833 } 3834 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3835 sipcom_sis900_eeprom_delay(sc); 3836 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3837 3838 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3839 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3840 sizeof(myea) / sizeof(myea[0]), myea); 3841 break; 3842 } 3843 DELAY(1); 3844 } 3845 3846 /* 3847 * Set SIS_EECTL_CLK to high, so a other master 3848 * can operate on the i2c bus. 3849 */ 3850 SIS_SET_EROMAR(sc, EROMAR_EESK); 3851 3852 /* Refuse EEPROM access by LAN */ 3853 SIS_SET_EROMAR(sc, EROMAR_DONE); 3854 } break; 3855 3856 default: 3857 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3858 sizeof(myea) / sizeof(myea[0]), myea); 3859 } 3860 3861 enaddr[0] = myea[0] & 0xff; 3862 enaddr[1] = myea[0] >> 8; 3863 enaddr[2] = myea[1] & 0xff; 3864 enaddr[3] = myea[1] >> 8; 3865 enaddr[4] = myea[2] & 0xff; 3866 enaddr[5] = myea[2] >> 8; 3867 } 3868 3869 /* Table and macro to bit-reverse an octet. */ 3870 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3871 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3872 3873 static void 3874 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3875 const struct pci_attach_args *pa, u_int8_t *enaddr) 3876 { 3877 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3878 u_int8_t cksum, *e, match; 3879 int i; 3880 3881 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3882 sizeof(eeprom_data[0]), eeprom_data); 3883 3884 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3885 match = ~(match - 1); 3886 3887 cksum = 0x55; 3888 e = (u_int8_t *) eeprom_data; 3889 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3890 cksum += *e++; 3891 } 3892 if (cksum != match) { 3893 printf("%s: Checksum (%x) mismatch (%x)", 3894 device_xname(&sc->sc_dev), cksum, match); 3895 } 3896 3897 /* 3898 * Unrolled because it makes slightly more sense this way. 3899 * The DP83815 stores the MAC address in bit 0 of word 6 3900 * through bit 15 of word 8. 3901 */ 3902 ea = &eeprom_data[6]; 3903 enaddr[0] = ((*ea & 0x1) << 7); 3904 ea++; 3905 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3906 enaddr[1] = ((*ea & 0x1FE) >> 1); 3907 enaddr[2] = ((*ea & 0x1) << 7); 3908 ea++; 3909 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3910 enaddr[3] = ((*ea & 0x1FE) >> 1); 3911 enaddr[4] = ((*ea & 0x1) << 7); 3912 ea++; 3913 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3914 enaddr[5] = ((*ea & 0x1FE) >> 1); 3915 3916 /* 3917 * In case that's not weird enough, we also need to reverse 3918 * the bits in each byte. This all actually makes more sense 3919 * if you think about the EEPROM storage as an array of bits 3920 * being shifted into bytes, but that's not how we're looking 3921 * at it here... 3922 */ 3923 for (i = 0; i < 6 ;i++) 3924 enaddr[i] = bbr(enaddr[i]); 3925 } 3926 3927 /* 3928 * sip_mediastatus: [ifmedia interface function] 3929 * 3930 * Get the current interface media status. 3931 */ 3932 static void 3933 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3934 { 3935 struct sip_softc *sc = ifp->if_softc; 3936 3937 ether_mediastatus(ifp, ifmr); 3938 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3939 sc->sc_flowflags; 3940 } 3941
Indexes created Tue Sep 30 11:09:46 GMT 2025