if_sip.c revision 1.134.8.1
1 /* $NetBSD: if_sip.c,v 1.134.8.1 2009/01/19 13:18:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.134.8.1 2009/01/19 13:18:26 skrll Exp $"); 77 78 #include "bpfilter.h" 79 #include "rnd.h" 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/callout.h> 84 #include <sys/mbuf.h> 85 #include <sys/malloc.h> 86 #include <sys/kernel.h> 87 #include <sys/socket.h> 88 #include <sys/ioctl.h> 89 #include <sys/errno.h> 90 #include <sys/device.h> 91 #include <sys/queue.h> 92 93 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 94 95 #if NRND > 0 96 #include <sys/rnd.h> 97 #endif 98 99 #include <net/if.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_ether.h> 103 104 #if NBPFILTER > 0 105 #include <net/bpf.h> 106 #endif 107 108 #include <sys/bus.h> 109 #include <sys/intr.h> 110 #include <machine/endian.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 #include <dev/mii/mii_bitbang.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 #include <dev/pci/pcidevs.h> 119 120 #include <dev/pci/if_sipreg.h> 121 122 /* 123 * Transmit descriptor list size. This is arbitrary, but allocate 124 * enough descriptors for 128 pending transmissions, and 8 segments 125 * per packet (64 for DP83820 for jumbo frames). 126 * 127 * This MUST work out to a power of 2. 128 */ 129 #define GSIP_NTXSEGS_ALLOC 16 130 #define SIP_NTXSEGS_ALLOC 8 131 132 #define SIP_TXQUEUELEN 256 133 #define MAX_SIP_NTXDESC \ 134 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 135 136 /* 137 * Receive descriptor list size. We have one Rx buffer per incoming 138 * packet, so this logic is a little simpler. 139 * 140 * Actually, on the DP83820, we allow the packet to consume more than 141 * one buffer, in order to support jumbo Ethernet frames. In that 142 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 143 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 144 * so we'd better be quick about handling receive interrupts. 145 */ 146 #define GSIP_NRXDESC 256 147 #define SIP_NRXDESC 128 148 149 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 150 151 /* 152 * Control structures are DMA'd to the SiS900 chip. We allocate them in 153 * a single clump that maps to a single DMA segment to make several things 154 * easier. 155 */ 156 struct sip_control_data { 157 /* 158 * The transmit descriptors. 159 */ 160 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 161 162 /* 163 * The receive descriptors. 164 */ 165 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 166 }; 167 168 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 169 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 170 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 171 172 /* 173 * Software state for transmit jobs. 174 */ 175 struct sip_txsoft { 176 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 177 bus_dmamap_t txs_dmamap; /* our DMA map */ 178 int txs_firstdesc; /* first descriptor in packet */ 179 int txs_lastdesc; /* last descriptor in packet */ 180 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 181 }; 182 183 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 184 185 /* 186 * Software state for receive jobs. 187 */ 188 struct sip_rxsoft { 189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t rxs_dmamap; /* our DMA map */ 191 }; 192 193 enum sip_attach_stage { 194 SIP_ATTACH_FIN = 0 195 , SIP_ATTACH_CREATE_RXMAP 196 , SIP_ATTACH_CREATE_TXMAP 197 , SIP_ATTACH_LOAD_MAP 198 , SIP_ATTACH_CREATE_MAP 199 , SIP_ATTACH_MAP_MEM 200 , SIP_ATTACH_ALLOC_MEM 201 , SIP_ATTACH_INTR 202 , SIP_ATTACH_MAP 203 }; 204 205 /* 206 * Software state per device. 207 */ 208 struct sip_softc { 209 struct device sc_dev; /* generic device information */ 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static int sip_ifflags_cb(struct ethercom *); 563 static void sipcom_start(struct ifnet *); 564 static void sipcom_watchdog(struct ifnet *); 565 static int sipcom_ioctl(struct ifnet *, u_long, void *); 566 static int sipcom_init(struct ifnet *); 567 static void sipcom_stop(struct ifnet *, int); 568 569 static bool sipcom_reset(struct sip_softc *); 570 static void sipcom_rxdrain(struct sip_softc *); 571 static int sipcom_add_rxbuf(struct sip_softc *, int); 572 static void sipcom_read_eeprom(struct sip_softc *, int, int, 573 u_int16_t *); 574 static void sipcom_tick(void *); 575 576 static void sipcom_sis900_set_filter(struct sip_softc *); 577 static void sipcom_dp83815_set_filter(struct sip_softc *); 578 579 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 580 const struct pci_attach_args *, u_int8_t *); 581 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 582 static void sipcom_sis900_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 585 const struct pci_attach_args *, u_int8_t *); 586 587 static int sipcom_intr(void *); 588 static void sipcom_txintr(struct sip_softc *); 589 static void sip_rxintr(struct sip_softc *); 590 static void gsip_rxintr(struct sip_softc *); 591 592 static int sipcom_dp83820_mii_readreg(device_t, int, int); 593 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 594 static void sipcom_dp83820_mii_statchg(device_t); 595 596 static int sipcom_sis900_mii_readreg(device_t, int, int); 597 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 598 static void sipcom_sis900_mii_statchg(device_t); 599 600 static int sipcom_dp83815_mii_readreg(device_t, int, int); 601 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 602 static void sipcom_dp83815_mii_statchg(device_t); 603 604 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 605 606 static int sipcom_match(device_t, struct cfdata *, void *); 607 static void sipcom_attach(device_t, device_t, void *); 608 static void sipcom_do_detach(device_t, enum sip_attach_stage); 609 static int sipcom_detach(device_t, int); 610 static bool sipcom_resume(device_t PMF_FN_PROTO); 611 static bool sipcom_suspend(device_t PMF_FN_PROTO); 612 613 int gsip_copy_small = 0; 614 int sip_copy_small = 0; 615 616 CFATTACH_DECL(gsip, sizeof(struct sip_softc), 617 sipcom_match, sipcom_attach, sipcom_detach, NULL); 618 CFATTACH_DECL(sip, sizeof(struct sip_softc), 619 sipcom_match, sipcom_attach, sipcom_detach, NULL); 620 621 /* 622 * Descriptions of the variants of the SiS900. 623 */ 624 struct sip_variant { 625 int (*sipv_mii_readreg)(device_t, int, int); 626 void (*sipv_mii_writereg)(device_t, int, int, int); 627 void (*sipv_mii_statchg)(device_t); 628 void (*sipv_set_filter)(struct sip_softc *); 629 void (*sipv_read_macaddr)(struct sip_softc *, 630 const struct pci_attach_args *, u_int8_t *); 631 }; 632 633 static u_int32_t sipcom_mii_bitbang_read(device_t); 634 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 635 636 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 637 sipcom_mii_bitbang_read, 638 sipcom_mii_bitbang_write, 639 { 640 EROMAR_MDIO, /* MII_BIT_MDO */ 641 EROMAR_MDIO, /* MII_BIT_MDI */ 642 EROMAR_MDC, /* MII_BIT_MDC */ 643 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 644 0, /* MII_BIT_DIR_PHY_HOST */ 645 } 646 }; 647 648 static const struct sip_variant sipcom_variant_dp83820 = { 649 sipcom_dp83820_mii_readreg, 650 sipcom_dp83820_mii_writereg, 651 sipcom_dp83820_mii_statchg, 652 sipcom_dp83815_set_filter, 653 sipcom_dp83820_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_sis900 = { 657 sipcom_sis900_mii_readreg, 658 sipcom_sis900_mii_writereg, 659 sipcom_sis900_mii_statchg, 660 sipcom_sis900_set_filter, 661 sipcom_sis900_read_macaddr, 662 }; 663 664 static const struct sip_variant sipcom_variant_dp83815 = { 665 sipcom_dp83815_mii_readreg, 666 sipcom_dp83815_mii_writereg, 667 sipcom_dp83815_mii_statchg, 668 sipcom_dp83815_set_filter, 669 sipcom_dp83815_read_macaddr, 670 }; 671 672 673 /* 674 * Devices supported by this driver. 675 */ 676 static const struct sip_product { 677 pci_vendor_id_t sip_vendor; 678 pci_product_id_t sip_product; 679 const char *sip_name; 680 const struct sip_variant *sip_variant; 681 int sip_gigabit; 682 } sipcom_products[] = { 683 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 684 "NatSemi DP83820 Gigabit Ethernet", 685 &sipcom_variant_dp83820, 1 }, 686 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 687 "SiS 900 10/100 Ethernet", 688 &sipcom_variant_sis900, 0 }, 689 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 690 "SiS 7016 10/100 Ethernet", 691 &sipcom_variant_sis900, 0 }, 692 693 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 694 "NatSemi DP83815 10/100 Ethernet", 695 &sipcom_variant_dp83815, 0 }, 696 697 { 0, 0, 698 NULL, 699 NULL, 0 }, 700 }; 701 702 static const struct sip_product * 703 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 704 { 705 const struct sip_product *sip; 706 707 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 708 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 709 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 710 sip->sip_gigabit == gigabit) 711 return sip; 712 } 713 return NULL; 714 } 715 716 /* 717 * I really hate stupid hardware vendors. There's a bit in the EEPROM 718 * which indicates if the card can do 64-bit data transfers. Unfortunately, 719 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 720 * which means we try to use 64-bit data transfers on those cards if we 721 * happen to be plugged into a 32-bit slot. 722 * 723 * What we do is use this table of cards known to be 64-bit cards. If 724 * you have a 64-bit card who's subsystem ID is not listed in this table, 725 * send the output of "pcictl dump ..." of the device to me so that your 726 * card will use the 64-bit data path when plugged into a 64-bit slot. 727 * 728 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 729 * June 30, 2002 730 */ 731 static int 732 sipcom_check_64bit(const struct pci_attach_args *pa) 733 { 734 static const struct { 735 pci_vendor_id_t c64_vendor; 736 pci_product_id_t c64_product; 737 } card64[] = { 738 /* Asante GigaNIX */ 739 { 0x128a, 0x0002 }, 740 741 /* Accton EN1407-T, Planex GN-1000TE */ 742 { 0x1113, 0x1407 }, 743 744 /* Netgear GA-621 */ 745 { 0x1385, 0x621a }, 746 747 /* SMC EZ Card */ 748 { 0x10b8, 0x9462 }, 749 750 { 0, 0} 751 }; 752 pcireg_t subsys; 753 int i; 754 755 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 756 757 for (i = 0; card64[i].c64_vendor != 0; i++) { 758 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 759 PCI_PRODUCT(subsys) == card64[i].c64_product) 760 return (1); 761 } 762 763 return (0); 764 } 765 766 static int 767 sipcom_match(device_t parent, struct cfdata *cf, void *aux) 768 { 769 struct pci_attach_args *pa = aux; 770 771 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 772 return 1; 773 774 return 0; 775 } 776 777 static void 778 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 779 { 780 u_int32_t reg; 781 int i; 782 783 /* 784 * Cause the chip to load configuration data from the EEPROM. 785 */ 786 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 787 for (i = 0; i < 10000; i++) { 788 delay(10); 789 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 790 PTSCR_EELOAD_EN) == 0) 791 break; 792 } 793 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 794 PTSCR_EELOAD_EN) { 795 printf("%s: timeout loading configuration from EEPROM\n", 796 device_xname(&sc->sc_dev)); 797 return; 798 } 799 800 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 801 802 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 803 if (reg & CFG_PCI64_DET) { 804 printf("%s: 64-bit PCI slot detected", device_xname(&sc->sc_dev)); 805 /* 806 * Check to see if this card is 64-bit. If so, enable 64-bit 807 * data transfers. 808 * 809 * We can't use the DATA64_EN bit in the EEPROM, because 810 * vendors of 32-bit cards fail to clear that bit in many 811 * cases (yet the card still detects that it's in a 64-bit 812 * slot; go figure). 813 */ 814 if (sipcom_check_64bit(pa)) { 815 sc->sc_cfg |= CFG_DATA64_EN; 816 printf(", using 64-bit data transfers"); 817 } 818 printf("\n"); 819 } 820 821 /* 822 * XXX Need some PCI flags indicating support for 823 * XXX 64-bit addressing. 824 */ 825 #if 0 826 if (reg & CFG_M64ADDR) 827 sc->sc_cfg |= CFG_M64ADDR; 828 if (reg & CFG_T64ADDR) 829 sc->sc_cfg |= CFG_T64ADDR; 830 #endif 831 832 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 833 const char *sep = ""; 834 printf("%s: using ", device_xname(&sc->sc_dev)); 835 if (reg & CFG_EXT_125) { 836 sc->sc_cfg |= CFG_EXT_125; 837 printf("%s125MHz clock", sep); 838 sep = ", "; 839 } 840 if (reg & CFG_TBI_EN) { 841 sc->sc_cfg |= CFG_TBI_EN; 842 printf("%sten-bit interface", sep); 843 sep = ", "; 844 } 845 printf("\n"); 846 } 847 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 848 (reg & CFG_MRM_DIS) != 0) 849 sc->sc_cfg |= CFG_MRM_DIS; 850 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 851 (reg & CFG_MWI_DIS) != 0) 852 sc->sc_cfg |= CFG_MWI_DIS; 853 854 /* 855 * Use the extended descriptor format on the DP83820. This 856 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 857 * checksumming. 858 */ 859 sc->sc_cfg |= CFG_EXTSTS_EN; 860 } 861 862 static int 863 sipcom_detach(device_t self, int flags) 864 { 865 int s; 866 867 s = splnet(); 868 sipcom_do_detach(self, SIP_ATTACH_FIN); 869 splx(s); 870 871 return 0; 872 } 873 874 static void 875 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 876 { 877 int i; 878 struct sip_softc *sc = device_private(self); 879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 880 881 /* 882 * Free any resources we've allocated during attach. 883 * Do this in reverse order and fall through. 884 */ 885 switch (stage) { 886 case SIP_ATTACH_FIN: 887 sipcom_stop(ifp, 1); 888 pmf_device_deregister(self); 889 #ifdef SIP_EVENT_COUNTERS 890 /* 891 * Attach event counters. 892 */ 893 evcnt_detach(&sc->sc_ev_txforceintr); 894 evcnt_detach(&sc->sc_ev_txdstall); 895 evcnt_detach(&sc->sc_ev_txsstall); 896 evcnt_detach(&sc->sc_ev_hiberr); 897 evcnt_detach(&sc->sc_ev_rxintr); 898 evcnt_detach(&sc->sc_ev_txiintr); 899 evcnt_detach(&sc->sc_ev_txdintr); 900 if (!sc->sc_gigabit) { 901 evcnt_detach(&sc->sc_ev_rxpause); 902 } else { 903 evcnt_detach(&sc->sc_ev_txudpsum); 904 evcnt_detach(&sc->sc_ev_txtcpsum); 905 evcnt_detach(&sc->sc_ev_txipsum); 906 evcnt_detach(&sc->sc_ev_rxudpsum); 907 evcnt_detach(&sc->sc_ev_rxtcpsum); 908 evcnt_detach(&sc->sc_ev_rxipsum); 909 evcnt_detach(&sc->sc_ev_txpause); 910 evcnt_detach(&sc->sc_ev_rxpause); 911 } 912 #endif /* SIP_EVENT_COUNTERS */ 913 914 #if NRND > 0 915 rnd_detach_source(&sc->rnd_source); 916 #endif 917 918 ether_ifdetach(ifp); 919 if_detach(ifp); 920 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 921 922 /*FALLTHROUGH*/ 923 case SIP_ATTACH_CREATE_RXMAP: 924 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 925 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 926 bus_dmamap_destroy(sc->sc_dmat, 927 sc->sc_rxsoft[i].rxs_dmamap); 928 } 929 /*FALLTHROUGH*/ 930 case SIP_ATTACH_CREATE_TXMAP: 931 for (i = 0; i < SIP_TXQUEUELEN; i++) { 932 if (sc->sc_txsoft[i].txs_dmamap != NULL) 933 bus_dmamap_destroy(sc->sc_dmat, 934 sc->sc_txsoft[i].txs_dmamap); 935 } 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_LOAD_MAP: 938 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_CREATE_MAP: 941 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 942 /*FALLTHROUGH*/ 943 case SIP_ATTACH_MAP_MEM: 944 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 945 sizeof(struct sip_control_data)); 946 /*FALLTHROUGH*/ 947 case SIP_ATTACH_ALLOC_MEM: 948 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_INTR: 951 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 952 /* FALLTHROUGH*/ 953 case SIP_ATTACH_MAP: 954 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 955 break; 956 default: 957 break; 958 } 959 return; 960 } 961 962 static bool 963 sipcom_resume(device_t self PMF_FN_ARGS) 964 { 965 struct sip_softc *sc = device_private(self); 966 967 return sipcom_reset(sc); 968 } 969 970 static bool 971 sipcom_suspend(device_t self PMF_FN_ARGS) 972 { 973 struct sip_softc *sc = device_private(self); 974 975 sipcom_rxdrain(sc); 976 return true; 977 } 978 979 static void 980 sipcom_attach(device_t parent, device_t self, void *aux) 981 { 982 struct sip_softc *sc = device_private(self); 983 struct pci_attach_args *pa = aux; 984 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 985 pci_chipset_tag_t pc = pa->pa_pc; 986 pci_intr_handle_t ih; 987 const char *intrstr = NULL; 988 bus_space_tag_t iot, memt; 989 bus_space_handle_t ioh, memh; 990 bus_size_t iosz, memsz; 991 int ioh_valid, memh_valid; 992 int i, rseg, error; 993 const struct sip_product *sip; 994 u_int8_t enaddr[ETHER_ADDR_LEN]; 995 pcireg_t csr; 996 pcireg_t memtype; 997 bus_size_t tx_dmamap_size; 998 int ntxsegs_alloc; 999 cfdata_t cf = device_cfdata(self); 1000 1001 callout_init(&sc->sc_tick_ch, 0); 1002 1003 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1004 if (sip == NULL) { 1005 printf("\n"); 1006 panic("%s: impossible", __func__); 1007 } 1008 sc->sc_gigabit = sip->sip_gigabit; 1009 1010 sc->sc_pc = pc; 1011 1012 if (sc->sc_gigabit) { 1013 sc->sc_rxintr = gsip_rxintr; 1014 sc->sc_parm = &gsip_parm; 1015 } else { 1016 sc->sc_rxintr = sip_rxintr; 1017 sc->sc_parm = &sip_parm; 1018 } 1019 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1020 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1021 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1022 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1023 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1024 1025 sc->sc_rev = PCI_REVISION(pa->pa_class); 1026 1027 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1028 1029 sc->sc_model = sip; 1030 1031 /* 1032 * XXX Work-around broken PXE firmware on some boards. 1033 * 1034 * The DP83815 shares an address decoder with the MEM BAR 1035 * and the ROM BAR. Make sure the ROM BAR is disabled, 1036 * so that memory mapped access works. 1037 */ 1038 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1040 ~PCI_MAPREG_ROM_ENABLE); 1041 1042 /* 1043 * Map the device. 1044 */ 1045 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1046 PCI_MAPREG_TYPE_IO, 0, 1047 &iot, &ioh, NULL, &iosz) == 0); 1048 if (sc->sc_gigabit) { 1049 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1050 switch (memtype) { 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1052 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1053 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1054 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1055 break; 1056 default: 1057 memh_valid = 0; 1058 } 1059 } else { 1060 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1061 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1062 &memt, &memh, NULL, &memsz) == 0); 1063 } 1064 1065 if (memh_valid) { 1066 sc->sc_st = memt; 1067 sc->sc_sh = memh; 1068 sc->sc_sz = memsz; 1069 } else if (ioh_valid) { 1070 sc->sc_st = iot; 1071 sc->sc_sh = ioh; 1072 sc->sc_sz = iosz; 1073 } else { 1074 printf("%s: unable to map device registers\n", 1075 device_xname(&sc->sc_dev)); 1076 return; 1077 } 1078 1079 sc->sc_dmat = pa->pa_dmat; 1080 1081 /* 1082 * Make sure bus mastering is enabled. Also make sure 1083 * Write/Invalidate is enabled if we're allowed to use it. 1084 */ 1085 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1086 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1087 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1088 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1089 csr | PCI_COMMAND_MASTER_ENABLE); 1090 1091 /* power up chip */ 1092 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1093 if (error != 0 && error != EOPNOTSUPP) { 1094 aprint_error_dev(&sc->sc_dev, "cannot activate %d\n", error); 1095 return; 1096 } 1097 1098 /* 1099 * Map and establish our interrupt. 1100 */ 1101 if (pci_intr_map(pa, &ih)) { 1102 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 1103 return; 1104 } 1105 intrstr = pci_intr_string(pc, ih); 1106 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1107 if (sc->sc_ih == NULL) { 1108 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 1109 if (intrstr != NULL) 1110 printf(" at %s", intrstr); 1111 printf("\n"); 1112 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1113 } 1114 printf("%s: interrupting at %s\n", device_xname(&sc->sc_dev), intrstr); 1115 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 1119 /* 1120 * Allocate the control data structures, and create and load the 1121 * DMA map for it. 1122 */ 1123 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1124 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1125 &rseg, 0)) != 0) { 1126 aprint_error_dev(&sc->sc_dev, "unable to allocate control data, error = %d\n", 1127 error); 1128 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1129 } 1130 1131 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1132 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1133 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1134 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 1135 error); 1136 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->sc_dmat, 1140 sizeof(struct sip_control_data), 1, 1141 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1142 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 1143 "error = %d\n", error); 1144 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1148 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1149 0)) != 0) { 1150 aprint_error_dev(&sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1151 error); 1152 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1153 } 1154 1155 /* 1156 * Create the transmit buffer DMA maps. 1157 */ 1158 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1159 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1160 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1161 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1162 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 1163 "error = %d\n", i, error); 1164 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1165 } 1166 } 1167 1168 /* 1169 * Create the receive buffer DMA maps. 1170 */ 1171 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1172 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1173 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1174 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 1175 "error = %d\n", i, error); 1176 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1177 } 1178 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1179 } 1180 1181 /* 1182 * Reset the chip to a known state. 1183 */ 1184 sipcom_reset(sc); 1185 1186 /* 1187 * Read the Ethernet address from the EEPROM. This might 1188 * also fetch other stuff from the EEPROM and stash it 1189 * in the softc. 1190 */ 1191 sc->sc_cfg = 0; 1192 if (!sc->sc_gigabit) { 1193 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1194 SIP_SIS900_REV(sc,SIS_REV_900B)) 1195 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1196 1197 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1198 SIP_SIS900_REV(sc,SIS_REV_960) || 1199 SIP_SIS900_REV(sc,SIS_REV_900B)) 1200 sc->sc_cfg |= 1201 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1202 CFG_EDBMASTEN); 1203 } 1204 1205 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1206 1207 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 1208 ether_sprintf(enaddr)); 1209 1210 /* 1211 * Initialize the configuration register: aggressive PCI 1212 * bus request algorithm, default backoff, default OW timer, 1213 * default parity error detection. 1214 * 1215 * NOTE: "Big endian mode" is useless on the SiS900 and 1216 * friends -- it affects packet data, not descriptors. 1217 */ 1218 if (sc->sc_gigabit) 1219 sipcom_dp83820_attach(sc, pa); 1220 1221 /* 1222 * Initialize our media structures and probe the MII. 1223 */ 1224 sc->sc_mii.mii_ifp = ifp; 1225 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1226 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1227 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1228 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1229 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1244 } else 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 ether_ifattach(ifp, enaddr); 1287 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1288 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1289 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1290 sc->sc_prev.if_capenable = ifp->if_capenable; 1291 #if NRND > 0 1292 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 1293 RND_TYPE_NET, 0); 1294 #endif 1295 1296 /* 1297 * The number of bytes that must be available in 1298 * the Tx FIFO before the bus master can DMA more 1299 * data into the FIFO. 1300 */ 1301 sc->sc_tx_fill_thresh = 64 / 32; 1302 1303 /* 1304 * Start at a drain threshold of 512 bytes. We will 1305 * increase it if a DMA underrun occurs. 1306 * 1307 * XXX The minimum value of this variable should be 1308 * tuned. We may be able to improve performance 1309 * by starting with a lower value. That, however, 1310 * may trash the first few outgoing packets if the 1311 * PCI bus is saturated. 1312 */ 1313 if (sc->sc_gigabit) 1314 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1315 else 1316 sc->sc_tx_drain_thresh = 1504 / 32; 1317 1318 /* 1319 * Initialize the Rx FIFO drain threshold. 1320 * 1321 * This is in units of 8 bytes. 1322 * 1323 * We should never set this value lower than 2; 14 bytes are 1324 * required to filter the packet. 1325 */ 1326 sc->sc_rx_drain_thresh = 128 / 8; 1327 1328 #ifdef SIP_EVENT_COUNTERS 1329 /* 1330 * Attach event counters. 1331 */ 1332 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(&sc->sc_dev), "txsstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1335 NULL, device_xname(&sc->sc_dev), "txdstall"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(&sc->sc_dev), "txforceintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(&sc->sc_dev), "txdintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(&sc->sc_dev), "txiintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(&sc->sc_dev), "rxintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(&sc->sc_dev), "hiberr"); 1346 if (!sc->sc_gigabit) { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1348 NULL, device_xname(&sc->sc_dev), "rxpause"); 1349 } else { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(&sc->sc_dev), "rxpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1353 NULL, device_xname(&sc->sc_dev), "txpause"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(&sc->sc_dev), "rxipsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(&sc->sc_dev), "rxtcpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(&sc->sc_dev), "rxudpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(&sc->sc_dev), "txipsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(&sc->sc_dev), "txtcpsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(&sc->sc_dev), "txudpsum"); 1366 } 1367 #endif /* SIP_EVENT_COUNTERS */ 1368 1369 if (!pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1370 aprint_error_dev(self, "couldn't establish power handler\n"); 1371 else 1372 pmf_class_network_register(self, ifp); 1373 } 1374 1375 static inline void 1376 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1377 uint64_t capenable) 1378 { 1379 struct m_tag *mtag; 1380 u_int32_t extsts; 1381 #ifdef DEBUG 1382 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1383 #endif 1384 /* 1385 * If VLANs are enabled and the packet has a VLAN tag, set 1386 * up the descriptor to encapsulate the packet for us. 1387 * 1388 * This apparently has to be on the last descriptor of 1389 * the packet. 1390 */ 1391 1392 /* 1393 * Byte swapping is tricky. We need to provide the tag 1394 * in a network byte order. On a big-endian machine, 1395 * the byteorder is correct, but we need to swap it 1396 * anyway, because this will be undone by the outside 1397 * htole32(). That's why there must be an 1398 * unconditional swap instead of htons() inside. 1399 */ 1400 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1401 sc->sc_txdescs[lasttx].sipd_extsts |= 1402 htole32(EXTSTS_VPKT | 1403 (bswap16(VLAN_TAG_VALUE(mtag)) & 1404 EXTSTS_VTCI)); 1405 } 1406 1407 /* 1408 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1409 * checksumming, set up the descriptor to do this work 1410 * for us. 1411 * 1412 * This apparently has to be on the first descriptor of 1413 * the packet. 1414 * 1415 * Byte-swap constants so the compiler can optimize. 1416 */ 1417 extsts = 0; 1418 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1419 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1420 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1421 extsts |= htole32(EXTSTS_IPPKT); 1422 } 1423 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1424 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1425 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1426 extsts |= htole32(EXTSTS_TCPPKT); 1427 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1428 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1429 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1430 extsts |= htole32(EXTSTS_UDPPKT); 1431 } 1432 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1433 } 1434 1435 /* 1436 * sip_start: [ifnet interface function] 1437 * 1438 * Start packet transmission on the interface. 1439 */ 1440 static void 1441 sipcom_start(struct ifnet *ifp) 1442 { 1443 struct sip_softc *sc = ifp->if_softc; 1444 struct mbuf *m0; 1445 struct mbuf *m; 1446 struct sip_txsoft *txs; 1447 bus_dmamap_t dmamap; 1448 int error, nexttx, lasttx, seg; 1449 int ofree = sc->sc_txfree; 1450 #if 0 1451 int firsttx = sc->sc_txnext; 1452 #endif 1453 1454 /* 1455 * If we've been told to pause, don't transmit any more packets. 1456 */ 1457 if (!sc->sc_gigabit && sc->sc_paused) 1458 ifp->if_flags |= IFF_OACTIVE; 1459 1460 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1461 return; 1462 1463 /* 1464 * Loop through the send queue, setting up transmit descriptors 1465 * until we drain the queue, or use up all available transmit 1466 * descriptors. 1467 */ 1468 for (;;) { 1469 /* Get a work queue entry. */ 1470 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1471 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1472 break; 1473 } 1474 1475 /* 1476 * Grab a packet off the queue. 1477 */ 1478 IFQ_POLL(&ifp->if_snd, m0); 1479 if (m0 == NULL) 1480 break; 1481 m = NULL; 1482 1483 dmamap = txs->txs_dmamap; 1484 1485 /* 1486 * Load the DMA map. If this fails, the packet either 1487 * didn't fit in the alloted number of segments, or we 1488 * were short on resources. 1489 */ 1490 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1491 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1492 /* In the non-gigabit case, we'll copy and try again. */ 1493 if (error != 0 && !sc->sc_gigabit) { 1494 MGETHDR(m, M_DONTWAIT, MT_DATA); 1495 if (m == NULL) { 1496 printf("%s: unable to allocate Tx mbuf\n", 1497 device_xname(&sc->sc_dev)); 1498 break; 1499 } 1500 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1501 if (m0->m_pkthdr.len > MHLEN) { 1502 MCLGET(m, M_DONTWAIT); 1503 if ((m->m_flags & M_EXT) == 0) { 1504 printf("%s: unable to allocate Tx " 1505 "cluster\n", device_xname(&sc->sc_dev)); 1506 m_freem(m); 1507 break; 1508 } 1509 } 1510 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1511 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1512 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1513 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1514 if (error) { 1515 printf("%s: unable to load Tx buffer, " 1516 "error = %d\n", device_xname(&sc->sc_dev), error); 1517 break; 1518 } 1519 } else if (error == EFBIG) { 1520 /* 1521 * For the too-many-segments case, we simply 1522 * report an error and drop the packet, 1523 * since we can't sanely copy a jumbo packet 1524 * to a single buffer. 1525 */ 1526 printf("%s: Tx packet consumes too many " 1527 "DMA segments, dropping...\n", device_xname(&sc->sc_dev)); 1528 IFQ_DEQUEUE(&ifp->if_snd, m0); 1529 m_freem(m0); 1530 continue; 1531 } else if (error != 0) { 1532 /* 1533 * Short on resources, just stop for now. 1534 */ 1535 break; 1536 } 1537 1538 /* 1539 * Ensure we have enough descriptors free to describe 1540 * the packet. Note, we always reserve one descriptor 1541 * at the end of the ring as a termination point, to 1542 * prevent wrap-around. 1543 */ 1544 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1545 /* 1546 * Not enough free descriptors to transmit this 1547 * packet. We haven't committed anything yet, 1548 * so just unload the DMA map, put the packet 1549 * back on the queue, and punt. Notify the upper 1550 * layer that there are not more slots left. 1551 * 1552 * XXX We could allocate an mbuf and copy, but 1553 * XXX is it worth it? 1554 */ 1555 ifp->if_flags |= IFF_OACTIVE; 1556 bus_dmamap_unload(sc->sc_dmat, dmamap); 1557 if (m != NULL) 1558 m_freem(m); 1559 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1560 break; 1561 } 1562 1563 IFQ_DEQUEUE(&ifp->if_snd, m0); 1564 if (m != NULL) { 1565 m_freem(m0); 1566 m0 = m; 1567 } 1568 1569 /* 1570 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1571 */ 1572 1573 /* Sync the DMA map. */ 1574 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1575 BUS_DMASYNC_PREWRITE); 1576 1577 /* 1578 * Initialize the transmit descriptors. 1579 */ 1580 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1581 seg < dmamap->dm_nsegs; 1582 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1583 /* 1584 * If this is the first descriptor we're 1585 * enqueueing, don't set the OWN bit just 1586 * yet. That could cause a race condition. 1587 * We'll do it below. 1588 */ 1589 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32(dmamap->dm_segs[seg].ds_addr); 1591 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1592 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1593 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1594 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1595 lasttx = nexttx; 1596 } 1597 1598 /* Clear the MORE bit on the last segment. */ 1599 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1600 htole32(~CMDSTS_MORE); 1601 1602 /* 1603 * If we're in the interrupt delay window, delay the 1604 * interrupt. 1605 */ 1606 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1607 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1608 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1609 htole32(CMDSTS_INTR); 1610 sc->sc_txwin = 0; 1611 } 1612 1613 if (sc->sc_gigabit) 1614 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1615 1616 /* Sync the descriptors we're using. */ 1617 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1618 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1619 1620 /* 1621 * The entire packet is set up. Give the first descrptor 1622 * to the chip now. 1623 */ 1624 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1625 htole32(CMDSTS_OWN); 1626 sip_cdtxsync(sc, sc->sc_txnext, 1, 1627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1628 1629 /* 1630 * Store a pointer to the packet so we can free it later, 1631 * and remember what txdirty will be once the packet is 1632 * done. 1633 */ 1634 txs->txs_mbuf = m0; 1635 txs->txs_firstdesc = sc->sc_txnext; 1636 txs->txs_lastdesc = lasttx; 1637 1638 /* Advance the tx pointer. */ 1639 sc->sc_txfree -= dmamap->dm_nsegs; 1640 sc->sc_txnext = nexttx; 1641 1642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1643 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1644 1645 #if NBPFILTER > 0 1646 /* 1647 * Pass the packet to any BPF listeners. 1648 */ 1649 if (ifp->if_bpf) 1650 bpf_mtap(ifp->if_bpf, m0); 1651 #endif /* NBPFILTER > 0 */ 1652 } 1653 1654 if (txs == NULL || sc->sc_txfree == 0) { 1655 /* No more slots left; notify upper layer. */ 1656 ifp->if_flags |= IFF_OACTIVE; 1657 } 1658 1659 if (sc->sc_txfree != ofree) { 1660 /* 1661 * Start the transmit process. Note, the manual says 1662 * that if there are no pending transmissions in the 1663 * chip's internal queue (indicated by TXE being clear), 1664 * then the driver software must set the TXDP to the 1665 * first descriptor to be transmitted. However, if we 1666 * do this, it causes serious performance degredation on 1667 * the DP83820 under load, not setting TXDP doesn't seem 1668 * to adversely affect the SiS 900 or DP83815. 1669 * 1670 * Well, I guess it wouldn't be the first time a manual 1671 * has lied -- and they could be speaking of the NULL- 1672 * terminated descriptor list case, rather than OWN- 1673 * terminated rings. 1674 */ 1675 #if 0 1676 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1677 CR_TXE) == 0) { 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1679 SIP_CDTXADDR(sc, firsttx)); 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1681 } 1682 #else 1683 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1684 #endif 1685 1686 /* Set a watchdog timer in case the chip flakes out. */ 1687 /* Gigabit autonegotiation takes 5 seconds. */ 1688 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1689 } 1690 } 1691 1692 /* 1693 * sip_watchdog: [ifnet interface function] 1694 * 1695 * Watchdog timer handler. 1696 */ 1697 static void 1698 sipcom_watchdog(struct ifnet *ifp) 1699 { 1700 struct sip_softc *sc = ifp->if_softc; 1701 1702 /* 1703 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1704 * If we get a timeout, try and sweep up transmit descriptors. 1705 * If we manage to sweep them all up, ignore the lack of 1706 * interrupt. 1707 */ 1708 sipcom_txintr(sc); 1709 1710 if (sc->sc_txfree != sc->sc_ntxdesc) { 1711 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 1712 ifp->if_oerrors++; 1713 1714 /* Reset the interface. */ 1715 (void) sipcom_init(ifp); 1716 } else if (ifp->if_flags & IFF_DEBUG) 1717 printf("%s: recovered from device timeout\n", 1718 device_xname(&sc->sc_dev)); 1719 1720 /* Try to get more packets going. */ 1721 sipcom_start(ifp); 1722 } 1723 1724 /* If the interface is up and running, only modify the receive 1725 * filter when setting promiscuous or debug mode. Otherwise fall 1726 * through to ether_ioctl, which will reset the chip. 1727 */ 1728 static int 1729 sip_ifflags_cb(struct ethercom *ec) 1730 { 1731 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1732 == (sc)->sc_ethercom.ec_capenable) \ 1733 && ((sc)->sc_prev.is_vlan == \ 1734 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1735 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1736 struct ifnet *ifp = &ec->ec_if; 1737 struct sip_softc *sc = ifp->if_softc; 1738 int change = ifp->if_flags ^ sc->sc_if_flags; 1739 1740 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1741 !COMPARE_IC(sc, ifp)) 1742 return ENETRESET; 1743 /* Set up the receive filter. */ 1744 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1745 return 0; 1746 } 1747 1748 /* 1749 * sip_ioctl: [ifnet interface function] 1750 * 1751 * Handle control requests from the operator. 1752 */ 1753 static int 1754 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1755 { 1756 struct sip_softc *sc = ifp->if_softc; 1757 struct ifreq *ifr = (struct ifreq *)data; 1758 int s, error; 1759 1760 s = splnet(); 1761 1762 switch (cmd) { 1763 case SIOCSIFMEDIA: 1764 /* Flow control requires full-duplex mode. */ 1765 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1766 (ifr->ifr_media & IFM_FDX) == 0) 1767 ifr->ifr_media &= ~IFM_ETH_FMASK; 1768 1769 /* XXX */ 1770 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1771 ifr->ifr_media &= ~IFM_ETH_FMASK; 1772 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1773 if (sc->sc_gigabit && 1774 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1775 /* We can do both TXPAUSE and RXPAUSE. */ 1776 ifr->ifr_media |= 1777 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1778 } else if (ifr->ifr_media & IFM_FLOW) { 1779 /* 1780 * Both TXPAUSE and RXPAUSE must be set. 1781 * (SiS900 and DP83815 don't have PAUSE_ASYM 1782 * feature.) 1783 * 1784 * XXX Can SiS900 and DP83815 send PAUSE? 1785 */ 1786 ifr->ifr_media |= 1787 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1788 } 1789 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1790 } 1791 /*FALLTHROUGH*/ 1792 default: 1793 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1794 break; 1795 1796 error = 0; 1797 1798 if (cmd == SIOCSIFCAP) 1799 error = (*ifp->if_init)(ifp); 1800 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1801 ; 1802 else if (ifp->if_flags & IFF_RUNNING) { 1803 /* 1804 * Multicast list has changed; set the hardware filter 1805 * accordingly. 1806 */ 1807 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1808 } 1809 break; 1810 } 1811 1812 /* Try to get more packets going. */ 1813 sipcom_start(ifp); 1814 1815 sc->sc_if_flags = ifp->if_flags; 1816 splx(s); 1817 return (error); 1818 } 1819 1820 /* 1821 * sip_intr: 1822 * 1823 * Interrupt service routine. 1824 */ 1825 static int 1826 sipcom_intr(void *arg) 1827 { 1828 struct sip_softc *sc = arg; 1829 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1830 u_int32_t isr; 1831 int handled = 0; 1832 1833 if (!device_is_active(&sc->sc_dev)) 1834 return 0; 1835 1836 /* Disable interrupts. */ 1837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1838 1839 for (;;) { 1840 /* Reading clears interrupt. */ 1841 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1842 if ((isr & sc->sc_imr) == 0) 1843 break; 1844 1845 #if NRND > 0 1846 if (RND_ENABLED(&sc->rnd_source)) 1847 rnd_add_uint32(&sc->rnd_source, isr); 1848 #endif 1849 1850 handled = 1; 1851 1852 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1853 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1854 1855 /* Grab any new packets. */ 1856 (*sc->sc_rxintr)(sc); 1857 1858 if (isr & ISR_RXORN) { 1859 printf("%s: receive FIFO overrun\n", 1860 device_xname(&sc->sc_dev)); 1861 1862 /* XXX adjust rx_drain_thresh? */ 1863 } 1864 1865 if (isr & ISR_RXIDLE) { 1866 printf("%s: receive ring overrun\n", 1867 device_xname(&sc->sc_dev)); 1868 1869 /* Get the receive process going again. */ 1870 bus_space_write_4(sc->sc_st, sc->sc_sh, 1871 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1872 bus_space_write_4(sc->sc_st, sc->sc_sh, 1873 SIP_CR, CR_RXE); 1874 } 1875 } 1876 1877 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1878 #ifdef SIP_EVENT_COUNTERS 1879 if (isr & ISR_TXDESC) 1880 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1881 else if (isr & ISR_TXIDLE) 1882 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1883 #endif 1884 1885 /* Sweep up transmit descriptors. */ 1886 sipcom_txintr(sc); 1887 1888 if (isr & ISR_TXURN) { 1889 u_int32_t thresh; 1890 int txfifo_size = (sc->sc_gigabit) 1891 ? DP83820_SIP_TXFIFO_SIZE 1892 : OTHER_SIP_TXFIFO_SIZE; 1893 1894 printf("%s: transmit FIFO underrun", 1895 device_xname(&sc->sc_dev)); 1896 thresh = sc->sc_tx_drain_thresh + 1; 1897 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1898 && (thresh * 32) <= (txfifo_size - 1899 (sc->sc_tx_fill_thresh * 32))) { 1900 printf("; increasing Tx drain " 1901 "threshold to %u bytes\n", 1902 thresh * 32); 1903 sc->sc_tx_drain_thresh = thresh; 1904 (void) sipcom_init(ifp); 1905 } else { 1906 (void) sipcom_init(ifp); 1907 printf("\n"); 1908 } 1909 } 1910 } 1911 1912 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1913 if (isr & ISR_PAUSE_ST) { 1914 sc->sc_paused = 1; 1915 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1916 ifp->if_flags |= IFF_OACTIVE; 1917 } 1918 if (isr & ISR_PAUSE_END) { 1919 sc->sc_paused = 0; 1920 ifp->if_flags &= ~IFF_OACTIVE; 1921 } 1922 } 1923 1924 if (isr & ISR_HIBERR) { 1925 int want_init = 0; 1926 1927 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1928 1929 #define PRINTERR(bit, str) \ 1930 do { \ 1931 if ((isr & (bit)) != 0) { \ 1932 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1933 printf("%s: %s\n", \ 1934 device_xname(&sc->sc_dev), str); \ 1935 want_init = 1; \ 1936 } \ 1937 } while (/*CONSTCOND*/0) 1938 1939 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1940 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1941 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1942 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1943 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1944 /* 1945 * Ignore: 1946 * Tx reset complete 1947 * Rx reset complete 1948 */ 1949 if (want_init) 1950 (void) sipcom_init(ifp); 1951 #undef PRINTERR 1952 } 1953 } 1954 1955 /* Re-enable interrupts. */ 1956 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1957 1958 /* Try to get more packets going. */ 1959 sipcom_start(ifp); 1960 1961 return (handled); 1962 } 1963 1964 /* 1965 * sip_txintr: 1966 * 1967 * Helper; handle transmit interrupts. 1968 */ 1969 static void 1970 sipcom_txintr(struct sip_softc *sc) 1971 { 1972 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1973 struct sip_txsoft *txs; 1974 u_int32_t cmdsts; 1975 1976 if (sc->sc_paused == 0) 1977 ifp->if_flags &= ~IFF_OACTIVE; 1978 1979 /* 1980 * Go through our Tx list and free mbufs for those 1981 * frames which have been transmitted. 1982 */ 1983 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1984 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1985 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1986 1987 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1988 if (cmdsts & CMDSTS_OWN) 1989 break; 1990 1991 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1992 1993 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1994 1995 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1996 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1997 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1998 m_freem(txs->txs_mbuf); 1999 txs->txs_mbuf = NULL; 2000 2001 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2002 2003 /* 2004 * Check for errors and collisions. 2005 */ 2006 if (cmdsts & 2007 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2008 ifp->if_oerrors++; 2009 if (cmdsts & CMDSTS_Tx_EC) 2010 ifp->if_collisions += 16; 2011 if (ifp->if_flags & IFF_DEBUG) { 2012 if (cmdsts & CMDSTS_Tx_ED) 2013 printf("%s: excessive deferral\n", 2014 device_xname(&sc->sc_dev)); 2015 if (cmdsts & CMDSTS_Tx_EC) 2016 printf("%s: excessive collisions\n", 2017 device_xname(&sc->sc_dev)); 2018 } 2019 } else { 2020 /* Packet was transmitted successfully. */ 2021 ifp->if_opackets++; 2022 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2023 } 2024 } 2025 2026 /* 2027 * If there are no more pending transmissions, cancel the watchdog 2028 * timer. 2029 */ 2030 if (txs == NULL) { 2031 ifp->if_timer = 0; 2032 sc->sc_txwin = 0; 2033 } 2034 } 2035 2036 /* 2037 * gsip_rxintr: 2038 * 2039 * Helper; handle receive interrupts on gigabit parts. 2040 */ 2041 static void 2042 gsip_rxintr(struct sip_softc *sc) 2043 { 2044 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2045 struct sip_rxsoft *rxs; 2046 struct mbuf *m; 2047 u_int32_t cmdsts, extsts; 2048 int i, len; 2049 2050 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2051 rxs = &sc->sc_rxsoft[i]; 2052 2053 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2054 2055 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2056 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2057 len = CMDSTS_SIZE(sc, cmdsts); 2058 2059 /* 2060 * NOTE: OWN is set if owned by _consumer_. We're the 2061 * consumer of the receive ring, so if the bit is clear, 2062 * we have processed all of the packets. 2063 */ 2064 if ((cmdsts & CMDSTS_OWN) == 0) { 2065 /* 2066 * We have processed all of the receive buffers. 2067 */ 2068 break; 2069 } 2070 2071 if (__predict_false(sc->sc_rxdiscard)) { 2072 sip_init_rxdesc(sc, i); 2073 if ((cmdsts & CMDSTS_MORE) == 0) { 2074 /* Reset our state. */ 2075 sc->sc_rxdiscard = 0; 2076 } 2077 continue; 2078 } 2079 2080 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2081 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2082 2083 m = rxs->rxs_mbuf; 2084 2085 /* 2086 * Add a new receive buffer to the ring. 2087 */ 2088 if (sipcom_add_rxbuf(sc, i) != 0) { 2089 /* 2090 * Failed, throw away what we've done so 2091 * far, and discard the rest of the packet. 2092 */ 2093 ifp->if_ierrors++; 2094 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2095 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2096 sip_init_rxdesc(sc, i); 2097 if (cmdsts & CMDSTS_MORE) 2098 sc->sc_rxdiscard = 1; 2099 if (sc->sc_rxhead != NULL) 2100 m_freem(sc->sc_rxhead); 2101 sip_rxchain_reset(sc); 2102 continue; 2103 } 2104 2105 sip_rxchain_link(sc, m); 2106 2107 m->m_len = len; 2108 2109 /* 2110 * If this is not the end of the packet, keep 2111 * looking. 2112 */ 2113 if (cmdsts & CMDSTS_MORE) { 2114 sc->sc_rxlen += len; 2115 continue; 2116 } 2117 2118 /* 2119 * Okay, we have the entire packet now. The chip includes 2120 * the FCS, so we need to trim it. 2121 */ 2122 m->m_len -= ETHER_CRC_LEN; 2123 2124 *sc->sc_rxtailp = NULL; 2125 len = m->m_len + sc->sc_rxlen; 2126 m = sc->sc_rxhead; 2127 2128 sip_rxchain_reset(sc); 2129 2130 /* 2131 * If an error occurred, update stats and drop the packet. 2132 */ 2133 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2134 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2135 ifp->if_ierrors++; 2136 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2137 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2138 /* Receive overrun handled elsewhere. */ 2139 printf("%s: receive descriptor error\n", 2140 device_xname(&sc->sc_dev)); 2141 } 2142 #define PRINTERR(bit, str) \ 2143 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2144 (cmdsts & (bit)) != 0) \ 2145 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2146 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2147 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2148 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2149 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2150 #undef PRINTERR 2151 m_freem(m); 2152 continue; 2153 } 2154 2155 /* 2156 * If the packet is small enough to fit in a 2157 * single header mbuf, allocate one and copy 2158 * the data into it. This greatly reduces 2159 * memory consumption when we receive lots 2160 * of small packets. 2161 */ 2162 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2163 struct mbuf *nm; 2164 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2165 if (nm == NULL) { 2166 ifp->if_ierrors++; 2167 m_freem(m); 2168 continue; 2169 } 2170 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2171 nm->m_data += 2; 2172 nm->m_pkthdr.len = nm->m_len = len; 2173 m_copydata(m, 0, len, mtod(nm, void *)); 2174 m_freem(m); 2175 m = nm; 2176 } 2177 #ifndef __NO_STRICT_ALIGNMENT 2178 else { 2179 /* 2180 * The DP83820's receive buffers must be 4-byte 2181 * aligned. But this means that the data after 2182 * the Ethernet header is misaligned. To compensate, 2183 * we have artificially shortened the buffer size 2184 * in the descriptor, and we do an overlapping copy 2185 * of the data two bytes further in (in the first 2186 * buffer of the chain only). 2187 */ 2188 memmove(mtod(m, char *) + 2, mtod(m, void *), 2189 m->m_len); 2190 m->m_data += 2; 2191 } 2192 #endif /* ! __NO_STRICT_ALIGNMENT */ 2193 2194 /* 2195 * If VLANs are enabled, VLAN packets have been unwrapped 2196 * for us. Associate the tag with the packet. 2197 */ 2198 2199 /* 2200 * Again, byte swapping is tricky. Hardware provided 2201 * the tag in the network byte order, but extsts was 2202 * passed through le32toh() in the meantime. On a 2203 * big-endian machine, we need to swap it again. On a 2204 * little-endian machine, we need to convert from the 2205 * network to host byte order. This means that we must 2206 * swap it in any case, so unconditional swap instead 2207 * of htons() is used. 2208 */ 2209 if ((extsts & EXTSTS_VPKT) != 0) { 2210 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2211 continue); 2212 } 2213 2214 /* 2215 * Set the incoming checksum information for the 2216 * packet. 2217 */ 2218 if ((extsts & EXTSTS_IPPKT) != 0) { 2219 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2220 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2221 if (extsts & EXTSTS_Rx_IPERR) 2222 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2223 if (extsts & EXTSTS_TCPPKT) { 2224 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2225 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2226 if (extsts & EXTSTS_Rx_TCPERR) 2227 m->m_pkthdr.csum_flags |= 2228 M_CSUM_TCP_UDP_BAD; 2229 } else if (extsts & EXTSTS_UDPPKT) { 2230 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2231 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2232 if (extsts & EXTSTS_Rx_UDPERR) 2233 m->m_pkthdr.csum_flags |= 2234 M_CSUM_TCP_UDP_BAD; 2235 } 2236 } 2237 2238 ifp->if_ipackets++; 2239 m->m_pkthdr.rcvif = ifp; 2240 m->m_pkthdr.len = len; 2241 2242 #if NBPFILTER > 0 2243 /* 2244 * Pass this up to any BPF listeners, but only 2245 * pass if up the stack if it's for us. 2246 */ 2247 if (ifp->if_bpf) 2248 bpf_mtap(ifp->if_bpf, m); 2249 #endif /* NBPFILTER > 0 */ 2250 2251 /* Pass it on. */ 2252 (*ifp->if_input)(ifp, m); 2253 } 2254 2255 /* Update the receive pointer. */ 2256 sc->sc_rxptr = i; 2257 } 2258 2259 /* 2260 * sip_rxintr: 2261 * 2262 * Helper; handle receive interrupts on 10/100 parts. 2263 */ 2264 static void 2265 sip_rxintr(struct sip_softc *sc) 2266 { 2267 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2268 struct sip_rxsoft *rxs; 2269 struct mbuf *m; 2270 u_int32_t cmdsts; 2271 int i, len; 2272 2273 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2274 rxs = &sc->sc_rxsoft[i]; 2275 2276 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2277 2278 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2279 2280 /* 2281 * NOTE: OWN is set if owned by _consumer_. We're the 2282 * consumer of the receive ring, so if the bit is clear, 2283 * we have processed all of the packets. 2284 */ 2285 if ((cmdsts & CMDSTS_OWN) == 0) { 2286 /* 2287 * We have processed all of the receive buffers. 2288 */ 2289 break; 2290 } 2291 2292 /* 2293 * If any collisions were seen on the wire, count one. 2294 */ 2295 if (cmdsts & CMDSTS_Rx_COL) 2296 ifp->if_collisions++; 2297 2298 /* 2299 * If an error occurred, update stats, clear the status 2300 * word, and leave the packet buffer in place. It will 2301 * simply be reused the next time the ring comes around. 2302 */ 2303 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2304 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2305 ifp->if_ierrors++; 2306 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2307 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2308 /* Receive overrun handled elsewhere. */ 2309 printf("%s: receive descriptor error\n", 2310 device_xname(&sc->sc_dev)); 2311 } 2312 #define PRINTERR(bit, str) \ 2313 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2314 (cmdsts & (bit)) != 0) \ 2315 printf("%s: %s\n", device_xname(&sc->sc_dev), str) 2316 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2317 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2318 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2319 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2320 #undef PRINTERR 2321 sip_init_rxdesc(sc, i); 2322 continue; 2323 } 2324 2325 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2326 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2327 2328 /* 2329 * No errors; receive the packet. Note, the SiS 900 2330 * includes the CRC with every packet. 2331 */ 2332 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2333 2334 #ifdef __NO_STRICT_ALIGNMENT 2335 /* 2336 * If the packet is small enough to fit in a 2337 * single header mbuf, allocate one and copy 2338 * the data into it. This greatly reduces 2339 * memory consumption when we receive lots 2340 * of small packets. 2341 * 2342 * Otherwise, we add a new buffer to the receive 2343 * chain. If this fails, we drop the packet and 2344 * recycle the old buffer. 2345 */ 2346 if (sip_copy_small != 0 && len <= MHLEN) { 2347 MGETHDR(m, M_DONTWAIT, MT_DATA); 2348 if (m == NULL) 2349 goto dropit; 2350 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2351 memcpy(mtod(m, void *), 2352 mtod(rxs->rxs_mbuf, void *), len); 2353 sip_init_rxdesc(sc, i); 2354 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2355 rxs->rxs_dmamap->dm_mapsize, 2356 BUS_DMASYNC_PREREAD); 2357 } else { 2358 m = rxs->rxs_mbuf; 2359 if (sipcom_add_rxbuf(sc, i) != 0) { 2360 dropit: 2361 ifp->if_ierrors++; 2362 sip_init_rxdesc(sc, i); 2363 bus_dmamap_sync(sc->sc_dmat, 2364 rxs->rxs_dmamap, 0, 2365 rxs->rxs_dmamap->dm_mapsize, 2366 BUS_DMASYNC_PREREAD); 2367 continue; 2368 } 2369 } 2370 #else 2371 /* 2372 * The SiS 900's receive buffers must be 4-byte aligned. 2373 * But this means that the data after the Ethernet header 2374 * is misaligned. We must allocate a new buffer and 2375 * copy the data, shifted forward 2 bytes. 2376 */ 2377 MGETHDR(m, M_DONTWAIT, MT_DATA); 2378 if (m == NULL) { 2379 dropit: 2380 ifp->if_ierrors++; 2381 sip_init_rxdesc(sc, i); 2382 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2383 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2384 continue; 2385 } 2386 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2387 if (len > (MHLEN - 2)) { 2388 MCLGET(m, M_DONTWAIT); 2389 if ((m->m_flags & M_EXT) == 0) { 2390 m_freem(m); 2391 goto dropit; 2392 } 2393 } 2394 m->m_data += 2; 2395 2396 /* 2397 * Note that we use clusters for incoming frames, so the 2398 * buffer is virtually contiguous. 2399 */ 2400 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2401 2402 /* Allow the receive descriptor to continue using its mbuf. */ 2403 sip_init_rxdesc(sc, i); 2404 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2405 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2406 #endif /* __NO_STRICT_ALIGNMENT */ 2407 2408 ifp->if_ipackets++; 2409 m->m_pkthdr.rcvif = ifp; 2410 m->m_pkthdr.len = m->m_len = len; 2411 2412 #if NBPFILTER > 0 2413 /* 2414 * Pass this up to any BPF listeners, but only 2415 * pass if up the stack if it's for us. 2416 */ 2417 if (ifp->if_bpf) 2418 bpf_mtap(ifp->if_bpf, m); 2419 #endif /* NBPFILTER > 0 */ 2420 2421 /* Pass it on. */ 2422 (*ifp->if_input)(ifp, m); 2423 } 2424 2425 /* Update the receive pointer. */ 2426 sc->sc_rxptr = i; 2427 } 2428 2429 /* 2430 * sip_tick: 2431 * 2432 * One second timer, used to tick the MII. 2433 */ 2434 static void 2435 sipcom_tick(void *arg) 2436 { 2437 struct sip_softc *sc = arg; 2438 int s; 2439 2440 s = splnet(); 2441 #ifdef SIP_EVENT_COUNTERS 2442 if (sc->sc_gigabit) { 2443 /* Read PAUSE related counts from MIB registers. */ 2444 sc->sc_ev_rxpause.ev_count += 2445 bus_space_read_4(sc->sc_st, sc->sc_sh, 2446 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2447 sc->sc_ev_txpause.ev_count += 2448 bus_space_read_4(sc->sc_st, sc->sc_sh, 2449 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2450 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2451 } 2452 #endif /* SIP_EVENT_COUNTERS */ 2453 mii_tick(&sc->sc_mii); 2454 splx(s); 2455 2456 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2457 } 2458 2459 /* 2460 * sip_reset: 2461 * 2462 * Perform a soft reset on the SiS 900. 2463 */ 2464 static bool 2465 sipcom_reset(struct sip_softc *sc) 2466 { 2467 bus_space_tag_t st = sc->sc_st; 2468 bus_space_handle_t sh = sc->sc_sh; 2469 int i; 2470 2471 bus_space_write_4(st, sh, SIP_IER, 0); 2472 bus_space_write_4(st, sh, SIP_IMR, 0); 2473 bus_space_write_4(st, sh, SIP_RFCR, 0); 2474 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2475 2476 for (i = 0; i < SIP_TIMEOUT; i++) { 2477 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2478 break; 2479 delay(2); 2480 } 2481 2482 if (i == SIP_TIMEOUT) { 2483 printf("%s: reset failed to complete\n", device_xname(&sc->sc_dev)); 2484 return false; 2485 } 2486 2487 delay(1000); 2488 2489 if (sc->sc_gigabit) { 2490 /* 2491 * Set the general purpose I/O bits. Do it here in case we 2492 * need to have GPIO set up to talk to the media interface. 2493 */ 2494 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2495 delay(1000); 2496 } 2497 return true; 2498 } 2499 2500 static void 2501 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2502 { 2503 u_int32_t reg; 2504 bus_space_tag_t st = sc->sc_st; 2505 bus_space_handle_t sh = sc->sc_sh; 2506 /* 2507 * Initialize the VLAN/IP receive control register. 2508 * We enable checksum computation on all incoming 2509 * packets, and do not reject packets w/ bad checksums. 2510 */ 2511 reg = 0; 2512 if (capenable & 2513 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2514 reg |= VRCR_IPEN; 2515 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2516 reg |= VRCR_VTDEN|VRCR_VTREN; 2517 bus_space_write_4(st, sh, SIP_VRCR, reg); 2518 2519 /* 2520 * Initialize the VLAN/IP transmit control register. 2521 * We enable outgoing checksum computation on a 2522 * per-packet basis. 2523 */ 2524 reg = 0; 2525 if (capenable & 2526 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2527 reg |= VTCR_PPCHK; 2528 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2529 reg |= VTCR_VPPTI; 2530 bus_space_write_4(st, sh, SIP_VTCR, reg); 2531 2532 /* 2533 * If we're using VLANs, initialize the VLAN data register. 2534 * To understand why we bswap the VLAN Ethertype, see section 2535 * 4.2.36 of the DP83820 manual. 2536 */ 2537 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2538 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2539 } 2540 2541 /* 2542 * sip_init: [ ifnet interface function ] 2543 * 2544 * Initialize the interface. Must be called at splnet(). 2545 */ 2546 static int 2547 sipcom_init(struct ifnet *ifp) 2548 { 2549 struct sip_softc *sc = ifp->if_softc; 2550 bus_space_tag_t st = sc->sc_st; 2551 bus_space_handle_t sh = sc->sc_sh; 2552 struct sip_txsoft *txs; 2553 struct sip_rxsoft *rxs; 2554 struct sip_desc *sipd; 2555 int i, error = 0; 2556 2557 if (device_is_active(&sc->sc_dev)) { 2558 /* 2559 * Cancel any pending I/O. 2560 */ 2561 sipcom_stop(ifp, 0); 2562 } else if (!pmf_device_resume_self(&sc->sc_dev)) 2563 return 0; 2564 2565 /* 2566 * Reset the chip to a known state. 2567 */ 2568 if (!sipcom_reset(sc)) 2569 return EBUSY; 2570 2571 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2572 /* 2573 * DP83815 manual, page 78: 2574 * 4.4 Recommended Registers Configuration 2575 * For optimum performance of the DP83815, version noted 2576 * as DP83815CVNG (SRR = 203h), the listed register 2577 * modifications must be followed in sequence... 2578 * 2579 * It's not clear if this should be 302h or 203h because that 2580 * chip name is listed as SRR 302h in the description of the 2581 * SRR register. However, my revision 302h DP83815 on the 2582 * Netgear FA311 purchased in 02/2001 needs these settings 2583 * to avoid tons of errors in AcceptPerfectMatch (non- 2584 * IFF_PROMISC) mode. I do not know if other revisions need 2585 * this set or not. [briggs -- 09 March 2001] 2586 * 2587 * Note that only the low-order 12 bits of 0xe4 are documented 2588 * and that this sets reserved bits in that register. 2589 */ 2590 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2591 2592 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2593 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2594 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2595 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2596 2597 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2598 } 2599 2600 /* 2601 * Initialize the transmit descriptor ring. 2602 */ 2603 for (i = 0; i < sc->sc_ntxdesc; i++) { 2604 sipd = &sc->sc_txdescs[i]; 2605 memset(sipd, 0, sizeof(struct sip_desc)); 2606 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2607 } 2608 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2609 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2610 sc->sc_txfree = sc->sc_ntxdesc; 2611 sc->sc_txnext = 0; 2612 sc->sc_txwin = 0; 2613 2614 /* 2615 * Initialize the transmit job descriptors. 2616 */ 2617 SIMPLEQ_INIT(&sc->sc_txfreeq); 2618 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2619 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2620 txs = &sc->sc_txsoft[i]; 2621 txs->txs_mbuf = NULL; 2622 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2623 } 2624 2625 /* 2626 * Initialize the receive descriptor and receive job 2627 * descriptor rings. 2628 */ 2629 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2630 rxs = &sc->sc_rxsoft[i]; 2631 if (rxs->rxs_mbuf == NULL) { 2632 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2633 printf("%s: unable to allocate or map rx " 2634 "buffer %d, error = %d\n", 2635 device_xname(&sc->sc_dev), i, error); 2636 /* 2637 * XXX Should attempt to run with fewer receive 2638 * XXX buffers instead of just failing. 2639 */ 2640 sipcom_rxdrain(sc); 2641 goto out; 2642 } 2643 } else 2644 sip_init_rxdesc(sc, i); 2645 } 2646 sc->sc_rxptr = 0; 2647 sc->sc_rxdiscard = 0; 2648 sip_rxchain_reset(sc); 2649 2650 /* 2651 * Set the configuration register; it's already initialized 2652 * in sip_attach(). 2653 */ 2654 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2655 2656 /* 2657 * Initialize the prototype TXCFG register. 2658 */ 2659 if (sc->sc_gigabit) { 2660 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2661 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2662 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2663 SIP_SIS900_REV(sc, SIS_REV_960) || 2664 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2665 (sc->sc_cfg & CFG_EDBMASTEN)) { 2666 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2667 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2668 } else { 2669 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2670 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2671 } 2672 2673 sc->sc_txcfg |= TXCFG_ATP | 2674 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2675 sc->sc_tx_drain_thresh; 2676 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2677 2678 /* 2679 * Initialize the receive drain threshold if we have never 2680 * done so. 2681 */ 2682 if (sc->sc_rx_drain_thresh == 0) { 2683 /* 2684 * XXX This value should be tuned. This is set to the 2685 * maximum of 248 bytes, and we may be able to improve 2686 * performance by decreasing it (although we should never 2687 * set this value lower than 2; 14 bytes are required to 2688 * filter the packet). 2689 */ 2690 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2691 } 2692 2693 /* 2694 * Initialize the prototype RXCFG register. 2695 */ 2696 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2697 /* 2698 * Accept long packets (including FCS) so we can handle 2699 * 802.1q-tagged frames and jumbo frames properly. 2700 */ 2701 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2702 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2703 sc->sc_rxcfg |= RXCFG_ALP; 2704 2705 /* 2706 * Checksum offloading is disabled if the user selects an MTU 2707 * larger than 8109. (FreeBSD says 8152, but there is emperical 2708 * evidence that >8109 does not work on some boards, such as the 2709 * Planex GN-1000TE). 2710 */ 2711 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2712 (ifp->if_capenable & 2713 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2714 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2715 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2716 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2717 "disabled.\n", device_xname(&sc->sc_dev)); 2718 ifp->if_capenable &= 2719 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2720 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2721 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2722 ifp->if_csum_flags_tx = 0; 2723 ifp->if_csum_flags_rx = 0; 2724 } 2725 2726 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2727 2728 if (sc->sc_gigabit) 2729 sipcom_dp83820_init(sc, ifp->if_capenable); 2730 2731 /* 2732 * Give the transmit and receive rings to the chip. 2733 */ 2734 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2735 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2736 2737 /* 2738 * Initialize the interrupt mask. 2739 */ 2740 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2741 sc->sc_bits.b_isr_sserr | 2742 sc->sc_bits.b_isr_rmabt | 2743 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2744 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2745 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2746 2747 /* Set up the receive filter. */ 2748 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2749 2750 /* 2751 * Tune sc_rx_flow_thresh. 2752 * XXX "More than 8KB" is too short for jumbo frames. 2753 * XXX TODO: Threshold value should be user-settable. 2754 */ 2755 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2756 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2757 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2758 2759 /* 2760 * Set the current media. Do this after initializing the prototype 2761 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2762 * control. 2763 */ 2764 if ((error = ether_mediachange(ifp)) != 0) 2765 goto out; 2766 2767 /* 2768 * Set the interrupt hold-off timer to 100us. 2769 */ 2770 if (sc->sc_gigabit) 2771 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2772 2773 /* 2774 * Enable interrupts. 2775 */ 2776 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2777 2778 /* 2779 * Start the transmit and receive processes. 2780 */ 2781 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2782 2783 /* 2784 * Start the one second MII clock. 2785 */ 2786 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2787 2788 /* 2789 * ...all done! 2790 */ 2791 ifp->if_flags |= IFF_RUNNING; 2792 ifp->if_flags &= ~IFF_OACTIVE; 2793 sc->sc_if_flags = ifp->if_flags; 2794 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2795 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2796 sc->sc_prev.if_capenable = ifp->if_capenable; 2797 2798 out: 2799 if (error) 2800 printf("%s: interface not running\n", device_xname(&sc->sc_dev)); 2801 return (error); 2802 } 2803 2804 /* 2805 * sip_drain: 2806 * 2807 * Drain the receive queue. 2808 */ 2809 static void 2810 sipcom_rxdrain(struct sip_softc *sc) 2811 { 2812 struct sip_rxsoft *rxs; 2813 int i; 2814 2815 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2816 rxs = &sc->sc_rxsoft[i]; 2817 if (rxs->rxs_mbuf != NULL) { 2818 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2819 m_freem(rxs->rxs_mbuf); 2820 rxs->rxs_mbuf = NULL; 2821 } 2822 } 2823 } 2824 2825 /* 2826 * sip_stop: [ ifnet interface function ] 2827 * 2828 * Stop transmission on the interface. 2829 */ 2830 static void 2831 sipcom_stop(struct ifnet *ifp, int disable) 2832 { 2833 struct sip_softc *sc = ifp->if_softc; 2834 bus_space_tag_t st = sc->sc_st; 2835 bus_space_handle_t sh = sc->sc_sh; 2836 struct sip_txsoft *txs; 2837 u_int32_t cmdsts = 0; /* DEBUG */ 2838 2839 /* 2840 * Stop the one second clock. 2841 */ 2842 callout_stop(&sc->sc_tick_ch); 2843 2844 /* Down the MII. */ 2845 mii_down(&sc->sc_mii); 2846 2847 /* 2848 * Disable interrupts. 2849 */ 2850 bus_space_write_4(st, sh, SIP_IER, 0); 2851 2852 /* 2853 * Stop receiver and transmitter. 2854 */ 2855 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2856 2857 /* 2858 * Release any queued transmit buffers. 2859 */ 2860 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2861 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2862 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2863 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2864 CMDSTS_INTR) == 0) 2865 printf("%s: sip_stop: last descriptor does not " 2866 "have INTR bit set\n", device_xname(&sc->sc_dev)); 2867 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2868 #ifdef DIAGNOSTIC 2869 if (txs->txs_mbuf == NULL) { 2870 printf("%s: dirty txsoft with no mbuf chain\n", 2871 device_xname(&sc->sc_dev)); 2872 panic("sip_stop"); 2873 } 2874 #endif 2875 cmdsts |= /* DEBUG */ 2876 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2877 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2878 m_freem(txs->txs_mbuf); 2879 txs->txs_mbuf = NULL; 2880 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2881 } 2882 2883 /* 2884 * Mark the interface down and cancel the watchdog timer. 2885 */ 2886 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2887 ifp->if_timer = 0; 2888 2889 if (disable) 2890 pmf_device_suspend_self(&sc->sc_dev); 2891 2892 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2893 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2894 printf("%s: sip_stop: no INTR bits set in dirty tx " 2895 "descriptors\n", device_xname(&sc->sc_dev)); 2896 } 2897 2898 /* 2899 * sip_read_eeprom: 2900 * 2901 * Read data from the serial EEPROM. 2902 */ 2903 static void 2904 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2905 u_int16_t *data) 2906 { 2907 bus_space_tag_t st = sc->sc_st; 2908 bus_space_handle_t sh = sc->sc_sh; 2909 u_int16_t reg; 2910 int i, x; 2911 2912 for (i = 0; i < wordcnt; i++) { 2913 /* Send CHIP SELECT. */ 2914 reg = EROMAR_EECS; 2915 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2916 2917 /* Shift in the READ opcode. */ 2918 for (x = 3; x > 0; x--) { 2919 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2920 reg |= EROMAR_EEDI; 2921 else 2922 reg &= ~EROMAR_EEDI; 2923 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2924 bus_space_write_4(st, sh, SIP_EROMAR, 2925 reg | EROMAR_EESK); 2926 delay(4); 2927 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2928 delay(4); 2929 } 2930 2931 /* Shift in address. */ 2932 for (x = 6; x > 0; x--) { 2933 if ((word + i) & (1 << (x - 1))) 2934 reg |= EROMAR_EEDI; 2935 else 2936 reg &= ~EROMAR_EEDI; 2937 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2938 bus_space_write_4(st, sh, SIP_EROMAR, 2939 reg | EROMAR_EESK); 2940 delay(4); 2941 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2942 delay(4); 2943 } 2944 2945 /* Shift out data. */ 2946 reg = EROMAR_EECS; 2947 data[i] = 0; 2948 for (x = 16; x > 0; x--) { 2949 bus_space_write_4(st, sh, SIP_EROMAR, 2950 reg | EROMAR_EESK); 2951 delay(4); 2952 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2953 data[i] |= (1 << (x - 1)); 2954 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2955 delay(4); 2956 } 2957 2958 /* Clear CHIP SELECT. */ 2959 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2960 delay(4); 2961 } 2962 } 2963 2964 /* 2965 * sipcom_add_rxbuf: 2966 * 2967 * Add a receive buffer to the indicated descriptor. 2968 */ 2969 static int 2970 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2971 { 2972 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2973 struct mbuf *m; 2974 int error; 2975 2976 MGETHDR(m, M_DONTWAIT, MT_DATA); 2977 if (m == NULL) 2978 return (ENOBUFS); 2979 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2980 2981 MCLGET(m, M_DONTWAIT); 2982 if ((m->m_flags & M_EXT) == 0) { 2983 m_freem(m); 2984 return (ENOBUFS); 2985 } 2986 2987 /* XXX I don't believe this is necessary. --dyoung */ 2988 if (sc->sc_gigabit) 2989 m->m_len = sc->sc_parm->p_rxbuf_len; 2990 2991 if (rxs->rxs_mbuf != NULL) 2992 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2993 2994 rxs->rxs_mbuf = m; 2995 2996 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2997 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2998 BUS_DMA_READ|BUS_DMA_NOWAIT); 2999 if (error) { 3000 printf("%s: can't load rx DMA map %d, error = %d\n", 3001 device_xname(&sc->sc_dev), idx, error); 3002 panic("%s", __func__); /* XXX */ 3003 } 3004 3005 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3006 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3007 3008 sip_init_rxdesc(sc, idx); 3009 3010 return (0); 3011 } 3012 3013 /* 3014 * sip_sis900_set_filter: 3015 * 3016 * Set up the receive filter. 3017 */ 3018 static void 3019 sipcom_sis900_set_filter(struct sip_softc *sc) 3020 { 3021 bus_space_tag_t st = sc->sc_st; 3022 bus_space_handle_t sh = sc->sc_sh; 3023 struct ethercom *ec = &sc->sc_ethercom; 3024 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3025 struct ether_multi *enm; 3026 const u_int8_t *cp; 3027 struct ether_multistep step; 3028 u_int32_t crc, mchash[16]; 3029 3030 /* 3031 * Initialize the prototype RFCR. 3032 */ 3033 sc->sc_rfcr = RFCR_RFEN; 3034 if (ifp->if_flags & IFF_BROADCAST) 3035 sc->sc_rfcr |= RFCR_AAB; 3036 if (ifp->if_flags & IFF_PROMISC) { 3037 sc->sc_rfcr |= RFCR_AAP; 3038 goto allmulti; 3039 } 3040 3041 /* 3042 * Set up the multicast address filter by passing all multicast 3043 * addresses through a CRC generator, and then using the high-order 3044 * 6 bits as an index into the 128 bit multicast hash table (only 3045 * the lower 16 bits of each 32 bit multicast hash register are 3046 * valid). The high order bits select the register, while the 3047 * rest of the bits select the bit within the register. 3048 */ 3049 3050 memset(mchash, 0, sizeof(mchash)); 3051 3052 /* 3053 * SiS900 (at least SiS963) requires us to register the address of 3054 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3055 */ 3056 crc = 0x0ed423f9; 3057 3058 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3059 SIP_SIS900_REV(sc, SIS_REV_960) || 3060 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3061 /* Just want the 8 most significant bits. */ 3062 crc >>= 24; 3063 } else { 3064 /* Just want the 7 most significant bits. */ 3065 crc >>= 25; 3066 } 3067 3068 /* Set the corresponding bit in the hash table. */ 3069 mchash[crc >> 4] |= 1 << (crc & 0xf); 3070 3071 ETHER_FIRST_MULTI(step, ec, enm); 3072 while (enm != NULL) { 3073 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3074 /* 3075 * We must listen to a range of multicast addresses. 3076 * For now, just accept all multicasts, rather than 3077 * trying to set only those filter bits needed to match 3078 * the range. (At this time, the only use of address 3079 * ranges is for IP multicast routing, for which the 3080 * range is big enough to require all bits set.) 3081 */ 3082 goto allmulti; 3083 } 3084 3085 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3086 3087 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3088 SIP_SIS900_REV(sc, SIS_REV_960) || 3089 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3090 /* Just want the 8 most significant bits. */ 3091 crc >>= 24; 3092 } else { 3093 /* Just want the 7 most significant bits. */ 3094 crc >>= 25; 3095 } 3096 3097 /* Set the corresponding bit in the hash table. */ 3098 mchash[crc >> 4] |= 1 << (crc & 0xf); 3099 3100 ETHER_NEXT_MULTI(step, enm); 3101 } 3102 3103 ifp->if_flags &= ~IFF_ALLMULTI; 3104 goto setit; 3105 3106 allmulti: 3107 ifp->if_flags |= IFF_ALLMULTI; 3108 sc->sc_rfcr |= RFCR_AAM; 3109 3110 setit: 3111 #define FILTER_EMIT(addr, data) \ 3112 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3113 delay(1); \ 3114 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3115 delay(1) 3116 3117 /* 3118 * Disable receive filter, and program the node address. 3119 */ 3120 cp = CLLADDR(ifp->if_sadl); 3121 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3122 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3123 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3124 3125 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3126 /* 3127 * Program the multicast hash table. 3128 */ 3129 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3130 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3131 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3132 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3133 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3134 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3135 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3136 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3137 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3138 SIP_SIS900_REV(sc, SIS_REV_960) || 3139 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3140 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3141 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3142 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3143 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3144 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3145 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3146 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3147 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3148 } 3149 } 3150 #undef FILTER_EMIT 3151 3152 /* 3153 * Re-enable the receiver filter. 3154 */ 3155 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3156 } 3157 3158 /* 3159 * sip_dp83815_set_filter: 3160 * 3161 * Set up the receive filter. 3162 */ 3163 static void 3164 sipcom_dp83815_set_filter(struct sip_softc *sc) 3165 { 3166 bus_space_tag_t st = sc->sc_st; 3167 bus_space_handle_t sh = sc->sc_sh; 3168 struct ethercom *ec = &sc->sc_ethercom; 3169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3170 struct ether_multi *enm; 3171 const u_int8_t *cp; 3172 struct ether_multistep step; 3173 u_int32_t crc, hash, slot, bit; 3174 #define MCHASH_NWORDS_83820 128 3175 #define MCHASH_NWORDS_83815 32 3176 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3177 u_int16_t mchash[MCHASH_NWORDS]; 3178 int i; 3179 3180 /* 3181 * Initialize the prototype RFCR. 3182 * Enable the receive filter, and accept on 3183 * Perfect (destination address) Match 3184 * If IFF_BROADCAST, also accept all broadcast packets. 3185 * If IFF_PROMISC, accept all unicast packets (and later, set 3186 * IFF_ALLMULTI and accept all multicast, too). 3187 */ 3188 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3189 if (ifp->if_flags & IFF_BROADCAST) 3190 sc->sc_rfcr |= RFCR_AAB; 3191 if (ifp->if_flags & IFF_PROMISC) { 3192 sc->sc_rfcr |= RFCR_AAP; 3193 goto allmulti; 3194 } 3195 3196 /* 3197 * Set up the DP83820/DP83815 multicast address filter by 3198 * passing all multicast addresses through a CRC generator, 3199 * and then using the high-order 11/9 bits as an index into 3200 * the 2048/512 bit multicast hash table. The high-order 3201 * 7/5 bits select the slot, while the low-order 4 bits 3202 * select the bit within the slot. Note that only the low 3203 * 16-bits of each filter word are used, and there are 3204 * 128/32 filter words. 3205 */ 3206 3207 memset(mchash, 0, sizeof(mchash)); 3208 3209 ifp->if_flags &= ~IFF_ALLMULTI; 3210 ETHER_FIRST_MULTI(step, ec, enm); 3211 if (enm == NULL) 3212 goto setit; 3213 while (enm != NULL) { 3214 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3215 /* 3216 * We must listen to a range of multicast addresses. 3217 * For now, just accept all multicasts, rather than 3218 * trying to set only those filter bits needed to match 3219 * the range. (At this time, the only use of address 3220 * ranges is for IP multicast routing, for which the 3221 * range is big enough to require all bits set.) 3222 */ 3223 goto allmulti; 3224 } 3225 3226 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3227 3228 if (sc->sc_gigabit) { 3229 /* Just want the 11 most significant bits. */ 3230 hash = crc >> 21; 3231 } else { 3232 /* Just want the 9 most significant bits. */ 3233 hash = crc >> 23; 3234 } 3235 3236 slot = hash >> 4; 3237 bit = hash & 0xf; 3238 3239 /* Set the corresponding bit in the hash table. */ 3240 mchash[slot] |= 1 << bit; 3241 3242 ETHER_NEXT_MULTI(step, enm); 3243 } 3244 sc->sc_rfcr |= RFCR_MHEN; 3245 goto setit; 3246 3247 allmulti: 3248 ifp->if_flags |= IFF_ALLMULTI; 3249 sc->sc_rfcr |= RFCR_AAM; 3250 3251 setit: 3252 #define FILTER_EMIT(addr, data) \ 3253 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3254 delay(1); \ 3255 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3256 delay(1) 3257 3258 /* 3259 * Disable receive filter, and program the node address. 3260 */ 3261 cp = CLLADDR(ifp->if_sadl); 3262 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3263 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3264 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3265 3266 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3267 int nwords = 3268 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3269 /* 3270 * Program the multicast hash table. 3271 */ 3272 for (i = 0; i < nwords; i++) { 3273 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3274 } 3275 } 3276 #undef FILTER_EMIT 3277 #undef MCHASH_NWORDS 3278 #undef MCHASH_NWORDS_83815 3279 #undef MCHASH_NWORDS_83820 3280 3281 /* 3282 * Re-enable the receiver filter. 3283 */ 3284 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3285 } 3286 3287 /* 3288 * sip_dp83820_mii_readreg: [mii interface function] 3289 * 3290 * Read a PHY register on the MII of the DP83820. 3291 */ 3292 static int 3293 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3294 { 3295 struct sip_softc *sc = device_private(self); 3296 3297 if (sc->sc_cfg & CFG_TBI_EN) { 3298 bus_addr_t tbireg; 3299 int rv; 3300 3301 if (phy != 0) 3302 return (0); 3303 3304 switch (reg) { 3305 case MII_BMCR: tbireg = SIP_TBICR; break; 3306 case MII_BMSR: tbireg = SIP_TBISR; break; 3307 case MII_ANAR: tbireg = SIP_TANAR; break; 3308 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3309 case MII_ANER: tbireg = SIP_TANER; break; 3310 case MII_EXTSR: 3311 /* 3312 * Don't even bother reading the TESR register. 3313 * The manual documents that the device has 3314 * 1000baseX full/half capability, but the 3315 * register itself seems read back 0 on some 3316 * boards. Just hard-code the result. 3317 */ 3318 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3319 3320 default: 3321 return (0); 3322 } 3323 3324 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3325 if (tbireg == SIP_TBISR) { 3326 /* LINK and ACOMP are switched! */ 3327 int val = rv; 3328 3329 rv = 0; 3330 if (val & TBISR_MR_LINK_STATUS) 3331 rv |= BMSR_LINK; 3332 if (val & TBISR_MR_AN_COMPLETE) 3333 rv |= BMSR_ACOMP; 3334 3335 /* 3336 * The manual claims this register reads back 0 3337 * on hard and soft reset. But we want to let 3338 * the gentbi driver know that we support auto- 3339 * negotiation, so hard-code this bit in the 3340 * result. 3341 */ 3342 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3343 } 3344 3345 return (rv); 3346 } 3347 3348 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3349 } 3350 3351 /* 3352 * sip_dp83820_mii_writereg: [mii interface function] 3353 * 3354 * Write a PHY register on the MII of the DP83820. 3355 */ 3356 static void 3357 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3358 { 3359 struct sip_softc *sc = device_private(self); 3360 3361 if (sc->sc_cfg & CFG_TBI_EN) { 3362 bus_addr_t tbireg; 3363 3364 if (phy != 0) 3365 return; 3366 3367 switch (reg) { 3368 case MII_BMCR: tbireg = SIP_TBICR; break; 3369 case MII_ANAR: tbireg = SIP_TANAR; break; 3370 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3371 default: 3372 return; 3373 } 3374 3375 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3376 return; 3377 } 3378 3379 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3380 } 3381 3382 /* 3383 * sip_dp83820_mii_statchg: [mii interface function] 3384 * 3385 * Callback from MII layer when media changes. 3386 */ 3387 static void 3388 sipcom_dp83820_mii_statchg(device_t self) 3389 { 3390 struct sip_softc *sc = device_private(self); 3391 struct mii_data *mii = &sc->sc_mii; 3392 u_int32_t cfg, pcr; 3393 3394 /* 3395 * Get flow control negotiation result. 3396 */ 3397 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3398 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3399 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3400 mii->mii_media_active &= ~IFM_ETH_FMASK; 3401 } 3402 3403 /* 3404 * Update TXCFG for full-duplex operation. 3405 */ 3406 if ((mii->mii_media_active & IFM_FDX) != 0) 3407 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3408 else 3409 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3410 3411 /* 3412 * Update RXCFG for full-duplex or loopback. 3413 */ 3414 if ((mii->mii_media_active & IFM_FDX) != 0 || 3415 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3416 sc->sc_rxcfg |= RXCFG_ATX; 3417 else 3418 sc->sc_rxcfg &= ~RXCFG_ATX; 3419 3420 /* 3421 * Update CFG for MII/GMII. 3422 */ 3423 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3424 cfg = sc->sc_cfg | CFG_MODE_1000; 3425 else 3426 cfg = sc->sc_cfg; 3427 3428 /* 3429 * 802.3x flow control. 3430 */ 3431 pcr = 0; 3432 if (sc->sc_flowflags & IFM_FLOW) { 3433 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3434 pcr |= sc->sc_rx_flow_thresh; 3435 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3436 pcr |= PCR_PSEN | PCR_PS_MCAST; 3437 } 3438 3439 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3440 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3441 sc->sc_txcfg); 3442 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3443 sc->sc_rxcfg); 3444 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3445 } 3446 3447 /* 3448 * sip_mii_bitbang_read: [mii bit-bang interface function] 3449 * 3450 * Read the MII serial port for the MII bit-bang module. 3451 */ 3452 static u_int32_t 3453 sipcom_mii_bitbang_read(device_t self) 3454 { 3455 struct sip_softc *sc = device_private(self); 3456 3457 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3458 } 3459 3460 /* 3461 * sip_mii_bitbang_write: [mii big-bang interface function] 3462 * 3463 * Write the MII serial port for the MII bit-bang module. 3464 */ 3465 static void 3466 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3467 { 3468 struct sip_softc *sc = device_private(self); 3469 3470 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3471 } 3472 3473 /* 3474 * sip_sis900_mii_readreg: [mii interface function] 3475 * 3476 * Read a PHY register on the MII. 3477 */ 3478 static int 3479 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3480 { 3481 struct sip_softc *sc = device_private(self); 3482 u_int32_t enphy; 3483 3484 /* 3485 * The PHY of recent SiS chipsets is accessed through bitbang 3486 * operations. 3487 */ 3488 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3489 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3490 phy, reg); 3491 3492 #ifndef SIS900_MII_RESTRICT 3493 /* 3494 * The SiS 900 has only an internal PHY on the MII. Only allow 3495 * MII address 0. 3496 */ 3497 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3498 return (0); 3499 #endif 3500 3501 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3502 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3503 ENPHY_RWCMD | ENPHY_ACCESS); 3504 do { 3505 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3506 } while (enphy & ENPHY_ACCESS); 3507 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3508 } 3509 3510 /* 3511 * sip_sis900_mii_writereg: [mii interface function] 3512 * 3513 * Write a PHY register on the MII. 3514 */ 3515 static void 3516 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3517 { 3518 struct sip_softc *sc = device_private(self); 3519 u_int32_t enphy; 3520 3521 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3522 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3523 phy, reg, val); 3524 return; 3525 } 3526 3527 #ifndef SIS900_MII_RESTRICT 3528 /* 3529 * The SiS 900 has only an internal PHY on the MII. Only allow 3530 * MII address 0. 3531 */ 3532 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3533 return; 3534 #endif 3535 3536 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3537 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3538 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3539 do { 3540 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3541 } while (enphy & ENPHY_ACCESS); 3542 } 3543 3544 /* 3545 * sip_sis900_mii_statchg: [mii interface function] 3546 * 3547 * Callback from MII layer when media changes. 3548 */ 3549 static void 3550 sipcom_sis900_mii_statchg(device_t self) 3551 { 3552 struct sip_softc *sc = device_private(self); 3553 struct mii_data *mii = &sc->sc_mii; 3554 u_int32_t flowctl; 3555 3556 /* 3557 * Get flow control negotiation result. 3558 */ 3559 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3560 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3561 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3562 mii->mii_media_active &= ~IFM_ETH_FMASK; 3563 } 3564 3565 /* 3566 * Update TXCFG for full-duplex operation. 3567 */ 3568 if ((mii->mii_media_active & IFM_FDX) != 0) 3569 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3570 else 3571 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3572 3573 /* 3574 * Update RXCFG for full-duplex or loopback. 3575 */ 3576 if ((mii->mii_media_active & IFM_FDX) != 0 || 3577 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3578 sc->sc_rxcfg |= RXCFG_ATX; 3579 else 3580 sc->sc_rxcfg &= ~RXCFG_ATX; 3581 3582 /* 3583 * Update IMR for use of 802.3x flow control. 3584 */ 3585 if (sc->sc_flowflags & IFM_FLOW) { 3586 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3587 flowctl = FLOWCTL_FLOWEN; 3588 } else { 3589 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3590 flowctl = 0; 3591 } 3592 3593 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3594 sc->sc_txcfg); 3595 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3596 sc->sc_rxcfg); 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3599 } 3600 3601 /* 3602 * sip_dp83815_mii_readreg: [mii interface function] 3603 * 3604 * Read a PHY register on the MII. 3605 */ 3606 static int 3607 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3608 { 3609 struct sip_softc *sc = device_private(self); 3610 u_int32_t val; 3611 3612 /* 3613 * The DP83815 only has an internal PHY. Only allow 3614 * MII address 0. 3615 */ 3616 if (phy != 0) 3617 return (0); 3618 3619 /* 3620 * Apparently, after a reset, the DP83815 can take a while 3621 * to respond. During this recovery period, the BMSR returns 3622 * a value of 0. Catch this -- it's not supposed to happen 3623 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3624 * PHY to come back to life. 3625 * 3626 * This works out because the BMSR is the first register 3627 * read during the PHY probe process. 3628 */ 3629 do { 3630 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3631 } while (reg == MII_BMSR && val == 0); 3632 3633 return (val & 0xffff); 3634 } 3635 3636 /* 3637 * sip_dp83815_mii_writereg: [mii interface function] 3638 * 3639 * Write a PHY register to the MII. 3640 */ 3641 static void 3642 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3643 { 3644 struct sip_softc *sc = device_private(self); 3645 3646 /* 3647 * The DP83815 only has an internal PHY. Only allow 3648 * MII address 0. 3649 */ 3650 if (phy != 0) 3651 return; 3652 3653 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3654 } 3655 3656 /* 3657 * sip_dp83815_mii_statchg: [mii interface function] 3658 * 3659 * Callback from MII layer when media changes. 3660 */ 3661 static void 3662 sipcom_dp83815_mii_statchg(device_t self) 3663 { 3664 struct sip_softc *sc = device_private(self); 3665 3666 /* 3667 * Update TXCFG for full-duplex operation. 3668 */ 3669 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3670 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3671 else 3672 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3673 3674 /* 3675 * Update RXCFG for full-duplex or loopback. 3676 */ 3677 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3678 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3679 sc->sc_rxcfg |= RXCFG_ATX; 3680 else 3681 sc->sc_rxcfg &= ~RXCFG_ATX; 3682 3683 /* 3684 * XXX 802.3x flow control. 3685 */ 3686 3687 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3688 sc->sc_txcfg); 3689 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3690 sc->sc_rxcfg); 3691 3692 /* 3693 * Some DP83815s experience problems when used with short 3694 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3695 * sequence adjusts the DSP's signal attenuation to fix the 3696 * problem. 3697 */ 3698 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3699 uint32_t reg; 3700 3701 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3702 3703 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3704 reg &= 0x0fff; 3705 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3706 delay(100); 3707 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3708 reg &= 0x00ff; 3709 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3710 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3711 0x00e8); 3712 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3713 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3714 reg | 0x20); 3715 } 3716 3717 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3718 } 3719 } 3720 3721 static void 3722 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3723 const struct pci_attach_args *pa, u_int8_t *enaddr) 3724 { 3725 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3726 u_int8_t cksum, *e, match; 3727 int i; 3728 3729 /* 3730 * EEPROM data format for the DP83820 can be found in 3731 * the DP83820 manual, section 4.2.4. 3732 */ 3733 3734 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3735 3736 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3737 match = ~(match - 1); 3738 3739 cksum = 0x55; 3740 e = (u_int8_t *) eeprom_data; 3741 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3742 cksum += *e++; 3743 3744 if (cksum != match) 3745 printf("%s: Checksum (%x) mismatch (%x)", 3746 device_xname(&sc->sc_dev), cksum, match); 3747 3748 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3749 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3750 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3751 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3752 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3753 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3754 } 3755 3756 static void 3757 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3758 { 3759 int i; 3760 3761 /* 3762 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3763 * a reason, but I don't know it. 3764 */ 3765 for (i = 0; i < 10; i++) 3766 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3767 } 3768 3769 static void 3770 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3771 const struct pci_attach_args *pa, u_int8_t *enaddr) 3772 { 3773 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3774 3775 switch (sc->sc_rev) { 3776 case SIS_REV_630S: 3777 case SIS_REV_630E: 3778 case SIS_REV_630EA1: 3779 case SIS_REV_630ET: 3780 case SIS_REV_635: 3781 /* 3782 * The MAC address for the on-board Ethernet of 3783 * the SiS 630 chipset is in the NVRAM. Kick 3784 * the chip into re-loading it from NVRAM, and 3785 * read the MAC address out of the filter registers. 3786 */ 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3788 3789 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3790 RFCR_RFADDR_NODE0); 3791 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3792 0xffff; 3793 3794 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3795 RFCR_RFADDR_NODE2); 3796 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3797 0xffff; 3798 3799 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3800 RFCR_RFADDR_NODE4); 3801 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3802 0xffff; 3803 break; 3804 3805 case SIS_REV_960: 3806 { 3807 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3808 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3809 3810 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3811 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3812 3813 int waittime, i; 3814 3815 /* Allow to read EEPROM from LAN. It is shared 3816 * between a 1394 controller and the NIC and each 3817 * time we access it, we need to set SIS_EECMD_REQ. 3818 */ 3819 SIS_SET_EROMAR(sc, EROMAR_REQ); 3820 3821 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3822 /* Force EEPROM to idle state. */ 3823 3824 /* 3825 * XXX-cube This is ugly. I'll look for docs about it. 3826 */ 3827 SIS_SET_EROMAR(sc, EROMAR_EECS); 3828 sipcom_sis900_eeprom_delay(sc); 3829 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3830 SIS_SET_EROMAR(sc, EROMAR_EESK); 3831 sipcom_sis900_eeprom_delay(sc); 3832 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3833 sipcom_sis900_eeprom_delay(sc); 3834 } 3835 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3836 sipcom_sis900_eeprom_delay(sc); 3837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3838 3839 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3840 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3841 sizeof(myea) / sizeof(myea[0]), myea); 3842 break; 3843 } 3844 DELAY(1); 3845 } 3846 3847 /* 3848 * Set SIS_EECTL_CLK to high, so a other master 3849 * can operate on the i2c bus. 3850 */ 3851 SIS_SET_EROMAR(sc, EROMAR_EESK); 3852 3853 /* Refuse EEPROM access by LAN */ 3854 SIS_SET_EROMAR(sc, EROMAR_DONE); 3855 } break; 3856 3857 default: 3858 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3859 sizeof(myea) / sizeof(myea[0]), myea); 3860 } 3861 3862 enaddr[0] = myea[0] & 0xff; 3863 enaddr[1] = myea[0] >> 8; 3864 enaddr[2] = myea[1] & 0xff; 3865 enaddr[3] = myea[1] >> 8; 3866 enaddr[4] = myea[2] & 0xff; 3867 enaddr[5] = myea[2] >> 8; 3868 } 3869 3870 /* Table and macro to bit-reverse an octet. */ 3871 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3872 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3873 3874 static void 3875 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3876 const struct pci_attach_args *pa, u_int8_t *enaddr) 3877 { 3878 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3879 u_int8_t cksum, *e, match; 3880 int i; 3881 3882 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3883 sizeof(eeprom_data[0]), eeprom_data); 3884 3885 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3886 match = ~(match - 1); 3887 3888 cksum = 0x55; 3889 e = (u_int8_t *) eeprom_data; 3890 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3891 cksum += *e++; 3892 } 3893 if (cksum != match) { 3894 printf("%s: Checksum (%x) mismatch (%x)", 3895 device_xname(&sc->sc_dev), cksum, match); 3896 } 3897 3898 /* 3899 * Unrolled because it makes slightly more sense this way. 3900 * The DP83815 stores the MAC address in bit 0 of word 6 3901 * through bit 15 of word 8. 3902 */ 3903 ea = &eeprom_data[6]; 3904 enaddr[0] = ((*ea & 0x1) << 7); 3905 ea++; 3906 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3907 enaddr[1] = ((*ea & 0x1FE) >> 1); 3908 enaddr[2] = ((*ea & 0x1) << 7); 3909 ea++; 3910 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3911 enaddr[3] = ((*ea & 0x1FE) >> 1); 3912 enaddr[4] = ((*ea & 0x1) << 7); 3913 ea++; 3914 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3915 enaddr[5] = ((*ea & 0x1FE) >> 1); 3916 3917 /* 3918 * In case that's not weird enough, we also need to reverse 3919 * the bits in each byte. This all actually makes more sense 3920 * if you think about the EEPROM storage as an array of bits 3921 * being shifted into bytes, but that's not how we're looking 3922 * at it here... 3923 */ 3924 for (i = 0; i < 6 ;i++) 3925 enaddr[i] = bbr(enaddr[i]); 3926 } 3927 3928 /* 3929 * sip_mediastatus: [ifmedia interface function] 3930 * 3931 * Get the current interface media status. 3932 */ 3933 static void 3934 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3935 { 3936 struct sip_softc *sc = ifp->if_softc; 3937 3938 ether_mediastatus(ifp, ifmr); 3939 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3940 sc->sc_flowflags; 3941 } 3942
Indexes created Tue Sep 30 11:09:46 GMT 2025