if_sip.c revision 1.145.2.1
1 /* $NetBSD: if_sip.c,v 1.145.2.1 2010/04/30 14:43:37 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.145.2.1 2010/04/30 14:43:37 uebayasi Exp $"); 77 78 #include "rnd.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 93 94 #if NRND > 0 95 #include <sys/rnd.h> 96 #endif 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_media.h> 101 #include <net/if_ether.h> 102 103 #include <net/bpf.h> 104 105 #include <sys/bus.h> 106 #include <sys/intr.h> 107 #include <machine/endian.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 #include <dev/mii/mii_bitbang.h> 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 #include <dev/pci/pcidevs.h> 116 117 #include <dev/pci/if_sipreg.h> 118 119 /* 120 * Transmit descriptor list size. This is arbitrary, but allocate 121 * enough descriptors for 128 pending transmissions, and 8 segments 122 * per packet (64 for DP83820 for jumbo frames). 123 * 124 * This MUST work out to a power of 2. 125 */ 126 #define GSIP_NTXSEGS_ALLOC 16 127 #define SIP_NTXSEGS_ALLOC 8 128 129 #define SIP_TXQUEUELEN 256 130 #define MAX_SIP_NTXDESC \ 131 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 132 133 /* 134 * Receive descriptor list size. We have one Rx buffer per incoming 135 * packet, so this logic is a little simpler. 136 * 137 * Actually, on the DP83820, we allow the packet to consume more than 138 * one buffer, in order to support jumbo Ethernet frames. In that 139 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 140 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 141 * so we'd better be quick about handling receive interrupts. 142 */ 143 #define GSIP_NRXDESC 256 144 #define SIP_NRXDESC 128 145 146 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 147 148 /* 149 * Control structures are DMA'd to the SiS900 chip. We allocate them in 150 * a single clump that maps to a single DMA segment to make several things 151 * easier. 152 */ 153 struct sip_control_data { 154 /* 155 * The transmit descriptors. 156 */ 157 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 158 159 /* 160 * The receive descriptors. 161 */ 162 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 163 }; 164 165 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 166 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 167 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 168 169 /* 170 * Software state for transmit jobs. 171 */ 172 struct sip_txsoft { 173 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 174 bus_dmamap_t txs_dmamap; /* our DMA map */ 175 int txs_firstdesc; /* first descriptor in packet */ 176 int txs_lastdesc; /* last descriptor in packet */ 177 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 178 }; 179 180 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 181 182 /* 183 * Software state for receive jobs. 184 */ 185 struct sip_rxsoft { 186 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 187 bus_dmamap_t rxs_dmamap; /* our DMA map */ 188 }; 189 190 enum sip_attach_stage { 191 SIP_ATTACH_FIN = 0 192 , SIP_ATTACH_CREATE_RXMAP 193 , SIP_ATTACH_CREATE_TXMAP 194 , SIP_ATTACH_LOAD_MAP 195 , SIP_ATTACH_CREATE_MAP 196 , SIP_ATTACH_MAP_MEM 197 , SIP_ATTACH_ALLOC_MEM 198 , SIP_ATTACH_INTR 199 , SIP_ATTACH_MAP 200 }; 201 202 /* 203 * Software state per device. 204 */ 205 struct sip_softc { 206 device_t sc_dev; /* generic device information */ 207 device_suspensor_t sc_suspensor; 208 pmf_qual_t sc_qual; 209 210 bus_space_tag_t sc_st; /* bus space tag */ 211 bus_space_handle_t sc_sh; /* bus space handle */ 212 bus_size_t sc_sz; /* bus space size */ 213 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t sc_pc; 215 bus_dma_segment_t sc_seg; 216 struct ethercom sc_ethercom; /* ethernet common data */ 217 218 const struct sip_product *sc_model; /* which model are we? */ 219 int sc_gigabit; /* 1: 83820, 0: other */ 220 int sc_rev; /* chip revision */ 221 222 void *sc_ih; /* interrupt cookie */ 223 224 struct mii_data sc_mii; /* MII/media information */ 225 226 callout_t sc_tick_ch; /* tick callout */ 227 228 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 229 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 235 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct sip_control_data *sc_control_data; 241 #define sc_txdescs sc_control_data->scd_txdescs 242 #define sc_rxdescs sc_control_data->scd_rxdescs 243 244 #ifdef SIP_EVENT_COUNTERS 245 /* 246 * Event counters. 247 */ 248 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 249 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 250 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 251 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 252 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 253 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 254 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 255 struct evcnt sc_ev_rxpause; /* PAUSE received */ 256 /* DP83820 only */ 257 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 258 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 259 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 260 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 261 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 262 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 263 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 264 #endif /* SIP_EVENT_COUNTERS */ 265 266 u_int32_t sc_txcfg; /* prototype TXCFG register */ 267 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 268 u_int32_t sc_imr; /* prototype IMR register */ 269 u_int32_t sc_rfcr; /* prototype RFCR register */ 270 271 u_int32_t sc_cfg; /* prototype CFG register */ 272 273 u_int32_t sc_gpior; /* prototype GPIOR register */ 274 275 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 276 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 277 278 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 279 280 int sc_flowflags; /* 802.3x flow control flags */ 281 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 282 int sc_paused; /* paused indication */ 283 284 int sc_txfree; /* number of free Tx descriptors */ 285 int sc_txnext; /* next ready Tx descriptor */ 286 int sc_txwin; /* Tx descriptors since last intr */ 287 288 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 289 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 290 291 /* values of interface state at last init */ 292 struct { 293 /* if_capenable */ 294 uint64_t if_capenable; 295 /* ec_capenable */ 296 int ec_capenable; 297 /* VLAN_ATTACHED */ 298 int is_vlan; 299 } sc_prev; 300 301 short sc_if_flags; 302 303 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 304 int sc_rxdiscard; 305 int sc_rxlen; 306 struct mbuf *sc_rxhead; 307 struct mbuf *sc_rxtail; 308 struct mbuf **sc_rxtailp; 309 310 int sc_ntxdesc; 311 int sc_ntxdesc_mask; 312 313 int sc_nrxdesc_mask; 314 315 const struct sip_parm { 316 const struct sip_regs { 317 int r_rxcfg; 318 int r_txcfg; 319 } p_regs; 320 321 const struct sip_bits { 322 uint32_t b_txcfg_mxdma_8; 323 uint32_t b_txcfg_mxdma_16; 324 uint32_t b_txcfg_mxdma_32; 325 uint32_t b_txcfg_mxdma_64; 326 uint32_t b_txcfg_mxdma_128; 327 uint32_t b_txcfg_mxdma_256; 328 uint32_t b_txcfg_mxdma_512; 329 uint32_t b_txcfg_flth_mask; 330 uint32_t b_txcfg_drth_mask; 331 332 uint32_t b_rxcfg_mxdma_8; 333 uint32_t b_rxcfg_mxdma_16; 334 uint32_t b_rxcfg_mxdma_32; 335 uint32_t b_rxcfg_mxdma_64; 336 uint32_t b_rxcfg_mxdma_128; 337 uint32_t b_rxcfg_mxdma_256; 338 uint32_t b_rxcfg_mxdma_512; 339 340 uint32_t b_isr_txrcmp; 341 uint32_t b_isr_rxrcmp; 342 uint32_t b_isr_dperr; 343 uint32_t b_isr_sserr; 344 uint32_t b_isr_rmabt; 345 uint32_t b_isr_rtabt; 346 347 uint32_t b_cmdsts_size_mask; 348 } p_bits; 349 int p_filtmem; 350 int p_rxbuf_len; 351 bus_size_t p_tx_dmamap_size; 352 int p_ntxsegs; 353 int p_ntxsegs_alloc; 354 int p_nrxdesc; 355 } *sc_parm; 356 357 void (*sc_rxintr)(struct sip_softc *); 358 359 #if NRND > 0 360 rndsource_element_t rnd_source; /* random source */ 361 #endif 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 485 { 486 int x, n; 487 488 x = x0; 489 n = n0; 490 491 /* If it will wrap around, sync to the end of the ring. */ 492 if (x + n > sc->sc_ntxdesc) { 493 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 494 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 495 (sc->sc_ntxdesc - x), ops); 496 n -= (sc->sc_ntxdesc - x); 497 x = 0; 498 } 499 500 /* Now sync whatever is left. */ 501 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 502 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 503 } 504 505 static inline void 506 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 507 { 508 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 509 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 510 } 511 512 #if 0 513 #ifdef DP83820 514 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 515 u_int32_t sipd_cmdsts; /* command/status word */ 516 #else 517 u_int32_t sipd_cmdsts; /* command/status word */ 518 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 519 #endif /* DP83820 */ 520 #endif /* 0 */ 521 522 static inline volatile uint32_t * 523 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 526 } 527 528 static inline volatile uint32_t * 529 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 530 { 531 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 532 } 533 534 static inline void 535 sip_init_rxdesc(struct sip_softc *sc, int x) 536 { 537 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 538 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 539 540 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 541 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 542 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 543 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 544 sipd->sipd_extsts = 0; 545 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 } 547 548 #define SIP_CHIP_VERS(sc, v, p, r) \ 549 ((sc)->sc_model->sip_vendor == (v) && \ 550 (sc)->sc_model->sip_product == (p) && \ 551 (sc)->sc_rev == (r)) 552 553 #define SIP_CHIP_MODEL(sc, v, p) \ 554 ((sc)->sc_model->sip_vendor == (v) && \ 555 (sc)->sc_model->sip_product == (p)) 556 557 #define SIP_SIS900_REV(sc, rev) \ 558 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 559 560 #define SIP_TIMEOUT 1000 561 562 static int sip_ifflags_cb(struct ethercom *); 563 static void sipcom_start(struct ifnet *); 564 static void sipcom_watchdog(struct ifnet *); 565 static int sipcom_ioctl(struct ifnet *, u_long, void *); 566 static int sipcom_init(struct ifnet *); 567 static void sipcom_stop(struct ifnet *, int); 568 569 static bool sipcom_reset(struct sip_softc *); 570 static void sipcom_rxdrain(struct sip_softc *); 571 static int sipcom_add_rxbuf(struct sip_softc *, int); 572 static void sipcom_read_eeprom(struct sip_softc *, int, int, 573 u_int16_t *); 574 static void sipcom_tick(void *); 575 576 static void sipcom_sis900_set_filter(struct sip_softc *); 577 static void sipcom_dp83815_set_filter(struct sip_softc *); 578 579 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 580 const struct pci_attach_args *, u_int8_t *); 581 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 582 static void sipcom_sis900_read_macaddr(struct sip_softc *, 583 const struct pci_attach_args *, u_int8_t *); 584 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 585 const struct pci_attach_args *, u_int8_t *); 586 587 static int sipcom_intr(void *); 588 static void sipcom_txintr(struct sip_softc *); 589 static void sip_rxintr(struct sip_softc *); 590 static void gsip_rxintr(struct sip_softc *); 591 592 static int sipcom_dp83820_mii_readreg(device_t, int, int); 593 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 594 static void sipcom_dp83820_mii_statchg(device_t); 595 596 static int sipcom_sis900_mii_readreg(device_t, int, int); 597 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 598 static void sipcom_sis900_mii_statchg(device_t); 599 600 static int sipcom_dp83815_mii_readreg(device_t, int, int); 601 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 602 static void sipcom_dp83815_mii_statchg(device_t); 603 604 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 605 606 static int sipcom_match(device_t, cfdata_t, void *); 607 static void sipcom_attach(device_t, device_t, void *); 608 static void sipcom_do_detach(device_t, enum sip_attach_stage); 609 static int sipcom_detach(device_t, int); 610 static bool sipcom_resume(device_t, const pmf_qual_t *); 611 static bool sipcom_suspend(device_t, const pmf_qual_t *); 612 613 int gsip_copy_small = 0; 614 int sip_copy_small = 0; 615 616 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 617 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 618 DVF_DETACH_SHUTDOWN); 619 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 620 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 621 DVF_DETACH_SHUTDOWN); 622 623 /* 624 * Descriptions of the variants of the SiS900. 625 */ 626 struct sip_variant { 627 int (*sipv_mii_readreg)(device_t, int, int); 628 void (*sipv_mii_writereg)(device_t, int, int, int); 629 void (*sipv_mii_statchg)(device_t); 630 void (*sipv_set_filter)(struct sip_softc *); 631 void (*sipv_read_macaddr)(struct sip_softc *, 632 const struct pci_attach_args *, u_int8_t *); 633 }; 634 635 static u_int32_t sipcom_mii_bitbang_read(device_t); 636 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 637 638 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 639 sipcom_mii_bitbang_read, 640 sipcom_mii_bitbang_write, 641 { 642 EROMAR_MDIO, /* MII_BIT_MDO */ 643 EROMAR_MDIO, /* MII_BIT_MDI */ 644 EROMAR_MDC, /* MII_BIT_MDC */ 645 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 646 0, /* MII_BIT_DIR_PHY_HOST */ 647 } 648 }; 649 650 static const struct sip_variant sipcom_variant_dp83820 = { 651 sipcom_dp83820_mii_readreg, 652 sipcom_dp83820_mii_writereg, 653 sipcom_dp83820_mii_statchg, 654 sipcom_dp83815_set_filter, 655 sipcom_dp83820_read_macaddr, 656 }; 657 658 static const struct sip_variant sipcom_variant_sis900 = { 659 sipcom_sis900_mii_readreg, 660 sipcom_sis900_mii_writereg, 661 sipcom_sis900_mii_statchg, 662 sipcom_sis900_set_filter, 663 sipcom_sis900_read_macaddr, 664 }; 665 666 static const struct sip_variant sipcom_variant_dp83815 = { 667 sipcom_dp83815_mii_readreg, 668 sipcom_dp83815_mii_writereg, 669 sipcom_dp83815_mii_statchg, 670 sipcom_dp83815_set_filter, 671 sipcom_dp83815_read_macaddr, 672 }; 673 674 675 /* 676 * Devices supported by this driver. 677 */ 678 static const struct sip_product { 679 pci_vendor_id_t sip_vendor; 680 pci_product_id_t sip_product; 681 const char *sip_name; 682 const struct sip_variant *sip_variant; 683 int sip_gigabit; 684 } sipcom_products[] = { 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 686 "NatSemi DP83820 Gigabit Ethernet", 687 &sipcom_variant_dp83820, 1 }, 688 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 689 "SiS 900 10/100 Ethernet", 690 &sipcom_variant_sis900, 0 }, 691 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 692 "SiS 7016 10/100 Ethernet", 693 &sipcom_variant_sis900, 0 }, 694 695 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 696 "NatSemi DP83815 10/100 Ethernet", 697 &sipcom_variant_dp83815, 0 }, 698 699 { 0, 0, 700 NULL, 701 NULL, 0 }, 702 }; 703 704 static const struct sip_product * 705 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 706 { 707 const struct sip_product *sip; 708 709 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 710 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 711 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 712 sip->sip_gigabit == gigabit) 713 return sip; 714 } 715 return NULL; 716 } 717 718 /* 719 * I really hate stupid hardware vendors. There's a bit in the EEPROM 720 * which indicates if the card can do 64-bit data transfers. Unfortunately, 721 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 722 * which means we try to use 64-bit data transfers on those cards if we 723 * happen to be plugged into a 32-bit slot. 724 * 725 * What we do is use this table of cards known to be 64-bit cards. If 726 * you have a 64-bit card who's subsystem ID is not listed in this table, 727 * send the output of "pcictl dump ..." of the device to me so that your 728 * card will use the 64-bit data path when plugged into a 64-bit slot. 729 * 730 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 731 * June 30, 2002 732 */ 733 static int 734 sipcom_check_64bit(const struct pci_attach_args *pa) 735 { 736 static const struct { 737 pci_vendor_id_t c64_vendor; 738 pci_product_id_t c64_product; 739 } card64[] = { 740 /* Asante GigaNIX */ 741 { 0x128a, 0x0002 }, 742 743 /* Accton EN1407-T, Planex GN-1000TE */ 744 { 0x1113, 0x1407 }, 745 746 /* Netgear GA-621 */ 747 { 0x1385, 0x621a }, 748 749 /* SMC EZ Card */ 750 { 0x10b8, 0x9462 }, 751 752 { 0, 0} 753 }; 754 pcireg_t subsys; 755 int i; 756 757 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 758 759 for (i = 0; card64[i].c64_vendor != 0; i++) { 760 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 761 PCI_PRODUCT(subsys) == card64[i].c64_product) 762 return (1); 763 } 764 765 return (0); 766 } 767 768 static int 769 sipcom_match(device_t parent, cfdata_t cf, void *aux) 770 { 771 struct pci_attach_args *pa = aux; 772 773 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 774 return 1; 775 776 return 0; 777 } 778 779 static void 780 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 781 { 782 u_int32_t reg; 783 int i; 784 785 /* 786 * Cause the chip to load configuration data from the EEPROM. 787 */ 788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 789 for (i = 0; i < 10000; i++) { 790 delay(10); 791 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 792 PTSCR_EELOAD_EN) == 0) 793 break; 794 } 795 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 796 PTSCR_EELOAD_EN) { 797 printf("%s: timeout loading configuration from EEPROM\n", 798 device_xname(sc->sc_dev)); 799 return; 800 } 801 802 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 803 804 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 805 if (reg & CFG_PCI64_DET) { 806 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 807 /* 808 * Check to see if this card is 64-bit. If so, enable 64-bit 809 * data transfers. 810 * 811 * We can't use the DATA64_EN bit in the EEPROM, because 812 * vendors of 32-bit cards fail to clear that bit in many 813 * cases (yet the card still detects that it's in a 64-bit 814 * slot; go figure). 815 */ 816 if (sipcom_check_64bit(pa)) { 817 sc->sc_cfg |= CFG_DATA64_EN; 818 printf(", using 64-bit data transfers"); 819 } 820 printf("\n"); 821 } 822 823 /* 824 * XXX Need some PCI flags indicating support for 825 * XXX 64-bit addressing. 826 */ 827 #if 0 828 if (reg & CFG_M64ADDR) 829 sc->sc_cfg |= CFG_M64ADDR; 830 if (reg & CFG_T64ADDR) 831 sc->sc_cfg |= CFG_T64ADDR; 832 #endif 833 834 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 835 const char *sep = ""; 836 printf("%s: using ", device_xname(sc->sc_dev)); 837 if (reg & CFG_EXT_125) { 838 sc->sc_cfg |= CFG_EXT_125; 839 printf("%s125MHz clock", sep); 840 sep = ", "; 841 } 842 if (reg & CFG_TBI_EN) { 843 sc->sc_cfg |= CFG_TBI_EN; 844 printf("%sten-bit interface", sep); 845 sep = ", "; 846 } 847 printf("\n"); 848 } 849 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 850 (reg & CFG_MRM_DIS) != 0) 851 sc->sc_cfg |= CFG_MRM_DIS; 852 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 853 (reg & CFG_MWI_DIS) != 0) 854 sc->sc_cfg |= CFG_MWI_DIS; 855 856 /* 857 * Use the extended descriptor format on the DP83820. This 858 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 859 * checksumming. 860 */ 861 sc->sc_cfg |= CFG_EXTSTS_EN; 862 } 863 864 static int 865 sipcom_detach(device_t self, int flags) 866 { 867 int s; 868 869 s = splnet(); 870 sipcom_do_detach(self, SIP_ATTACH_FIN); 871 splx(s); 872 873 return 0; 874 } 875 876 static void 877 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 878 { 879 int i; 880 struct sip_softc *sc = device_private(self); 881 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 882 883 /* 884 * Free any resources we've allocated during attach. 885 * Do this in reverse order and fall through. 886 */ 887 switch (stage) { 888 case SIP_ATTACH_FIN: 889 sipcom_stop(ifp, 1); 890 pmf_device_deregister(self); 891 #ifdef SIP_EVENT_COUNTERS 892 /* 893 * Attach event counters. 894 */ 895 evcnt_detach(&sc->sc_ev_txforceintr); 896 evcnt_detach(&sc->sc_ev_txdstall); 897 evcnt_detach(&sc->sc_ev_txsstall); 898 evcnt_detach(&sc->sc_ev_hiberr); 899 evcnt_detach(&sc->sc_ev_rxintr); 900 evcnt_detach(&sc->sc_ev_txiintr); 901 evcnt_detach(&sc->sc_ev_txdintr); 902 if (!sc->sc_gigabit) { 903 evcnt_detach(&sc->sc_ev_rxpause); 904 } else { 905 evcnt_detach(&sc->sc_ev_txudpsum); 906 evcnt_detach(&sc->sc_ev_txtcpsum); 907 evcnt_detach(&sc->sc_ev_txipsum); 908 evcnt_detach(&sc->sc_ev_rxudpsum); 909 evcnt_detach(&sc->sc_ev_rxtcpsum); 910 evcnt_detach(&sc->sc_ev_rxipsum); 911 evcnt_detach(&sc->sc_ev_txpause); 912 evcnt_detach(&sc->sc_ev_rxpause); 913 } 914 #endif /* SIP_EVENT_COUNTERS */ 915 916 #if NRND > 0 917 rnd_detach_source(&sc->rnd_source); 918 #endif 919 920 ether_ifdetach(ifp); 921 if_detach(ifp); 922 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 923 924 /*FALLTHROUGH*/ 925 case SIP_ATTACH_CREATE_RXMAP: 926 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 927 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 928 bus_dmamap_destroy(sc->sc_dmat, 929 sc->sc_rxsoft[i].rxs_dmamap); 930 } 931 /*FALLTHROUGH*/ 932 case SIP_ATTACH_CREATE_TXMAP: 933 for (i = 0; i < SIP_TXQUEUELEN; i++) { 934 if (sc->sc_txsoft[i].txs_dmamap != NULL) 935 bus_dmamap_destroy(sc->sc_dmat, 936 sc->sc_txsoft[i].txs_dmamap); 937 } 938 /*FALLTHROUGH*/ 939 case SIP_ATTACH_LOAD_MAP: 940 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 941 /*FALLTHROUGH*/ 942 case SIP_ATTACH_CREATE_MAP: 943 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 944 /*FALLTHROUGH*/ 945 case SIP_ATTACH_MAP_MEM: 946 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 947 sizeof(struct sip_control_data)); 948 /*FALLTHROUGH*/ 949 case SIP_ATTACH_ALLOC_MEM: 950 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 951 /* FALLTHROUGH*/ 952 case SIP_ATTACH_INTR: 953 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 954 /* FALLTHROUGH*/ 955 case SIP_ATTACH_MAP: 956 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 957 break; 958 default: 959 break; 960 } 961 return; 962 } 963 964 static bool 965 sipcom_resume(device_t self, const pmf_qual_t *qual) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 return sipcom_reset(sc); 970 } 971 972 static bool 973 sipcom_suspend(device_t self, const pmf_qual_t *qual) 974 { 975 struct sip_softc *sc = device_private(self); 976 977 sipcom_rxdrain(sc); 978 return true; 979 } 980 981 static void 982 sipcom_attach(device_t parent, device_t self, void *aux) 983 { 984 struct sip_softc *sc = device_private(self); 985 struct pci_attach_args *pa = aux; 986 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 987 pci_chipset_tag_t pc = pa->pa_pc; 988 pci_intr_handle_t ih; 989 const char *intrstr = NULL; 990 bus_space_tag_t iot, memt; 991 bus_space_handle_t ioh, memh; 992 bus_size_t iosz, memsz; 993 int ioh_valid, memh_valid; 994 int i, rseg, error; 995 const struct sip_product *sip; 996 u_int8_t enaddr[ETHER_ADDR_LEN]; 997 pcireg_t csr; 998 pcireg_t memtype; 999 bus_size_t tx_dmamap_size; 1000 int ntxsegs_alloc; 1001 cfdata_t cf = device_cfdata(self); 1002 1003 callout_init(&sc->sc_tick_ch, 0); 1004 1005 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1006 if (sip == NULL) { 1007 printf("\n"); 1008 panic("%s: impossible", __func__); 1009 } 1010 sc->sc_dev = self; 1011 sc->sc_gigabit = sip->sip_gigabit; 1012 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1013 sc->sc_pc = pc; 1014 1015 if (sc->sc_gigabit) { 1016 sc->sc_rxintr = gsip_rxintr; 1017 sc->sc_parm = &gsip_parm; 1018 } else { 1019 sc->sc_rxintr = sip_rxintr; 1020 sc->sc_parm = &sip_parm; 1021 } 1022 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1023 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1024 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1025 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1026 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1027 1028 sc->sc_rev = PCI_REVISION(pa->pa_class); 1029 1030 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1031 1032 sc->sc_model = sip; 1033 1034 /* 1035 * XXX Work-around broken PXE firmware on some boards. 1036 * 1037 * The DP83815 shares an address decoder with the MEM BAR 1038 * and the ROM BAR. Make sure the ROM BAR is disabled, 1039 * so that memory mapped access works. 1040 */ 1041 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1042 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1043 ~PCI_MAPREG_ROM_ENABLE); 1044 1045 /* 1046 * Map the device. 1047 */ 1048 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1049 PCI_MAPREG_TYPE_IO, 0, 1050 &iot, &ioh, NULL, &iosz) == 0); 1051 if (sc->sc_gigabit) { 1052 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1053 switch (memtype) { 1054 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1055 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1056 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1057 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1058 break; 1059 default: 1060 memh_valid = 0; 1061 } 1062 } else { 1063 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1064 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1065 &memt, &memh, NULL, &memsz) == 0); 1066 } 1067 1068 if (memh_valid) { 1069 sc->sc_st = memt; 1070 sc->sc_sh = memh; 1071 sc->sc_sz = memsz; 1072 } else if (ioh_valid) { 1073 sc->sc_st = iot; 1074 sc->sc_sh = ioh; 1075 sc->sc_sz = iosz; 1076 } else { 1077 printf("%s: unable to map device registers\n", 1078 device_xname(sc->sc_dev)); 1079 return; 1080 } 1081 1082 sc->sc_dmat = pa->pa_dmat; 1083 1084 /* 1085 * Make sure bus mastering is enabled. Also make sure 1086 * Write/Invalidate is enabled if we're allowed to use it. 1087 */ 1088 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1089 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1090 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1091 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1092 csr | PCI_COMMAND_MASTER_ENABLE); 1093 1094 /* power up chip */ 1095 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1096 if (error != 0 && error != EOPNOTSUPP) { 1097 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1098 return; 1099 } 1100 1101 /* 1102 * Map and establish our interrupt. 1103 */ 1104 if (pci_intr_map(pa, &ih)) { 1105 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1106 return; 1107 } 1108 intrstr = pci_intr_string(pc, ih); 1109 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1110 if (sc->sc_ih == NULL) { 1111 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1112 if (intrstr != NULL) 1113 aprint_error(" at %s", intrstr); 1114 aprint_error("\n"); 1115 return sipcom_do_detach(self, SIP_ATTACH_MAP); 1116 } 1117 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1118 1119 SIMPLEQ_INIT(&sc->sc_txfreeq); 1120 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1121 1122 /* 1123 * Allocate the control data structures, and create and load the 1124 * DMA map for it. 1125 */ 1126 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1127 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1128 &rseg, 0)) != 0) { 1129 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1130 error); 1131 return sipcom_do_detach(self, SIP_ATTACH_INTR); 1132 } 1133 1134 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1135 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1136 BUS_DMA_COHERENT|BUS_DMA_NOCACHE)) != 0) { 1137 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1138 error); 1139 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1140 } 1141 1142 if ((error = bus_dmamap_create(sc->sc_dmat, 1143 sizeof(struct sip_control_data), 1, 1144 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1145 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1146 "error = %d\n", error); 1147 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1148 } 1149 1150 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1151 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1152 0)) != 0) { 1153 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1154 error); 1155 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1156 } 1157 1158 /* 1159 * Create the transmit buffer DMA maps. 1160 */ 1161 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1162 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1163 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1164 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1165 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1166 "error = %d\n", i, error); 1167 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1168 } 1169 } 1170 1171 /* 1172 * Create the receive buffer DMA maps. 1173 */ 1174 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1175 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1176 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1177 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1178 "error = %d\n", i, error); 1179 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1180 } 1181 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1182 } 1183 1184 /* 1185 * Reset the chip to a known state. 1186 */ 1187 sipcom_reset(sc); 1188 1189 /* 1190 * Read the Ethernet address from the EEPROM. This might 1191 * also fetch other stuff from the EEPROM and stash it 1192 * in the softc. 1193 */ 1194 sc->sc_cfg = 0; 1195 if (!sc->sc_gigabit) { 1196 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1197 SIP_SIS900_REV(sc,SIS_REV_900B)) 1198 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1199 1200 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1201 SIP_SIS900_REV(sc,SIS_REV_960) || 1202 SIP_SIS900_REV(sc,SIS_REV_900B)) 1203 sc->sc_cfg |= 1204 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1205 CFG_EDBMASTEN); 1206 } 1207 1208 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1209 1210 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1211 ether_sprintf(enaddr)); 1212 1213 /* 1214 * Initialize the configuration register: aggressive PCI 1215 * bus request algorithm, default backoff, default OW timer, 1216 * default parity error detection. 1217 * 1218 * NOTE: "Big endian mode" is useless on the SiS900 and 1219 * friends -- it affects packet data, not descriptors. 1220 */ 1221 if (sc->sc_gigabit) 1222 sipcom_dp83820_attach(sc, pa); 1223 1224 /* 1225 * Initialize our media structures and probe the MII. 1226 */ 1227 sc->sc_mii.mii_ifp = ifp; 1228 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1229 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1230 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1231 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1232 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1233 sipcom_mediastatus); 1234 1235 /* 1236 * XXX We cannot handle flow control on the DP83815. 1237 */ 1238 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1239 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, 0); 1241 else 1242 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1243 MII_OFFSET_ANY, MIIF_DOPAUSE); 1244 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1245 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1247 } else 1248 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1249 1250 ifp = &sc->sc_ethercom.ec_if; 1251 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1252 ifp->if_softc = sc; 1253 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1254 sc->sc_if_flags = ifp->if_flags; 1255 ifp->if_ioctl = sipcom_ioctl; 1256 ifp->if_start = sipcom_start; 1257 ifp->if_watchdog = sipcom_watchdog; 1258 ifp->if_init = sipcom_init; 1259 ifp->if_stop = sipcom_stop; 1260 IFQ_SET_READY(&ifp->if_snd); 1261 1262 /* 1263 * We can support 802.1Q VLAN-sized frames. 1264 */ 1265 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1266 1267 if (sc->sc_gigabit) { 1268 /* 1269 * And the DP83820 can do VLAN tagging in hardware, and 1270 * support the jumbo Ethernet MTU. 1271 */ 1272 sc->sc_ethercom.ec_capabilities |= 1273 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1274 1275 /* 1276 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1277 * in hardware. 1278 */ 1279 ifp->if_capabilities |= 1280 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1281 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1282 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1283 } 1284 1285 /* 1286 * Attach the interface. 1287 */ 1288 if_attach(ifp); 1289 ether_ifattach(ifp, enaddr); 1290 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1291 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1292 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1293 sc->sc_prev.if_capenable = ifp->if_capenable; 1294 #if NRND > 0 1295 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1296 RND_TYPE_NET, 0); 1297 #endif 1298 1299 /* 1300 * The number of bytes that must be available in 1301 * the Tx FIFO before the bus master can DMA more 1302 * data into the FIFO. 1303 */ 1304 sc->sc_tx_fill_thresh = 64 / 32; 1305 1306 /* 1307 * Start at a drain threshold of 512 bytes. We will 1308 * increase it if a DMA underrun occurs. 1309 * 1310 * XXX The minimum value of this variable should be 1311 * tuned. We may be able to improve performance 1312 * by starting with a lower value. That, however, 1313 * may trash the first few outgoing packets if the 1314 * PCI bus is saturated. 1315 */ 1316 if (sc->sc_gigabit) 1317 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1318 else 1319 sc->sc_tx_drain_thresh = 1504 / 32; 1320 1321 /* 1322 * Initialize the Rx FIFO drain threshold. 1323 * 1324 * This is in units of 8 bytes. 1325 * 1326 * We should never set this value lower than 2; 14 bytes are 1327 * required to filter the packet. 1328 */ 1329 sc->sc_rx_drain_thresh = 128 / 8; 1330 1331 #ifdef SIP_EVENT_COUNTERS 1332 /* 1333 * Attach event counters. 1334 */ 1335 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1336 NULL, device_xname(sc->sc_dev), "txsstall"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1338 NULL, device_xname(sc->sc_dev), "txdstall"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txforceintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "txdintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "txiintr"); 1345 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1346 NULL, device_xname(sc->sc_dev), "rxintr"); 1347 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1348 NULL, device_xname(sc->sc_dev), "hiberr"); 1349 if (!sc->sc_gigabit) { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1351 NULL, device_xname(sc->sc_dev), "rxpause"); 1352 } else { 1353 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxpause"); 1355 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "txpause"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxipsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txipsum"); 1365 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1366 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1367 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1368 NULL, device_xname(sc->sc_dev), "txudpsum"); 1369 } 1370 #endif /* SIP_EVENT_COUNTERS */ 1371 1372 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1373 pmf_class_network_register(self, ifp); 1374 else 1375 aprint_error_dev(self, "couldn't establish power handler\n"); 1376 } 1377 1378 static inline void 1379 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1380 uint64_t capenable) 1381 { 1382 struct m_tag *mtag; 1383 u_int32_t extsts; 1384 #ifdef DEBUG 1385 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1386 #endif 1387 /* 1388 * If VLANs are enabled and the packet has a VLAN tag, set 1389 * up the descriptor to encapsulate the packet for us. 1390 * 1391 * This apparently has to be on the last descriptor of 1392 * the packet. 1393 */ 1394 1395 /* 1396 * Byte swapping is tricky. We need to provide the tag 1397 * in a network byte order. On a big-endian machine, 1398 * the byteorder is correct, but we need to swap it 1399 * anyway, because this will be undone by the outside 1400 * htole32(). That's why there must be an 1401 * unconditional swap instead of htons() inside. 1402 */ 1403 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1404 sc->sc_txdescs[lasttx].sipd_extsts |= 1405 htole32(EXTSTS_VPKT | 1406 (bswap16(VLAN_TAG_VALUE(mtag)) & 1407 EXTSTS_VTCI)); 1408 } 1409 1410 /* 1411 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1412 * checksumming, set up the descriptor to do this work 1413 * for us. 1414 * 1415 * This apparently has to be on the first descriptor of 1416 * the packet. 1417 * 1418 * Byte-swap constants so the compiler can optimize. 1419 */ 1420 extsts = 0; 1421 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1422 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1423 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1424 extsts |= htole32(EXTSTS_IPPKT); 1425 } 1426 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1429 extsts |= htole32(EXTSTS_TCPPKT); 1430 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1431 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1432 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1433 extsts |= htole32(EXTSTS_UDPPKT); 1434 } 1435 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1436 } 1437 1438 /* 1439 * sip_start: [ifnet interface function] 1440 * 1441 * Start packet transmission on the interface. 1442 */ 1443 static void 1444 sipcom_start(struct ifnet *ifp) 1445 { 1446 struct sip_softc *sc = ifp->if_softc; 1447 struct mbuf *m0; 1448 struct mbuf *m; 1449 struct sip_txsoft *txs; 1450 bus_dmamap_t dmamap; 1451 int error, nexttx, lasttx, seg; 1452 int ofree = sc->sc_txfree; 1453 #if 0 1454 int firsttx = sc->sc_txnext; 1455 #endif 1456 1457 /* 1458 * If we've been told to pause, don't transmit any more packets. 1459 */ 1460 if (!sc->sc_gigabit && sc->sc_paused) 1461 ifp->if_flags |= IFF_OACTIVE; 1462 1463 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1464 return; 1465 1466 /* 1467 * Loop through the send queue, setting up transmit descriptors 1468 * until we drain the queue, or use up all available transmit 1469 * descriptors. 1470 */ 1471 for (;;) { 1472 /* Get a work queue entry. */ 1473 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1474 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1475 break; 1476 } 1477 1478 /* 1479 * Grab a packet off the queue. 1480 */ 1481 IFQ_POLL(&ifp->if_snd, m0); 1482 if (m0 == NULL) 1483 break; 1484 m = NULL; 1485 1486 dmamap = txs->txs_dmamap; 1487 1488 /* 1489 * Load the DMA map. If this fails, the packet either 1490 * didn't fit in the alloted number of segments, or we 1491 * were short on resources. 1492 */ 1493 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1494 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1495 /* In the non-gigabit case, we'll copy and try again. */ 1496 if (error != 0 && !sc->sc_gigabit) { 1497 MGETHDR(m, M_DONTWAIT, MT_DATA); 1498 if (m == NULL) { 1499 printf("%s: unable to allocate Tx mbuf\n", 1500 device_xname(sc->sc_dev)); 1501 break; 1502 } 1503 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1504 if (m0->m_pkthdr.len > MHLEN) { 1505 MCLGET(m, M_DONTWAIT); 1506 if ((m->m_flags & M_EXT) == 0) { 1507 printf("%s: unable to allocate Tx " 1508 "cluster\n", device_xname(sc->sc_dev)); 1509 m_freem(m); 1510 break; 1511 } 1512 } 1513 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1514 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1515 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1516 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1517 if (error) { 1518 printf("%s: unable to load Tx buffer, " 1519 "error = %d\n", device_xname(sc->sc_dev), error); 1520 break; 1521 } 1522 } else if (error == EFBIG) { 1523 /* 1524 * For the too-many-segments case, we simply 1525 * report an error and drop the packet, 1526 * since we can't sanely copy a jumbo packet 1527 * to a single buffer. 1528 */ 1529 printf("%s: Tx packet consumes too many " 1530 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1531 IFQ_DEQUEUE(&ifp->if_snd, m0); 1532 m_freem(m0); 1533 continue; 1534 } else if (error != 0) { 1535 /* 1536 * Short on resources, just stop for now. 1537 */ 1538 break; 1539 } 1540 1541 /* 1542 * Ensure we have enough descriptors free to describe 1543 * the packet. Note, we always reserve one descriptor 1544 * at the end of the ring as a termination point, to 1545 * prevent wrap-around. 1546 */ 1547 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1548 /* 1549 * Not enough free descriptors to transmit this 1550 * packet. We haven't committed anything yet, 1551 * so just unload the DMA map, put the packet 1552 * back on the queue, and punt. Notify the upper 1553 * layer that there are not more slots left. 1554 * 1555 * XXX We could allocate an mbuf and copy, but 1556 * XXX is it worth it? 1557 */ 1558 ifp->if_flags |= IFF_OACTIVE; 1559 bus_dmamap_unload(sc->sc_dmat, dmamap); 1560 if (m != NULL) 1561 m_freem(m); 1562 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1563 break; 1564 } 1565 1566 IFQ_DEQUEUE(&ifp->if_snd, m0); 1567 if (m != NULL) { 1568 m_freem(m0); 1569 m0 = m; 1570 } 1571 1572 /* 1573 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1574 */ 1575 1576 /* Sync the DMA map. */ 1577 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1578 BUS_DMASYNC_PREWRITE); 1579 1580 /* 1581 * Initialize the transmit descriptors. 1582 */ 1583 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1584 seg < dmamap->dm_nsegs; 1585 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1586 /* 1587 * If this is the first descriptor we're 1588 * enqueueing, don't set the OWN bit just 1589 * yet. That could cause a race condition. 1590 * We'll do it below. 1591 */ 1592 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1593 htole32(dmamap->dm_segs[seg].ds_addr); 1594 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1595 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1596 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1597 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1598 lasttx = nexttx; 1599 } 1600 1601 /* Clear the MORE bit on the last segment. */ 1602 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1603 htole32(~CMDSTS_MORE); 1604 1605 /* 1606 * If we're in the interrupt delay window, delay the 1607 * interrupt. 1608 */ 1609 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1610 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1611 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1612 htole32(CMDSTS_INTR); 1613 sc->sc_txwin = 0; 1614 } 1615 1616 if (sc->sc_gigabit) 1617 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1618 1619 /* Sync the descriptors we're using. */ 1620 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1621 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1622 1623 /* 1624 * The entire packet is set up. Give the first descrptor 1625 * to the chip now. 1626 */ 1627 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1628 htole32(CMDSTS_OWN); 1629 sip_cdtxsync(sc, sc->sc_txnext, 1, 1630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1631 1632 /* 1633 * Store a pointer to the packet so we can free it later, 1634 * and remember what txdirty will be once the packet is 1635 * done. 1636 */ 1637 txs->txs_mbuf = m0; 1638 txs->txs_firstdesc = sc->sc_txnext; 1639 txs->txs_lastdesc = lasttx; 1640 1641 /* Advance the tx pointer. */ 1642 sc->sc_txfree -= dmamap->dm_nsegs; 1643 sc->sc_txnext = nexttx; 1644 1645 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1646 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1647 1648 /* 1649 * Pass the packet to any BPF listeners. 1650 */ 1651 bpf_mtap(ifp, m0); 1652 } 1653 1654 if (txs == NULL || sc->sc_txfree == 0) { 1655 /* No more slots left; notify upper layer. */ 1656 ifp->if_flags |= IFF_OACTIVE; 1657 } 1658 1659 if (sc->sc_txfree != ofree) { 1660 /* 1661 * Start the transmit process. Note, the manual says 1662 * that if there are no pending transmissions in the 1663 * chip's internal queue (indicated by TXE being clear), 1664 * then the driver software must set the TXDP to the 1665 * first descriptor to be transmitted. However, if we 1666 * do this, it causes serious performance degredation on 1667 * the DP83820 under load, not setting TXDP doesn't seem 1668 * to adversely affect the SiS 900 or DP83815. 1669 * 1670 * Well, I guess it wouldn't be the first time a manual 1671 * has lied -- and they could be speaking of the NULL- 1672 * terminated descriptor list case, rather than OWN- 1673 * terminated rings. 1674 */ 1675 #if 0 1676 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1677 CR_TXE) == 0) { 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1679 SIP_CDTXADDR(sc, firsttx)); 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1681 } 1682 #else 1683 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1684 #endif 1685 1686 /* Set a watchdog timer in case the chip flakes out. */ 1687 /* Gigabit autonegotiation takes 5 seconds. */ 1688 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1689 } 1690 } 1691 1692 /* 1693 * sip_watchdog: [ifnet interface function] 1694 * 1695 * Watchdog timer handler. 1696 */ 1697 static void 1698 sipcom_watchdog(struct ifnet *ifp) 1699 { 1700 struct sip_softc *sc = ifp->if_softc; 1701 1702 /* 1703 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1704 * If we get a timeout, try and sweep up transmit descriptors. 1705 * If we manage to sweep them all up, ignore the lack of 1706 * interrupt. 1707 */ 1708 sipcom_txintr(sc); 1709 1710 if (sc->sc_txfree != sc->sc_ntxdesc) { 1711 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1712 ifp->if_oerrors++; 1713 1714 /* Reset the interface. */ 1715 (void) sipcom_init(ifp); 1716 } else if (ifp->if_flags & IFF_DEBUG) 1717 printf("%s: recovered from device timeout\n", 1718 device_xname(sc->sc_dev)); 1719 1720 /* Try to get more packets going. */ 1721 sipcom_start(ifp); 1722 } 1723 1724 /* If the interface is up and running, only modify the receive 1725 * filter when setting promiscuous or debug mode. Otherwise fall 1726 * through to ether_ioctl, which will reset the chip. 1727 */ 1728 static int 1729 sip_ifflags_cb(struct ethercom *ec) 1730 { 1731 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1732 == (sc)->sc_ethercom.ec_capenable) \ 1733 && ((sc)->sc_prev.is_vlan == \ 1734 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1735 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1736 struct ifnet *ifp = &ec->ec_if; 1737 struct sip_softc *sc = ifp->if_softc; 1738 int change = ifp->if_flags ^ sc->sc_if_flags; 1739 1740 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1741 !COMPARE_IC(sc, ifp)) 1742 return ENETRESET; 1743 /* Set up the receive filter. */ 1744 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1745 return 0; 1746 } 1747 1748 /* 1749 * sip_ioctl: [ifnet interface function] 1750 * 1751 * Handle control requests from the operator. 1752 */ 1753 static int 1754 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1755 { 1756 struct sip_softc *sc = ifp->if_softc; 1757 struct ifreq *ifr = (struct ifreq *)data; 1758 int s, error; 1759 1760 s = splnet(); 1761 1762 switch (cmd) { 1763 case SIOCSIFMEDIA: 1764 /* Flow control requires full-duplex mode. */ 1765 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1766 (ifr->ifr_media & IFM_FDX) == 0) 1767 ifr->ifr_media &= ~IFM_ETH_FMASK; 1768 1769 /* XXX */ 1770 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1771 ifr->ifr_media &= ~IFM_ETH_FMASK; 1772 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1773 if (sc->sc_gigabit && 1774 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1775 /* We can do both TXPAUSE and RXPAUSE. */ 1776 ifr->ifr_media |= 1777 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1778 } else if (ifr->ifr_media & IFM_FLOW) { 1779 /* 1780 * Both TXPAUSE and RXPAUSE must be set. 1781 * (SiS900 and DP83815 don't have PAUSE_ASYM 1782 * feature.) 1783 * 1784 * XXX Can SiS900 and DP83815 send PAUSE? 1785 */ 1786 ifr->ifr_media |= 1787 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1788 } 1789 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1790 } 1791 /*FALLTHROUGH*/ 1792 default: 1793 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1794 break; 1795 1796 error = 0; 1797 1798 if (cmd == SIOCSIFCAP) 1799 error = (*ifp->if_init)(ifp); 1800 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1801 ; 1802 else if (ifp->if_flags & IFF_RUNNING) { 1803 /* 1804 * Multicast list has changed; set the hardware filter 1805 * accordingly. 1806 */ 1807 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1808 } 1809 break; 1810 } 1811 1812 /* Try to get more packets going. */ 1813 sipcom_start(ifp); 1814 1815 sc->sc_if_flags = ifp->if_flags; 1816 splx(s); 1817 return (error); 1818 } 1819 1820 /* 1821 * sip_intr: 1822 * 1823 * Interrupt service routine. 1824 */ 1825 static int 1826 sipcom_intr(void *arg) 1827 { 1828 struct sip_softc *sc = arg; 1829 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1830 u_int32_t isr; 1831 int handled = 0; 1832 1833 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1834 return 0; 1835 1836 /* Disable interrupts. */ 1837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1838 1839 for (;;) { 1840 /* Reading clears interrupt. */ 1841 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1842 if ((isr & sc->sc_imr) == 0) 1843 break; 1844 1845 #if NRND > 0 1846 if (RND_ENABLED(&sc->rnd_source)) 1847 rnd_add_uint32(&sc->rnd_source, isr); 1848 #endif 1849 1850 handled = 1; 1851 1852 if ((ifp->if_flags & IFF_RUNNING) == 0) 1853 break; 1854 1855 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1856 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1857 1858 /* Grab any new packets. */ 1859 (*sc->sc_rxintr)(sc); 1860 1861 if (isr & ISR_RXORN) { 1862 printf("%s: receive FIFO overrun\n", 1863 device_xname(sc->sc_dev)); 1864 1865 /* XXX adjust rx_drain_thresh? */ 1866 } 1867 1868 if (isr & ISR_RXIDLE) { 1869 printf("%s: receive ring overrun\n", 1870 device_xname(sc->sc_dev)); 1871 1872 /* Get the receive process going again. */ 1873 bus_space_write_4(sc->sc_st, sc->sc_sh, 1874 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1875 bus_space_write_4(sc->sc_st, sc->sc_sh, 1876 SIP_CR, CR_RXE); 1877 } 1878 } 1879 1880 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1881 #ifdef SIP_EVENT_COUNTERS 1882 if (isr & ISR_TXDESC) 1883 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1884 else if (isr & ISR_TXIDLE) 1885 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1886 #endif 1887 1888 /* Sweep up transmit descriptors. */ 1889 sipcom_txintr(sc); 1890 1891 if (isr & ISR_TXURN) { 1892 u_int32_t thresh; 1893 int txfifo_size = (sc->sc_gigabit) 1894 ? DP83820_SIP_TXFIFO_SIZE 1895 : OTHER_SIP_TXFIFO_SIZE; 1896 1897 printf("%s: transmit FIFO underrun", 1898 device_xname(sc->sc_dev)); 1899 thresh = sc->sc_tx_drain_thresh + 1; 1900 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1901 && (thresh * 32) <= (txfifo_size - 1902 (sc->sc_tx_fill_thresh * 32))) { 1903 printf("; increasing Tx drain " 1904 "threshold to %u bytes\n", 1905 thresh * 32); 1906 sc->sc_tx_drain_thresh = thresh; 1907 (void) sipcom_init(ifp); 1908 } else { 1909 (void) sipcom_init(ifp); 1910 printf("\n"); 1911 } 1912 } 1913 } 1914 1915 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1916 if (isr & ISR_PAUSE_ST) { 1917 sc->sc_paused = 1; 1918 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1919 ifp->if_flags |= IFF_OACTIVE; 1920 } 1921 if (isr & ISR_PAUSE_END) { 1922 sc->sc_paused = 0; 1923 ifp->if_flags &= ~IFF_OACTIVE; 1924 } 1925 } 1926 1927 if (isr & ISR_HIBERR) { 1928 int want_init = 0; 1929 1930 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1931 1932 #define PRINTERR(bit, str) \ 1933 do { \ 1934 if ((isr & (bit)) != 0) { \ 1935 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1936 printf("%s: %s\n", \ 1937 device_xname(sc->sc_dev), str); \ 1938 want_init = 1; \ 1939 } \ 1940 } while (/*CONSTCOND*/0) 1941 1942 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1943 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1944 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1945 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1946 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1947 /* 1948 * Ignore: 1949 * Tx reset complete 1950 * Rx reset complete 1951 */ 1952 if (want_init) 1953 (void) sipcom_init(ifp); 1954 #undef PRINTERR 1955 } 1956 } 1957 1958 /* Re-enable interrupts. */ 1959 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1960 1961 /* Try to get more packets going. */ 1962 sipcom_start(ifp); 1963 1964 return (handled); 1965 } 1966 1967 /* 1968 * sip_txintr: 1969 * 1970 * Helper; handle transmit interrupts. 1971 */ 1972 static void 1973 sipcom_txintr(struct sip_softc *sc) 1974 { 1975 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1976 struct sip_txsoft *txs; 1977 u_int32_t cmdsts; 1978 1979 if (sc->sc_paused == 0) 1980 ifp->if_flags &= ~IFF_OACTIVE; 1981 1982 /* 1983 * Go through our Tx list and free mbufs for those 1984 * frames which have been transmitted. 1985 */ 1986 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1987 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1988 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1989 1990 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1991 if (cmdsts & CMDSTS_OWN) 1992 break; 1993 1994 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1995 1996 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1997 1998 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1999 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2000 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2001 m_freem(txs->txs_mbuf); 2002 txs->txs_mbuf = NULL; 2003 2004 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2005 2006 /* 2007 * Check for errors and collisions. 2008 */ 2009 if (cmdsts & 2010 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2011 ifp->if_oerrors++; 2012 if (cmdsts & CMDSTS_Tx_EC) 2013 ifp->if_collisions += 16; 2014 if (ifp->if_flags & IFF_DEBUG) { 2015 if (cmdsts & CMDSTS_Tx_ED) 2016 printf("%s: excessive deferral\n", 2017 device_xname(sc->sc_dev)); 2018 if (cmdsts & CMDSTS_Tx_EC) 2019 printf("%s: excessive collisions\n", 2020 device_xname(sc->sc_dev)); 2021 } 2022 } else { 2023 /* Packet was transmitted successfully. */ 2024 ifp->if_opackets++; 2025 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2026 } 2027 } 2028 2029 /* 2030 * If there are no more pending transmissions, cancel the watchdog 2031 * timer. 2032 */ 2033 if (txs == NULL) { 2034 ifp->if_timer = 0; 2035 sc->sc_txwin = 0; 2036 } 2037 } 2038 2039 /* 2040 * gsip_rxintr: 2041 * 2042 * Helper; handle receive interrupts on gigabit parts. 2043 */ 2044 static void 2045 gsip_rxintr(struct sip_softc *sc) 2046 { 2047 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2048 struct sip_rxsoft *rxs; 2049 struct mbuf *m; 2050 u_int32_t cmdsts, extsts; 2051 int i, len; 2052 2053 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2054 rxs = &sc->sc_rxsoft[i]; 2055 2056 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2057 2058 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2059 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2060 len = CMDSTS_SIZE(sc, cmdsts); 2061 2062 /* 2063 * NOTE: OWN is set if owned by _consumer_. We're the 2064 * consumer of the receive ring, so if the bit is clear, 2065 * we have processed all of the packets. 2066 */ 2067 if ((cmdsts & CMDSTS_OWN) == 0) { 2068 /* 2069 * We have processed all of the receive buffers. 2070 */ 2071 break; 2072 } 2073 2074 if (__predict_false(sc->sc_rxdiscard)) { 2075 sip_init_rxdesc(sc, i); 2076 if ((cmdsts & CMDSTS_MORE) == 0) { 2077 /* Reset our state. */ 2078 sc->sc_rxdiscard = 0; 2079 } 2080 continue; 2081 } 2082 2083 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2084 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2085 2086 m = rxs->rxs_mbuf; 2087 2088 /* 2089 * Add a new receive buffer to the ring. 2090 */ 2091 if (sipcom_add_rxbuf(sc, i) != 0) { 2092 /* 2093 * Failed, throw away what we've done so 2094 * far, and discard the rest of the packet. 2095 */ 2096 ifp->if_ierrors++; 2097 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2098 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2099 sip_init_rxdesc(sc, i); 2100 if (cmdsts & CMDSTS_MORE) 2101 sc->sc_rxdiscard = 1; 2102 if (sc->sc_rxhead != NULL) 2103 m_freem(sc->sc_rxhead); 2104 sip_rxchain_reset(sc); 2105 continue; 2106 } 2107 2108 sip_rxchain_link(sc, m); 2109 2110 m->m_len = len; 2111 2112 /* 2113 * If this is not the end of the packet, keep 2114 * looking. 2115 */ 2116 if (cmdsts & CMDSTS_MORE) { 2117 sc->sc_rxlen += len; 2118 continue; 2119 } 2120 2121 /* 2122 * Okay, we have the entire packet now. The chip includes 2123 * the FCS, so we need to trim it. 2124 */ 2125 m->m_len -= ETHER_CRC_LEN; 2126 2127 *sc->sc_rxtailp = NULL; 2128 len = m->m_len + sc->sc_rxlen; 2129 m = sc->sc_rxhead; 2130 2131 sip_rxchain_reset(sc); 2132 2133 /* 2134 * If an error occurred, update stats and drop the packet. 2135 */ 2136 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2137 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2138 ifp->if_ierrors++; 2139 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2140 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2141 /* Receive overrun handled elsewhere. */ 2142 printf("%s: receive descriptor error\n", 2143 device_xname(sc->sc_dev)); 2144 } 2145 #define PRINTERR(bit, str) \ 2146 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2147 (cmdsts & (bit)) != 0) \ 2148 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2149 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2150 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2151 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2152 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2153 #undef PRINTERR 2154 m_freem(m); 2155 continue; 2156 } 2157 2158 /* 2159 * If the packet is small enough to fit in a 2160 * single header mbuf, allocate one and copy 2161 * the data into it. This greatly reduces 2162 * memory consumption when we receive lots 2163 * of small packets. 2164 */ 2165 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2166 struct mbuf *nm; 2167 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2168 if (nm == NULL) { 2169 ifp->if_ierrors++; 2170 m_freem(m); 2171 continue; 2172 } 2173 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2174 nm->m_data += 2; 2175 nm->m_pkthdr.len = nm->m_len = len; 2176 m_copydata(m, 0, len, mtod(nm, void *)); 2177 m_freem(m); 2178 m = nm; 2179 } 2180 #ifndef __NO_STRICT_ALIGNMENT 2181 else { 2182 /* 2183 * The DP83820's receive buffers must be 4-byte 2184 * aligned. But this means that the data after 2185 * the Ethernet header is misaligned. To compensate, 2186 * we have artificially shortened the buffer size 2187 * in the descriptor, and we do an overlapping copy 2188 * of the data two bytes further in (in the first 2189 * buffer of the chain only). 2190 */ 2191 memmove(mtod(m, char *) + 2, mtod(m, void *), 2192 m->m_len); 2193 m->m_data += 2; 2194 } 2195 #endif /* ! __NO_STRICT_ALIGNMENT */ 2196 2197 /* 2198 * If VLANs are enabled, VLAN packets have been unwrapped 2199 * for us. Associate the tag with the packet. 2200 */ 2201 2202 /* 2203 * Again, byte swapping is tricky. Hardware provided 2204 * the tag in the network byte order, but extsts was 2205 * passed through le32toh() in the meantime. On a 2206 * big-endian machine, we need to swap it again. On a 2207 * little-endian machine, we need to convert from the 2208 * network to host byte order. This means that we must 2209 * swap it in any case, so unconditional swap instead 2210 * of htons() is used. 2211 */ 2212 if ((extsts & EXTSTS_VPKT) != 0) { 2213 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2214 continue); 2215 } 2216 2217 /* 2218 * Set the incoming checksum information for the 2219 * packet. 2220 */ 2221 if ((extsts & EXTSTS_IPPKT) != 0) { 2222 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2223 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2224 if (extsts & EXTSTS_Rx_IPERR) 2225 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2226 if (extsts & EXTSTS_TCPPKT) { 2227 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2228 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2229 if (extsts & EXTSTS_Rx_TCPERR) 2230 m->m_pkthdr.csum_flags |= 2231 M_CSUM_TCP_UDP_BAD; 2232 } else if (extsts & EXTSTS_UDPPKT) { 2233 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2234 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2235 if (extsts & EXTSTS_Rx_UDPERR) 2236 m->m_pkthdr.csum_flags |= 2237 M_CSUM_TCP_UDP_BAD; 2238 } 2239 } 2240 2241 ifp->if_ipackets++; 2242 m->m_pkthdr.rcvif = ifp; 2243 m->m_pkthdr.len = len; 2244 2245 /* 2246 * Pass this up to any BPF listeners, but only 2247 * pass if up the stack if it's for us. 2248 */ 2249 bpf_mtap(ifp, m); 2250 2251 /* Pass it on. */ 2252 (*ifp->if_input)(ifp, m); 2253 } 2254 2255 /* Update the receive pointer. */ 2256 sc->sc_rxptr = i; 2257 } 2258 2259 /* 2260 * sip_rxintr: 2261 * 2262 * Helper; handle receive interrupts on 10/100 parts. 2263 */ 2264 static void 2265 sip_rxintr(struct sip_softc *sc) 2266 { 2267 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2268 struct sip_rxsoft *rxs; 2269 struct mbuf *m; 2270 u_int32_t cmdsts; 2271 int i, len; 2272 2273 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2274 rxs = &sc->sc_rxsoft[i]; 2275 2276 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2277 2278 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2279 2280 /* 2281 * NOTE: OWN is set if owned by _consumer_. We're the 2282 * consumer of the receive ring, so if the bit is clear, 2283 * we have processed all of the packets. 2284 */ 2285 if ((cmdsts & CMDSTS_OWN) == 0) { 2286 /* 2287 * We have processed all of the receive buffers. 2288 */ 2289 break; 2290 } 2291 2292 /* 2293 * If any collisions were seen on the wire, count one. 2294 */ 2295 if (cmdsts & CMDSTS_Rx_COL) 2296 ifp->if_collisions++; 2297 2298 /* 2299 * If an error occurred, update stats, clear the status 2300 * word, and leave the packet buffer in place. It will 2301 * simply be reused the next time the ring comes around. 2302 */ 2303 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2304 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2305 ifp->if_ierrors++; 2306 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2307 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2308 /* Receive overrun handled elsewhere. */ 2309 printf("%s: receive descriptor error\n", 2310 device_xname(sc->sc_dev)); 2311 } 2312 #define PRINTERR(bit, str) \ 2313 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2314 (cmdsts & (bit)) != 0) \ 2315 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2316 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2317 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2318 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2319 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2320 #undef PRINTERR 2321 sip_init_rxdesc(sc, i); 2322 continue; 2323 } 2324 2325 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2326 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2327 2328 /* 2329 * No errors; receive the packet. Note, the SiS 900 2330 * includes the CRC with every packet. 2331 */ 2332 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2333 2334 #ifdef __NO_STRICT_ALIGNMENT 2335 /* 2336 * If the packet is small enough to fit in a 2337 * single header mbuf, allocate one and copy 2338 * the data into it. This greatly reduces 2339 * memory consumption when we receive lots 2340 * of small packets. 2341 * 2342 * Otherwise, we add a new buffer to the receive 2343 * chain. If this fails, we drop the packet and 2344 * recycle the old buffer. 2345 */ 2346 if (sip_copy_small != 0 && len <= MHLEN) { 2347 MGETHDR(m, M_DONTWAIT, MT_DATA); 2348 if (m == NULL) 2349 goto dropit; 2350 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2351 memcpy(mtod(m, void *), 2352 mtod(rxs->rxs_mbuf, void *), len); 2353 sip_init_rxdesc(sc, i); 2354 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2355 rxs->rxs_dmamap->dm_mapsize, 2356 BUS_DMASYNC_PREREAD); 2357 } else { 2358 m = rxs->rxs_mbuf; 2359 if (sipcom_add_rxbuf(sc, i) != 0) { 2360 dropit: 2361 ifp->if_ierrors++; 2362 sip_init_rxdesc(sc, i); 2363 bus_dmamap_sync(sc->sc_dmat, 2364 rxs->rxs_dmamap, 0, 2365 rxs->rxs_dmamap->dm_mapsize, 2366 BUS_DMASYNC_PREREAD); 2367 continue; 2368 } 2369 } 2370 #else 2371 /* 2372 * The SiS 900's receive buffers must be 4-byte aligned. 2373 * But this means that the data after the Ethernet header 2374 * is misaligned. We must allocate a new buffer and 2375 * copy the data, shifted forward 2 bytes. 2376 */ 2377 MGETHDR(m, M_DONTWAIT, MT_DATA); 2378 if (m == NULL) { 2379 dropit: 2380 ifp->if_ierrors++; 2381 sip_init_rxdesc(sc, i); 2382 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2383 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2384 continue; 2385 } 2386 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2387 if (len > (MHLEN - 2)) { 2388 MCLGET(m, M_DONTWAIT); 2389 if ((m->m_flags & M_EXT) == 0) { 2390 m_freem(m); 2391 goto dropit; 2392 } 2393 } 2394 m->m_data += 2; 2395 2396 /* 2397 * Note that we use clusters for incoming frames, so the 2398 * buffer is virtually contiguous. 2399 */ 2400 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2401 2402 /* Allow the receive descriptor to continue using its mbuf. */ 2403 sip_init_rxdesc(sc, i); 2404 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2405 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2406 #endif /* __NO_STRICT_ALIGNMENT */ 2407 2408 ifp->if_ipackets++; 2409 m->m_pkthdr.rcvif = ifp; 2410 m->m_pkthdr.len = m->m_len = len; 2411 2412 /* 2413 * Pass this up to any BPF listeners, but only 2414 * pass if up the stack if it's for us. 2415 */ 2416 bpf_mtap(ifp, m); 2417 2418 /* Pass it on. */ 2419 (*ifp->if_input)(ifp, m); 2420 } 2421 2422 /* Update the receive pointer. */ 2423 sc->sc_rxptr = i; 2424 } 2425 2426 /* 2427 * sip_tick: 2428 * 2429 * One second timer, used to tick the MII. 2430 */ 2431 static void 2432 sipcom_tick(void *arg) 2433 { 2434 struct sip_softc *sc = arg; 2435 int s; 2436 2437 s = splnet(); 2438 #ifdef SIP_EVENT_COUNTERS 2439 if (sc->sc_gigabit) { 2440 /* Read PAUSE related counts from MIB registers. */ 2441 sc->sc_ev_rxpause.ev_count += 2442 bus_space_read_4(sc->sc_st, sc->sc_sh, 2443 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2444 sc->sc_ev_txpause.ev_count += 2445 bus_space_read_4(sc->sc_st, sc->sc_sh, 2446 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2447 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2448 } 2449 #endif /* SIP_EVENT_COUNTERS */ 2450 mii_tick(&sc->sc_mii); 2451 splx(s); 2452 2453 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2454 } 2455 2456 /* 2457 * sip_reset: 2458 * 2459 * Perform a soft reset on the SiS 900. 2460 */ 2461 static bool 2462 sipcom_reset(struct sip_softc *sc) 2463 { 2464 bus_space_tag_t st = sc->sc_st; 2465 bus_space_handle_t sh = sc->sc_sh; 2466 int i; 2467 2468 bus_space_write_4(st, sh, SIP_IER, 0); 2469 bus_space_write_4(st, sh, SIP_IMR, 0); 2470 bus_space_write_4(st, sh, SIP_RFCR, 0); 2471 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2472 2473 for (i = 0; i < SIP_TIMEOUT; i++) { 2474 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2475 break; 2476 delay(2); 2477 } 2478 2479 if (i == SIP_TIMEOUT) { 2480 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2481 return false; 2482 } 2483 2484 delay(1000); 2485 2486 if (sc->sc_gigabit) { 2487 /* 2488 * Set the general purpose I/O bits. Do it here in case we 2489 * need to have GPIO set up to talk to the media interface. 2490 */ 2491 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2492 delay(1000); 2493 } 2494 return true; 2495 } 2496 2497 static void 2498 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2499 { 2500 u_int32_t reg; 2501 bus_space_tag_t st = sc->sc_st; 2502 bus_space_handle_t sh = sc->sc_sh; 2503 /* 2504 * Initialize the VLAN/IP receive control register. 2505 * We enable checksum computation on all incoming 2506 * packets, and do not reject packets w/ bad checksums. 2507 */ 2508 reg = 0; 2509 if (capenable & 2510 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2511 reg |= VRCR_IPEN; 2512 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2513 reg |= VRCR_VTDEN|VRCR_VTREN; 2514 bus_space_write_4(st, sh, SIP_VRCR, reg); 2515 2516 /* 2517 * Initialize the VLAN/IP transmit control register. 2518 * We enable outgoing checksum computation on a 2519 * per-packet basis. 2520 */ 2521 reg = 0; 2522 if (capenable & 2523 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2524 reg |= VTCR_PPCHK; 2525 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2526 reg |= VTCR_VPPTI; 2527 bus_space_write_4(st, sh, SIP_VTCR, reg); 2528 2529 /* 2530 * If we're using VLANs, initialize the VLAN data register. 2531 * To understand why we bswap the VLAN Ethertype, see section 2532 * 4.2.36 of the DP83820 manual. 2533 */ 2534 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2535 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2536 } 2537 2538 /* 2539 * sip_init: [ ifnet interface function ] 2540 * 2541 * Initialize the interface. Must be called at splnet(). 2542 */ 2543 static int 2544 sipcom_init(struct ifnet *ifp) 2545 { 2546 struct sip_softc *sc = ifp->if_softc; 2547 bus_space_tag_t st = sc->sc_st; 2548 bus_space_handle_t sh = sc->sc_sh; 2549 struct sip_txsoft *txs; 2550 struct sip_rxsoft *rxs; 2551 struct sip_desc *sipd; 2552 int i, error = 0; 2553 2554 if (device_is_active(sc->sc_dev)) { 2555 /* 2556 * Cancel any pending I/O. 2557 */ 2558 sipcom_stop(ifp, 0); 2559 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2560 !device_is_active(sc->sc_dev)) 2561 return 0; 2562 2563 /* 2564 * Reset the chip to a known state. 2565 */ 2566 if (!sipcom_reset(sc)) 2567 return EBUSY; 2568 2569 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2570 /* 2571 * DP83815 manual, page 78: 2572 * 4.4 Recommended Registers Configuration 2573 * For optimum performance of the DP83815, version noted 2574 * as DP83815CVNG (SRR = 203h), the listed register 2575 * modifications must be followed in sequence... 2576 * 2577 * It's not clear if this should be 302h or 203h because that 2578 * chip name is listed as SRR 302h in the description of the 2579 * SRR register. However, my revision 302h DP83815 on the 2580 * Netgear FA311 purchased in 02/2001 needs these settings 2581 * to avoid tons of errors in AcceptPerfectMatch (non- 2582 * IFF_PROMISC) mode. I do not know if other revisions need 2583 * this set or not. [briggs -- 09 March 2001] 2584 * 2585 * Note that only the low-order 12 bits of 0xe4 are documented 2586 * and that this sets reserved bits in that register. 2587 */ 2588 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2589 2590 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2591 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2592 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2593 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2594 2595 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2596 } 2597 2598 /* 2599 * Initialize the transmit descriptor ring. 2600 */ 2601 for (i = 0; i < sc->sc_ntxdesc; i++) { 2602 sipd = &sc->sc_txdescs[i]; 2603 memset(sipd, 0, sizeof(struct sip_desc)); 2604 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2605 } 2606 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2607 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2608 sc->sc_txfree = sc->sc_ntxdesc; 2609 sc->sc_txnext = 0; 2610 sc->sc_txwin = 0; 2611 2612 /* 2613 * Initialize the transmit job descriptors. 2614 */ 2615 SIMPLEQ_INIT(&sc->sc_txfreeq); 2616 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2617 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2618 txs = &sc->sc_txsoft[i]; 2619 txs->txs_mbuf = NULL; 2620 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2621 } 2622 2623 /* 2624 * Initialize the receive descriptor and receive job 2625 * descriptor rings. 2626 */ 2627 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2628 rxs = &sc->sc_rxsoft[i]; 2629 if (rxs->rxs_mbuf == NULL) { 2630 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2631 printf("%s: unable to allocate or map rx " 2632 "buffer %d, error = %d\n", 2633 device_xname(sc->sc_dev), i, error); 2634 /* 2635 * XXX Should attempt to run with fewer receive 2636 * XXX buffers instead of just failing. 2637 */ 2638 sipcom_rxdrain(sc); 2639 goto out; 2640 } 2641 } else 2642 sip_init_rxdesc(sc, i); 2643 } 2644 sc->sc_rxptr = 0; 2645 sc->sc_rxdiscard = 0; 2646 sip_rxchain_reset(sc); 2647 2648 /* 2649 * Set the configuration register; it's already initialized 2650 * in sip_attach(). 2651 */ 2652 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2653 2654 /* 2655 * Initialize the prototype TXCFG register. 2656 */ 2657 if (sc->sc_gigabit) { 2658 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2659 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2660 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2661 SIP_SIS900_REV(sc, SIS_REV_960) || 2662 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2663 (sc->sc_cfg & CFG_EDBMASTEN)) { 2664 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2665 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2666 } else { 2667 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2668 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2669 } 2670 2671 sc->sc_txcfg |= TXCFG_ATP | 2672 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2673 sc->sc_tx_drain_thresh; 2674 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2675 2676 /* 2677 * Initialize the receive drain threshold if we have never 2678 * done so. 2679 */ 2680 if (sc->sc_rx_drain_thresh == 0) { 2681 /* 2682 * XXX This value should be tuned. This is set to the 2683 * maximum of 248 bytes, and we may be able to improve 2684 * performance by decreasing it (although we should never 2685 * set this value lower than 2; 14 bytes are required to 2686 * filter the packet). 2687 */ 2688 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2689 } 2690 2691 /* 2692 * Initialize the prototype RXCFG register. 2693 */ 2694 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2695 /* 2696 * Accept long packets (including FCS) so we can handle 2697 * 802.1q-tagged frames and jumbo frames properly. 2698 */ 2699 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2700 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2701 sc->sc_rxcfg |= RXCFG_ALP; 2702 2703 /* 2704 * Checksum offloading is disabled if the user selects an MTU 2705 * larger than 8109. (FreeBSD says 8152, but there is emperical 2706 * evidence that >8109 does not work on some boards, such as the 2707 * Planex GN-1000TE). 2708 */ 2709 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2710 (ifp->if_capenable & 2711 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2712 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2713 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2714 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2715 "disabled.\n", device_xname(sc->sc_dev)); 2716 ifp->if_capenable &= 2717 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2718 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2719 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2720 ifp->if_csum_flags_tx = 0; 2721 ifp->if_csum_flags_rx = 0; 2722 } 2723 2724 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2725 2726 if (sc->sc_gigabit) 2727 sipcom_dp83820_init(sc, ifp->if_capenable); 2728 2729 /* 2730 * Give the transmit and receive rings to the chip. 2731 */ 2732 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2733 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2734 2735 /* 2736 * Initialize the interrupt mask. 2737 */ 2738 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2739 sc->sc_bits.b_isr_sserr | 2740 sc->sc_bits.b_isr_rmabt | 2741 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2742 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2743 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2744 2745 /* Set up the receive filter. */ 2746 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2747 2748 /* 2749 * Tune sc_rx_flow_thresh. 2750 * XXX "More than 8KB" is too short for jumbo frames. 2751 * XXX TODO: Threshold value should be user-settable. 2752 */ 2753 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2754 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2755 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2756 2757 /* 2758 * Set the current media. Do this after initializing the prototype 2759 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2760 * control. 2761 */ 2762 if ((error = ether_mediachange(ifp)) != 0) 2763 goto out; 2764 2765 /* 2766 * Set the interrupt hold-off timer to 100us. 2767 */ 2768 if (sc->sc_gigabit) 2769 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2770 2771 /* 2772 * Enable interrupts. 2773 */ 2774 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2775 2776 /* 2777 * Start the transmit and receive processes. 2778 */ 2779 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2780 2781 /* 2782 * Start the one second MII clock. 2783 */ 2784 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2785 2786 /* 2787 * ...all done! 2788 */ 2789 ifp->if_flags |= IFF_RUNNING; 2790 ifp->if_flags &= ~IFF_OACTIVE; 2791 sc->sc_if_flags = ifp->if_flags; 2792 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2793 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2794 sc->sc_prev.if_capenable = ifp->if_capenable; 2795 2796 out: 2797 if (error) 2798 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2799 return (error); 2800 } 2801 2802 /* 2803 * sip_drain: 2804 * 2805 * Drain the receive queue. 2806 */ 2807 static void 2808 sipcom_rxdrain(struct sip_softc *sc) 2809 { 2810 struct sip_rxsoft *rxs; 2811 int i; 2812 2813 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2814 rxs = &sc->sc_rxsoft[i]; 2815 if (rxs->rxs_mbuf != NULL) { 2816 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2817 m_freem(rxs->rxs_mbuf); 2818 rxs->rxs_mbuf = NULL; 2819 } 2820 } 2821 } 2822 2823 /* 2824 * sip_stop: [ ifnet interface function ] 2825 * 2826 * Stop transmission on the interface. 2827 */ 2828 static void 2829 sipcom_stop(struct ifnet *ifp, int disable) 2830 { 2831 struct sip_softc *sc = ifp->if_softc; 2832 bus_space_tag_t st = sc->sc_st; 2833 bus_space_handle_t sh = sc->sc_sh; 2834 struct sip_txsoft *txs; 2835 u_int32_t cmdsts = 0; /* DEBUG */ 2836 2837 /* 2838 * Stop the one second clock. 2839 */ 2840 callout_stop(&sc->sc_tick_ch); 2841 2842 /* Down the MII. */ 2843 mii_down(&sc->sc_mii); 2844 2845 if (device_is_active(sc->sc_dev)) { 2846 /* 2847 * Disable interrupts. 2848 */ 2849 bus_space_write_4(st, sh, SIP_IER, 0); 2850 2851 /* 2852 * Stop receiver and transmitter. 2853 */ 2854 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2855 } 2856 2857 /* 2858 * Release any queued transmit buffers. 2859 */ 2860 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2861 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2862 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2863 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2864 CMDSTS_INTR) == 0) 2865 printf("%s: sip_stop: last descriptor does not " 2866 "have INTR bit set\n", device_xname(sc->sc_dev)); 2867 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2868 #ifdef DIAGNOSTIC 2869 if (txs->txs_mbuf == NULL) { 2870 printf("%s: dirty txsoft with no mbuf chain\n", 2871 device_xname(sc->sc_dev)); 2872 panic("sip_stop"); 2873 } 2874 #endif 2875 cmdsts |= /* DEBUG */ 2876 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2877 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2878 m_freem(txs->txs_mbuf); 2879 txs->txs_mbuf = NULL; 2880 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2881 } 2882 2883 /* 2884 * Mark the interface down and cancel the watchdog timer. 2885 */ 2886 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2887 ifp->if_timer = 0; 2888 2889 if (disable) 2890 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2891 2892 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2893 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2894 printf("%s: sip_stop: no INTR bits set in dirty tx " 2895 "descriptors\n", device_xname(sc->sc_dev)); 2896 } 2897 2898 /* 2899 * sip_read_eeprom: 2900 * 2901 * Read data from the serial EEPROM. 2902 */ 2903 static void 2904 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2905 u_int16_t *data) 2906 { 2907 bus_space_tag_t st = sc->sc_st; 2908 bus_space_handle_t sh = sc->sc_sh; 2909 u_int16_t reg; 2910 int i, x; 2911 2912 for (i = 0; i < wordcnt; i++) { 2913 /* Send CHIP SELECT. */ 2914 reg = EROMAR_EECS; 2915 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2916 2917 /* Shift in the READ opcode. */ 2918 for (x = 3; x > 0; x--) { 2919 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2920 reg |= EROMAR_EEDI; 2921 else 2922 reg &= ~EROMAR_EEDI; 2923 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2924 bus_space_write_4(st, sh, SIP_EROMAR, 2925 reg | EROMAR_EESK); 2926 delay(4); 2927 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2928 delay(4); 2929 } 2930 2931 /* Shift in address. */ 2932 for (x = 6; x > 0; x--) { 2933 if ((word + i) & (1 << (x - 1))) 2934 reg |= EROMAR_EEDI; 2935 else 2936 reg &= ~EROMAR_EEDI; 2937 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2938 bus_space_write_4(st, sh, SIP_EROMAR, 2939 reg | EROMAR_EESK); 2940 delay(4); 2941 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2942 delay(4); 2943 } 2944 2945 /* Shift out data. */ 2946 reg = EROMAR_EECS; 2947 data[i] = 0; 2948 for (x = 16; x > 0; x--) { 2949 bus_space_write_4(st, sh, SIP_EROMAR, 2950 reg | EROMAR_EESK); 2951 delay(4); 2952 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2953 data[i] |= (1 << (x - 1)); 2954 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2955 delay(4); 2956 } 2957 2958 /* Clear CHIP SELECT. */ 2959 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2960 delay(4); 2961 } 2962 } 2963 2964 /* 2965 * sipcom_add_rxbuf: 2966 * 2967 * Add a receive buffer to the indicated descriptor. 2968 */ 2969 static int 2970 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2971 { 2972 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2973 struct mbuf *m; 2974 int error; 2975 2976 MGETHDR(m, M_DONTWAIT, MT_DATA); 2977 if (m == NULL) 2978 return (ENOBUFS); 2979 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2980 2981 MCLGET(m, M_DONTWAIT); 2982 if ((m->m_flags & M_EXT) == 0) { 2983 m_freem(m); 2984 return (ENOBUFS); 2985 } 2986 2987 /* XXX I don't believe this is necessary. --dyoung */ 2988 if (sc->sc_gigabit) 2989 m->m_len = sc->sc_parm->p_rxbuf_len; 2990 2991 if (rxs->rxs_mbuf != NULL) 2992 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2993 2994 rxs->rxs_mbuf = m; 2995 2996 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2997 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2998 BUS_DMA_READ|BUS_DMA_NOWAIT); 2999 if (error) { 3000 printf("%s: can't load rx DMA map %d, error = %d\n", 3001 device_xname(sc->sc_dev), idx, error); 3002 panic("%s", __func__); /* XXX */ 3003 } 3004 3005 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3006 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3007 3008 sip_init_rxdesc(sc, idx); 3009 3010 return (0); 3011 } 3012 3013 /* 3014 * sip_sis900_set_filter: 3015 * 3016 * Set up the receive filter. 3017 */ 3018 static void 3019 sipcom_sis900_set_filter(struct sip_softc *sc) 3020 { 3021 bus_space_tag_t st = sc->sc_st; 3022 bus_space_handle_t sh = sc->sc_sh; 3023 struct ethercom *ec = &sc->sc_ethercom; 3024 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3025 struct ether_multi *enm; 3026 const u_int8_t *cp; 3027 struct ether_multistep step; 3028 u_int32_t crc, mchash[16]; 3029 3030 /* 3031 * Initialize the prototype RFCR. 3032 */ 3033 sc->sc_rfcr = RFCR_RFEN; 3034 if (ifp->if_flags & IFF_BROADCAST) 3035 sc->sc_rfcr |= RFCR_AAB; 3036 if (ifp->if_flags & IFF_PROMISC) { 3037 sc->sc_rfcr |= RFCR_AAP; 3038 goto allmulti; 3039 } 3040 3041 /* 3042 * Set up the multicast address filter by passing all multicast 3043 * addresses through a CRC generator, and then using the high-order 3044 * 6 bits as an index into the 128 bit multicast hash table (only 3045 * the lower 16 bits of each 32 bit multicast hash register are 3046 * valid). The high order bits select the register, while the 3047 * rest of the bits select the bit within the register. 3048 */ 3049 3050 memset(mchash, 0, sizeof(mchash)); 3051 3052 /* 3053 * SiS900 (at least SiS963) requires us to register the address of 3054 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3055 */ 3056 crc = 0x0ed423f9; 3057 3058 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3059 SIP_SIS900_REV(sc, SIS_REV_960) || 3060 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3061 /* Just want the 8 most significant bits. */ 3062 crc >>= 24; 3063 } else { 3064 /* Just want the 7 most significant bits. */ 3065 crc >>= 25; 3066 } 3067 3068 /* Set the corresponding bit in the hash table. */ 3069 mchash[crc >> 4] |= 1 << (crc & 0xf); 3070 3071 ETHER_FIRST_MULTI(step, ec, enm); 3072 while (enm != NULL) { 3073 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3074 /* 3075 * We must listen to a range of multicast addresses. 3076 * For now, just accept all multicasts, rather than 3077 * trying to set only those filter bits needed to match 3078 * the range. (At this time, the only use of address 3079 * ranges is for IP multicast routing, for which the 3080 * range is big enough to require all bits set.) 3081 */ 3082 goto allmulti; 3083 } 3084 3085 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3086 3087 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3088 SIP_SIS900_REV(sc, SIS_REV_960) || 3089 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3090 /* Just want the 8 most significant bits. */ 3091 crc >>= 24; 3092 } else { 3093 /* Just want the 7 most significant bits. */ 3094 crc >>= 25; 3095 } 3096 3097 /* Set the corresponding bit in the hash table. */ 3098 mchash[crc >> 4] |= 1 << (crc & 0xf); 3099 3100 ETHER_NEXT_MULTI(step, enm); 3101 } 3102 3103 ifp->if_flags &= ~IFF_ALLMULTI; 3104 goto setit; 3105 3106 allmulti: 3107 ifp->if_flags |= IFF_ALLMULTI; 3108 sc->sc_rfcr |= RFCR_AAM; 3109 3110 setit: 3111 #define FILTER_EMIT(addr, data) \ 3112 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3113 delay(1); \ 3114 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3115 delay(1) 3116 3117 /* 3118 * Disable receive filter, and program the node address. 3119 */ 3120 cp = CLLADDR(ifp->if_sadl); 3121 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3122 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3123 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3124 3125 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3126 /* 3127 * Program the multicast hash table. 3128 */ 3129 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3130 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3131 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3132 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3133 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3134 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3135 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3136 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3137 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3138 SIP_SIS900_REV(sc, SIS_REV_960) || 3139 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3140 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3141 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3142 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3143 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3144 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3145 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3146 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3147 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3148 } 3149 } 3150 #undef FILTER_EMIT 3151 3152 /* 3153 * Re-enable the receiver filter. 3154 */ 3155 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3156 } 3157 3158 /* 3159 * sip_dp83815_set_filter: 3160 * 3161 * Set up the receive filter. 3162 */ 3163 static void 3164 sipcom_dp83815_set_filter(struct sip_softc *sc) 3165 { 3166 bus_space_tag_t st = sc->sc_st; 3167 bus_space_handle_t sh = sc->sc_sh; 3168 struct ethercom *ec = &sc->sc_ethercom; 3169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3170 struct ether_multi *enm; 3171 const u_int8_t *cp; 3172 struct ether_multistep step; 3173 u_int32_t crc, hash, slot, bit; 3174 #define MCHASH_NWORDS_83820 128 3175 #define MCHASH_NWORDS_83815 32 3176 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3177 u_int16_t mchash[MCHASH_NWORDS]; 3178 int i; 3179 3180 /* 3181 * Initialize the prototype RFCR. 3182 * Enable the receive filter, and accept on 3183 * Perfect (destination address) Match 3184 * If IFF_BROADCAST, also accept all broadcast packets. 3185 * If IFF_PROMISC, accept all unicast packets (and later, set 3186 * IFF_ALLMULTI and accept all multicast, too). 3187 */ 3188 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3189 if (ifp->if_flags & IFF_BROADCAST) 3190 sc->sc_rfcr |= RFCR_AAB; 3191 if (ifp->if_flags & IFF_PROMISC) { 3192 sc->sc_rfcr |= RFCR_AAP; 3193 goto allmulti; 3194 } 3195 3196 /* 3197 * Set up the DP83820/DP83815 multicast address filter by 3198 * passing all multicast addresses through a CRC generator, 3199 * and then using the high-order 11/9 bits as an index into 3200 * the 2048/512 bit multicast hash table. The high-order 3201 * 7/5 bits select the slot, while the low-order 4 bits 3202 * select the bit within the slot. Note that only the low 3203 * 16-bits of each filter word are used, and there are 3204 * 128/32 filter words. 3205 */ 3206 3207 memset(mchash, 0, sizeof(mchash)); 3208 3209 ifp->if_flags &= ~IFF_ALLMULTI; 3210 ETHER_FIRST_MULTI(step, ec, enm); 3211 if (enm == NULL) 3212 goto setit; 3213 while (enm != NULL) { 3214 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3215 /* 3216 * We must listen to a range of multicast addresses. 3217 * For now, just accept all multicasts, rather than 3218 * trying to set only those filter bits needed to match 3219 * the range. (At this time, the only use of address 3220 * ranges is for IP multicast routing, for which the 3221 * range is big enough to require all bits set.) 3222 */ 3223 goto allmulti; 3224 } 3225 3226 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3227 3228 if (sc->sc_gigabit) { 3229 /* Just want the 11 most significant bits. */ 3230 hash = crc >> 21; 3231 } else { 3232 /* Just want the 9 most significant bits. */ 3233 hash = crc >> 23; 3234 } 3235 3236 slot = hash >> 4; 3237 bit = hash & 0xf; 3238 3239 /* Set the corresponding bit in the hash table. */ 3240 mchash[slot] |= 1 << bit; 3241 3242 ETHER_NEXT_MULTI(step, enm); 3243 } 3244 sc->sc_rfcr |= RFCR_MHEN; 3245 goto setit; 3246 3247 allmulti: 3248 ifp->if_flags |= IFF_ALLMULTI; 3249 sc->sc_rfcr |= RFCR_AAM; 3250 3251 setit: 3252 #define FILTER_EMIT(addr, data) \ 3253 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3254 delay(1); \ 3255 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3256 delay(1) 3257 3258 /* 3259 * Disable receive filter, and program the node address. 3260 */ 3261 cp = CLLADDR(ifp->if_sadl); 3262 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3263 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3264 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3265 3266 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3267 int nwords = 3268 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3269 /* 3270 * Program the multicast hash table. 3271 */ 3272 for (i = 0; i < nwords; i++) { 3273 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3274 } 3275 } 3276 #undef FILTER_EMIT 3277 #undef MCHASH_NWORDS 3278 #undef MCHASH_NWORDS_83815 3279 #undef MCHASH_NWORDS_83820 3280 3281 /* 3282 * Re-enable the receiver filter. 3283 */ 3284 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3285 } 3286 3287 /* 3288 * sip_dp83820_mii_readreg: [mii interface function] 3289 * 3290 * Read a PHY register on the MII of the DP83820. 3291 */ 3292 static int 3293 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3294 { 3295 struct sip_softc *sc = device_private(self); 3296 3297 if (sc->sc_cfg & CFG_TBI_EN) { 3298 bus_addr_t tbireg; 3299 int rv; 3300 3301 if (phy != 0) 3302 return (0); 3303 3304 switch (reg) { 3305 case MII_BMCR: tbireg = SIP_TBICR; break; 3306 case MII_BMSR: tbireg = SIP_TBISR; break; 3307 case MII_ANAR: tbireg = SIP_TANAR; break; 3308 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3309 case MII_ANER: tbireg = SIP_TANER; break; 3310 case MII_EXTSR: 3311 /* 3312 * Don't even bother reading the TESR register. 3313 * The manual documents that the device has 3314 * 1000baseX full/half capability, but the 3315 * register itself seems read back 0 on some 3316 * boards. Just hard-code the result. 3317 */ 3318 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3319 3320 default: 3321 return (0); 3322 } 3323 3324 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3325 if (tbireg == SIP_TBISR) { 3326 /* LINK and ACOMP are switched! */ 3327 int val = rv; 3328 3329 rv = 0; 3330 if (val & TBISR_MR_LINK_STATUS) 3331 rv |= BMSR_LINK; 3332 if (val & TBISR_MR_AN_COMPLETE) 3333 rv |= BMSR_ACOMP; 3334 3335 /* 3336 * The manual claims this register reads back 0 3337 * on hard and soft reset. But we want to let 3338 * the gentbi driver know that we support auto- 3339 * negotiation, so hard-code this bit in the 3340 * result. 3341 */ 3342 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3343 } 3344 3345 return (rv); 3346 } 3347 3348 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3349 } 3350 3351 /* 3352 * sip_dp83820_mii_writereg: [mii interface function] 3353 * 3354 * Write a PHY register on the MII of the DP83820. 3355 */ 3356 static void 3357 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3358 { 3359 struct sip_softc *sc = device_private(self); 3360 3361 if (sc->sc_cfg & CFG_TBI_EN) { 3362 bus_addr_t tbireg; 3363 3364 if (phy != 0) 3365 return; 3366 3367 switch (reg) { 3368 case MII_BMCR: tbireg = SIP_TBICR; break; 3369 case MII_ANAR: tbireg = SIP_TANAR; break; 3370 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3371 default: 3372 return; 3373 } 3374 3375 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3376 return; 3377 } 3378 3379 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3380 } 3381 3382 /* 3383 * sip_dp83820_mii_statchg: [mii interface function] 3384 * 3385 * Callback from MII layer when media changes. 3386 */ 3387 static void 3388 sipcom_dp83820_mii_statchg(device_t self) 3389 { 3390 struct sip_softc *sc = device_private(self); 3391 struct mii_data *mii = &sc->sc_mii; 3392 u_int32_t cfg, pcr; 3393 3394 /* 3395 * Get flow control negotiation result. 3396 */ 3397 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3398 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3399 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3400 mii->mii_media_active &= ~IFM_ETH_FMASK; 3401 } 3402 3403 /* 3404 * Update TXCFG for full-duplex operation. 3405 */ 3406 if ((mii->mii_media_active & IFM_FDX) != 0) 3407 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3408 else 3409 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3410 3411 /* 3412 * Update RXCFG for full-duplex or loopback. 3413 */ 3414 if ((mii->mii_media_active & IFM_FDX) != 0 || 3415 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3416 sc->sc_rxcfg |= RXCFG_ATX; 3417 else 3418 sc->sc_rxcfg &= ~RXCFG_ATX; 3419 3420 /* 3421 * Update CFG for MII/GMII. 3422 */ 3423 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3424 cfg = sc->sc_cfg | CFG_MODE_1000; 3425 else 3426 cfg = sc->sc_cfg; 3427 3428 /* 3429 * 802.3x flow control. 3430 */ 3431 pcr = 0; 3432 if (sc->sc_flowflags & IFM_FLOW) { 3433 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3434 pcr |= sc->sc_rx_flow_thresh; 3435 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3436 pcr |= PCR_PSEN | PCR_PS_MCAST; 3437 } 3438 3439 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3440 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3441 sc->sc_txcfg); 3442 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3443 sc->sc_rxcfg); 3444 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3445 } 3446 3447 /* 3448 * sip_mii_bitbang_read: [mii bit-bang interface function] 3449 * 3450 * Read the MII serial port for the MII bit-bang module. 3451 */ 3452 static u_int32_t 3453 sipcom_mii_bitbang_read(device_t self) 3454 { 3455 struct sip_softc *sc = device_private(self); 3456 3457 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3458 } 3459 3460 /* 3461 * sip_mii_bitbang_write: [mii big-bang interface function] 3462 * 3463 * Write the MII serial port for the MII bit-bang module. 3464 */ 3465 static void 3466 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3467 { 3468 struct sip_softc *sc = device_private(self); 3469 3470 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3471 } 3472 3473 /* 3474 * sip_sis900_mii_readreg: [mii interface function] 3475 * 3476 * Read a PHY register on the MII. 3477 */ 3478 static int 3479 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3480 { 3481 struct sip_softc *sc = device_private(self); 3482 u_int32_t enphy; 3483 3484 /* 3485 * The PHY of recent SiS chipsets is accessed through bitbang 3486 * operations. 3487 */ 3488 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3489 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3490 phy, reg); 3491 3492 #ifndef SIS900_MII_RESTRICT 3493 /* 3494 * The SiS 900 has only an internal PHY on the MII. Only allow 3495 * MII address 0. 3496 */ 3497 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3498 return (0); 3499 #endif 3500 3501 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3502 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3503 ENPHY_RWCMD | ENPHY_ACCESS); 3504 do { 3505 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3506 } while (enphy & ENPHY_ACCESS); 3507 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3508 } 3509 3510 /* 3511 * sip_sis900_mii_writereg: [mii interface function] 3512 * 3513 * Write a PHY register on the MII. 3514 */ 3515 static void 3516 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3517 { 3518 struct sip_softc *sc = device_private(self); 3519 u_int32_t enphy; 3520 3521 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3522 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3523 phy, reg, val); 3524 return; 3525 } 3526 3527 #ifndef SIS900_MII_RESTRICT 3528 /* 3529 * The SiS 900 has only an internal PHY on the MII. Only allow 3530 * MII address 0. 3531 */ 3532 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3533 return; 3534 #endif 3535 3536 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3537 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3538 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3539 do { 3540 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3541 } while (enphy & ENPHY_ACCESS); 3542 } 3543 3544 /* 3545 * sip_sis900_mii_statchg: [mii interface function] 3546 * 3547 * Callback from MII layer when media changes. 3548 */ 3549 static void 3550 sipcom_sis900_mii_statchg(device_t self) 3551 { 3552 struct sip_softc *sc = device_private(self); 3553 struct mii_data *mii = &sc->sc_mii; 3554 u_int32_t flowctl; 3555 3556 /* 3557 * Get flow control negotiation result. 3558 */ 3559 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3560 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3561 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3562 mii->mii_media_active &= ~IFM_ETH_FMASK; 3563 } 3564 3565 /* 3566 * Update TXCFG for full-duplex operation. 3567 */ 3568 if ((mii->mii_media_active & IFM_FDX) != 0) 3569 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3570 else 3571 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3572 3573 /* 3574 * Update RXCFG for full-duplex or loopback. 3575 */ 3576 if ((mii->mii_media_active & IFM_FDX) != 0 || 3577 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3578 sc->sc_rxcfg |= RXCFG_ATX; 3579 else 3580 sc->sc_rxcfg &= ~RXCFG_ATX; 3581 3582 /* 3583 * Update IMR for use of 802.3x flow control. 3584 */ 3585 if (sc->sc_flowflags & IFM_FLOW) { 3586 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3587 flowctl = FLOWCTL_FLOWEN; 3588 } else { 3589 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3590 flowctl = 0; 3591 } 3592 3593 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3594 sc->sc_txcfg); 3595 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3596 sc->sc_rxcfg); 3597 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3598 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3599 } 3600 3601 /* 3602 * sip_dp83815_mii_readreg: [mii interface function] 3603 * 3604 * Read a PHY register on the MII. 3605 */ 3606 static int 3607 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3608 { 3609 struct sip_softc *sc = device_private(self); 3610 u_int32_t val; 3611 3612 /* 3613 * The DP83815 only has an internal PHY. Only allow 3614 * MII address 0. 3615 */ 3616 if (phy != 0) 3617 return (0); 3618 3619 /* 3620 * Apparently, after a reset, the DP83815 can take a while 3621 * to respond. During this recovery period, the BMSR returns 3622 * a value of 0. Catch this -- it's not supposed to happen 3623 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3624 * PHY to come back to life. 3625 * 3626 * This works out because the BMSR is the first register 3627 * read during the PHY probe process. 3628 */ 3629 do { 3630 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3631 } while (reg == MII_BMSR && val == 0); 3632 3633 return (val & 0xffff); 3634 } 3635 3636 /* 3637 * sip_dp83815_mii_writereg: [mii interface function] 3638 * 3639 * Write a PHY register to the MII. 3640 */ 3641 static void 3642 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3643 { 3644 struct sip_softc *sc = device_private(self); 3645 3646 /* 3647 * The DP83815 only has an internal PHY. Only allow 3648 * MII address 0. 3649 */ 3650 if (phy != 0) 3651 return; 3652 3653 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3654 } 3655 3656 /* 3657 * sip_dp83815_mii_statchg: [mii interface function] 3658 * 3659 * Callback from MII layer when media changes. 3660 */ 3661 static void 3662 sipcom_dp83815_mii_statchg(device_t self) 3663 { 3664 struct sip_softc *sc = device_private(self); 3665 3666 /* 3667 * Update TXCFG for full-duplex operation. 3668 */ 3669 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3670 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3671 else 3672 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3673 3674 /* 3675 * Update RXCFG for full-duplex or loopback. 3676 */ 3677 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3678 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3679 sc->sc_rxcfg |= RXCFG_ATX; 3680 else 3681 sc->sc_rxcfg &= ~RXCFG_ATX; 3682 3683 /* 3684 * XXX 802.3x flow control. 3685 */ 3686 3687 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3688 sc->sc_txcfg); 3689 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3690 sc->sc_rxcfg); 3691 3692 /* 3693 * Some DP83815s experience problems when used with short 3694 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3695 * sequence adjusts the DSP's signal attenuation to fix the 3696 * problem. 3697 */ 3698 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3699 uint32_t reg; 3700 3701 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3702 3703 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3704 reg &= 0x0fff; 3705 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3706 delay(100); 3707 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3708 reg &= 0x00ff; 3709 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3710 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3711 0x00e8); 3712 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3713 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3714 reg | 0x20); 3715 } 3716 3717 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3718 } 3719 } 3720 3721 static void 3722 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3723 const struct pci_attach_args *pa, u_int8_t *enaddr) 3724 { 3725 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3726 u_int8_t cksum, *e, match; 3727 int i; 3728 3729 /* 3730 * EEPROM data format for the DP83820 can be found in 3731 * the DP83820 manual, section 4.2.4. 3732 */ 3733 3734 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3735 3736 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3737 match = ~(match - 1); 3738 3739 cksum = 0x55; 3740 e = (u_int8_t *) eeprom_data; 3741 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3742 cksum += *e++; 3743 3744 if (cksum != match) 3745 printf("%s: Checksum (%x) mismatch (%x)", 3746 device_xname(sc->sc_dev), cksum, match); 3747 3748 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3749 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3750 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3751 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3752 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3753 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3754 } 3755 3756 static void 3757 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3758 { 3759 int i; 3760 3761 /* 3762 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3763 * a reason, but I don't know it. 3764 */ 3765 for (i = 0; i < 10; i++) 3766 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3767 } 3768 3769 static void 3770 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3771 const struct pci_attach_args *pa, u_int8_t *enaddr) 3772 { 3773 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3774 3775 switch (sc->sc_rev) { 3776 case SIS_REV_630S: 3777 case SIS_REV_630E: 3778 case SIS_REV_630EA1: 3779 case SIS_REV_630ET: 3780 case SIS_REV_635: 3781 /* 3782 * The MAC address for the on-board Ethernet of 3783 * the SiS 630 chipset is in the NVRAM. Kick 3784 * the chip into re-loading it from NVRAM, and 3785 * read the MAC address out of the filter registers. 3786 */ 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3788 3789 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3790 RFCR_RFADDR_NODE0); 3791 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3792 0xffff; 3793 3794 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3795 RFCR_RFADDR_NODE2); 3796 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3797 0xffff; 3798 3799 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3800 RFCR_RFADDR_NODE4); 3801 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3802 0xffff; 3803 break; 3804 3805 case SIS_REV_960: 3806 { 3807 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3808 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3809 3810 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3811 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3812 3813 int waittime, i; 3814 3815 /* Allow to read EEPROM from LAN. It is shared 3816 * between a 1394 controller and the NIC and each 3817 * time we access it, we need to set SIS_EECMD_REQ. 3818 */ 3819 SIS_SET_EROMAR(sc, EROMAR_REQ); 3820 3821 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3822 /* Force EEPROM to idle state. */ 3823 3824 /* 3825 * XXX-cube This is ugly. I'll look for docs about it. 3826 */ 3827 SIS_SET_EROMAR(sc, EROMAR_EECS); 3828 sipcom_sis900_eeprom_delay(sc); 3829 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3830 SIS_SET_EROMAR(sc, EROMAR_EESK); 3831 sipcom_sis900_eeprom_delay(sc); 3832 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3833 sipcom_sis900_eeprom_delay(sc); 3834 } 3835 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3836 sipcom_sis900_eeprom_delay(sc); 3837 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3838 3839 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3840 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3841 sizeof(myea) / sizeof(myea[0]), myea); 3842 break; 3843 } 3844 DELAY(1); 3845 } 3846 3847 /* 3848 * Set SIS_EECTL_CLK to high, so a other master 3849 * can operate on the i2c bus. 3850 */ 3851 SIS_SET_EROMAR(sc, EROMAR_EESK); 3852 3853 /* Refuse EEPROM access by LAN */ 3854 SIS_SET_EROMAR(sc, EROMAR_DONE); 3855 } break; 3856 3857 default: 3858 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3859 sizeof(myea) / sizeof(myea[0]), myea); 3860 } 3861 3862 enaddr[0] = myea[0] & 0xff; 3863 enaddr[1] = myea[0] >> 8; 3864 enaddr[2] = myea[1] & 0xff; 3865 enaddr[3] = myea[1] >> 8; 3866 enaddr[4] = myea[2] & 0xff; 3867 enaddr[5] = myea[2] >> 8; 3868 } 3869 3870 /* Table and macro to bit-reverse an octet. */ 3871 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3872 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3873 3874 static void 3875 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3876 const struct pci_attach_args *pa, u_int8_t *enaddr) 3877 { 3878 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3879 u_int8_t cksum, *e, match; 3880 int i; 3881 3882 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3883 sizeof(eeprom_data[0]), eeprom_data); 3884 3885 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3886 match = ~(match - 1); 3887 3888 cksum = 0x55; 3889 e = (u_int8_t *) eeprom_data; 3890 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3891 cksum += *e++; 3892 } 3893 if (cksum != match) { 3894 printf("%s: Checksum (%x) mismatch (%x)", 3895 device_xname(sc->sc_dev), cksum, match); 3896 } 3897 3898 /* 3899 * Unrolled because it makes slightly more sense this way. 3900 * The DP83815 stores the MAC address in bit 0 of word 6 3901 * through bit 15 of word 8. 3902 */ 3903 ea = &eeprom_data[6]; 3904 enaddr[0] = ((*ea & 0x1) << 7); 3905 ea++; 3906 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3907 enaddr[1] = ((*ea & 0x1FE) >> 1); 3908 enaddr[2] = ((*ea & 0x1) << 7); 3909 ea++; 3910 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3911 enaddr[3] = ((*ea & 0x1FE) >> 1); 3912 enaddr[4] = ((*ea & 0x1) << 7); 3913 ea++; 3914 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3915 enaddr[5] = ((*ea & 0x1FE) >> 1); 3916 3917 /* 3918 * In case that's not weird enough, we also need to reverse 3919 * the bits in each byte. This all actually makes more sense 3920 * if you think about the EEPROM storage as an array of bits 3921 * being shifted into bytes, but that's not how we're looking 3922 * at it here... 3923 */ 3924 for (i = 0; i < 6 ;i++) 3925 enaddr[i] = bbr(enaddr[i]); 3926 } 3927 3928 /* 3929 * sip_mediastatus: [ifmedia interface function] 3930 * 3931 * Get the current interface media status. 3932 */ 3933 static void 3934 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3935 { 3936 struct sip_softc *sc = ifp->if_softc; 3937 3938 if (!device_is_active(sc->sc_dev)) { 3939 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3940 ifmr->ifm_status = 0; 3941 return; 3942 } 3943 ether_mediastatus(ifp, ifmr); 3944 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3945 sc->sc_flowflags; 3946 } 3947
Indexes created Tue Sep 30 11:09:46 GMT 2025