if_sip.c revision 1.154
1 /* $NetBSD: if_sip.c,v 1.154 2012/07/22 14:33:03 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.154 2012/07/22 14:33:03 matt Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rnd.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int); 587 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int); 591 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int); 595 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int); 622 void (*sipv_mii_writereg)(device_t, int, int, int); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA-621 */ 741 { 0x1385, 0x621a }, 742 743 /* SMC EZ Card */ 744 { 0x10b8, 0x9462 }, 745 746 { 0, 0} 747 }; 748 pcireg_t subsys; 749 int i; 750 751 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 752 753 for (i = 0; card64[i].c64_vendor != 0; i++) { 754 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 755 PCI_PRODUCT(subsys) == card64[i].c64_product) 756 return (1); 757 } 758 759 return (0); 760 } 761 762 static int 763 sipcom_match(device_t parent, cfdata_t cf, void *aux) 764 { 765 struct pci_attach_args *pa = aux; 766 767 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 768 return 1; 769 770 return 0; 771 } 772 773 static void 774 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 775 { 776 u_int32_t reg; 777 int i; 778 779 /* 780 * Cause the chip to load configuration data from the EEPROM. 781 */ 782 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 783 for (i = 0; i < 10000; i++) { 784 delay(10); 785 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 786 PTSCR_EELOAD_EN) == 0) 787 break; 788 } 789 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 790 PTSCR_EELOAD_EN) { 791 printf("%s: timeout loading configuration from EEPROM\n", 792 device_xname(sc->sc_dev)); 793 return; 794 } 795 796 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 797 798 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 799 if (reg & CFG_PCI64_DET) { 800 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 801 /* 802 * Check to see if this card is 64-bit. If so, enable 64-bit 803 * data transfers. 804 * 805 * We can't use the DATA64_EN bit in the EEPROM, because 806 * vendors of 32-bit cards fail to clear that bit in many 807 * cases (yet the card still detects that it's in a 64-bit 808 * slot; go figure). 809 */ 810 if (sipcom_check_64bit(pa)) { 811 sc->sc_cfg |= CFG_DATA64_EN; 812 printf(", using 64-bit data transfers"); 813 } 814 printf("\n"); 815 } 816 817 /* 818 * XXX Need some PCI flags indicating support for 819 * XXX 64-bit addressing. 820 */ 821 #if 0 822 if (reg & CFG_M64ADDR) 823 sc->sc_cfg |= CFG_M64ADDR; 824 if (reg & CFG_T64ADDR) 825 sc->sc_cfg |= CFG_T64ADDR; 826 #endif 827 828 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 829 const char *sep = ""; 830 printf("%s: using ", device_xname(sc->sc_dev)); 831 if (reg & CFG_EXT_125) { 832 sc->sc_cfg |= CFG_EXT_125; 833 printf("%s125MHz clock", sep); 834 sep = ", "; 835 } 836 if (reg & CFG_TBI_EN) { 837 sc->sc_cfg |= CFG_TBI_EN; 838 printf("%sten-bit interface", sep); 839 sep = ", "; 840 } 841 printf("\n"); 842 } 843 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 844 (reg & CFG_MRM_DIS) != 0) 845 sc->sc_cfg |= CFG_MRM_DIS; 846 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 847 (reg & CFG_MWI_DIS) != 0) 848 sc->sc_cfg |= CFG_MWI_DIS; 849 850 /* 851 * Use the extended descriptor format on the DP83820. This 852 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 853 * checksumming. 854 */ 855 sc->sc_cfg |= CFG_EXTSTS_EN; 856 } 857 858 static int 859 sipcom_detach(device_t self, int flags) 860 { 861 int s; 862 863 s = splnet(); 864 sipcom_do_detach(self, SIP_ATTACH_FIN); 865 splx(s); 866 867 return 0; 868 } 869 870 static void 871 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 872 { 873 int i; 874 struct sip_softc *sc = device_private(self); 875 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 876 877 /* 878 * Free any resources we've allocated during attach. 879 * Do this in reverse order and fall through. 880 */ 881 switch (stage) { 882 case SIP_ATTACH_FIN: 883 sipcom_stop(ifp, 1); 884 pmf_device_deregister(self); 885 #ifdef SIP_EVENT_COUNTERS 886 /* 887 * Attach event counters. 888 */ 889 evcnt_detach(&sc->sc_ev_txforceintr); 890 evcnt_detach(&sc->sc_ev_txdstall); 891 evcnt_detach(&sc->sc_ev_txsstall); 892 evcnt_detach(&sc->sc_ev_hiberr); 893 evcnt_detach(&sc->sc_ev_rxintr); 894 evcnt_detach(&sc->sc_ev_txiintr); 895 evcnt_detach(&sc->sc_ev_txdintr); 896 if (!sc->sc_gigabit) { 897 evcnt_detach(&sc->sc_ev_rxpause); 898 } else { 899 evcnt_detach(&sc->sc_ev_txudpsum); 900 evcnt_detach(&sc->sc_ev_txtcpsum); 901 evcnt_detach(&sc->sc_ev_txipsum); 902 evcnt_detach(&sc->sc_ev_rxudpsum); 903 evcnt_detach(&sc->sc_ev_rxtcpsum); 904 evcnt_detach(&sc->sc_ev_rxipsum); 905 evcnt_detach(&sc->sc_ev_txpause); 906 evcnt_detach(&sc->sc_ev_rxpause); 907 } 908 #endif /* SIP_EVENT_COUNTERS */ 909 910 rnd_detach_source(&sc->rnd_source); 911 912 ether_ifdetach(ifp); 913 if_detach(ifp); 914 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 915 916 /*FALLTHROUGH*/ 917 case SIP_ATTACH_CREATE_RXMAP: 918 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 919 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 920 bus_dmamap_destroy(sc->sc_dmat, 921 sc->sc_rxsoft[i].rxs_dmamap); 922 } 923 /*FALLTHROUGH*/ 924 case SIP_ATTACH_CREATE_TXMAP: 925 for (i = 0; i < SIP_TXQUEUELEN; i++) { 926 if (sc->sc_txsoft[i].txs_dmamap != NULL) 927 bus_dmamap_destroy(sc->sc_dmat, 928 sc->sc_txsoft[i].txs_dmamap); 929 } 930 /*FALLTHROUGH*/ 931 case SIP_ATTACH_LOAD_MAP: 932 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_CREATE_MAP: 935 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_MAP_MEM: 938 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 939 sizeof(struct sip_control_data)); 940 /*FALLTHROUGH*/ 941 case SIP_ATTACH_ALLOC_MEM: 942 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 943 /* FALLTHROUGH*/ 944 case SIP_ATTACH_INTR: 945 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_MAP: 948 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 949 break; 950 default: 951 break; 952 } 953 return; 954 } 955 956 static bool 957 sipcom_resume(device_t self, const pmf_qual_t *qual) 958 { 959 struct sip_softc *sc = device_private(self); 960 961 return sipcom_reset(sc); 962 } 963 964 static bool 965 sipcom_suspend(device_t self, const pmf_qual_t *qual) 966 { 967 struct sip_softc *sc = device_private(self); 968 969 sipcom_rxdrain(sc); 970 return true; 971 } 972 973 static void 974 sipcom_attach(device_t parent, device_t self, void *aux) 975 { 976 struct sip_softc *sc = device_private(self); 977 struct pci_attach_args *pa = aux; 978 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 979 pci_chipset_tag_t pc = pa->pa_pc; 980 pci_intr_handle_t ih; 981 const char *intrstr = NULL; 982 bus_space_tag_t iot, memt; 983 bus_space_handle_t ioh, memh; 984 bus_size_t iosz, memsz; 985 int ioh_valid, memh_valid; 986 int i, rseg, error; 987 const struct sip_product *sip; 988 u_int8_t enaddr[ETHER_ADDR_LEN]; 989 pcireg_t csr; 990 pcireg_t memtype; 991 bus_size_t tx_dmamap_size; 992 int ntxsegs_alloc; 993 cfdata_t cf = device_cfdata(self); 994 995 callout_init(&sc->sc_tick_ch, 0); 996 997 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 998 if (sip == NULL) { 999 printf("\n"); 1000 panic("%s: impossible", __func__); 1001 } 1002 sc->sc_dev = self; 1003 sc->sc_gigabit = sip->sip_gigabit; 1004 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1005 sc->sc_pc = pc; 1006 1007 if (sc->sc_gigabit) { 1008 sc->sc_rxintr = gsip_rxintr; 1009 sc->sc_parm = &gsip_parm; 1010 } else { 1011 sc->sc_rxintr = sip_rxintr; 1012 sc->sc_parm = &sip_parm; 1013 } 1014 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1015 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1016 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1017 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1018 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1019 1020 sc->sc_rev = PCI_REVISION(pa->pa_class); 1021 1022 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1023 1024 sc->sc_model = sip; 1025 1026 /* 1027 * XXX Work-around broken PXE firmware on some boards. 1028 * 1029 * The DP83815 shares an address decoder with the MEM BAR 1030 * and the ROM BAR. Make sure the ROM BAR is disabled, 1031 * so that memory mapped access works. 1032 */ 1033 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1034 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1035 ~PCI_MAPREG_ROM_ENABLE); 1036 1037 /* 1038 * Map the device. 1039 */ 1040 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1041 PCI_MAPREG_TYPE_IO, 0, 1042 &iot, &ioh, NULL, &iosz) == 0); 1043 if (sc->sc_gigabit) { 1044 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1045 switch (memtype) { 1046 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1047 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1048 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1049 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1050 break; 1051 default: 1052 memh_valid = 0; 1053 } 1054 } else { 1055 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1056 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1057 &memt, &memh, NULL, &memsz) == 0); 1058 } 1059 1060 if (memh_valid) { 1061 sc->sc_st = memt; 1062 sc->sc_sh = memh; 1063 sc->sc_sz = memsz; 1064 } else if (ioh_valid) { 1065 sc->sc_st = iot; 1066 sc->sc_sh = ioh; 1067 sc->sc_sz = iosz; 1068 } else { 1069 printf("%s: unable to map device registers\n", 1070 device_xname(sc->sc_dev)); 1071 return; 1072 } 1073 1074 sc->sc_dmat = pa->pa_dmat; 1075 1076 /* 1077 * Make sure bus mastering is enabled. Also make sure 1078 * Write/Invalidate is enabled if we're allowed to use it. 1079 */ 1080 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1081 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1082 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1083 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1084 csr | PCI_COMMAND_MASTER_ENABLE); 1085 1086 /* power up chip */ 1087 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1088 if (error != 0 && error != EOPNOTSUPP) { 1089 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1090 return; 1091 } 1092 1093 /* 1094 * Map and establish our interrupt. 1095 */ 1096 if (pci_intr_map(pa, &ih)) { 1097 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1098 return; 1099 } 1100 intrstr = pci_intr_string(pc, ih); 1101 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1102 if (sc->sc_ih == NULL) { 1103 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1104 if (intrstr != NULL) 1105 aprint_error(" at %s", intrstr); 1106 aprint_error("\n"); 1107 sipcom_do_detach(self, SIP_ATTACH_MAP); 1108 return; 1109 } 1110 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1111 1112 SIMPLEQ_INIT(&sc->sc_txfreeq); 1113 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1114 1115 /* 1116 * Allocate the control data structures, and create and load the 1117 * DMA map for it. 1118 */ 1119 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1120 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1121 &rseg, 0)) != 0) { 1122 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1123 error); 1124 sipcom_do_detach(self, SIP_ATTACH_INTR); 1125 return; 1126 } 1127 1128 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1129 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1130 BUS_DMA_COHERENT)) != 0) { 1131 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1132 error); 1133 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1134 } 1135 1136 if ((error = bus_dmamap_create(sc->sc_dmat, 1137 sizeof(struct sip_control_data), 1, 1138 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1139 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1140 "error = %d\n", error); 1141 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1142 } 1143 1144 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1145 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1146 0)) != 0) { 1147 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1148 error); 1149 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1150 } 1151 1152 /* 1153 * Create the transmit buffer DMA maps. 1154 */ 1155 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1156 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1157 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1158 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1159 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1160 "error = %d\n", i, error); 1161 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1162 } 1163 } 1164 1165 /* 1166 * Create the receive buffer DMA maps. 1167 */ 1168 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1169 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1170 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1171 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1172 "error = %d\n", i, error); 1173 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1174 } 1175 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1176 } 1177 1178 /* 1179 * Reset the chip to a known state. 1180 */ 1181 sipcom_reset(sc); 1182 1183 /* 1184 * Read the Ethernet address from the EEPROM. This might 1185 * also fetch other stuff from the EEPROM and stash it 1186 * in the softc. 1187 */ 1188 sc->sc_cfg = 0; 1189 if (!sc->sc_gigabit) { 1190 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1191 SIP_SIS900_REV(sc,SIS_REV_900B)) 1192 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1193 1194 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1195 SIP_SIS900_REV(sc,SIS_REV_960) || 1196 SIP_SIS900_REV(sc,SIS_REV_900B)) 1197 sc->sc_cfg |= 1198 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1199 CFG_EDBMASTEN); 1200 } 1201 1202 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1203 1204 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1205 ether_sprintf(enaddr)); 1206 1207 /* 1208 * Initialize the configuration register: aggressive PCI 1209 * bus request algorithm, default backoff, default OW timer, 1210 * default parity error detection. 1211 * 1212 * NOTE: "Big endian mode" is useless on the SiS900 and 1213 * friends -- it affects packet data, not descriptors. 1214 */ 1215 if (sc->sc_gigabit) 1216 sipcom_dp83820_attach(sc, pa); 1217 1218 /* 1219 * Initialize our media structures and probe the MII. 1220 */ 1221 sc->sc_mii.mii_ifp = ifp; 1222 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1223 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1224 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1225 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1226 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1227 sipcom_mediastatus); 1228 1229 /* 1230 * XXX We cannot handle flow control on the DP83815. 1231 */ 1232 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1233 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1234 MII_OFFSET_ANY, 0); 1235 else 1236 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, MIIF_DOPAUSE); 1238 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1239 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1240 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1241 } else 1242 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1243 1244 ifp = &sc->sc_ethercom.ec_if; 1245 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1246 ifp->if_softc = sc; 1247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1248 sc->sc_if_flags = ifp->if_flags; 1249 ifp->if_ioctl = sipcom_ioctl; 1250 ifp->if_start = sipcom_start; 1251 ifp->if_watchdog = sipcom_watchdog; 1252 ifp->if_init = sipcom_init; 1253 ifp->if_stop = sipcom_stop; 1254 IFQ_SET_READY(&ifp->if_snd); 1255 1256 /* 1257 * We can support 802.1Q VLAN-sized frames. 1258 */ 1259 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1260 1261 if (sc->sc_gigabit) { 1262 /* 1263 * And the DP83820 can do VLAN tagging in hardware, and 1264 * support the jumbo Ethernet MTU. 1265 */ 1266 sc->sc_ethercom.ec_capabilities |= 1267 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1268 1269 /* 1270 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1271 * in hardware. 1272 */ 1273 ifp->if_capabilities |= 1274 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1275 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1276 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1277 } 1278 1279 /* 1280 * Attach the interface. 1281 */ 1282 if_attach(ifp); 1283 ether_ifattach(ifp, enaddr); 1284 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1285 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1286 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1287 sc->sc_prev.if_capenable = ifp->if_capenable; 1288 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1289 RND_TYPE_NET, 0); 1290 1291 /* 1292 * The number of bytes that must be available in 1293 * the Tx FIFO before the bus master can DMA more 1294 * data into the FIFO. 1295 */ 1296 sc->sc_tx_fill_thresh = 64 / 32; 1297 1298 /* 1299 * Start at a drain threshold of 512 bytes. We will 1300 * increase it if a DMA underrun occurs. 1301 * 1302 * XXX The minimum value of this variable should be 1303 * tuned. We may be able to improve performance 1304 * by starting with a lower value. That, however, 1305 * may trash the first few outgoing packets if the 1306 * PCI bus is saturated. 1307 */ 1308 if (sc->sc_gigabit) 1309 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1310 else 1311 sc->sc_tx_drain_thresh = 1504 / 32; 1312 1313 /* 1314 * Initialize the Rx FIFO drain threshold. 1315 * 1316 * This is in units of 8 bytes. 1317 * 1318 * We should never set this value lower than 2; 14 bytes are 1319 * required to filter the packet. 1320 */ 1321 sc->sc_rx_drain_thresh = 128 / 8; 1322 1323 #ifdef SIP_EVENT_COUNTERS 1324 /* 1325 * Attach event counters. 1326 */ 1327 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1328 NULL, device_xname(sc->sc_dev), "txsstall"); 1329 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1330 NULL, device_xname(sc->sc_dev), "txdstall"); 1331 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1332 NULL, device_xname(sc->sc_dev), "txforceintr"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1334 NULL, device_xname(sc->sc_dev), "txdintr"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(sc->sc_dev), "txiintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "rxintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "hiberr"); 1341 if (!sc->sc_gigabit) { 1342 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "rxpause"); 1344 } else { 1345 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1346 NULL, device_xname(sc->sc_dev), "rxpause"); 1347 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1348 NULL, device_xname(sc->sc_dev), "txpause"); 1349 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1350 NULL, device_xname(sc->sc_dev), "rxipsum"); 1351 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "txipsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "txudpsum"); 1361 } 1362 #endif /* SIP_EVENT_COUNTERS */ 1363 1364 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1365 pmf_class_network_register(self, ifp); 1366 else 1367 aprint_error_dev(self, "couldn't establish power handler\n"); 1368 } 1369 1370 static inline void 1371 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1372 uint64_t capenable) 1373 { 1374 struct m_tag *mtag; 1375 u_int32_t extsts; 1376 #ifdef DEBUG 1377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1378 #endif 1379 /* 1380 * If VLANs are enabled and the packet has a VLAN tag, set 1381 * up the descriptor to encapsulate the packet for us. 1382 * 1383 * This apparently has to be on the last descriptor of 1384 * the packet. 1385 */ 1386 1387 /* 1388 * Byte swapping is tricky. We need to provide the tag 1389 * in a network byte order. On a big-endian machine, 1390 * the byteorder is correct, but we need to swap it 1391 * anyway, because this will be undone by the outside 1392 * htole32(). That's why there must be an 1393 * unconditional swap instead of htons() inside. 1394 */ 1395 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1396 sc->sc_txdescs[lasttx].sipd_extsts |= 1397 htole32(EXTSTS_VPKT | 1398 (bswap16(VLAN_TAG_VALUE(mtag)) & 1399 EXTSTS_VTCI)); 1400 } 1401 1402 /* 1403 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1404 * checksumming, set up the descriptor to do this work 1405 * for us. 1406 * 1407 * This apparently has to be on the first descriptor of 1408 * the packet. 1409 * 1410 * Byte-swap constants so the compiler can optimize. 1411 */ 1412 extsts = 0; 1413 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1414 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1415 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1416 extsts |= htole32(EXTSTS_IPPKT); 1417 } 1418 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1419 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1420 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1421 extsts |= htole32(EXTSTS_TCPPKT); 1422 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1425 extsts |= htole32(EXTSTS_UDPPKT); 1426 } 1427 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1428 } 1429 1430 /* 1431 * sip_start: [ifnet interface function] 1432 * 1433 * Start packet transmission on the interface. 1434 */ 1435 static void 1436 sipcom_start(struct ifnet *ifp) 1437 { 1438 struct sip_softc *sc = ifp->if_softc; 1439 struct mbuf *m0; 1440 struct mbuf *m; 1441 struct sip_txsoft *txs; 1442 bus_dmamap_t dmamap; 1443 int error, nexttx, lasttx, seg; 1444 int ofree = sc->sc_txfree; 1445 #if 0 1446 int firsttx = sc->sc_txnext; 1447 #endif 1448 1449 /* 1450 * If we've been told to pause, don't transmit any more packets. 1451 */ 1452 if (!sc->sc_gigabit && sc->sc_paused) 1453 ifp->if_flags |= IFF_OACTIVE; 1454 1455 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1456 return; 1457 1458 /* 1459 * Loop through the send queue, setting up transmit descriptors 1460 * until we drain the queue, or use up all available transmit 1461 * descriptors. 1462 */ 1463 for (;;) { 1464 /* Get a work queue entry. */ 1465 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1466 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1467 break; 1468 } 1469 1470 /* 1471 * Grab a packet off the queue. 1472 */ 1473 IFQ_POLL(&ifp->if_snd, m0); 1474 if (m0 == NULL) 1475 break; 1476 m = NULL; 1477 1478 dmamap = txs->txs_dmamap; 1479 1480 /* 1481 * Load the DMA map. If this fails, the packet either 1482 * didn't fit in the alloted number of segments, or we 1483 * were short on resources. 1484 */ 1485 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1486 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1487 /* In the non-gigabit case, we'll copy and try again. */ 1488 if (error != 0 && !sc->sc_gigabit) { 1489 MGETHDR(m, M_DONTWAIT, MT_DATA); 1490 if (m == NULL) { 1491 printf("%s: unable to allocate Tx mbuf\n", 1492 device_xname(sc->sc_dev)); 1493 break; 1494 } 1495 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1496 if (m0->m_pkthdr.len > MHLEN) { 1497 MCLGET(m, M_DONTWAIT); 1498 if ((m->m_flags & M_EXT) == 0) { 1499 printf("%s: unable to allocate Tx " 1500 "cluster\n", device_xname(sc->sc_dev)); 1501 m_freem(m); 1502 break; 1503 } 1504 } 1505 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1506 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1507 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1508 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1509 if (error) { 1510 printf("%s: unable to load Tx buffer, " 1511 "error = %d\n", device_xname(sc->sc_dev), error); 1512 break; 1513 } 1514 } else if (error == EFBIG) { 1515 /* 1516 * For the too-many-segments case, we simply 1517 * report an error and drop the packet, 1518 * since we can't sanely copy a jumbo packet 1519 * to a single buffer. 1520 */ 1521 printf("%s: Tx packet consumes too many " 1522 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1523 IFQ_DEQUEUE(&ifp->if_snd, m0); 1524 m_freem(m0); 1525 continue; 1526 } else if (error != 0) { 1527 /* 1528 * Short on resources, just stop for now. 1529 */ 1530 break; 1531 } 1532 1533 /* 1534 * Ensure we have enough descriptors free to describe 1535 * the packet. Note, we always reserve one descriptor 1536 * at the end of the ring as a termination point, to 1537 * prevent wrap-around. 1538 */ 1539 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1540 /* 1541 * Not enough free descriptors to transmit this 1542 * packet. We haven't committed anything yet, 1543 * so just unload the DMA map, put the packet 1544 * back on the queue, and punt. Notify the upper 1545 * layer that there are not more slots left. 1546 * 1547 * XXX We could allocate an mbuf and copy, but 1548 * XXX is it worth it? 1549 */ 1550 ifp->if_flags |= IFF_OACTIVE; 1551 bus_dmamap_unload(sc->sc_dmat, dmamap); 1552 if (m != NULL) 1553 m_freem(m); 1554 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1555 break; 1556 } 1557 1558 IFQ_DEQUEUE(&ifp->if_snd, m0); 1559 if (m != NULL) { 1560 m_freem(m0); 1561 m0 = m; 1562 } 1563 1564 /* 1565 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1566 */ 1567 1568 /* Sync the DMA map. */ 1569 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1570 BUS_DMASYNC_PREWRITE); 1571 1572 /* 1573 * Initialize the transmit descriptors. 1574 */ 1575 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1576 seg < dmamap->dm_nsegs; 1577 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1578 /* 1579 * If this is the first descriptor we're 1580 * enqueueing, don't set the OWN bit just 1581 * yet. That could cause a race condition. 1582 * We'll do it below. 1583 */ 1584 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1585 htole32(dmamap->dm_segs[seg].ds_addr); 1586 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1587 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1588 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1589 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1590 lasttx = nexttx; 1591 } 1592 1593 /* Clear the MORE bit on the last segment. */ 1594 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1595 htole32(~CMDSTS_MORE); 1596 1597 /* 1598 * If we're in the interrupt delay window, delay the 1599 * interrupt. 1600 */ 1601 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1602 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1603 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1604 htole32(CMDSTS_INTR); 1605 sc->sc_txwin = 0; 1606 } 1607 1608 if (sc->sc_gigabit) 1609 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1610 1611 /* Sync the descriptors we're using. */ 1612 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1613 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1614 1615 /* 1616 * The entire packet is set up. Give the first descrptor 1617 * to the chip now. 1618 */ 1619 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1620 htole32(CMDSTS_OWN); 1621 sip_cdtxsync(sc, sc->sc_txnext, 1, 1622 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1623 1624 /* 1625 * Store a pointer to the packet so we can free it later, 1626 * and remember what txdirty will be once the packet is 1627 * done. 1628 */ 1629 txs->txs_mbuf = m0; 1630 txs->txs_firstdesc = sc->sc_txnext; 1631 txs->txs_lastdesc = lasttx; 1632 1633 /* Advance the tx pointer. */ 1634 sc->sc_txfree -= dmamap->dm_nsegs; 1635 sc->sc_txnext = nexttx; 1636 1637 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1638 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1639 1640 /* 1641 * Pass the packet to any BPF listeners. 1642 */ 1643 bpf_mtap(ifp, m0); 1644 } 1645 1646 if (txs == NULL || sc->sc_txfree == 0) { 1647 /* No more slots left; notify upper layer. */ 1648 ifp->if_flags |= IFF_OACTIVE; 1649 } 1650 1651 if (sc->sc_txfree != ofree) { 1652 /* 1653 * Start the transmit process. Note, the manual says 1654 * that if there are no pending transmissions in the 1655 * chip's internal queue (indicated by TXE being clear), 1656 * then the driver software must set the TXDP to the 1657 * first descriptor to be transmitted. However, if we 1658 * do this, it causes serious performance degredation on 1659 * the DP83820 under load, not setting TXDP doesn't seem 1660 * to adversely affect the SiS 900 or DP83815. 1661 * 1662 * Well, I guess it wouldn't be the first time a manual 1663 * has lied -- and they could be speaking of the NULL- 1664 * terminated descriptor list case, rather than OWN- 1665 * terminated rings. 1666 */ 1667 #if 0 1668 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1669 CR_TXE) == 0) { 1670 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1671 SIP_CDTXADDR(sc, firsttx)); 1672 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1673 } 1674 #else 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1676 #endif 1677 1678 /* Set a watchdog timer in case the chip flakes out. */ 1679 /* Gigabit autonegotiation takes 5 seconds. */ 1680 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1681 } 1682 } 1683 1684 /* 1685 * sip_watchdog: [ifnet interface function] 1686 * 1687 * Watchdog timer handler. 1688 */ 1689 static void 1690 sipcom_watchdog(struct ifnet *ifp) 1691 { 1692 struct sip_softc *sc = ifp->if_softc; 1693 1694 /* 1695 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1696 * If we get a timeout, try and sweep up transmit descriptors. 1697 * If we manage to sweep them all up, ignore the lack of 1698 * interrupt. 1699 */ 1700 sipcom_txintr(sc); 1701 1702 if (sc->sc_txfree != sc->sc_ntxdesc) { 1703 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1704 ifp->if_oerrors++; 1705 1706 /* Reset the interface. */ 1707 (void) sipcom_init(ifp); 1708 } else if (ifp->if_flags & IFF_DEBUG) 1709 printf("%s: recovered from device timeout\n", 1710 device_xname(sc->sc_dev)); 1711 1712 /* Try to get more packets going. */ 1713 sipcom_start(ifp); 1714 } 1715 1716 /* If the interface is up and running, only modify the receive 1717 * filter when setting promiscuous or debug mode. Otherwise fall 1718 * through to ether_ioctl, which will reset the chip. 1719 */ 1720 static int 1721 sip_ifflags_cb(struct ethercom *ec) 1722 { 1723 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1724 == (sc)->sc_ethercom.ec_capenable) \ 1725 && ((sc)->sc_prev.is_vlan == \ 1726 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1727 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1728 struct ifnet *ifp = &ec->ec_if; 1729 struct sip_softc *sc = ifp->if_softc; 1730 int change = ifp->if_flags ^ sc->sc_if_flags; 1731 1732 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1733 !COMPARE_IC(sc, ifp)) 1734 return ENETRESET; 1735 /* Set up the receive filter. */ 1736 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1737 return 0; 1738 } 1739 1740 /* 1741 * sip_ioctl: [ifnet interface function] 1742 * 1743 * Handle control requests from the operator. 1744 */ 1745 static int 1746 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1747 { 1748 struct sip_softc *sc = ifp->if_softc; 1749 struct ifreq *ifr = (struct ifreq *)data; 1750 int s, error; 1751 1752 s = splnet(); 1753 1754 switch (cmd) { 1755 case SIOCSIFMEDIA: 1756 /* Flow control requires full-duplex mode. */ 1757 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1758 (ifr->ifr_media & IFM_FDX) == 0) 1759 ifr->ifr_media &= ~IFM_ETH_FMASK; 1760 1761 /* XXX */ 1762 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1763 ifr->ifr_media &= ~IFM_ETH_FMASK; 1764 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1765 if (sc->sc_gigabit && 1766 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1767 /* We can do both TXPAUSE and RXPAUSE. */ 1768 ifr->ifr_media |= 1769 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1770 } else if (ifr->ifr_media & IFM_FLOW) { 1771 /* 1772 * Both TXPAUSE and RXPAUSE must be set. 1773 * (SiS900 and DP83815 don't have PAUSE_ASYM 1774 * feature.) 1775 * 1776 * XXX Can SiS900 and DP83815 send PAUSE? 1777 */ 1778 ifr->ifr_media |= 1779 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1780 } 1781 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1782 } 1783 /*FALLTHROUGH*/ 1784 default: 1785 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1786 break; 1787 1788 error = 0; 1789 1790 if (cmd == SIOCSIFCAP) 1791 error = (*ifp->if_init)(ifp); 1792 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1793 ; 1794 else if (ifp->if_flags & IFF_RUNNING) { 1795 /* 1796 * Multicast list has changed; set the hardware filter 1797 * accordingly. 1798 */ 1799 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1800 } 1801 break; 1802 } 1803 1804 /* Try to get more packets going. */ 1805 sipcom_start(ifp); 1806 1807 sc->sc_if_flags = ifp->if_flags; 1808 splx(s); 1809 return (error); 1810 } 1811 1812 /* 1813 * sip_intr: 1814 * 1815 * Interrupt service routine. 1816 */ 1817 static int 1818 sipcom_intr(void *arg) 1819 { 1820 struct sip_softc *sc = arg; 1821 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1822 u_int32_t isr; 1823 int handled = 0; 1824 1825 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1826 return 0; 1827 1828 /* Disable interrupts. */ 1829 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1830 1831 for (;;) { 1832 /* Reading clears interrupt. */ 1833 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1834 if ((isr & sc->sc_imr) == 0) 1835 break; 1836 1837 rnd_add_uint32(&sc->rnd_source, isr); 1838 1839 handled = 1; 1840 1841 if ((ifp->if_flags & IFF_RUNNING) == 0) 1842 break; 1843 1844 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1845 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1846 1847 /* Grab any new packets. */ 1848 (*sc->sc_rxintr)(sc); 1849 1850 if (isr & ISR_RXORN) { 1851 printf("%s: receive FIFO overrun\n", 1852 device_xname(sc->sc_dev)); 1853 1854 /* XXX adjust rx_drain_thresh? */ 1855 } 1856 1857 if (isr & ISR_RXIDLE) { 1858 printf("%s: receive ring overrun\n", 1859 device_xname(sc->sc_dev)); 1860 1861 /* Get the receive process going again. */ 1862 bus_space_write_4(sc->sc_st, sc->sc_sh, 1863 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1864 bus_space_write_4(sc->sc_st, sc->sc_sh, 1865 SIP_CR, CR_RXE); 1866 } 1867 } 1868 1869 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1870 #ifdef SIP_EVENT_COUNTERS 1871 if (isr & ISR_TXDESC) 1872 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1873 else if (isr & ISR_TXIDLE) 1874 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1875 #endif 1876 1877 /* Sweep up transmit descriptors. */ 1878 sipcom_txintr(sc); 1879 1880 if (isr & ISR_TXURN) { 1881 u_int32_t thresh; 1882 int txfifo_size = (sc->sc_gigabit) 1883 ? DP83820_SIP_TXFIFO_SIZE 1884 : OTHER_SIP_TXFIFO_SIZE; 1885 1886 printf("%s: transmit FIFO underrun", 1887 device_xname(sc->sc_dev)); 1888 thresh = sc->sc_tx_drain_thresh + 1; 1889 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1890 && (thresh * 32) <= (txfifo_size - 1891 (sc->sc_tx_fill_thresh * 32))) { 1892 printf("; increasing Tx drain " 1893 "threshold to %u bytes\n", 1894 thresh * 32); 1895 sc->sc_tx_drain_thresh = thresh; 1896 (void) sipcom_init(ifp); 1897 } else { 1898 (void) sipcom_init(ifp); 1899 printf("\n"); 1900 } 1901 } 1902 } 1903 1904 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1905 if (isr & ISR_PAUSE_ST) { 1906 sc->sc_paused = 1; 1907 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1908 ifp->if_flags |= IFF_OACTIVE; 1909 } 1910 if (isr & ISR_PAUSE_END) { 1911 sc->sc_paused = 0; 1912 ifp->if_flags &= ~IFF_OACTIVE; 1913 } 1914 } 1915 1916 if (isr & ISR_HIBERR) { 1917 int want_init = 0; 1918 1919 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1920 1921 #define PRINTERR(bit, str) \ 1922 do { \ 1923 if ((isr & (bit)) != 0) { \ 1924 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1925 printf("%s: %s\n", \ 1926 device_xname(sc->sc_dev), str); \ 1927 want_init = 1; \ 1928 } \ 1929 } while (/*CONSTCOND*/0) 1930 1931 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1932 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1933 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1934 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1935 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1936 /* 1937 * Ignore: 1938 * Tx reset complete 1939 * Rx reset complete 1940 */ 1941 if (want_init) 1942 (void) sipcom_init(ifp); 1943 #undef PRINTERR 1944 } 1945 } 1946 1947 /* Re-enable interrupts. */ 1948 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1949 1950 /* Try to get more packets going. */ 1951 sipcom_start(ifp); 1952 1953 return (handled); 1954 } 1955 1956 /* 1957 * sip_txintr: 1958 * 1959 * Helper; handle transmit interrupts. 1960 */ 1961 static void 1962 sipcom_txintr(struct sip_softc *sc) 1963 { 1964 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1965 struct sip_txsoft *txs; 1966 u_int32_t cmdsts; 1967 1968 if (sc->sc_paused == 0) 1969 ifp->if_flags &= ~IFF_OACTIVE; 1970 1971 /* 1972 * Go through our Tx list and free mbufs for those 1973 * frames which have been transmitted. 1974 */ 1975 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1976 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1977 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1978 1979 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1980 if (cmdsts & CMDSTS_OWN) 1981 break; 1982 1983 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1984 1985 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1986 1987 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1988 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1989 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1990 m_freem(txs->txs_mbuf); 1991 txs->txs_mbuf = NULL; 1992 1993 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1994 1995 /* 1996 * Check for errors and collisions. 1997 */ 1998 if (cmdsts & 1999 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2000 ifp->if_oerrors++; 2001 if (cmdsts & CMDSTS_Tx_EC) 2002 ifp->if_collisions += 16; 2003 if (ifp->if_flags & IFF_DEBUG) { 2004 if (cmdsts & CMDSTS_Tx_ED) 2005 printf("%s: excessive deferral\n", 2006 device_xname(sc->sc_dev)); 2007 if (cmdsts & CMDSTS_Tx_EC) 2008 printf("%s: excessive collisions\n", 2009 device_xname(sc->sc_dev)); 2010 } 2011 } else { 2012 /* Packet was transmitted successfully. */ 2013 ifp->if_opackets++; 2014 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2015 } 2016 } 2017 2018 /* 2019 * If there are no more pending transmissions, cancel the watchdog 2020 * timer. 2021 */ 2022 if (txs == NULL) { 2023 ifp->if_timer = 0; 2024 sc->sc_txwin = 0; 2025 } 2026 } 2027 2028 /* 2029 * gsip_rxintr: 2030 * 2031 * Helper; handle receive interrupts on gigabit parts. 2032 */ 2033 static void 2034 gsip_rxintr(struct sip_softc *sc) 2035 { 2036 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2037 struct sip_rxsoft *rxs; 2038 struct mbuf *m; 2039 u_int32_t cmdsts, extsts; 2040 int i, len; 2041 2042 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2043 rxs = &sc->sc_rxsoft[i]; 2044 2045 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2046 2047 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2048 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2049 len = CMDSTS_SIZE(sc, cmdsts); 2050 2051 /* 2052 * NOTE: OWN is set if owned by _consumer_. We're the 2053 * consumer of the receive ring, so if the bit is clear, 2054 * we have processed all of the packets. 2055 */ 2056 if ((cmdsts & CMDSTS_OWN) == 0) { 2057 /* 2058 * We have processed all of the receive buffers. 2059 */ 2060 break; 2061 } 2062 2063 if (__predict_false(sc->sc_rxdiscard)) { 2064 sip_init_rxdesc(sc, i); 2065 if ((cmdsts & CMDSTS_MORE) == 0) { 2066 /* Reset our state. */ 2067 sc->sc_rxdiscard = 0; 2068 } 2069 continue; 2070 } 2071 2072 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2073 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2074 2075 m = rxs->rxs_mbuf; 2076 2077 /* 2078 * Add a new receive buffer to the ring. 2079 */ 2080 if (sipcom_add_rxbuf(sc, i) != 0) { 2081 /* 2082 * Failed, throw away what we've done so 2083 * far, and discard the rest of the packet. 2084 */ 2085 ifp->if_ierrors++; 2086 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2087 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2088 sip_init_rxdesc(sc, i); 2089 if (cmdsts & CMDSTS_MORE) 2090 sc->sc_rxdiscard = 1; 2091 if (sc->sc_rxhead != NULL) 2092 m_freem(sc->sc_rxhead); 2093 sip_rxchain_reset(sc); 2094 continue; 2095 } 2096 2097 sip_rxchain_link(sc, m); 2098 2099 m->m_len = len; 2100 2101 /* 2102 * If this is not the end of the packet, keep 2103 * looking. 2104 */ 2105 if (cmdsts & CMDSTS_MORE) { 2106 sc->sc_rxlen += len; 2107 continue; 2108 } 2109 2110 /* 2111 * Okay, we have the entire packet now. The chip includes 2112 * the FCS, so we need to trim it. 2113 */ 2114 m->m_len -= ETHER_CRC_LEN; 2115 2116 *sc->sc_rxtailp = NULL; 2117 len = m->m_len + sc->sc_rxlen; 2118 m = sc->sc_rxhead; 2119 2120 sip_rxchain_reset(sc); 2121 2122 /* 2123 * If an error occurred, update stats and drop the packet. 2124 */ 2125 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2126 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2127 ifp->if_ierrors++; 2128 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2129 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2130 /* Receive overrun handled elsewhere. */ 2131 printf("%s: receive descriptor error\n", 2132 device_xname(sc->sc_dev)); 2133 } 2134 #define PRINTERR(bit, str) \ 2135 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2136 (cmdsts & (bit)) != 0) \ 2137 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2138 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2139 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2140 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2141 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2142 #undef PRINTERR 2143 m_freem(m); 2144 continue; 2145 } 2146 2147 /* 2148 * If the packet is small enough to fit in a 2149 * single header mbuf, allocate one and copy 2150 * the data into it. This greatly reduces 2151 * memory consumption when we receive lots 2152 * of small packets. 2153 */ 2154 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2155 struct mbuf *nm; 2156 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2157 if (nm == NULL) { 2158 ifp->if_ierrors++; 2159 m_freem(m); 2160 continue; 2161 } 2162 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2163 nm->m_data += 2; 2164 nm->m_pkthdr.len = nm->m_len = len; 2165 m_copydata(m, 0, len, mtod(nm, void *)); 2166 m_freem(m); 2167 m = nm; 2168 } 2169 #ifndef __NO_STRICT_ALIGNMENT 2170 else { 2171 /* 2172 * The DP83820's receive buffers must be 4-byte 2173 * aligned. But this means that the data after 2174 * the Ethernet header is misaligned. To compensate, 2175 * we have artificially shortened the buffer size 2176 * in the descriptor, and we do an overlapping copy 2177 * of the data two bytes further in (in the first 2178 * buffer of the chain only). 2179 */ 2180 memmove(mtod(m, char *) + 2, mtod(m, void *), 2181 m->m_len); 2182 m->m_data += 2; 2183 } 2184 #endif /* ! __NO_STRICT_ALIGNMENT */ 2185 2186 /* 2187 * If VLANs are enabled, VLAN packets have been unwrapped 2188 * for us. Associate the tag with the packet. 2189 */ 2190 2191 /* 2192 * Again, byte swapping is tricky. Hardware provided 2193 * the tag in the network byte order, but extsts was 2194 * passed through le32toh() in the meantime. On a 2195 * big-endian machine, we need to swap it again. On a 2196 * little-endian machine, we need to convert from the 2197 * network to host byte order. This means that we must 2198 * swap it in any case, so unconditional swap instead 2199 * of htons() is used. 2200 */ 2201 if ((extsts & EXTSTS_VPKT) != 0) { 2202 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2203 continue); 2204 } 2205 2206 /* 2207 * Set the incoming checksum information for the 2208 * packet. 2209 */ 2210 if ((extsts & EXTSTS_IPPKT) != 0) { 2211 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2212 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2213 if (extsts & EXTSTS_Rx_IPERR) 2214 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2215 if (extsts & EXTSTS_TCPPKT) { 2216 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2217 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2218 if (extsts & EXTSTS_Rx_TCPERR) 2219 m->m_pkthdr.csum_flags |= 2220 M_CSUM_TCP_UDP_BAD; 2221 } else if (extsts & EXTSTS_UDPPKT) { 2222 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2223 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2224 if (extsts & EXTSTS_Rx_UDPERR) 2225 m->m_pkthdr.csum_flags |= 2226 M_CSUM_TCP_UDP_BAD; 2227 } 2228 } 2229 2230 ifp->if_ipackets++; 2231 m->m_pkthdr.rcvif = ifp; 2232 m->m_pkthdr.len = len; 2233 2234 /* 2235 * Pass this up to any BPF listeners, but only 2236 * pass if up the stack if it's for us. 2237 */ 2238 bpf_mtap(ifp, m); 2239 2240 /* Pass it on. */ 2241 (*ifp->if_input)(ifp, m); 2242 } 2243 2244 /* Update the receive pointer. */ 2245 sc->sc_rxptr = i; 2246 } 2247 2248 /* 2249 * sip_rxintr: 2250 * 2251 * Helper; handle receive interrupts on 10/100 parts. 2252 */ 2253 static void 2254 sip_rxintr(struct sip_softc *sc) 2255 { 2256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2257 struct sip_rxsoft *rxs; 2258 struct mbuf *m; 2259 u_int32_t cmdsts; 2260 int i, len; 2261 2262 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2263 rxs = &sc->sc_rxsoft[i]; 2264 2265 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2266 2267 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2268 2269 /* 2270 * NOTE: OWN is set if owned by _consumer_. We're the 2271 * consumer of the receive ring, so if the bit is clear, 2272 * we have processed all of the packets. 2273 */ 2274 if ((cmdsts & CMDSTS_OWN) == 0) { 2275 /* 2276 * We have processed all of the receive buffers. 2277 */ 2278 break; 2279 } 2280 2281 /* 2282 * If any collisions were seen on the wire, count one. 2283 */ 2284 if (cmdsts & CMDSTS_Rx_COL) 2285 ifp->if_collisions++; 2286 2287 /* 2288 * If an error occurred, update stats, clear the status 2289 * word, and leave the packet buffer in place. It will 2290 * simply be reused the next time the ring comes around. 2291 */ 2292 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2293 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2294 ifp->if_ierrors++; 2295 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2296 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2297 /* Receive overrun handled elsewhere. */ 2298 printf("%s: receive descriptor error\n", 2299 device_xname(sc->sc_dev)); 2300 } 2301 #define PRINTERR(bit, str) \ 2302 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2303 (cmdsts & (bit)) != 0) \ 2304 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2305 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2306 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2307 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2308 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2309 #undef PRINTERR 2310 sip_init_rxdesc(sc, i); 2311 continue; 2312 } 2313 2314 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2315 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2316 2317 /* 2318 * No errors; receive the packet. Note, the SiS 900 2319 * includes the CRC with every packet. 2320 */ 2321 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2322 2323 #ifdef __NO_STRICT_ALIGNMENT 2324 /* 2325 * If the packet is small enough to fit in a 2326 * single header mbuf, allocate one and copy 2327 * the data into it. This greatly reduces 2328 * memory consumption when we receive lots 2329 * of small packets. 2330 * 2331 * Otherwise, we add a new buffer to the receive 2332 * chain. If this fails, we drop the packet and 2333 * recycle the old buffer. 2334 */ 2335 if (sip_copy_small != 0 && len <= MHLEN) { 2336 MGETHDR(m, M_DONTWAIT, MT_DATA); 2337 if (m == NULL) 2338 goto dropit; 2339 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2340 memcpy(mtod(m, void *), 2341 mtod(rxs->rxs_mbuf, void *), len); 2342 sip_init_rxdesc(sc, i); 2343 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2344 rxs->rxs_dmamap->dm_mapsize, 2345 BUS_DMASYNC_PREREAD); 2346 } else { 2347 m = rxs->rxs_mbuf; 2348 if (sipcom_add_rxbuf(sc, i) != 0) { 2349 dropit: 2350 ifp->if_ierrors++; 2351 sip_init_rxdesc(sc, i); 2352 bus_dmamap_sync(sc->sc_dmat, 2353 rxs->rxs_dmamap, 0, 2354 rxs->rxs_dmamap->dm_mapsize, 2355 BUS_DMASYNC_PREREAD); 2356 continue; 2357 } 2358 } 2359 #else 2360 /* 2361 * The SiS 900's receive buffers must be 4-byte aligned. 2362 * But this means that the data after the Ethernet header 2363 * is misaligned. We must allocate a new buffer and 2364 * copy the data, shifted forward 2 bytes. 2365 */ 2366 MGETHDR(m, M_DONTWAIT, MT_DATA); 2367 if (m == NULL) { 2368 dropit: 2369 ifp->if_ierrors++; 2370 sip_init_rxdesc(sc, i); 2371 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2372 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2373 continue; 2374 } 2375 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2376 if (len > (MHLEN - 2)) { 2377 MCLGET(m, M_DONTWAIT); 2378 if ((m->m_flags & M_EXT) == 0) { 2379 m_freem(m); 2380 goto dropit; 2381 } 2382 } 2383 m->m_data += 2; 2384 2385 /* 2386 * Note that we use clusters for incoming frames, so the 2387 * buffer is virtually contiguous. 2388 */ 2389 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2390 2391 /* Allow the receive descriptor to continue using its mbuf. */ 2392 sip_init_rxdesc(sc, i); 2393 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2394 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2395 #endif /* __NO_STRICT_ALIGNMENT */ 2396 2397 ifp->if_ipackets++; 2398 m->m_pkthdr.rcvif = ifp; 2399 m->m_pkthdr.len = m->m_len = len; 2400 2401 /* 2402 * Pass this up to any BPF listeners, but only 2403 * pass if up the stack if it's for us. 2404 */ 2405 bpf_mtap(ifp, m); 2406 2407 /* Pass it on. */ 2408 (*ifp->if_input)(ifp, m); 2409 } 2410 2411 /* Update the receive pointer. */ 2412 sc->sc_rxptr = i; 2413 } 2414 2415 /* 2416 * sip_tick: 2417 * 2418 * One second timer, used to tick the MII. 2419 */ 2420 static void 2421 sipcom_tick(void *arg) 2422 { 2423 struct sip_softc *sc = arg; 2424 int s; 2425 2426 s = splnet(); 2427 #ifdef SIP_EVENT_COUNTERS 2428 if (sc->sc_gigabit) { 2429 /* Read PAUSE related counts from MIB registers. */ 2430 sc->sc_ev_rxpause.ev_count += 2431 bus_space_read_4(sc->sc_st, sc->sc_sh, 2432 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2433 sc->sc_ev_txpause.ev_count += 2434 bus_space_read_4(sc->sc_st, sc->sc_sh, 2435 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2436 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2437 } 2438 #endif /* SIP_EVENT_COUNTERS */ 2439 mii_tick(&sc->sc_mii); 2440 splx(s); 2441 2442 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2443 } 2444 2445 /* 2446 * sip_reset: 2447 * 2448 * Perform a soft reset on the SiS 900. 2449 */ 2450 static bool 2451 sipcom_reset(struct sip_softc *sc) 2452 { 2453 bus_space_tag_t st = sc->sc_st; 2454 bus_space_handle_t sh = sc->sc_sh; 2455 int i; 2456 2457 bus_space_write_4(st, sh, SIP_IER, 0); 2458 bus_space_write_4(st, sh, SIP_IMR, 0); 2459 bus_space_write_4(st, sh, SIP_RFCR, 0); 2460 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2461 2462 for (i = 0; i < SIP_TIMEOUT; i++) { 2463 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2464 break; 2465 delay(2); 2466 } 2467 2468 if (i == SIP_TIMEOUT) { 2469 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2470 return false; 2471 } 2472 2473 delay(1000); 2474 2475 if (sc->sc_gigabit) { 2476 /* 2477 * Set the general purpose I/O bits. Do it here in case we 2478 * need to have GPIO set up to talk to the media interface. 2479 */ 2480 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2481 delay(1000); 2482 } 2483 return true; 2484 } 2485 2486 static void 2487 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2488 { 2489 u_int32_t reg; 2490 bus_space_tag_t st = sc->sc_st; 2491 bus_space_handle_t sh = sc->sc_sh; 2492 /* 2493 * Initialize the VLAN/IP receive control register. 2494 * We enable checksum computation on all incoming 2495 * packets, and do not reject packets w/ bad checksums. 2496 */ 2497 reg = 0; 2498 if (capenable & 2499 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2500 reg |= VRCR_IPEN; 2501 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2502 reg |= VRCR_VTDEN|VRCR_VTREN; 2503 bus_space_write_4(st, sh, SIP_VRCR, reg); 2504 2505 /* 2506 * Initialize the VLAN/IP transmit control register. 2507 * We enable outgoing checksum computation on a 2508 * per-packet basis. 2509 */ 2510 reg = 0; 2511 if (capenable & 2512 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2513 reg |= VTCR_PPCHK; 2514 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2515 reg |= VTCR_VPPTI; 2516 bus_space_write_4(st, sh, SIP_VTCR, reg); 2517 2518 /* 2519 * If we're using VLANs, initialize the VLAN data register. 2520 * To understand why we bswap the VLAN Ethertype, see section 2521 * 4.2.36 of the DP83820 manual. 2522 */ 2523 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2524 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2525 } 2526 2527 /* 2528 * sip_init: [ ifnet interface function ] 2529 * 2530 * Initialize the interface. Must be called at splnet(). 2531 */ 2532 static int 2533 sipcom_init(struct ifnet *ifp) 2534 { 2535 struct sip_softc *sc = ifp->if_softc; 2536 bus_space_tag_t st = sc->sc_st; 2537 bus_space_handle_t sh = sc->sc_sh; 2538 struct sip_txsoft *txs; 2539 struct sip_rxsoft *rxs; 2540 struct sip_desc *sipd; 2541 int i, error = 0; 2542 2543 if (device_is_active(sc->sc_dev)) { 2544 /* 2545 * Cancel any pending I/O. 2546 */ 2547 sipcom_stop(ifp, 0); 2548 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2549 !device_is_active(sc->sc_dev)) 2550 return 0; 2551 2552 /* 2553 * Reset the chip to a known state. 2554 */ 2555 if (!sipcom_reset(sc)) 2556 return EBUSY; 2557 2558 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2559 /* 2560 * DP83815 manual, page 78: 2561 * 4.4 Recommended Registers Configuration 2562 * For optimum performance of the DP83815, version noted 2563 * as DP83815CVNG (SRR = 203h), the listed register 2564 * modifications must be followed in sequence... 2565 * 2566 * It's not clear if this should be 302h or 203h because that 2567 * chip name is listed as SRR 302h in the description of the 2568 * SRR register. However, my revision 302h DP83815 on the 2569 * Netgear FA311 purchased in 02/2001 needs these settings 2570 * to avoid tons of errors in AcceptPerfectMatch (non- 2571 * IFF_PROMISC) mode. I do not know if other revisions need 2572 * this set or not. [briggs -- 09 March 2001] 2573 * 2574 * Note that only the low-order 12 bits of 0xe4 are documented 2575 * and that this sets reserved bits in that register. 2576 */ 2577 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2578 2579 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2580 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2581 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2582 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2583 2584 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2585 } 2586 2587 /* 2588 * Initialize the transmit descriptor ring. 2589 */ 2590 for (i = 0; i < sc->sc_ntxdesc; i++) { 2591 sipd = &sc->sc_txdescs[i]; 2592 memset(sipd, 0, sizeof(struct sip_desc)); 2593 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2594 } 2595 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2596 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2597 sc->sc_txfree = sc->sc_ntxdesc; 2598 sc->sc_txnext = 0; 2599 sc->sc_txwin = 0; 2600 2601 /* 2602 * Initialize the transmit job descriptors. 2603 */ 2604 SIMPLEQ_INIT(&sc->sc_txfreeq); 2605 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2606 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2607 txs = &sc->sc_txsoft[i]; 2608 txs->txs_mbuf = NULL; 2609 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2610 } 2611 2612 /* 2613 * Initialize the receive descriptor and receive job 2614 * descriptor rings. 2615 */ 2616 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2617 rxs = &sc->sc_rxsoft[i]; 2618 if (rxs->rxs_mbuf == NULL) { 2619 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2620 printf("%s: unable to allocate or map rx " 2621 "buffer %d, error = %d\n", 2622 device_xname(sc->sc_dev), i, error); 2623 /* 2624 * XXX Should attempt to run with fewer receive 2625 * XXX buffers instead of just failing. 2626 */ 2627 sipcom_rxdrain(sc); 2628 goto out; 2629 } 2630 } else 2631 sip_init_rxdesc(sc, i); 2632 } 2633 sc->sc_rxptr = 0; 2634 sc->sc_rxdiscard = 0; 2635 sip_rxchain_reset(sc); 2636 2637 /* 2638 * Set the configuration register; it's already initialized 2639 * in sip_attach(). 2640 */ 2641 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2642 2643 /* 2644 * Initialize the prototype TXCFG register. 2645 */ 2646 if (sc->sc_gigabit) { 2647 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2648 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2649 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2650 SIP_SIS900_REV(sc, SIS_REV_960) || 2651 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2652 (sc->sc_cfg & CFG_EDBMASTEN)) { 2653 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2654 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2655 } else { 2656 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2657 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2658 } 2659 2660 sc->sc_txcfg |= TXCFG_ATP | 2661 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2662 sc->sc_tx_drain_thresh; 2663 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2664 2665 /* 2666 * Initialize the receive drain threshold if we have never 2667 * done so. 2668 */ 2669 if (sc->sc_rx_drain_thresh == 0) { 2670 /* 2671 * XXX This value should be tuned. This is set to the 2672 * maximum of 248 bytes, and we may be able to improve 2673 * performance by decreasing it (although we should never 2674 * set this value lower than 2; 14 bytes are required to 2675 * filter the packet). 2676 */ 2677 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2678 } 2679 2680 /* 2681 * Initialize the prototype RXCFG register. 2682 */ 2683 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2684 /* 2685 * Accept long packets (including FCS) so we can handle 2686 * 802.1q-tagged frames and jumbo frames properly. 2687 */ 2688 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2689 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2690 sc->sc_rxcfg |= RXCFG_ALP; 2691 2692 /* 2693 * Checksum offloading is disabled if the user selects an MTU 2694 * larger than 8109. (FreeBSD says 8152, but there is emperical 2695 * evidence that >8109 does not work on some boards, such as the 2696 * Planex GN-1000TE). 2697 */ 2698 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2699 (ifp->if_capenable & 2700 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2701 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2702 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2703 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2704 "disabled.\n", device_xname(sc->sc_dev)); 2705 ifp->if_capenable &= 2706 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2707 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2708 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2709 ifp->if_csum_flags_tx = 0; 2710 ifp->if_csum_flags_rx = 0; 2711 } 2712 2713 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2714 2715 if (sc->sc_gigabit) 2716 sipcom_dp83820_init(sc, ifp->if_capenable); 2717 2718 /* 2719 * Give the transmit and receive rings to the chip. 2720 */ 2721 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2722 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2723 2724 /* 2725 * Initialize the interrupt mask. 2726 */ 2727 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2728 sc->sc_bits.b_isr_sserr | 2729 sc->sc_bits.b_isr_rmabt | 2730 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2731 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2732 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2733 2734 /* Set up the receive filter. */ 2735 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2736 2737 /* 2738 * Tune sc_rx_flow_thresh. 2739 * XXX "More than 8KB" is too short for jumbo frames. 2740 * XXX TODO: Threshold value should be user-settable. 2741 */ 2742 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2743 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2744 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2745 2746 /* 2747 * Set the current media. Do this after initializing the prototype 2748 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2749 * control. 2750 */ 2751 if ((error = ether_mediachange(ifp)) != 0) 2752 goto out; 2753 2754 /* 2755 * Set the interrupt hold-off timer to 100us. 2756 */ 2757 if (sc->sc_gigabit) 2758 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2759 2760 /* 2761 * Enable interrupts. 2762 */ 2763 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2764 2765 /* 2766 * Start the transmit and receive processes. 2767 */ 2768 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2769 2770 /* 2771 * Start the one second MII clock. 2772 */ 2773 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2774 2775 /* 2776 * ...all done! 2777 */ 2778 ifp->if_flags |= IFF_RUNNING; 2779 ifp->if_flags &= ~IFF_OACTIVE; 2780 sc->sc_if_flags = ifp->if_flags; 2781 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2782 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2783 sc->sc_prev.if_capenable = ifp->if_capenable; 2784 2785 out: 2786 if (error) 2787 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2788 return (error); 2789 } 2790 2791 /* 2792 * sip_drain: 2793 * 2794 * Drain the receive queue. 2795 */ 2796 static void 2797 sipcom_rxdrain(struct sip_softc *sc) 2798 { 2799 struct sip_rxsoft *rxs; 2800 int i; 2801 2802 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2803 rxs = &sc->sc_rxsoft[i]; 2804 if (rxs->rxs_mbuf != NULL) { 2805 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2806 m_freem(rxs->rxs_mbuf); 2807 rxs->rxs_mbuf = NULL; 2808 } 2809 } 2810 } 2811 2812 /* 2813 * sip_stop: [ ifnet interface function ] 2814 * 2815 * Stop transmission on the interface. 2816 */ 2817 static void 2818 sipcom_stop(struct ifnet *ifp, int disable) 2819 { 2820 struct sip_softc *sc = ifp->if_softc; 2821 bus_space_tag_t st = sc->sc_st; 2822 bus_space_handle_t sh = sc->sc_sh; 2823 struct sip_txsoft *txs; 2824 u_int32_t cmdsts = 0; /* DEBUG */ 2825 2826 /* 2827 * Stop the one second clock. 2828 */ 2829 callout_stop(&sc->sc_tick_ch); 2830 2831 /* Down the MII. */ 2832 mii_down(&sc->sc_mii); 2833 2834 if (device_is_active(sc->sc_dev)) { 2835 /* 2836 * Disable interrupts. 2837 */ 2838 bus_space_write_4(st, sh, SIP_IER, 0); 2839 2840 /* 2841 * Stop receiver and transmitter. 2842 */ 2843 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2844 } 2845 2846 /* 2847 * Release any queued transmit buffers. 2848 */ 2849 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2850 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2851 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2852 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2853 CMDSTS_INTR) == 0) 2854 printf("%s: sip_stop: last descriptor does not " 2855 "have INTR bit set\n", device_xname(sc->sc_dev)); 2856 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2857 #ifdef DIAGNOSTIC 2858 if (txs->txs_mbuf == NULL) { 2859 printf("%s: dirty txsoft with no mbuf chain\n", 2860 device_xname(sc->sc_dev)); 2861 panic("sip_stop"); 2862 } 2863 #endif 2864 cmdsts |= /* DEBUG */ 2865 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2866 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2867 m_freem(txs->txs_mbuf); 2868 txs->txs_mbuf = NULL; 2869 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2870 } 2871 2872 /* 2873 * Mark the interface down and cancel the watchdog timer. 2874 */ 2875 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2876 ifp->if_timer = 0; 2877 2878 if (disable) 2879 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2880 2881 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2882 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2883 printf("%s: sip_stop: no INTR bits set in dirty tx " 2884 "descriptors\n", device_xname(sc->sc_dev)); 2885 } 2886 2887 /* 2888 * sip_read_eeprom: 2889 * 2890 * Read data from the serial EEPROM. 2891 */ 2892 static void 2893 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2894 u_int16_t *data) 2895 { 2896 bus_space_tag_t st = sc->sc_st; 2897 bus_space_handle_t sh = sc->sc_sh; 2898 u_int16_t reg; 2899 int i, x; 2900 2901 for (i = 0; i < wordcnt; i++) { 2902 /* Send CHIP SELECT. */ 2903 reg = EROMAR_EECS; 2904 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2905 2906 /* Shift in the READ opcode. */ 2907 for (x = 3; x > 0; x--) { 2908 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2909 reg |= EROMAR_EEDI; 2910 else 2911 reg &= ~EROMAR_EEDI; 2912 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2913 bus_space_write_4(st, sh, SIP_EROMAR, 2914 reg | EROMAR_EESK); 2915 delay(4); 2916 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2917 delay(4); 2918 } 2919 2920 /* Shift in address. */ 2921 for (x = 6; x > 0; x--) { 2922 if ((word + i) & (1 << (x - 1))) 2923 reg |= EROMAR_EEDI; 2924 else 2925 reg &= ~EROMAR_EEDI; 2926 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2927 bus_space_write_4(st, sh, SIP_EROMAR, 2928 reg | EROMAR_EESK); 2929 delay(4); 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 delay(4); 2932 } 2933 2934 /* Shift out data. */ 2935 reg = EROMAR_EECS; 2936 data[i] = 0; 2937 for (x = 16; x > 0; x--) { 2938 bus_space_write_4(st, sh, SIP_EROMAR, 2939 reg | EROMAR_EESK); 2940 delay(4); 2941 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2942 data[i] |= (1 << (x - 1)); 2943 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2944 delay(4); 2945 } 2946 2947 /* Clear CHIP SELECT. */ 2948 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2949 delay(4); 2950 } 2951 } 2952 2953 /* 2954 * sipcom_add_rxbuf: 2955 * 2956 * Add a receive buffer to the indicated descriptor. 2957 */ 2958 static int 2959 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2960 { 2961 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2962 struct mbuf *m; 2963 int error; 2964 2965 MGETHDR(m, M_DONTWAIT, MT_DATA); 2966 if (m == NULL) 2967 return (ENOBUFS); 2968 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2969 2970 MCLGET(m, M_DONTWAIT); 2971 if ((m->m_flags & M_EXT) == 0) { 2972 m_freem(m); 2973 return (ENOBUFS); 2974 } 2975 2976 /* XXX I don't believe this is necessary. --dyoung */ 2977 if (sc->sc_gigabit) 2978 m->m_len = sc->sc_parm->p_rxbuf_len; 2979 2980 if (rxs->rxs_mbuf != NULL) 2981 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2982 2983 rxs->rxs_mbuf = m; 2984 2985 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2986 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2987 BUS_DMA_READ|BUS_DMA_NOWAIT); 2988 if (error) { 2989 printf("%s: can't load rx DMA map %d, error = %d\n", 2990 device_xname(sc->sc_dev), idx, error); 2991 panic("%s", __func__); /* XXX */ 2992 } 2993 2994 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2995 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2996 2997 sip_init_rxdesc(sc, idx); 2998 2999 return (0); 3000 } 3001 3002 /* 3003 * sip_sis900_set_filter: 3004 * 3005 * Set up the receive filter. 3006 */ 3007 static void 3008 sipcom_sis900_set_filter(struct sip_softc *sc) 3009 { 3010 bus_space_tag_t st = sc->sc_st; 3011 bus_space_handle_t sh = sc->sc_sh; 3012 struct ethercom *ec = &sc->sc_ethercom; 3013 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3014 struct ether_multi *enm; 3015 const u_int8_t *cp; 3016 struct ether_multistep step; 3017 u_int32_t crc, mchash[16]; 3018 3019 /* 3020 * Initialize the prototype RFCR. 3021 */ 3022 sc->sc_rfcr = RFCR_RFEN; 3023 if (ifp->if_flags & IFF_BROADCAST) 3024 sc->sc_rfcr |= RFCR_AAB; 3025 if (ifp->if_flags & IFF_PROMISC) { 3026 sc->sc_rfcr |= RFCR_AAP; 3027 goto allmulti; 3028 } 3029 3030 /* 3031 * Set up the multicast address filter by passing all multicast 3032 * addresses through a CRC generator, and then using the high-order 3033 * 6 bits as an index into the 128 bit multicast hash table (only 3034 * the lower 16 bits of each 32 bit multicast hash register are 3035 * valid). The high order bits select the register, while the 3036 * rest of the bits select the bit within the register. 3037 */ 3038 3039 memset(mchash, 0, sizeof(mchash)); 3040 3041 /* 3042 * SiS900 (at least SiS963) requires us to register the address of 3043 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3044 */ 3045 crc = 0x0ed423f9; 3046 3047 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3048 SIP_SIS900_REV(sc, SIS_REV_960) || 3049 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3050 /* Just want the 8 most significant bits. */ 3051 crc >>= 24; 3052 } else { 3053 /* Just want the 7 most significant bits. */ 3054 crc >>= 25; 3055 } 3056 3057 /* Set the corresponding bit in the hash table. */ 3058 mchash[crc >> 4] |= 1 << (crc & 0xf); 3059 3060 ETHER_FIRST_MULTI(step, ec, enm); 3061 while (enm != NULL) { 3062 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3063 /* 3064 * We must listen to a range of multicast addresses. 3065 * For now, just accept all multicasts, rather than 3066 * trying to set only those filter bits needed to match 3067 * the range. (At this time, the only use of address 3068 * ranges is for IP multicast routing, for which the 3069 * range is big enough to require all bits set.) 3070 */ 3071 goto allmulti; 3072 } 3073 3074 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3075 3076 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3077 SIP_SIS900_REV(sc, SIS_REV_960) || 3078 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3079 /* Just want the 8 most significant bits. */ 3080 crc >>= 24; 3081 } else { 3082 /* Just want the 7 most significant bits. */ 3083 crc >>= 25; 3084 } 3085 3086 /* Set the corresponding bit in the hash table. */ 3087 mchash[crc >> 4] |= 1 << (crc & 0xf); 3088 3089 ETHER_NEXT_MULTI(step, enm); 3090 } 3091 3092 ifp->if_flags &= ~IFF_ALLMULTI; 3093 goto setit; 3094 3095 allmulti: 3096 ifp->if_flags |= IFF_ALLMULTI; 3097 sc->sc_rfcr |= RFCR_AAM; 3098 3099 setit: 3100 #define FILTER_EMIT(addr, data) \ 3101 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3102 delay(1); \ 3103 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3104 delay(1) 3105 3106 /* 3107 * Disable receive filter, and program the node address. 3108 */ 3109 cp = CLLADDR(ifp->if_sadl); 3110 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3111 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3112 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3113 3114 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3115 /* 3116 * Program the multicast hash table. 3117 */ 3118 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3119 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3120 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3121 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3122 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3123 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3124 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3125 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3126 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3127 SIP_SIS900_REV(sc, SIS_REV_960) || 3128 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3129 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3130 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3131 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3132 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3133 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3134 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3135 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3136 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3137 } 3138 } 3139 #undef FILTER_EMIT 3140 3141 /* 3142 * Re-enable the receiver filter. 3143 */ 3144 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3145 } 3146 3147 /* 3148 * sip_dp83815_set_filter: 3149 * 3150 * Set up the receive filter. 3151 */ 3152 static void 3153 sipcom_dp83815_set_filter(struct sip_softc *sc) 3154 { 3155 bus_space_tag_t st = sc->sc_st; 3156 bus_space_handle_t sh = sc->sc_sh; 3157 struct ethercom *ec = &sc->sc_ethercom; 3158 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3159 struct ether_multi *enm; 3160 const u_int8_t *cp; 3161 struct ether_multistep step; 3162 u_int32_t crc, hash, slot, bit; 3163 #define MCHASH_NWORDS_83820 128 3164 #define MCHASH_NWORDS_83815 32 3165 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3166 u_int16_t mchash[MCHASH_NWORDS]; 3167 int i; 3168 3169 /* 3170 * Initialize the prototype RFCR. 3171 * Enable the receive filter, and accept on 3172 * Perfect (destination address) Match 3173 * If IFF_BROADCAST, also accept all broadcast packets. 3174 * If IFF_PROMISC, accept all unicast packets (and later, set 3175 * IFF_ALLMULTI and accept all multicast, too). 3176 */ 3177 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3178 if (ifp->if_flags & IFF_BROADCAST) 3179 sc->sc_rfcr |= RFCR_AAB; 3180 if (ifp->if_flags & IFF_PROMISC) { 3181 sc->sc_rfcr |= RFCR_AAP; 3182 goto allmulti; 3183 } 3184 3185 /* 3186 * Set up the DP83820/DP83815 multicast address filter by 3187 * passing all multicast addresses through a CRC generator, 3188 * and then using the high-order 11/9 bits as an index into 3189 * the 2048/512 bit multicast hash table. The high-order 3190 * 7/5 bits select the slot, while the low-order 4 bits 3191 * select the bit within the slot. Note that only the low 3192 * 16-bits of each filter word are used, and there are 3193 * 128/32 filter words. 3194 */ 3195 3196 memset(mchash, 0, sizeof(mchash)); 3197 3198 ifp->if_flags &= ~IFF_ALLMULTI; 3199 ETHER_FIRST_MULTI(step, ec, enm); 3200 if (enm == NULL) 3201 goto setit; 3202 while (enm != NULL) { 3203 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3204 /* 3205 * We must listen to a range of multicast addresses. 3206 * For now, just accept all multicasts, rather than 3207 * trying to set only those filter bits needed to match 3208 * the range. (At this time, the only use of address 3209 * ranges is for IP multicast routing, for which the 3210 * range is big enough to require all bits set.) 3211 */ 3212 goto allmulti; 3213 } 3214 3215 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3216 3217 if (sc->sc_gigabit) { 3218 /* Just want the 11 most significant bits. */ 3219 hash = crc >> 21; 3220 } else { 3221 /* Just want the 9 most significant bits. */ 3222 hash = crc >> 23; 3223 } 3224 3225 slot = hash >> 4; 3226 bit = hash & 0xf; 3227 3228 /* Set the corresponding bit in the hash table. */ 3229 mchash[slot] |= 1 << bit; 3230 3231 ETHER_NEXT_MULTI(step, enm); 3232 } 3233 sc->sc_rfcr |= RFCR_MHEN; 3234 goto setit; 3235 3236 allmulti: 3237 ifp->if_flags |= IFF_ALLMULTI; 3238 sc->sc_rfcr |= RFCR_AAM; 3239 3240 setit: 3241 #define FILTER_EMIT(addr, data) \ 3242 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3243 delay(1); \ 3244 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3245 delay(1) 3246 3247 /* 3248 * Disable receive filter, and program the node address. 3249 */ 3250 cp = CLLADDR(ifp->if_sadl); 3251 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3252 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3253 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3254 3255 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3256 int nwords = 3257 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3258 /* 3259 * Program the multicast hash table. 3260 */ 3261 for (i = 0; i < nwords; i++) { 3262 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3263 } 3264 } 3265 #undef FILTER_EMIT 3266 #undef MCHASH_NWORDS 3267 #undef MCHASH_NWORDS_83815 3268 #undef MCHASH_NWORDS_83820 3269 3270 /* 3271 * Re-enable the receiver filter. 3272 */ 3273 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3274 } 3275 3276 /* 3277 * sip_dp83820_mii_readreg: [mii interface function] 3278 * 3279 * Read a PHY register on the MII of the DP83820. 3280 */ 3281 static int 3282 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3283 { 3284 struct sip_softc *sc = device_private(self); 3285 3286 if (sc->sc_cfg & CFG_TBI_EN) { 3287 bus_addr_t tbireg; 3288 int rv; 3289 3290 if (phy != 0) 3291 return (0); 3292 3293 switch (reg) { 3294 case MII_BMCR: tbireg = SIP_TBICR; break; 3295 case MII_BMSR: tbireg = SIP_TBISR; break; 3296 case MII_ANAR: tbireg = SIP_TANAR; break; 3297 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3298 case MII_ANER: tbireg = SIP_TANER; break; 3299 case MII_EXTSR: 3300 /* 3301 * Don't even bother reading the TESR register. 3302 * The manual documents that the device has 3303 * 1000baseX full/half capability, but the 3304 * register itself seems read back 0 on some 3305 * boards. Just hard-code the result. 3306 */ 3307 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3308 3309 default: 3310 return (0); 3311 } 3312 3313 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3314 if (tbireg == SIP_TBISR) { 3315 /* LINK and ACOMP are switched! */ 3316 int val = rv; 3317 3318 rv = 0; 3319 if (val & TBISR_MR_LINK_STATUS) 3320 rv |= BMSR_LINK; 3321 if (val & TBISR_MR_AN_COMPLETE) 3322 rv |= BMSR_ACOMP; 3323 3324 /* 3325 * The manual claims this register reads back 0 3326 * on hard and soft reset. But we want to let 3327 * the gentbi driver know that we support auto- 3328 * negotiation, so hard-code this bit in the 3329 * result. 3330 */ 3331 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3332 } 3333 3334 return (rv); 3335 } 3336 3337 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3338 } 3339 3340 /* 3341 * sip_dp83820_mii_writereg: [mii interface function] 3342 * 3343 * Write a PHY register on the MII of the DP83820. 3344 */ 3345 static void 3346 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3347 { 3348 struct sip_softc *sc = device_private(self); 3349 3350 if (sc->sc_cfg & CFG_TBI_EN) { 3351 bus_addr_t tbireg; 3352 3353 if (phy != 0) 3354 return; 3355 3356 switch (reg) { 3357 case MII_BMCR: tbireg = SIP_TBICR; break; 3358 case MII_ANAR: tbireg = SIP_TANAR; break; 3359 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3360 default: 3361 return; 3362 } 3363 3364 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3365 return; 3366 } 3367 3368 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3369 } 3370 3371 /* 3372 * sip_dp83820_mii_statchg: [mii interface function] 3373 * 3374 * Callback from MII layer when media changes. 3375 */ 3376 static void 3377 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3378 { 3379 struct sip_softc *sc = ifp->if_softc; 3380 struct mii_data *mii = &sc->sc_mii; 3381 u_int32_t cfg, pcr; 3382 3383 /* 3384 * Get flow control negotiation result. 3385 */ 3386 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3387 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3388 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3389 mii->mii_media_active &= ~IFM_ETH_FMASK; 3390 } 3391 3392 /* 3393 * Update TXCFG for full-duplex operation. 3394 */ 3395 if ((mii->mii_media_active & IFM_FDX) != 0) 3396 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3397 else 3398 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3399 3400 /* 3401 * Update RXCFG for full-duplex or loopback. 3402 */ 3403 if ((mii->mii_media_active & IFM_FDX) != 0 || 3404 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3405 sc->sc_rxcfg |= RXCFG_ATX; 3406 else 3407 sc->sc_rxcfg &= ~RXCFG_ATX; 3408 3409 /* 3410 * Update CFG for MII/GMII. 3411 */ 3412 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3413 cfg = sc->sc_cfg | CFG_MODE_1000; 3414 else 3415 cfg = sc->sc_cfg; 3416 3417 /* 3418 * 802.3x flow control. 3419 */ 3420 pcr = 0; 3421 if (sc->sc_flowflags & IFM_FLOW) { 3422 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3423 pcr |= sc->sc_rx_flow_thresh; 3424 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3425 pcr |= PCR_PSEN | PCR_PS_MCAST; 3426 } 3427 3428 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3429 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3430 sc->sc_txcfg); 3431 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3432 sc->sc_rxcfg); 3433 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3434 } 3435 3436 /* 3437 * sip_mii_bitbang_read: [mii bit-bang interface function] 3438 * 3439 * Read the MII serial port for the MII bit-bang module. 3440 */ 3441 static u_int32_t 3442 sipcom_mii_bitbang_read(device_t self) 3443 { 3444 struct sip_softc *sc = device_private(self); 3445 3446 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3447 } 3448 3449 /* 3450 * sip_mii_bitbang_write: [mii big-bang interface function] 3451 * 3452 * Write the MII serial port for the MII bit-bang module. 3453 */ 3454 static void 3455 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3456 { 3457 struct sip_softc *sc = device_private(self); 3458 3459 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3460 } 3461 3462 /* 3463 * sip_sis900_mii_readreg: [mii interface function] 3464 * 3465 * Read a PHY register on the MII. 3466 */ 3467 static int 3468 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3469 { 3470 struct sip_softc *sc = device_private(self); 3471 u_int32_t enphy; 3472 3473 /* 3474 * The PHY of recent SiS chipsets is accessed through bitbang 3475 * operations. 3476 */ 3477 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3478 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3479 phy, reg); 3480 3481 #ifndef SIS900_MII_RESTRICT 3482 /* 3483 * The SiS 900 has only an internal PHY on the MII. Only allow 3484 * MII address 0. 3485 */ 3486 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3487 return (0); 3488 #endif 3489 3490 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3491 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3492 ENPHY_RWCMD | ENPHY_ACCESS); 3493 do { 3494 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3495 } while (enphy & ENPHY_ACCESS); 3496 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3497 } 3498 3499 /* 3500 * sip_sis900_mii_writereg: [mii interface function] 3501 * 3502 * Write a PHY register on the MII. 3503 */ 3504 static void 3505 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3506 { 3507 struct sip_softc *sc = device_private(self); 3508 u_int32_t enphy; 3509 3510 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3511 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3512 phy, reg, val); 3513 return; 3514 } 3515 3516 #ifndef SIS900_MII_RESTRICT 3517 /* 3518 * The SiS 900 has only an internal PHY on the MII. Only allow 3519 * MII address 0. 3520 */ 3521 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3522 return; 3523 #endif 3524 3525 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3526 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3527 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3528 do { 3529 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3530 } while (enphy & ENPHY_ACCESS); 3531 } 3532 3533 /* 3534 * sip_sis900_mii_statchg: [mii interface function] 3535 * 3536 * Callback from MII layer when media changes. 3537 */ 3538 static void 3539 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3540 { 3541 struct sip_softc *sc = ifp->if_softc; 3542 struct mii_data *mii = &sc->sc_mii; 3543 u_int32_t flowctl; 3544 3545 /* 3546 * Get flow control negotiation result. 3547 */ 3548 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3549 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3550 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3551 mii->mii_media_active &= ~IFM_ETH_FMASK; 3552 } 3553 3554 /* 3555 * Update TXCFG for full-duplex operation. 3556 */ 3557 if ((mii->mii_media_active & IFM_FDX) != 0) 3558 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3559 else 3560 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3561 3562 /* 3563 * Update RXCFG for full-duplex or loopback. 3564 */ 3565 if ((mii->mii_media_active & IFM_FDX) != 0 || 3566 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3567 sc->sc_rxcfg |= RXCFG_ATX; 3568 else 3569 sc->sc_rxcfg &= ~RXCFG_ATX; 3570 3571 /* 3572 * Update IMR for use of 802.3x flow control. 3573 */ 3574 if (sc->sc_flowflags & IFM_FLOW) { 3575 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3576 flowctl = FLOWCTL_FLOWEN; 3577 } else { 3578 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3579 flowctl = 0; 3580 } 3581 3582 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3583 sc->sc_txcfg); 3584 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3585 sc->sc_rxcfg); 3586 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3587 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3588 } 3589 3590 /* 3591 * sip_dp83815_mii_readreg: [mii interface function] 3592 * 3593 * Read a PHY register on the MII. 3594 */ 3595 static int 3596 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3597 { 3598 struct sip_softc *sc = device_private(self); 3599 u_int32_t val; 3600 3601 /* 3602 * The DP83815 only has an internal PHY. Only allow 3603 * MII address 0. 3604 */ 3605 if (phy != 0) 3606 return (0); 3607 3608 /* 3609 * Apparently, after a reset, the DP83815 can take a while 3610 * to respond. During this recovery period, the BMSR returns 3611 * a value of 0. Catch this -- it's not supposed to happen 3612 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3613 * PHY to come back to life. 3614 * 3615 * This works out because the BMSR is the first register 3616 * read during the PHY probe process. 3617 */ 3618 do { 3619 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3620 } while (reg == MII_BMSR && val == 0); 3621 3622 return (val & 0xffff); 3623 } 3624 3625 /* 3626 * sip_dp83815_mii_writereg: [mii interface function] 3627 * 3628 * Write a PHY register to the MII. 3629 */ 3630 static void 3631 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3632 { 3633 struct sip_softc *sc = device_private(self); 3634 3635 /* 3636 * The DP83815 only has an internal PHY. Only allow 3637 * MII address 0. 3638 */ 3639 if (phy != 0) 3640 return; 3641 3642 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3643 } 3644 3645 /* 3646 * sip_dp83815_mii_statchg: [mii interface function] 3647 * 3648 * Callback from MII layer when media changes. 3649 */ 3650 static void 3651 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3652 { 3653 struct sip_softc *sc = ifp->if_softc; 3654 3655 /* 3656 * Update TXCFG for full-duplex operation. 3657 */ 3658 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3659 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3660 else 3661 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3662 3663 /* 3664 * Update RXCFG for full-duplex or loopback. 3665 */ 3666 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3667 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3668 sc->sc_rxcfg |= RXCFG_ATX; 3669 else 3670 sc->sc_rxcfg &= ~RXCFG_ATX; 3671 3672 /* 3673 * XXX 802.3x flow control. 3674 */ 3675 3676 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3677 sc->sc_txcfg); 3678 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3679 sc->sc_rxcfg); 3680 3681 /* 3682 * Some DP83815s experience problems when used with short 3683 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3684 * sequence adjusts the DSP's signal attenuation to fix the 3685 * problem. 3686 */ 3687 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3688 uint32_t reg; 3689 3690 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3691 3692 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3693 reg &= 0x0fff; 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3695 delay(100); 3696 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3697 reg &= 0x00ff; 3698 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3699 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3700 0x00e8); 3701 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3703 reg | 0x20); 3704 } 3705 3706 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3707 } 3708 } 3709 3710 static void 3711 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3712 const struct pci_attach_args *pa, u_int8_t *enaddr) 3713 { 3714 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3715 u_int8_t cksum, *e, match; 3716 int i; 3717 3718 /* 3719 * EEPROM data format for the DP83820 can be found in 3720 * the DP83820 manual, section 4.2.4. 3721 */ 3722 3723 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3724 3725 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3726 match = ~(match - 1); 3727 3728 cksum = 0x55; 3729 e = (u_int8_t *) eeprom_data; 3730 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3731 cksum += *e++; 3732 3733 if (cksum != match) 3734 printf("%s: Checksum (%x) mismatch (%x)", 3735 device_xname(sc->sc_dev), cksum, match); 3736 3737 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3738 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3739 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3740 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3741 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3742 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3743 } 3744 3745 static void 3746 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3747 { 3748 int i; 3749 3750 /* 3751 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3752 * a reason, but I don't know it. 3753 */ 3754 for (i = 0; i < 10; i++) 3755 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3756 } 3757 3758 static void 3759 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3760 const struct pci_attach_args *pa, u_int8_t *enaddr) 3761 { 3762 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3763 3764 switch (sc->sc_rev) { 3765 case SIS_REV_630S: 3766 case SIS_REV_630E: 3767 case SIS_REV_630EA1: 3768 case SIS_REV_630ET: 3769 case SIS_REV_635: 3770 /* 3771 * The MAC address for the on-board Ethernet of 3772 * the SiS 630 chipset is in the NVRAM. Kick 3773 * the chip into re-loading it from NVRAM, and 3774 * read the MAC address out of the filter registers. 3775 */ 3776 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3777 3778 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3779 RFCR_RFADDR_NODE0); 3780 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3781 0xffff; 3782 3783 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3784 RFCR_RFADDR_NODE2); 3785 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3786 0xffff; 3787 3788 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3789 RFCR_RFADDR_NODE4); 3790 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3791 0xffff; 3792 break; 3793 3794 case SIS_REV_960: 3795 { 3796 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3797 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3798 3799 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3800 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3801 3802 int waittime, i; 3803 3804 /* Allow to read EEPROM from LAN. It is shared 3805 * between a 1394 controller and the NIC and each 3806 * time we access it, we need to set SIS_EECMD_REQ. 3807 */ 3808 SIS_SET_EROMAR(sc, EROMAR_REQ); 3809 3810 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3811 /* Force EEPROM to idle state. */ 3812 3813 /* 3814 * XXX-cube This is ugly. I'll look for docs about it. 3815 */ 3816 SIS_SET_EROMAR(sc, EROMAR_EECS); 3817 sipcom_sis900_eeprom_delay(sc); 3818 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3819 SIS_SET_EROMAR(sc, EROMAR_EESK); 3820 sipcom_sis900_eeprom_delay(sc); 3821 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3822 sipcom_sis900_eeprom_delay(sc); 3823 } 3824 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3825 sipcom_sis900_eeprom_delay(sc); 3826 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3827 3828 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3829 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3830 sizeof(myea) / sizeof(myea[0]), myea); 3831 break; 3832 } 3833 DELAY(1); 3834 } 3835 3836 /* 3837 * Set SIS_EECTL_CLK to high, so a other master 3838 * can operate on the i2c bus. 3839 */ 3840 SIS_SET_EROMAR(sc, EROMAR_EESK); 3841 3842 /* Refuse EEPROM access by LAN */ 3843 SIS_SET_EROMAR(sc, EROMAR_DONE); 3844 } break; 3845 3846 default: 3847 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3848 sizeof(myea) / sizeof(myea[0]), myea); 3849 } 3850 3851 enaddr[0] = myea[0] & 0xff; 3852 enaddr[1] = myea[0] >> 8; 3853 enaddr[2] = myea[1] & 0xff; 3854 enaddr[3] = myea[1] >> 8; 3855 enaddr[4] = myea[2] & 0xff; 3856 enaddr[5] = myea[2] >> 8; 3857 } 3858 3859 /* Table and macro to bit-reverse an octet. */ 3860 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3861 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3862 3863 static void 3864 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3865 const struct pci_attach_args *pa, u_int8_t *enaddr) 3866 { 3867 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3868 u_int8_t cksum, *e, match; 3869 int i; 3870 3871 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3872 sizeof(eeprom_data[0]), eeprom_data); 3873 3874 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3875 match = ~(match - 1); 3876 3877 cksum = 0x55; 3878 e = (u_int8_t *) eeprom_data; 3879 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3880 cksum += *e++; 3881 } 3882 if (cksum != match) { 3883 printf("%s: Checksum (%x) mismatch (%x)", 3884 device_xname(sc->sc_dev), cksum, match); 3885 } 3886 3887 /* 3888 * Unrolled because it makes slightly more sense this way. 3889 * The DP83815 stores the MAC address in bit 0 of word 6 3890 * through bit 15 of word 8. 3891 */ 3892 ea = &eeprom_data[6]; 3893 enaddr[0] = ((*ea & 0x1) << 7); 3894 ea++; 3895 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3896 enaddr[1] = ((*ea & 0x1FE) >> 1); 3897 enaddr[2] = ((*ea & 0x1) << 7); 3898 ea++; 3899 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3900 enaddr[3] = ((*ea & 0x1FE) >> 1); 3901 enaddr[4] = ((*ea & 0x1) << 7); 3902 ea++; 3903 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3904 enaddr[5] = ((*ea & 0x1FE) >> 1); 3905 3906 /* 3907 * In case that's not weird enough, we also need to reverse 3908 * the bits in each byte. This all actually makes more sense 3909 * if you think about the EEPROM storage as an array of bits 3910 * being shifted into bytes, but that's not how we're looking 3911 * at it here... 3912 */ 3913 for (i = 0; i < 6 ;i++) 3914 enaddr[i] = bbr(enaddr[i]); 3915 } 3916 3917 /* 3918 * sip_mediastatus: [ifmedia interface function] 3919 * 3920 * Get the current interface media status. 3921 */ 3922 static void 3923 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3924 { 3925 struct sip_softc *sc = ifp->if_softc; 3926 3927 if (!device_is_active(sc->sc_dev)) { 3928 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3929 ifmr->ifm_status = 0; 3930 return; 3931 } 3932 ether_mediastatus(ifp, ifmr); 3933 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3934 sc->sc_flowflags; 3935 } 3936
Indexes created Tue Sep 30 11:09:46 GMT 2025