if_sip.c revision 1.154.2.2
1 /* $NetBSD: if_sip.c,v 1.154.2.2 2013/06/23 06:20:18 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.154.2.2 2013/06/23 06:20:18 tls Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rnd.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int); 587 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int); 591 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int); 595 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int); 622 void (*sipv_mii_writereg)(device_t, int, int, int); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA621 */ 741 { 0x1385, 0x621a }, 742 743 /* Netgear GA622 */ 744 { 0x1385, 0x622a }, 745 746 /* SMC EZ Card 1000 (9462TX) */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, cfdata_t cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 rnd_detach_source(&sc->rnd_source); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 918 919 /*FALLTHROUGH*/ 920 case SIP_ATTACH_CREATE_RXMAP: 921 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 922 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_rxsoft[i].rxs_dmamap); 925 } 926 /*FALLTHROUGH*/ 927 case SIP_ATTACH_CREATE_TXMAP: 928 for (i = 0; i < SIP_TXQUEUELEN; i++) { 929 if (sc->sc_txsoft[i].txs_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txsoft[i].txs_dmamap); 932 } 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_LOAD_MAP: 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_CREATE_MAP: 938 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_MAP_MEM: 941 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 942 sizeof(struct sip_control_data)); 943 /*FALLTHROUGH*/ 944 case SIP_ATTACH_ALLOC_MEM: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_INTR: 948 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_MAP: 951 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 952 break; 953 default: 954 break; 955 } 956 return; 957 } 958 959 static bool 960 sipcom_resume(device_t self, const pmf_qual_t *qual) 961 { 962 struct sip_softc *sc = device_private(self); 963 964 return sipcom_reset(sc); 965 } 966 967 static bool 968 sipcom_suspend(device_t self, const pmf_qual_t *qual) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 sipcom_rxdrain(sc); 973 return true; 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = device_private(self); 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t csr; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 998 callout_init(&sc->sc_tick_ch, 0); 999 1000 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1001 if (sip == NULL) { 1002 printf("\n"); 1003 panic("%s: impossible", __func__); 1004 } 1005 sc->sc_dev = self; 1006 sc->sc_gigabit = sip->sip_gigabit; 1007 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1008 sc->sc_pc = pc; 1009 1010 if (sc->sc_gigabit) { 1011 sc->sc_rxintr = gsip_rxintr; 1012 sc->sc_parm = &gsip_parm; 1013 } else { 1014 sc->sc_rxintr = sip_rxintr; 1015 sc->sc_parm = &sip_parm; 1016 } 1017 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1018 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1019 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1020 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1021 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1022 1023 sc->sc_rev = PCI_REVISION(pa->pa_class); 1024 1025 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1026 1027 sc->sc_model = sip; 1028 1029 /* 1030 * XXX Work-around broken PXE firmware on some boards. 1031 * 1032 * The DP83815 shares an address decoder with the MEM BAR 1033 * and the ROM BAR. Make sure the ROM BAR is disabled, 1034 * so that memory mapped access works. 1035 */ 1036 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1037 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1038 ~PCI_MAPREG_ROM_ENABLE); 1039 1040 /* 1041 * Map the device. 1042 */ 1043 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1044 PCI_MAPREG_TYPE_IO, 0, 1045 &iot, &ioh, NULL, &iosz) == 0); 1046 if (sc->sc_gigabit) { 1047 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1048 switch (memtype) { 1049 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1051 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1052 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1053 break; 1054 default: 1055 memh_valid = 0; 1056 } 1057 } else { 1058 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1059 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1060 &memt, &memh, NULL, &memsz) == 0); 1061 } 1062 1063 if (memh_valid) { 1064 sc->sc_st = memt; 1065 sc->sc_sh = memh; 1066 sc->sc_sz = memsz; 1067 } else if (ioh_valid) { 1068 sc->sc_st = iot; 1069 sc->sc_sh = ioh; 1070 sc->sc_sz = iosz; 1071 } else { 1072 printf("%s: unable to map device registers\n", 1073 device_xname(sc->sc_dev)); 1074 return; 1075 } 1076 1077 sc->sc_dmat = pa->pa_dmat; 1078 1079 /* 1080 * Make sure bus mastering is enabled. Also make sure 1081 * Write/Invalidate is enabled if we're allowed to use it. 1082 */ 1083 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1084 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1085 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1086 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1087 csr | PCI_COMMAND_MASTER_ENABLE); 1088 1089 /* power up chip */ 1090 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1091 if (error != 0 && error != EOPNOTSUPP) { 1092 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1093 return; 1094 } 1095 1096 /* 1097 * Map and establish our interrupt. 1098 */ 1099 if (pci_intr_map(pa, &ih)) { 1100 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1101 return; 1102 } 1103 intrstr = pci_intr_string(pc, ih); 1104 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1105 if (sc->sc_ih == NULL) { 1106 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1107 if (intrstr != NULL) 1108 aprint_error(" at %s", intrstr); 1109 aprint_error("\n"); 1110 sipcom_do_detach(self, SIP_ATTACH_MAP); 1111 return; 1112 } 1113 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1114 1115 SIMPLEQ_INIT(&sc->sc_txfreeq); 1116 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1117 1118 /* 1119 * Allocate the control data structures, and create and load the 1120 * DMA map for it. 1121 */ 1122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1123 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1124 &rseg, 0)) != 0) { 1125 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1126 error); 1127 sipcom_do_detach(self, SIP_ATTACH_INTR); 1128 return; 1129 } 1130 1131 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1132 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1133 BUS_DMA_COHERENT)) != 0) { 1134 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1135 error); 1136 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1137 } 1138 1139 if ((error = bus_dmamap_create(sc->sc_dmat, 1140 sizeof(struct sip_control_data), 1, 1141 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1142 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1143 "error = %d\n", error); 1144 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1145 } 1146 1147 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1148 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1149 0)) != 0) { 1150 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1151 error); 1152 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1153 } 1154 1155 /* 1156 * Create the transmit buffer DMA maps. 1157 */ 1158 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1159 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1160 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1161 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1162 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1163 "error = %d\n", i, error); 1164 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1165 } 1166 } 1167 1168 /* 1169 * Create the receive buffer DMA maps. 1170 */ 1171 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1172 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1173 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1174 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1175 "error = %d\n", i, error); 1176 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1177 } 1178 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1179 } 1180 1181 /* 1182 * Reset the chip to a known state. 1183 */ 1184 sipcom_reset(sc); 1185 1186 /* 1187 * Read the Ethernet address from the EEPROM. This might 1188 * also fetch other stuff from the EEPROM and stash it 1189 * in the softc. 1190 */ 1191 sc->sc_cfg = 0; 1192 if (!sc->sc_gigabit) { 1193 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1194 SIP_SIS900_REV(sc,SIS_REV_900B)) 1195 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1196 1197 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1198 SIP_SIS900_REV(sc,SIS_REV_960) || 1199 SIP_SIS900_REV(sc,SIS_REV_900B)) 1200 sc->sc_cfg |= 1201 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1202 CFG_EDBMASTEN); 1203 } 1204 1205 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1206 1207 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1208 ether_sprintf(enaddr)); 1209 1210 /* 1211 * Initialize the configuration register: aggressive PCI 1212 * bus request algorithm, default backoff, default OW timer, 1213 * default parity error detection. 1214 * 1215 * NOTE: "Big endian mode" is useless on the SiS900 and 1216 * friends -- it affects packet data, not descriptors. 1217 */ 1218 if (sc->sc_gigabit) 1219 sipcom_dp83820_attach(sc, pa); 1220 1221 /* 1222 * Initialize our media structures and probe the MII. 1223 */ 1224 sc->sc_mii.mii_ifp = ifp; 1225 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1226 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1227 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1228 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1229 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1244 } else 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 ether_ifattach(ifp, enaddr); 1287 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1288 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1289 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1290 sc->sc_prev.if_capenable = ifp->if_capenable; 1291 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1292 RND_TYPE_NET, 0); 1293 1294 /* 1295 * The number of bytes that must be available in 1296 * the Tx FIFO before the bus master can DMA more 1297 * data into the FIFO. 1298 */ 1299 sc->sc_tx_fill_thresh = 64 / 32; 1300 1301 /* 1302 * Start at a drain threshold of 512 bytes. We will 1303 * increase it if a DMA underrun occurs. 1304 * 1305 * XXX The minimum value of this variable should be 1306 * tuned. We may be able to improve performance 1307 * by starting with a lower value. That, however, 1308 * may trash the first few outgoing packets if the 1309 * PCI bus is saturated. 1310 */ 1311 if (sc->sc_gigabit) 1312 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1313 else 1314 sc->sc_tx_drain_thresh = 1504 / 32; 1315 1316 /* 1317 * Initialize the Rx FIFO drain threshold. 1318 * 1319 * This is in units of 8 bytes. 1320 * 1321 * We should never set this value lower than 2; 14 bytes are 1322 * required to filter the packet. 1323 */ 1324 sc->sc_rx_drain_thresh = 128 / 8; 1325 1326 #ifdef SIP_EVENT_COUNTERS 1327 /* 1328 * Attach event counters. 1329 */ 1330 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1331 NULL, device_xname(sc->sc_dev), "txsstall"); 1332 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(sc->sc_dev), "txdstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1335 NULL, device_xname(sc->sc_dev), "txforceintr"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txdintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "txiintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "rxintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "hiberr"); 1344 if (!sc->sc_gigabit) { 1345 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1346 NULL, device_xname(sc->sc_dev), "rxpause"); 1347 } else { 1348 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1349 NULL, device_xname(sc->sc_dev), "rxpause"); 1350 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "txpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "rxipsum"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "txipsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(sc->sc_dev), "txudpsum"); 1364 } 1365 #endif /* SIP_EVENT_COUNTERS */ 1366 1367 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1368 pmf_class_network_register(self, ifp); 1369 else 1370 aprint_error_dev(self, "couldn't establish power handler\n"); 1371 } 1372 1373 static inline void 1374 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1375 uint64_t capenable) 1376 { 1377 struct m_tag *mtag; 1378 u_int32_t extsts; 1379 #ifdef DEBUG 1380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1381 #endif 1382 /* 1383 * If VLANs are enabled and the packet has a VLAN tag, set 1384 * up the descriptor to encapsulate the packet for us. 1385 * 1386 * This apparently has to be on the last descriptor of 1387 * the packet. 1388 */ 1389 1390 /* 1391 * Byte swapping is tricky. We need to provide the tag 1392 * in a network byte order. On a big-endian machine, 1393 * the byteorder is correct, but we need to swap it 1394 * anyway, because this will be undone by the outside 1395 * htole32(). That's why there must be an 1396 * unconditional swap instead of htons() inside. 1397 */ 1398 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1399 sc->sc_txdescs[lasttx].sipd_extsts |= 1400 htole32(EXTSTS_VPKT | 1401 (bswap16(VLAN_TAG_VALUE(mtag)) & 1402 EXTSTS_VTCI)); 1403 } 1404 1405 /* 1406 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1407 * checksumming, set up the descriptor to do this work 1408 * for us. 1409 * 1410 * This apparently has to be on the first descriptor of 1411 * the packet. 1412 * 1413 * Byte-swap constants so the compiler can optimize. 1414 */ 1415 extsts = 0; 1416 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1417 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1418 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1419 extsts |= htole32(EXTSTS_IPPKT); 1420 } 1421 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1422 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1423 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1424 extsts |= htole32(EXTSTS_TCPPKT); 1425 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1426 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1427 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1428 extsts |= htole32(EXTSTS_UDPPKT); 1429 } 1430 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1431 } 1432 1433 /* 1434 * sip_start: [ifnet interface function] 1435 * 1436 * Start packet transmission on the interface. 1437 */ 1438 static void 1439 sipcom_start(struct ifnet *ifp) 1440 { 1441 struct sip_softc *sc = ifp->if_softc; 1442 struct mbuf *m0; 1443 struct mbuf *m; 1444 struct sip_txsoft *txs; 1445 bus_dmamap_t dmamap; 1446 int error, nexttx, lasttx, seg; 1447 int ofree = sc->sc_txfree; 1448 #if 0 1449 int firsttx = sc->sc_txnext; 1450 #endif 1451 1452 /* 1453 * If we've been told to pause, don't transmit any more packets. 1454 */ 1455 if (!sc->sc_gigabit && sc->sc_paused) 1456 ifp->if_flags |= IFF_OACTIVE; 1457 1458 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1459 return; 1460 1461 /* 1462 * Loop through the send queue, setting up transmit descriptors 1463 * until we drain the queue, or use up all available transmit 1464 * descriptors. 1465 */ 1466 for (;;) { 1467 /* Get a work queue entry. */ 1468 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1469 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1470 break; 1471 } 1472 1473 /* 1474 * Grab a packet off the queue. 1475 */ 1476 IFQ_POLL(&ifp->if_snd, m0); 1477 if (m0 == NULL) 1478 break; 1479 m = NULL; 1480 1481 dmamap = txs->txs_dmamap; 1482 1483 /* 1484 * Load the DMA map. If this fails, the packet either 1485 * didn't fit in the alloted number of segments, or we 1486 * were short on resources. 1487 */ 1488 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1489 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1490 /* In the non-gigabit case, we'll copy and try again. */ 1491 if (error != 0 && !sc->sc_gigabit) { 1492 MGETHDR(m, M_DONTWAIT, MT_DATA); 1493 if (m == NULL) { 1494 printf("%s: unable to allocate Tx mbuf\n", 1495 device_xname(sc->sc_dev)); 1496 break; 1497 } 1498 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1499 if (m0->m_pkthdr.len > MHLEN) { 1500 MCLGET(m, M_DONTWAIT); 1501 if ((m->m_flags & M_EXT) == 0) { 1502 printf("%s: unable to allocate Tx " 1503 "cluster\n", device_xname(sc->sc_dev)); 1504 m_freem(m); 1505 break; 1506 } 1507 } 1508 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1509 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1510 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1511 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1512 if (error) { 1513 printf("%s: unable to load Tx buffer, " 1514 "error = %d\n", device_xname(sc->sc_dev), error); 1515 break; 1516 } 1517 } else if (error == EFBIG) { 1518 /* 1519 * For the too-many-segments case, we simply 1520 * report an error and drop the packet, 1521 * since we can't sanely copy a jumbo packet 1522 * to a single buffer. 1523 */ 1524 printf("%s: Tx packet consumes too many " 1525 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1526 IFQ_DEQUEUE(&ifp->if_snd, m0); 1527 m_freem(m0); 1528 continue; 1529 } else if (error != 0) { 1530 /* 1531 * Short on resources, just stop for now. 1532 */ 1533 break; 1534 } 1535 1536 /* 1537 * Ensure we have enough descriptors free to describe 1538 * the packet. Note, we always reserve one descriptor 1539 * at the end of the ring as a termination point, to 1540 * prevent wrap-around. 1541 */ 1542 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1543 /* 1544 * Not enough free descriptors to transmit this 1545 * packet. We haven't committed anything yet, 1546 * so just unload the DMA map, put the packet 1547 * back on the queue, and punt. Notify the upper 1548 * layer that there are not more slots left. 1549 * 1550 * XXX We could allocate an mbuf and copy, but 1551 * XXX is it worth it? 1552 */ 1553 ifp->if_flags |= IFF_OACTIVE; 1554 bus_dmamap_unload(sc->sc_dmat, dmamap); 1555 if (m != NULL) 1556 m_freem(m); 1557 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1558 break; 1559 } 1560 1561 IFQ_DEQUEUE(&ifp->if_snd, m0); 1562 if (m != NULL) { 1563 m_freem(m0); 1564 m0 = m; 1565 } 1566 1567 /* 1568 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1569 */ 1570 1571 /* Sync the DMA map. */ 1572 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1573 BUS_DMASYNC_PREWRITE); 1574 1575 /* 1576 * Initialize the transmit descriptors. 1577 */ 1578 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1579 seg < dmamap->dm_nsegs; 1580 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1581 /* 1582 * If this is the first descriptor we're 1583 * enqueueing, don't set the OWN bit just 1584 * yet. That could cause a race condition. 1585 * We'll do it below. 1586 */ 1587 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1588 htole32(dmamap->dm_segs[seg].ds_addr); 1589 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1591 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1592 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1593 lasttx = nexttx; 1594 } 1595 1596 /* Clear the MORE bit on the last segment. */ 1597 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1598 htole32(~CMDSTS_MORE); 1599 1600 /* 1601 * If we're in the interrupt delay window, delay the 1602 * interrupt. 1603 */ 1604 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1605 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1606 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1607 htole32(CMDSTS_INTR); 1608 sc->sc_txwin = 0; 1609 } 1610 1611 if (sc->sc_gigabit) 1612 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1613 1614 /* Sync the descriptors we're using. */ 1615 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1616 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1617 1618 /* 1619 * The entire packet is set up. Give the first descrptor 1620 * to the chip now. 1621 */ 1622 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1623 htole32(CMDSTS_OWN); 1624 sip_cdtxsync(sc, sc->sc_txnext, 1, 1625 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1626 1627 /* 1628 * Store a pointer to the packet so we can free it later, 1629 * and remember what txdirty will be once the packet is 1630 * done. 1631 */ 1632 txs->txs_mbuf = m0; 1633 txs->txs_firstdesc = sc->sc_txnext; 1634 txs->txs_lastdesc = lasttx; 1635 1636 /* Advance the tx pointer. */ 1637 sc->sc_txfree -= dmamap->dm_nsegs; 1638 sc->sc_txnext = nexttx; 1639 1640 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1641 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1642 1643 /* 1644 * Pass the packet to any BPF listeners. 1645 */ 1646 bpf_mtap(ifp, m0); 1647 } 1648 1649 if (txs == NULL || sc->sc_txfree == 0) { 1650 /* No more slots left; notify upper layer. */ 1651 ifp->if_flags |= IFF_OACTIVE; 1652 } 1653 1654 if (sc->sc_txfree != ofree) { 1655 /* 1656 * Start the transmit process. Note, the manual says 1657 * that if there are no pending transmissions in the 1658 * chip's internal queue (indicated by TXE being clear), 1659 * then the driver software must set the TXDP to the 1660 * first descriptor to be transmitted. However, if we 1661 * do this, it causes serious performance degredation on 1662 * the DP83820 under load, not setting TXDP doesn't seem 1663 * to adversely affect the SiS 900 or DP83815. 1664 * 1665 * Well, I guess it wouldn't be the first time a manual 1666 * has lied -- and they could be speaking of the NULL- 1667 * terminated descriptor list case, rather than OWN- 1668 * terminated rings. 1669 */ 1670 #if 0 1671 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1672 CR_TXE) == 0) { 1673 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1674 SIP_CDTXADDR(sc, firsttx)); 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1676 } 1677 #else 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1679 #endif 1680 1681 /* Set a watchdog timer in case the chip flakes out. */ 1682 /* Gigabit autonegotiation takes 5 seconds. */ 1683 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1684 } 1685 } 1686 1687 /* 1688 * sip_watchdog: [ifnet interface function] 1689 * 1690 * Watchdog timer handler. 1691 */ 1692 static void 1693 sipcom_watchdog(struct ifnet *ifp) 1694 { 1695 struct sip_softc *sc = ifp->if_softc; 1696 1697 /* 1698 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1699 * If we get a timeout, try and sweep up transmit descriptors. 1700 * If we manage to sweep them all up, ignore the lack of 1701 * interrupt. 1702 */ 1703 sipcom_txintr(sc); 1704 1705 if (sc->sc_txfree != sc->sc_ntxdesc) { 1706 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1707 ifp->if_oerrors++; 1708 1709 /* Reset the interface. */ 1710 (void) sipcom_init(ifp); 1711 } else if (ifp->if_flags & IFF_DEBUG) 1712 printf("%s: recovered from device timeout\n", 1713 device_xname(sc->sc_dev)); 1714 1715 /* Try to get more packets going. */ 1716 sipcom_start(ifp); 1717 } 1718 1719 /* If the interface is up and running, only modify the receive 1720 * filter when setting promiscuous or debug mode. Otherwise fall 1721 * through to ether_ioctl, which will reset the chip. 1722 */ 1723 static int 1724 sip_ifflags_cb(struct ethercom *ec) 1725 { 1726 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1727 == (sc)->sc_ethercom.ec_capenable) \ 1728 && ((sc)->sc_prev.is_vlan == \ 1729 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1730 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1731 struct ifnet *ifp = &ec->ec_if; 1732 struct sip_softc *sc = ifp->if_softc; 1733 int change = ifp->if_flags ^ sc->sc_if_flags; 1734 1735 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1736 !COMPARE_IC(sc, ifp)) 1737 return ENETRESET; 1738 /* Set up the receive filter. */ 1739 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1740 return 0; 1741 } 1742 1743 /* 1744 * sip_ioctl: [ifnet interface function] 1745 * 1746 * Handle control requests from the operator. 1747 */ 1748 static int 1749 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1750 { 1751 struct sip_softc *sc = ifp->if_softc; 1752 struct ifreq *ifr = (struct ifreq *)data; 1753 int s, error; 1754 1755 s = splnet(); 1756 1757 switch (cmd) { 1758 case SIOCSIFMEDIA: 1759 /* Flow control requires full-duplex mode. */ 1760 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1761 (ifr->ifr_media & IFM_FDX) == 0) 1762 ifr->ifr_media &= ~IFM_ETH_FMASK; 1763 1764 /* XXX */ 1765 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1766 ifr->ifr_media &= ~IFM_ETH_FMASK; 1767 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1768 if (sc->sc_gigabit && 1769 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1770 /* We can do both TXPAUSE and RXPAUSE. */ 1771 ifr->ifr_media |= 1772 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1773 } else if (ifr->ifr_media & IFM_FLOW) { 1774 /* 1775 * Both TXPAUSE and RXPAUSE must be set. 1776 * (SiS900 and DP83815 don't have PAUSE_ASYM 1777 * feature.) 1778 * 1779 * XXX Can SiS900 and DP83815 send PAUSE? 1780 */ 1781 ifr->ifr_media |= 1782 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1783 } 1784 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1785 } 1786 /*FALLTHROUGH*/ 1787 default: 1788 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1789 break; 1790 1791 error = 0; 1792 1793 if (cmd == SIOCSIFCAP) 1794 error = (*ifp->if_init)(ifp); 1795 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1796 ; 1797 else if (ifp->if_flags & IFF_RUNNING) { 1798 /* 1799 * Multicast list has changed; set the hardware filter 1800 * accordingly. 1801 */ 1802 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1803 } 1804 break; 1805 } 1806 1807 /* Try to get more packets going. */ 1808 sipcom_start(ifp); 1809 1810 sc->sc_if_flags = ifp->if_flags; 1811 splx(s); 1812 return (error); 1813 } 1814 1815 /* 1816 * sip_intr: 1817 * 1818 * Interrupt service routine. 1819 */ 1820 static int 1821 sipcom_intr(void *arg) 1822 { 1823 struct sip_softc *sc = arg; 1824 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1825 u_int32_t isr; 1826 int handled = 0; 1827 1828 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1829 return 0; 1830 1831 /* Disable interrupts. */ 1832 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1833 1834 for (;;) { 1835 /* Reading clears interrupt. */ 1836 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1837 if ((isr & sc->sc_imr) == 0) 1838 break; 1839 1840 rnd_add_uint32(&sc->rnd_source, isr); 1841 1842 handled = 1; 1843 1844 if ((ifp->if_flags & IFF_RUNNING) == 0) 1845 break; 1846 1847 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1848 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1849 1850 /* Grab any new packets. */ 1851 (*sc->sc_rxintr)(sc); 1852 1853 if (isr & ISR_RXORN) { 1854 printf("%s: receive FIFO overrun\n", 1855 device_xname(sc->sc_dev)); 1856 1857 /* XXX adjust rx_drain_thresh? */ 1858 } 1859 1860 if (isr & ISR_RXIDLE) { 1861 printf("%s: receive ring overrun\n", 1862 device_xname(sc->sc_dev)); 1863 1864 /* Get the receive process going again. */ 1865 bus_space_write_4(sc->sc_st, sc->sc_sh, 1866 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1867 bus_space_write_4(sc->sc_st, sc->sc_sh, 1868 SIP_CR, CR_RXE); 1869 } 1870 } 1871 1872 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1873 #ifdef SIP_EVENT_COUNTERS 1874 if (isr & ISR_TXDESC) 1875 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1876 else if (isr & ISR_TXIDLE) 1877 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1878 #endif 1879 1880 /* Sweep up transmit descriptors. */ 1881 sipcom_txintr(sc); 1882 1883 if (isr & ISR_TXURN) { 1884 u_int32_t thresh; 1885 int txfifo_size = (sc->sc_gigabit) 1886 ? DP83820_SIP_TXFIFO_SIZE 1887 : OTHER_SIP_TXFIFO_SIZE; 1888 1889 printf("%s: transmit FIFO underrun", 1890 device_xname(sc->sc_dev)); 1891 thresh = sc->sc_tx_drain_thresh + 1; 1892 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1893 && (thresh * 32) <= (txfifo_size - 1894 (sc->sc_tx_fill_thresh * 32))) { 1895 printf("; increasing Tx drain " 1896 "threshold to %u bytes\n", 1897 thresh * 32); 1898 sc->sc_tx_drain_thresh = thresh; 1899 (void) sipcom_init(ifp); 1900 } else { 1901 (void) sipcom_init(ifp); 1902 printf("\n"); 1903 } 1904 } 1905 } 1906 1907 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1908 if (isr & ISR_PAUSE_ST) { 1909 sc->sc_paused = 1; 1910 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1911 ifp->if_flags |= IFF_OACTIVE; 1912 } 1913 if (isr & ISR_PAUSE_END) { 1914 sc->sc_paused = 0; 1915 ifp->if_flags &= ~IFF_OACTIVE; 1916 } 1917 } 1918 1919 if (isr & ISR_HIBERR) { 1920 int want_init = 0; 1921 1922 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1923 1924 #define PRINTERR(bit, str) \ 1925 do { \ 1926 if ((isr & (bit)) != 0) { \ 1927 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1928 printf("%s: %s\n", \ 1929 device_xname(sc->sc_dev), str); \ 1930 want_init = 1; \ 1931 } \ 1932 } while (/*CONSTCOND*/0) 1933 1934 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1935 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1936 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1937 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1938 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1939 /* 1940 * Ignore: 1941 * Tx reset complete 1942 * Rx reset complete 1943 */ 1944 if (want_init) 1945 (void) sipcom_init(ifp); 1946 #undef PRINTERR 1947 } 1948 } 1949 1950 /* Re-enable interrupts. */ 1951 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1952 1953 /* Try to get more packets going. */ 1954 sipcom_start(ifp); 1955 1956 return (handled); 1957 } 1958 1959 /* 1960 * sip_txintr: 1961 * 1962 * Helper; handle transmit interrupts. 1963 */ 1964 static void 1965 sipcom_txintr(struct sip_softc *sc) 1966 { 1967 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1968 struct sip_txsoft *txs; 1969 u_int32_t cmdsts; 1970 1971 if (sc->sc_paused == 0) 1972 ifp->if_flags &= ~IFF_OACTIVE; 1973 1974 /* 1975 * Go through our Tx list and free mbufs for those 1976 * frames which have been transmitted. 1977 */ 1978 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1979 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1980 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1981 1982 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1983 if (cmdsts & CMDSTS_OWN) 1984 break; 1985 1986 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1987 1988 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1989 1990 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1991 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1992 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1993 m_freem(txs->txs_mbuf); 1994 txs->txs_mbuf = NULL; 1995 1996 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1997 1998 /* 1999 * Check for errors and collisions. 2000 */ 2001 if (cmdsts & 2002 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2003 ifp->if_oerrors++; 2004 if (cmdsts & CMDSTS_Tx_EC) 2005 ifp->if_collisions += 16; 2006 if (ifp->if_flags & IFF_DEBUG) { 2007 if (cmdsts & CMDSTS_Tx_ED) 2008 printf("%s: excessive deferral\n", 2009 device_xname(sc->sc_dev)); 2010 if (cmdsts & CMDSTS_Tx_EC) 2011 printf("%s: excessive collisions\n", 2012 device_xname(sc->sc_dev)); 2013 } 2014 } else { 2015 /* Packet was transmitted successfully. */ 2016 ifp->if_opackets++; 2017 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2018 } 2019 } 2020 2021 /* 2022 * If there are no more pending transmissions, cancel the watchdog 2023 * timer. 2024 */ 2025 if (txs == NULL) { 2026 ifp->if_timer = 0; 2027 sc->sc_txwin = 0; 2028 } 2029 } 2030 2031 /* 2032 * gsip_rxintr: 2033 * 2034 * Helper; handle receive interrupts on gigabit parts. 2035 */ 2036 static void 2037 gsip_rxintr(struct sip_softc *sc) 2038 { 2039 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2040 struct sip_rxsoft *rxs; 2041 struct mbuf *m; 2042 u_int32_t cmdsts, extsts; 2043 int i, len; 2044 2045 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2046 rxs = &sc->sc_rxsoft[i]; 2047 2048 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2049 2050 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2051 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2052 len = CMDSTS_SIZE(sc, cmdsts); 2053 2054 /* 2055 * NOTE: OWN is set if owned by _consumer_. We're the 2056 * consumer of the receive ring, so if the bit is clear, 2057 * we have processed all of the packets. 2058 */ 2059 if ((cmdsts & CMDSTS_OWN) == 0) { 2060 /* 2061 * We have processed all of the receive buffers. 2062 */ 2063 break; 2064 } 2065 2066 if (__predict_false(sc->sc_rxdiscard)) { 2067 sip_init_rxdesc(sc, i); 2068 if ((cmdsts & CMDSTS_MORE) == 0) { 2069 /* Reset our state. */ 2070 sc->sc_rxdiscard = 0; 2071 } 2072 continue; 2073 } 2074 2075 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2076 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2077 2078 m = rxs->rxs_mbuf; 2079 2080 /* 2081 * Add a new receive buffer to the ring. 2082 */ 2083 if (sipcom_add_rxbuf(sc, i) != 0) { 2084 /* 2085 * Failed, throw away what we've done so 2086 * far, and discard the rest of the packet. 2087 */ 2088 ifp->if_ierrors++; 2089 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2090 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2091 sip_init_rxdesc(sc, i); 2092 if (cmdsts & CMDSTS_MORE) 2093 sc->sc_rxdiscard = 1; 2094 if (sc->sc_rxhead != NULL) 2095 m_freem(sc->sc_rxhead); 2096 sip_rxchain_reset(sc); 2097 continue; 2098 } 2099 2100 sip_rxchain_link(sc, m); 2101 2102 m->m_len = len; 2103 2104 /* 2105 * If this is not the end of the packet, keep 2106 * looking. 2107 */ 2108 if (cmdsts & CMDSTS_MORE) { 2109 sc->sc_rxlen += len; 2110 continue; 2111 } 2112 2113 /* 2114 * Okay, we have the entire packet now. The chip includes 2115 * the FCS, so we need to trim it. 2116 */ 2117 m->m_len -= ETHER_CRC_LEN; 2118 2119 *sc->sc_rxtailp = NULL; 2120 len = m->m_len + sc->sc_rxlen; 2121 m = sc->sc_rxhead; 2122 2123 sip_rxchain_reset(sc); 2124 2125 /* 2126 * If an error occurred, update stats and drop the packet. 2127 */ 2128 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2129 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2130 ifp->if_ierrors++; 2131 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2132 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2133 /* Receive overrun handled elsewhere. */ 2134 printf("%s: receive descriptor error\n", 2135 device_xname(sc->sc_dev)); 2136 } 2137 #define PRINTERR(bit, str) \ 2138 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2139 (cmdsts & (bit)) != 0) \ 2140 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2141 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2142 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2143 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2144 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2145 #undef PRINTERR 2146 m_freem(m); 2147 continue; 2148 } 2149 2150 /* 2151 * If the packet is small enough to fit in a 2152 * single header mbuf, allocate one and copy 2153 * the data into it. This greatly reduces 2154 * memory consumption when we receive lots 2155 * of small packets. 2156 */ 2157 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2158 struct mbuf *nm; 2159 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2160 if (nm == NULL) { 2161 ifp->if_ierrors++; 2162 m_freem(m); 2163 continue; 2164 } 2165 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2166 nm->m_data += 2; 2167 nm->m_pkthdr.len = nm->m_len = len; 2168 m_copydata(m, 0, len, mtod(nm, void *)); 2169 m_freem(m); 2170 m = nm; 2171 } 2172 #ifndef __NO_STRICT_ALIGNMENT 2173 else { 2174 /* 2175 * The DP83820's receive buffers must be 4-byte 2176 * aligned. But this means that the data after 2177 * the Ethernet header is misaligned. To compensate, 2178 * we have artificially shortened the buffer size 2179 * in the descriptor, and we do an overlapping copy 2180 * of the data two bytes further in (in the first 2181 * buffer of the chain only). 2182 */ 2183 memmove(mtod(m, char *) + 2, mtod(m, void *), 2184 m->m_len); 2185 m->m_data += 2; 2186 } 2187 #endif /* ! __NO_STRICT_ALIGNMENT */ 2188 2189 /* 2190 * If VLANs are enabled, VLAN packets have been unwrapped 2191 * for us. Associate the tag with the packet. 2192 */ 2193 2194 /* 2195 * Again, byte swapping is tricky. Hardware provided 2196 * the tag in the network byte order, but extsts was 2197 * passed through le32toh() in the meantime. On a 2198 * big-endian machine, we need to swap it again. On a 2199 * little-endian machine, we need to convert from the 2200 * network to host byte order. This means that we must 2201 * swap it in any case, so unconditional swap instead 2202 * of htons() is used. 2203 */ 2204 if ((extsts & EXTSTS_VPKT) != 0) { 2205 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2206 continue); 2207 } 2208 2209 /* 2210 * Set the incoming checksum information for the 2211 * packet. 2212 */ 2213 if ((extsts & EXTSTS_IPPKT) != 0) { 2214 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2215 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2216 if (extsts & EXTSTS_Rx_IPERR) 2217 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2218 if (extsts & EXTSTS_TCPPKT) { 2219 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2220 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2221 if (extsts & EXTSTS_Rx_TCPERR) 2222 m->m_pkthdr.csum_flags |= 2223 M_CSUM_TCP_UDP_BAD; 2224 } else if (extsts & EXTSTS_UDPPKT) { 2225 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2226 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2227 if (extsts & EXTSTS_Rx_UDPERR) 2228 m->m_pkthdr.csum_flags |= 2229 M_CSUM_TCP_UDP_BAD; 2230 } 2231 } 2232 2233 ifp->if_ipackets++; 2234 m->m_pkthdr.rcvif = ifp; 2235 m->m_pkthdr.len = len; 2236 2237 /* 2238 * Pass this up to any BPF listeners, but only 2239 * pass if up the stack if it's for us. 2240 */ 2241 bpf_mtap(ifp, m); 2242 2243 /* Pass it on. */ 2244 (*ifp->if_input)(ifp, m); 2245 } 2246 2247 /* Update the receive pointer. */ 2248 sc->sc_rxptr = i; 2249 } 2250 2251 /* 2252 * sip_rxintr: 2253 * 2254 * Helper; handle receive interrupts on 10/100 parts. 2255 */ 2256 static void 2257 sip_rxintr(struct sip_softc *sc) 2258 { 2259 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2260 struct sip_rxsoft *rxs; 2261 struct mbuf *m; 2262 u_int32_t cmdsts; 2263 int i, len; 2264 2265 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2266 rxs = &sc->sc_rxsoft[i]; 2267 2268 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2269 2270 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2271 2272 /* 2273 * NOTE: OWN is set if owned by _consumer_. We're the 2274 * consumer of the receive ring, so if the bit is clear, 2275 * we have processed all of the packets. 2276 */ 2277 if ((cmdsts & CMDSTS_OWN) == 0) { 2278 /* 2279 * We have processed all of the receive buffers. 2280 */ 2281 break; 2282 } 2283 2284 /* 2285 * If any collisions were seen on the wire, count one. 2286 */ 2287 if (cmdsts & CMDSTS_Rx_COL) 2288 ifp->if_collisions++; 2289 2290 /* 2291 * If an error occurred, update stats, clear the status 2292 * word, and leave the packet buffer in place. It will 2293 * simply be reused the next time the ring comes around. 2294 */ 2295 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2296 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2297 ifp->if_ierrors++; 2298 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2299 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2300 /* Receive overrun handled elsewhere. */ 2301 printf("%s: receive descriptor error\n", 2302 device_xname(sc->sc_dev)); 2303 } 2304 #define PRINTERR(bit, str) \ 2305 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2306 (cmdsts & (bit)) != 0) \ 2307 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2308 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2309 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2310 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2311 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2312 #undef PRINTERR 2313 sip_init_rxdesc(sc, i); 2314 continue; 2315 } 2316 2317 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2318 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2319 2320 /* 2321 * No errors; receive the packet. Note, the SiS 900 2322 * includes the CRC with every packet. 2323 */ 2324 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2325 2326 #ifdef __NO_STRICT_ALIGNMENT 2327 /* 2328 * If the packet is small enough to fit in a 2329 * single header mbuf, allocate one and copy 2330 * the data into it. This greatly reduces 2331 * memory consumption when we receive lots 2332 * of small packets. 2333 * 2334 * Otherwise, we add a new buffer to the receive 2335 * chain. If this fails, we drop the packet and 2336 * recycle the old buffer. 2337 */ 2338 if (sip_copy_small != 0 && len <= MHLEN) { 2339 MGETHDR(m, M_DONTWAIT, MT_DATA); 2340 if (m == NULL) 2341 goto dropit; 2342 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2343 memcpy(mtod(m, void *), 2344 mtod(rxs->rxs_mbuf, void *), len); 2345 sip_init_rxdesc(sc, i); 2346 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2347 rxs->rxs_dmamap->dm_mapsize, 2348 BUS_DMASYNC_PREREAD); 2349 } else { 2350 m = rxs->rxs_mbuf; 2351 if (sipcom_add_rxbuf(sc, i) != 0) { 2352 dropit: 2353 ifp->if_ierrors++; 2354 sip_init_rxdesc(sc, i); 2355 bus_dmamap_sync(sc->sc_dmat, 2356 rxs->rxs_dmamap, 0, 2357 rxs->rxs_dmamap->dm_mapsize, 2358 BUS_DMASYNC_PREREAD); 2359 continue; 2360 } 2361 } 2362 #else 2363 /* 2364 * The SiS 900's receive buffers must be 4-byte aligned. 2365 * But this means that the data after the Ethernet header 2366 * is misaligned. We must allocate a new buffer and 2367 * copy the data, shifted forward 2 bytes. 2368 */ 2369 MGETHDR(m, M_DONTWAIT, MT_DATA); 2370 if (m == NULL) { 2371 dropit: 2372 ifp->if_ierrors++; 2373 sip_init_rxdesc(sc, i); 2374 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2375 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2376 continue; 2377 } 2378 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2379 if (len > (MHLEN - 2)) { 2380 MCLGET(m, M_DONTWAIT); 2381 if ((m->m_flags & M_EXT) == 0) { 2382 m_freem(m); 2383 goto dropit; 2384 } 2385 } 2386 m->m_data += 2; 2387 2388 /* 2389 * Note that we use clusters for incoming frames, so the 2390 * buffer is virtually contiguous. 2391 */ 2392 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2393 2394 /* Allow the receive descriptor to continue using its mbuf. */ 2395 sip_init_rxdesc(sc, i); 2396 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2397 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2398 #endif /* __NO_STRICT_ALIGNMENT */ 2399 2400 ifp->if_ipackets++; 2401 m->m_pkthdr.rcvif = ifp; 2402 m->m_pkthdr.len = m->m_len = len; 2403 2404 /* 2405 * Pass this up to any BPF listeners, but only 2406 * pass if up the stack if it's for us. 2407 */ 2408 bpf_mtap(ifp, m); 2409 2410 /* Pass it on. */ 2411 (*ifp->if_input)(ifp, m); 2412 } 2413 2414 /* Update the receive pointer. */ 2415 sc->sc_rxptr = i; 2416 } 2417 2418 /* 2419 * sip_tick: 2420 * 2421 * One second timer, used to tick the MII. 2422 */ 2423 static void 2424 sipcom_tick(void *arg) 2425 { 2426 struct sip_softc *sc = arg; 2427 int s; 2428 2429 s = splnet(); 2430 #ifdef SIP_EVENT_COUNTERS 2431 if (sc->sc_gigabit) { 2432 /* Read PAUSE related counts from MIB registers. */ 2433 sc->sc_ev_rxpause.ev_count += 2434 bus_space_read_4(sc->sc_st, sc->sc_sh, 2435 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2436 sc->sc_ev_txpause.ev_count += 2437 bus_space_read_4(sc->sc_st, sc->sc_sh, 2438 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2439 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2440 } 2441 #endif /* SIP_EVENT_COUNTERS */ 2442 mii_tick(&sc->sc_mii); 2443 splx(s); 2444 2445 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2446 } 2447 2448 /* 2449 * sip_reset: 2450 * 2451 * Perform a soft reset on the SiS 900. 2452 */ 2453 static bool 2454 sipcom_reset(struct sip_softc *sc) 2455 { 2456 bus_space_tag_t st = sc->sc_st; 2457 bus_space_handle_t sh = sc->sc_sh; 2458 int i; 2459 2460 bus_space_write_4(st, sh, SIP_IER, 0); 2461 bus_space_write_4(st, sh, SIP_IMR, 0); 2462 bus_space_write_4(st, sh, SIP_RFCR, 0); 2463 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2464 2465 for (i = 0; i < SIP_TIMEOUT; i++) { 2466 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2467 break; 2468 delay(2); 2469 } 2470 2471 if (i == SIP_TIMEOUT) { 2472 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2473 return false; 2474 } 2475 2476 delay(1000); 2477 2478 if (sc->sc_gigabit) { 2479 /* 2480 * Set the general purpose I/O bits. Do it here in case we 2481 * need to have GPIO set up to talk to the media interface. 2482 */ 2483 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2484 delay(1000); 2485 } 2486 return true; 2487 } 2488 2489 static void 2490 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2491 { 2492 u_int32_t reg; 2493 bus_space_tag_t st = sc->sc_st; 2494 bus_space_handle_t sh = sc->sc_sh; 2495 /* 2496 * Initialize the VLAN/IP receive control register. 2497 * We enable checksum computation on all incoming 2498 * packets, and do not reject packets w/ bad checksums. 2499 */ 2500 reg = 0; 2501 if (capenable & 2502 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2503 reg |= VRCR_IPEN; 2504 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2505 reg |= VRCR_VTDEN|VRCR_VTREN; 2506 bus_space_write_4(st, sh, SIP_VRCR, reg); 2507 2508 /* 2509 * Initialize the VLAN/IP transmit control register. 2510 * We enable outgoing checksum computation on a 2511 * per-packet basis. 2512 */ 2513 reg = 0; 2514 if (capenable & 2515 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2516 reg |= VTCR_PPCHK; 2517 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2518 reg |= VTCR_VPPTI; 2519 bus_space_write_4(st, sh, SIP_VTCR, reg); 2520 2521 /* 2522 * If we're using VLANs, initialize the VLAN data register. 2523 * To understand why we bswap the VLAN Ethertype, see section 2524 * 4.2.36 of the DP83820 manual. 2525 */ 2526 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2527 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2528 } 2529 2530 /* 2531 * sip_init: [ ifnet interface function ] 2532 * 2533 * Initialize the interface. Must be called at splnet(). 2534 */ 2535 static int 2536 sipcom_init(struct ifnet *ifp) 2537 { 2538 struct sip_softc *sc = ifp->if_softc; 2539 bus_space_tag_t st = sc->sc_st; 2540 bus_space_handle_t sh = sc->sc_sh; 2541 struct sip_txsoft *txs; 2542 struct sip_rxsoft *rxs; 2543 struct sip_desc *sipd; 2544 int i, error = 0; 2545 2546 if (device_is_active(sc->sc_dev)) { 2547 /* 2548 * Cancel any pending I/O. 2549 */ 2550 sipcom_stop(ifp, 0); 2551 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2552 !device_is_active(sc->sc_dev)) 2553 return 0; 2554 2555 /* 2556 * Reset the chip to a known state. 2557 */ 2558 if (!sipcom_reset(sc)) 2559 return EBUSY; 2560 2561 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2562 /* 2563 * DP83815 manual, page 78: 2564 * 4.4 Recommended Registers Configuration 2565 * For optimum performance of the DP83815, version noted 2566 * as DP83815CVNG (SRR = 203h), the listed register 2567 * modifications must be followed in sequence... 2568 * 2569 * It's not clear if this should be 302h or 203h because that 2570 * chip name is listed as SRR 302h in the description of the 2571 * SRR register. However, my revision 302h DP83815 on the 2572 * Netgear FA311 purchased in 02/2001 needs these settings 2573 * to avoid tons of errors in AcceptPerfectMatch (non- 2574 * IFF_PROMISC) mode. I do not know if other revisions need 2575 * this set or not. [briggs -- 09 March 2001] 2576 * 2577 * Note that only the low-order 12 bits of 0xe4 are documented 2578 * and that this sets reserved bits in that register. 2579 */ 2580 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2581 2582 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2583 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2584 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2585 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2586 2587 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2588 } 2589 2590 /* 2591 * Initialize the transmit descriptor ring. 2592 */ 2593 for (i = 0; i < sc->sc_ntxdesc; i++) { 2594 sipd = &sc->sc_txdescs[i]; 2595 memset(sipd, 0, sizeof(struct sip_desc)); 2596 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2597 } 2598 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2599 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2600 sc->sc_txfree = sc->sc_ntxdesc; 2601 sc->sc_txnext = 0; 2602 sc->sc_txwin = 0; 2603 2604 /* 2605 * Initialize the transmit job descriptors. 2606 */ 2607 SIMPLEQ_INIT(&sc->sc_txfreeq); 2608 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2609 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2610 txs = &sc->sc_txsoft[i]; 2611 txs->txs_mbuf = NULL; 2612 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2613 } 2614 2615 /* 2616 * Initialize the receive descriptor and receive job 2617 * descriptor rings. 2618 */ 2619 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2620 rxs = &sc->sc_rxsoft[i]; 2621 if (rxs->rxs_mbuf == NULL) { 2622 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2623 printf("%s: unable to allocate or map rx " 2624 "buffer %d, error = %d\n", 2625 device_xname(sc->sc_dev), i, error); 2626 /* 2627 * XXX Should attempt to run with fewer receive 2628 * XXX buffers instead of just failing. 2629 */ 2630 sipcom_rxdrain(sc); 2631 goto out; 2632 } 2633 } else 2634 sip_init_rxdesc(sc, i); 2635 } 2636 sc->sc_rxptr = 0; 2637 sc->sc_rxdiscard = 0; 2638 sip_rxchain_reset(sc); 2639 2640 /* 2641 * Set the configuration register; it's already initialized 2642 * in sip_attach(). 2643 */ 2644 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2645 2646 /* 2647 * Initialize the prototype TXCFG register. 2648 */ 2649 if (sc->sc_gigabit) { 2650 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2651 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2652 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2653 SIP_SIS900_REV(sc, SIS_REV_960) || 2654 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2655 (sc->sc_cfg & CFG_EDBMASTEN)) { 2656 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2657 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2658 } else { 2659 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2660 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2661 } 2662 2663 sc->sc_txcfg |= TXCFG_ATP | 2664 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2665 sc->sc_tx_drain_thresh; 2666 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2667 2668 /* 2669 * Initialize the receive drain threshold if we have never 2670 * done so. 2671 */ 2672 if (sc->sc_rx_drain_thresh == 0) { 2673 /* 2674 * XXX This value should be tuned. This is set to the 2675 * maximum of 248 bytes, and we may be able to improve 2676 * performance by decreasing it (although we should never 2677 * set this value lower than 2; 14 bytes are required to 2678 * filter the packet). 2679 */ 2680 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2681 } 2682 2683 /* 2684 * Initialize the prototype RXCFG register. 2685 */ 2686 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2687 /* 2688 * Accept long packets (including FCS) so we can handle 2689 * 802.1q-tagged frames and jumbo frames properly. 2690 */ 2691 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2692 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2693 sc->sc_rxcfg |= RXCFG_ALP; 2694 2695 /* 2696 * Checksum offloading is disabled if the user selects an MTU 2697 * larger than 8109. (FreeBSD says 8152, but there is emperical 2698 * evidence that >8109 does not work on some boards, such as the 2699 * Planex GN-1000TE). 2700 */ 2701 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2702 (ifp->if_capenable & 2703 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2704 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2705 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2706 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2707 "disabled.\n", device_xname(sc->sc_dev)); 2708 ifp->if_capenable &= 2709 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2710 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2711 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2712 ifp->if_csum_flags_tx = 0; 2713 ifp->if_csum_flags_rx = 0; 2714 } 2715 2716 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2717 2718 if (sc->sc_gigabit) 2719 sipcom_dp83820_init(sc, ifp->if_capenable); 2720 2721 /* 2722 * Give the transmit and receive rings to the chip. 2723 */ 2724 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2725 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2726 2727 /* 2728 * Initialize the interrupt mask. 2729 */ 2730 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2731 sc->sc_bits.b_isr_sserr | 2732 sc->sc_bits.b_isr_rmabt | 2733 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2734 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2735 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2736 2737 /* Set up the receive filter. */ 2738 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2739 2740 /* 2741 * Tune sc_rx_flow_thresh. 2742 * XXX "More than 8KB" is too short for jumbo frames. 2743 * XXX TODO: Threshold value should be user-settable. 2744 */ 2745 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2746 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2747 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2748 2749 /* 2750 * Set the current media. Do this after initializing the prototype 2751 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2752 * control. 2753 */ 2754 if ((error = ether_mediachange(ifp)) != 0) 2755 goto out; 2756 2757 /* 2758 * Set the interrupt hold-off timer to 100us. 2759 */ 2760 if (sc->sc_gigabit) 2761 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2762 2763 /* 2764 * Enable interrupts. 2765 */ 2766 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2767 2768 /* 2769 * Start the transmit and receive processes. 2770 */ 2771 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2772 2773 /* 2774 * Start the one second MII clock. 2775 */ 2776 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2777 2778 /* 2779 * ...all done! 2780 */ 2781 ifp->if_flags |= IFF_RUNNING; 2782 ifp->if_flags &= ~IFF_OACTIVE; 2783 sc->sc_if_flags = ifp->if_flags; 2784 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2785 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2786 sc->sc_prev.if_capenable = ifp->if_capenable; 2787 2788 out: 2789 if (error) 2790 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2791 return (error); 2792 } 2793 2794 /* 2795 * sip_drain: 2796 * 2797 * Drain the receive queue. 2798 */ 2799 static void 2800 sipcom_rxdrain(struct sip_softc *sc) 2801 { 2802 struct sip_rxsoft *rxs; 2803 int i; 2804 2805 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2806 rxs = &sc->sc_rxsoft[i]; 2807 if (rxs->rxs_mbuf != NULL) { 2808 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2809 m_freem(rxs->rxs_mbuf); 2810 rxs->rxs_mbuf = NULL; 2811 } 2812 } 2813 } 2814 2815 /* 2816 * sip_stop: [ ifnet interface function ] 2817 * 2818 * Stop transmission on the interface. 2819 */ 2820 static void 2821 sipcom_stop(struct ifnet *ifp, int disable) 2822 { 2823 struct sip_softc *sc = ifp->if_softc; 2824 bus_space_tag_t st = sc->sc_st; 2825 bus_space_handle_t sh = sc->sc_sh; 2826 struct sip_txsoft *txs; 2827 u_int32_t cmdsts = 0; /* DEBUG */ 2828 2829 /* 2830 * Stop the one second clock. 2831 */ 2832 callout_stop(&sc->sc_tick_ch); 2833 2834 /* Down the MII. */ 2835 mii_down(&sc->sc_mii); 2836 2837 if (device_is_active(sc->sc_dev)) { 2838 /* 2839 * Disable interrupts. 2840 */ 2841 bus_space_write_4(st, sh, SIP_IER, 0); 2842 2843 /* 2844 * Stop receiver and transmitter. 2845 */ 2846 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2847 } 2848 2849 /* 2850 * Release any queued transmit buffers. 2851 */ 2852 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2853 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2854 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2855 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2856 CMDSTS_INTR) == 0) 2857 printf("%s: sip_stop: last descriptor does not " 2858 "have INTR bit set\n", device_xname(sc->sc_dev)); 2859 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2860 #ifdef DIAGNOSTIC 2861 if (txs->txs_mbuf == NULL) { 2862 printf("%s: dirty txsoft with no mbuf chain\n", 2863 device_xname(sc->sc_dev)); 2864 panic("sip_stop"); 2865 } 2866 #endif 2867 cmdsts |= /* DEBUG */ 2868 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2869 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2870 m_freem(txs->txs_mbuf); 2871 txs->txs_mbuf = NULL; 2872 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2873 } 2874 2875 /* 2876 * Mark the interface down and cancel the watchdog timer. 2877 */ 2878 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2879 ifp->if_timer = 0; 2880 2881 if (disable) 2882 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2883 2884 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2885 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2886 printf("%s: sip_stop: no INTR bits set in dirty tx " 2887 "descriptors\n", device_xname(sc->sc_dev)); 2888 } 2889 2890 /* 2891 * sip_read_eeprom: 2892 * 2893 * Read data from the serial EEPROM. 2894 */ 2895 static void 2896 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2897 u_int16_t *data) 2898 { 2899 bus_space_tag_t st = sc->sc_st; 2900 bus_space_handle_t sh = sc->sc_sh; 2901 u_int16_t reg; 2902 int i, x; 2903 2904 for (i = 0; i < wordcnt; i++) { 2905 /* Send CHIP SELECT. */ 2906 reg = EROMAR_EECS; 2907 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2908 2909 /* Shift in the READ opcode. */ 2910 for (x = 3; x > 0; x--) { 2911 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2912 reg |= EROMAR_EEDI; 2913 else 2914 reg &= ~EROMAR_EEDI; 2915 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2916 bus_space_write_4(st, sh, SIP_EROMAR, 2917 reg | EROMAR_EESK); 2918 delay(4); 2919 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2920 delay(4); 2921 } 2922 2923 /* Shift in address. */ 2924 for (x = 6; x > 0; x--) { 2925 if ((word + i) & (1 << (x - 1))) 2926 reg |= EROMAR_EEDI; 2927 else 2928 reg &= ~EROMAR_EEDI; 2929 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2930 bus_space_write_4(st, sh, SIP_EROMAR, 2931 reg | EROMAR_EESK); 2932 delay(4); 2933 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2934 delay(4); 2935 } 2936 2937 /* Shift out data. */ 2938 reg = EROMAR_EECS; 2939 data[i] = 0; 2940 for (x = 16; x > 0; x--) { 2941 bus_space_write_4(st, sh, SIP_EROMAR, 2942 reg | EROMAR_EESK); 2943 delay(4); 2944 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2945 data[i] |= (1 << (x - 1)); 2946 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2947 delay(4); 2948 } 2949 2950 /* Clear CHIP SELECT. */ 2951 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2952 delay(4); 2953 } 2954 } 2955 2956 /* 2957 * sipcom_add_rxbuf: 2958 * 2959 * Add a receive buffer to the indicated descriptor. 2960 */ 2961 static int 2962 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2963 { 2964 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2965 struct mbuf *m; 2966 int error; 2967 2968 MGETHDR(m, M_DONTWAIT, MT_DATA); 2969 if (m == NULL) 2970 return (ENOBUFS); 2971 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2972 2973 MCLGET(m, M_DONTWAIT); 2974 if ((m->m_flags & M_EXT) == 0) { 2975 m_freem(m); 2976 return (ENOBUFS); 2977 } 2978 2979 /* XXX I don't believe this is necessary. --dyoung */ 2980 if (sc->sc_gigabit) 2981 m->m_len = sc->sc_parm->p_rxbuf_len; 2982 2983 if (rxs->rxs_mbuf != NULL) 2984 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2985 2986 rxs->rxs_mbuf = m; 2987 2988 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2989 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2990 BUS_DMA_READ|BUS_DMA_NOWAIT); 2991 if (error) { 2992 printf("%s: can't load rx DMA map %d, error = %d\n", 2993 device_xname(sc->sc_dev), idx, error); 2994 panic("%s", __func__); /* XXX */ 2995 } 2996 2997 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2998 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2999 3000 sip_init_rxdesc(sc, idx); 3001 3002 return (0); 3003 } 3004 3005 /* 3006 * sip_sis900_set_filter: 3007 * 3008 * Set up the receive filter. 3009 */ 3010 static void 3011 sipcom_sis900_set_filter(struct sip_softc *sc) 3012 { 3013 bus_space_tag_t st = sc->sc_st; 3014 bus_space_handle_t sh = sc->sc_sh; 3015 struct ethercom *ec = &sc->sc_ethercom; 3016 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3017 struct ether_multi *enm; 3018 const u_int8_t *cp; 3019 struct ether_multistep step; 3020 u_int32_t crc, mchash[16]; 3021 3022 /* 3023 * Initialize the prototype RFCR. 3024 */ 3025 sc->sc_rfcr = RFCR_RFEN; 3026 if (ifp->if_flags & IFF_BROADCAST) 3027 sc->sc_rfcr |= RFCR_AAB; 3028 if (ifp->if_flags & IFF_PROMISC) { 3029 sc->sc_rfcr |= RFCR_AAP; 3030 goto allmulti; 3031 } 3032 3033 /* 3034 * Set up the multicast address filter by passing all multicast 3035 * addresses through a CRC generator, and then using the high-order 3036 * 6 bits as an index into the 128 bit multicast hash table (only 3037 * the lower 16 bits of each 32 bit multicast hash register are 3038 * valid). The high order bits select the register, while the 3039 * rest of the bits select the bit within the register. 3040 */ 3041 3042 memset(mchash, 0, sizeof(mchash)); 3043 3044 /* 3045 * SiS900 (at least SiS963) requires us to register the address of 3046 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3047 */ 3048 crc = 0x0ed423f9; 3049 3050 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3051 SIP_SIS900_REV(sc, SIS_REV_960) || 3052 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3053 /* Just want the 8 most significant bits. */ 3054 crc >>= 24; 3055 } else { 3056 /* Just want the 7 most significant bits. */ 3057 crc >>= 25; 3058 } 3059 3060 /* Set the corresponding bit in the hash table. */ 3061 mchash[crc >> 4] |= 1 << (crc & 0xf); 3062 3063 ETHER_FIRST_MULTI(step, ec, enm); 3064 while (enm != NULL) { 3065 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3066 /* 3067 * We must listen to a range of multicast addresses. 3068 * For now, just accept all multicasts, rather than 3069 * trying to set only those filter bits needed to match 3070 * the range. (At this time, the only use of address 3071 * ranges is for IP multicast routing, for which the 3072 * range is big enough to require all bits set.) 3073 */ 3074 goto allmulti; 3075 } 3076 3077 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3078 3079 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3080 SIP_SIS900_REV(sc, SIS_REV_960) || 3081 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3082 /* Just want the 8 most significant bits. */ 3083 crc >>= 24; 3084 } else { 3085 /* Just want the 7 most significant bits. */ 3086 crc >>= 25; 3087 } 3088 3089 /* Set the corresponding bit in the hash table. */ 3090 mchash[crc >> 4] |= 1 << (crc & 0xf); 3091 3092 ETHER_NEXT_MULTI(step, enm); 3093 } 3094 3095 ifp->if_flags &= ~IFF_ALLMULTI; 3096 goto setit; 3097 3098 allmulti: 3099 ifp->if_flags |= IFF_ALLMULTI; 3100 sc->sc_rfcr |= RFCR_AAM; 3101 3102 setit: 3103 #define FILTER_EMIT(addr, data) \ 3104 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3105 delay(1); \ 3106 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3107 delay(1) 3108 3109 /* 3110 * Disable receive filter, and program the node address. 3111 */ 3112 cp = CLLADDR(ifp->if_sadl); 3113 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3114 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3115 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3116 3117 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3118 /* 3119 * Program the multicast hash table. 3120 */ 3121 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3122 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3123 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3124 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3125 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3126 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3127 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3128 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3129 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3130 SIP_SIS900_REV(sc, SIS_REV_960) || 3131 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3132 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3133 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3134 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3135 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3136 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3137 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3138 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3139 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3140 } 3141 } 3142 #undef FILTER_EMIT 3143 3144 /* 3145 * Re-enable the receiver filter. 3146 */ 3147 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3148 } 3149 3150 /* 3151 * sip_dp83815_set_filter: 3152 * 3153 * Set up the receive filter. 3154 */ 3155 static void 3156 sipcom_dp83815_set_filter(struct sip_softc *sc) 3157 { 3158 bus_space_tag_t st = sc->sc_st; 3159 bus_space_handle_t sh = sc->sc_sh; 3160 struct ethercom *ec = &sc->sc_ethercom; 3161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3162 struct ether_multi *enm; 3163 const u_int8_t *cp; 3164 struct ether_multistep step; 3165 u_int32_t crc, hash, slot, bit; 3166 #define MCHASH_NWORDS_83820 128 3167 #define MCHASH_NWORDS_83815 32 3168 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3169 u_int16_t mchash[MCHASH_NWORDS]; 3170 int i; 3171 3172 /* 3173 * Initialize the prototype RFCR. 3174 * Enable the receive filter, and accept on 3175 * Perfect (destination address) Match 3176 * If IFF_BROADCAST, also accept all broadcast packets. 3177 * If IFF_PROMISC, accept all unicast packets (and later, set 3178 * IFF_ALLMULTI and accept all multicast, too). 3179 */ 3180 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3181 if (ifp->if_flags & IFF_BROADCAST) 3182 sc->sc_rfcr |= RFCR_AAB; 3183 if (ifp->if_flags & IFF_PROMISC) { 3184 sc->sc_rfcr |= RFCR_AAP; 3185 goto allmulti; 3186 } 3187 3188 /* 3189 * Set up the DP83820/DP83815 multicast address filter by 3190 * passing all multicast addresses through a CRC generator, 3191 * and then using the high-order 11/9 bits as an index into 3192 * the 2048/512 bit multicast hash table. The high-order 3193 * 7/5 bits select the slot, while the low-order 4 bits 3194 * select the bit within the slot. Note that only the low 3195 * 16-bits of each filter word are used, and there are 3196 * 128/32 filter words. 3197 */ 3198 3199 memset(mchash, 0, sizeof(mchash)); 3200 3201 ifp->if_flags &= ~IFF_ALLMULTI; 3202 ETHER_FIRST_MULTI(step, ec, enm); 3203 if (enm == NULL) 3204 goto setit; 3205 while (enm != NULL) { 3206 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3207 /* 3208 * We must listen to a range of multicast addresses. 3209 * For now, just accept all multicasts, rather than 3210 * trying to set only those filter bits needed to match 3211 * the range. (At this time, the only use of address 3212 * ranges is for IP multicast routing, for which the 3213 * range is big enough to require all bits set.) 3214 */ 3215 goto allmulti; 3216 } 3217 3218 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3219 3220 if (sc->sc_gigabit) { 3221 /* Just want the 11 most significant bits. */ 3222 hash = crc >> 21; 3223 } else { 3224 /* Just want the 9 most significant bits. */ 3225 hash = crc >> 23; 3226 } 3227 3228 slot = hash >> 4; 3229 bit = hash & 0xf; 3230 3231 /* Set the corresponding bit in the hash table. */ 3232 mchash[slot] |= 1 << bit; 3233 3234 ETHER_NEXT_MULTI(step, enm); 3235 } 3236 sc->sc_rfcr |= RFCR_MHEN; 3237 goto setit; 3238 3239 allmulti: 3240 ifp->if_flags |= IFF_ALLMULTI; 3241 sc->sc_rfcr |= RFCR_AAM; 3242 3243 setit: 3244 #define FILTER_EMIT(addr, data) \ 3245 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3246 delay(1); \ 3247 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3248 delay(1) 3249 3250 /* 3251 * Disable receive filter, and program the node address. 3252 */ 3253 cp = CLLADDR(ifp->if_sadl); 3254 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3255 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3256 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3257 3258 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3259 int nwords = 3260 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3261 /* 3262 * Program the multicast hash table. 3263 */ 3264 for (i = 0; i < nwords; i++) { 3265 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3266 } 3267 } 3268 #undef FILTER_EMIT 3269 #undef MCHASH_NWORDS 3270 #undef MCHASH_NWORDS_83815 3271 #undef MCHASH_NWORDS_83820 3272 3273 /* 3274 * Re-enable the receiver filter. 3275 */ 3276 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3277 } 3278 3279 /* 3280 * sip_dp83820_mii_readreg: [mii interface function] 3281 * 3282 * Read a PHY register on the MII of the DP83820. 3283 */ 3284 static int 3285 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3286 { 3287 struct sip_softc *sc = device_private(self); 3288 3289 if (sc->sc_cfg & CFG_TBI_EN) { 3290 bus_addr_t tbireg; 3291 int rv; 3292 3293 if (phy != 0) 3294 return (0); 3295 3296 switch (reg) { 3297 case MII_BMCR: tbireg = SIP_TBICR; break; 3298 case MII_BMSR: tbireg = SIP_TBISR; break; 3299 case MII_ANAR: tbireg = SIP_TANAR; break; 3300 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3301 case MII_ANER: tbireg = SIP_TANER; break; 3302 case MII_EXTSR: 3303 /* 3304 * Don't even bother reading the TESR register. 3305 * The manual documents that the device has 3306 * 1000baseX full/half capability, but the 3307 * register itself seems read back 0 on some 3308 * boards. Just hard-code the result. 3309 */ 3310 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3311 3312 default: 3313 return (0); 3314 } 3315 3316 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3317 if (tbireg == SIP_TBISR) { 3318 /* LINK and ACOMP are switched! */ 3319 int val = rv; 3320 3321 rv = 0; 3322 if (val & TBISR_MR_LINK_STATUS) 3323 rv |= BMSR_LINK; 3324 if (val & TBISR_MR_AN_COMPLETE) 3325 rv |= BMSR_ACOMP; 3326 3327 /* 3328 * The manual claims this register reads back 0 3329 * on hard and soft reset. But we want to let 3330 * the gentbi driver know that we support auto- 3331 * negotiation, so hard-code this bit in the 3332 * result. 3333 */ 3334 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3335 } 3336 3337 return (rv); 3338 } 3339 3340 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3341 } 3342 3343 /* 3344 * sip_dp83820_mii_writereg: [mii interface function] 3345 * 3346 * Write a PHY register on the MII of the DP83820. 3347 */ 3348 static void 3349 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3350 { 3351 struct sip_softc *sc = device_private(self); 3352 3353 if (sc->sc_cfg & CFG_TBI_EN) { 3354 bus_addr_t tbireg; 3355 3356 if (phy != 0) 3357 return; 3358 3359 switch (reg) { 3360 case MII_BMCR: tbireg = SIP_TBICR; break; 3361 case MII_ANAR: tbireg = SIP_TANAR; break; 3362 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3363 default: 3364 return; 3365 } 3366 3367 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3368 return; 3369 } 3370 3371 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3372 } 3373 3374 /* 3375 * sip_dp83820_mii_statchg: [mii interface function] 3376 * 3377 * Callback from MII layer when media changes. 3378 */ 3379 static void 3380 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3381 { 3382 struct sip_softc *sc = ifp->if_softc; 3383 struct mii_data *mii = &sc->sc_mii; 3384 u_int32_t cfg, pcr; 3385 3386 /* 3387 * Get flow control negotiation result. 3388 */ 3389 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3390 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3391 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3392 mii->mii_media_active &= ~IFM_ETH_FMASK; 3393 } 3394 3395 /* 3396 * Update TXCFG for full-duplex operation. 3397 */ 3398 if ((mii->mii_media_active & IFM_FDX) != 0) 3399 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3400 else 3401 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3402 3403 /* 3404 * Update RXCFG for full-duplex or loopback. 3405 */ 3406 if ((mii->mii_media_active & IFM_FDX) != 0 || 3407 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3408 sc->sc_rxcfg |= RXCFG_ATX; 3409 else 3410 sc->sc_rxcfg &= ~RXCFG_ATX; 3411 3412 /* 3413 * Update CFG for MII/GMII. 3414 */ 3415 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3416 cfg = sc->sc_cfg | CFG_MODE_1000; 3417 else 3418 cfg = sc->sc_cfg; 3419 3420 /* 3421 * 802.3x flow control. 3422 */ 3423 pcr = 0; 3424 if (sc->sc_flowflags & IFM_FLOW) { 3425 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3426 pcr |= sc->sc_rx_flow_thresh; 3427 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3428 pcr |= PCR_PSEN | PCR_PS_MCAST; 3429 } 3430 3431 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3432 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3433 sc->sc_txcfg); 3434 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3435 sc->sc_rxcfg); 3436 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3437 } 3438 3439 /* 3440 * sip_mii_bitbang_read: [mii bit-bang interface function] 3441 * 3442 * Read the MII serial port for the MII bit-bang module. 3443 */ 3444 static u_int32_t 3445 sipcom_mii_bitbang_read(device_t self) 3446 { 3447 struct sip_softc *sc = device_private(self); 3448 3449 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3450 } 3451 3452 /* 3453 * sip_mii_bitbang_write: [mii big-bang interface function] 3454 * 3455 * Write the MII serial port for the MII bit-bang module. 3456 */ 3457 static void 3458 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3459 { 3460 struct sip_softc *sc = device_private(self); 3461 3462 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3463 } 3464 3465 /* 3466 * sip_sis900_mii_readreg: [mii interface function] 3467 * 3468 * Read a PHY register on the MII. 3469 */ 3470 static int 3471 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3472 { 3473 struct sip_softc *sc = device_private(self); 3474 u_int32_t enphy; 3475 3476 /* 3477 * The PHY of recent SiS chipsets is accessed through bitbang 3478 * operations. 3479 */ 3480 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3481 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3482 phy, reg); 3483 3484 #ifndef SIS900_MII_RESTRICT 3485 /* 3486 * The SiS 900 has only an internal PHY on the MII. Only allow 3487 * MII address 0. 3488 */ 3489 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3490 return (0); 3491 #endif 3492 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3494 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3495 ENPHY_RWCMD | ENPHY_ACCESS); 3496 do { 3497 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3498 } while (enphy & ENPHY_ACCESS); 3499 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3500 } 3501 3502 /* 3503 * sip_sis900_mii_writereg: [mii interface function] 3504 * 3505 * Write a PHY register on the MII. 3506 */ 3507 static void 3508 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3509 { 3510 struct sip_softc *sc = device_private(self); 3511 u_int32_t enphy; 3512 3513 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3514 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3515 phy, reg, val); 3516 return; 3517 } 3518 3519 #ifndef SIS900_MII_RESTRICT 3520 /* 3521 * The SiS 900 has only an internal PHY on the MII. Only allow 3522 * MII address 0. 3523 */ 3524 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3525 return; 3526 #endif 3527 3528 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3529 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3530 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3531 do { 3532 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3533 } while (enphy & ENPHY_ACCESS); 3534 } 3535 3536 /* 3537 * sip_sis900_mii_statchg: [mii interface function] 3538 * 3539 * Callback from MII layer when media changes. 3540 */ 3541 static void 3542 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3543 { 3544 struct sip_softc *sc = ifp->if_softc; 3545 struct mii_data *mii = &sc->sc_mii; 3546 u_int32_t flowctl; 3547 3548 /* 3549 * Get flow control negotiation result. 3550 */ 3551 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3552 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3553 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3554 mii->mii_media_active &= ~IFM_ETH_FMASK; 3555 } 3556 3557 /* 3558 * Update TXCFG for full-duplex operation. 3559 */ 3560 if ((mii->mii_media_active & IFM_FDX) != 0) 3561 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3562 else 3563 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3564 3565 /* 3566 * Update RXCFG for full-duplex or loopback. 3567 */ 3568 if ((mii->mii_media_active & IFM_FDX) != 0 || 3569 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3570 sc->sc_rxcfg |= RXCFG_ATX; 3571 else 3572 sc->sc_rxcfg &= ~RXCFG_ATX; 3573 3574 /* 3575 * Update IMR for use of 802.3x flow control. 3576 */ 3577 if (sc->sc_flowflags & IFM_FLOW) { 3578 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3579 flowctl = FLOWCTL_FLOWEN; 3580 } else { 3581 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3582 flowctl = 0; 3583 } 3584 3585 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3586 sc->sc_txcfg); 3587 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3588 sc->sc_rxcfg); 3589 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3590 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3591 } 3592 3593 /* 3594 * sip_dp83815_mii_readreg: [mii interface function] 3595 * 3596 * Read a PHY register on the MII. 3597 */ 3598 static int 3599 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3600 { 3601 struct sip_softc *sc = device_private(self); 3602 u_int32_t val; 3603 3604 /* 3605 * The DP83815 only has an internal PHY. Only allow 3606 * MII address 0. 3607 */ 3608 if (phy != 0) 3609 return (0); 3610 3611 /* 3612 * Apparently, after a reset, the DP83815 can take a while 3613 * to respond. During this recovery period, the BMSR returns 3614 * a value of 0. Catch this -- it's not supposed to happen 3615 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3616 * PHY to come back to life. 3617 * 3618 * This works out because the BMSR is the first register 3619 * read during the PHY probe process. 3620 */ 3621 do { 3622 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3623 } while (reg == MII_BMSR && val == 0); 3624 3625 return (val & 0xffff); 3626 } 3627 3628 /* 3629 * sip_dp83815_mii_writereg: [mii interface function] 3630 * 3631 * Write a PHY register to the MII. 3632 */ 3633 static void 3634 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3635 { 3636 struct sip_softc *sc = device_private(self); 3637 3638 /* 3639 * The DP83815 only has an internal PHY. Only allow 3640 * MII address 0. 3641 */ 3642 if (phy != 0) 3643 return; 3644 3645 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3646 } 3647 3648 /* 3649 * sip_dp83815_mii_statchg: [mii interface function] 3650 * 3651 * Callback from MII layer when media changes. 3652 */ 3653 static void 3654 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3655 { 3656 struct sip_softc *sc = ifp->if_softc; 3657 3658 /* 3659 * Update TXCFG for full-duplex operation. 3660 */ 3661 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3662 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3663 else 3664 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3665 3666 /* 3667 * Update RXCFG for full-duplex or loopback. 3668 */ 3669 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3670 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3671 sc->sc_rxcfg |= RXCFG_ATX; 3672 else 3673 sc->sc_rxcfg &= ~RXCFG_ATX; 3674 3675 /* 3676 * XXX 802.3x flow control. 3677 */ 3678 3679 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3680 sc->sc_txcfg); 3681 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3682 sc->sc_rxcfg); 3683 3684 /* 3685 * Some DP83815s experience problems when used with short 3686 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3687 * sequence adjusts the DSP's signal attenuation to fix the 3688 * problem. 3689 */ 3690 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3691 uint32_t reg; 3692 3693 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3694 3695 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3696 reg &= 0x0fff; 3697 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3698 delay(100); 3699 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3700 reg &= 0x00ff; 3701 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3702 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3703 0x00e8); 3704 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3705 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3706 reg | 0x20); 3707 } 3708 3709 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3710 } 3711 } 3712 3713 static void 3714 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3715 const struct pci_attach_args *pa, u_int8_t *enaddr) 3716 { 3717 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3718 u_int8_t cksum, *e, match; 3719 int i; 3720 3721 /* 3722 * EEPROM data format for the DP83820 can be found in 3723 * the DP83820 manual, section 4.2.4. 3724 */ 3725 3726 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3727 3728 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3729 match = ~(match - 1); 3730 3731 cksum = 0x55; 3732 e = (u_int8_t *) eeprom_data; 3733 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3734 cksum += *e++; 3735 3736 if (cksum != match) 3737 printf("%s: Checksum (%x) mismatch (%x)", 3738 device_xname(sc->sc_dev), cksum, match); 3739 3740 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3741 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3742 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3743 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3744 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3745 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3746 } 3747 3748 static void 3749 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3750 { 3751 int i; 3752 3753 /* 3754 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3755 * a reason, but I don't know it. 3756 */ 3757 for (i = 0; i < 10; i++) 3758 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3759 } 3760 3761 static void 3762 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3763 const struct pci_attach_args *pa, u_int8_t *enaddr) 3764 { 3765 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3766 3767 switch (sc->sc_rev) { 3768 case SIS_REV_630S: 3769 case SIS_REV_630E: 3770 case SIS_REV_630EA1: 3771 case SIS_REV_630ET: 3772 case SIS_REV_635: 3773 /* 3774 * The MAC address for the on-board Ethernet of 3775 * the SiS 630 chipset is in the NVRAM. Kick 3776 * the chip into re-loading it from NVRAM, and 3777 * read the MAC address out of the filter registers. 3778 */ 3779 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3780 3781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3782 RFCR_RFADDR_NODE0); 3783 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3784 0xffff; 3785 3786 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3787 RFCR_RFADDR_NODE2); 3788 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3789 0xffff; 3790 3791 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3792 RFCR_RFADDR_NODE4); 3793 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3794 0xffff; 3795 break; 3796 3797 case SIS_REV_960: 3798 { 3799 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3800 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3801 3802 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3803 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3804 3805 int waittime, i; 3806 3807 /* Allow to read EEPROM from LAN. It is shared 3808 * between a 1394 controller and the NIC and each 3809 * time we access it, we need to set SIS_EECMD_REQ. 3810 */ 3811 SIS_SET_EROMAR(sc, EROMAR_REQ); 3812 3813 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3814 /* Force EEPROM to idle state. */ 3815 3816 /* 3817 * XXX-cube This is ugly. I'll look for docs about it. 3818 */ 3819 SIS_SET_EROMAR(sc, EROMAR_EECS); 3820 sipcom_sis900_eeprom_delay(sc); 3821 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3822 SIS_SET_EROMAR(sc, EROMAR_EESK); 3823 sipcom_sis900_eeprom_delay(sc); 3824 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3825 sipcom_sis900_eeprom_delay(sc); 3826 } 3827 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3828 sipcom_sis900_eeprom_delay(sc); 3829 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3830 3831 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3832 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3833 sizeof(myea) / sizeof(myea[0]), myea); 3834 break; 3835 } 3836 DELAY(1); 3837 } 3838 3839 /* 3840 * Set SIS_EECTL_CLK to high, so a other master 3841 * can operate on the i2c bus. 3842 */ 3843 SIS_SET_EROMAR(sc, EROMAR_EESK); 3844 3845 /* Refuse EEPROM access by LAN */ 3846 SIS_SET_EROMAR(sc, EROMAR_DONE); 3847 } break; 3848 3849 default: 3850 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3851 sizeof(myea) / sizeof(myea[0]), myea); 3852 } 3853 3854 enaddr[0] = myea[0] & 0xff; 3855 enaddr[1] = myea[0] >> 8; 3856 enaddr[2] = myea[1] & 0xff; 3857 enaddr[3] = myea[1] >> 8; 3858 enaddr[4] = myea[2] & 0xff; 3859 enaddr[5] = myea[2] >> 8; 3860 } 3861 3862 /* Table and macro to bit-reverse an octet. */ 3863 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3864 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3865 3866 static void 3867 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3868 const struct pci_attach_args *pa, u_int8_t *enaddr) 3869 { 3870 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3871 u_int8_t cksum, *e, match; 3872 int i; 3873 3874 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3875 sizeof(eeprom_data[0]), eeprom_data); 3876 3877 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3878 match = ~(match - 1); 3879 3880 cksum = 0x55; 3881 e = (u_int8_t *) eeprom_data; 3882 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3883 cksum += *e++; 3884 } 3885 if (cksum != match) { 3886 printf("%s: Checksum (%x) mismatch (%x)", 3887 device_xname(sc->sc_dev), cksum, match); 3888 } 3889 3890 /* 3891 * Unrolled because it makes slightly more sense this way. 3892 * The DP83815 stores the MAC address in bit 0 of word 6 3893 * through bit 15 of word 8. 3894 */ 3895 ea = &eeprom_data[6]; 3896 enaddr[0] = ((*ea & 0x1) << 7); 3897 ea++; 3898 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3899 enaddr[1] = ((*ea & 0x1FE) >> 1); 3900 enaddr[2] = ((*ea & 0x1) << 7); 3901 ea++; 3902 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3903 enaddr[3] = ((*ea & 0x1FE) >> 1); 3904 enaddr[4] = ((*ea & 0x1) << 7); 3905 ea++; 3906 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3907 enaddr[5] = ((*ea & 0x1FE) >> 1); 3908 3909 /* 3910 * In case that's not weird enough, we also need to reverse 3911 * the bits in each byte. This all actually makes more sense 3912 * if you think about the EEPROM storage as an array of bits 3913 * being shifted into bytes, but that's not how we're looking 3914 * at it here... 3915 */ 3916 for (i = 0; i < 6 ;i++) 3917 enaddr[i] = bbr(enaddr[i]); 3918 } 3919 3920 /* 3921 * sip_mediastatus: [ifmedia interface function] 3922 * 3923 * Get the current interface media status. 3924 */ 3925 static void 3926 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3927 { 3928 struct sip_softc *sc = ifp->if_softc; 3929 3930 if (!device_is_active(sc->sc_dev)) { 3931 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3932 ifmr->ifm_status = 0; 3933 return; 3934 } 3935 ether_mediastatus(ifp, ifmr); 3936 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3937 sc->sc_flowflags; 3938 } 3939
Indexes created Tue Sep 30 17:09:57 GMT 2025