if_sip.c revision 1.161
1 /* $NetBSD: if_sip.c,v 1.161 2016/06/10 13:27:14 ozaki-r Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.161 2016/06/10 13:27:14 ozaki-r Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rndsource.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int); 587 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int); 591 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int); 595 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int); 622 void (*sipv_mii_writereg)(device_t, int, int, int); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA621 */ 741 { 0x1385, 0x621a }, 742 743 /* Netgear GA622 */ 744 { 0x1385, 0x622a }, 745 746 /* SMC EZ Card 1000 (9462TX) */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, cfdata_t cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 rnd_detach_source(&sc->rnd_source); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 918 919 /*FALLTHROUGH*/ 920 case SIP_ATTACH_CREATE_RXMAP: 921 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 922 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_rxsoft[i].rxs_dmamap); 925 } 926 /*FALLTHROUGH*/ 927 case SIP_ATTACH_CREATE_TXMAP: 928 for (i = 0; i < SIP_TXQUEUELEN; i++) { 929 if (sc->sc_txsoft[i].txs_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txsoft[i].txs_dmamap); 932 } 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_LOAD_MAP: 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_CREATE_MAP: 938 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_MAP_MEM: 941 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 942 sizeof(struct sip_control_data)); 943 /*FALLTHROUGH*/ 944 case SIP_ATTACH_ALLOC_MEM: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_INTR: 948 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_MAP: 951 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 952 break; 953 default: 954 break; 955 } 956 return; 957 } 958 959 static bool 960 sipcom_resume(device_t self, const pmf_qual_t *qual) 961 { 962 struct sip_softc *sc = device_private(self); 963 964 return sipcom_reset(sc); 965 } 966 967 static bool 968 sipcom_suspend(device_t self, const pmf_qual_t *qual) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 sipcom_rxdrain(sc); 973 return true; 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = device_private(self); 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t csr; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 char intrbuf[PCI_INTRSTR_LEN]; 998 999 callout_init(&sc->sc_tick_ch, 0); 1000 1001 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1002 if (sip == NULL) { 1003 printf("\n"); 1004 panic("%s: impossible", __func__); 1005 } 1006 sc->sc_dev = self; 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1027 1028 sc->sc_model = sip; 1029 1030 /* 1031 * XXX Work-around broken PXE firmware on some boards. 1032 * 1033 * The DP83815 shares an address decoder with the MEM BAR 1034 * and the ROM BAR. Make sure the ROM BAR is disabled, 1035 * so that memory mapped access works. 1036 */ 1037 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1038 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1039 ~PCI_MAPREG_ROM_ENABLE); 1040 1041 /* 1042 * Map the device. 1043 */ 1044 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1045 PCI_MAPREG_TYPE_IO, 0, 1046 &iot, &ioh, NULL, &iosz) == 0); 1047 if (sc->sc_gigabit) { 1048 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1049 switch (memtype) { 1050 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1052 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1053 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1054 break; 1055 default: 1056 memh_valid = 0; 1057 } 1058 } else { 1059 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1060 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1061 &memt, &memh, NULL, &memsz) == 0); 1062 } 1063 1064 if (memh_valid) { 1065 sc->sc_st = memt; 1066 sc->sc_sh = memh; 1067 sc->sc_sz = memsz; 1068 } else if (ioh_valid) { 1069 sc->sc_st = iot; 1070 sc->sc_sh = ioh; 1071 sc->sc_sz = iosz; 1072 } else { 1073 printf("%s: unable to map device registers\n", 1074 device_xname(sc->sc_dev)); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 csr | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1092 if (error != 0 && error != EOPNOTSUPP) { 1093 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1094 return; 1095 } 1096 1097 /* 1098 * Map and establish our interrupt. 1099 */ 1100 if (pci_intr_map(pa, &ih)) { 1101 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1102 return; 1103 } 1104 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1105 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1106 if (sc->sc_ih == NULL) { 1107 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1108 if (intrstr != NULL) 1109 aprint_error(" at %s", intrstr); 1110 aprint_error("\n"); 1111 sipcom_do_detach(self, SIP_ATTACH_MAP); 1112 return; 1113 } 1114 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1115 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 1119 /* 1120 * Allocate the control data structures, and create and load the 1121 * DMA map for it. 1122 */ 1123 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1124 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1125 &rseg, 0)) != 0) { 1126 aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n", 1127 error); 1128 sipcom_do_detach(self, SIP_ATTACH_INTR); 1129 return; 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1133 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1134 BUS_DMA_COHERENT)) != 0) { 1135 aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n", 1136 error); 1137 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1138 } 1139 1140 if ((error = bus_dmamap_create(sc->sc_dmat, 1141 sizeof(struct sip_control_data), 1, 1142 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1143 aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, " 1144 "error = %d\n", error); 1145 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1146 } 1147 1148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1149 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1150 0)) != 0) { 1151 aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n", 1152 error); 1153 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1154 } 1155 1156 /* 1157 * Create the transmit buffer DMA maps. 1158 */ 1159 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1160 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1161 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1162 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1163 aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, " 1164 "error = %d\n", i, error); 1165 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1166 } 1167 } 1168 1169 /* 1170 * Create the receive buffer DMA maps. 1171 */ 1172 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1173 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1174 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1175 aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, " 1176 "error = %d\n", i, error); 1177 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1178 } 1179 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1180 } 1181 1182 /* 1183 * Reset the chip to a known state. 1184 */ 1185 sipcom_reset(sc); 1186 1187 /* 1188 * Read the Ethernet address from the EEPROM. This might 1189 * also fetch other stuff from the EEPROM and stash it 1190 * in the softc. 1191 */ 1192 sc->sc_cfg = 0; 1193 if (!sc->sc_gigabit) { 1194 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1195 SIP_SIS900_REV(sc,SIS_REV_900B)) 1196 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1197 1198 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1199 SIP_SIS900_REV(sc,SIS_REV_960) || 1200 SIP_SIS900_REV(sc,SIS_REV_900B)) 1201 sc->sc_cfg |= 1202 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1203 CFG_EDBMASTEN); 1204 } 1205 1206 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1207 1208 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 1209 ether_sprintf(enaddr)); 1210 1211 /* 1212 * Initialize the configuration register: aggressive PCI 1213 * bus request algorithm, default backoff, default OW timer, 1214 * default parity error detection. 1215 * 1216 * NOTE: "Big endian mode" is useless on the SiS900 and 1217 * friends -- it affects packet data, not descriptors. 1218 */ 1219 if (sc->sc_gigabit) 1220 sipcom_dp83820_attach(sc, pa); 1221 1222 /* 1223 * Initialize our media structures and probe the MII. 1224 */ 1225 sc->sc_mii.mii_ifp = ifp; 1226 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1227 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1228 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1229 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1230 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1231 sipcom_mediastatus); 1232 1233 /* 1234 * XXX We cannot handle flow control on the DP83815. 1235 */ 1236 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1237 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, 0); 1239 else 1240 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1241 MII_OFFSET_ANY, MIIF_DOPAUSE); 1242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1245 } else 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1247 1248 ifp = &sc->sc_ethercom.ec_if; 1249 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1250 ifp->if_softc = sc; 1251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1252 sc->sc_if_flags = ifp->if_flags; 1253 ifp->if_ioctl = sipcom_ioctl; 1254 ifp->if_start = sipcom_start; 1255 ifp->if_watchdog = sipcom_watchdog; 1256 ifp->if_init = sipcom_init; 1257 ifp->if_stop = sipcom_stop; 1258 IFQ_SET_READY(&ifp->if_snd); 1259 1260 /* 1261 * We can support 802.1Q VLAN-sized frames. 1262 */ 1263 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1264 1265 if (sc->sc_gigabit) { 1266 /* 1267 * And the DP83820 can do VLAN tagging in hardware, and 1268 * support the jumbo Ethernet MTU. 1269 */ 1270 sc->sc_ethercom.ec_capabilities |= 1271 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1272 1273 /* 1274 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1275 * in hardware. 1276 */ 1277 ifp->if_capabilities |= 1278 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1279 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1280 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1281 } 1282 1283 /* 1284 * Attach the interface. 1285 */ 1286 if_attach(ifp); 1287 ether_ifattach(ifp, enaddr); 1288 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1289 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1290 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1291 sc->sc_prev.if_capenable = ifp->if_capenable; 1292 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1293 RND_TYPE_NET, RND_FLAG_DEFAULT); 1294 1295 /* 1296 * The number of bytes that must be available in 1297 * the Tx FIFO before the bus master can DMA more 1298 * data into the FIFO. 1299 */ 1300 sc->sc_tx_fill_thresh = 64 / 32; 1301 1302 /* 1303 * Start at a drain threshold of 512 bytes. We will 1304 * increase it if a DMA underrun occurs. 1305 * 1306 * XXX The minimum value of this variable should be 1307 * tuned. We may be able to improve performance 1308 * by starting with a lower value. That, however, 1309 * may trash the first few outgoing packets if the 1310 * PCI bus is saturated. 1311 */ 1312 if (sc->sc_gigabit) 1313 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1314 else 1315 sc->sc_tx_drain_thresh = 1504 / 32; 1316 1317 /* 1318 * Initialize the Rx FIFO drain threshold. 1319 * 1320 * This is in units of 8 bytes. 1321 * 1322 * We should never set this value lower than 2; 14 bytes are 1323 * required to filter the packet. 1324 */ 1325 sc->sc_rx_drain_thresh = 128 / 8; 1326 1327 #ifdef SIP_EVENT_COUNTERS 1328 /* 1329 * Attach event counters. 1330 */ 1331 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1332 NULL, device_xname(sc->sc_dev), "txsstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1334 NULL, device_xname(sc->sc_dev), "txdstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(sc->sc_dev), "txforceintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "txdintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txiintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "rxintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "hiberr"); 1345 if (!sc->sc_gigabit) { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1347 NULL, device_xname(sc->sc_dev), "rxpause"); 1348 } else { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1350 NULL, device_xname(sc->sc_dev), "rxpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "txpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxipsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "txipsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txudpsum"); 1365 } 1366 #endif /* SIP_EVENT_COUNTERS */ 1367 1368 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1369 pmf_class_network_register(self, ifp); 1370 else 1371 aprint_error_dev(self, "couldn't establish power handler\n"); 1372 } 1373 1374 static inline void 1375 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1376 uint64_t capenable) 1377 { 1378 struct m_tag *mtag; 1379 u_int32_t extsts; 1380 #ifdef DEBUG 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 #endif 1383 /* 1384 * If VLANs are enabled and the packet has a VLAN tag, set 1385 * up the descriptor to encapsulate the packet for us. 1386 * 1387 * This apparently has to be on the last descriptor of 1388 * the packet. 1389 */ 1390 1391 /* 1392 * Byte swapping is tricky. We need to provide the tag 1393 * in a network byte order. On a big-endian machine, 1394 * the byteorder is correct, but we need to swap it 1395 * anyway, because this will be undone by the outside 1396 * htole32(). That's why there must be an 1397 * unconditional swap instead of htons() inside. 1398 */ 1399 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1400 sc->sc_txdescs[lasttx].sipd_extsts |= 1401 htole32(EXTSTS_VPKT | 1402 (bswap16(VLAN_TAG_VALUE(mtag)) & 1403 EXTSTS_VTCI)); 1404 } 1405 1406 /* 1407 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1408 * checksumming, set up the descriptor to do this work 1409 * for us. 1410 * 1411 * This apparently has to be on the first descriptor of 1412 * the packet. 1413 * 1414 * Byte-swap constants so the compiler can optimize. 1415 */ 1416 extsts = 0; 1417 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1418 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1419 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1420 extsts |= htole32(EXTSTS_IPPKT); 1421 } 1422 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1425 extsts |= htole32(EXTSTS_TCPPKT); 1426 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1429 extsts |= htole32(EXTSTS_UDPPKT); 1430 } 1431 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1432 } 1433 1434 /* 1435 * sip_start: [ifnet interface function] 1436 * 1437 * Start packet transmission on the interface. 1438 */ 1439 static void 1440 sipcom_start(struct ifnet *ifp) 1441 { 1442 struct sip_softc *sc = ifp->if_softc; 1443 struct mbuf *m0; 1444 struct mbuf *m; 1445 struct sip_txsoft *txs; 1446 bus_dmamap_t dmamap; 1447 int error, nexttx, lasttx, seg; 1448 int ofree = sc->sc_txfree; 1449 #if 0 1450 int firsttx = sc->sc_txnext; 1451 #endif 1452 1453 /* 1454 * If we've been told to pause, don't transmit any more packets. 1455 */ 1456 if (!sc->sc_gigabit && sc->sc_paused) 1457 ifp->if_flags |= IFF_OACTIVE; 1458 1459 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1460 return; 1461 1462 /* 1463 * Loop through the send queue, setting up transmit descriptors 1464 * until we drain the queue, or use up all available transmit 1465 * descriptors. 1466 */ 1467 for (;;) { 1468 /* Get a work queue entry. */ 1469 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1470 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1471 break; 1472 } 1473 1474 /* 1475 * Grab a packet off the queue. 1476 */ 1477 IFQ_POLL(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 m = NULL; 1481 1482 dmamap = txs->txs_dmamap; 1483 1484 /* 1485 * Load the DMA map. If this fails, the packet either 1486 * didn't fit in the alloted number of segments, or we 1487 * were short on resources. 1488 */ 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1490 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1491 /* In the non-gigabit case, we'll copy and try again. */ 1492 if (error != 0 && !sc->sc_gigabit) { 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) { 1495 printf("%s: unable to allocate Tx mbuf\n", 1496 device_xname(sc->sc_dev)); 1497 break; 1498 } 1499 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1500 if (m0->m_pkthdr.len > MHLEN) { 1501 MCLGET(m, M_DONTWAIT); 1502 if ((m->m_flags & M_EXT) == 0) { 1503 printf("%s: unable to allocate Tx " 1504 "cluster\n", device_xname(sc->sc_dev)); 1505 m_freem(m); 1506 break; 1507 } 1508 } 1509 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1510 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1511 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1512 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1513 if (error) { 1514 printf("%s: unable to load Tx buffer, " 1515 "error = %d\n", device_xname(sc->sc_dev), error); 1516 break; 1517 } 1518 } else if (error == EFBIG) { 1519 /* 1520 * For the too-many-segments case, we simply 1521 * report an error and drop the packet, 1522 * since we can't sanely copy a jumbo packet 1523 * to a single buffer. 1524 */ 1525 printf("%s: Tx packet consumes too many " 1526 "DMA segments, dropping...\n", device_xname(sc->sc_dev)); 1527 IFQ_DEQUEUE(&ifp->if_snd, m0); 1528 m_freem(m0); 1529 continue; 1530 } else if (error != 0) { 1531 /* 1532 * Short on resources, just stop for now. 1533 */ 1534 break; 1535 } 1536 1537 /* 1538 * Ensure we have enough descriptors free to describe 1539 * the packet. Note, we always reserve one descriptor 1540 * at the end of the ring as a termination point, to 1541 * prevent wrap-around. 1542 */ 1543 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1544 /* 1545 * Not enough free descriptors to transmit this 1546 * packet. We haven't committed anything yet, 1547 * so just unload the DMA map, put the packet 1548 * back on the queue, and punt. Notify the upper 1549 * layer that there are not more slots left. 1550 * 1551 * XXX We could allocate an mbuf and copy, but 1552 * XXX is it worth it? 1553 */ 1554 ifp->if_flags |= IFF_OACTIVE; 1555 bus_dmamap_unload(sc->sc_dmat, dmamap); 1556 if (m != NULL) 1557 m_freem(m); 1558 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1559 break; 1560 } 1561 1562 IFQ_DEQUEUE(&ifp->if_snd, m0); 1563 if (m != NULL) { 1564 m_freem(m0); 1565 m0 = m; 1566 } 1567 1568 /* 1569 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1570 */ 1571 1572 /* Sync the DMA map. */ 1573 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1574 BUS_DMASYNC_PREWRITE); 1575 1576 /* 1577 * Initialize the transmit descriptors. 1578 */ 1579 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1580 seg < dmamap->dm_nsegs; 1581 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1582 /* 1583 * If this is the first descriptor we're 1584 * enqueueing, don't set the OWN bit just 1585 * yet. That could cause a race condition. 1586 * We'll do it below. 1587 */ 1588 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1589 htole32(dmamap->dm_segs[seg].ds_addr); 1590 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1591 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1592 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1593 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1594 lasttx = nexttx; 1595 } 1596 1597 /* Clear the MORE bit on the last segment. */ 1598 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1599 htole32(~CMDSTS_MORE); 1600 1601 /* 1602 * If we're in the interrupt delay window, delay the 1603 * interrupt. 1604 */ 1605 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1606 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1607 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1608 htole32(CMDSTS_INTR); 1609 sc->sc_txwin = 0; 1610 } 1611 1612 if (sc->sc_gigabit) 1613 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1614 1615 /* Sync the descriptors we're using. */ 1616 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1617 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1618 1619 /* 1620 * The entire packet is set up. Give the first descrptor 1621 * to the chip now. 1622 */ 1623 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1624 htole32(CMDSTS_OWN); 1625 sip_cdtxsync(sc, sc->sc_txnext, 1, 1626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1627 1628 /* 1629 * Store a pointer to the packet so we can free it later, 1630 * and remember what txdirty will be once the packet is 1631 * done. 1632 */ 1633 txs->txs_mbuf = m0; 1634 txs->txs_firstdesc = sc->sc_txnext; 1635 txs->txs_lastdesc = lasttx; 1636 1637 /* Advance the tx pointer. */ 1638 sc->sc_txfree -= dmamap->dm_nsegs; 1639 sc->sc_txnext = nexttx; 1640 1641 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1642 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1643 1644 /* 1645 * Pass the packet to any BPF listeners. 1646 */ 1647 bpf_mtap(ifp, m0); 1648 } 1649 1650 if (txs == NULL || sc->sc_txfree == 0) { 1651 /* No more slots left; notify upper layer. */ 1652 ifp->if_flags |= IFF_OACTIVE; 1653 } 1654 1655 if (sc->sc_txfree != ofree) { 1656 /* 1657 * Start the transmit process. Note, the manual says 1658 * that if there are no pending transmissions in the 1659 * chip's internal queue (indicated by TXE being clear), 1660 * then the driver software must set the TXDP to the 1661 * first descriptor to be transmitted. However, if we 1662 * do this, it causes serious performance degredation on 1663 * the DP83820 under load, not setting TXDP doesn't seem 1664 * to adversely affect the SiS 900 or DP83815. 1665 * 1666 * Well, I guess it wouldn't be the first time a manual 1667 * has lied -- and they could be speaking of the NULL- 1668 * terminated descriptor list case, rather than OWN- 1669 * terminated rings. 1670 */ 1671 #if 0 1672 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1673 CR_TXE) == 0) { 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1675 SIP_CDTXADDR(sc, firsttx)); 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1677 } 1678 #else 1679 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1680 #endif 1681 1682 /* Set a watchdog timer in case the chip flakes out. */ 1683 /* Gigabit autonegotiation takes 5 seconds. */ 1684 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1685 } 1686 } 1687 1688 /* 1689 * sip_watchdog: [ifnet interface function] 1690 * 1691 * Watchdog timer handler. 1692 */ 1693 static void 1694 sipcom_watchdog(struct ifnet *ifp) 1695 { 1696 struct sip_softc *sc = ifp->if_softc; 1697 1698 /* 1699 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1700 * If we get a timeout, try and sweep up transmit descriptors. 1701 * If we manage to sweep them all up, ignore the lack of 1702 * interrupt. 1703 */ 1704 sipcom_txintr(sc); 1705 1706 if (sc->sc_txfree != sc->sc_ntxdesc) { 1707 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1708 ifp->if_oerrors++; 1709 1710 /* Reset the interface. */ 1711 (void) sipcom_init(ifp); 1712 } else if (ifp->if_flags & IFF_DEBUG) 1713 printf("%s: recovered from device timeout\n", 1714 device_xname(sc->sc_dev)); 1715 1716 /* Try to get more packets going. */ 1717 sipcom_start(ifp); 1718 } 1719 1720 /* If the interface is up and running, only modify the receive 1721 * filter when setting promiscuous or debug mode. Otherwise fall 1722 * through to ether_ioctl, which will reset the chip. 1723 */ 1724 static int 1725 sip_ifflags_cb(struct ethercom *ec) 1726 { 1727 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1728 == (sc)->sc_ethercom.ec_capenable) \ 1729 && ((sc)->sc_prev.is_vlan == \ 1730 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1731 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1732 struct ifnet *ifp = &ec->ec_if; 1733 struct sip_softc *sc = ifp->if_softc; 1734 int change = ifp->if_flags ^ sc->sc_if_flags; 1735 1736 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1737 !COMPARE_IC(sc, ifp)) 1738 return ENETRESET; 1739 /* Set up the receive filter. */ 1740 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1741 return 0; 1742 } 1743 1744 /* 1745 * sip_ioctl: [ifnet interface function] 1746 * 1747 * Handle control requests from the operator. 1748 */ 1749 static int 1750 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1751 { 1752 struct sip_softc *sc = ifp->if_softc; 1753 struct ifreq *ifr = (struct ifreq *)data; 1754 int s, error; 1755 1756 s = splnet(); 1757 1758 switch (cmd) { 1759 case SIOCSIFMEDIA: 1760 /* Flow control requires full-duplex mode. */ 1761 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1762 (ifr->ifr_media & IFM_FDX) == 0) 1763 ifr->ifr_media &= ~IFM_ETH_FMASK; 1764 1765 /* XXX */ 1766 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1767 ifr->ifr_media &= ~IFM_ETH_FMASK; 1768 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1769 if (sc->sc_gigabit && 1770 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1771 /* We can do both TXPAUSE and RXPAUSE. */ 1772 ifr->ifr_media |= 1773 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1774 } else if (ifr->ifr_media & IFM_FLOW) { 1775 /* 1776 * Both TXPAUSE and RXPAUSE must be set. 1777 * (SiS900 and DP83815 don't have PAUSE_ASYM 1778 * feature.) 1779 * 1780 * XXX Can SiS900 and DP83815 send PAUSE? 1781 */ 1782 ifr->ifr_media |= 1783 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1784 } 1785 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1786 } 1787 /*FALLTHROUGH*/ 1788 default: 1789 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1790 break; 1791 1792 error = 0; 1793 1794 if (cmd == SIOCSIFCAP) 1795 error = (*ifp->if_init)(ifp); 1796 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1797 ; 1798 else if (ifp->if_flags & IFF_RUNNING) { 1799 /* 1800 * Multicast list has changed; set the hardware filter 1801 * accordingly. 1802 */ 1803 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1804 } 1805 break; 1806 } 1807 1808 /* Try to get more packets going. */ 1809 sipcom_start(ifp); 1810 1811 sc->sc_if_flags = ifp->if_flags; 1812 splx(s); 1813 return (error); 1814 } 1815 1816 /* 1817 * sip_intr: 1818 * 1819 * Interrupt service routine. 1820 */ 1821 static int 1822 sipcom_intr(void *arg) 1823 { 1824 struct sip_softc *sc = arg; 1825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1826 u_int32_t isr; 1827 int handled = 0; 1828 1829 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1830 return 0; 1831 1832 /* Disable interrupts. */ 1833 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1834 1835 for (;;) { 1836 /* Reading clears interrupt. */ 1837 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1838 if ((isr & sc->sc_imr) == 0) 1839 break; 1840 1841 rnd_add_uint32(&sc->rnd_source, isr); 1842 1843 handled = 1; 1844 1845 if ((ifp->if_flags & IFF_RUNNING) == 0) 1846 break; 1847 1848 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1849 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1850 1851 /* Grab any new packets. */ 1852 (*sc->sc_rxintr)(sc); 1853 1854 if (isr & ISR_RXORN) { 1855 printf("%s: receive FIFO overrun\n", 1856 device_xname(sc->sc_dev)); 1857 1858 /* XXX adjust rx_drain_thresh? */ 1859 } 1860 1861 if (isr & ISR_RXIDLE) { 1862 printf("%s: receive ring overrun\n", 1863 device_xname(sc->sc_dev)); 1864 1865 /* Get the receive process going again. */ 1866 bus_space_write_4(sc->sc_st, sc->sc_sh, 1867 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1868 bus_space_write_4(sc->sc_st, sc->sc_sh, 1869 SIP_CR, CR_RXE); 1870 } 1871 } 1872 1873 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1874 #ifdef SIP_EVENT_COUNTERS 1875 if (isr & ISR_TXDESC) 1876 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1877 else if (isr & ISR_TXIDLE) 1878 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1879 #endif 1880 1881 /* Sweep up transmit descriptors. */ 1882 sipcom_txintr(sc); 1883 1884 if (isr & ISR_TXURN) { 1885 u_int32_t thresh; 1886 int txfifo_size = (sc->sc_gigabit) 1887 ? DP83820_SIP_TXFIFO_SIZE 1888 : OTHER_SIP_TXFIFO_SIZE; 1889 1890 printf("%s: transmit FIFO underrun", 1891 device_xname(sc->sc_dev)); 1892 thresh = sc->sc_tx_drain_thresh + 1; 1893 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1894 && (thresh * 32) <= (txfifo_size - 1895 (sc->sc_tx_fill_thresh * 32))) { 1896 printf("; increasing Tx drain " 1897 "threshold to %u bytes\n", 1898 thresh * 32); 1899 sc->sc_tx_drain_thresh = thresh; 1900 (void) sipcom_init(ifp); 1901 } else { 1902 (void) sipcom_init(ifp); 1903 printf("\n"); 1904 } 1905 } 1906 } 1907 1908 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1909 if (isr & ISR_PAUSE_ST) { 1910 sc->sc_paused = 1; 1911 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1912 ifp->if_flags |= IFF_OACTIVE; 1913 } 1914 if (isr & ISR_PAUSE_END) { 1915 sc->sc_paused = 0; 1916 ifp->if_flags &= ~IFF_OACTIVE; 1917 } 1918 } 1919 1920 if (isr & ISR_HIBERR) { 1921 int want_init = 0; 1922 1923 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1924 1925 #define PRINTERR(bit, str) \ 1926 do { \ 1927 if ((isr & (bit)) != 0) { \ 1928 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1929 printf("%s: %s\n", \ 1930 device_xname(sc->sc_dev), str); \ 1931 want_init = 1; \ 1932 } \ 1933 } while (/*CONSTCOND*/0) 1934 1935 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1936 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1937 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1938 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1939 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1940 /* 1941 * Ignore: 1942 * Tx reset complete 1943 * Rx reset complete 1944 */ 1945 if (want_init) 1946 (void) sipcom_init(ifp); 1947 #undef PRINTERR 1948 } 1949 } 1950 1951 /* Re-enable interrupts. */ 1952 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1953 1954 /* Try to get more packets going. */ 1955 sipcom_start(ifp); 1956 1957 return (handled); 1958 } 1959 1960 /* 1961 * sip_txintr: 1962 * 1963 * Helper; handle transmit interrupts. 1964 */ 1965 static void 1966 sipcom_txintr(struct sip_softc *sc) 1967 { 1968 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1969 struct sip_txsoft *txs; 1970 u_int32_t cmdsts; 1971 1972 if (sc->sc_paused == 0) 1973 ifp->if_flags &= ~IFF_OACTIVE; 1974 1975 /* 1976 * Go through our Tx list and free mbufs for those 1977 * frames which have been transmitted. 1978 */ 1979 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1980 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1981 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1982 1983 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 1984 if (cmdsts & CMDSTS_OWN) 1985 break; 1986 1987 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1988 1989 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1990 1991 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1992 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1993 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1994 m_freem(txs->txs_mbuf); 1995 txs->txs_mbuf = NULL; 1996 1997 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1998 1999 /* 2000 * Check for errors and collisions. 2001 */ 2002 if (cmdsts & 2003 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2004 ifp->if_oerrors++; 2005 if (cmdsts & CMDSTS_Tx_EC) 2006 ifp->if_collisions += 16; 2007 if (ifp->if_flags & IFF_DEBUG) { 2008 if (cmdsts & CMDSTS_Tx_ED) 2009 printf("%s: excessive deferral\n", 2010 device_xname(sc->sc_dev)); 2011 if (cmdsts & CMDSTS_Tx_EC) 2012 printf("%s: excessive collisions\n", 2013 device_xname(sc->sc_dev)); 2014 } 2015 } else { 2016 /* Packet was transmitted successfully. */ 2017 ifp->if_opackets++; 2018 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2019 } 2020 } 2021 2022 /* 2023 * If there are no more pending transmissions, cancel the watchdog 2024 * timer. 2025 */ 2026 if (txs == NULL) { 2027 ifp->if_timer = 0; 2028 sc->sc_txwin = 0; 2029 } 2030 } 2031 2032 /* 2033 * gsip_rxintr: 2034 * 2035 * Helper; handle receive interrupts on gigabit parts. 2036 */ 2037 static void 2038 gsip_rxintr(struct sip_softc *sc) 2039 { 2040 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2041 struct sip_rxsoft *rxs; 2042 struct mbuf *m; 2043 u_int32_t cmdsts, extsts; 2044 int i, len; 2045 2046 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2047 rxs = &sc->sc_rxsoft[i]; 2048 2049 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2050 2051 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2052 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2053 len = CMDSTS_SIZE(sc, cmdsts); 2054 2055 /* 2056 * NOTE: OWN is set if owned by _consumer_. We're the 2057 * consumer of the receive ring, so if the bit is clear, 2058 * we have processed all of the packets. 2059 */ 2060 if ((cmdsts & CMDSTS_OWN) == 0) { 2061 /* 2062 * We have processed all of the receive buffers. 2063 */ 2064 break; 2065 } 2066 2067 if (__predict_false(sc->sc_rxdiscard)) { 2068 sip_init_rxdesc(sc, i); 2069 if ((cmdsts & CMDSTS_MORE) == 0) { 2070 /* Reset our state. */ 2071 sc->sc_rxdiscard = 0; 2072 } 2073 continue; 2074 } 2075 2076 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2077 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2078 2079 m = rxs->rxs_mbuf; 2080 2081 /* 2082 * Add a new receive buffer to the ring. 2083 */ 2084 if (sipcom_add_rxbuf(sc, i) != 0) { 2085 /* 2086 * Failed, throw away what we've done so 2087 * far, and discard the rest of the packet. 2088 */ 2089 ifp->if_ierrors++; 2090 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2091 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2092 sip_init_rxdesc(sc, i); 2093 if (cmdsts & CMDSTS_MORE) 2094 sc->sc_rxdiscard = 1; 2095 if (sc->sc_rxhead != NULL) 2096 m_freem(sc->sc_rxhead); 2097 sip_rxchain_reset(sc); 2098 continue; 2099 } 2100 2101 sip_rxchain_link(sc, m); 2102 2103 m->m_len = len; 2104 2105 /* 2106 * If this is not the end of the packet, keep 2107 * looking. 2108 */ 2109 if (cmdsts & CMDSTS_MORE) { 2110 sc->sc_rxlen += len; 2111 continue; 2112 } 2113 2114 /* 2115 * Okay, we have the entire packet now. The chip includes 2116 * the FCS, so we need to trim it. 2117 */ 2118 m->m_len -= ETHER_CRC_LEN; 2119 2120 *sc->sc_rxtailp = NULL; 2121 len = m->m_len + sc->sc_rxlen; 2122 m = sc->sc_rxhead; 2123 2124 sip_rxchain_reset(sc); 2125 2126 /* 2127 * If an error occurred, update stats and drop the packet. 2128 */ 2129 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2130 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2131 ifp->if_ierrors++; 2132 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2133 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2134 /* Receive overrun handled elsewhere. */ 2135 printf("%s: receive descriptor error\n", 2136 device_xname(sc->sc_dev)); 2137 } 2138 #define PRINTERR(bit, str) \ 2139 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2140 (cmdsts & (bit)) != 0) \ 2141 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2142 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2143 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2144 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2145 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2146 #undef PRINTERR 2147 m_freem(m); 2148 continue; 2149 } 2150 2151 /* 2152 * If the packet is small enough to fit in a 2153 * single header mbuf, allocate one and copy 2154 * the data into it. This greatly reduces 2155 * memory consumption when we receive lots 2156 * of small packets. 2157 */ 2158 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2159 struct mbuf *nm; 2160 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2161 if (nm == NULL) { 2162 ifp->if_ierrors++; 2163 m_freem(m); 2164 continue; 2165 } 2166 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2167 nm->m_data += 2; 2168 nm->m_pkthdr.len = nm->m_len = len; 2169 m_copydata(m, 0, len, mtod(nm, void *)); 2170 m_freem(m); 2171 m = nm; 2172 } 2173 #ifndef __NO_STRICT_ALIGNMENT 2174 else { 2175 /* 2176 * The DP83820's receive buffers must be 4-byte 2177 * aligned. But this means that the data after 2178 * the Ethernet header is misaligned. To compensate, 2179 * we have artificially shortened the buffer size 2180 * in the descriptor, and we do an overlapping copy 2181 * of the data two bytes further in (in the first 2182 * buffer of the chain only). 2183 */ 2184 memmove(mtod(m, char *) + 2, mtod(m, void *), 2185 m->m_len); 2186 m->m_data += 2; 2187 } 2188 #endif /* ! __NO_STRICT_ALIGNMENT */ 2189 2190 /* 2191 * If VLANs are enabled, VLAN packets have been unwrapped 2192 * for us. Associate the tag with the packet. 2193 */ 2194 2195 /* 2196 * Again, byte swapping is tricky. Hardware provided 2197 * the tag in the network byte order, but extsts was 2198 * passed through le32toh() in the meantime. On a 2199 * big-endian machine, we need to swap it again. On a 2200 * little-endian machine, we need to convert from the 2201 * network to host byte order. This means that we must 2202 * swap it in any case, so unconditional swap instead 2203 * of htons() is used. 2204 */ 2205 if ((extsts & EXTSTS_VPKT) != 0) { 2206 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2207 continue); 2208 } 2209 2210 /* 2211 * Set the incoming checksum information for the 2212 * packet. 2213 */ 2214 if ((extsts & EXTSTS_IPPKT) != 0) { 2215 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2216 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2217 if (extsts & EXTSTS_Rx_IPERR) 2218 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2219 if (extsts & EXTSTS_TCPPKT) { 2220 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2221 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2222 if (extsts & EXTSTS_Rx_TCPERR) 2223 m->m_pkthdr.csum_flags |= 2224 M_CSUM_TCP_UDP_BAD; 2225 } else if (extsts & EXTSTS_UDPPKT) { 2226 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2227 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2228 if (extsts & EXTSTS_Rx_UDPERR) 2229 m->m_pkthdr.csum_flags |= 2230 M_CSUM_TCP_UDP_BAD; 2231 } 2232 } 2233 2234 ifp->if_ipackets++; 2235 m_set_rcvif(m, ifp); 2236 m->m_pkthdr.len = len; 2237 2238 /* 2239 * Pass this up to any BPF listeners, but only 2240 * pass if up the stack if it's for us. 2241 */ 2242 bpf_mtap(ifp, m); 2243 2244 /* Pass it on. */ 2245 if_percpuq_enqueue(ifp->if_percpuq, m); 2246 } 2247 2248 /* Update the receive pointer. */ 2249 sc->sc_rxptr = i; 2250 } 2251 2252 /* 2253 * sip_rxintr: 2254 * 2255 * Helper; handle receive interrupts on 10/100 parts. 2256 */ 2257 static void 2258 sip_rxintr(struct sip_softc *sc) 2259 { 2260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2261 struct sip_rxsoft *rxs; 2262 struct mbuf *m; 2263 u_int32_t cmdsts; 2264 int i, len; 2265 2266 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2267 rxs = &sc->sc_rxsoft[i]; 2268 2269 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2270 2271 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2272 2273 /* 2274 * NOTE: OWN is set if owned by _consumer_. We're the 2275 * consumer of the receive ring, so if the bit is clear, 2276 * we have processed all of the packets. 2277 */ 2278 if ((cmdsts & CMDSTS_OWN) == 0) { 2279 /* 2280 * We have processed all of the receive buffers. 2281 */ 2282 break; 2283 } 2284 2285 /* 2286 * If any collisions were seen on the wire, count one. 2287 */ 2288 if (cmdsts & CMDSTS_Rx_COL) 2289 ifp->if_collisions++; 2290 2291 /* 2292 * If an error occurred, update stats, clear the status 2293 * word, and leave the packet buffer in place. It will 2294 * simply be reused the next time the ring comes around. 2295 */ 2296 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2297 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2298 ifp->if_ierrors++; 2299 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2300 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2301 /* Receive overrun handled elsewhere. */ 2302 printf("%s: receive descriptor error\n", 2303 device_xname(sc->sc_dev)); 2304 } 2305 #define PRINTERR(bit, str) \ 2306 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2307 (cmdsts & (bit)) != 0) \ 2308 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2309 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2310 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2311 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2312 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2313 #undef PRINTERR 2314 sip_init_rxdesc(sc, i); 2315 continue; 2316 } 2317 2318 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2319 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2320 2321 /* 2322 * No errors; receive the packet. Note, the SiS 900 2323 * includes the CRC with every packet. 2324 */ 2325 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2326 2327 #ifdef __NO_STRICT_ALIGNMENT 2328 /* 2329 * If the packet is small enough to fit in a 2330 * single header mbuf, allocate one and copy 2331 * the data into it. This greatly reduces 2332 * memory consumption when we receive lots 2333 * of small packets. 2334 * 2335 * Otherwise, we add a new buffer to the receive 2336 * chain. If this fails, we drop the packet and 2337 * recycle the old buffer. 2338 */ 2339 if (sip_copy_small != 0 && len <= MHLEN) { 2340 MGETHDR(m, M_DONTWAIT, MT_DATA); 2341 if (m == NULL) 2342 goto dropit; 2343 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2344 memcpy(mtod(m, void *), 2345 mtod(rxs->rxs_mbuf, void *), len); 2346 sip_init_rxdesc(sc, i); 2347 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2348 rxs->rxs_dmamap->dm_mapsize, 2349 BUS_DMASYNC_PREREAD); 2350 } else { 2351 m = rxs->rxs_mbuf; 2352 if (sipcom_add_rxbuf(sc, i) != 0) { 2353 dropit: 2354 ifp->if_ierrors++; 2355 sip_init_rxdesc(sc, i); 2356 bus_dmamap_sync(sc->sc_dmat, 2357 rxs->rxs_dmamap, 0, 2358 rxs->rxs_dmamap->dm_mapsize, 2359 BUS_DMASYNC_PREREAD); 2360 continue; 2361 } 2362 } 2363 #else 2364 /* 2365 * The SiS 900's receive buffers must be 4-byte aligned. 2366 * But this means that the data after the Ethernet header 2367 * is misaligned. We must allocate a new buffer and 2368 * copy the data, shifted forward 2 bytes. 2369 */ 2370 MGETHDR(m, M_DONTWAIT, MT_DATA); 2371 if (m == NULL) { 2372 dropit: 2373 ifp->if_ierrors++; 2374 sip_init_rxdesc(sc, i); 2375 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2376 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2377 continue; 2378 } 2379 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2380 if (len > (MHLEN - 2)) { 2381 MCLGET(m, M_DONTWAIT); 2382 if ((m->m_flags & M_EXT) == 0) { 2383 m_freem(m); 2384 goto dropit; 2385 } 2386 } 2387 m->m_data += 2; 2388 2389 /* 2390 * Note that we use clusters for incoming frames, so the 2391 * buffer is virtually contiguous. 2392 */ 2393 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2394 2395 /* Allow the receive descriptor to continue using its mbuf. */ 2396 sip_init_rxdesc(sc, i); 2397 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2398 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2399 #endif /* __NO_STRICT_ALIGNMENT */ 2400 2401 ifp->if_ipackets++; 2402 m_set_rcvif(m, ifp); 2403 m->m_pkthdr.len = m->m_len = len; 2404 2405 /* 2406 * Pass this up to any BPF listeners, but only 2407 * pass if up the stack if it's for us. 2408 */ 2409 bpf_mtap(ifp, m); 2410 2411 /* Pass it on. */ 2412 if_percpuq_enqueue(ifp->if_percpuq, m); 2413 } 2414 2415 /* Update the receive pointer. */ 2416 sc->sc_rxptr = i; 2417 } 2418 2419 /* 2420 * sip_tick: 2421 * 2422 * One second timer, used to tick the MII. 2423 */ 2424 static void 2425 sipcom_tick(void *arg) 2426 { 2427 struct sip_softc *sc = arg; 2428 int s; 2429 2430 s = splnet(); 2431 #ifdef SIP_EVENT_COUNTERS 2432 if (sc->sc_gigabit) { 2433 /* Read PAUSE related counts from MIB registers. */ 2434 sc->sc_ev_rxpause.ev_count += 2435 bus_space_read_4(sc->sc_st, sc->sc_sh, 2436 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2437 sc->sc_ev_txpause.ev_count += 2438 bus_space_read_4(sc->sc_st, sc->sc_sh, 2439 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2440 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2441 } 2442 #endif /* SIP_EVENT_COUNTERS */ 2443 mii_tick(&sc->sc_mii); 2444 splx(s); 2445 2446 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2447 } 2448 2449 /* 2450 * sip_reset: 2451 * 2452 * Perform a soft reset on the SiS 900. 2453 */ 2454 static bool 2455 sipcom_reset(struct sip_softc *sc) 2456 { 2457 bus_space_tag_t st = sc->sc_st; 2458 bus_space_handle_t sh = sc->sc_sh; 2459 int i; 2460 2461 bus_space_write_4(st, sh, SIP_IER, 0); 2462 bus_space_write_4(st, sh, SIP_IMR, 0); 2463 bus_space_write_4(st, sh, SIP_RFCR, 0); 2464 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2465 2466 for (i = 0; i < SIP_TIMEOUT; i++) { 2467 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2468 break; 2469 delay(2); 2470 } 2471 2472 if (i == SIP_TIMEOUT) { 2473 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 2474 return false; 2475 } 2476 2477 delay(1000); 2478 2479 if (sc->sc_gigabit) { 2480 /* 2481 * Set the general purpose I/O bits. Do it here in case we 2482 * need to have GPIO set up to talk to the media interface. 2483 */ 2484 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2485 delay(1000); 2486 } 2487 return true; 2488 } 2489 2490 static void 2491 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2492 { 2493 u_int32_t reg; 2494 bus_space_tag_t st = sc->sc_st; 2495 bus_space_handle_t sh = sc->sc_sh; 2496 /* 2497 * Initialize the VLAN/IP receive control register. 2498 * We enable checksum computation on all incoming 2499 * packets, and do not reject packets w/ bad checksums. 2500 */ 2501 reg = 0; 2502 if (capenable & 2503 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2504 reg |= VRCR_IPEN; 2505 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2506 reg |= VRCR_VTDEN|VRCR_VTREN; 2507 bus_space_write_4(st, sh, SIP_VRCR, reg); 2508 2509 /* 2510 * Initialize the VLAN/IP transmit control register. 2511 * We enable outgoing checksum computation on a 2512 * per-packet basis. 2513 */ 2514 reg = 0; 2515 if (capenable & 2516 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2517 reg |= VTCR_PPCHK; 2518 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2519 reg |= VTCR_VPPTI; 2520 bus_space_write_4(st, sh, SIP_VTCR, reg); 2521 2522 /* 2523 * If we're using VLANs, initialize the VLAN data register. 2524 * To understand why we bswap the VLAN Ethertype, see section 2525 * 4.2.36 of the DP83820 manual. 2526 */ 2527 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2528 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2529 } 2530 2531 /* 2532 * sip_init: [ ifnet interface function ] 2533 * 2534 * Initialize the interface. Must be called at splnet(). 2535 */ 2536 static int 2537 sipcom_init(struct ifnet *ifp) 2538 { 2539 struct sip_softc *sc = ifp->if_softc; 2540 bus_space_tag_t st = sc->sc_st; 2541 bus_space_handle_t sh = sc->sc_sh; 2542 struct sip_txsoft *txs; 2543 struct sip_rxsoft *rxs; 2544 struct sip_desc *sipd; 2545 int i, error = 0; 2546 2547 if (device_is_active(sc->sc_dev)) { 2548 /* 2549 * Cancel any pending I/O. 2550 */ 2551 sipcom_stop(ifp, 0); 2552 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2553 !device_is_active(sc->sc_dev)) 2554 return 0; 2555 2556 /* 2557 * Reset the chip to a known state. 2558 */ 2559 if (!sipcom_reset(sc)) 2560 return EBUSY; 2561 2562 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2563 /* 2564 * DP83815 manual, page 78: 2565 * 4.4 Recommended Registers Configuration 2566 * For optimum performance of the DP83815, version noted 2567 * as DP83815CVNG (SRR = 203h), the listed register 2568 * modifications must be followed in sequence... 2569 * 2570 * It's not clear if this should be 302h or 203h because that 2571 * chip name is listed as SRR 302h in the description of the 2572 * SRR register. However, my revision 302h DP83815 on the 2573 * Netgear FA311 purchased in 02/2001 needs these settings 2574 * to avoid tons of errors in AcceptPerfectMatch (non- 2575 * IFF_PROMISC) mode. I do not know if other revisions need 2576 * this set or not. [briggs -- 09 March 2001] 2577 * 2578 * Note that only the low-order 12 bits of 0xe4 are documented 2579 * and that this sets reserved bits in that register. 2580 */ 2581 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2582 2583 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2584 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2585 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2586 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2587 2588 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2589 } 2590 2591 /* 2592 * Initialize the transmit descriptor ring. 2593 */ 2594 for (i = 0; i < sc->sc_ntxdesc; i++) { 2595 sipd = &sc->sc_txdescs[i]; 2596 memset(sipd, 0, sizeof(struct sip_desc)); 2597 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2598 } 2599 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2600 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2601 sc->sc_txfree = sc->sc_ntxdesc; 2602 sc->sc_txnext = 0; 2603 sc->sc_txwin = 0; 2604 2605 /* 2606 * Initialize the transmit job descriptors. 2607 */ 2608 SIMPLEQ_INIT(&sc->sc_txfreeq); 2609 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2610 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2611 txs = &sc->sc_txsoft[i]; 2612 txs->txs_mbuf = NULL; 2613 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2614 } 2615 2616 /* 2617 * Initialize the receive descriptor and receive job 2618 * descriptor rings. 2619 */ 2620 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2621 rxs = &sc->sc_rxsoft[i]; 2622 if (rxs->rxs_mbuf == NULL) { 2623 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2624 printf("%s: unable to allocate or map rx " 2625 "buffer %d, error = %d\n", 2626 device_xname(sc->sc_dev), i, error); 2627 /* 2628 * XXX Should attempt to run with fewer receive 2629 * XXX buffers instead of just failing. 2630 */ 2631 sipcom_rxdrain(sc); 2632 goto out; 2633 } 2634 } else 2635 sip_init_rxdesc(sc, i); 2636 } 2637 sc->sc_rxptr = 0; 2638 sc->sc_rxdiscard = 0; 2639 sip_rxchain_reset(sc); 2640 2641 /* 2642 * Set the configuration register; it's already initialized 2643 * in sip_attach(). 2644 */ 2645 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2646 2647 /* 2648 * Initialize the prototype TXCFG register. 2649 */ 2650 if (sc->sc_gigabit) { 2651 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2652 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2653 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2654 SIP_SIS900_REV(sc, SIS_REV_960) || 2655 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2656 (sc->sc_cfg & CFG_EDBMASTEN)) { 2657 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2658 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2659 } else { 2660 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2661 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2662 } 2663 2664 sc->sc_txcfg |= TXCFG_ATP | 2665 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2666 sc->sc_tx_drain_thresh; 2667 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2668 2669 /* 2670 * Initialize the receive drain threshold if we have never 2671 * done so. 2672 */ 2673 if (sc->sc_rx_drain_thresh == 0) { 2674 /* 2675 * XXX This value should be tuned. This is set to the 2676 * maximum of 248 bytes, and we may be able to improve 2677 * performance by decreasing it (although we should never 2678 * set this value lower than 2; 14 bytes are required to 2679 * filter the packet). 2680 */ 2681 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2682 } 2683 2684 /* 2685 * Initialize the prototype RXCFG register. 2686 */ 2687 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2688 /* 2689 * Accept long packets (including FCS) so we can handle 2690 * 802.1q-tagged frames and jumbo frames properly. 2691 */ 2692 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2693 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2694 sc->sc_rxcfg |= RXCFG_ALP; 2695 2696 /* 2697 * Checksum offloading is disabled if the user selects an MTU 2698 * larger than 8109. (FreeBSD says 8152, but there is emperical 2699 * evidence that >8109 does not work on some boards, such as the 2700 * Planex GN-1000TE). 2701 */ 2702 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2703 (ifp->if_capenable & 2704 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2705 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2706 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2707 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2708 "disabled.\n", device_xname(sc->sc_dev)); 2709 ifp->if_capenable &= 2710 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2711 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2712 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2713 ifp->if_csum_flags_tx = 0; 2714 ifp->if_csum_flags_rx = 0; 2715 } 2716 2717 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2718 2719 if (sc->sc_gigabit) 2720 sipcom_dp83820_init(sc, ifp->if_capenable); 2721 2722 /* 2723 * Give the transmit and receive rings to the chip. 2724 */ 2725 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2726 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2727 2728 /* 2729 * Initialize the interrupt mask. 2730 */ 2731 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2732 sc->sc_bits.b_isr_sserr | 2733 sc->sc_bits.b_isr_rmabt | 2734 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2735 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2736 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2737 2738 /* Set up the receive filter. */ 2739 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2740 2741 /* 2742 * Tune sc_rx_flow_thresh. 2743 * XXX "More than 8KB" is too short for jumbo frames. 2744 * XXX TODO: Threshold value should be user-settable. 2745 */ 2746 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2747 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2748 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2749 2750 /* 2751 * Set the current media. Do this after initializing the prototype 2752 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2753 * control. 2754 */ 2755 if ((error = ether_mediachange(ifp)) != 0) 2756 goto out; 2757 2758 /* 2759 * Set the interrupt hold-off timer to 100us. 2760 */ 2761 if (sc->sc_gigabit) 2762 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2763 2764 /* 2765 * Enable interrupts. 2766 */ 2767 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2768 2769 /* 2770 * Start the transmit and receive processes. 2771 */ 2772 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2773 2774 /* 2775 * Start the one second MII clock. 2776 */ 2777 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2778 2779 /* 2780 * ...all done! 2781 */ 2782 ifp->if_flags |= IFF_RUNNING; 2783 ifp->if_flags &= ~IFF_OACTIVE; 2784 sc->sc_if_flags = ifp->if_flags; 2785 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2786 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2787 sc->sc_prev.if_capenable = ifp->if_capenable; 2788 2789 out: 2790 if (error) 2791 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2792 return (error); 2793 } 2794 2795 /* 2796 * sip_drain: 2797 * 2798 * Drain the receive queue. 2799 */ 2800 static void 2801 sipcom_rxdrain(struct sip_softc *sc) 2802 { 2803 struct sip_rxsoft *rxs; 2804 int i; 2805 2806 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2807 rxs = &sc->sc_rxsoft[i]; 2808 if (rxs->rxs_mbuf != NULL) { 2809 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2810 m_freem(rxs->rxs_mbuf); 2811 rxs->rxs_mbuf = NULL; 2812 } 2813 } 2814 } 2815 2816 /* 2817 * sip_stop: [ ifnet interface function ] 2818 * 2819 * Stop transmission on the interface. 2820 */ 2821 static void 2822 sipcom_stop(struct ifnet *ifp, int disable) 2823 { 2824 struct sip_softc *sc = ifp->if_softc; 2825 bus_space_tag_t st = sc->sc_st; 2826 bus_space_handle_t sh = sc->sc_sh; 2827 struct sip_txsoft *txs; 2828 u_int32_t cmdsts = 0; /* DEBUG */ 2829 2830 /* 2831 * Stop the one second clock. 2832 */ 2833 callout_stop(&sc->sc_tick_ch); 2834 2835 /* Down the MII. */ 2836 mii_down(&sc->sc_mii); 2837 2838 if (device_is_active(sc->sc_dev)) { 2839 /* 2840 * Disable interrupts. 2841 */ 2842 bus_space_write_4(st, sh, SIP_IER, 0); 2843 2844 /* 2845 * Stop receiver and transmitter. 2846 */ 2847 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2848 } 2849 2850 /* 2851 * Release any queued transmit buffers. 2852 */ 2853 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2854 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2855 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2856 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2857 CMDSTS_INTR) == 0) 2858 printf("%s: sip_stop: last descriptor does not " 2859 "have INTR bit set\n", device_xname(sc->sc_dev)); 2860 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2861 #ifdef DIAGNOSTIC 2862 if (txs->txs_mbuf == NULL) { 2863 printf("%s: dirty txsoft with no mbuf chain\n", 2864 device_xname(sc->sc_dev)); 2865 panic("sip_stop"); 2866 } 2867 #endif 2868 cmdsts |= /* DEBUG */ 2869 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2870 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2871 m_freem(txs->txs_mbuf); 2872 txs->txs_mbuf = NULL; 2873 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2874 } 2875 2876 /* 2877 * Mark the interface down and cancel the watchdog timer. 2878 */ 2879 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2880 ifp->if_timer = 0; 2881 2882 if (disable) 2883 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2884 2885 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2886 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2887 printf("%s: sip_stop: no INTR bits set in dirty tx " 2888 "descriptors\n", device_xname(sc->sc_dev)); 2889 } 2890 2891 /* 2892 * sip_read_eeprom: 2893 * 2894 * Read data from the serial EEPROM. 2895 */ 2896 static void 2897 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2898 u_int16_t *data) 2899 { 2900 bus_space_tag_t st = sc->sc_st; 2901 bus_space_handle_t sh = sc->sc_sh; 2902 u_int16_t reg; 2903 int i, x; 2904 2905 for (i = 0; i < wordcnt; i++) { 2906 /* Send CHIP SELECT. */ 2907 reg = EROMAR_EECS; 2908 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2909 2910 /* Shift in the READ opcode. */ 2911 for (x = 3; x > 0; x--) { 2912 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2913 reg |= EROMAR_EEDI; 2914 else 2915 reg &= ~EROMAR_EEDI; 2916 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2917 bus_space_write_4(st, sh, SIP_EROMAR, 2918 reg | EROMAR_EESK); 2919 delay(4); 2920 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2921 delay(4); 2922 } 2923 2924 /* Shift in address. */ 2925 for (x = 6; x > 0; x--) { 2926 if ((word + i) & (1 << (x - 1))) 2927 reg |= EROMAR_EEDI; 2928 else 2929 reg &= ~EROMAR_EEDI; 2930 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2931 bus_space_write_4(st, sh, SIP_EROMAR, 2932 reg | EROMAR_EESK); 2933 delay(4); 2934 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2935 delay(4); 2936 } 2937 2938 /* Shift out data. */ 2939 reg = EROMAR_EECS; 2940 data[i] = 0; 2941 for (x = 16; x > 0; x--) { 2942 bus_space_write_4(st, sh, SIP_EROMAR, 2943 reg | EROMAR_EESK); 2944 delay(4); 2945 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2946 data[i] |= (1 << (x - 1)); 2947 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2948 delay(4); 2949 } 2950 2951 /* Clear CHIP SELECT. */ 2952 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2953 delay(4); 2954 } 2955 } 2956 2957 /* 2958 * sipcom_add_rxbuf: 2959 * 2960 * Add a receive buffer to the indicated descriptor. 2961 */ 2962 static int 2963 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2964 { 2965 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2966 struct mbuf *m; 2967 int error; 2968 2969 MGETHDR(m, M_DONTWAIT, MT_DATA); 2970 if (m == NULL) 2971 return (ENOBUFS); 2972 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2973 2974 MCLGET(m, M_DONTWAIT); 2975 if ((m->m_flags & M_EXT) == 0) { 2976 m_freem(m); 2977 return (ENOBUFS); 2978 } 2979 2980 /* XXX I don't believe this is necessary. --dyoung */ 2981 if (sc->sc_gigabit) 2982 m->m_len = sc->sc_parm->p_rxbuf_len; 2983 2984 if (rxs->rxs_mbuf != NULL) 2985 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2986 2987 rxs->rxs_mbuf = m; 2988 2989 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2990 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2991 BUS_DMA_READ|BUS_DMA_NOWAIT); 2992 if (error) { 2993 printf("%s: can't load rx DMA map %d, error = %d\n", 2994 device_xname(sc->sc_dev), idx, error); 2995 panic("%s", __func__); /* XXX */ 2996 } 2997 2998 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2999 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3000 3001 sip_init_rxdesc(sc, idx); 3002 3003 return (0); 3004 } 3005 3006 /* 3007 * sip_sis900_set_filter: 3008 * 3009 * Set up the receive filter. 3010 */ 3011 static void 3012 sipcom_sis900_set_filter(struct sip_softc *sc) 3013 { 3014 bus_space_tag_t st = sc->sc_st; 3015 bus_space_handle_t sh = sc->sc_sh; 3016 struct ethercom *ec = &sc->sc_ethercom; 3017 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3018 struct ether_multi *enm; 3019 const u_int8_t *cp; 3020 struct ether_multistep step; 3021 u_int32_t crc, mchash[16]; 3022 3023 /* 3024 * Initialize the prototype RFCR. 3025 */ 3026 sc->sc_rfcr = RFCR_RFEN; 3027 if (ifp->if_flags & IFF_BROADCAST) 3028 sc->sc_rfcr |= RFCR_AAB; 3029 if (ifp->if_flags & IFF_PROMISC) { 3030 sc->sc_rfcr |= RFCR_AAP; 3031 goto allmulti; 3032 } 3033 3034 /* 3035 * Set up the multicast address filter by passing all multicast 3036 * addresses through a CRC generator, and then using the high-order 3037 * 6 bits as an index into the 128 bit multicast hash table (only 3038 * the lower 16 bits of each 32 bit multicast hash register are 3039 * valid). The high order bits select the register, while the 3040 * rest of the bits select the bit within the register. 3041 */ 3042 3043 memset(mchash, 0, sizeof(mchash)); 3044 3045 /* 3046 * SiS900 (at least SiS963) requires us to register the address of 3047 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3048 */ 3049 crc = 0x0ed423f9; 3050 3051 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3052 SIP_SIS900_REV(sc, SIS_REV_960) || 3053 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3054 /* Just want the 8 most significant bits. */ 3055 crc >>= 24; 3056 } else { 3057 /* Just want the 7 most significant bits. */ 3058 crc >>= 25; 3059 } 3060 3061 /* Set the corresponding bit in the hash table. */ 3062 mchash[crc >> 4] |= 1 << (crc & 0xf); 3063 3064 ETHER_FIRST_MULTI(step, ec, enm); 3065 while (enm != NULL) { 3066 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3067 /* 3068 * We must listen to a range of multicast addresses. 3069 * For now, just accept all multicasts, rather than 3070 * trying to set only those filter bits needed to match 3071 * the range. (At this time, the only use of address 3072 * ranges is for IP multicast routing, for which the 3073 * range is big enough to require all bits set.) 3074 */ 3075 goto allmulti; 3076 } 3077 3078 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3079 3080 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3081 SIP_SIS900_REV(sc, SIS_REV_960) || 3082 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3083 /* Just want the 8 most significant bits. */ 3084 crc >>= 24; 3085 } else { 3086 /* Just want the 7 most significant bits. */ 3087 crc >>= 25; 3088 } 3089 3090 /* Set the corresponding bit in the hash table. */ 3091 mchash[crc >> 4] |= 1 << (crc & 0xf); 3092 3093 ETHER_NEXT_MULTI(step, enm); 3094 } 3095 3096 ifp->if_flags &= ~IFF_ALLMULTI; 3097 goto setit; 3098 3099 allmulti: 3100 ifp->if_flags |= IFF_ALLMULTI; 3101 sc->sc_rfcr |= RFCR_AAM; 3102 3103 setit: 3104 #define FILTER_EMIT(addr, data) \ 3105 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3106 delay(1); \ 3107 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3108 delay(1) 3109 3110 /* 3111 * Disable receive filter, and program the node address. 3112 */ 3113 cp = CLLADDR(ifp->if_sadl); 3114 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3115 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3116 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3117 3118 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3119 /* 3120 * Program the multicast hash table. 3121 */ 3122 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3123 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3124 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3125 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3126 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3127 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3128 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3129 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3130 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3131 SIP_SIS900_REV(sc, SIS_REV_960) || 3132 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3133 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3134 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3135 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3136 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3137 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3138 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3139 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3140 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3141 } 3142 } 3143 #undef FILTER_EMIT 3144 3145 /* 3146 * Re-enable the receiver filter. 3147 */ 3148 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3149 } 3150 3151 /* 3152 * sip_dp83815_set_filter: 3153 * 3154 * Set up the receive filter. 3155 */ 3156 static void 3157 sipcom_dp83815_set_filter(struct sip_softc *sc) 3158 { 3159 bus_space_tag_t st = sc->sc_st; 3160 bus_space_handle_t sh = sc->sc_sh; 3161 struct ethercom *ec = &sc->sc_ethercom; 3162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3163 struct ether_multi *enm; 3164 const u_int8_t *cp; 3165 struct ether_multistep step; 3166 u_int32_t crc, hash, slot, bit; 3167 #define MCHASH_NWORDS_83820 128 3168 #define MCHASH_NWORDS_83815 32 3169 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3170 u_int16_t mchash[MCHASH_NWORDS]; 3171 int i; 3172 3173 /* 3174 * Initialize the prototype RFCR. 3175 * Enable the receive filter, and accept on 3176 * Perfect (destination address) Match 3177 * If IFF_BROADCAST, also accept all broadcast packets. 3178 * If IFF_PROMISC, accept all unicast packets (and later, set 3179 * IFF_ALLMULTI and accept all multicast, too). 3180 */ 3181 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3182 if (ifp->if_flags & IFF_BROADCAST) 3183 sc->sc_rfcr |= RFCR_AAB; 3184 if (ifp->if_flags & IFF_PROMISC) { 3185 sc->sc_rfcr |= RFCR_AAP; 3186 goto allmulti; 3187 } 3188 3189 /* 3190 * Set up the DP83820/DP83815 multicast address filter by 3191 * passing all multicast addresses through a CRC generator, 3192 * and then using the high-order 11/9 bits as an index into 3193 * the 2048/512 bit multicast hash table. The high-order 3194 * 7/5 bits select the slot, while the low-order 4 bits 3195 * select the bit within the slot. Note that only the low 3196 * 16-bits of each filter word are used, and there are 3197 * 128/32 filter words. 3198 */ 3199 3200 memset(mchash, 0, sizeof(mchash)); 3201 3202 ifp->if_flags &= ~IFF_ALLMULTI; 3203 ETHER_FIRST_MULTI(step, ec, enm); 3204 if (enm == NULL) 3205 goto setit; 3206 while (enm != NULL) { 3207 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3208 /* 3209 * We must listen to a range of multicast addresses. 3210 * For now, just accept all multicasts, rather than 3211 * trying to set only those filter bits needed to match 3212 * the range. (At this time, the only use of address 3213 * ranges is for IP multicast routing, for which the 3214 * range is big enough to require all bits set.) 3215 */ 3216 goto allmulti; 3217 } 3218 3219 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3220 3221 if (sc->sc_gigabit) { 3222 /* Just want the 11 most significant bits. */ 3223 hash = crc >> 21; 3224 } else { 3225 /* Just want the 9 most significant bits. */ 3226 hash = crc >> 23; 3227 } 3228 3229 slot = hash >> 4; 3230 bit = hash & 0xf; 3231 3232 /* Set the corresponding bit in the hash table. */ 3233 mchash[slot] |= 1 << bit; 3234 3235 ETHER_NEXT_MULTI(step, enm); 3236 } 3237 sc->sc_rfcr |= RFCR_MHEN; 3238 goto setit; 3239 3240 allmulti: 3241 ifp->if_flags |= IFF_ALLMULTI; 3242 sc->sc_rfcr |= RFCR_AAM; 3243 3244 setit: 3245 #define FILTER_EMIT(addr, data) \ 3246 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3247 delay(1); \ 3248 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3249 delay(1) 3250 3251 /* 3252 * Disable receive filter, and program the node address. 3253 */ 3254 cp = CLLADDR(ifp->if_sadl); 3255 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3256 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3257 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3258 3259 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3260 int nwords = 3261 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3262 /* 3263 * Program the multicast hash table. 3264 */ 3265 for (i = 0; i < nwords; i++) { 3266 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3267 } 3268 } 3269 #undef FILTER_EMIT 3270 #undef MCHASH_NWORDS 3271 #undef MCHASH_NWORDS_83815 3272 #undef MCHASH_NWORDS_83820 3273 3274 /* 3275 * Re-enable the receiver filter. 3276 */ 3277 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3278 } 3279 3280 /* 3281 * sip_dp83820_mii_readreg: [mii interface function] 3282 * 3283 * Read a PHY register on the MII of the DP83820. 3284 */ 3285 static int 3286 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3287 { 3288 struct sip_softc *sc = device_private(self); 3289 3290 if (sc->sc_cfg & CFG_TBI_EN) { 3291 bus_addr_t tbireg; 3292 int rv; 3293 3294 if (phy != 0) 3295 return (0); 3296 3297 switch (reg) { 3298 case MII_BMCR: tbireg = SIP_TBICR; break; 3299 case MII_BMSR: tbireg = SIP_TBISR; break; 3300 case MII_ANAR: tbireg = SIP_TANAR; break; 3301 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3302 case MII_ANER: tbireg = SIP_TANER; break; 3303 case MII_EXTSR: 3304 /* 3305 * Don't even bother reading the TESR register. 3306 * The manual documents that the device has 3307 * 1000baseX full/half capability, but the 3308 * register itself seems read back 0 on some 3309 * boards. Just hard-code the result. 3310 */ 3311 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3312 3313 default: 3314 return (0); 3315 } 3316 3317 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3318 if (tbireg == SIP_TBISR) { 3319 /* LINK and ACOMP are switched! */ 3320 int val = rv; 3321 3322 rv = 0; 3323 if (val & TBISR_MR_LINK_STATUS) 3324 rv |= BMSR_LINK; 3325 if (val & TBISR_MR_AN_COMPLETE) 3326 rv |= BMSR_ACOMP; 3327 3328 /* 3329 * The manual claims this register reads back 0 3330 * on hard and soft reset. But we want to let 3331 * the gentbi driver know that we support auto- 3332 * negotiation, so hard-code this bit in the 3333 * result. 3334 */ 3335 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3336 } 3337 3338 return (rv); 3339 } 3340 3341 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3342 } 3343 3344 /* 3345 * sip_dp83820_mii_writereg: [mii interface function] 3346 * 3347 * Write a PHY register on the MII of the DP83820. 3348 */ 3349 static void 3350 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3351 { 3352 struct sip_softc *sc = device_private(self); 3353 3354 if (sc->sc_cfg & CFG_TBI_EN) { 3355 bus_addr_t tbireg; 3356 3357 if (phy != 0) 3358 return; 3359 3360 switch (reg) { 3361 case MII_BMCR: tbireg = SIP_TBICR; break; 3362 case MII_ANAR: tbireg = SIP_TANAR; break; 3363 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3364 default: 3365 return; 3366 } 3367 3368 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3369 return; 3370 } 3371 3372 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3373 } 3374 3375 /* 3376 * sip_dp83820_mii_statchg: [mii interface function] 3377 * 3378 * Callback from MII layer when media changes. 3379 */ 3380 static void 3381 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3382 { 3383 struct sip_softc *sc = ifp->if_softc; 3384 struct mii_data *mii = &sc->sc_mii; 3385 u_int32_t cfg, pcr; 3386 3387 /* 3388 * Get flow control negotiation result. 3389 */ 3390 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3391 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3392 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3393 mii->mii_media_active &= ~IFM_ETH_FMASK; 3394 } 3395 3396 /* 3397 * Update TXCFG for full-duplex operation. 3398 */ 3399 if ((mii->mii_media_active & IFM_FDX) != 0) 3400 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3401 else 3402 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3403 3404 /* 3405 * Update RXCFG for full-duplex or loopback. 3406 */ 3407 if ((mii->mii_media_active & IFM_FDX) != 0 || 3408 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3409 sc->sc_rxcfg |= RXCFG_ATX; 3410 else 3411 sc->sc_rxcfg &= ~RXCFG_ATX; 3412 3413 /* 3414 * Update CFG for MII/GMII. 3415 */ 3416 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3417 cfg = sc->sc_cfg | CFG_MODE_1000; 3418 else 3419 cfg = sc->sc_cfg; 3420 3421 /* 3422 * 802.3x flow control. 3423 */ 3424 pcr = 0; 3425 if (sc->sc_flowflags & IFM_FLOW) { 3426 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3427 pcr |= sc->sc_rx_flow_thresh; 3428 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3429 pcr |= PCR_PSEN | PCR_PS_MCAST; 3430 } 3431 3432 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3433 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3434 sc->sc_txcfg); 3435 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3436 sc->sc_rxcfg); 3437 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3438 } 3439 3440 /* 3441 * sip_mii_bitbang_read: [mii bit-bang interface function] 3442 * 3443 * Read the MII serial port for the MII bit-bang module. 3444 */ 3445 static u_int32_t 3446 sipcom_mii_bitbang_read(device_t self) 3447 { 3448 struct sip_softc *sc = device_private(self); 3449 3450 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3451 } 3452 3453 /* 3454 * sip_mii_bitbang_write: [mii big-bang interface function] 3455 * 3456 * Write the MII serial port for the MII bit-bang module. 3457 */ 3458 static void 3459 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3460 { 3461 struct sip_softc *sc = device_private(self); 3462 3463 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3464 } 3465 3466 /* 3467 * sip_sis900_mii_readreg: [mii interface function] 3468 * 3469 * Read a PHY register on the MII. 3470 */ 3471 static int 3472 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3473 { 3474 struct sip_softc *sc = device_private(self); 3475 u_int32_t enphy; 3476 3477 /* 3478 * The PHY of recent SiS chipsets is accessed through bitbang 3479 * operations. 3480 */ 3481 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3482 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3483 phy, reg); 3484 3485 #ifndef SIS900_MII_RESTRICT 3486 /* 3487 * The SiS 900 has only an internal PHY on the MII. Only allow 3488 * MII address 0. 3489 */ 3490 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3491 return (0); 3492 #endif 3493 3494 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3495 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3496 ENPHY_RWCMD | ENPHY_ACCESS); 3497 do { 3498 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3499 } while (enphy & ENPHY_ACCESS); 3500 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3501 } 3502 3503 /* 3504 * sip_sis900_mii_writereg: [mii interface function] 3505 * 3506 * Write a PHY register on the MII. 3507 */ 3508 static void 3509 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3510 { 3511 struct sip_softc *sc = device_private(self); 3512 u_int32_t enphy; 3513 3514 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3515 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3516 phy, reg, val); 3517 return; 3518 } 3519 3520 #ifndef SIS900_MII_RESTRICT 3521 /* 3522 * The SiS 900 has only an internal PHY on the MII. Only allow 3523 * MII address 0. 3524 */ 3525 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3526 return; 3527 #endif 3528 3529 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3530 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3531 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3532 do { 3533 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3534 } while (enphy & ENPHY_ACCESS); 3535 } 3536 3537 /* 3538 * sip_sis900_mii_statchg: [mii interface function] 3539 * 3540 * Callback from MII layer when media changes. 3541 */ 3542 static void 3543 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3544 { 3545 struct sip_softc *sc = ifp->if_softc; 3546 struct mii_data *mii = &sc->sc_mii; 3547 u_int32_t flowctl; 3548 3549 /* 3550 * Get flow control negotiation result. 3551 */ 3552 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3553 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3554 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3555 mii->mii_media_active &= ~IFM_ETH_FMASK; 3556 } 3557 3558 /* 3559 * Update TXCFG for full-duplex operation. 3560 */ 3561 if ((mii->mii_media_active & IFM_FDX) != 0) 3562 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3563 else 3564 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3565 3566 /* 3567 * Update RXCFG for full-duplex or loopback. 3568 */ 3569 if ((mii->mii_media_active & IFM_FDX) != 0 || 3570 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3571 sc->sc_rxcfg |= RXCFG_ATX; 3572 else 3573 sc->sc_rxcfg &= ~RXCFG_ATX; 3574 3575 /* 3576 * Update IMR for use of 802.3x flow control. 3577 */ 3578 if (sc->sc_flowflags & IFM_FLOW) { 3579 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3580 flowctl = FLOWCTL_FLOWEN; 3581 } else { 3582 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3583 flowctl = 0; 3584 } 3585 3586 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3587 sc->sc_txcfg); 3588 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3589 sc->sc_rxcfg); 3590 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3591 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3592 } 3593 3594 /* 3595 * sip_dp83815_mii_readreg: [mii interface function] 3596 * 3597 * Read a PHY register on the MII. 3598 */ 3599 static int 3600 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3601 { 3602 struct sip_softc *sc = device_private(self); 3603 u_int32_t val; 3604 3605 /* 3606 * The DP83815 only has an internal PHY. Only allow 3607 * MII address 0. 3608 */ 3609 if (phy != 0) 3610 return (0); 3611 3612 /* 3613 * Apparently, after a reset, the DP83815 can take a while 3614 * to respond. During this recovery period, the BMSR returns 3615 * a value of 0. Catch this -- it's not supposed to happen 3616 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3617 * PHY to come back to life. 3618 * 3619 * This works out because the BMSR is the first register 3620 * read during the PHY probe process. 3621 */ 3622 do { 3623 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3624 } while (reg == MII_BMSR && val == 0); 3625 3626 return (val & 0xffff); 3627 } 3628 3629 /* 3630 * sip_dp83815_mii_writereg: [mii interface function] 3631 * 3632 * Write a PHY register to the MII. 3633 */ 3634 static void 3635 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3636 { 3637 struct sip_softc *sc = device_private(self); 3638 3639 /* 3640 * The DP83815 only has an internal PHY. Only allow 3641 * MII address 0. 3642 */ 3643 if (phy != 0) 3644 return; 3645 3646 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3647 } 3648 3649 /* 3650 * sip_dp83815_mii_statchg: [mii interface function] 3651 * 3652 * Callback from MII layer when media changes. 3653 */ 3654 static void 3655 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3656 { 3657 struct sip_softc *sc = ifp->if_softc; 3658 3659 /* 3660 * Update TXCFG for full-duplex operation. 3661 */ 3662 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3663 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3664 else 3665 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3666 3667 /* 3668 * Update RXCFG for full-duplex or loopback. 3669 */ 3670 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3671 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3672 sc->sc_rxcfg |= RXCFG_ATX; 3673 else 3674 sc->sc_rxcfg &= ~RXCFG_ATX; 3675 3676 /* 3677 * XXX 802.3x flow control. 3678 */ 3679 3680 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3681 sc->sc_txcfg); 3682 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3683 sc->sc_rxcfg); 3684 3685 /* 3686 * Some DP83815s experience problems when used with short 3687 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3688 * sequence adjusts the DSP's signal attenuation to fix the 3689 * problem. 3690 */ 3691 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3692 uint32_t reg; 3693 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3695 3696 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3697 reg &= 0x0fff; 3698 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3699 delay(100); 3700 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3701 reg &= 0x00ff; 3702 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3703 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3704 0x00e8); 3705 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3706 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3707 reg | 0x20); 3708 } 3709 3710 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3711 } 3712 } 3713 3714 static void 3715 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3716 const struct pci_attach_args *pa, u_int8_t *enaddr) 3717 { 3718 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3719 u_int8_t cksum, *e, match; 3720 int i; 3721 3722 /* 3723 * EEPROM data format for the DP83820 can be found in 3724 * the DP83820 manual, section 4.2.4. 3725 */ 3726 3727 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3728 3729 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3730 match = ~(match - 1); 3731 3732 cksum = 0x55; 3733 e = (u_int8_t *) eeprom_data; 3734 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3735 cksum += *e++; 3736 3737 if (cksum != match) 3738 printf("%s: Checksum (%x) mismatch (%x)", 3739 device_xname(sc->sc_dev), cksum, match); 3740 3741 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3742 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3743 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3744 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3745 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3746 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3747 } 3748 3749 static void 3750 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3751 { 3752 int i; 3753 3754 /* 3755 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3756 * a reason, but I don't know it. 3757 */ 3758 for (i = 0; i < 10; i++) 3759 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3760 } 3761 3762 static void 3763 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3764 const struct pci_attach_args *pa, u_int8_t *enaddr) 3765 { 3766 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3767 3768 switch (sc->sc_rev) { 3769 case SIS_REV_630S: 3770 case SIS_REV_630E: 3771 case SIS_REV_630EA1: 3772 case SIS_REV_630ET: 3773 case SIS_REV_635: 3774 /* 3775 * The MAC address for the on-board Ethernet of 3776 * the SiS 630 chipset is in the NVRAM. Kick 3777 * the chip into re-loading it from NVRAM, and 3778 * read the MAC address out of the filter registers. 3779 */ 3780 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3781 3782 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3783 RFCR_RFADDR_NODE0); 3784 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3785 0xffff; 3786 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3788 RFCR_RFADDR_NODE2); 3789 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3790 0xffff; 3791 3792 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3793 RFCR_RFADDR_NODE4); 3794 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3795 0xffff; 3796 break; 3797 3798 case SIS_REV_960: 3799 { 3800 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3801 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3802 3803 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3804 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3805 3806 int waittime, i; 3807 3808 /* Allow to read EEPROM from LAN. It is shared 3809 * between a 1394 controller and the NIC and each 3810 * time we access it, we need to set SIS_EECMD_REQ. 3811 */ 3812 SIS_SET_EROMAR(sc, EROMAR_REQ); 3813 3814 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3815 /* Force EEPROM to idle state. */ 3816 3817 /* 3818 * XXX-cube This is ugly. I'll look for docs about it. 3819 */ 3820 SIS_SET_EROMAR(sc, EROMAR_EECS); 3821 sipcom_sis900_eeprom_delay(sc); 3822 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3823 SIS_SET_EROMAR(sc, EROMAR_EESK); 3824 sipcom_sis900_eeprom_delay(sc); 3825 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3826 sipcom_sis900_eeprom_delay(sc); 3827 } 3828 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3829 sipcom_sis900_eeprom_delay(sc); 3830 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3831 3832 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3833 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3834 sizeof(myea) / sizeof(myea[0]), myea); 3835 break; 3836 } 3837 DELAY(1); 3838 } 3839 3840 /* 3841 * Set SIS_EECTL_CLK to high, so a other master 3842 * can operate on the i2c bus. 3843 */ 3844 SIS_SET_EROMAR(sc, EROMAR_EESK); 3845 3846 /* Refuse EEPROM access by LAN */ 3847 SIS_SET_EROMAR(sc, EROMAR_DONE); 3848 } break; 3849 3850 default: 3851 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3852 sizeof(myea) / sizeof(myea[0]), myea); 3853 } 3854 3855 enaddr[0] = myea[0] & 0xff; 3856 enaddr[1] = myea[0] >> 8; 3857 enaddr[2] = myea[1] & 0xff; 3858 enaddr[3] = myea[1] >> 8; 3859 enaddr[4] = myea[2] & 0xff; 3860 enaddr[5] = myea[2] >> 8; 3861 } 3862 3863 /* Table and macro to bit-reverse an octet. */ 3864 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3865 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3866 3867 static void 3868 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3869 const struct pci_attach_args *pa, u_int8_t *enaddr) 3870 { 3871 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3872 u_int8_t cksum, *e, match; 3873 int i; 3874 3875 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3876 sizeof(eeprom_data[0]), eeprom_data); 3877 3878 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3879 match = ~(match - 1); 3880 3881 cksum = 0x55; 3882 e = (u_int8_t *) eeprom_data; 3883 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3884 cksum += *e++; 3885 } 3886 if (cksum != match) { 3887 printf("%s: Checksum (%x) mismatch (%x)", 3888 device_xname(sc->sc_dev), cksum, match); 3889 } 3890 3891 /* 3892 * Unrolled because it makes slightly more sense this way. 3893 * The DP83815 stores the MAC address in bit 0 of word 6 3894 * through bit 15 of word 8. 3895 */ 3896 ea = &eeprom_data[6]; 3897 enaddr[0] = ((*ea & 0x1) << 7); 3898 ea++; 3899 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3900 enaddr[1] = ((*ea & 0x1FE) >> 1); 3901 enaddr[2] = ((*ea & 0x1) << 7); 3902 ea++; 3903 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3904 enaddr[3] = ((*ea & 0x1FE) >> 1); 3905 enaddr[4] = ((*ea & 0x1) << 7); 3906 ea++; 3907 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3908 enaddr[5] = ((*ea & 0x1FE) >> 1); 3909 3910 /* 3911 * In case that's not weird enough, we also need to reverse 3912 * the bits in each byte. This all actually makes more sense 3913 * if you think about the EEPROM storage as an array of bits 3914 * being shifted into bytes, but that's not how we're looking 3915 * at it here... 3916 */ 3917 for (i = 0; i < 6 ;i++) 3918 enaddr[i] = bbr(enaddr[i]); 3919 } 3920 3921 /* 3922 * sip_mediastatus: [ifmedia interface function] 3923 * 3924 * Get the current interface media status. 3925 */ 3926 static void 3927 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3928 { 3929 struct sip_softc *sc = ifp->if_softc; 3930 3931 if (!device_is_active(sc->sc_dev)) { 3932 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3933 ifmr->ifm_status = 0; 3934 return; 3935 } 3936 ether_mediastatus(ifp, ifmr); 3937 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3938 sc->sc_flowflags; 3939 } 3940
Indexes created Sun Sep 21 20:09:37 GMT 2025