if_sip.c revision 1.163.2.1
1 /* $NetBSD: if_sip.c,v 1.163.2.1 2017/01/07 08:56:33 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.163.2.1 2017/01/07 08:56:33 pgoyette Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rndsource.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int); 587 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int); 591 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int); 595 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int); 622 void (*sipv_mii_writereg)(device_t, int, int, int); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA621 */ 741 { 0x1385, 0x621a }, 742 743 /* Netgear GA622 */ 744 { 0x1385, 0x622a }, 745 746 /* SMC EZ Card 1000 (9462TX) */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, cfdata_t cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 rnd_detach_source(&sc->rnd_source); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 918 919 /*FALLTHROUGH*/ 920 case SIP_ATTACH_CREATE_RXMAP: 921 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 922 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_rxsoft[i].rxs_dmamap); 925 } 926 /*FALLTHROUGH*/ 927 case SIP_ATTACH_CREATE_TXMAP: 928 for (i = 0; i < SIP_TXQUEUELEN; i++) { 929 if (sc->sc_txsoft[i].txs_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txsoft[i].txs_dmamap); 932 } 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_LOAD_MAP: 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_CREATE_MAP: 938 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_MAP_MEM: 941 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 942 sizeof(struct sip_control_data)); 943 /*FALLTHROUGH*/ 944 case SIP_ATTACH_ALLOC_MEM: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_INTR: 948 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_MAP: 951 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 952 break; 953 default: 954 break; 955 } 956 return; 957 } 958 959 static bool 960 sipcom_resume(device_t self, const pmf_qual_t *qual) 961 { 962 struct sip_softc *sc = device_private(self); 963 964 return sipcom_reset(sc); 965 } 966 967 static bool 968 sipcom_suspend(device_t self, const pmf_qual_t *qual) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 sipcom_rxdrain(sc); 973 return true; 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = device_private(self); 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t csr; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 char intrbuf[PCI_INTRSTR_LEN]; 998 999 callout_init(&sc->sc_tick_ch, 0); 1000 1001 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1002 if (sip == NULL) { 1003 aprint_error("\n"); 1004 panic("%s: impossible", __func__); 1005 } 1006 sc->sc_dev = self; 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 aprint_naive("\n"); 1027 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1028 1029 sc->sc_model = sip; 1030 1031 /* 1032 * XXX Work-around broken PXE firmware on some boards. 1033 * 1034 * The DP83815 shares an address decoder with the MEM BAR 1035 * and the ROM BAR. Make sure the ROM BAR is disabled, 1036 * so that memory mapped access works. 1037 */ 1038 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1040 ~PCI_MAPREG_ROM_ENABLE); 1041 1042 /* 1043 * Map the device. 1044 */ 1045 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1046 PCI_MAPREG_TYPE_IO, 0, 1047 &iot, &ioh, NULL, &iosz) == 0); 1048 if (sc->sc_gigabit) { 1049 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1050 switch (memtype) { 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1052 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1053 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1054 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1055 break; 1056 default: 1057 memh_valid = 0; 1058 } 1059 } else { 1060 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1061 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1062 &memt, &memh, NULL, &memsz) == 0); 1063 } 1064 1065 if (memh_valid) { 1066 sc->sc_st = memt; 1067 sc->sc_sh = memh; 1068 sc->sc_sz = memsz; 1069 } else if (ioh_valid) { 1070 sc->sc_st = iot; 1071 sc->sc_sh = ioh; 1072 sc->sc_sz = iosz; 1073 } else { 1074 aprint_error_dev(self, "unable to map device registers\n"); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 csr | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1092 if (error != 0 && error != EOPNOTSUPP) { 1093 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1094 return; 1095 } 1096 1097 /* 1098 * Map and establish our interrupt. 1099 */ 1100 if (pci_intr_map(pa, &ih)) { 1101 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1102 return; 1103 } 1104 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1105 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc); 1106 if (sc->sc_ih == NULL) { 1107 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1108 if (intrstr != NULL) 1109 aprint_error(" at %s", intrstr); 1110 aprint_error("\n"); 1111 sipcom_do_detach(self, SIP_ATTACH_MAP); 1112 return; 1113 } 1114 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1115 1116 SIMPLEQ_INIT(&sc->sc_txfreeq); 1117 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1118 1119 /* 1120 * Allocate the control data structures, and create and load the 1121 * DMA map for it. 1122 */ 1123 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1124 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1125 &rseg, 0)) != 0) { 1126 aprint_error_dev(sc->sc_dev, 1127 "unable to allocate control data, error = %d\n", error); 1128 sipcom_do_detach(self, SIP_ATTACH_INTR); 1129 return; 1130 } 1131 1132 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1133 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1134 BUS_DMA_COHERENT)) != 0) { 1135 aprint_error_dev(sc->sc_dev, 1136 "unable to map control data, error = %d\n", error); 1137 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1138 } 1139 1140 if ((error = bus_dmamap_create(sc->sc_dmat, 1141 sizeof(struct sip_control_data), 1, 1142 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1143 aprint_error_dev(self, "unable to create control data DMA map" 1144 ", error = %d\n", error); 1145 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1146 } 1147 1148 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1149 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1150 0)) != 0) { 1151 aprint_error_dev(self, "unable to load control data DMA map" 1152 ", error = %d\n", error); 1153 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1154 } 1155 1156 /* 1157 * Create the transmit buffer DMA maps. 1158 */ 1159 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1160 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1161 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1162 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1163 aprint_error_dev(self, "unable to create tx DMA map %d" 1164 ", error = %d\n", i, error); 1165 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1166 } 1167 } 1168 1169 /* 1170 * Create the receive buffer DMA maps. 1171 */ 1172 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1173 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1174 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1175 aprint_error_dev(self, "unable to create rx DMA map %d" 1176 ", error = %d\n", i, error); 1177 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1178 } 1179 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1180 } 1181 1182 /* 1183 * Reset the chip to a known state. 1184 */ 1185 sipcom_reset(sc); 1186 1187 /* 1188 * Read the Ethernet address from the EEPROM. This might 1189 * also fetch other stuff from the EEPROM and stash it 1190 * in the softc. 1191 */ 1192 sc->sc_cfg = 0; 1193 if (!sc->sc_gigabit) { 1194 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1195 SIP_SIS900_REV(sc,SIS_REV_900B)) 1196 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1197 1198 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1199 SIP_SIS900_REV(sc,SIS_REV_960) || 1200 SIP_SIS900_REV(sc,SIS_REV_900B)) 1201 sc->sc_cfg |= 1202 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1203 CFG_EDBMASTEN); 1204 } 1205 1206 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1207 1208 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1209 1210 /* 1211 * Initialize the configuration register: aggressive PCI 1212 * bus request algorithm, default backoff, default OW timer, 1213 * default parity error detection. 1214 * 1215 * NOTE: "Big endian mode" is useless on the SiS900 and 1216 * friends -- it affects packet data, not descriptors. 1217 */ 1218 if (sc->sc_gigabit) 1219 sipcom_dp83820_attach(sc, pa); 1220 1221 /* 1222 * Initialize our media structures and probe the MII. 1223 */ 1224 sc->sc_mii.mii_ifp = ifp; 1225 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1226 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1227 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1228 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1229 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1230 sipcom_mediastatus); 1231 1232 /* 1233 * XXX We cannot handle flow control on the DP83815. 1234 */ 1235 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1236 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, 0); 1238 else 1239 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1240 MII_OFFSET_ANY, MIIF_DOPAUSE); 1241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1244 } else 1245 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1246 1247 ifp = &sc->sc_ethercom.ec_if; 1248 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1249 ifp->if_softc = sc; 1250 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1251 sc->sc_if_flags = ifp->if_flags; 1252 ifp->if_ioctl = sipcom_ioctl; 1253 ifp->if_start = sipcom_start; 1254 ifp->if_watchdog = sipcom_watchdog; 1255 ifp->if_init = sipcom_init; 1256 ifp->if_stop = sipcom_stop; 1257 IFQ_SET_READY(&ifp->if_snd); 1258 1259 /* 1260 * We can support 802.1Q VLAN-sized frames. 1261 */ 1262 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1263 1264 if (sc->sc_gigabit) { 1265 /* 1266 * And the DP83820 can do VLAN tagging in hardware, and 1267 * support the jumbo Ethernet MTU. 1268 */ 1269 sc->sc_ethercom.ec_capabilities |= 1270 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1271 1272 /* 1273 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1274 * in hardware. 1275 */ 1276 ifp->if_capabilities |= 1277 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1278 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1279 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1280 } 1281 1282 /* 1283 * Attach the interface. 1284 */ 1285 if_attach(ifp); 1286 if_deferred_start_init(ifp, NULL); 1287 ether_ifattach(ifp, enaddr); 1288 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1289 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1290 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1291 sc->sc_prev.if_capenable = ifp->if_capenable; 1292 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1293 RND_TYPE_NET, RND_FLAG_DEFAULT); 1294 1295 /* 1296 * The number of bytes that must be available in 1297 * the Tx FIFO before the bus master can DMA more 1298 * data into the FIFO. 1299 */ 1300 sc->sc_tx_fill_thresh = 64 / 32; 1301 1302 /* 1303 * Start at a drain threshold of 512 bytes. We will 1304 * increase it if a DMA underrun occurs. 1305 * 1306 * XXX The minimum value of this variable should be 1307 * tuned. We may be able to improve performance 1308 * by starting with a lower value. That, however, 1309 * may trash the first few outgoing packets if the 1310 * PCI bus is saturated. 1311 */ 1312 if (sc->sc_gigabit) 1313 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1314 else 1315 sc->sc_tx_drain_thresh = 1504 / 32; 1316 1317 /* 1318 * Initialize the Rx FIFO drain threshold. 1319 * 1320 * This is in units of 8 bytes. 1321 * 1322 * We should never set this value lower than 2; 14 bytes are 1323 * required to filter the packet. 1324 */ 1325 sc->sc_rx_drain_thresh = 128 / 8; 1326 1327 #ifdef SIP_EVENT_COUNTERS 1328 /* 1329 * Attach event counters. 1330 */ 1331 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1332 NULL, device_xname(sc->sc_dev), "txsstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1334 NULL, device_xname(sc->sc_dev), "txdstall"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(sc->sc_dev), "txforceintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "txdintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "txiintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "rxintr"); 1343 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "hiberr"); 1345 if (!sc->sc_gigabit) { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1347 NULL, device_xname(sc->sc_dev), "rxpause"); 1348 } else { 1349 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1350 NULL, device_xname(sc->sc_dev), "rxpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "txpause"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxipsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "txipsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1363 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1364 NULL, device_xname(sc->sc_dev), "txudpsum"); 1365 } 1366 #endif /* SIP_EVENT_COUNTERS */ 1367 1368 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1369 pmf_class_network_register(self, ifp); 1370 else 1371 aprint_error_dev(self, "couldn't establish power handler\n"); 1372 } 1373 1374 static inline void 1375 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1376 uint64_t capenable) 1377 { 1378 struct m_tag *mtag; 1379 u_int32_t extsts; 1380 #ifdef DEBUG 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 #endif 1383 /* 1384 * If VLANs are enabled and the packet has a VLAN tag, set 1385 * up the descriptor to encapsulate the packet for us. 1386 * 1387 * This apparently has to be on the last descriptor of 1388 * the packet. 1389 */ 1390 1391 /* 1392 * Byte swapping is tricky. We need to provide the tag 1393 * in a network byte order. On a big-endian machine, 1394 * the byteorder is correct, but we need to swap it 1395 * anyway, because this will be undone by the outside 1396 * htole32(). That's why there must be an 1397 * unconditional swap instead of htons() inside. 1398 */ 1399 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1400 sc->sc_txdescs[lasttx].sipd_extsts |= 1401 htole32(EXTSTS_VPKT | 1402 (bswap16(VLAN_TAG_VALUE(mtag)) & 1403 EXTSTS_VTCI)); 1404 } 1405 1406 /* 1407 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1408 * checksumming, set up the descriptor to do this work 1409 * for us. 1410 * 1411 * This apparently has to be on the first descriptor of 1412 * the packet. 1413 * 1414 * Byte-swap constants so the compiler can optimize. 1415 */ 1416 extsts = 0; 1417 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1418 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1419 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1420 extsts |= htole32(EXTSTS_IPPKT); 1421 } 1422 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1425 extsts |= htole32(EXTSTS_TCPPKT); 1426 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1429 extsts |= htole32(EXTSTS_UDPPKT); 1430 } 1431 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1432 } 1433 1434 /* 1435 * sip_start: [ifnet interface function] 1436 * 1437 * Start packet transmission on the interface. 1438 */ 1439 static void 1440 sipcom_start(struct ifnet *ifp) 1441 { 1442 struct sip_softc *sc = ifp->if_softc; 1443 struct mbuf *m0; 1444 struct mbuf *m; 1445 struct sip_txsoft *txs; 1446 bus_dmamap_t dmamap; 1447 int error, nexttx, lasttx, seg; 1448 int ofree = sc->sc_txfree; 1449 #if 0 1450 int firsttx = sc->sc_txnext; 1451 #endif 1452 1453 /* 1454 * If we've been told to pause, don't transmit any more packets. 1455 */ 1456 if (!sc->sc_gigabit && sc->sc_paused) 1457 ifp->if_flags |= IFF_OACTIVE; 1458 1459 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1460 return; 1461 1462 /* 1463 * Loop through the send queue, setting up transmit descriptors 1464 * until we drain the queue, or use up all available transmit 1465 * descriptors. 1466 */ 1467 for (;;) { 1468 /* Get a work queue entry. */ 1469 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1470 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1471 break; 1472 } 1473 1474 /* 1475 * Grab a packet off the queue. 1476 */ 1477 IFQ_POLL(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 m = NULL; 1481 1482 dmamap = txs->txs_dmamap; 1483 1484 /* 1485 * Load the DMA map. If this fails, the packet either 1486 * didn't fit in the alloted number of segments, or we 1487 * were short on resources. 1488 */ 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1490 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1491 /* In the non-gigabit case, we'll copy and try again. */ 1492 if (error != 0 && !sc->sc_gigabit) { 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) { 1495 printf("%s: unable to allocate Tx mbuf\n", 1496 device_xname(sc->sc_dev)); 1497 break; 1498 } 1499 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1500 if (m0->m_pkthdr.len > MHLEN) { 1501 MCLGET(m, M_DONTWAIT); 1502 if ((m->m_flags & M_EXT) == 0) { 1503 printf("%s: unable to allocate Tx " 1504 "cluster\n", 1505 device_xname(sc->sc_dev)); 1506 m_freem(m); 1507 break; 1508 } 1509 } 1510 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1511 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1512 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1513 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1514 if (error) { 1515 printf("%s: unable to load Tx buffer, error = " 1516 "%d\n", device_xname(sc->sc_dev), error); 1517 break; 1518 } 1519 } else if (error == EFBIG) { 1520 /* 1521 * For the too-many-segments case, we simply 1522 * report an error and drop the packet, 1523 * since we can't sanely copy a jumbo packet 1524 * to a single buffer. 1525 */ 1526 printf("%s: Tx packet consumes too many DMA segments, " 1527 "dropping...\n", device_xname(sc->sc_dev)); 1528 IFQ_DEQUEUE(&ifp->if_snd, m0); 1529 m_freem(m0); 1530 continue; 1531 } else if (error != 0) { 1532 /* 1533 * Short on resources, just stop for now. 1534 */ 1535 break; 1536 } 1537 1538 /* 1539 * Ensure we have enough descriptors free to describe 1540 * the packet. Note, we always reserve one descriptor 1541 * at the end of the ring as a termination point, to 1542 * prevent wrap-around. 1543 */ 1544 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1545 /* 1546 * Not enough free descriptors to transmit this 1547 * packet. We haven't committed anything yet, 1548 * so just unload the DMA map, put the packet 1549 * back on the queue, and punt. Notify the upper 1550 * layer that there are not more slots left. 1551 * 1552 * XXX We could allocate an mbuf and copy, but 1553 * XXX is it worth it? 1554 */ 1555 ifp->if_flags |= IFF_OACTIVE; 1556 bus_dmamap_unload(sc->sc_dmat, dmamap); 1557 if (m != NULL) 1558 m_freem(m); 1559 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1560 break; 1561 } 1562 1563 IFQ_DEQUEUE(&ifp->if_snd, m0); 1564 if (m != NULL) { 1565 m_freem(m0); 1566 m0 = m; 1567 } 1568 1569 /* 1570 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1571 */ 1572 1573 /* Sync the DMA map. */ 1574 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1575 BUS_DMASYNC_PREWRITE); 1576 1577 /* 1578 * Initialize the transmit descriptors. 1579 */ 1580 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1581 seg < dmamap->dm_nsegs; 1582 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1583 /* 1584 * If this is the first descriptor we're 1585 * enqueueing, don't set the OWN bit just 1586 * yet. That could cause a race condition. 1587 * We'll do it below. 1588 */ 1589 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32(dmamap->dm_segs[seg].ds_addr); 1591 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1592 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1593 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1594 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1595 lasttx = nexttx; 1596 } 1597 1598 /* Clear the MORE bit on the last segment. */ 1599 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1600 htole32(~CMDSTS_MORE); 1601 1602 /* 1603 * If we're in the interrupt delay window, delay the 1604 * interrupt. 1605 */ 1606 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1607 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1608 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1609 htole32(CMDSTS_INTR); 1610 sc->sc_txwin = 0; 1611 } 1612 1613 if (sc->sc_gigabit) 1614 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1615 1616 /* Sync the descriptors we're using. */ 1617 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1618 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1619 1620 /* 1621 * The entire packet is set up. Give the first descrptor 1622 * to the chip now. 1623 */ 1624 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1625 htole32(CMDSTS_OWN); 1626 sip_cdtxsync(sc, sc->sc_txnext, 1, 1627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1628 1629 /* 1630 * Store a pointer to the packet so we can free it later, 1631 * and remember what txdirty will be once the packet is 1632 * done. 1633 */ 1634 txs->txs_mbuf = m0; 1635 txs->txs_firstdesc = sc->sc_txnext; 1636 txs->txs_lastdesc = lasttx; 1637 1638 /* Advance the tx pointer. */ 1639 sc->sc_txfree -= dmamap->dm_nsegs; 1640 sc->sc_txnext = nexttx; 1641 1642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1643 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1644 1645 /* 1646 * Pass the packet to any BPF listeners. 1647 */ 1648 bpf_mtap(ifp, m0); 1649 } 1650 1651 if (txs == NULL || sc->sc_txfree == 0) { 1652 /* No more slots left; notify upper layer. */ 1653 ifp->if_flags |= IFF_OACTIVE; 1654 } 1655 1656 if (sc->sc_txfree != ofree) { 1657 /* 1658 * Start the transmit process. Note, the manual says 1659 * that if there are no pending transmissions in the 1660 * chip's internal queue (indicated by TXE being clear), 1661 * then the driver software must set the TXDP to the 1662 * first descriptor to be transmitted. However, if we 1663 * do this, it causes serious performance degredation on 1664 * the DP83820 under load, not setting TXDP doesn't seem 1665 * to adversely affect the SiS 900 or DP83815. 1666 * 1667 * Well, I guess it wouldn't be the first time a manual 1668 * has lied -- and they could be speaking of the NULL- 1669 * terminated descriptor list case, rather than OWN- 1670 * terminated rings. 1671 */ 1672 #if 0 1673 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1674 CR_TXE) == 0) { 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1676 SIP_CDTXADDR(sc, firsttx)); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1678 } 1679 #else 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1681 #endif 1682 1683 /* Set a watchdog timer in case the chip flakes out. */ 1684 /* Gigabit autonegotiation takes 5 seconds. */ 1685 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1686 } 1687 } 1688 1689 /* 1690 * sip_watchdog: [ifnet interface function] 1691 * 1692 * Watchdog timer handler. 1693 */ 1694 static void 1695 sipcom_watchdog(struct ifnet *ifp) 1696 { 1697 struct sip_softc *sc = ifp->if_softc; 1698 1699 /* 1700 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1701 * If we get a timeout, try and sweep up transmit descriptors. 1702 * If we manage to sweep them all up, ignore the lack of 1703 * interrupt. 1704 */ 1705 sipcom_txintr(sc); 1706 1707 if (sc->sc_txfree != sc->sc_ntxdesc) { 1708 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1709 ifp->if_oerrors++; 1710 1711 /* Reset the interface. */ 1712 (void) sipcom_init(ifp); 1713 } else if (ifp->if_flags & IFF_DEBUG) 1714 printf("%s: recovered from device timeout\n", 1715 device_xname(sc->sc_dev)); 1716 1717 /* Try to get more packets going. */ 1718 sipcom_start(ifp); 1719 } 1720 1721 /* If the interface is up and running, only modify the receive 1722 * filter when setting promiscuous or debug mode. Otherwise fall 1723 * through to ether_ioctl, which will reset the chip. 1724 */ 1725 static int 1726 sip_ifflags_cb(struct ethercom *ec) 1727 { 1728 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1729 == (sc)->sc_ethercom.ec_capenable) \ 1730 && ((sc)->sc_prev.is_vlan == \ 1731 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1732 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1733 struct ifnet *ifp = &ec->ec_if; 1734 struct sip_softc *sc = ifp->if_softc; 1735 int change = ifp->if_flags ^ sc->sc_if_flags; 1736 1737 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1738 !COMPARE_IC(sc, ifp)) 1739 return ENETRESET; 1740 /* Set up the receive filter. */ 1741 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1742 return 0; 1743 } 1744 1745 /* 1746 * sip_ioctl: [ifnet interface function] 1747 * 1748 * Handle control requests from the operator. 1749 */ 1750 static int 1751 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1752 { 1753 struct sip_softc *sc = ifp->if_softc; 1754 struct ifreq *ifr = (struct ifreq *)data; 1755 int s, error; 1756 1757 s = splnet(); 1758 1759 switch (cmd) { 1760 case SIOCSIFMEDIA: 1761 /* Flow control requires full-duplex mode. */ 1762 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1763 (ifr->ifr_media & IFM_FDX) == 0) 1764 ifr->ifr_media &= ~IFM_ETH_FMASK; 1765 1766 /* XXX */ 1767 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1768 ifr->ifr_media &= ~IFM_ETH_FMASK; 1769 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1770 if (sc->sc_gigabit && 1771 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1772 /* We can do both TXPAUSE and RXPAUSE. */ 1773 ifr->ifr_media |= 1774 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1775 } else if (ifr->ifr_media & IFM_FLOW) { 1776 /* 1777 * Both TXPAUSE and RXPAUSE must be set. 1778 * (SiS900 and DP83815 don't have PAUSE_ASYM 1779 * feature.) 1780 * 1781 * XXX Can SiS900 and DP83815 send PAUSE? 1782 */ 1783 ifr->ifr_media |= 1784 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1785 } 1786 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1787 } 1788 /*FALLTHROUGH*/ 1789 default: 1790 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1791 break; 1792 1793 error = 0; 1794 1795 if (cmd == SIOCSIFCAP) 1796 error = (*ifp->if_init)(ifp); 1797 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1798 ; 1799 else if (ifp->if_flags & IFF_RUNNING) { 1800 /* 1801 * Multicast list has changed; set the hardware filter 1802 * accordingly. 1803 */ 1804 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1805 } 1806 break; 1807 } 1808 1809 /* Try to get more packets going. */ 1810 sipcom_start(ifp); 1811 1812 sc->sc_if_flags = ifp->if_flags; 1813 splx(s); 1814 return (error); 1815 } 1816 1817 /* 1818 * sip_intr: 1819 * 1820 * Interrupt service routine. 1821 */ 1822 static int 1823 sipcom_intr(void *arg) 1824 { 1825 struct sip_softc *sc = arg; 1826 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1827 u_int32_t isr; 1828 int handled = 0; 1829 1830 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1831 return 0; 1832 1833 /* Disable interrupts. */ 1834 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1835 1836 for (;;) { 1837 /* Reading clears interrupt. */ 1838 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1839 if ((isr & sc->sc_imr) == 0) 1840 break; 1841 1842 rnd_add_uint32(&sc->rnd_source, isr); 1843 1844 handled = 1; 1845 1846 if ((ifp->if_flags & IFF_RUNNING) == 0) 1847 break; 1848 1849 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1850 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1851 1852 /* Grab any new packets. */ 1853 (*sc->sc_rxintr)(sc); 1854 1855 if (isr & ISR_RXORN) { 1856 printf("%s: receive FIFO overrun\n", 1857 device_xname(sc->sc_dev)); 1858 1859 /* XXX adjust rx_drain_thresh? */ 1860 } 1861 1862 if (isr & ISR_RXIDLE) { 1863 printf("%s: receive ring overrun\n", 1864 device_xname(sc->sc_dev)); 1865 1866 /* Get the receive process going again. */ 1867 bus_space_write_4(sc->sc_st, sc->sc_sh, 1868 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1869 bus_space_write_4(sc->sc_st, sc->sc_sh, 1870 SIP_CR, CR_RXE); 1871 } 1872 } 1873 1874 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1875 #ifdef SIP_EVENT_COUNTERS 1876 if (isr & ISR_TXDESC) 1877 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1878 else if (isr & ISR_TXIDLE) 1879 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1880 #endif 1881 1882 /* Sweep up transmit descriptors. */ 1883 sipcom_txintr(sc); 1884 1885 if (isr & ISR_TXURN) { 1886 u_int32_t thresh; 1887 int txfifo_size = (sc->sc_gigabit) 1888 ? DP83820_SIP_TXFIFO_SIZE 1889 : OTHER_SIP_TXFIFO_SIZE; 1890 1891 printf("%s: transmit FIFO underrun", 1892 device_xname(sc->sc_dev)); 1893 thresh = sc->sc_tx_drain_thresh + 1; 1894 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1895 && (thresh * 32) <= (txfifo_size - 1896 (sc->sc_tx_fill_thresh * 32))) { 1897 printf("; increasing Tx drain " 1898 "threshold to %u bytes\n", 1899 thresh * 32); 1900 sc->sc_tx_drain_thresh = thresh; 1901 (void) sipcom_init(ifp); 1902 } else { 1903 (void) sipcom_init(ifp); 1904 printf("\n"); 1905 } 1906 } 1907 } 1908 1909 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1910 if (isr & ISR_PAUSE_ST) { 1911 sc->sc_paused = 1; 1912 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1913 ifp->if_flags |= IFF_OACTIVE; 1914 } 1915 if (isr & ISR_PAUSE_END) { 1916 sc->sc_paused = 0; 1917 ifp->if_flags &= ~IFF_OACTIVE; 1918 } 1919 } 1920 1921 if (isr & ISR_HIBERR) { 1922 int want_init = 0; 1923 1924 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1925 1926 #define PRINTERR(bit, str) \ 1927 do { \ 1928 if ((isr & (bit)) != 0) { \ 1929 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1930 printf("%s: %s\n", \ 1931 device_xname(sc->sc_dev), str); \ 1932 want_init = 1; \ 1933 } \ 1934 } while (/*CONSTCOND*/0) 1935 1936 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1937 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1938 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1939 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1940 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1941 /* 1942 * Ignore: 1943 * Tx reset complete 1944 * Rx reset complete 1945 */ 1946 if (want_init) 1947 (void) sipcom_init(ifp); 1948 #undef PRINTERR 1949 } 1950 } 1951 1952 /* Re-enable interrupts. */ 1953 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1954 1955 /* Try to get more packets going. */ 1956 if_schedule_deferred_start(ifp); 1957 1958 return (handled); 1959 } 1960 1961 /* 1962 * sip_txintr: 1963 * 1964 * Helper; handle transmit interrupts. 1965 */ 1966 static void 1967 sipcom_txintr(struct sip_softc *sc) 1968 { 1969 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1970 struct sip_txsoft *txs; 1971 u_int32_t cmdsts; 1972 1973 if (sc->sc_paused == 0) 1974 ifp->if_flags &= ~IFF_OACTIVE; 1975 1976 /* 1977 * Go through our Tx list and free mbufs for those 1978 * frames which have been transmitted. 1979 */ 1980 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1981 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1982 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1983 1984 cmdsts = le32toh(*sipd_cmdsts(sc, 1985 &sc->sc_txdescs[txs->txs_lastdesc])); 1986 if (cmdsts & CMDSTS_OWN) 1987 break; 1988 1989 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1990 1991 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1992 1993 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1994 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1995 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1996 m_freem(txs->txs_mbuf); 1997 txs->txs_mbuf = NULL; 1998 1999 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2000 2001 /* 2002 * Check for errors and collisions. 2003 */ 2004 if (cmdsts & 2005 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2006 ifp->if_oerrors++; 2007 if (cmdsts & CMDSTS_Tx_EC) 2008 ifp->if_collisions += 16; 2009 if (ifp->if_flags & IFF_DEBUG) { 2010 if (cmdsts & CMDSTS_Tx_ED) 2011 printf("%s: excessive deferral\n", 2012 device_xname(sc->sc_dev)); 2013 if (cmdsts & CMDSTS_Tx_EC) 2014 printf("%s: excessive collisions\n", 2015 device_xname(sc->sc_dev)); 2016 } 2017 } else { 2018 /* Packet was transmitted successfully. */ 2019 ifp->if_opackets++; 2020 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2021 } 2022 } 2023 2024 /* 2025 * If there are no more pending transmissions, cancel the watchdog 2026 * timer. 2027 */ 2028 if (txs == NULL) { 2029 ifp->if_timer = 0; 2030 sc->sc_txwin = 0; 2031 } 2032 } 2033 2034 /* 2035 * gsip_rxintr: 2036 * 2037 * Helper; handle receive interrupts on gigabit parts. 2038 */ 2039 static void 2040 gsip_rxintr(struct sip_softc *sc) 2041 { 2042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2043 struct sip_rxsoft *rxs; 2044 struct mbuf *m; 2045 u_int32_t cmdsts, extsts; 2046 int i, len; 2047 2048 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2049 rxs = &sc->sc_rxsoft[i]; 2050 2051 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2052 2053 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2054 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2055 len = CMDSTS_SIZE(sc, cmdsts); 2056 2057 /* 2058 * NOTE: OWN is set if owned by _consumer_. We're the 2059 * consumer of the receive ring, so if the bit is clear, 2060 * we have processed all of the packets. 2061 */ 2062 if ((cmdsts & CMDSTS_OWN) == 0) { 2063 /* 2064 * We have processed all of the receive buffers. 2065 */ 2066 break; 2067 } 2068 2069 if (__predict_false(sc->sc_rxdiscard)) { 2070 sip_init_rxdesc(sc, i); 2071 if ((cmdsts & CMDSTS_MORE) == 0) { 2072 /* Reset our state. */ 2073 sc->sc_rxdiscard = 0; 2074 } 2075 continue; 2076 } 2077 2078 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2079 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2080 2081 m = rxs->rxs_mbuf; 2082 2083 /* 2084 * Add a new receive buffer to the ring. 2085 */ 2086 if (sipcom_add_rxbuf(sc, i) != 0) { 2087 /* 2088 * Failed, throw away what we've done so 2089 * far, and discard the rest of the packet. 2090 */ 2091 ifp->if_ierrors++; 2092 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2093 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2094 sip_init_rxdesc(sc, i); 2095 if (cmdsts & CMDSTS_MORE) 2096 sc->sc_rxdiscard = 1; 2097 if (sc->sc_rxhead != NULL) 2098 m_freem(sc->sc_rxhead); 2099 sip_rxchain_reset(sc); 2100 continue; 2101 } 2102 2103 sip_rxchain_link(sc, m); 2104 2105 m->m_len = len; 2106 2107 /* 2108 * If this is not the end of the packet, keep 2109 * looking. 2110 */ 2111 if (cmdsts & CMDSTS_MORE) { 2112 sc->sc_rxlen += len; 2113 continue; 2114 } 2115 2116 /* 2117 * Okay, we have the entire packet now. The chip includes 2118 * the FCS, so we need to trim it. 2119 */ 2120 m->m_len -= ETHER_CRC_LEN; 2121 2122 *sc->sc_rxtailp = NULL; 2123 len = m->m_len + sc->sc_rxlen; 2124 m = sc->sc_rxhead; 2125 2126 sip_rxchain_reset(sc); 2127 2128 /* 2129 * If an error occurred, update stats and drop the packet. 2130 */ 2131 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2132 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2133 ifp->if_ierrors++; 2134 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2135 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2136 /* Receive overrun handled elsewhere. */ 2137 printf("%s: receive descriptor error\n", 2138 device_xname(sc->sc_dev)); 2139 } 2140 #define PRINTERR(bit, str) \ 2141 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2142 (cmdsts & (bit)) != 0) \ 2143 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2144 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2145 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2146 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2147 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2148 #undef PRINTERR 2149 m_freem(m); 2150 continue; 2151 } 2152 2153 /* 2154 * If the packet is small enough to fit in a 2155 * single header mbuf, allocate one and copy 2156 * the data into it. This greatly reduces 2157 * memory consumption when we receive lots 2158 * of small packets. 2159 */ 2160 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2161 struct mbuf *nm; 2162 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2163 if (nm == NULL) { 2164 ifp->if_ierrors++; 2165 m_freem(m); 2166 continue; 2167 } 2168 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2169 nm->m_data += 2; 2170 nm->m_pkthdr.len = nm->m_len = len; 2171 m_copydata(m, 0, len, mtod(nm, void *)); 2172 m_freem(m); 2173 m = nm; 2174 } 2175 #ifndef __NO_STRICT_ALIGNMENT 2176 else { 2177 /* 2178 * The DP83820's receive buffers must be 4-byte 2179 * aligned. But this means that the data after 2180 * the Ethernet header is misaligned. To compensate, 2181 * we have artificially shortened the buffer size 2182 * in the descriptor, and we do an overlapping copy 2183 * of the data two bytes further in (in the first 2184 * buffer of the chain only). 2185 */ 2186 memmove(mtod(m, char *) + 2, mtod(m, void *), 2187 m->m_len); 2188 m->m_data += 2; 2189 } 2190 #endif /* ! __NO_STRICT_ALIGNMENT */ 2191 2192 /* 2193 * If VLANs are enabled, VLAN packets have been unwrapped 2194 * for us. Associate the tag with the packet. 2195 */ 2196 2197 /* 2198 * Again, byte swapping is tricky. Hardware provided 2199 * the tag in the network byte order, but extsts was 2200 * passed through le32toh() in the meantime. On a 2201 * big-endian machine, we need to swap it again. On a 2202 * little-endian machine, we need to convert from the 2203 * network to host byte order. This means that we must 2204 * swap it in any case, so unconditional swap instead 2205 * of htons() is used. 2206 */ 2207 if ((extsts & EXTSTS_VPKT) != 0) { 2208 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2209 continue); 2210 } 2211 2212 /* 2213 * Set the incoming checksum information for the 2214 * packet. 2215 */ 2216 if ((extsts & EXTSTS_IPPKT) != 0) { 2217 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2218 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2219 if (extsts & EXTSTS_Rx_IPERR) 2220 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2221 if (extsts & EXTSTS_TCPPKT) { 2222 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2223 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2224 if (extsts & EXTSTS_Rx_TCPERR) 2225 m->m_pkthdr.csum_flags |= 2226 M_CSUM_TCP_UDP_BAD; 2227 } else if (extsts & EXTSTS_UDPPKT) { 2228 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2229 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2230 if (extsts & EXTSTS_Rx_UDPERR) 2231 m->m_pkthdr.csum_flags |= 2232 M_CSUM_TCP_UDP_BAD; 2233 } 2234 } 2235 2236 m_set_rcvif(m, ifp); 2237 m->m_pkthdr.len = len; 2238 2239 /* Pass it on. */ 2240 if_percpuq_enqueue(ifp->if_percpuq, m); 2241 } 2242 2243 /* Update the receive pointer. */ 2244 sc->sc_rxptr = i; 2245 } 2246 2247 /* 2248 * sip_rxintr: 2249 * 2250 * Helper; handle receive interrupts on 10/100 parts. 2251 */ 2252 static void 2253 sip_rxintr(struct sip_softc *sc) 2254 { 2255 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2256 struct sip_rxsoft *rxs; 2257 struct mbuf *m; 2258 u_int32_t cmdsts; 2259 int i, len; 2260 2261 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2262 rxs = &sc->sc_rxsoft[i]; 2263 2264 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2265 2266 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2267 2268 /* 2269 * NOTE: OWN is set if owned by _consumer_. We're the 2270 * consumer of the receive ring, so if the bit is clear, 2271 * we have processed all of the packets. 2272 */ 2273 if ((cmdsts & CMDSTS_OWN) == 0) { 2274 /* 2275 * We have processed all of the receive buffers. 2276 */ 2277 break; 2278 } 2279 2280 /* 2281 * If any collisions were seen on the wire, count one. 2282 */ 2283 if (cmdsts & CMDSTS_Rx_COL) 2284 ifp->if_collisions++; 2285 2286 /* 2287 * If an error occurred, update stats, clear the status 2288 * word, and leave the packet buffer in place. It will 2289 * simply be reused the next time the ring comes around. 2290 */ 2291 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2292 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2293 ifp->if_ierrors++; 2294 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2295 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2296 /* Receive overrun handled elsewhere. */ 2297 printf("%s: receive descriptor error\n", 2298 device_xname(sc->sc_dev)); 2299 } 2300 #define PRINTERR(bit, str) \ 2301 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2302 (cmdsts & (bit)) != 0) \ 2303 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2304 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2305 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2306 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2307 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2308 #undef PRINTERR 2309 sip_init_rxdesc(sc, i); 2310 continue; 2311 } 2312 2313 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2314 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2315 2316 /* 2317 * No errors; receive the packet. Note, the SiS 900 2318 * includes the CRC with every packet. 2319 */ 2320 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2321 2322 #ifdef __NO_STRICT_ALIGNMENT 2323 /* 2324 * If the packet is small enough to fit in a 2325 * single header mbuf, allocate one and copy 2326 * the data into it. This greatly reduces 2327 * memory consumption when we receive lots 2328 * of small packets. 2329 * 2330 * Otherwise, we add a new buffer to the receive 2331 * chain. If this fails, we drop the packet and 2332 * recycle the old buffer. 2333 */ 2334 if (sip_copy_small != 0 && len <= MHLEN) { 2335 MGETHDR(m, M_DONTWAIT, MT_DATA); 2336 if (m == NULL) 2337 goto dropit; 2338 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2339 memcpy(mtod(m, void *), 2340 mtod(rxs->rxs_mbuf, void *), len); 2341 sip_init_rxdesc(sc, i); 2342 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2343 rxs->rxs_dmamap->dm_mapsize, 2344 BUS_DMASYNC_PREREAD); 2345 } else { 2346 m = rxs->rxs_mbuf; 2347 if (sipcom_add_rxbuf(sc, i) != 0) { 2348 dropit: 2349 ifp->if_ierrors++; 2350 sip_init_rxdesc(sc, i); 2351 bus_dmamap_sync(sc->sc_dmat, 2352 rxs->rxs_dmamap, 0, 2353 rxs->rxs_dmamap->dm_mapsize, 2354 BUS_DMASYNC_PREREAD); 2355 continue; 2356 } 2357 } 2358 #else 2359 /* 2360 * The SiS 900's receive buffers must be 4-byte aligned. 2361 * But this means that the data after the Ethernet header 2362 * is misaligned. We must allocate a new buffer and 2363 * copy the data, shifted forward 2 bytes. 2364 */ 2365 MGETHDR(m, M_DONTWAIT, MT_DATA); 2366 if (m == NULL) { 2367 dropit: 2368 ifp->if_ierrors++; 2369 sip_init_rxdesc(sc, i); 2370 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2371 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2372 continue; 2373 } 2374 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2375 if (len > (MHLEN - 2)) { 2376 MCLGET(m, M_DONTWAIT); 2377 if ((m->m_flags & M_EXT) == 0) { 2378 m_freem(m); 2379 goto dropit; 2380 } 2381 } 2382 m->m_data += 2; 2383 2384 /* 2385 * Note that we use clusters for incoming frames, so the 2386 * buffer is virtually contiguous. 2387 */ 2388 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2389 2390 /* Allow the receive descriptor to continue using its mbuf. */ 2391 sip_init_rxdesc(sc, i); 2392 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2393 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2394 #endif /* __NO_STRICT_ALIGNMENT */ 2395 2396 m_set_rcvif(m, ifp); 2397 m->m_pkthdr.len = m->m_len = len; 2398 2399 /* Pass it on. */ 2400 if_percpuq_enqueue(ifp->if_percpuq, m); 2401 } 2402 2403 /* Update the receive pointer. */ 2404 sc->sc_rxptr = i; 2405 } 2406 2407 /* 2408 * sip_tick: 2409 * 2410 * One second timer, used to tick the MII. 2411 */ 2412 static void 2413 sipcom_tick(void *arg) 2414 { 2415 struct sip_softc *sc = arg; 2416 int s; 2417 2418 s = splnet(); 2419 #ifdef SIP_EVENT_COUNTERS 2420 if (sc->sc_gigabit) { 2421 /* Read PAUSE related counts from MIB registers. */ 2422 sc->sc_ev_rxpause.ev_count += 2423 bus_space_read_4(sc->sc_st, sc->sc_sh, 2424 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2425 sc->sc_ev_txpause.ev_count += 2426 bus_space_read_4(sc->sc_st, sc->sc_sh, 2427 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2428 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2429 } 2430 #endif /* SIP_EVENT_COUNTERS */ 2431 mii_tick(&sc->sc_mii); 2432 splx(s); 2433 2434 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2435 } 2436 2437 /* 2438 * sip_reset: 2439 * 2440 * Perform a soft reset on the SiS 900. 2441 */ 2442 static bool 2443 sipcom_reset(struct sip_softc *sc) 2444 { 2445 bus_space_tag_t st = sc->sc_st; 2446 bus_space_handle_t sh = sc->sc_sh; 2447 int i; 2448 2449 bus_space_write_4(st, sh, SIP_IER, 0); 2450 bus_space_write_4(st, sh, SIP_IMR, 0); 2451 bus_space_write_4(st, sh, SIP_RFCR, 0); 2452 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2453 2454 for (i = 0; i < SIP_TIMEOUT; i++) { 2455 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2456 break; 2457 delay(2); 2458 } 2459 2460 if (i == SIP_TIMEOUT) { 2461 printf("%s: reset failed to complete\n", 2462 device_xname(sc->sc_dev)); 2463 return false; 2464 } 2465 2466 delay(1000); 2467 2468 if (sc->sc_gigabit) { 2469 /* 2470 * Set the general purpose I/O bits. Do it here in case we 2471 * need to have GPIO set up to talk to the media interface. 2472 */ 2473 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2474 delay(1000); 2475 } 2476 return true; 2477 } 2478 2479 static void 2480 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2481 { 2482 u_int32_t reg; 2483 bus_space_tag_t st = sc->sc_st; 2484 bus_space_handle_t sh = sc->sc_sh; 2485 /* 2486 * Initialize the VLAN/IP receive control register. 2487 * We enable checksum computation on all incoming 2488 * packets, and do not reject packets w/ bad checksums. 2489 */ 2490 reg = 0; 2491 if (capenable & 2492 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2493 reg |= VRCR_IPEN; 2494 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2495 reg |= VRCR_VTDEN|VRCR_VTREN; 2496 bus_space_write_4(st, sh, SIP_VRCR, reg); 2497 2498 /* 2499 * Initialize the VLAN/IP transmit control register. 2500 * We enable outgoing checksum computation on a 2501 * per-packet basis. 2502 */ 2503 reg = 0; 2504 if (capenable & 2505 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2506 reg |= VTCR_PPCHK; 2507 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2508 reg |= VTCR_VPPTI; 2509 bus_space_write_4(st, sh, SIP_VTCR, reg); 2510 2511 /* 2512 * If we're using VLANs, initialize the VLAN data register. 2513 * To understand why we bswap the VLAN Ethertype, see section 2514 * 4.2.36 of the DP83820 manual. 2515 */ 2516 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2517 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2518 } 2519 2520 /* 2521 * sip_init: [ ifnet interface function ] 2522 * 2523 * Initialize the interface. Must be called at splnet(). 2524 */ 2525 static int 2526 sipcom_init(struct ifnet *ifp) 2527 { 2528 struct sip_softc *sc = ifp->if_softc; 2529 bus_space_tag_t st = sc->sc_st; 2530 bus_space_handle_t sh = sc->sc_sh; 2531 struct sip_txsoft *txs; 2532 struct sip_rxsoft *rxs; 2533 struct sip_desc *sipd; 2534 int i, error = 0; 2535 2536 if (device_is_active(sc->sc_dev)) { 2537 /* 2538 * Cancel any pending I/O. 2539 */ 2540 sipcom_stop(ifp, 0); 2541 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2542 !device_is_active(sc->sc_dev)) 2543 return 0; 2544 2545 /* 2546 * Reset the chip to a known state. 2547 */ 2548 if (!sipcom_reset(sc)) 2549 return EBUSY; 2550 2551 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2552 /* 2553 * DP83815 manual, page 78: 2554 * 4.4 Recommended Registers Configuration 2555 * For optimum performance of the DP83815, version noted 2556 * as DP83815CVNG (SRR = 203h), the listed register 2557 * modifications must be followed in sequence... 2558 * 2559 * It's not clear if this should be 302h or 203h because that 2560 * chip name is listed as SRR 302h in the description of the 2561 * SRR register. However, my revision 302h DP83815 on the 2562 * Netgear FA311 purchased in 02/2001 needs these settings 2563 * to avoid tons of errors in AcceptPerfectMatch (non- 2564 * IFF_PROMISC) mode. I do not know if other revisions need 2565 * this set or not. [briggs -- 09 March 2001] 2566 * 2567 * Note that only the low-order 12 bits of 0xe4 are documented 2568 * and that this sets reserved bits in that register. 2569 */ 2570 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2571 2572 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2573 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2574 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2575 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2576 2577 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2578 } 2579 2580 /* 2581 * Initialize the transmit descriptor ring. 2582 */ 2583 for (i = 0; i < sc->sc_ntxdesc; i++) { 2584 sipd = &sc->sc_txdescs[i]; 2585 memset(sipd, 0, sizeof(struct sip_desc)); 2586 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2587 } 2588 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2589 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2590 sc->sc_txfree = sc->sc_ntxdesc; 2591 sc->sc_txnext = 0; 2592 sc->sc_txwin = 0; 2593 2594 /* 2595 * Initialize the transmit job descriptors. 2596 */ 2597 SIMPLEQ_INIT(&sc->sc_txfreeq); 2598 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2599 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2600 txs = &sc->sc_txsoft[i]; 2601 txs->txs_mbuf = NULL; 2602 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2603 } 2604 2605 /* 2606 * Initialize the receive descriptor and receive job 2607 * descriptor rings. 2608 */ 2609 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2610 rxs = &sc->sc_rxsoft[i]; 2611 if (rxs->rxs_mbuf == NULL) { 2612 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2613 printf("%s: unable to allocate or map rx " 2614 "buffer %d, error = %d\n", 2615 device_xname(sc->sc_dev), i, error); 2616 /* 2617 * XXX Should attempt to run with fewer receive 2618 * XXX buffers instead of just failing. 2619 */ 2620 sipcom_rxdrain(sc); 2621 goto out; 2622 } 2623 } else 2624 sip_init_rxdesc(sc, i); 2625 } 2626 sc->sc_rxptr = 0; 2627 sc->sc_rxdiscard = 0; 2628 sip_rxchain_reset(sc); 2629 2630 /* 2631 * Set the configuration register; it's already initialized 2632 * in sip_attach(). 2633 */ 2634 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2635 2636 /* 2637 * Initialize the prototype TXCFG register. 2638 */ 2639 if (sc->sc_gigabit) { 2640 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2641 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2642 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2643 SIP_SIS900_REV(sc, SIS_REV_960) || 2644 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2645 (sc->sc_cfg & CFG_EDBMASTEN)) { 2646 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2647 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2648 } else { 2649 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2650 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2651 } 2652 2653 sc->sc_txcfg |= TXCFG_ATP | 2654 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2655 sc->sc_tx_drain_thresh; 2656 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2657 2658 /* 2659 * Initialize the receive drain threshold if we have never 2660 * done so. 2661 */ 2662 if (sc->sc_rx_drain_thresh == 0) { 2663 /* 2664 * XXX This value should be tuned. This is set to the 2665 * maximum of 248 bytes, and we may be able to improve 2666 * performance by decreasing it (although we should never 2667 * set this value lower than 2; 14 bytes are required to 2668 * filter the packet). 2669 */ 2670 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2671 } 2672 2673 /* 2674 * Initialize the prototype RXCFG register. 2675 */ 2676 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2677 /* 2678 * Accept long packets (including FCS) so we can handle 2679 * 802.1q-tagged frames and jumbo frames properly. 2680 */ 2681 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2682 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2683 sc->sc_rxcfg |= RXCFG_ALP; 2684 2685 /* 2686 * Checksum offloading is disabled if the user selects an MTU 2687 * larger than 8109. (FreeBSD says 8152, but there is emperical 2688 * evidence that >8109 does not work on some boards, such as the 2689 * Planex GN-1000TE). 2690 */ 2691 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2692 (ifp->if_capenable & 2693 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2694 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2695 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2696 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2697 "disabled.\n", device_xname(sc->sc_dev)); 2698 ifp->if_capenable &= 2699 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2700 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2701 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2702 ifp->if_csum_flags_tx = 0; 2703 ifp->if_csum_flags_rx = 0; 2704 } 2705 2706 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2707 2708 if (sc->sc_gigabit) 2709 sipcom_dp83820_init(sc, ifp->if_capenable); 2710 2711 /* 2712 * Give the transmit and receive rings to the chip. 2713 */ 2714 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2715 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2716 2717 /* 2718 * Initialize the interrupt mask. 2719 */ 2720 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2721 sc->sc_bits.b_isr_sserr | 2722 sc->sc_bits.b_isr_rmabt | 2723 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2724 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2725 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2726 2727 /* Set up the receive filter. */ 2728 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2729 2730 /* 2731 * Tune sc_rx_flow_thresh. 2732 * XXX "More than 8KB" is too short for jumbo frames. 2733 * XXX TODO: Threshold value should be user-settable. 2734 */ 2735 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2736 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2737 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2738 2739 /* 2740 * Set the current media. Do this after initializing the prototype 2741 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2742 * control. 2743 */ 2744 if ((error = ether_mediachange(ifp)) != 0) 2745 goto out; 2746 2747 /* 2748 * Set the interrupt hold-off timer to 100us. 2749 */ 2750 if (sc->sc_gigabit) 2751 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2752 2753 /* 2754 * Enable interrupts. 2755 */ 2756 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2757 2758 /* 2759 * Start the transmit and receive processes. 2760 */ 2761 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2762 2763 /* 2764 * Start the one second MII clock. 2765 */ 2766 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2767 2768 /* 2769 * ...all done! 2770 */ 2771 ifp->if_flags |= IFF_RUNNING; 2772 ifp->if_flags &= ~IFF_OACTIVE; 2773 sc->sc_if_flags = ifp->if_flags; 2774 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2775 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2776 sc->sc_prev.if_capenable = ifp->if_capenable; 2777 2778 out: 2779 if (error) 2780 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2781 return (error); 2782 } 2783 2784 /* 2785 * sip_drain: 2786 * 2787 * Drain the receive queue. 2788 */ 2789 static void 2790 sipcom_rxdrain(struct sip_softc *sc) 2791 { 2792 struct sip_rxsoft *rxs; 2793 int i; 2794 2795 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2796 rxs = &sc->sc_rxsoft[i]; 2797 if (rxs->rxs_mbuf != NULL) { 2798 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2799 m_freem(rxs->rxs_mbuf); 2800 rxs->rxs_mbuf = NULL; 2801 } 2802 } 2803 } 2804 2805 /* 2806 * sip_stop: [ ifnet interface function ] 2807 * 2808 * Stop transmission on the interface. 2809 */ 2810 static void 2811 sipcom_stop(struct ifnet *ifp, int disable) 2812 { 2813 struct sip_softc *sc = ifp->if_softc; 2814 bus_space_tag_t st = sc->sc_st; 2815 bus_space_handle_t sh = sc->sc_sh; 2816 struct sip_txsoft *txs; 2817 u_int32_t cmdsts = 0; /* DEBUG */ 2818 2819 /* 2820 * Stop the one second clock. 2821 */ 2822 callout_stop(&sc->sc_tick_ch); 2823 2824 /* Down the MII. */ 2825 mii_down(&sc->sc_mii); 2826 2827 if (device_is_active(sc->sc_dev)) { 2828 /* 2829 * Disable interrupts. 2830 */ 2831 bus_space_write_4(st, sh, SIP_IER, 0); 2832 2833 /* 2834 * Stop receiver and transmitter. 2835 */ 2836 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2837 } 2838 2839 /* 2840 * Release any queued transmit buffers. 2841 */ 2842 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2843 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2844 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2845 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2846 CMDSTS_INTR) == 0) 2847 printf("%s: sip_stop: last descriptor does not " 2848 "have INTR bit set\n", device_xname(sc->sc_dev)); 2849 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2850 #ifdef DIAGNOSTIC 2851 if (txs->txs_mbuf == NULL) { 2852 printf("%s: dirty txsoft with no mbuf chain\n", 2853 device_xname(sc->sc_dev)); 2854 panic("sip_stop"); 2855 } 2856 #endif 2857 cmdsts |= /* DEBUG */ 2858 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2859 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2860 m_freem(txs->txs_mbuf); 2861 txs->txs_mbuf = NULL; 2862 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2863 } 2864 2865 /* 2866 * Mark the interface down and cancel the watchdog timer. 2867 */ 2868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2869 ifp->if_timer = 0; 2870 2871 if (disable) 2872 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2873 2874 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2875 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2876 printf("%s: sip_stop: no INTR bits set in dirty tx " 2877 "descriptors\n", device_xname(sc->sc_dev)); 2878 } 2879 2880 /* 2881 * sip_read_eeprom: 2882 * 2883 * Read data from the serial EEPROM. 2884 */ 2885 static void 2886 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2887 u_int16_t *data) 2888 { 2889 bus_space_tag_t st = sc->sc_st; 2890 bus_space_handle_t sh = sc->sc_sh; 2891 u_int16_t reg; 2892 int i, x; 2893 2894 for (i = 0; i < wordcnt; i++) { 2895 /* Send CHIP SELECT. */ 2896 reg = EROMAR_EECS; 2897 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2898 2899 /* Shift in the READ opcode. */ 2900 for (x = 3; x > 0; x--) { 2901 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2902 reg |= EROMAR_EEDI; 2903 else 2904 reg &= ~EROMAR_EEDI; 2905 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2906 bus_space_write_4(st, sh, SIP_EROMAR, 2907 reg | EROMAR_EESK); 2908 delay(4); 2909 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2910 delay(4); 2911 } 2912 2913 /* Shift in address. */ 2914 for (x = 6; x > 0; x--) { 2915 if ((word + i) & (1 << (x - 1))) 2916 reg |= EROMAR_EEDI; 2917 else 2918 reg &= ~EROMAR_EEDI; 2919 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2920 bus_space_write_4(st, sh, SIP_EROMAR, 2921 reg | EROMAR_EESK); 2922 delay(4); 2923 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2924 delay(4); 2925 } 2926 2927 /* Shift out data. */ 2928 reg = EROMAR_EECS; 2929 data[i] = 0; 2930 for (x = 16; x > 0; x--) { 2931 bus_space_write_4(st, sh, SIP_EROMAR, 2932 reg | EROMAR_EESK); 2933 delay(4); 2934 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2935 data[i] |= (1 << (x - 1)); 2936 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2937 delay(4); 2938 } 2939 2940 /* Clear CHIP SELECT. */ 2941 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2942 delay(4); 2943 } 2944 } 2945 2946 /* 2947 * sipcom_add_rxbuf: 2948 * 2949 * Add a receive buffer to the indicated descriptor. 2950 */ 2951 static int 2952 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2953 { 2954 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2955 struct mbuf *m; 2956 int error; 2957 2958 MGETHDR(m, M_DONTWAIT, MT_DATA); 2959 if (m == NULL) 2960 return (ENOBUFS); 2961 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2962 2963 MCLGET(m, M_DONTWAIT); 2964 if ((m->m_flags & M_EXT) == 0) { 2965 m_freem(m); 2966 return (ENOBUFS); 2967 } 2968 2969 /* XXX I don't believe this is necessary. --dyoung */ 2970 if (sc->sc_gigabit) 2971 m->m_len = sc->sc_parm->p_rxbuf_len; 2972 2973 if (rxs->rxs_mbuf != NULL) 2974 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2975 2976 rxs->rxs_mbuf = m; 2977 2978 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2979 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2980 BUS_DMA_READ|BUS_DMA_NOWAIT); 2981 if (error) { 2982 printf("%s: can't load rx DMA map %d, error = %d\n", 2983 device_xname(sc->sc_dev), idx, error); 2984 panic("%s", __func__); /* XXX */ 2985 } 2986 2987 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2988 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2989 2990 sip_init_rxdesc(sc, idx); 2991 2992 return (0); 2993 } 2994 2995 /* 2996 * sip_sis900_set_filter: 2997 * 2998 * Set up the receive filter. 2999 */ 3000 static void 3001 sipcom_sis900_set_filter(struct sip_softc *sc) 3002 { 3003 bus_space_tag_t st = sc->sc_st; 3004 bus_space_handle_t sh = sc->sc_sh; 3005 struct ethercom *ec = &sc->sc_ethercom; 3006 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3007 struct ether_multi *enm; 3008 const u_int8_t *cp; 3009 struct ether_multistep step; 3010 u_int32_t crc, mchash[16]; 3011 3012 /* 3013 * Initialize the prototype RFCR. 3014 */ 3015 sc->sc_rfcr = RFCR_RFEN; 3016 if (ifp->if_flags & IFF_BROADCAST) 3017 sc->sc_rfcr |= RFCR_AAB; 3018 if (ifp->if_flags & IFF_PROMISC) { 3019 sc->sc_rfcr |= RFCR_AAP; 3020 goto allmulti; 3021 } 3022 3023 /* 3024 * Set up the multicast address filter by passing all multicast 3025 * addresses through a CRC generator, and then using the high-order 3026 * 6 bits as an index into the 128 bit multicast hash table (only 3027 * the lower 16 bits of each 32 bit multicast hash register are 3028 * valid). The high order bits select the register, while the 3029 * rest of the bits select the bit within the register. 3030 */ 3031 3032 memset(mchash, 0, sizeof(mchash)); 3033 3034 /* 3035 * SiS900 (at least SiS963) requires us to register the address of 3036 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3037 */ 3038 crc = 0x0ed423f9; 3039 3040 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3041 SIP_SIS900_REV(sc, SIS_REV_960) || 3042 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3043 /* Just want the 8 most significant bits. */ 3044 crc >>= 24; 3045 } else { 3046 /* Just want the 7 most significant bits. */ 3047 crc >>= 25; 3048 } 3049 3050 /* Set the corresponding bit in the hash table. */ 3051 mchash[crc >> 4] |= 1 << (crc & 0xf); 3052 3053 ETHER_FIRST_MULTI(step, ec, enm); 3054 while (enm != NULL) { 3055 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3056 /* 3057 * We must listen to a range of multicast addresses. 3058 * For now, just accept all multicasts, rather than 3059 * trying to set only those filter bits needed to match 3060 * the range. (At this time, the only use of address 3061 * ranges is for IP multicast routing, for which the 3062 * range is big enough to require all bits set.) 3063 */ 3064 goto allmulti; 3065 } 3066 3067 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3068 3069 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3070 SIP_SIS900_REV(sc, SIS_REV_960) || 3071 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3072 /* Just want the 8 most significant bits. */ 3073 crc >>= 24; 3074 } else { 3075 /* Just want the 7 most significant bits. */ 3076 crc >>= 25; 3077 } 3078 3079 /* Set the corresponding bit in the hash table. */ 3080 mchash[crc >> 4] |= 1 << (crc & 0xf); 3081 3082 ETHER_NEXT_MULTI(step, enm); 3083 } 3084 3085 ifp->if_flags &= ~IFF_ALLMULTI; 3086 goto setit; 3087 3088 allmulti: 3089 ifp->if_flags |= IFF_ALLMULTI; 3090 sc->sc_rfcr |= RFCR_AAM; 3091 3092 setit: 3093 #define FILTER_EMIT(addr, data) \ 3094 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3095 delay(1); \ 3096 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3097 delay(1) 3098 3099 /* 3100 * Disable receive filter, and program the node address. 3101 */ 3102 cp = CLLADDR(ifp->if_sadl); 3103 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3104 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3105 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3106 3107 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3108 /* 3109 * Program the multicast hash table. 3110 */ 3111 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3112 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3113 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3114 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3115 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3116 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3117 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3118 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3119 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3120 SIP_SIS900_REV(sc, SIS_REV_960) || 3121 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3122 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3123 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3124 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3125 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3126 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3127 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3128 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3129 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3130 } 3131 } 3132 #undef FILTER_EMIT 3133 3134 /* 3135 * Re-enable the receiver filter. 3136 */ 3137 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3138 } 3139 3140 /* 3141 * sip_dp83815_set_filter: 3142 * 3143 * Set up the receive filter. 3144 */ 3145 static void 3146 sipcom_dp83815_set_filter(struct sip_softc *sc) 3147 { 3148 bus_space_tag_t st = sc->sc_st; 3149 bus_space_handle_t sh = sc->sc_sh; 3150 struct ethercom *ec = &sc->sc_ethercom; 3151 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3152 struct ether_multi *enm; 3153 const u_int8_t *cp; 3154 struct ether_multistep step; 3155 u_int32_t crc, hash, slot, bit; 3156 #define MCHASH_NWORDS_83820 128 3157 #define MCHASH_NWORDS_83815 32 3158 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3159 u_int16_t mchash[MCHASH_NWORDS]; 3160 int i; 3161 3162 /* 3163 * Initialize the prototype RFCR. 3164 * Enable the receive filter, and accept on 3165 * Perfect (destination address) Match 3166 * If IFF_BROADCAST, also accept all broadcast packets. 3167 * If IFF_PROMISC, accept all unicast packets (and later, set 3168 * IFF_ALLMULTI and accept all multicast, too). 3169 */ 3170 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3171 if (ifp->if_flags & IFF_BROADCAST) 3172 sc->sc_rfcr |= RFCR_AAB; 3173 if (ifp->if_flags & IFF_PROMISC) { 3174 sc->sc_rfcr |= RFCR_AAP; 3175 goto allmulti; 3176 } 3177 3178 /* 3179 * Set up the DP83820/DP83815 multicast address filter by 3180 * passing all multicast addresses through a CRC generator, 3181 * and then using the high-order 11/9 bits as an index into 3182 * the 2048/512 bit multicast hash table. The high-order 3183 * 7/5 bits select the slot, while the low-order 4 bits 3184 * select the bit within the slot. Note that only the low 3185 * 16-bits of each filter word are used, and there are 3186 * 128/32 filter words. 3187 */ 3188 3189 memset(mchash, 0, sizeof(mchash)); 3190 3191 ifp->if_flags &= ~IFF_ALLMULTI; 3192 ETHER_FIRST_MULTI(step, ec, enm); 3193 if (enm == NULL) 3194 goto setit; 3195 while (enm != NULL) { 3196 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3197 /* 3198 * We must listen to a range of multicast addresses. 3199 * For now, just accept all multicasts, rather than 3200 * trying to set only those filter bits needed to match 3201 * the range. (At this time, the only use of address 3202 * ranges is for IP multicast routing, for which the 3203 * range is big enough to require all bits set.) 3204 */ 3205 goto allmulti; 3206 } 3207 3208 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3209 3210 if (sc->sc_gigabit) { 3211 /* Just want the 11 most significant bits. */ 3212 hash = crc >> 21; 3213 } else { 3214 /* Just want the 9 most significant bits. */ 3215 hash = crc >> 23; 3216 } 3217 3218 slot = hash >> 4; 3219 bit = hash & 0xf; 3220 3221 /* Set the corresponding bit in the hash table. */ 3222 mchash[slot] |= 1 << bit; 3223 3224 ETHER_NEXT_MULTI(step, enm); 3225 } 3226 sc->sc_rfcr |= RFCR_MHEN; 3227 goto setit; 3228 3229 allmulti: 3230 ifp->if_flags |= IFF_ALLMULTI; 3231 sc->sc_rfcr |= RFCR_AAM; 3232 3233 setit: 3234 #define FILTER_EMIT(addr, data) \ 3235 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3236 delay(1); \ 3237 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3238 delay(1) 3239 3240 /* 3241 * Disable receive filter, and program the node address. 3242 */ 3243 cp = CLLADDR(ifp->if_sadl); 3244 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3245 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3246 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3247 3248 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3249 int nwords = 3250 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3251 /* 3252 * Program the multicast hash table. 3253 */ 3254 for (i = 0; i < nwords; i++) { 3255 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3256 } 3257 } 3258 #undef FILTER_EMIT 3259 #undef MCHASH_NWORDS 3260 #undef MCHASH_NWORDS_83815 3261 #undef MCHASH_NWORDS_83820 3262 3263 /* 3264 * Re-enable the receiver filter. 3265 */ 3266 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3267 } 3268 3269 /* 3270 * sip_dp83820_mii_readreg: [mii interface function] 3271 * 3272 * Read a PHY register on the MII of the DP83820. 3273 */ 3274 static int 3275 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3276 { 3277 struct sip_softc *sc = device_private(self); 3278 3279 if (sc->sc_cfg & CFG_TBI_EN) { 3280 bus_addr_t tbireg; 3281 int rv; 3282 3283 if (phy != 0) 3284 return (0); 3285 3286 switch (reg) { 3287 case MII_BMCR: tbireg = SIP_TBICR; break; 3288 case MII_BMSR: tbireg = SIP_TBISR; break; 3289 case MII_ANAR: tbireg = SIP_TANAR; break; 3290 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3291 case MII_ANER: tbireg = SIP_TANER; break; 3292 case MII_EXTSR: 3293 /* 3294 * Don't even bother reading the TESR register. 3295 * The manual documents that the device has 3296 * 1000baseX full/half capability, but the 3297 * register itself seems read back 0 on some 3298 * boards. Just hard-code the result. 3299 */ 3300 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3301 3302 default: 3303 return (0); 3304 } 3305 3306 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3307 if (tbireg == SIP_TBISR) { 3308 /* LINK and ACOMP are switched! */ 3309 int val = rv; 3310 3311 rv = 0; 3312 if (val & TBISR_MR_LINK_STATUS) 3313 rv |= BMSR_LINK; 3314 if (val & TBISR_MR_AN_COMPLETE) 3315 rv |= BMSR_ACOMP; 3316 3317 /* 3318 * The manual claims this register reads back 0 3319 * on hard and soft reset. But we want to let 3320 * the gentbi driver know that we support auto- 3321 * negotiation, so hard-code this bit in the 3322 * result. 3323 */ 3324 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3325 } 3326 3327 return (rv); 3328 } 3329 3330 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3331 } 3332 3333 /* 3334 * sip_dp83820_mii_writereg: [mii interface function] 3335 * 3336 * Write a PHY register on the MII of the DP83820. 3337 */ 3338 static void 3339 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3340 { 3341 struct sip_softc *sc = device_private(self); 3342 3343 if (sc->sc_cfg & CFG_TBI_EN) { 3344 bus_addr_t tbireg; 3345 3346 if (phy != 0) 3347 return; 3348 3349 switch (reg) { 3350 case MII_BMCR: tbireg = SIP_TBICR; break; 3351 case MII_ANAR: tbireg = SIP_TANAR; break; 3352 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3353 default: 3354 return; 3355 } 3356 3357 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3358 return; 3359 } 3360 3361 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3362 } 3363 3364 /* 3365 * sip_dp83820_mii_statchg: [mii interface function] 3366 * 3367 * Callback from MII layer when media changes. 3368 */ 3369 static void 3370 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3371 { 3372 struct sip_softc *sc = ifp->if_softc; 3373 struct mii_data *mii = &sc->sc_mii; 3374 u_int32_t cfg, pcr; 3375 3376 /* 3377 * Get flow control negotiation result. 3378 */ 3379 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3380 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3381 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3382 mii->mii_media_active &= ~IFM_ETH_FMASK; 3383 } 3384 3385 /* 3386 * Update TXCFG for full-duplex operation. 3387 */ 3388 if ((mii->mii_media_active & IFM_FDX) != 0) 3389 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3390 else 3391 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3392 3393 /* 3394 * Update RXCFG for full-duplex or loopback. 3395 */ 3396 if ((mii->mii_media_active & IFM_FDX) != 0 || 3397 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3398 sc->sc_rxcfg |= RXCFG_ATX; 3399 else 3400 sc->sc_rxcfg &= ~RXCFG_ATX; 3401 3402 /* 3403 * Update CFG for MII/GMII. 3404 */ 3405 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3406 cfg = sc->sc_cfg | CFG_MODE_1000; 3407 else 3408 cfg = sc->sc_cfg; 3409 3410 /* 3411 * 802.3x flow control. 3412 */ 3413 pcr = 0; 3414 if (sc->sc_flowflags & IFM_FLOW) { 3415 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3416 pcr |= sc->sc_rx_flow_thresh; 3417 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3418 pcr |= PCR_PSEN | PCR_PS_MCAST; 3419 } 3420 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3423 sc->sc_txcfg); 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3425 sc->sc_rxcfg); 3426 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3427 } 3428 3429 /* 3430 * sip_mii_bitbang_read: [mii bit-bang interface function] 3431 * 3432 * Read the MII serial port for the MII bit-bang module. 3433 */ 3434 static u_int32_t 3435 sipcom_mii_bitbang_read(device_t self) 3436 { 3437 struct sip_softc *sc = device_private(self); 3438 3439 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3440 } 3441 3442 /* 3443 * sip_mii_bitbang_write: [mii big-bang interface function] 3444 * 3445 * Write the MII serial port for the MII bit-bang module. 3446 */ 3447 static void 3448 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3449 { 3450 struct sip_softc *sc = device_private(self); 3451 3452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3453 } 3454 3455 /* 3456 * sip_sis900_mii_readreg: [mii interface function] 3457 * 3458 * Read a PHY register on the MII. 3459 */ 3460 static int 3461 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3462 { 3463 struct sip_softc *sc = device_private(self); 3464 u_int32_t enphy; 3465 3466 /* 3467 * The PHY of recent SiS chipsets is accessed through bitbang 3468 * operations. 3469 */ 3470 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3471 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3472 phy, reg); 3473 3474 #ifndef SIS900_MII_RESTRICT 3475 /* 3476 * The SiS 900 has only an internal PHY on the MII. Only allow 3477 * MII address 0. 3478 */ 3479 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3480 return (0); 3481 #endif 3482 3483 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3484 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3485 ENPHY_RWCMD | ENPHY_ACCESS); 3486 do { 3487 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3488 } while (enphy & ENPHY_ACCESS); 3489 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3490 } 3491 3492 /* 3493 * sip_sis900_mii_writereg: [mii interface function] 3494 * 3495 * Write a PHY register on the MII. 3496 */ 3497 static void 3498 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3499 { 3500 struct sip_softc *sc = device_private(self); 3501 u_int32_t enphy; 3502 3503 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3504 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3505 phy, reg, val); 3506 return; 3507 } 3508 3509 #ifndef SIS900_MII_RESTRICT 3510 /* 3511 * The SiS 900 has only an internal PHY on the MII. Only allow 3512 * MII address 0. 3513 */ 3514 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3515 return; 3516 #endif 3517 3518 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3519 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3520 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3521 do { 3522 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3523 } while (enphy & ENPHY_ACCESS); 3524 } 3525 3526 /* 3527 * sip_sis900_mii_statchg: [mii interface function] 3528 * 3529 * Callback from MII layer when media changes. 3530 */ 3531 static void 3532 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3533 { 3534 struct sip_softc *sc = ifp->if_softc; 3535 struct mii_data *mii = &sc->sc_mii; 3536 u_int32_t flowctl; 3537 3538 /* 3539 * Get flow control negotiation result. 3540 */ 3541 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3542 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3543 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3544 mii->mii_media_active &= ~IFM_ETH_FMASK; 3545 } 3546 3547 /* 3548 * Update TXCFG for full-duplex operation. 3549 */ 3550 if ((mii->mii_media_active & IFM_FDX) != 0) 3551 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3552 else 3553 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3554 3555 /* 3556 * Update RXCFG for full-duplex or loopback. 3557 */ 3558 if ((mii->mii_media_active & IFM_FDX) != 0 || 3559 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3560 sc->sc_rxcfg |= RXCFG_ATX; 3561 else 3562 sc->sc_rxcfg &= ~RXCFG_ATX; 3563 3564 /* 3565 * Update IMR for use of 802.3x flow control. 3566 */ 3567 if (sc->sc_flowflags & IFM_FLOW) { 3568 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3569 flowctl = FLOWCTL_FLOWEN; 3570 } else { 3571 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3572 flowctl = 0; 3573 } 3574 3575 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3576 sc->sc_txcfg); 3577 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3578 sc->sc_rxcfg); 3579 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3580 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3581 } 3582 3583 /* 3584 * sip_dp83815_mii_readreg: [mii interface function] 3585 * 3586 * Read a PHY register on the MII. 3587 */ 3588 static int 3589 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3590 { 3591 struct sip_softc *sc = device_private(self); 3592 u_int32_t val; 3593 3594 /* 3595 * The DP83815 only has an internal PHY. Only allow 3596 * MII address 0. 3597 */ 3598 if (phy != 0) 3599 return (0); 3600 3601 /* 3602 * Apparently, after a reset, the DP83815 can take a while 3603 * to respond. During this recovery period, the BMSR returns 3604 * a value of 0. Catch this -- it's not supposed to happen 3605 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3606 * PHY to come back to life. 3607 * 3608 * This works out because the BMSR is the first register 3609 * read during the PHY probe process. 3610 */ 3611 do { 3612 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3613 } while (reg == MII_BMSR && val == 0); 3614 3615 return (val & 0xffff); 3616 } 3617 3618 /* 3619 * sip_dp83815_mii_writereg: [mii interface function] 3620 * 3621 * Write a PHY register to the MII. 3622 */ 3623 static void 3624 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3625 { 3626 struct sip_softc *sc = device_private(self); 3627 3628 /* 3629 * The DP83815 only has an internal PHY. Only allow 3630 * MII address 0. 3631 */ 3632 if (phy != 0) 3633 return; 3634 3635 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3636 } 3637 3638 /* 3639 * sip_dp83815_mii_statchg: [mii interface function] 3640 * 3641 * Callback from MII layer when media changes. 3642 */ 3643 static void 3644 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3645 { 3646 struct sip_softc *sc = ifp->if_softc; 3647 3648 /* 3649 * Update TXCFG for full-duplex operation. 3650 */ 3651 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3652 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3653 else 3654 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3655 3656 /* 3657 * Update RXCFG for full-duplex or loopback. 3658 */ 3659 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3660 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3661 sc->sc_rxcfg |= RXCFG_ATX; 3662 else 3663 sc->sc_rxcfg &= ~RXCFG_ATX; 3664 3665 /* 3666 * XXX 802.3x flow control. 3667 */ 3668 3669 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3670 sc->sc_txcfg); 3671 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3672 sc->sc_rxcfg); 3673 3674 /* 3675 * Some DP83815s experience problems when used with short 3676 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3677 * sequence adjusts the DSP's signal attenuation to fix the 3678 * problem. 3679 */ 3680 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3681 uint32_t reg; 3682 3683 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3684 3685 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3686 reg &= 0x0fff; 3687 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3688 delay(100); 3689 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3690 reg &= 0x00ff; 3691 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3692 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3693 0x00e8); 3694 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3695 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3696 reg | 0x20); 3697 } 3698 3699 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3700 } 3701 } 3702 3703 static void 3704 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3705 const struct pci_attach_args *pa, u_int8_t *enaddr) 3706 { 3707 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3708 u_int8_t cksum, *e, match; 3709 int i; 3710 3711 /* 3712 * EEPROM data format for the DP83820 can be found in 3713 * the DP83820 manual, section 4.2.4. 3714 */ 3715 3716 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3717 3718 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3719 match = ~(match - 1); 3720 3721 cksum = 0x55; 3722 e = (u_int8_t *) eeprom_data; 3723 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3724 cksum += *e++; 3725 3726 if (cksum != match) 3727 printf("%s: Checksum (%x) mismatch (%x)", 3728 device_xname(sc->sc_dev), cksum, match); 3729 3730 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3731 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3732 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3733 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3734 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3735 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3736 } 3737 3738 static void 3739 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3740 { 3741 int i; 3742 3743 /* 3744 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3745 * a reason, but I don't know it. 3746 */ 3747 for (i = 0; i < 10; i++) 3748 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3749 } 3750 3751 static void 3752 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3753 const struct pci_attach_args *pa, u_int8_t *enaddr) 3754 { 3755 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3756 3757 switch (sc->sc_rev) { 3758 case SIS_REV_630S: 3759 case SIS_REV_630E: 3760 case SIS_REV_630EA1: 3761 case SIS_REV_630ET: 3762 case SIS_REV_635: 3763 /* 3764 * The MAC address for the on-board Ethernet of 3765 * the SiS 630 chipset is in the NVRAM. Kick 3766 * the chip into re-loading it from NVRAM, and 3767 * read the MAC address out of the filter registers. 3768 */ 3769 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3770 3771 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3772 RFCR_RFADDR_NODE0); 3773 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3774 0xffff; 3775 3776 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3777 RFCR_RFADDR_NODE2); 3778 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3779 0xffff; 3780 3781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3782 RFCR_RFADDR_NODE4); 3783 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3784 0xffff; 3785 break; 3786 3787 case SIS_REV_960: 3788 { 3789 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3790 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3791 3792 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3793 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3794 3795 int waittime, i; 3796 3797 /* Allow to read EEPROM from LAN. It is shared 3798 * between a 1394 controller and the NIC and each 3799 * time we access it, we need to set SIS_EECMD_REQ. 3800 */ 3801 SIS_SET_EROMAR(sc, EROMAR_REQ); 3802 3803 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3804 /* Force EEPROM to idle state. */ 3805 3806 /* 3807 * XXX-cube This is ugly. I'll look for docs about it. 3808 */ 3809 SIS_SET_EROMAR(sc, EROMAR_EECS); 3810 sipcom_sis900_eeprom_delay(sc); 3811 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3812 SIS_SET_EROMAR(sc, EROMAR_EESK); 3813 sipcom_sis900_eeprom_delay(sc); 3814 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3815 sipcom_sis900_eeprom_delay(sc); 3816 } 3817 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3818 sipcom_sis900_eeprom_delay(sc); 3819 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3820 3821 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3822 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3823 sizeof(myea) / sizeof(myea[0]), myea); 3824 break; 3825 } 3826 DELAY(1); 3827 } 3828 3829 /* 3830 * Set SIS_EECTL_CLK to high, so a other master 3831 * can operate on the i2c bus. 3832 */ 3833 SIS_SET_EROMAR(sc, EROMAR_EESK); 3834 3835 /* Refuse EEPROM access by LAN */ 3836 SIS_SET_EROMAR(sc, EROMAR_DONE); 3837 } break; 3838 3839 default: 3840 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3841 sizeof(myea) / sizeof(myea[0]), myea); 3842 } 3843 3844 enaddr[0] = myea[0] & 0xff; 3845 enaddr[1] = myea[0] >> 8; 3846 enaddr[2] = myea[1] & 0xff; 3847 enaddr[3] = myea[1] >> 8; 3848 enaddr[4] = myea[2] & 0xff; 3849 enaddr[5] = myea[2] >> 8; 3850 } 3851 3852 /* Table and macro to bit-reverse an octet. */ 3853 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3854 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3855 3856 static void 3857 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3858 const struct pci_attach_args *pa, u_int8_t *enaddr) 3859 { 3860 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3861 u_int8_t cksum, *e, match; 3862 int i; 3863 3864 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3865 sizeof(eeprom_data[0]), eeprom_data); 3866 3867 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3868 match = ~(match - 1); 3869 3870 cksum = 0x55; 3871 e = (u_int8_t *) eeprom_data; 3872 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3873 cksum += *e++; 3874 } 3875 if (cksum != match) { 3876 printf("%s: Checksum (%x) mismatch (%x)", 3877 device_xname(sc->sc_dev), cksum, match); 3878 } 3879 3880 /* 3881 * Unrolled because it makes slightly more sense this way. 3882 * The DP83815 stores the MAC address in bit 0 of word 6 3883 * through bit 15 of word 8. 3884 */ 3885 ea = &eeprom_data[6]; 3886 enaddr[0] = ((*ea & 0x1) << 7); 3887 ea++; 3888 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3889 enaddr[1] = ((*ea & 0x1FE) >> 1); 3890 enaddr[2] = ((*ea & 0x1) << 7); 3891 ea++; 3892 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3893 enaddr[3] = ((*ea & 0x1FE) >> 1); 3894 enaddr[4] = ((*ea & 0x1) << 7); 3895 ea++; 3896 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3897 enaddr[5] = ((*ea & 0x1FE) >> 1); 3898 3899 /* 3900 * In case that's not weird enough, we also need to reverse 3901 * the bits in each byte. This all actually makes more sense 3902 * if you think about the EEPROM storage as an array of bits 3903 * being shifted into bytes, but that's not how we're looking 3904 * at it here... 3905 */ 3906 for (i = 0; i < 6 ;i++) 3907 enaddr[i] = bbr(enaddr[i]); 3908 } 3909 3910 /* 3911 * sip_mediastatus: [ifmedia interface function] 3912 * 3913 * Get the current interface media status. 3914 */ 3915 static void 3916 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3917 { 3918 struct sip_softc *sc = ifp->if_softc; 3919 3920 if (!device_is_active(sc->sc_dev)) { 3921 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3922 ifmr->ifm_status = 0; 3923 return; 3924 } 3925 ether_mediastatus(ifp, ifmr); 3926 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3927 sc->sc_flowflags; 3928 } 3929
Indexes created Tue Sep 30 17:09:57 GMT 2025