if_sip.c revision 1.165.6.1
1 /* $NetBSD: if_sip.c,v 1.165.6.1 2017/05/11 02:58:38 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.165.6.1 2017/05/11 02:58:38 pgoyette Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rndsource.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int); 587 static void sipcom_dp83820_mii_writereg(device_t, int, int, int); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int); 591 static void sipcom_sis900_mii_writereg(device_t, int, int, int); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int); 595 static void sipcom_dp83815_mii_writereg(device_t, int, int, int); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int); 622 void (*sipv_mii_writereg)(device_t, int, int, int); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA621 */ 741 { 0x1385, 0x621a }, 742 743 /* Netgear GA622 */ 744 { 0x1385, 0x622a }, 745 746 /* SMC EZ Card 1000 (9462TX) */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, cfdata_t cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 rnd_detach_source(&sc->rnd_source); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 918 919 /*FALLTHROUGH*/ 920 case SIP_ATTACH_CREATE_RXMAP: 921 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 922 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_rxsoft[i].rxs_dmamap); 925 } 926 /*FALLTHROUGH*/ 927 case SIP_ATTACH_CREATE_TXMAP: 928 for (i = 0; i < SIP_TXQUEUELEN; i++) { 929 if (sc->sc_txsoft[i].txs_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txsoft[i].txs_dmamap); 932 } 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_LOAD_MAP: 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_CREATE_MAP: 938 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_MAP_MEM: 941 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 942 sizeof(struct sip_control_data)); 943 /*FALLTHROUGH*/ 944 case SIP_ATTACH_ALLOC_MEM: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_INTR: 948 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_MAP: 951 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 952 break; 953 default: 954 break; 955 } 956 return; 957 } 958 959 static bool 960 sipcom_resume(device_t self, const pmf_qual_t *qual) 961 { 962 struct sip_softc *sc = device_private(self); 963 964 return sipcom_reset(sc); 965 } 966 967 static bool 968 sipcom_suspend(device_t self, const pmf_qual_t *qual) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 sipcom_rxdrain(sc); 973 return true; 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = device_private(self); 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t csr; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 char intrbuf[PCI_INTRSTR_LEN]; 998 999 callout_init(&sc->sc_tick_ch, 0); 1000 1001 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1002 if (sip == NULL) { 1003 aprint_error("\n"); 1004 panic("%s: impossible", __func__); 1005 } 1006 sc->sc_dev = self; 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 aprint_naive("\n"); 1027 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1028 1029 sc->sc_model = sip; 1030 1031 /* 1032 * XXX Work-around broken PXE firmware on some boards. 1033 * 1034 * The DP83815 shares an address decoder with the MEM BAR 1035 * and the ROM BAR. Make sure the ROM BAR is disabled, 1036 * so that memory mapped access works. 1037 */ 1038 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1040 ~PCI_MAPREG_ROM_ENABLE); 1041 1042 /* 1043 * Map the device. 1044 */ 1045 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1046 PCI_MAPREG_TYPE_IO, 0, 1047 &iot, &ioh, NULL, &iosz) == 0); 1048 if (sc->sc_gigabit) { 1049 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1050 switch (memtype) { 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1052 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1053 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1054 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1055 break; 1056 default: 1057 memh_valid = 0; 1058 } 1059 } else { 1060 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1061 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1062 &memt, &memh, NULL, &memsz) == 0); 1063 } 1064 1065 if (memh_valid) { 1066 sc->sc_st = memt; 1067 sc->sc_sh = memh; 1068 sc->sc_sz = memsz; 1069 } else if (ioh_valid) { 1070 sc->sc_st = iot; 1071 sc->sc_sh = ioh; 1072 sc->sc_sz = iosz; 1073 } else { 1074 aprint_error_dev(self, "unable to map device registers\n"); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 csr | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1092 if (error != 0 && error != EOPNOTSUPP) { 1093 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1094 return; 1095 } 1096 1097 /* 1098 * Map and establish our interrupt. 1099 */ 1100 if (pci_intr_map(pa, &ih)) { 1101 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1102 return; 1103 } 1104 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1105 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1106 device_xname(self)); 1107 if (sc->sc_ih == NULL) { 1108 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1109 if (intrstr != NULL) 1110 aprint_error(" at %s", intrstr); 1111 aprint_error("\n"); 1112 sipcom_do_detach(self, SIP_ATTACH_MAP); 1113 return; 1114 } 1115 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1116 1117 SIMPLEQ_INIT(&sc->sc_txfreeq); 1118 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1119 1120 /* 1121 * Allocate the control data structures, and create and load the 1122 * DMA map for it. 1123 */ 1124 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1125 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1126 &rseg, 0)) != 0) { 1127 aprint_error_dev(sc->sc_dev, 1128 "unable to allocate control data, error = %d\n", error); 1129 sipcom_do_detach(self, SIP_ATTACH_INTR); 1130 return; 1131 } 1132 1133 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1134 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1135 BUS_DMA_COHERENT)) != 0) { 1136 aprint_error_dev(sc->sc_dev, 1137 "unable to map control data, error = %d\n", error); 1138 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1139 } 1140 1141 if ((error = bus_dmamap_create(sc->sc_dmat, 1142 sizeof(struct sip_control_data), 1, 1143 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1144 aprint_error_dev(self, "unable to create control data DMA map" 1145 ", error = %d\n", error); 1146 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1147 } 1148 1149 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1150 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1151 0)) != 0) { 1152 aprint_error_dev(self, "unable to load control data DMA map" 1153 ", error = %d\n", error); 1154 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1155 } 1156 1157 /* 1158 * Create the transmit buffer DMA maps. 1159 */ 1160 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1161 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1162 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1163 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1164 aprint_error_dev(self, "unable to create tx DMA map %d" 1165 ", error = %d\n", i, error); 1166 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1167 } 1168 } 1169 1170 /* 1171 * Create the receive buffer DMA maps. 1172 */ 1173 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1174 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1175 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1176 aprint_error_dev(self, "unable to create rx DMA map %d" 1177 ", error = %d\n", i, error); 1178 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1179 } 1180 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1181 } 1182 1183 /* 1184 * Reset the chip to a known state. 1185 */ 1186 sipcom_reset(sc); 1187 1188 /* 1189 * Read the Ethernet address from the EEPROM. This might 1190 * also fetch other stuff from the EEPROM and stash it 1191 * in the softc. 1192 */ 1193 sc->sc_cfg = 0; 1194 if (!sc->sc_gigabit) { 1195 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1196 SIP_SIS900_REV(sc,SIS_REV_900B)) 1197 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1198 1199 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1200 SIP_SIS900_REV(sc,SIS_REV_960) || 1201 SIP_SIS900_REV(sc,SIS_REV_900B)) 1202 sc->sc_cfg |= 1203 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1204 CFG_EDBMASTEN); 1205 } 1206 1207 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1208 1209 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1210 1211 /* 1212 * Initialize the configuration register: aggressive PCI 1213 * bus request algorithm, default backoff, default OW timer, 1214 * default parity error detection. 1215 * 1216 * NOTE: "Big endian mode" is useless on the SiS900 and 1217 * friends -- it affects packet data, not descriptors. 1218 */ 1219 if (sc->sc_gigabit) 1220 sipcom_dp83820_attach(sc, pa); 1221 1222 /* 1223 * Initialize our media structures and probe the MII. 1224 */ 1225 sc->sc_mii.mii_ifp = ifp; 1226 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1227 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1228 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1229 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1230 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1231 sipcom_mediastatus); 1232 1233 /* 1234 * XXX We cannot handle flow control on the DP83815. 1235 */ 1236 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1237 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, 0); 1239 else 1240 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1241 MII_OFFSET_ANY, MIIF_DOPAUSE); 1242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1245 } else 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1247 1248 ifp = &sc->sc_ethercom.ec_if; 1249 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1250 ifp->if_softc = sc; 1251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1252 sc->sc_if_flags = ifp->if_flags; 1253 ifp->if_ioctl = sipcom_ioctl; 1254 ifp->if_start = sipcom_start; 1255 ifp->if_watchdog = sipcom_watchdog; 1256 ifp->if_init = sipcom_init; 1257 ifp->if_stop = sipcom_stop; 1258 IFQ_SET_READY(&ifp->if_snd); 1259 1260 /* 1261 * We can support 802.1Q VLAN-sized frames. 1262 */ 1263 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1264 1265 if (sc->sc_gigabit) { 1266 /* 1267 * And the DP83820 can do VLAN tagging in hardware, and 1268 * support the jumbo Ethernet MTU. 1269 */ 1270 sc->sc_ethercom.ec_capabilities |= 1271 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1272 1273 /* 1274 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1275 * in hardware. 1276 */ 1277 ifp->if_capabilities |= 1278 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1279 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1280 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1281 } 1282 1283 /* 1284 * Attach the interface. 1285 */ 1286 if_attach(ifp); 1287 if_deferred_start_init(ifp, NULL); 1288 ether_ifattach(ifp, enaddr); 1289 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1290 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1291 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1292 sc->sc_prev.if_capenable = ifp->if_capenable; 1293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1294 RND_TYPE_NET, RND_FLAG_DEFAULT); 1295 1296 /* 1297 * The number of bytes that must be available in 1298 * the Tx FIFO before the bus master can DMA more 1299 * data into the FIFO. 1300 */ 1301 sc->sc_tx_fill_thresh = 64 / 32; 1302 1303 /* 1304 * Start at a drain threshold of 512 bytes. We will 1305 * increase it if a DMA underrun occurs. 1306 * 1307 * XXX The minimum value of this variable should be 1308 * tuned. We may be able to improve performance 1309 * by starting with a lower value. That, however, 1310 * may trash the first few outgoing packets if the 1311 * PCI bus is saturated. 1312 */ 1313 if (sc->sc_gigabit) 1314 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1315 else 1316 sc->sc_tx_drain_thresh = 1504 / 32; 1317 1318 /* 1319 * Initialize the Rx FIFO drain threshold. 1320 * 1321 * This is in units of 8 bytes. 1322 * 1323 * We should never set this value lower than 2; 14 bytes are 1324 * required to filter the packet. 1325 */ 1326 sc->sc_rx_drain_thresh = 128 / 8; 1327 1328 #ifdef SIP_EVENT_COUNTERS 1329 /* 1330 * Attach event counters. 1331 */ 1332 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(sc->sc_dev), "txsstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1335 NULL, device_xname(sc->sc_dev), "txdstall"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txforceintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "txdintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "txiintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "rxintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(sc->sc_dev), "hiberr"); 1346 if (!sc->sc_gigabit) { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1348 NULL, device_xname(sc->sc_dev), "rxpause"); 1349 } else { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "rxpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "txpause"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxipsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txipsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(sc->sc_dev), "txudpsum"); 1366 } 1367 #endif /* SIP_EVENT_COUNTERS */ 1368 1369 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1370 pmf_class_network_register(self, ifp); 1371 else 1372 aprint_error_dev(self, "couldn't establish power handler\n"); 1373 } 1374 1375 static inline void 1376 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1377 uint64_t capenable) 1378 { 1379 struct m_tag *mtag; 1380 u_int32_t extsts; 1381 #ifdef DEBUG 1382 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1383 #endif 1384 /* 1385 * If VLANs are enabled and the packet has a VLAN tag, set 1386 * up the descriptor to encapsulate the packet for us. 1387 * 1388 * This apparently has to be on the last descriptor of 1389 * the packet. 1390 */ 1391 1392 /* 1393 * Byte swapping is tricky. We need to provide the tag 1394 * in a network byte order. On a big-endian machine, 1395 * the byteorder is correct, but we need to swap it 1396 * anyway, because this will be undone by the outside 1397 * htole32(). That's why there must be an 1398 * unconditional swap instead of htons() inside. 1399 */ 1400 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) { 1401 sc->sc_txdescs[lasttx].sipd_extsts |= 1402 htole32(EXTSTS_VPKT | 1403 (bswap16(VLAN_TAG_VALUE(mtag)) & 1404 EXTSTS_VTCI)); 1405 } 1406 1407 /* 1408 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1409 * checksumming, set up the descriptor to do this work 1410 * for us. 1411 * 1412 * This apparently has to be on the first descriptor of 1413 * the packet. 1414 * 1415 * Byte-swap constants so the compiler can optimize. 1416 */ 1417 extsts = 0; 1418 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1419 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1420 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1421 extsts |= htole32(EXTSTS_IPPKT); 1422 } 1423 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1424 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1425 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1426 extsts |= htole32(EXTSTS_TCPPKT); 1427 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1428 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1429 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1430 extsts |= htole32(EXTSTS_UDPPKT); 1431 } 1432 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1433 } 1434 1435 /* 1436 * sip_start: [ifnet interface function] 1437 * 1438 * Start packet transmission on the interface. 1439 */ 1440 static void 1441 sipcom_start(struct ifnet *ifp) 1442 { 1443 struct sip_softc *sc = ifp->if_softc; 1444 struct mbuf *m0; 1445 struct mbuf *m; 1446 struct sip_txsoft *txs; 1447 bus_dmamap_t dmamap; 1448 int error, nexttx, lasttx, seg; 1449 int ofree = sc->sc_txfree; 1450 #if 0 1451 int firsttx = sc->sc_txnext; 1452 #endif 1453 1454 /* 1455 * If we've been told to pause, don't transmit any more packets. 1456 */ 1457 if (!sc->sc_gigabit && sc->sc_paused) 1458 ifp->if_flags |= IFF_OACTIVE; 1459 1460 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1461 return; 1462 1463 /* 1464 * Loop through the send queue, setting up transmit descriptors 1465 * until we drain the queue, or use up all available transmit 1466 * descriptors. 1467 */ 1468 for (;;) { 1469 /* Get a work queue entry. */ 1470 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1471 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1472 break; 1473 } 1474 1475 /* 1476 * Grab a packet off the queue. 1477 */ 1478 IFQ_POLL(&ifp->if_snd, m0); 1479 if (m0 == NULL) 1480 break; 1481 m = NULL; 1482 1483 dmamap = txs->txs_dmamap; 1484 1485 /* 1486 * Load the DMA map. If this fails, the packet either 1487 * didn't fit in the alloted number of segments, or we 1488 * were short on resources. 1489 */ 1490 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1491 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1492 /* In the non-gigabit case, we'll copy and try again. */ 1493 if (error != 0 && !sc->sc_gigabit) { 1494 MGETHDR(m, M_DONTWAIT, MT_DATA); 1495 if (m == NULL) { 1496 printf("%s: unable to allocate Tx mbuf\n", 1497 device_xname(sc->sc_dev)); 1498 break; 1499 } 1500 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1501 if (m0->m_pkthdr.len > MHLEN) { 1502 MCLGET(m, M_DONTWAIT); 1503 if ((m->m_flags & M_EXT) == 0) { 1504 printf("%s: unable to allocate Tx " 1505 "cluster\n", 1506 device_xname(sc->sc_dev)); 1507 m_freem(m); 1508 break; 1509 } 1510 } 1511 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1512 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1513 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1514 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1515 if (error) { 1516 printf("%s: unable to load Tx buffer, error = " 1517 "%d\n", device_xname(sc->sc_dev), error); 1518 break; 1519 } 1520 } else if (error == EFBIG) { 1521 /* 1522 * For the too-many-segments case, we simply 1523 * report an error and drop the packet, 1524 * since we can't sanely copy a jumbo packet 1525 * to a single buffer. 1526 */ 1527 printf("%s: Tx packet consumes too many DMA segments, " 1528 "dropping...\n", device_xname(sc->sc_dev)); 1529 IFQ_DEQUEUE(&ifp->if_snd, m0); 1530 m_freem(m0); 1531 continue; 1532 } else if (error != 0) { 1533 /* 1534 * Short on resources, just stop for now. 1535 */ 1536 break; 1537 } 1538 1539 /* 1540 * Ensure we have enough descriptors free to describe 1541 * the packet. Note, we always reserve one descriptor 1542 * at the end of the ring as a termination point, to 1543 * prevent wrap-around. 1544 */ 1545 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1546 /* 1547 * Not enough free descriptors to transmit this 1548 * packet. We haven't committed anything yet, 1549 * so just unload the DMA map, put the packet 1550 * back on the queue, and punt. Notify the upper 1551 * layer that there are not more slots left. 1552 * 1553 * XXX We could allocate an mbuf and copy, but 1554 * XXX is it worth it? 1555 */ 1556 ifp->if_flags |= IFF_OACTIVE; 1557 bus_dmamap_unload(sc->sc_dmat, dmamap); 1558 if (m != NULL) 1559 m_freem(m); 1560 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1561 break; 1562 } 1563 1564 IFQ_DEQUEUE(&ifp->if_snd, m0); 1565 if (m != NULL) { 1566 m_freem(m0); 1567 m0 = m; 1568 } 1569 1570 /* 1571 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1572 */ 1573 1574 /* Sync the DMA map. */ 1575 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1576 BUS_DMASYNC_PREWRITE); 1577 1578 /* 1579 * Initialize the transmit descriptors. 1580 */ 1581 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1582 seg < dmamap->dm_nsegs; 1583 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1584 /* 1585 * If this is the first descriptor we're 1586 * enqueueing, don't set the OWN bit just 1587 * yet. That could cause a race condition. 1588 * We'll do it below. 1589 */ 1590 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1591 htole32(dmamap->dm_segs[seg].ds_addr); 1592 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1593 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1594 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1595 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1596 lasttx = nexttx; 1597 } 1598 1599 /* Clear the MORE bit on the last segment. */ 1600 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1601 htole32(~CMDSTS_MORE); 1602 1603 /* 1604 * If we're in the interrupt delay window, delay the 1605 * interrupt. 1606 */ 1607 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1608 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1609 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1610 htole32(CMDSTS_INTR); 1611 sc->sc_txwin = 0; 1612 } 1613 1614 if (sc->sc_gigabit) 1615 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1616 1617 /* Sync the descriptors we're using. */ 1618 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1619 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1620 1621 /* 1622 * The entire packet is set up. Give the first descrptor 1623 * to the chip now. 1624 */ 1625 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1626 htole32(CMDSTS_OWN); 1627 sip_cdtxsync(sc, sc->sc_txnext, 1, 1628 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1629 1630 /* 1631 * Store a pointer to the packet so we can free it later, 1632 * and remember what txdirty will be once the packet is 1633 * done. 1634 */ 1635 txs->txs_mbuf = m0; 1636 txs->txs_firstdesc = sc->sc_txnext; 1637 txs->txs_lastdesc = lasttx; 1638 1639 /* Advance the tx pointer. */ 1640 sc->sc_txfree -= dmamap->dm_nsegs; 1641 sc->sc_txnext = nexttx; 1642 1643 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1644 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1645 1646 /* 1647 * Pass the packet to any BPF listeners. 1648 */ 1649 bpf_mtap(ifp, m0); 1650 } 1651 1652 if (txs == NULL || sc->sc_txfree == 0) { 1653 /* No more slots left; notify upper layer. */ 1654 ifp->if_flags |= IFF_OACTIVE; 1655 } 1656 1657 if (sc->sc_txfree != ofree) { 1658 /* 1659 * Start the transmit process. Note, the manual says 1660 * that if there are no pending transmissions in the 1661 * chip's internal queue (indicated by TXE being clear), 1662 * then the driver software must set the TXDP to the 1663 * first descriptor to be transmitted. However, if we 1664 * do this, it causes serious performance degredation on 1665 * the DP83820 under load, not setting TXDP doesn't seem 1666 * to adversely affect the SiS 900 or DP83815. 1667 * 1668 * Well, I guess it wouldn't be the first time a manual 1669 * has lied -- and they could be speaking of the NULL- 1670 * terminated descriptor list case, rather than OWN- 1671 * terminated rings. 1672 */ 1673 #if 0 1674 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1675 CR_TXE) == 0) { 1676 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1677 SIP_CDTXADDR(sc, firsttx)); 1678 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1679 } 1680 #else 1681 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1682 #endif 1683 1684 /* Set a watchdog timer in case the chip flakes out. */ 1685 /* Gigabit autonegotiation takes 5 seconds. */ 1686 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1687 } 1688 } 1689 1690 /* 1691 * sip_watchdog: [ifnet interface function] 1692 * 1693 * Watchdog timer handler. 1694 */ 1695 static void 1696 sipcom_watchdog(struct ifnet *ifp) 1697 { 1698 struct sip_softc *sc = ifp->if_softc; 1699 1700 /* 1701 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1702 * If we get a timeout, try and sweep up transmit descriptors. 1703 * If we manage to sweep them all up, ignore the lack of 1704 * interrupt. 1705 */ 1706 sipcom_txintr(sc); 1707 1708 if (sc->sc_txfree != sc->sc_ntxdesc) { 1709 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1710 ifp->if_oerrors++; 1711 1712 /* Reset the interface. */ 1713 (void) sipcom_init(ifp); 1714 } else if (ifp->if_flags & IFF_DEBUG) 1715 printf("%s: recovered from device timeout\n", 1716 device_xname(sc->sc_dev)); 1717 1718 /* Try to get more packets going. */ 1719 sipcom_start(ifp); 1720 } 1721 1722 /* If the interface is up and running, only modify the receive 1723 * filter when setting promiscuous or debug mode. Otherwise fall 1724 * through to ether_ioctl, which will reset the chip. 1725 */ 1726 static int 1727 sip_ifflags_cb(struct ethercom *ec) 1728 { 1729 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1730 == (sc)->sc_ethercom.ec_capenable) \ 1731 && ((sc)->sc_prev.is_vlan == \ 1732 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1733 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1734 struct ifnet *ifp = &ec->ec_if; 1735 struct sip_softc *sc = ifp->if_softc; 1736 int change = ifp->if_flags ^ sc->sc_if_flags; 1737 1738 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1739 !COMPARE_IC(sc, ifp)) 1740 return ENETRESET; 1741 /* Set up the receive filter. */ 1742 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1743 return 0; 1744 } 1745 1746 /* 1747 * sip_ioctl: [ifnet interface function] 1748 * 1749 * Handle control requests from the operator. 1750 */ 1751 static int 1752 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1753 { 1754 struct sip_softc *sc = ifp->if_softc; 1755 struct ifreq *ifr = (struct ifreq *)data; 1756 int s, error; 1757 1758 s = splnet(); 1759 1760 switch (cmd) { 1761 case SIOCSIFMEDIA: 1762 /* Flow control requires full-duplex mode. */ 1763 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1764 (ifr->ifr_media & IFM_FDX) == 0) 1765 ifr->ifr_media &= ~IFM_ETH_FMASK; 1766 1767 /* XXX */ 1768 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1769 ifr->ifr_media &= ~IFM_ETH_FMASK; 1770 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1771 if (sc->sc_gigabit && 1772 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1773 /* We can do both TXPAUSE and RXPAUSE. */ 1774 ifr->ifr_media |= 1775 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1776 } else if (ifr->ifr_media & IFM_FLOW) { 1777 /* 1778 * Both TXPAUSE and RXPAUSE must be set. 1779 * (SiS900 and DP83815 don't have PAUSE_ASYM 1780 * feature.) 1781 * 1782 * XXX Can SiS900 and DP83815 send PAUSE? 1783 */ 1784 ifr->ifr_media |= 1785 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1786 } 1787 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1788 } 1789 /*FALLTHROUGH*/ 1790 default: 1791 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1792 break; 1793 1794 error = 0; 1795 1796 if (cmd == SIOCSIFCAP) 1797 error = (*ifp->if_init)(ifp); 1798 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1799 ; 1800 else if (ifp->if_flags & IFF_RUNNING) { 1801 /* 1802 * Multicast list has changed; set the hardware filter 1803 * accordingly. 1804 */ 1805 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1806 } 1807 break; 1808 } 1809 1810 /* Try to get more packets going. */ 1811 sipcom_start(ifp); 1812 1813 sc->sc_if_flags = ifp->if_flags; 1814 splx(s); 1815 return (error); 1816 } 1817 1818 /* 1819 * sip_intr: 1820 * 1821 * Interrupt service routine. 1822 */ 1823 static int 1824 sipcom_intr(void *arg) 1825 { 1826 struct sip_softc *sc = arg; 1827 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1828 u_int32_t isr; 1829 int handled = 0; 1830 1831 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1832 return 0; 1833 1834 /* Disable interrupts. */ 1835 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1836 1837 for (;;) { 1838 /* Reading clears interrupt. */ 1839 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1840 if ((isr & sc->sc_imr) == 0) 1841 break; 1842 1843 rnd_add_uint32(&sc->rnd_source, isr); 1844 1845 handled = 1; 1846 1847 if ((ifp->if_flags & IFF_RUNNING) == 0) 1848 break; 1849 1850 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1851 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1852 1853 /* Grab any new packets. */ 1854 (*sc->sc_rxintr)(sc); 1855 1856 if (isr & ISR_RXORN) { 1857 printf("%s: receive FIFO overrun\n", 1858 device_xname(sc->sc_dev)); 1859 1860 /* XXX adjust rx_drain_thresh? */ 1861 } 1862 1863 if (isr & ISR_RXIDLE) { 1864 printf("%s: receive ring overrun\n", 1865 device_xname(sc->sc_dev)); 1866 1867 /* Get the receive process going again. */ 1868 bus_space_write_4(sc->sc_st, sc->sc_sh, 1869 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1870 bus_space_write_4(sc->sc_st, sc->sc_sh, 1871 SIP_CR, CR_RXE); 1872 } 1873 } 1874 1875 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1876 #ifdef SIP_EVENT_COUNTERS 1877 if (isr & ISR_TXDESC) 1878 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1879 else if (isr & ISR_TXIDLE) 1880 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1881 #endif 1882 1883 /* Sweep up transmit descriptors. */ 1884 sipcom_txintr(sc); 1885 1886 if (isr & ISR_TXURN) { 1887 u_int32_t thresh; 1888 int txfifo_size = (sc->sc_gigabit) 1889 ? DP83820_SIP_TXFIFO_SIZE 1890 : OTHER_SIP_TXFIFO_SIZE; 1891 1892 printf("%s: transmit FIFO underrun", 1893 device_xname(sc->sc_dev)); 1894 thresh = sc->sc_tx_drain_thresh + 1; 1895 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1896 && (thresh * 32) <= (txfifo_size - 1897 (sc->sc_tx_fill_thresh * 32))) { 1898 printf("; increasing Tx drain " 1899 "threshold to %u bytes\n", 1900 thresh * 32); 1901 sc->sc_tx_drain_thresh = thresh; 1902 (void) sipcom_init(ifp); 1903 } else { 1904 (void) sipcom_init(ifp); 1905 printf("\n"); 1906 } 1907 } 1908 } 1909 1910 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1911 if (isr & ISR_PAUSE_ST) { 1912 sc->sc_paused = 1; 1913 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1914 ifp->if_flags |= IFF_OACTIVE; 1915 } 1916 if (isr & ISR_PAUSE_END) { 1917 sc->sc_paused = 0; 1918 ifp->if_flags &= ~IFF_OACTIVE; 1919 } 1920 } 1921 1922 if (isr & ISR_HIBERR) { 1923 int want_init = 0; 1924 1925 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1926 1927 #define PRINTERR(bit, str) \ 1928 do { \ 1929 if ((isr & (bit)) != 0) { \ 1930 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1931 printf("%s: %s\n", \ 1932 device_xname(sc->sc_dev), str); \ 1933 want_init = 1; \ 1934 } \ 1935 } while (/*CONSTCOND*/0) 1936 1937 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1938 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1939 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1940 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1941 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1942 /* 1943 * Ignore: 1944 * Tx reset complete 1945 * Rx reset complete 1946 */ 1947 if (want_init) 1948 (void) sipcom_init(ifp); 1949 #undef PRINTERR 1950 } 1951 } 1952 1953 /* Re-enable interrupts. */ 1954 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1955 1956 /* Try to get more packets going. */ 1957 if_schedule_deferred_start(ifp); 1958 1959 return (handled); 1960 } 1961 1962 /* 1963 * sip_txintr: 1964 * 1965 * Helper; handle transmit interrupts. 1966 */ 1967 static void 1968 sipcom_txintr(struct sip_softc *sc) 1969 { 1970 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1971 struct sip_txsoft *txs; 1972 u_int32_t cmdsts; 1973 1974 if (sc->sc_paused == 0) 1975 ifp->if_flags &= ~IFF_OACTIVE; 1976 1977 /* 1978 * Go through our Tx list and free mbufs for those 1979 * frames which have been transmitted. 1980 */ 1981 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1982 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1983 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1984 1985 cmdsts = le32toh(*sipd_cmdsts(sc, 1986 &sc->sc_txdescs[txs->txs_lastdesc])); 1987 if (cmdsts & CMDSTS_OWN) 1988 break; 1989 1990 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1991 1992 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1993 1994 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1995 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1996 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1997 m_freem(txs->txs_mbuf); 1998 txs->txs_mbuf = NULL; 1999 2000 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2001 2002 /* 2003 * Check for errors and collisions. 2004 */ 2005 if (cmdsts & 2006 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2007 ifp->if_oerrors++; 2008 if (cmdsts & CMDSTS_Tx_EC) 2009 ifp->if_collisions += 16; 2010 if (ifp->if_flags & IFF_DEBUG) { 2011 if (cmdsts & CMDSTS_Tx_ED) 2012 printf("%s: excessive deferral\n", 2013 device_xname(sc->sc_dev)); 2014 if (cmdsts & CMDSTS_Tx_EC) 2015 printf("%s: excessive collisions\n", 2016 device_xname(sc->sc_dev)); 2017 } 2018 } else { 2019 /* Packet was transmitted successfully. */ 2020 ifp->if_opackets++; 2021 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2022 } 2023 } 2024 2025 /* 2026 * If there are no more pending transmissions, cancel the watchdog 2027 * timer. 2028 */ 2029 if (txs == NULL) { 2030 ifp->if_timer = 0; 2031 sc->sc_txwin = 0; 2032 } 2033 } 2034 2035 /* 2036 * gsip_rxintr: 2037 * 2038 * Helper; handle receive interrupts on gigabit parts. 2039 */ 2040 static void 2041 gsip_rxintr(struct sip_softc *sc) 2042 { 2043 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2044 struct sip_rxsoft *rxs; 2045 struct mbuf *m; 2046 u_int32_t cmdsts, extsts; 2047 int i, len; 2048 2049 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2050 rxs = &sc->sc_rxsoft[i]; 2051 2052 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2053 2054 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2055 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2056 len = CMDSTS_SIZE(sc, cmdsts); 2057 2058 /* 2059 * NOTE: OWN is set if owned by _consumer_. We're the 2060 * consumer of the receive ring, so if the bit is clear, 2061 * we have processed all of the packets. 2062 */ 2063 if ((cmdsts & CMDSTS_OWN) == 0) { 2064 /* 2065 * We have processed all of the receive buffers. 2066 */ 2067 break; 2068 } 2069 2070 if (__predict_false(sc->sc_rxdiscard)) { 2071 sip_init_rxdesc(sc, i); 2072 if ((cmdsts & CMDSTS_MORE) == 0) { 2073 /* Reset our state. */ 2074 sc->sc_rxdiscard = 0; 2075 } 2076 continue; 2077 } 2078 2079 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2080 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2081 2082 m = rxs->rxs_mbuf; 2083 2084 /* 2085 * Add a new receive buffer to the ring. 2086 */ 2087 if (sipcom_add_rxbuf(sc, i) != 0) { 2088 /* 2089 * Failed, throw away what we've done so 2090 * far, and discard the rest of the packet. 2091 */ 2092 ifp->if_ierrors++; 2093 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2094 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2095 sip_init_rxdesc(sc, i); 2096 if (cmdsts & CMDSTS_MORE) 2097 sc->sc_rxdiscard = 1; 2098 if (sc->sc_rxhead != NULL) 2099 m_freem(sc->sc_rxhead); 2100 sip_rxchain_reset(sc); 2101 continue; 2102 } 2103 2104 sip_rxchain_link(sc, m); 2105 2106 m->m_len = len; 2107 2108 /* 2109 * If this is not the end of the packet, keep 2110 * looking. 2111 */ 2112 if (cmdsts & CMDSTS_MORE) { 2113 sc->sc_rxlen += len; 2114 continue; 2115 } 2116 2117 /* 2118 * Okay, we have the entire packet now. The chip includes 2119 * the FCS, so we need to trim it. 2120 */ 2121 m->m_len -= ETHER_CRC_LEN; 2122 2123 *sc->sc_rxtailp = NULL; 2124 len = m->m_len + sc->sc_rxlen; 2125 m = sc->sc_rxhead; 2126 2127 sip_rxchain_reset(sc); 2128 2129 /* 2130 * If an error occurred, update stats and drop the packet. 2131 */ 2132 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2133 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2134 ifp->if_ierrors++; 2135 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2136 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2137 /* Receive overrun handled elsewhere. */ 2138 printf("%s: receive descriptor error\n", 2139 device_xname(sc->sc_dev)); 2140 } 2141 #define PRINTERR(bit, str) \ 2142 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2143 (cmdsts & (bit)) != 0) \ 2144 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2145 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2146 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2147 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2148 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2149 #undef PRINTERR 2150 m_freem(m); 2151 continue; 2152 } 2153 2154 /* 2155 * If the packet is small enough to fit in a 2156 * single header mbuf, allocate one and copy 2157 * the data into it. This greatly reduces 2158 * memory consumption when we receive lots 2159 * of small packets. 2160 */ 2161 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2162 struct mbuf *nm; 2163 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2164 if (nm == NULL) { 2165 ifp->if_ierrors++; 2166 m_freem(m); 2167 continue; 2168 } 2169 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2170 nm->m_data += 2; 2171 nm->m_pkthdr.len = nm->m_len = len; 2172 m_copydata(m, 0, len, mtod(nm, void *)); 2173 m_freem(m); 2174 m = nm; 2175 } 2176 #ifndef __NO_STRICT_ALIGNMENT 2177 else { 2178 /* 2179 * The DP83820's receive buffers must be 4-byte 2180 * aligned. But this means that the data after 2181 * the Ethernet header is misaligned. To compensate, 2182 * we have artificially shortened the buffer size 2183 * in the descriptor, and we do an overlapping copy 2184 * of the data two bytes further in (in the first 2185 * buffer of the chain only). 2186 */ 2187 memmove(mtod(m, char *) + 2, mtod(m, void *), 2188 m->m_len); 2189 m->m_data += 2; 2190 } 2191 #endif /* ! __NO_STRICT_ALIGNMENT */ 2192 2193 /* 2194 * If VLANs are enabled, VLAN packets have been unwrapped 2195 * for us. Associate the tag with the packet. 2196 */ 2197 2198 /* 2199 * Again, byte swapping is tricky. Hardware provided 2200 * the tag in the network byte order, but extsts was 2201 * passed through le32toh() in the meantime. On a 2202 * big-endian machine, we need to swap it again. On a 2203 * little-endian machine, we need to convert from the 2204 * network to host byte order. This means that we must 2205 * swap it in any case, so unconditional swap instead 2206 * of htons() is used. 2207 */ 2208 if ((extsts & EXTSTS_VPKT) != 0) { 2209 VLAN_INPUT_TAG(ifp, m, bswap16(extsts & EXTSTS_VTCI), 2210 continue); 2211 } 2212 2213 /* 2214 * Set the incoming checksum information for the 2215 * packet. 2216 */ 2217 if ((extsts & EXTSTS_IPPKT) != 0) { 2218 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2219 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2220 if (extsts & EXTSTS_Rx_IPERR) 2221 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2222 if (extsts & EXTSTS_TCPPKT) { 2223 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2224 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2225 if (extsts & EXTSTS_Rx_TCPERR) 2226 m->m_pkthdr.csum_flags |= 2227 M_CSUM_TCP_UDP_BAD; 2228 } else if (extsts & EXTSTS_UDPPKT) { 2229 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2230 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2231 if (extsts & EXTSTS_Rx_UDPERR) 2232 m->m_pkthdr.csum_flags |= 2233 M_CSUM_TCP_UDP_BAD; 2234 } 2235 } 2236 2237 m_set_rcvif(m, ifp); 2238 m->m_pkthdr.len = len; 2239 2240 /* Pass it on. */ 2241 if_percpuq_enqueue(ifp->if_percpuq, m); 2242 } 2243 2244 /* Update the receive pointer. */ 2245 sc->sc_rxptr = i; 2246 } 2247 2248 /* 2249 * sip_rxintr: 2250 * 2251 * Helper; handle receive interrupts on 10/100 parts. 2252 */ 2253 static void 2254 sip_rxintr(struct sip_softc *sc) 2255 { 2256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2257 struct sip_rxsoft *rxs; 2258 struct mbuf *m; 2259 u_int32_t cmdsts; 2260 int i, len; 2261 2262 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2263 rxs = &sc->sc_rxsoft[i]; 2264 2265 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2266 2267 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2268 2269 /* 2270 * NOTE: OWN is set if owned by _consumer_. We're the 2271 * consumer of the receive ring, so if the bit is clear, 2272 * we have processed all of the packets. 2273 */ 2274 if ((cmdsts & CMDSTS_OWN) == 0) { 2275 /* 2276 * We have processed all of the receive buffers. 2277 */ 2278 break; 2279 } 2280 2281 /* 2282 * If any collisions were seen on the wire, count one. 2283 */ 2284 if (cmdsts & CMDSTS_Rx_COL) 2285 ifp->if_collisions++; 2286 2287 /* 2288 * If an error occurred, update stats, clear the status 2289 * word, and leave the packet buffer in place. It will 2290 * simply be reused the next time the ring comes around. 2291 */ 2292 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2293 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2294 ifp->if_ierrors++; 2295 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2296 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2297 /* Receive overrun handled elsewhere. */ 2298 printf("%s: receive descriptor error\n", 2299 device_xname(sc->sc_dev)); 2300 } 2301 #define PRINTERR(bit, str) \ 2302 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2303 (cmdsts & (bit)) != 0) \ 2304 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2305 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2306 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2307 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2308 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2309 #undef PRINTERR 2310 sip_init_rxdesc(sc, i); 2311 continue; 2312 } 2313 2314 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2315 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2316 2317 /* 2318 * No errors; receive the packet. Note, the SiS 900 2319 * includes the CRC with every packet. 2320 */ 2321 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2322 2323 #ifdef __NO_STRICT_ALIGNMENT 2324 /* 2325 * If the packet is small enough to fit in a 2326 * single header mbuf, allocate one and copy 2327 * the data into it. This greatly reduces 2328 * memory consumption when we receive lots 2329 * of small packets. 2330 * 2331 * Otherwise, we add a new buffer to the receive 2332 * chain. If this fails, we drop the packet and 2333 * recycle the old buffer. 2334 */ 2335 if (sip_copy_small != 0 && len <= MHLEN) { 2336 MGETHDR(m, M_DONTWAIT, MT_DATA); 2337 if (m == NULL) 2338 goto dropit; 2339 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2340 memcpy(mtod(m, void *), 2341 mtod(rxs->rxs_mbuf, void *), len); 2342 sip_init_rxdesc(sc, i); 2343 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2344 rxs->rxs_dmamap->dm_mapsize, 2345 BUS_DMASYNC_PREREAD); 2346 } else { 2347 m = rxs->rxs_mbuf; 2348 if (sipcom_add_rxbuf(sc, i) != 0) { 2349 dropit: 2350 ifp->if_ierrors++; 2351 sip_init_rxdesc(sc, i); 2352 bus_dmamap_sync(sc->sc_dmat, 2353 rxs->rxs_dmamap, 0, 2354 rxs->rxs_dmamap->dm_mapsize, 2355 BUS_DMASYNC_PREREAD); 2356 continue; 2357 } 2358 } 2359 #else 2360 /* 2361 * The SiS 900's receive buffers must be 4-byte aligned. 2362 * But this means that the data after the Ethernet header 2363 * is misaligned. We must allocate a new buffer and 2364 * copy the data, shifted forward 2 bytes. 2365 */ 2366 MGETHDR(m, M_DONTWAIT, MT_DATA); 2367 if (m == NULL) { 2368 dropit: 2369 ifp->if_ierrors++; 2370 sip_init_rxdesc(sc, i); 2371 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2372 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2373 continue; 2374 } 2375 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2376 if (len > (MHLEN - 2)) { 2377 MCLGET(m, M_DONTWAIT); 2378 if ((m->m_flags & M_EXT) == 0) { 2379 m_freem(m); 2380 goto dropit; 2381 } 2382 } 2383 m->m_data += 2; 2384 2385 /* 2386 * Note that we use clusters for incoming frames, so the 2387 * buffer is virtually contiguous. 2388 */ 2389 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2390 2391 /* Allow the receive descriptor to continue using its mbuf. */ 2392 sip_init_rxdesc(sc, i); 2393 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2394 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2395 #endif /* __NO_STRICT_ALIGNMENT */ 2396 2397 m_set_rcvif(m, ifp); 2398 m->m_pkthdr.len = m->m_len = len; 2399 2400 /* Pass it on. */ 2401 if_percpuq_enqueue(ifp->if_percpuq, m); 2402 } 2403 2404 /* Update the receive pointer. */ 2405 sc->sc_rxptr = i; 2406 } 2407 2408 /* 2409 * sip_tick: 2410 * 2411 * One second timer, used to tick the MII. 2412 */ 2413 static void 2414 sipcom_tick(void *arg) 2415 { 2416 struct sip_softc *sc = arg; 2417 int s; 2418 2419 s = splnet(); 2420 #ifdef SIP_EVENT_COUNTERS 2421 if (sc->sc_gigabit) { 2422 /* Read PAUSE related counts from MIB registers. */ 2423 sc->sc_ev_rxpause.ev_count += 2424 bus_space_read_4(sc->sc_st, sc->sc_sh, 2425 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2426 sc->sc_ev_txpause.ev_count += 2427 bus_space_read_4(sc->sc_st, sc->sc_sh, 2428 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2429 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2430 } 2431 #endif /* SIP_EVENT_COUNTERS */ 2432 mii_tick(&sc->sc_mii); 2433 splx(s); 2434 2435 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2436 } 2437 2438 /* 2439 * sip_reset: 2440 * 2441 * Perform a soft reset on the SiS 900. 2442 */ 2443 static bool 2444 sipcom_reset(struct sip_softc *sc) 2445 { 2446 bus_space_tag_t st = sc->sc_st; 2447 bus_space_handle_t sh = sc->sc_sh; 2448 int i; 2449 2450 bus_space_write_4(st, sh, SIP_IER, 0); 2451 bus_space_write_4(st, sh, SIP_IMR, 0); 2452 bus_space_write_4(st, sh, SIP_RFCR, 0); 2453 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2454 2455 for (i = 0; i < SIP_TIMEOUT; i++) { 2456 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2457 break; 2458 delay(2); 2459 } 2460 2461 if (i == SIP_TIMEOUT) { 2462 printf("%s: reset failed to complete\n", 2463 device_xname(sc->sc_dev)); 2464 return false; 2465 } 2466 2467 delay(1000); 2468 2469 if (sc->sc_gigabit) { 2470 /* 2471 * Set the general purpose I/O bits. Do it here in case we 2472 * need to have GPIO set up to talk to the media interface. 2473 */ 2474 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2475 delay(1000); 2476 } 2477 return true; 2478 } 2479 2480 static void 2481 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2482 { 2483 u_int32_t reg; 2484 bus_space_tag_t st = sc->sc_st; 2485 bus_space_handle_t sh = sc->sc_sh; 2486 /* 2487 * Initialize the VLAN/IP receive control register. 2488 * We enable checksum computation on all incoming 2489 * packets, and do not reject packets w/ bad checksums. 2490 */ 2491 reg = 0; 2492 if (capenable & 2493 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2494 reg |= VRCR_IPEN; 2495 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2496 reg |= VRCR_VTDEN|VRCR_VTREN; 2497 bus_space_write_4(st, sh, SIP_VRCR, reg); 2498 2499 /* 2500 * Initialize the VLAN/IP transmit control register. 2501 * We enable outgoing checksum computation on a 2502 * per-packet basis. 2503 */ 2504 reg = 0; 2505 if (capenable & 2506 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2507 reg |= VTCR_PPCHK; 2508 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2509 reg |= VTCR_VPPTI; 2510 bus_space_write_4(st, sh, SIP_VTCR, reg); 2511 2512 /* 2513 * If we're using VLANs, initialize the VLAN data register. 2514 * To understand why we bswap the VLAN Ethertype, see section 2515 * 4.2.36 of the DP83820 manual. 2516 */ 2517 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2518 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2519 } 2520 2521 /* 2522 * sip_init: [ ifnet interface function ] 2523 * 2524 * Initialize the interface. Must be called at splnet(). 2525 */ 2526 static int 2527 sipcom_init(struct ifnet *ifp) 2528 { 2529 struct sip_softc *sc = ifp->if_softc; 2530 bus_space_tag_t st = sc->sc_st; 2531 bus_space_handle_t sh = sc->sc_sh; 2532 struct sip_txsoft *txs; 2533 struct sip_rxsoft *rxs; 2534 struct sip_desc *sipd; 2535 int i, error = 0; 2536 2537 if (device_is_active(sc->sc_dev)) { 2538 /* 2539 * Cancel any pending I/O. 2540 */ 2541 sipcom_stop(ifp, 0); 2542 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2543 !device_is_active(sc->sc_dev)) 2544 return 0; 2545 2546 /* 2547 * Reset the chip to a known state. 2548 */ 2549 if (!sipcom_reset(sc)) 2550 return EBUSY; 2551 2552 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2553 /* 2554 * DP83815 manual, page 78: 2555 * 4.4 Recommended Registers Configuration 2556 * For optimum performance of the DP83815, version noted 2557 * as DP83815CVNG (SRR = 203h), the listed register 2558 * modifications must be followed in sequence... 2559 * 2560 * It's not clear if this should be 302h or 203h because that 2561 * chip name is listed as SRR 302h in the description of the 2562 * SRR register. However, my revision 302h DP83815 on the 2563 * Netgear FA311 purchased in 02/2001 needs these settings 2564 * to avoid tons of errors in AcceptPerfectMatch (non- 2565 * IFF_PROMISC) mode. I do not know if other revisions need 2566 * this set or not. [briggs -- 09 March 2001] 2567 * 2568 * Note that only the low-order 12 bits of 0xe4 are documented 2569 * and that this sets reserved bits in that register. 2570 */ 2571 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2572 2573 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2574 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2575 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2576 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2577 2578 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2579 } 2580 2581 /* 2582 * Initialize the transmit descriptor ring. 2583 */ 2584 for (i = 0; i < sc->sc_ntxdesc; i++) { 2585 sipd = &sc->sc_txdescs[i]; 2586 memset(sipd, 0, sizeof(struct sip_desc)); 2587 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2588 } 2589 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2590 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2591 sc->sc_txfree = sc->sc_ntxdesc; 2592 sc->sc_txnext = 0; 2593 sc->sc_txwin = 0; 2594 2595 /* 2596 * Initialize the transmit job descriptors. 2597 */ 2598 SIMPLEQ_INIT(&sc->sc_txfreeq); 2599 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2600 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2601 txs = &sc->sc_txsoft[i]; 2602 txs->txs_mbuf = NULL; 2603 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2604 } 2605 2606 /* 2607 * Initialize the receive descriptor and receive job 2608 * descriptor rings. 2609 */ 2610 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2611 rxs = &sc->sc_rxsoft[i]; 2612 if (rxs->rxs_mbuf == NULL) { 2613 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2614 printf("%s: unable to allocate or map rx " 2615 "buffer %d, error = %d\n", 2616 device_xname(sc->sc_dev), i, error); 2617 /* 2618 * XXX Should attempt to run with fewer receive 2619 * XXX buffers instead of just failing. 2620 */ 2621 sipcom_rxdrain(sc); 2622 goto out; 2623 } 2624 } else 2625 sip_init_rxdesc(sc, i); 2626 } 2627 sc->sc_rxptr = 0; 2628 sc->sc_rxdiscard = 0; 2629 sip_rxchain_reset(sc); 2630 2631 /* 2632 * Set the configuration register; it's already initialized 2633 * in sip_attach(). 2634 */ 2635 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2636 2637 /* 2638 * Initialize the prototype TXCFG register. 2639 */ 2640 if (sc->sc_gigabit) { 2641 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2642 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2643 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2644 SIP_SIS900_REV(sc, SIS_REV_960) || 2645 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2646 (sc->sc_cfg & CFG_EDBMASTEN)) { 2647 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2648 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2649 } else { 2650 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2651 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2652 } 2653 2654 sc->sc_txcfg |= TXCFG_ATP | 2655 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2656 sc->sc_tx_drain_thresh; 2657 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2658 2659 /* 2660 * Initialize the receive drain threshold if we have never 2661 * done so. 2662 */ 2663 if (sc->sc_rx_drain_thresh == 0) { 2664 /* 2665 * XXX This value should be tuned. This is set to the 2666 * maximum of 248 bytes, and we may be able to improve 2667 * performance by decreasing it (although we should never 2668 * set this value lower than 2; 14 bytes are required to 2669 * filter the packet). 2670 */ 2671 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2672 } 2673 2674 /* 2675 * Initialize the prototype RXCFG register. 2676 */ 2677 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2678 /* 2679 * Accept long packets (including FCS) so we can handle 2680 * 802.1q-tagged frames and jumbo frames properly. 2681 */ 2682 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2683 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2684 sc->sc_rxcfg |= RXCFG_ALP; 2685 2686 /* 2687 * Checksum offloading is disabled if the user selects an MTU 2688 * larger than 8109. (FreeBSD says 8152, but there is emperical 2689 * evidence that >8109 does not work on some boards, such as the 2690 * Planex GN-1000TE). 2691 */ 2692 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2693 (ifp->if_capenable & 2694 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2695 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2696 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2697 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2698 "disabled.\n", device_xname(sc->sc_dev)); 2699 ifp->if_capenable &= 2700 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2701 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2702 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2703 ifp->if_csum_flags_tx = 0; 2704 ifp->if_csum_flags_rx = 0; 2705 } 2706 2707 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2708 2709 if (sc->sc_gigabit) 2710 sipcom_dp83820_init(sc, ifp->if_capenable); 2711 2712 /* 2713 * Give the transmit and receive rings to the chip. 2714 */ 2715 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2716 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2717 2718 /* 2719 * Initialize the interrupt mask. 2720 */ 2721 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2722 sc->sc_bits.b_isr_sserr | 2723 sc->sc_bits.b_isr_rmabt | 2724 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2725 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2726 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2727 2728 /* Set up the receive filter. */ 2729 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2730 2731 /* 2732 * Tune sc_rx_flow_thresh. 2733 * XXX "More than 8KB" is too short for jumbo frames. 2734 * XXX TODO: Threshold value should be user-settable. 2735 */ 2736 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2737 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2738 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2739 2740 /* 2741 * Set the current media. Do this after initializing the prototype 2742 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2743 * control. 2744 */ 2745 if ((error = ether_mediachange(ifp)) != 0) 2746 goto out; 2747 2748 /* 2749 * Set the interrupt hold-off timer to 100us. 2750 */ 2751 if (sc->sc_gigabit) 2752 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2753 2754 /* 2755 * Enable interrupts. 2756 */ 2757 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2758 2759 /* 2760 * Start the transmit and receive processes. 2761 */ 2762 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2763 2764 /* 2765 * Start the one second MII clock. 2766 */ 2767 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2768 2769 /* 2770 * ...all done! 2771 */ 2772 ifp->if_flags |= IFF_RUNNING; 2773 ifp->if_flags &= ~IFF_OACTIVE; 2774 sc->sc_if_flags = ifp->if_flags; 2775 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2776 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2777 sc->sc_prev.if_capenable = ifp->if_capenable; 2778 2779 out: 2780 if (error) 2781 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2782 return (error); 2783 } 2784 2785 /* 2786 * sip_drain: 2787 * 2788 * Drain the receive queue. 2789 */ 2790 static void 2791 sipcom_rxdrain(struct sip_softc *sc) 2792 { 2793 struct sip_rxsoft *rxs; 2794 int i; 2795 2796 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2797 rxs = &sc->sc_rxsoft[i]; 2798 if (rxs->rxs_mbuf != NULL) { 2799 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2800 m_freem(rxs->rxs_mbuf); 2801 rxs->rxs_mbuf = NULL; 2802 } 2803 } 2804 } 2805 2806 /* 2807 * sip_stop: [ ifnet interface function ] 2808 * 2809 * Stop transmission on the interface. 2810 */ 2811 static void 2812 sipcom_stop(struct ifnet *ifp, int disable) 2813 { 2814 struct sip_softc *sc = ifp->if_softc; 2815 bus_space_tag_t st = sc->sc_st; 2816 bus_space_handle_t sh = sc->sc_sh; 2817 struct sip_txsoft *txs; 2818 u_int32_t cmdsts = 0; /* DEBUG */ 2819 2820 /* 2821 * Stop the one second clock. 2822 */ 2823 callout_stop(&sc->sc_tick_ch); 2824 2825 /* Down the MII. */ 2826 mii_down(&sc->sc_mii); 2827 2828 if (device_is_active(sc->sc_dev)) { 2829 /* 2830 * Disable interrupts. 2831 */ 2832 bus_space_write_4(st, sh, SIP_IER, 0); 2833 2834 /* 2835 * Stop receiver and transmitter. 2836 */ 2837 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2838 } 2839 2840 /* 2841 * Release any queued transmit buffers. 2842 */ 2843 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2844 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2845 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2846 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2847 CMDSTS_INTR) == 0) 2848 printf("%s: sip_stop: last descriptor does not " 2849 "have INTR bit set\n", device_xname(sc->sc_dev)); 2850 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2851 #ifdef DIAGNOSTIC 2852 if (txs->txs_mbuf == NULL) { 2853 printf("%s: dirty txsoft with no mbuf chain\n", 2854 device_xname(sc->sc_dev)); 2855 panic("sip_stop"); 2856 } 2857 #endif 2858 cmdsts |= /* DEBUG */ 2859 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2860 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2861 m_freem(txs->txs_mbuf); 2862 txs->txs_mbuf = NULL; 2863 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2864 } 2865 2866 /* 2867 * Mark the interface down and cancel the watchdog timer. 2868 */ 2869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2870 ifp->if_timer = 0; 2871 2872 if (disable) 2873 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2874 2875 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2876 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2877 printf("%s: sip_stop: no INTR bits set in dirty tx " 2878 "descriptors\n", device_xname(sc->sc_dev)); 2879 } 2880 2881 /* 2882 * sip_read_eeprom: 2883 * 2884 * Read data from the serial EEPROM. 2885 */ 2886 static void 2887 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2888 u_int16_t *data) 2889 { 2890 bus_space_tag_t st = sc->sc_st; 2891 bus_space_handle_t sh = sc->sc_sh; 2892 u_int16_t reg; 2893 int i, x; 2894 2895 for (i = 0; i < wordcnt; i++) { 2896 /* Send CHIP SELECT. */ 2897 reg = EROMAR_EECS; 2898 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2899 2900 /* Shift in the READ opcode. */ 2901 for (x = 3; x > 0; x--) { 2902 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2903 reg |= EROMAR_EEDI; 2904 else 2905 reg &= ~EROMAR_EEDI; 2906 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2907 bus_space_write_4(st, sh, SIP_EROMAR, 2908 reg | EROMAR_EESK); 2909 delay(4); 2910 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2911 delay(4); 2912 } 2913 2914 /* Shift in address. */ 2915 for (x = 6; x > 0; x--) { 2916 if ((word + i) & (1 << (x - 1))) 2917 reg |= EROMAR_EEDI; 2918 else 2919 reg &= ~EROMAR_EEDI; 2920 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2921 bus_space_write_4(st, sh, SIP_EROMAR, 2922 reg | EROMAR_EESK); 2923 delay(4); 2924 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2925 delay(4); 2926 } 2927 2928 /* Shift out data. */ 2929 reg = EROMAR_EECS; 2930 data[i] = 0; 2931 for (x = 16; x > 0; x--) { 2932 bus_space_write_4(st, sh, SIP_EROMAR, 2933 reg | EROMAR_EESK); 2934 delay(4); 2935 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2936 data[i] |= (1 << (x - 1)); 2937 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2938 delay(4); 2939 } 2940 2941 /* Clear CHIP SELECT. */ 2942 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2943 delay(4); 2944 } 2945 } 2946 2947 /* 2948 * sipcom_add_rxbuf: 2949 * 2950 * Add a receive buffer to the indicated descriptor. 2951 */ 2952 static int 2953 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2954 { 2955 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2956 struct mbuf *m; 2957 int error; 2958 2959 MGETHDR(m, M_DONTWAIT, MT_DATA); 2960 if (m == NULL) 2961 return (ENOBUFS); 2962 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2963 2964 MCLGET(m, M_DONTWAIT); 2965 if ((m->m_flags & M_EXT) == 0) { 2966 m_freem(m); 2967 return (ENOBUFS); 2968 } 2969 2970 /* XXX I don't believe this is necessary. --dyoung */ 2971 if (sc->sc_gigabit) 2972 m->m_len = sc->sc_parm->p_rxbuf_len; 2973 2974 if (rxs->rxs_mbuf != NULL) 2975 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2976 2977 rxs->rxs_mbuf = m; 2978 2979 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2980 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2981 BUS_DMA_READ|BUS_DMA_NOWAIT); 2982 if (error) { 2983 printf("%s: can't load rx DMA map %d, error = %d\n", 2984 device_xname(sc->sc_dev), idx, error); 2985 panic("%s", __func__); /* XXX */ 2986 } 2987 2988 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2989 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2990 2991 sip_init_rxdesc(sc, idx); 2992 2993 return (0); 2994 } 2995 2996 /* 2997 * sip_sis900_set_filter: 2998 * 2999 * Set up the receive filter. 3000 */ 3001 static void 3002 sipcom_sis900_set_filter(struct sip_softc *sc) 3003 { 3004 bus_space_tag_t st = sc->sc_st; 3005 bus_space_handle_t sh = sc->sc_sh; 3006 struct ethercom *ec = &sc->sc_ethercom; 3007 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3008 struct ether_multi *enm; 3009 const u_int8_t *cp; 3010 struct ether_multistep step; 3011 u_int32_t crc, mchash[16]; 3012 3013 /* 3014 * Initialize the prototype RFCR. 3015 */ 3016 sc->sc_rfcr = RFCR_RFEN; 3017 if (ifp->if_flags & IFF_BROADCAST) 3018 sc->sc_rfcr |= RFCR_AAB; 3019 if (ifp->if_flags & IFF_PROMISC) { 3020 sc->sc_rfcr |= RFCR_AAP; 3021 goto allmulti; 3022 } 3023 3024 /* 3025 * Set up the multicast address filter by passing all multicast 3026 * addresses through a CRC generator, and then using the high-order 3027 * 6 bits as an index into the 128 bit multicast hash table (only 3028 * the lower 16 bits of each 32 bit multicast hash register are 3029 * valid). The high order bits select the register, while the 3030 * rest of the bits select the bit within the register. 3031 */ 3032 3033 memset(mchash, 0, sizeof(mchash)); 3034 3035 /* 3036 * SiS900 (at least SiS963) requires us to register the address of 3037 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3038 */ 3039 crc = 0x0ed423f9; 3040 3041 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3042 SIP_SIS900_REV(sc, SIS_REV_960) || 3043 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3044 /* Just want the 8 most significant bits. */ 3045 crc >>= 24; 3046 } else { 3047 /* Just want the 7 most significant bits. */ 3048 crc >>= 25; 3049 } 3050 3051 /* Set the corresponding bit in the hash table. */ 3052 mchash[crc >> 4] |= 1 << (crc & 0xf); 3053 3054 ETHER_FIRST_MULTI(step, ec, enm); 3055 while (enm != NULL) { 3056 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3057 /* 3058 * We must listen to a range of multicast addresses. 3059 * For now, just accept all multicasts, rather than 3060 * trying to set only those filter bits needed to match 3061 * the range. (At this time, the only use of address 3062 * ranges is for IP multicast routing, for which the 3063 * range is big enough to require all bits set.) 3064 */ 3065 goto allmulti; 3066 } 3067 3068 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3069 3070 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3071 SIP_SIS900_REV(sc, SIS_REV_960) || 3072 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3073 /* Just want the 8 most significant bits. */ 3074 crc >>= 24; 3075 } else { 3076 /* Just want the 7 most significant bits. */ 3077 crc >>= 25; 3078 } 3079 3080 /* Set the corresponding bit in the hash table. */ 3081 mchash[crc >> 4] |= 1 << (crc & 0xf); 3082 3083 ETHER_NEXT_MULTI(step, enm); 3084 } 3085 3086 ifp->if_flags &= ~IFF_ALLMULTI; 3087 goto setit; 3088 3089 allmulti: 3090 ifp->if_flags |= IFF_ALLMULTI; 3091 sc->sc_rfcr |= RFCR_AAM; 3092 3093 setit: 3094 #define FILTER_EMIT(addr, data) \ 3095 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3096 delay(1); \ 3097 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3098 delay(1) 3099 3100 /* 3101 * Disable receive filter, and program the node address. 3102 */ 3103 cp = CLLADDR(ifp->if_sadl); 3104 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3105 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3106 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3107 3108 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3109 /* 3110 * Program the multicast hash table. 3111 */ 3112 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3113 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3114 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3115 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3116 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3117 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3118 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3119 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3120 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3121 SIP_SIS900_REV(sc, SIS_REV_960) || 3122 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3123 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3124 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3125 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3126 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3127 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3128 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3129 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3130 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3131 } 3132 } 3133 #undef FILTER_EMIT 3134 3135 /* 3136 * Re-enable the receiver filter. 3137 */ 3138 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3139 } 3140 3141 /* 3142 * sip_dp83815_set_filter: 3143 * 3144 * Set up the receive filter. 3145 */ 3146 static void 3147 sipcom_dp83815_set_filter(struct sip_softc *sc) 3148 { 3149 bus_space_tag_t st = sc->sc_st; 3150 bus_space_handle_t sh = sc->sc_sh; 3151 struct ethercom *ec = &sc->sc_ethercom; 3152 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3153 struct ether_multi *enm; 3154 const u_int8_t *cp; 3155 struct ether_multistep step; 3156 u_int32_t crc, hash, slot, bit; 3157 #define MCHASH_NWORDS_83820 128 3158 #define MCHASH_NWORDS_83815 32 3159 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3160 u_int16_t mchash[MCHASH_NWORDS]; 3161 int i; 3162 3163 /* 3164 * Initialize the prototype RFCR. 3165 * Enable the receive filter, and accept on 3166 * Perfect (destination address) Match 3167 * If IFF_BROADCAST, also accept all broadcast packets. 3168 * If IFF_PROMISC, accept all unicast packets (and later, set 3169 * IFF_ALLMULTI and accept all multicast, too). 3170 */ 3171 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3172 if (ifp->if_flags & IFF_BROADCAST) 3173 sc->sc_rfcr |= RFCR_AAB; 3174 if (ifp->if_flags & IFF_PROMISC) { 3175 sc->sc_rfcr |= RFCR_AAP; 3176 goto allmulti; 3177 } 3178 3179 /* 3180 * Set up the DP83820/DP83815 multicast address filter by 3181 * passing all multicast addresses through a CRC generator, 3182 * and then using the high-order 11/9 bits as an index into 3183 * the 2048/512 bit multicast hash table. The high-order 3184 * 7/5 bits select the slot, while the low-order 4 bits 3185 * select the bit within the slot. Note that only the low 3186 * 16-bits of each filter word are used, and there are 3187 * 128/32 filter words. 3188 */ 3189 3190 memset(mchash, 0, sizeof(mchash)); 3191 3192 ifp->if_flags &= ~IFF_ALLMULTI; 3193 ETHER_FIRST_MULTI(step, ec, enm); 3194 if (enm == NULL) 3195 goto setit; 3196 while (enm != NULL) { 3197 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3198 /* 3199 * We must listen to a range of multicast addresses. 3200 * For now, just accept all multicasts, rather than 3201 * trying to set only those filter bits needed to match 3202 * the range. (At this time, the only use of address 3203 * ranges is for IP multicast routing, for which the 3204 * range is big enough to require all bits set.) 3205 */ 3206 goto allmulti; 3207 } 3208 3209 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3210 3211 if (sc->sc_gigabit) { 3212 /* Just want the 11 most significant bits. */ 3213 hash = crc >> 21; 3214 } else { 3215 /* Just want the 9 most significant bits. */ 3216 hash = crc >> 23; 3217 } 3218 3219 slot = hash >> 4; 3220 bit = hash & 0xf; 3221 3222 /* Set the corresponding bit in the hash table. */ 3223 mchash[slot] |= 1 << bit; 3224 3225 ETHER_NEXT_MULTI(step, enm); 3226 } 3227 sc->sc_rfcr |= RFCR_MHEN; 3228 goto setit; 3229 3230 allmulti: 3231 ifp->if_flags |= IFF_ALLMULTI; 3232 sc->sc_rfcr |= RFCR_AAM; 3233 3234 setit: 3235 #define FILTER_EMIT(addr, data) \ 3236 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3237 delay(1); \ 3238 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3239 delay(1) 3240 3241 /* 3242 * Disable receive filter, and program the node address. 3243 */ 3244 cp = CLLADDR(ifp->if_sadl); 3245 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3246 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3247 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3248 3249 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3250 int nwords = 3251 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3252 /* 3253 * Program the multicast hash table. 3254 */ 3255 for (i = 0; i < nwords; i++) { 3256 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3257 } 3258 } 3259 #undef FILTER_EMIT 3260 #undef MCHASH_NWORDS 3261 #undef MCHASH_NWORDS_83815 3262 #undef MCHASH_NWORDS_83820 3263 3264 /* 3265 * Re-enable the receiver filter. 3266 */ 3267 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3268 } 3269 3270 /* 3271 * sip_dp83820_mii_readreg: [mii interface function] 3272 * 3273 * Read a PHY register on the MII of the DP83820. 3274 */ 3275 static int 3276 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg) 3277 { 3278 struct sip_softc *sc = device_private(self); 3279 3280 if (sc->sc_cfg & CFG_TBI_EN) { 3281 bus_addr_t tbireg; 3282 int rv; 3283 3284 if (phy != 0) 3285 return (0); 3286 3287 switch (reg) { 3288 case MII_BMCR: tbireg = SIP_TBICR; break; 3289 case MII_BMSR: tbireg = SIP_TBISR; break; 3290 case MII_ANAR: tbireg = SIP_TANAR; break; 3291 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3292 case MII_ANER: tbireg = SIP_TANER; break; 3293 case MII_EXTSR: 3294 /* 3295 * Don't even bother reading the TESR register. 3296 * The manual documents that the device has 3297 * 1000baseX full/half capability, but the 3298 * register itself seems read back 0 on some 3299 * boards. Just hard-code the result. 3300 */ 3301 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3302 3303 default: 3304 return (0); 3305 } 3306 3307 rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3308 if (tbireg == SIP_TBISR) { 3309 /* LINK and ACOMP are switched! */ 3310 int val = rv; 3311 3312 rv = 0; 3313 if (val & TBISR_MR_LINK_STATUS) 3314 rv |= BMSR_LINK; 3315 if (val & TBISR_MR_AN_COMPLETE) 3316 rv |= BMSR_ACOMP; 3317 3318 /* 3319 * The manual claims this register reads back 0 3320 * on hard and soft reset. But we want to let 3321 * the gentbi driver know that we support auto- 3322 * negotiation, so hard-code this bit in the 3323 * result. 3324 */ 3325 rv |= BMSR_ANEG | BMSR_EXTSTAT; 3326 } 3327 3328 return (rv); 3329 } 3330 3331 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg); 3332 } 3333 3334 /* 3335 * sip_dp83820_mii_writereg: [mii interface function] 3336 * 3337 * Write a PHY register on the MII of the DP83820. 3338 */ 3339 static void 3340 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, int val) 3341 { 3342 struct sip_softc *sc = device_private(self); 3343 3344 if (sc->sc_cfg & CFG_TBI_EN) { 3345 bus_addr_t tbireg; 3346 3347 if (phy != 0) 3348 return; 3349 3350 switch (reg) { 3351 case MII_BMCR: tbireg = SIP_TBICR; break; 3352 case MII_ANAR: tbireg = SIP_TANAR; break; 3353 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3354 default: 3355 return; 3356 } 3357 3358 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3359 return; 3360 } 3361 3362 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, val); 3363 } 3364 3365 /* 3366 * sip_dp83820_mii_statchg: [mii interface function] 3367 * 3368 * Callback from MII layer when media changes. 3369 */ 3370 static void 3371 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3372 { 3373 struct sip_softc *sc = ifp->if_softc; 3374 struct mii_data *mii = &sc->sc_mii; 3375 u_int32_t cfg, pcr; 3376 3377 /* 3378 * Get flow control negotiation result. 3379 */ 3380 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3381 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3382 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3383 mii->mii_media_active &= ~IFM_ETH_FMASK; 3384 } 3385 3386 /* 3387 * Update TXCFG for full-duplex operation. 3388 */ 3389 if ((mii->mii_media_active & IFM_FDX) != 0) 3390 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3391 else 3392 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3393 3394 /* 3395 * Update RXCFG for full-duplex or loopback. 3396 */ 3397 if ((mii->mii_media_active & IFM_FDX) != 0 || 3398 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3399 sc->sc_rxcfg |= RXCFG_ATX; 3400 else 3401 sc->sc_rxcfg &= ~RXCFG_ATX; 3402 3403 /* 3404 * Update CFG for MII/GMII. 3405 */ 3406 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3407 cfg = sc->sc_cfg | CFG_MODE_1000; 3408 else 3409 cfg = sc->sc_cfg; 3410 3411 /* 3412 * 802.3x flow control. 3413 */ 3414 pcr = 0; 3415 if (sc->sc_flowflags & IFM_FLOW) { 3416 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3417 pcr |= sc->sc_rx_flow_thresh; 3418 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3419 pcr |= PCR_PSEN | PCR_PS_MCAST; 3420 } 3421 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3423 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3424 sc->sc_txcfg); 3425 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3426 sc->sc_rxcfg); 3427 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3428 } 3429 3430 /* 3431 * sip_mii_bitbang_read: [mii bit-bang interface function] 3432 * 3433 * Read the MII serial port for the MII bit-bang module. 3434 */ 3435 static u_int32_t 3436 sipcom_mii_bitbang_read(device_t self) 3437 { 3438 struct sip_softc *sc = device_private(self); 3439 3440 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3441 } 3442 3443 /* 3444 * sip_mii_bitbang_write: [mii big-bang interface function] 3445 * 3446 * Write the MII serial port for the MII bit-bang module. 3447 */ 3448 static void 3449 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3450 { 3451 struct sip_softc *sc = device_private(self); 3452 3453 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3454 } 3455 3456 /* 3457 * sip_sis900_mii_readreg: [mii interface function] 3458 * 3459 * Read a PHY register on the MII. 3460 */ 3461 static int 3462 sipcom_sis900_mii_readreg(device_t self, int phy, int reg) 3463 { 3464 struct sip_softc *sc = device_private(self); 3465 u_int32_t enphy; 3466 3467 /* 3468 * The PHY of recent SiS chipsets is accessed through bitbang 3469 * operations. 3470 */ 3471 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3472 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3473 phy, reg); 3474 3475 #ifndef SIS900_MII_RESTRICT 3476 /* 3477 * The SiS 900 has only an internal PHY on the MII. Only allow 3478 * MII address 0. 3479 */ 3480 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3481 return (0); 3482 #endif 3483 3484 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3485 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3486 ENPHY_RWCMD | ENPHY_ACCESS); 3487 do { 3488 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3489 } while (enphy & ENPHY_ACCESS); 3490 return ((enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT); 3491 } 3492 3493 /* 3494 * sip_sis900_mii_writereg: [mii interface function] 3495 * 3496 * Write a PHY register on the MII. 3497 */ 3498 static void 3499 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, int val) 3500 { 3501 struct sip_softc *sc = device_private(self); 3502 u_int32_t enphy; 3503 3504 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3505 mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3506 phy, reg, val); 3507 return; 3508 } 3509 3510 #ifndef SIS900_MII_RESTRICT 3511 /* 3512 * The SiS 900 has only an internal PHY on the MII. Only allow 3513 * MII address 0. 3514 */ 3515 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3516 return; 3517 #endif 3518 3519 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3520 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3521 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3522 do { 3523 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3524 } while (enphy & ENPHY_ACCESS); 3525 } 3526 3527 /* 3528 * sip_sis900_mii_statchg: [mii interface function] 3529 * 3530 * Callback from MII layer when media changes. 3531 */ 3532 static void 3533 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3534 { 3535 struct sip_softc *sc = ifp->if_softc; 3536 struct mii_data *mii = &sc->sc_mii; 3537 u_int32_t flowctl; 3538 3539 /* 3540 * Get flow control negotiation result. 3541 */ 3542 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3543 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3544 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3545 mii->mii_media_active &= ~IFM_ETH_FMASK; 3546 } 3547 3548 /* 3549 * Update TXCFG for full-duplex operation. 3550 */ 3551 if ((mii->mii_media_active & IFM_FDX) != 0) 3552 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3553 else 3554 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3555 3556 /* 3557 * Update RXCFG for full-duplex or loopback. 3558 */ 3559 if ((mii->mii_media_active & IFM_FDX) != 0 || 3560 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3561 sc->sc_rxcfg |= RXCFG_ATX; 3562 else 3563 sc->sc_rxcfg &= ~RXCFG_ATX; 3564 3565 /* 3566 * Update IMR for use of 802.3x flow control. 3567 */ 3568 if (sc->sc_flowflags & IFM_FLOW) { 3569 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3570 flowctl = FLOWCTL_FLOWEN; 3571 } else { 3572 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3573 flowctl = 0; 3574 } 3575 3576 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3577 sc->sc_txcfg); 3578 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3579 sc->sc_rxcfg); 3580 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3581 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3582 } 3583 3584 /* 3585 * sip_dp83815_mii_readreg: [mii interface function] 3586 * 3587 * Read a PHY register on the MII. 3588 */ 3589 static int 3590 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg) 3591 { 3592 struct sip_softc *sc = device_private(self); 3593 u_int32_t val; 3594 3595 /* 3596 * The DP83815 only has an internal PHY. Only allow 3597 * MII address 0. 3598 */ 3599 if (phy != 0) 3600 return (0); 3601 3602 /* 3603 * Apparently, after a reset, the DP83815 can take a while 3604 * to respond. During this recovery period, the BMSR returns 3605 * a value of 0. Catch this -- it's not supposed to happen 3606 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3607 * PHY to come back to life. 3608 * 3609 * This works out because the BMSR is the first register 3610 * read during the PHY probe process. 3611 */ 3612 do { 3613 val = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3614 } while (reg == MII_BMSR && val == 0); 3615 3616 return (val & 0xffff); 3617 } 3618 3619 /* 3620 * sip_dp83815_mii_writereg: [mii interface function] 3621 * 3622 * Write a PHY register to the MII. 3623 */ 3624 static void 3625 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, int val) 3626 { 3627 struct sip_softc *sc = device_private(self); 3628 3629 /* 3630 * The DP83815 only has an internal PHY. Only allow 3631 * MII address 0. 3632 */ 3633 if (phy != 0) 3634 return; 3635 3636 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3637 } 3638 3639 /* 3640 * sip_dp83815_mii_statchg: [mii interface function] 3641 * 3642 * Callback from MII layer when media changes. 3643 */ 3644 static void 3645 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3646 { 3647 struct sip_softc *sc = ifp->if_softc; 3648 3649 /* 3650 * Update TXCFG for full-duplex operation. 3651 */ 3652 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3653 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3654 else 3655 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3656 3657 /* 3658 * Update RXCFG for full-duplex or loopback. 3659 */ 3660 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3661 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3662 sc->sc_rxcfg |= RXCFG_ATX; 3663 else 3664 sc->sc_rxcfg &= ~RXCFG_ATX; 3665 3666 /* 3667 * XXX 802.3x flow control. 3668 */ 3669 3670 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3671 sc->sc_txcfg); 3672 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3673 sc->sc_rxcfg); 3674 3675 /* 3676 * Some DP83815s experience problems when used with short 3677 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3678 * sequence adjusts the DSP's signal attenuation to fix the 3679 * problem. 3680 */ 3681 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3682 uint32_t reg; 3683 3684 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3685 3686 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3687 reg &= 0x0fff; 3688 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3689 delay(100); 3690 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3691 reg &= 0x00ff; 3692 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3693 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3694 0x00e8); 3695 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3696 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3697 reg | 0x20); 3698 } 3699 3700 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3701 } 3702 } 3703 3704 static void 3705 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3706 const struct pci_attach_args *pa, u_int8_t *enaddr) 3707 { 3708 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3709 u_int8_t cksum, *e, match; 3710 int i; 3711 3712 /* 3713 * EEPROM data format for the DP83820 can be found in 3714 * the DP83820 manual, section 4.2.4. 3715 */ 3716 3717 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3718 3719 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3720 match = ~(match - 1); 3721 3722 cksum = 0x55; 3723 e = (u_int8_t *) eeprom_data; 3724 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3725 cksum += *e++; 3726 3727 if (cksum != match) 3728 printf("%s: Checksum (%x) mismatch (%x)", 3729 device_xname(sc->sc_dev), cksum, match); 3730 3731 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3732 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3733 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3734 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3735 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3736 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3737 } 3738 3739 static void 3740 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3741 { 3742 int i; 3743 3744 /* 3745 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3746 * a reason, but I don't know it. 3747 */ 3748 for (i = 0; i < 10; i++) 3749 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3750 } 3751 3752 static void 3753 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3754 const struct pci_attach_args *pa, u_int8_t *enaddr) 3755 { 3756 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3757 3758 switch (sc->sc_rev) { 3759 case SIS_REV_630S: 3760 case SIS_REV_630E: 3761 case SIS_REV_630EA1: 3762 case SIS_REV_630ET: 3763 case SIS_REV_635: 3764 /* 3765 * The MAC address for the on-board Ethernet of 3766 * the SiS 630 chipset is in the NVRAM. Kick 3767 * the chip into re-loading it from NVRAM, and 3768 * read the MAC address out of the filter registers. 3769 */ 3770 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3771 3772 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3773 RFCR_RFADDR_NODE0); 3774 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3775 0xffff; 3776 3777 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3778 RFCR_RFADDR_NODE2); 3779 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3780 0xffff; 3781 3782 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3783 RFCR_RFADDR_NODE4); 3784 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3785 0xffff; 3786 break; 3787 3788 case SIS_REV_960: 3789 { 3790 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3791 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3792 3793 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3794 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3795 3796 int waittime, i; 3797 3798 /* Allow to read EEPROM from LAN. It is shared 3799 * between a 1394 controller and the NIC and each 3800 * time we access it, we need to set SIS_EECMD_REQ. 3801 */ 3802 SIS_SET_EROMAR(sc, EROMAR_REQ); 3803 3804 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3805 /* Force EEPROM to idle state. */ 3806 3807 /* 3808 * XXX-cube This is ugly. I'll look for docs about it. 3809 */ 3810 SIS_SET_EROMAR(sc, EROMAR_EECS); 3811 sipcom_sis900_eeprom_delay(sc); 3812 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3813 SIS_SET_EROMAR(sc, EROMAR_EESK); 3814 sipcom_sis900_eeprom_delay(sc); 3815 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3816 sipcom_sis900_eeprom_delay(sc); 3817 } 3818 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3819 sipcom_sis900_eeprom_delay(sc); 3820 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3821 3822 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3823 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3824 sizeof(myea) / sizeof(myea[0]), myea); 3825 break; 3826 } 3827 DELAY(1); 3828 } 3829 3830 /* 3831 * Set SIS_EECTL_CLK to high, so a other master 3832 * can operate on the i2c bus. 3833 */ 3834 SIS_SET_EROMAR(sc, EROMAR_EESK); 3835 3836 /* Refuse EEPROM access by LAN */ 3837 SIS_SET_EROMAR(sc, EROMAR_DONE); 3838 } break; 3839 3840 default: 3841 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3842 sizeof(myea) / sizeof(myea[0]), myea); 3843 } 3844 3845 enaddr[0] = myea[0] & 0xff; 3846 enaddr[1] = myea[0] >> 8; 3847 enaddr[2] = myea[1] & 0xff; 3848 enaddr[3] = myea[1] >> 8; 3849 enaddr[4] = myea[2] & 0xff; 3850 enaddr[5] = myea[2] >> 8; 3851 } 3852 3853 /* Table and macro to bit-reverse an octet. */ 3854 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3855 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3856 3857 static void 3858 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3859 const struct pci_attach_args *pa, u_int8_t *enaddr) 3860 { 3861 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3862 u_int8_t cksum, *e, match; 3863 int i; 3864 3865 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3866 sizeof(eeprom_data[0]), eeprom_data); 3867 3868 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3869 match = ~(match - 1); 3870 3871 cksum = 0x55; 3872 e = (u_int8_t *) eeprom_data; 3873 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3874 cksum += *e++; 3875 } 3876 if (cksum != match) { 3877 printf("%s: Checksum (%x) mismatch (%x)", 3878 device_xname(sc->sc_dev), cksum, match); 3879 } 3880 3881 /* 3882 * Unrolled because it makes slightly more sense this way. 3883 * The DP83815 stores the MAC address in bit 0 of word 6 3884 * through bit 15 of word 8. 3885 */ 3886 ea = &eeprom_data[6]; 3887 enaddr[0] = ((*ea & 0x1) << 7); 3888 ea++; 3889 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3890 enaddr[1] = ((*ea & 0x1FE) >> 1); 3891 enaddr[2] = ((*ea & 0x1) << 7); 3892 ea++; 3893 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3894 enaddr[3] = ((*ea & 0x1FE) >> 1); 3895 enaddr[4] = ((*ea & 0x1) << 7); 3896 ea++; 3897 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3898 enaddr[5] = ((*ea & 0x1FE) >> 1); 3899 3900 /* 3901 * In case that's not weird enough, we also need to reverse 3902 * the bits in each byte. This all actually makes more sense 3903 * if you think about the EEPROM storage as an array of bits 3904 * being shifted into bytes, but that's not how we're looking 3905 * at it here... 3906 */ 3907 for (i = 0; i < 6 ;i++) 3908 enaddr[i] = bbr(enaddr[i]); 3909 } 3910 3911 /* 3912 * sip_mediastatus: [ifmedia interface function] 3913 * 3914 * Get the current interface media status. 3915 */ 3916 static void 3917 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3918 { 3919 struct sip_softc *sc = ifp->if_softc; 3920 3921 if (!device_is_active(sc->sc_dev)) { 3922 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3923 ifmr->ifm_status = 0; 3924 return; 3925 } 3926 ether_mediastatus(ifp, ifmr); 3927 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3928 sc->sc_flowflags; 3929 } 3930
Indexes created Tue Sep 30 11:09:46 GMT 2025