if_sip.c revision 1.168.2.1
1 /* $NetBSD: if_sip.c,v 1.168.2.1 2019/06/10 22:07:16 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.168.2.1 2019/06/10 22:07:16 christos Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Control structures are DMA'd to the SiS900 chip. We allocate them in 142 * a single clump that maps to a single DMA segment to make several things 143 * easier. 144 */ 145 struct sip_control_data { 146 /* 147 * The transmit descriptors. 148 */ 149 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 150 151 /* 152 * The receive descriptors. 153 */ 154 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 155 }; 156 157 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 158 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 159 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 160 161 /* 162 * Software state for transmit jobs. 163 */ 164 struct sip_txsoft { 165 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 166 bus_dmamap_t txs_dmamap; /* our DMA map */ 167 int txs_firstdesc; /* first descriptor in packet */ 168 int txs_lastdesc; /* last descriptor in packet */ 169 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 170 }; 171 172 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct sip_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 enum sip_attach_stage { 183 SIP_ATTACH_FIN = 0 184 , SIP_ATTACH_CREATE_RXMAP 185 , SIP_ATTACH_CREATE_TXMAP 186 , SIP_ATTACH_LOAD_MAP 187 , SIP_ATTACH_CREATE_MAP 188 , SIP_ATTACH_MAP_MEM 189 , SIP_ATTACH_ALLOC_MEM 190 , SIP_ATTACH_INTR 191 , SIP_ATTACH_MAP 192 }; 193 194 /* 195 * Software state per device. 196 */ 197 struct sip_softc { 198 device_t sc_dev; /* generic device information */ 199 device_suspensor_t sc_suspensor; 200 pmf_qual_t sc_qual; 201 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_size_t sc_sz; /* bus space size */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 pci_chipset_tag_t sc_pc; 207 bus_dma_segment_t sc_seg; 208 struct ethercom sc_ethercom; /* ethernet common data */ 209 210 const struct sip_product *sc_model; /* which model are we? */ 211 int sc_gigabit; /* 1: 83820, 0: other */ 212 int sc_rev; /* chip revision */ 213 214 void *sc_ih; /* interrupt cookie */ 215 216 struct mii_data sc_mii; /* MII/media information */ 217 218 callout_t sc_tick_ch; /* tick callout */ 219 220 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 221 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 222 223 /* 224 * Software state for transmit and receive descriptors. 225 */ 226 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 227 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 228 229 /* 230 * Control data structures. 231 */ 232 struct sip_control_data *sc_control_data; 233 #define sc_txdescs sc_control_data->scd_txdescs 234 #define sc_rxdescs sc_control_data->scd_rxdescs 235 236 #ifdef SIP_EVENT_COUNTERS 237 /* 238 * Event counters. 239 */ 240 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 241 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 242 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 243 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 244 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 245 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 246 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 247 struct evcnt sc_ev_rxpause; /* PAUSE received */ 248 /* DP83820 only */ 249 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 250 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 251 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 252 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 253 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 254 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 255 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 uint32_t sc_txcfg; /* prototype TXCFG register */ 259 uint32_t sc_rxcfg; /* prototype RXCFG register */ 260 uint32_t sc_imr; /* prototype IMR register */ 261 uint32_t sc_rfcr; /* prototype RFCR register */ 262 263 uint32_t sc_cfg; /* prototype CFG register */ 264 265 uint32_t sc_gpior; /* prototype GPIOR register */ 266 267 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 268 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 269 270 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 271 272 int sc_flowflags; /* 802.3x flow control flags */ 273 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 274 int sc_paused; /* paused indication */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 int sc_txwin; /* Tx descriptors since last intr */ 279 280 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 281 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 282 283 /* values of interface state at last init */ 284 struct { 285 /* if_capenable */ 286 uint64_t if_capenable; 287 /* ec_capenable */ 288 int ec_capenable; 289 /* VLAN_ATTACHED */ 290 int is_vlan; 291 } sc_prev; 292 293 short sc_if_flags; 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 int sc_rxdiscard; 297 int sc_rxlen; 298 struct mbuf *sc_rxhead; 299 struct mbuf *sc_rxtail; 300 struct mbuf **sc_rxtailp; 301 302 int sc_ntxdesc; 303 int sc_ntxdesc_mask; 304 305 int sc_nrxdesc_mask; 306 307 const struct sip_parm { 308 const struct sip_regs { 309 int r_rxcfg; 310 int r_txcfg; 311 } p_regs; 312 313 const struct sip_bits { 314 uint32_t b_txcfg_mxdma_8; 315 uint32_t b_txcfg_mxdma_16; 316 uint32_t b_txcfg_mxdma_32; 317 uint32_t b_txcfg_mxdma_64; 318 uint32_t b_txcfg_mxdma_128; 319 uint32_t b_txcfg_mxdma_256; 320 uint32_t b_txcfg_mxdma_512; 321 uint32_t b_txcfg_flth_mask; 322 uint32_t b_txcfg_drth_mask; 323 324 uint32_t b_rxcfg_mxdma_8; 325 uint32_t b_rxcfg_mxdma_16; 326 uint32_t b_rxcfg_mxdma_32; 327 uint32_t b_rxcfg_mxdma_64; 328 uint32_t b_rxcfg_mxdma_128; 329 uint32_t b_rxcfg_mxdma_256; 330 uint32_t b_rxcfg_mxdma_512; 331 332 uint32_t b_isr_txrcmp; 333 uint32_t b_isr_rxrcmp; 334 uint32_t b_isr_dperr; 335 uint32_t b_isr_sserr; 336 uint32_t b_isr_rmabt; 337 uint32_t b_isr_rtabt; 338 339 uint32_t b_cmdsts_size_mask; 340 } p_bits; 341 int p_filtmem; 342 int p_rxbuf_len; 343 bus_size_t p_tx_dmamap_size; 344 int p_ntxsegs; 345 int p_ntxsegs_alloc; 346 int p_nrxdesc; 347 } *sc_parm; 348 349 void (*sc_rxintr)(struct sip_softc *); 350 351 krndsource_t rnd_source; /* random source */ 352 }; 353 354 #define sc_bits sc_parm->p_bits 355 #define sc_regs sc_parm->p_regs 356 357 static const struct sip_parm sip_parm = { 358 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 359 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 360 , .p_tx_dmamap_size = MCLBYTES 361 , .p_ntxsegs = 16 362 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 363 , .p_nrxdesc = SIP_NRXDESC 364 , .p_bits = { 365 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 366 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 367 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 368 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 369 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 370 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 371 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 372 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 373 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 374 375 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 383 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 384 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 385 , .b_isr_dperr = 0x00800000 /* detected parity error */ 386 , .b_isr_sserr = 0x00400000 /* signalled system error */ 387 , .b_isr_rmabt = 0x00200000 /* received master abort */ 388 , .b_isr_rtabt = 0x00100000 /* received target abort */ 389 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 390 } 391 , .p_regs = { 392 .r_rxcfg = OTHER_SIP_RXCFG, 393 .r_txcfg = OTHER_SIP_TXCFG 394 } 395 }, gsip_parm = { 396 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 397 , .p_rxbuf_len = MCLBYTES - 8 398 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 399 , .p_ntxsegs = 64 400 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 401 , .p_nrxdesc = GSIP_NRXDESC 402 , .p_bits = { 403 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 404 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 405 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 406 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 407 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 408 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 409 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 410 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 411 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 412 413 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 421 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 422 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 423 , .b_isr_dperr = 0x00100000 /* detected parity error */ 424 , .b_isr_sserr = 0x00080000 /* signalled system error */ 425 , .b_isr_rmabt = 0x00040000 /* received master abort */ 426 , .b_isr_rtabt = 0x00020000 /* received target abort */ 427 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 428 } 429 , .p_regs = { 430 .r_rxcfg = DP83820_SIP_RXCFG, 431 .r_txcfg = DP83820_SIP_TXCFG 432 } 433 }; 434 435 static inline int 436 sip_nexttx(const struct sip_softc *sc, int x) 437 { 438 return (x + 1) & sc->sc_ntxdesc_mask; 439 } 440 441 static inline int 442 sip_nextrx(const struct sip_softc *sc, int x) 443 { 444 return (x + 1) & sc->sc_nrxdesc_mask; 445 } 446 447 /* 83820 only */ 448 static inline void 449 sip_rxchain_reset(struct sip_softc *sc) 450 { 451 sc->sc_rxtailp = &sc->sc_rxhead; 452 *sc->sc_rxtailp = NULL; 453 sc->sc_rxlen = 0; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 459 { 460 *sc->sc_rxtailp = sc->sc_rxtail = m; 461 sc->sc_rxtailp = &m->m_next; 462 } 463 464 #ifdef SIP_EVENT_COUNTERS 465 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 466 #else 467 #define SIP_EVCNT_INCR(ev) /* nothing */ 468 #endif 469 470 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 471 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 472 473 static inline void 474 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 475 { 476 int x, n; 477 478 x = x0; 479 n = n0; 480 481 /* If it will wrap around, sync to the end of the ring. */ 482 if (x + n > sc->sc_ntxdesc) { 483 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 484 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 485 (sc->sc_ntxdesc - x), ops); 486 n -= (sc->sc_ntxdesc - x); 487 x = 0; 488 } 489 490 /* Now sync whatever is left. */ 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 493 } 494 495 static inline void 496 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 497 { 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 499 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 500 } 501 502 #if 0 503 #ifdef DP83820 504 uint32_t sipd_bufptr; /* pointer to DMA segment */ 505 uint32_t sipd_cmdsts; /* command/status word */ 506 #else 507 uint32_t sipd_cmdsts; /* command/status word */ 508 uint32_t sipd_bufptr; /* pointer to DMA segment */ 509 #endif /* DP83820 */ 510 #endif /* 0 */ 511 512 static inline volatile uint32_t * 513 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 514 { 515 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 516 } 517 518 static inline volatile uint32_t * 519 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 520 { 521 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 522 } 523 524 static inline void 525 sip_init_rxdesc(struct sip_softc *sc, int x) 526 { 527 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 528 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 529 530 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 531 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 532 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 533 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 534 sipd->sipd_extsts = 0; 535 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 536 } 537 538 #define SIP_CHIP_VERS(sc, v, p, r) \ 539 ((sc)->sc_model->sip_vendor == (v) && \ 540 (sc)->sc_model->sip_product == (p) && \ 541 (sc)->sc_rev == (r)) 542 543 #define SIP_CHIP_MODEL(sc, v, p) \ 544 ((sc)->sc_model->sip_vendor == (v) && \ 545 (sc)->sc_model->sip_product == (p)) 546 547 #define SIP_SIS900_REV(sc, rev) \ 548 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 549 550 #define SIP_TIMEOUT 1000 551 552 static int sip_ifflags_cb(struct ethercom *); 553 static void sipcom_start(struct ifnet *); 554 static void sipcom_watchdog(struct ifnet *); 555 static int sipcom_ioctl(struct ifnet *, u_long, void *); 556 static int sipcom_init(struct ifnet *); 557 static void sipcom_stop(struct ifnet *, int); 558 559 static bool sipcom_reset(struct sip_softc *); 560 static void sipcom_rxdrain(struct sip_softc *); 561 static int sipcom_add_rxbuf(struct sip_softc *, int); 562 static void sipcom_read_eeprom(struct sip_softc *, int, int, 563 uint16_t *); 564 static void sipcom_tick(void *); 565 566 static void sipcom_sis900_set_filter(struct sip_softc *); 567 static void sipcom_dp83815_set_filter(struct sip_softc *); 568 569 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 570 const struct pci_attach_args *, uint8_t *); 571 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 572 static void sipcom_sis900_read_macaddr(struct sip_softc *, 573 const struct pci_attach_args *, uint8_t *); 574 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 575 const struct pci_attach_args *, uint8_t *); 576 577 static int sipcom_intr(void *); 578 static void sipcom_txintr(struct sip_softc *); 579 static void sip_rxintr(struct sip_softc *); 580 static void gsip_rxintr(struct sip_softc *); 581 582 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 583 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 584 static void sipcom_dp83820_mii_statchg(struct ifnet *); 585 586 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_sis900_mii_statchg(struct ifnet *); 589 590 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_dp83815_mii_statchg(struct ifnet *); 593 594 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 595 596 static int sipcom_match(device_t, cfdata_t, void *); 597 static void sipcom_attach(device_t, device_t, void *); 598 static void sipcom_do_detach(device_t, enum sip_attach_stage); 599 static int sipcom_detach(device_t, int); 600 static bool sipcom_resume(device_t, const pmf_qual_t *); 601 static bool sipcom_suspend(device_t, const pmf_qual_t *); 602 603 int gsip_copy_small = 0; 604 int sip_copy_small = 0; 605 606 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 607 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 608 DVF_DETACH_SHUTDOWN); 609 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 610 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 611 DVF_DETACH_SHUTDOWN); 612 613 /* 614 * Descriptions of the variants of the SiS900. 615 */ 616 struct sip_variant { 617 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 618 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 619 void (*sipv_mii_statchg)(struct ifnet *); 620 void (*sipv_set_filter)(struct sip_softc *); 621 void (*sipv_read_macaddr)(struct sip_softc *, 622 const struct pci_attach_args *, uint8_t *); 623 }; 624 625 static uint32_t sipcom_mii_bitbang_read(device_t); 626 static void sipcom_mii_bitbang_write(device_t, uint32_t); 627 628 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 629 sipcom_mii_bitbang_read, 630 sipcom_mii_bitbang_write, 631 { 632 EROMAR_MDIO, /* MII_BIT_MDO */ 633 EROMAR_MDIO, /* MII_BIT_MDI */ 634 EROMAR_MDC, /* MII_BIT_MDC */ 635 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 636 0, /* MII_BIT_DIR_PHY_HOST */ 637 } 638 }; 639 640 static const struct sip_variant sipcom_variant_dp83820 = { 641 sipcom_dp83820_mii_readreg, 642 sipcom_dp83820_mii_writereg, 643 sipcom_dp83820_mii_statchg, 644 sipcom_dp83815_set_filter, 645 sipcom_dp83820_read_macaddr, 646 }; 647 648 static const struct sip_variant sipcom_variant_sis900 = { 649 sipcom_sis900_mii_readreg, 650 sipcom_sis900_mii_writereg, 651 sipcom_sis900_mii_statchg, 652 sipcom_sis900_set_filter, 653 sipcom_sis900_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_dp83815 = { 657 sipcom_dp83815_mii_readreg, 658 sipcom_dp83815_mii_writereg, 659 sipcom_dp83815_mii_statchg, 660 sipcom_dp83815_set_filter, 661 sipcom_dp83815_read_macaddr, 662 }; 663 664 665 /* 666 * Devices supported by this driver. 667 */ 668 static const struct sip_product { 669 pci_vendor_id_t sip_vendor; 670 pci_product_id_t sip_product; 671 const char *sip_name; 672 const struct sip_variant *sip_variant; 673 int sip_gigabit; 674 } sipcom_products[] = { 675 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 676 "NatSemi DP83820 Gigabit Ethernet", 677 &sipcom_variant_dp83820, 1 }, 678 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 679 "SiS 900 10/100 Ethernet", 680 &sipcom_variant_sis900, 0 }, 681 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 682 "SiS 7016 10/100 Ethernet", 683 &sipcom_variant_sis900, 0 }, 684 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 686 "NatSemi DP83815 10/100 Ethernet", 687 &sipcom_variant_dp83815, 0 }, 688 689 { 0, 0, 690 NULL, 691 NULL, 0 }, 692 }; 693 694 static const struct sip_product * 695 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 696 { 697 const struct sip_product *sip; 698 699 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 700 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 701 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 702 sip->sip_gigabit == gigabit) 703 return sip; 704 } 705 return NULL; 706 } 707 708 /* 709 * I really hate stupid hardware vendors. There's a bit in the EEPROM 710 * which indicates if the card can do 64-bit data transfers. Unfortunately, 711 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 712 * which means we try to use 64-bit data transfers on those cards if we 713 * happen to be plugged into a 32-bit slot. 714 * 715 * What we do is use this table of cards known to be 64-bit cards. If 716 * you have a 64-bit card who's subsystem ID is not listed in this table, 717 * send the output of "pcictl dump ..." of the device to me so that your 718 * card will use the 64-bit data path when plugged into a 64-bit slot. 719 * 720 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 721 * June 30, 2002 722 */ 723 static int 724 sipcom_check_64bit(const struct pci_attach_args *pa) 725 { 726 static const struct { 727 pci_vendor_id_t c64_vendor; 728 pci_product_id_t c64_product; 729 } card64[] = { 730 /* Asante GigaNIX */ 731 { 0x128a, 0x0002 }, 732 733 /* Accton EN1407-T, Planex GN-1000TE */ 734 { 0x1113, 0x1407 }, 735 736 /* Netgear GA621 */ 737 { 0x1385, 0x621a }, 738 739 /* Netgear GA622 */ 740 { 0x1385, 0x622a }, 741 742 /* SMC EZ Card 1000 (9462TX) */ 743 { 0x10b8, 0x9462 }, 744 745 { 0, 0} 746 }; 747 pcireg_t subsys; 748 int i; 749 750 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 752 for (i = 0; card64[i].c64_vendor != 0; i++) { 753 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 754 PCI_PRODUCT(subsys) == card64[i].c64_product) 755 return 1; 756 } 757 758 return 0; 759 } 760 761 static int 762 sipcom_match(device_t parent, cfdata_t cf, void *aux) 763 { 764 struct pci_attach_args *pa = aux; 765 766 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 767 return 1; 768 769 return 0; 770 } 771 772 static void 773 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 774 { 775 uint32_t reg; 776 int i; 777 778 /* 779 * Cause the chip to load configuration data from the EEPROM. 780 */ 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 782 for (i = 0; i < 10000; i++) { 783 delay(10); 784 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 785 PTSCR_EELOAD_EN) == 0) 786 break; 787 } 788 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) { 790 printf("%s: timeout loading configuration from EEPROM\n", 791 device_xname(sc->sc_dev)); 792 return; 793 } 794 795 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 796 797 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 798 if (reg & CFG_PCI64_DET) { 799 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 800 /* 801 * Check to see if this card is 64-bit. If so, enable 64-bit 802 * data transfers. 803 * 804 * We can't use the DATA64_EN bit in the EEPROM, because 805 * vendors of 32-bit cards fail to clear that bit in many 806 * cases (yet the card still detects that it's in a 64-bit 807 * slot; go figure). 808 */ 809 if (sipcom_check_64bit(pa)) { 810 sc->sc_cfg |= CFG_DATA64_EN; 811 printf(", using 64-bit data transfers"); 812 } 813 printf("\n"); 814 } 815 816 /* 817 * XXX Need some PCI flags indicating support for 818 * XXX 64-bit addressing. 819 */ 820 #if 0 821 if (reg & CFG_M64ADDR) 822 sc->sc_cfg |= CFG_M64ADDR; 823 if (reg & CFG_T64ADDR) 824 sc->sc_cfg |= CFG_T64ADDR; 825 #endif 826 827 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 828 const char *sep = ""; 829 printf("%s: using ", device_xname(sc->sc_dev)); 830 if (reg & CFG_EXT_125) { 831 sc->sc_cfg |= CFG_EXT_125; 832 printf("%s125MHz clock", sep); 833 sep = ", "; 834 } 835 if (reg & CFG_TBI_EN) { 836 sc->sc_cfg |= CFG_TBI_EN; 837 printf("%sten-bit interface", sep); 838 sep = ", "; 839 } 840 printf("\n"); 841 } 842 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 843 (reg & CFG_MRM_DIS) != 0) 844 sc->sc_cfg |= CFG_MRM_DIS; 845 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 846 (reg & CFG_MWI_DIS) != 0) 847 sc->sc_cfg |= CFG_MWI_DIS; 848 849 /* 850 * Use the extended descriptor format on the DP83820. This 851 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 852 * checksumming. 853 */ 854 sc->sc_cfg |= CFG_EXTSTS_EN; 855 } 856 857 static int 858 sipcom_detach(device_t self, int flags) 859 { 860 int s; 861 862 s = splnet(); 863 sipcom_do_detach(self, SIP_ATTACH_FIN); 864 splx(s); 865 866 return 0; 867 } 868 869 static void 870 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 871 { 872 int i; 873 struct sip_softc *sc = device_private(self); 874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 875 876 /* 877 * Free any resources we've allocated during attach. 878 * Do this in reverse order and fall through. 879 */ 880 switch (stage) { 881 case SIP_ATTACH_FIN: 882 sipcom_stop(ifp, 1); 883 pmf_device_deregister(self); 884 #ifdef SIP_EVENT_COUNTERS 885 /* 886 * Attach event counters. 887 */ 888 evcnt_detach(&sc->sc_ev_txforceintr); 889 evcnt_detach(&sc->sc_ev_txdstall); 890 evcnt_detach(&sc->sc_ev_txsstall); 891 evcnt_detach(&sc->sc_ev_hiberr); 892 evcnt_detach(&sc->sc_ev_rxintr); 893 evcnt_detach(&sc->sc_ev_txiintr); 894 evcnt_detach(&sc->sc_ev_txdintr); 895 if (!sc->sc_gigabit) { 896 evcnt_detach(&sc->sc_ev_rxpause); 897 } else { 898 evcnt_detach(&sc->sc_ev_txudpsum); 899 evcnt_detach(&sc->sc_ev_txtcpsum); 900 evcnt_detach(&sc->sc_ev_txipsum); 901 evcnt_detach(&sc->sc_ev_rxudpsum); 902 evcnt_detach(&sc->sc_ev_rxtcpsum); 903 evcnt_detach(&sc->sc_ev_rxipsum); 904 evcnt_detach(&sc->sc_ev_txpause); 905 evcnt_detach(&sc->sc_ev_rxpause); 906 } 907 #endif /* SIP_EVENT_COUNTERS */ 908 909 rnd_detach_source(&sc->rnd_source); 910 911 ether_ifdetach(ifp); 912 if_detach(ifp); 913 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 914 915 /*FALLTHROUGH*/ 916 case SIP_ATTACH_CREATE_RXMAP: 917 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 918 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 919 bus_dmamap_destroy(sc->sc_dmat, 920 sc->sc_rxsoft[i].rxs_dmamap); 921 } 922 /*FALLTHROUGH*/ 923 case SIP_ATTACH_CREATE_TXMAP: 924 for (i = 0; i < SIP_TXQUEUELEN; i++) { 925 if (sc->sc_txsoft[i].txs_dmamap != NULL) 926 bus_dmamap_destroy(sc->sc_dmat, 927 sc->sc_txsoft[i].txs_dmamap); 928 } 929 /*FALLTHROUGH*/ 930 case SIP_ATTACH_LOAD_MAP: 931 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 932 /*FALLTHROUGH*/ 933 case SIP_ATTACH_CREATE_MAP: 934 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_MAP_MEM: 937 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 938 sizeof(struct sip_control_data)); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_ALLOC_MEM: 941 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 942 /* FALLTHROUGH*/ 943 case SIP_ATTACH_INTR: 944 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 945 /* FALLTHROUGH*/ 946 case SIP_ATTACH_MAP: 947 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 948 break; 949 default: 950 break; 951 } 952 return; 953 } 954 955 static bool 956 sipcom_resume(device_t self, const pmf_qual_t *qual) 957 { 958 struct sip_softc *sc = device_private(self); 959 960 return sipcom_reset(sc); 961 } 962 963 static bool 964 sipcom_suspend(device_t self, const pmf_qual_t *qual) 965 { 966 struct sip_softc *sc = device_private(self); 967 968 sipcom_rxdrain(sc); 969 return true; 970 } 971 972 static void 973 sipcom_attach(device_t parent, device_t self, void *aux) 974 { 975 struct sip_softc *sc = device_private(self); 976 struct pci_attach_args *pa = aux; 977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 978 struct mii_data * const mii = &sc->sc_mii; 979 pci_chipset_tag_t pc = pa->pa_pc; 980 pci_intr_handle_t ih; 981 const char *intrstr = NULL; 982 bus_space_tag_t iot, memt; 983 bus_space_handle_t ioh, memh; 984 bus_size_t iosz, memsz; 985 int ioh_valid, memh_valid; 986 int i, rseg, error; 987 const struct sip_product *sip; 988 uint8_t enaddr[ETHER_ADDR_LEN]; 989 pcireg_t csr; 990 pcireg_t memtype; 991 bus_size_t tx_dmamap_size; 992 int ntxsegs_alloc; 993 cfdata_t cf = device_cfdata(self); 994 char intrbuf[PCI_INTRSTR_LEN]; 995 996 callout_init(&sc->sc_tick_ch, 0); 997 998 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 999 if (sip == NULL) { 1000 aprint_error("\n"); 1001 panic("%s: impossible", __func__); 1002 } 1003 sc->sc_dev = self; 1004 sc->sc_gigabit = sip->sip_gigabit; 1005 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1006 sc->sc_pc = pc; 1007 1008 if (sc->sc_gigabit) { 1009 sc->sc_rxintr = gsip_rxintr; 1010 sc->sc_parm = &gsip_parm; 1011 } else { 1012 sc->sc_rxintr = sip_rxintr; 1013 sc->sc_parm = &sip_parm; 1014 } 1015 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1016 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1017 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1018 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1019 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1020 1021 sc->sc_rev = PCI_REVISION(pa->pa_class); 1022 1023 aprint_naive("\n"); 1024 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1025 1026 sc->sc_model = sip; 1027 1028 /* 1029 * XXX Work-around broken PXE firmware on some boards. 1030 * 1031 * The DP83815 shares an address decoder with the MEM BAR 1032 * and the ROM BAR. Make sure the ROM BAR is disabled, 1033 * so that memory mapped access works. 1034 */ 1035 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1036 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1037 ~PCI_MAPREG_ROM_ENABLE); 1038 1039 /* 1040 * Map the device. 1041 */ 1042 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1043 PCI_MAPREG_TYPE_IO, 0, 1044 &iot, &ioh, NULL, &iosz) == 0); 1045 if (sc->sc_gigabit) { 1046 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1047 switch (memtype) { 1048 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1049 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1050 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1051 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1052 break; 1053 default: 1054 memh_valid = 0; 1055 } 1056 } else { 1057 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1058 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1059 &memt, &memh, NULL, &memsz) == 0); 1060 } 1061 1062 if (memh_valid) { 1063 sc->sc_st = memt; 1064 sc->sc_sh = memh; 1065 sc->sc_sz = memsz; 1066 } else if (ioh_valid) { 1067 sc->sc_st = iot; 1068 sc->sc_sh = ioh; 1069 sc->sc_sz = iosz; 1070 } else { 1071 aprint_error_dev(self, "unable to map device registers\n"); 1072 return; 1073 } 1074 1075 sc->sc_dmat = pa->pa_dmat; 1076 1077 /* 1078 * Make sure bus mastering is enabled. Also make sure 1079 * Write/Invalidate is enabled if we're allowed to use it. 1080 */ 1081 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1082 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1083 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1084 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1085 csr | PCI_COMMAND_MASTER_ENABLE); 1086 1087 /* Power up chip */ 1088 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1089 if (error != 0 && error != EOPNOTSUPP) { 1090 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1091 return; 1092 } 1093 1094 /* 1095 * Map and establish our interrupt. 1096 */ 1097 if (pci_intr_map(pa, &ih)) { 1098 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1099 return; 1100 } 1101 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1102 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1103 device_xname(self)); 1104 if (sc->sc_ih == NULL) { 1105 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1106 if (intrstr != NULL) 1107 aprint_error(" at %s", intrstr); 1108 aprint_error("\n"); 1109 sipcom_do_detach(self, SIP_ATTACH_MAP); 1110 return; 1111 } 1112 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1113 1114 SIMPLEQ_INIT(&sc->sc_txfreeq); 1115 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1116 1117 /* 1118 * Allocate the control data structures, and create and load the 1119 * DMA map for it. 1120 */ 1121 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1122 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1123 &rseg, 0)) != 0) { 1124 aprint_error_dev(sc->sc_dev, 1125 "unable to allocate control data, error = %d\n", error); 1126 sipcom_do_detach(self, SIP_ATTACH_INTR); 1127 return; 1128 } 1129 1130 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1131 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1132 BUS_DMA_COHERENT)) != 0) { 1133 aprint_error_dev(sc->sc_dev, 1134 "unable to map control data, error = %d\n", error); 1135 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1136 } 1137 1138 if ((error = bus_dmamap_create(sc->sc_dmat, 1139 sizeof(struct sip_control_data), 1, 1140 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1141 aprint_error_dev(self, "unable to create control data DMA map" 1142 ", error = %d\n", error); 1143 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1144 } 1145 1146 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1147 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1148 0)) != 0) { 1149 aprint_error_dev(self, "unable to load control data DMA map" 1150 ", error = %d\n", error); 1151 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1152 } 1153 1154 /* 1155 * Create the transmit buffer DMA maps. 1156 */ 1157 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1158 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1159 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1160 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1161 aprint_error_dev(self, "unable to create tx DMA map %d" 1162 ", error = %d\n", i, error); 1163 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1164 } 1165 } 1166 1167 /* 1168 * Create the receive buffer DMA maps. 1169 */ 1170 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1171 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1172 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1173 aprint_error_dev(self, "unable to create rx DMA map %d" 1174 ", error = %d\n", i, error); 1175 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1176 } 1177 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1178 } 1179 1180 /* 1181 * Reset the chip to a known state. 1182 */ 1183 sipcom_reset(sc); 1184 1185 /* 1186 * Read the Ethernet address from the EEPROM. This might 1187 * also fetch other stuff from the EEPROM and stash it 1188 * in the softc. 1189 */ 1190 sc->sc_cfg = 0; 1191 if (!sc->sc_gigabit) { 1192 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1193 SIP_SIS900_REV(sc, SIS_REV_900B)) 1194 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1195 1196 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1197 SIP_SIS900_REV(sc, SIS_REV_960) || 1198 SIP_SIS900_REV(sc, SIS_REV_900B)) 1199 sc->sc_cfg |= 1200 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1201 CFG_EDBMASTEN); 1202 } 1203 1204 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1205 1206 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1207 1208 /* 1209 * Initialize the configuration register: aggressive PCI 1210 * bus request algorithm, default backoff, default OW timer, 1211 * default parity error detection. 1212 * 1213 * NOTE: "Big endian mode" is useless on the SiS900 and 1214 * friends -- it affects packet data, not descriptors. 1215 */ 1216 if (sc->sc_gigabit) 1217 sipcom_dp83820_attach(sc, pa); 1218 1219 /* 1220 * Initialize our media structures and probe the MII. 1221 */ 1222 mii->mii_ifp = ifp; 1223 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1224 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1225 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1226 sc->sc_ethercom.ec_mii = mii; 1227 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1228 sipcom_mediastatus); 1229 1230 /* 1231 * XXX We cannot handle flow control on the DP83815. 1232 */ 1233 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1234 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1235 MII_OFFSET_ANY, 0); 1236 else 1237 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, MIIF_DOPAUSE); 1239 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1240 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1241 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1242 } else 1243 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1244 1245 ifp = &sc->sc_ethercom.ec_if; 1246 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1247 ifp->if_softc = sc; 1248 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1249 sc->sc_if_flags = ifp->if_flags; 1250 ifp->if_ioctl = sipcom_ioctl; 1251 ifp->if_start = sipcom_start; 1252 ifp->if_watchdog = sipcom_watchdog; 1253 ifp->if_init = sipcom_init; 1254 ifp->if_stop = sipcom_stop; 1255 IFQ_SET_READY(&ifp->if_snd); 1256 1257 /* 1258 * We can support 802.1Q VLAN-sized frames. 1259 */ 1260 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1261 1262 if (sc->sc_gigabit) { 1263 /* 1264 * And the DP83820 can do VLAN tagging in hardware, and 1265 * support the jumbo Ethernet MTU. 1266 */ 1267 sc->sc_ethercom.ec_capabilities |= 1268 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1269 1270 /* 1271 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1272 * in hardware. 1273 */ 1274 ifp->if_capabilities |= 1275 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1276 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1277 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1278 } 1279 1280 /* 1281 * Attach the interface. 1282 */ 1283 if_attach(ifp); 1284 if_deferred_start_init(ifp, NULL); 1285 ether_ifattach(ifp, enaddr); 1286 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1287 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1288 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1289 sc->sc_prev.if_capenable = ifp->if_capenable; 1290 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1291 RND_TYPE_NET, RND_FLAG_DEFAULT); 1292 1293 /* 1294 * The number of bytes that must be available in 1295 * the Tx FIFO before the bus master can DMA more 1296 * data into the FIFO. 1297 */ 1298 sc->sc_tx_fill_thresh = 64 / 32; 1299 1300 /* 1301 * Start at a drain threshold of 512 bytes. We will 1302 * increase it if a DMA underrun occurs. 1303 * 1304 * XXX The minimum value of this variable should be 1305 * tuned. We may be able to improve performance 1306 * by starting with a lower value. That, however, 1307 * may trash the first few outgoing packets if the 1308 * PCI bus is saturated. 1309 */ 1310 if (sc->sc_gigabit) 1311 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1312 else 1313 sc->sc_tx_drain_thresh = 1504 / 32; 1314 1315 /* 1316 * Initialize the Rx FIFO drain threshold. 1317 * 1318 * This is in units of 8 bytes. 1319 * 1320 * We should never set this value lower than 2; 14 bytes are 1321 * required to filter the packet. 1322 */ 1323 sc->sc_rx_drain_thresh = 128 / 8; 1324 1325 #ifdef SIP_EVENT_COUNTERS 1326 /* 1327 * Attach event counters. 1328 */ 1329 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1330 NULL, device_xname(sc->sc_dev), "txsstall"); 1331 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1332 NULL, device_xname(sc->sc_dev), "txdstall"); 1333 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1334 NULL, device_xname(sc->sc_dev), "txforceintr"); 1335 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1336 NULL, device_xname(sc->sc_dev), "txdintr"); 1337 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1338 NULL, device_xname(sc->sc_dev), "txiintr"); 1339 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1340 NULL, device_xname(sc->sc_dev), "rxintr"); 1341 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1342 NULL, device_xname(sc->sc_dev), "hiberr"); 1343 if (!sc->sc_gigabit) { 1344 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1345 NULL, device_xname(sc->sc_dev), "rxpause"); 1346 } else { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1348 NULL, device_xname(sc->sc_dev), "rxpause"); 1349 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1350 NULL, device_xname(sc->sc_dev), "txpause"); 1351 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1352 NULL, device_xname(sc->sc_dev), "rxipsum"); 1353 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1354 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1355 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1356 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1357 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1358 NULL, device_xname(sc->sc_dev), "txipsum"); 1359 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1360 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1361 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1362 NULL, device_xname(sc->sc_dev), "txudpsum"); 1363 } 1364 #endif /* SIP_EVENT_COUNTERS */ 1365 1366 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1367 pmf_class_network_register(self, ifp); 1368 else 1369 aprint_error_dev(self, "couldn't establish power handler\n"); 1370 } 1371 1372 static inline void 1373 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1374 uint64_t capenable) 1375 { 1376 uint32_t extsts; 1377 #ifdef DEBUG 1378 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1379 #endif 1380 /* 1381 * If VLANs are enabled and the packet has a VLAN tag, set 1382 * up the descriptor to encapsulate the packet for us. 1383 * 1384 * This apparently has to be on the last descriptor of 1385 * the packet. 1386 */ 1387 1388 /* 1389 * Byte swapping is tricky. We need to provide the tag 1390 * in a network byte order. On a big-endian machine, 1391 * the byteorder is correct, but we need to swap it 1392 * anyway, because this will be undone by the outside 1393 * htole32(). That's why there must be an 1394 * unconditional swap instead of htons() inside. 1395 */ 1396 if (vlan_has_tag(m0)) { 1397 sc->sc_txdescs[lasttx].sipd_extsts |= 1398 htole32(EXTSTS_VPKT | 1399 (bswap16(vlan_get_tag(m0)) & 1400 EXTSTS_VTCI)); 1401 } 1402 1403 /* 1404 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1405 * checksumming, set up the descriptor to do this work 1406 * for us. 1407 * 1408 * This apparently has to be on the first descriptor of 1409 * the packet. 1410 * 1411 * Byte-swap constants so the compiler can optimize. 1412 */ 1413 extsts = 0; 1414 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1415 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1416 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1417 extsts |= htole32(EXTSTS_IPPKT); 1418 } 1419 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1420 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1421 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1422 extsts |= htole32(EXTSTS_TCPPKT); 1423 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1424 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1425 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1426 extsts |= htole32(EXTSTS_UDPPKT); 1427 } 1428 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1429 } 1430 1431 /* 1432 * sip_start: [ifnet interface function] 1433 * 1434 * Start packet transmission on the interface. 1435 */ 1436 static void 1437 sipcom_start(struct ifnet *ifp) 1438 { 1439 struct sip_softc *sc = ifp->if_softc; 1440 struct mbuf *m0; 1441 struct mbuf *m; 1442 struct sip_txsoft *txs; 1443 bus_dmamap_t dmamap; 1444 int error, nexttx, lasttx, seg; 1445 int ofree = sc->sc_txfree; 1446 #if 0 1447 int firsttx = sc->sc_txnext; 1448 #endif 1449 1450 /* 1451 * If we've been told to pause, don't transmit any more packets. 1452 */ 1453 if (!sc->sc_gigabit && sc->sc_paused) 1454 ifp->if_flags |= IFF_OACTIVE; 1455 1456 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1457 return; 1458 1459 /* 1460 * Loop through the send queue, setting up transmit descriptors 1461 * until we drain the queue, or use up all available transmit 1462 * descriptors. 1463 */ 1464 for (;;) { 1465 /* Get a work queue entry. */ 1466 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1467 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1468 break; 1469 } 1470 1471 /* 1472 * Grab a packet off the queue. 1473 */ 1474 IFQ_POLL(&ifp->if_snd, m0); 1475 if (m0 == NULL) 1476 break; 1477 m = NULL; 1478 1479 dmamap = txs->txs_dmamap; 1480 1481 /* 1482 * Load the DMA map. If this fails, the packet either 1483 * didn't fit in the alloted number of segments, or we 1484 * were short on resources. 1485 */ 1486 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1487 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1488 /* In the non-gigabit case, we'll copy and try again. */ 1489 if (error != 0 && !sc->sc_gigabit) { 1490 MGETHDR(m, M_DONTWAIT, MT_DATA); 1491 if (m == NULL) { 1492 printf("%s: unable to allocate Tx mbuf\n", 1493 device_xname(sc->sc_dev)); 1494 break; 1495 } 1496 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1497 if (m0->m_pkthdr.len > MHLEN) { 1498 MCLGET(m, M_DONTWAIT); 1499 if ((m->m_flags & M_EXT) == 0) { 1500 printf("%s: unable to allocate Tx " 1501 "cluster\n", 1502 device_xname(sc->sc_dev)); 1503 m_freem(m); 1504 break; 1505 } 1506 } 1507 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1508 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1509 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1510 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1511 if (error) { 1512 printf("%s: unable to load Tx buffer, error = " 1513 "%d\n", device_xname(sc->sc_dev), error); 1514 break; 1515 } 1516 } else if (error == EFBIG) { 1517 /* 1518 * For the too-many-segments case, we simply 1519 * report an error and drop the packet, 1520 * since we can't sanely copy a jumbo packet 1521 * to a single buffer. 1522 */ 1523 printf("%s: Tx packet consumes too many DMA segments, " 1524 "dropping...\n", device_xname(sc->sc_dev)); 1525 IFQ_DEQUEUE(&ifp->if_snd, m0); 1526 m_freem(m0); 1527 continue; 1528 } else if (error != 0) { 1529 /* 1530 * Short on resources, just stop for now. 1531 */ 1532 break; 1533 } 1534 1535 /* 1536 * Ensure we have enough descriptors free to describe 1537 * the packet. Note, we always reserve one descriptor 1538 * at the end of the ring as a termination point, to 1539 * prevent wrap-around. 1540 */ 1541 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1542 /* 1543 * Not enough free descriptors to transmit this 1544 * packet. We haven't committed anything yet, 1545 * so just unload the DMA map, put the packet 1546 * back on the queue, and punt. Notify the upper 1547 * layer that there are not more slots left. 1548 * 1549 * XXX We could allocate an mbuf and copy, but 1550 * XXX is it worth it? 1551 */ 1552 ifp->if_flags |= IFF_OACTIVE; 1553 bus_dmamap_unload(sc->sc_dmat, dmamap); 1554 if (m != NULL) 1555 m_freem(m); 1556 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1557 break; 1558 } 1559 1560 IFQ_DEQUEUE(&ifp->if_snd, m0); 1561 if (m != NULL) { 1562 m_freem(m0); 1563 m0 = m; 1564 } 1565 1566 /* 1567 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1568 */ 1569 1570 /* Sync the DMA map. */ 1571 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1572 BUS_DMASYNC_PREWRITE); 1573 1574 /* 1575 * Initialize the transmit descriptors. 1576 */ 1577 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1578 seg < dmamap->dm_nsegs; 1579 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1580 /* 1581 * If this is the first descriptor we're 1582 * enqueueing, don't set the OWN bit just 1583 * yet. That could cause a race condition. 1584 * We'll do it below. 1585 */ 1586 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1587 htole32(dmamap->dm_segs[seg].ds_addr); 1588 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1589 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) 1590 | CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1591 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1592 lasttx = nexttx; 1593 } 1594 1595 /* Clear the MORE bit on the last segment. */ 1596 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1597 htole32(~CMDSTS_MORE); 1598 1599 /* 1600 * If we're in the interrupt delay window, delay the 1601 * interrupt. 1602 */ 1603 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1604 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1605 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1606 htole32(CMDSTS_INTR); 1607 sc->sc_txwin = 0; 1608 } 1609 1610 if (sc->sc_gigabit) 1611 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1612 1613 /* Sync the descriptors we're using. */ 1614 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1615 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1616 1617 /* 1618 * The entire packet is set up. Give the first descrptor 1619 * to the chip now. 1620 */ 1621 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1622 htole32(CMDSTS_OWN); 1623 sip_cdtxsync(sc, sc->sc_txnext, 1, 1624 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1625 1626 /* 1627 * Store a pointer to the packet so we can free it later, 1628 * and remember what txdirty will be once the packet is 1629 * done. 1630 */ 1631 txs->txs_mbuf = m0; 1632 txs->txs_firstdesc = sc->sc_txnext; 1633 txs->txs_lastdesc = lasttx; 1634 1635 /* Advance the tx pointer. */ 1636 sc->sc_txfree -= dmamap->dm_nsegs; 1637 sc->sc_txnext = nexttx; 1638 1639 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1640 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1641 1642 /* Pass the packet to any BPF listeners. */ 1643 bpf_mtap(ifp, m0, BPF_D_OUT); 1644 } 1645 1646 if (txs == NULL || sc->sc_txfree == 0) { 1647 /* No more slots left; notify upper layer. */ 1648 ifp->if_flags |= IFF_OACTIVE; 1649 } 1650 1651 if (sc->sc_txfree != ofree) { 1652 /* 1653 * Start the transmit process. Note, the manual says 1654 * that if there are no pending transmissions in the 1655 * chip's internal queue (indicated by TXE being clear), 1656 * then the driver software must set the TXDP to the 1657 * first descriptor to be transmitted. However, if we 1658 * do this, it causes serious performance degredation on 1659 * the DP83820 under load, not setting TXDP doesn't seem 1660 * to adversely affect the SiS 900 or DP83815. 1661 * 1662 * Well, I guess it wouldn't be the first time a manual 1663 * has lied -- and they could be speaking of the NULL- 1664 * terminated descriptor list case, rather than OWN- 1665 * terminated rings. 1666 */ 1667 #if 0 1668 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1669 CR_TXE) == 0) { 1670 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1671 SIP_CDTXADDR(sc, firsttx)); 1672 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1673 } 1674 #else 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1676 #endif 1677 1678 /* Set a watchdog timer in case the chip flakes out. */ 1679 /* Gigabit autonegotiation takes 5 seconds. */ 1680 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1681 } 1682 } 1683 1684 /* 1685 * sip_watchdog: [ifnet interface function] 1686 * 1687 * Watchdog timer handler. 1688 */ 1689 static void 1690 sipcom_watchdog(struct ifnet *ifp) 1691 { 1692 struct sip_softc *sc = ifp->if_softc; 1693 1694 /* 1695 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1696 * If we get a timeout, try and sweep up transmit descriptors. 1697 * If we manage to sweep them all up, ignore the lack of 1698 * interrupt. 1699 */ 1700 sipcom_txintr(sc); 1701 1702 if (sc->sc_txfree != sc->sc_ntxdesc) { 1703 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1704 ifp->if_oerrors++; 1705 1706 /* Reset the interface. */ 1707 (void) sipcom_init(ifp); 1708 } else if (ifp->if_flags & IFF_DEBUG) 1709 printf("%s: recovered from device timeout\n", 1710 device_xname(sc->sc_dev)); 1711 1712 /* Try to get more packets going. */ 1713 sipcom_start(ifp); 1714 } 1715 1716 /* If the interface is up and running, only modify the receive 1717 * filter when setting promiscuous or debug mode. Otherwise fall 1718 * through to ether_ioctl, which will reset the chip. 1719 */ 1720 static int 1721 sip_ifflags_cb(struct ethercom *ec) 1722 { 1723 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1724 == (sc)->sc_ethercom.ec_capenable) \ 1725 && ((sc)->sc_prev.is_vlan == \ 1726 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1727 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1728 struct ifnet *ifp = &ec->ec_if; 1729 struct sip_softc *sc = ifp->if_softc; 1730 int change = ifp->if_flags ^ sc->sc_if_flags; 1731 1732 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1733 !COMPARE_IC(sc, ifp)) 1734 return ENETRESET; 1735 /* Set up the receive filter. */ 1736 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1737 return 0; 1738 } 1739 1740 /* 1741 * sip_ioctl: [ifnet interface function] 1742 * 1743 * Handle control requests from the operator. 1744 */ 1745 static int 1746 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1747 { 1748 struct sip_softc *sc = ifp->if_softc; 1749 struct ifreq *ifr = (struct ifreq *)data; 1750 int s, error; 1751 1752 s = splnet(); 1753 1754 switch (cmd) { 1755 case SIOCSIFMEDIA: 1756 /* Flow control requires full-duplex mode. */ 1757 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1758 (ifr->ifr_media & IFM_FDX) == 0) 1759 ifr->ifr_media &= ~IFM_ETH_FMASK; 1760 1761 /* XXX */ 1762 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1763 ifr->ifr_media &= ~IFM_ETH_FMASK; 1764 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1765 if (sc->sc_gigabit && 1766 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1767 /* We can do both TXPAUSE and RXPAUSE. */ 1768 ifr->ifr_media |= 1769 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1770 } else if (ifr->ifr_media & IFM_FLOW) { 1771 /* 1772 * Both TXPAUSE and RXPAUSE must be set. 1773 * (SiS900 and DP83815 don't have PAUSE_ASYM 1774 * feature.) 1775 * 1776 * XXX Can SiS900 and DP83815 send PAUSE? 1777 */ 1778 ifr->ifr_media |= 1779 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1780 } 1781 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1782 } 1783 /*FALLTHROUGH*/ 1784 default: 1785 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1786 break; 1787 1788 error = 0; 1789 1790 if (cmd == SIOCSIFCAP) 1791 error = (*ifp->if_init)(ifp); 1792 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1793 ; 1794 else if (ifp->if_flags & IFF_RUNNING) { 1795 /* 1796 * Multicast list has changed; set the hardware filter 1797 * accordingly. 1798 */ 1799 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1800 } 1801 break; 1802 } 1803 1804 /* Try to get more packets going. */ 1805 sipcom_start(ifp); 1806 1807 sc->sc_if_flags = ifp->if_flags; 1808 splx(s); 1809 return error; 1810 } 1811 1812 /* 1813 * sip_intr: 1814 * 1815 * Interrupt service routine. 1816 */ 1817 static int 1818 sipcom_intr(void *arg) 1819 { 1820 struct sip_softc *sc = arg; 1821 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1822 uint32_t isr; 1823 int handled = 0; 1824 1825 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1826 return 0; 1827 1828 /* Disable interrupts. */ 1829 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1830 1831 for (;;) { 1832 /* Reading clears interrupt. */ 1833 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1834 if ((isr & sc->sc_imr) == 0) 1835 break; 1836 1837 rnd_add_uint32(&sc->rnd_source, isr); 1838 1839 handled = 1; 1840 1841 if ((ifp->if_flags & IFF_RUNNING) == 0) 1842 break; 1843 1844 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1845 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1846 1847 /* Grab any new packets. */ 1848 (*sc->sc_rxintr)(sc); 1849 1850 if (isr & ISR_RXORN) { 1851 printf("%s: receive FIFO overrun\n", 1852 device_xname(sc->sc_dev)); 1853 1854 /* XXX adjust rx_drain_thresh? */ 1855 } 1856 1857 if (isr & ISR_RXIDLE) { 1858 printf("%s: receive ring overrun\n", 1859 device_xname(sc->sc_dev)); 1860 1861 /* Get the receive process going again. */ 1862 bus_space_write_4(sc->sc_st, sc->sc_sh, 1863 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1864 bus_space_write_4(sc->sc_st, sc->sc_sh, 1865 SIP_CR, CR_RXE); 1866 } 1867 } 1868 1869 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1870 #ifdef SIP_EVENT_COUNTERS 1871 if (isr & ISR_TXDESC) 1872 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1873 else if (isr & ISR_TXIDLE) 1874 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1875 #endif 1876 1877 /* Sweep up transmit descriptors. */ 1878 sipcom_txintr(sc); 1879 1880 if (isr & ISR_TXURN) { 1881 uint32_t thresh; 1882 int txfifo_size = (sc->sc_gigabit) 1883 ? DP83820_SIP_TXFIFO_SIZE 1884 : OTHER_SIP_TXFIFO_SIZE; 1885 1886 printf("%s: transmit FIFO underrun", 1887 device_xname(sc->sc_dev)); 1888 thresh = sc->sc_tx_drain_thresh + 1; 1889 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1890 && (thresh * 32) <= (txfifo_size - 1891 (sc->sc_tx_fill_thresh * 32))) { 1892 printf("; increasing Tx drain " 1893 "threshold to %u bytes\n", 1894 thresh * 32); 1895 sc->sc_tx_drain_thresh = thresh; 1896 (void) sipcom_init(ifp); 1897 } else { 1898 (void) sipcom_init(ifp); 1899 printf("\n"); 1900 } 1901 } 1902 } 1903 1904 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1905 if (isr & ISR_PAUSE_ST) { 1906 sc->sc_paused = 1; 1907 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1908 ifp->if_flags |= IFF_OACTIVE; 1909 } 1910 if (isr & ISR_PAUSE_END) { 1911 sc->sc_paused = 0; 1912 ifp->if_flags &= ~IFF_OACTIVE; 1913 } 1914 } 1915 1916 if (isr & ISR_HIBERR) { 1917 int want_init = 0; 1918 1919 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1920 1921 #define PRINTERR(bit, str) \ 1922 do { \ 1923 if ((isr & (bit)) != 0) { \ 1924 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1925 printf("%s: %s\n", \ 1926 device_xname(sc->sc_dev), str); \ 1927 want_init = 1; \ 1928 } \ 1929 } while (/*CONSTCOND*/0) 1930 1931 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1932 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1933 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1934 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1935 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1936 /* 1937 * Ignore: 1938 * Tx reset complete 1939 * Rx reset complete 1940 */ 1941 if (want_init) 1942 (void) sipcom_init(ifp); 1943 #undef PRINTERR 1944 } 1945 } 1946 1947 /* Re-enable interrupts. */ 1948 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1949 1950 /* Try to get more packets going. */ 1951 if_schedule_deferred_start(ifp); 1952 1953 return handled; 1954 } 1955 1956 /* 1957 * sip_txintr: 1958 * 1959 * Helper; handle transmit interrupts. 1960 */ 1961 static void 1962 sipcom_txintr(struct sip_softc *sc) 1963 { 1964 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1965 struct sip_txsoft *txs; 1966 uint32_t cmdsts; 1967 1968 if (sc->sc_paused == 0) 1969 ifp->if_flags &= ~IFF_OACTIVE; 1970 1971 /* 1972 * Go through our Tx list and free mbufs for those 1973 * frames which have been transmitted. 1974 */ 1975 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1976 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1977 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1978 1979 cmdsts = le32toh(*sipd_cmdsts(sc, 1980 &sc->sc_txdescs[txs->txs_lastdesc])); 1981 if (cmdsts & CMDSTS_OWN) 1982 break; 1983 1984 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1985 1986 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1987 1988 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1989 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1990 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1991 m_freem(txs->txs_mbuf); 1992 txs->txs_mbuf = NULL; 1993 1994 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1995 1996 /* Check for errors and collisions. */ 1997 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 1998 CMDSTS_Tx_EC)) { 1999 ifp->if_oerrors++; 2000 if (cmdsts & CMDSTS_Tx_EC) 2001 ifp->if_collisions += 16; 2002 if (ifp->if_flags & IFF_DEBUG) { 2003 if (cmdsts & CMDSTS_Tx_ED) 2004 printf("%s: excessive deferral\n", 2005 device_xname(sc->sc_dev)); 2006 if (cmdsts & CMDSTS_Tx_EC) 2007 printf("%s: excessive collisions\n", 2008 device_xname(sc->sc_dev)); 2009 } 2010 } else { 2011 /* Packet was transmitted successfully. */ 2012 ifp->if_opackets++; 2013 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2014 } 2015 } 2016 2017 /* 2018 * If there are no more pending transmissions, cancel the watchdog 2019 * timer. 2020 */ 2021 if (txs == NULL) { 2022 ifp->if_timer = 0; 2023 sc->sc_txwin = 0; 2024 } 2025 } 2026 2027 /* 2028 * gsip_rxintr: 2029 * 2030 * Helper; handle receive interrupts on gigabit parts. 2031 */ 2032 static void 2033 gsip_rxintr(struct sip_softc *sc) 2034 { 2035 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2036 struct sip_rxsoft *rxs; 2037 struct mbuf *m; 2038 uint32_t cmdsts, extsts; 2039 int i, len; 2040 2041 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2042 rxs = &sc->sc_rxsoft[i]; 2043 2044 sip_cdrxsync(sc, i, 2045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2046 2047 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2048 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2049 len = CMDSTS_SIZE(sc, cmdsts); 2050 2051 /* 2052 * NOTE: OWN is set if owned by _consumer_. We're the 2053 * consumer of the receive ring, so if the bit is clear, 2054 * we have processed all of the packets. 2055 */ 2056 if ((cmdsts & CMDSTS_OWN) == 0) { 2057 /* 2058 * We have processed all of the receive buffers. 2059 */ 2060 break; 2061 } 2062 2063 if (__predict_false(sc->sc_rxdiscard)) { 2064 sip_init_rxdesc(sc, i); 2065 if ((cmdsts & CMDSTS_MORE) == 0) { 2066 /* Reset our state. */ 2067 sc->sc_rxdiscard = 0; 2068 } 2069 continue; 2070 } 2071 2072 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2073 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2074 2075 m = rxs->rxs_mbuf; 2076 2077 /* 2078 * Add a new receive buffer to the ring. 2079 */ 2080 if (sipcom_add_rxbuf(sc, i) != 0) { 2081 /* 2082 * Failed, throw away what we've done so 2083 * far, and discard the rest of the packet. 2084 */ 2085 ifp->if_ierrors++; 2086 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2087 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2088 sip_init_rxdesc(sc, i); 2089 if (cmdsts & CMDSTS_MORE) 2090 sc->sc_rxdiscard = 1; 2091 if (sc->sc_rxhead != NULL) 2092 m_freem(sc->sc_rxhead); 2093 sip_rxchain_reset(sc); 2094 continue; 2095 } 2096 2097 sip_rxchain_link(sc, m); 2098 2099 m->m_len = len; 2100 2101 /* 2102 * If this is not the end of the packet, keep 2103 * looking. 2104 */ 2105 if (cmdsts & CMDSTS_MORE) { 2106 sc->sc_rxlen += len; 2107 continue; 2108 } 2109 2110 /* 2111 * Okay, we have the entire packet now. The chip includes 2112 * the FCS, so we need to trim it. 2113 */ 2114 m->m_len -= ETHER_CRC_LEN; 2115 2116 *sc->sc_rxtailp = NULL; 2117 len = m->m_len + sc->sc_rxlen; 2118 m = sc->sc_rxhead; 2119 2120 sip_rxchain_reset(sc); 2121 2122 /* If an error occurred, update stats and drop the packet. */ 2123 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2124 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2125 ifp->if_ierrors++; 2126 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2127 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2128 /* Receive overrun handled elsewhere. */ 2129 printf("%s: receive descriptor error\n", 2130 device_xname(sc->sc_dev)); 2131 } 2132 #define PRINTERR(bit, str) \ 2133 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2134 (cmdsts & (bit)) != 0) \ 2135 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2136 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2137 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2138 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2139 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2140 #undef PRINTERR 2141 m_freem(m); 2142 continue; 2143 } 2144 2145 /* 2146 * If the packet is small enough to fit in a 2147 * single header mbuf, allocate one and copy 2148 * the data into it. This greatly reduces 2149 * memory consumption when we receive lots 2150 * of small packets. 2151 */ 2152 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2153 struct mbuf *nm; 2154 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2155 if (nm == NULL) { 2156 ifp->if_ierrors++; 2157 m_freem(m); 2158 continue; 2159 } 2160 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2161 nm->m_data += 2; 2162 nm->m_pkthdr.len = nm->m_len = len; 2163 m_copydata(m, 0, len, mtod(nm, void *)); 2164 m_freem(m); 2165 m = nm; 2166 } 2167 #ifndef __NO_STRICT_ALIGNMENT 2168 else { 2169 /* 2170 * The DP83820's receive buffers must be 4-byte 2171 * aligned. But this means that the data after 2172 * the Ethernet header is misaligned. To compensate, 2173 * we have artificially shortened the buffer size 2174 * in the descriptor, and we do an overlapping copy 2175 * of the data two bytes further in (in the first 2176 * buffer of the chain only). 2177 */ 2178 memmove(mtod(m, char *) + 2, mtod(m, void *), 2179 m->m_len); 2180 m->m_data += 2; 2181 } 2182 #endif /* ! __NO_STRICT_ALIGNMENT */ 2183 2184 /* 2185 * If VLANs are enabled, VLAN packets have been unwrapped 2186 * for us. Associate the tag with the packet. 2187 */ 2188 2189 /* 2190 * Again, byte swapping is tricky. Hardware provided 2191 * the tag in the network byte order, but extsts was 2192 * passed through le32toh() in the meantime. On a 2193 * big-endian machine, we need to swap it again. On a 2194 * little-endian machine, we need to convert from the 2195 * network to host byte order. This means that we must 2196 * swap it in any case, so unconditional swap instead 2197 * of htons() is used. 2198 */ 2199 if ((extsts & EXTSTS_VPKT) != 0) { 2200 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2201 } 2202 2203 /* 2204 * Set the incoming checksum information for the 2205 * packet. 2206 */ 2207 if ((extsts & EXTSTS_IPPKT) != 0) { 2208 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2209 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2210 if (extsts & EXTSTS_Rx_IPERR) 2211 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2212 if (extsts & EXTSTS_TCPPKT) { 2213 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2214 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2215 if (extsts & EXTSTS_Rx_TCPERR) 2216 m->m_pkthdr.csum_flags |= 2217 M_CSUM_TCP_UDP_BAD; 2218 } else if (extsts & EXTSTS_UDPPKT) { 2219 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2220 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2221 if (extsts & EXTSTS_Rx_UDPERR) 2222 m->m_pkthdr.csum_flags |= 2223 M_CSUM_TCP_UDP_BAD; 2224 } 2225 } 2226 2227 m_set_rcvif(m, ifp); 2228 m->m_pkthdr.len = len; 2229 2230 /* Pass it on. */ 2231 if_percpuq_enqueue(ifp->if_percpuq, m); 2232 } 2233 2234 /* Update the receive pointer. */ 2235 sc->sc_rxptr = i; 2236 } 2237 2238 /* 2239 * sip_rxintr: 2240 * 2241 * Helper; handle receive interrupts on 10/100 parts. 2242 */ 2243 static void 2244 sip_rxintr(struct sip_softc *sc) 2245 { 2246 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2247 struct sip_rxsoft *rxs; 2248 struct mbuf *m; 2249 uint32_t cmdsts; 2250 int i, len; 2251 2252 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2253 rxs = &sc->sc_rxsoft[i]; 2254 2255 sip_cdrxsync(sc, i, 2256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2257 2258 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2259 2260 /* 2261 * NOTE: OWN is set if owned by _consumer_. We're the 2262 * consumer of the receive ring, so if the bit is clear, 2263 * we have processed all of the packets. 2264 */ 2265 if ((cmdsts & CMDSTS_OWN) == 0) { 2266 /* 2267 * We have processed all of the receive buffers. 2268 */ 2269 break; 2270 } 2271 2272 /* If any collisions were seen on the wire, count one. */ 2273 if (cmdsts & CMDSTS_Rx_COL) 2274 ifp->if_collisions++; 2275 2276 /* 2277 * If an error occurred, update stats, clear the status 2278 * word, and leave the packet buffer in place. It will 2279 * simply be reused the next time the ring comes around. 2280 */ 2281 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2282 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2283 ifp->if_ierrors++; 2284 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2285 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2286 /* Receive overrun handled elsewhere. */ 2287 printf("%s: receive descriptor error\n", 2288 device_xname(sc->sc_dev)); 2289 } 2290 #define PRINTERR(bit, str) \ 2291 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2292 (cmdsts & (bit)) != 0) \ 2293 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2294 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2295 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2296 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2297 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2298 #undef PRINTERR 2299 sip_init_rxdesc(sc, i); 2300 continue; 2301 } 2302 2303 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2304 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2305 2306 /* 2307 * No errors; receive the packet. Note, the SiS 900 2308 * includes the CRC with every packet. 2309 */ 2310 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2311 2312 #ifdef __NO_STRICT_ALIGNMENT 2313 /* 2314 * If the packet is small enough to fit in a 2315 * single header mbuf, allocate one and copy 2316 * the data into it. This greatly reduces 2317 * memory consumption when we receive lots 2318 * of small packets. 2319 * 2320 * Otherwise, we add a new buffer to the receive 2321 * chain. If this fails, we drop the packet and 2322 * recycle the old buffer. 2323 */ 2324 if (sip_copy_small != 0 && len <= MHLEN) { 2325 MGETHDR(m, M_DONTWAIT, MT_DATA); 2326 if (m == NULL) 2327 goto dropit; 2328 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2329 memcpy(mtod(m, void *), 2330 mtod(rxs->rxs_mbuf, void *), len); 2331 sip_init_rxdesc(sc, i); 2332 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2333 rxs->rxs_dmamap->dm_mapsize, 2334 BUS_DMASYNC_PREREAD); 2335 } else { 2336 m = rxs->rxs_mbuf; 2337 if (sipcom_add_rxbuf(sc, i) != 0) { 2338 dropit: 2339 ifp->if_ierrors++; 2340 sip_init_rxdesc(sc, i); 2341 bus_dmamap_sync(sc->sc_dmat, 2342 rxs->rxs_dmamap, 0, 2343 rxs->rxs_dmamap->dm_mapsize, 2344 BUS_DMASYNC_PREREAD); 2345 continue; 2346 } 2347 } 2348 #else 2349 /* 2350 * The SiS 900's receive buffers must be 4-byte aligned. 2351 * But this means that the data after the Ethernet header 2352 * is misaligned. We must allocate a new buffer and 2353 * copy the data, shifted forward 2 bytes. 2354 */ 2355 MGETHDR(m, M_DONTWAIT, MT_DATA); 2356 if (m == NULL) { 2357 dropit: 2358 ifp->if_ierrors++; 2359 sip_init_rxdesc(sc, i); 2360 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2361 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2362 continue; 2363 } 2364 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2365 if (len > (MHLEN - 2)) { 2366 MCLGET(m, M_DONTWAIT); 2367 if ((m->m_flags & M_EXT) == 0) { 2368 m_freem(m); 2369 goto dropit; 2370 } 2371 } 2372 m->m_data += 2; 2373 2374 /* 2375 * Note that we use clusters for incoming frames, so the 2376 * buffer is virtually contiguous. 2377 */ 2378 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2379 2380 /* Allow the receive descriptor to continue using its mbuf. */ 2381 sip_init_rxdesc(sc, i); 2382 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2383 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2384 #endif /* __NO_STRICT_ALIGNMENT */ 2385 2386 m_set_rcvif(m, ifp); 2387 m->m_pkthdr.len = m->m_len = len; 2388 2389 /* Pass it on. */ 2390 if_percpuq_enqueue(ifp->if_percpuq, m); 2391 } 2392 2393 /* Update the receive pointer. */ 2394 sc->sc_rxptr = i; 2395 } 2396 2397 /* 2398 * sip_tick: 2399 * 2400 * One second timer, used to tick the MII. 2401 */ 2402 static void 2403 sipcom_tick(void *arg) 2404 { 2405 struct sip_softc *sc = arg; 2406 int s; 2407 2408 s = splnet(); 2409 #ifdef SIP_EVENT_COUNTERS 2410 if (sc->sc_gigabit) { 2411 /* Read PAUSE related counts from MIB registers. */ 2412 sc->sc_ev_rxpause.ev_count += 2413 bus_space_read_4(sc->sc_st, sc->sc_sh, 2414 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2415 sc->sc_ev_txpause.ev_count += 2416 bus_space_read_4(sc->sc_st, sc->sc_sh, 2417 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2418 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2419 } 2420 #endif /* SIP_EVENT_COUNTERS */ 2421 mii_tick(&sc->sc_mii); 2422 splx(s); 2423 2424 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2425 } 2426 2427 /* 2428 * sip_reset: 2429 * 2430 * Perform a soft reset on the SiS 900. 2431 */ 2432 static bool 2433 sipcom_reset(struct sip_softc *sc) 2434 { 2435 bus_space_tag_t st = sc->sc_st; 2436 bus_space_handle_t sh = sc->sc_sh; 2437 int i; 2438 2439 bus_space_write_4(st, sh, SIP_IER, 0); 2440 bus_space_write_4(st, sh, SIP_IMR, 0); 2441 bus_space_write_4(st, sh, SIP_RFCR, 0); 2442 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2443 2444 for (i = 0; i < SIP_TIMEOUT; i++) { 2445 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2446 break; 2447 delay(2); 2448 } 2449 2450 if (i == SIP_TIMEOUT) { 2451 printf("%s: reset failed to complete\n", 2452 device_xname(sc->sc_dev)); 2453 return false; 2454 } 2455 2456 delay(1000); 2457 2458 if (sc->sc_gigabit) { 2459 /* 2460 * Set the general purpose I/O bits. Do it here in case we 2461 * need to have GPIO set up to talk to the media interface. 2462 */ 2463 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2464 delay(1000); 2465 } 2466 return true; 2467 } 2468 2469 static void 2470 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2471 { 2472 uint32_t reg; 2473 bus_space_tag_t st = sc->sc_st; 2474 bus_space_handle_t sh = sc->sc_sh; 2475 /* 2476 * Initialize the VLAN/IP receive control register. 2477 * We enable checksum computation on all incoming 2478 * packets, and do not reject packets w/ bad checksums. 2479 */ 2480 reg = 0; 2481 if (capenable & 2482 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2483 reg |= VRCR_IPEN; 2484 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2485 reg |= VRCR_VTDEN | VRCR_VTREN; 2486 bus_space_write_4(st, sh, SIP_VRCR, reg); 2487 2488 /* 2489 * Initialize the VLAN/IP transmit control register. 2490 * We enable outgoing checksum computation on a 2491 * per-packet basis. 2492 */ 2493 reg = 0; 2494 if (capenable & 2495 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2496 reg |= VTCR_PPCHK; 2497 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2498 reg |= VTCR_VPPTI; 2499 bus_space_write_4(st, sh, SIP_VTCR, reg); 2500 2501 /* 2502 * If we're using VLANs, initialize the VLAN data register. 2503 * To understand why we bswap the VLAN Ethertype, see section 2504 * 4.2.36 of the DP83820 manual. 2505 */ 2506 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2507 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2508 } 2509 2510 /* 2511 * sip_init: [ ifnet interface function ] 2512 * 2513 * Initialize the interface. Must be called at splnet(). 2514 */ 2515 static int 2516 sipcom_init(struct ifnet *ifp) 2517 { 2518 struct sip_softc *sc = ifp->if_softc; 2519 bus_space_tag_t st = sc->sc_st; 2520 bus_space_handle_t sh = sc->sc_sh; 2521 struct sip_txsoft *txs; 2522 struct sip_rxsoft *rxs; 2523 struct sip_desc *sipd; 2524 int i, error = 0; 2525 2526 if (device_is_active(sc->sc_dev)) { 2527 /* 2528 * Cancel any pending I/O. 2529 */ 2530 sipcom_stop(ifp, 0); 2531 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2532 !device_is_active(sc->sc_dev)) 2533 return 0; 2534 2535 /* 2536 * Reset the chip to a known state. 2537 */ 2538 if (!sipcom_reset(sc)) 2539 return EBUSY; 2540 2541 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2542 /* 2543 * DP83815 manual, page 78: 2544 * 4.4 Recommended Registers Configuration 2545 * For optimum performance of the DP83815, version noted 2546 * as DP83815CVNG (SRR = 203h), the listed register 2547 * modifications must be followed in sequence... 2548 * 2549 * It's not clear if this should be 302h or 203h because that 2550 * chip name is listed as SRR 302h in the description of the 2551 * SRR register. However, my revision 302h DP83815 on the 2552 * Netgear FA311 purchased in 02/2001 needs these settings 2553 * to avoid tons of errors in AcceptPerfectMatch (non- 2554 * IFF_PROMISC) mode. I do not know if other revisions need 2555 * this set or not. [briggs -- 09 March 2001] 2556 * 2557 * Note that only the low-order 12 bits of 0xe4 are documented 2558 * and that this sets reserved bits in that register. 2559 */ 2560 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2561 2562 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2563 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2564 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2565 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2566 2567 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2568 } 2569 2570 /* 2571 * Initialize the transmit descriptor ring. 2572 */ 2573 for (i = 0; i < sc->sc_ntxdesc; i++) { 2574 sipd = &sc->sc_txdescs[i]; 2575 memset(sipd, 0, sizeof(struct sip_desc)); 2576 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2577 } 2578 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2580 sc->sc_txfree = sc->sc_ntxdesc; 2581 sc->sc_txnext = 0; 2582 sc->sc_txwin = 0; 2583 2584 /* 2585 * Initialize the transmit job descriptors. 2586 */ 2587 SIMPLEQ_INIT(&sc->sc_txfreeq); 2588 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2589 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2590 txs = &sc->sc_txsoft[i]; 2591 txs->txs_mbuf = NULL; 2592 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2593 } 2594 2595 /* 2596 * Initialize the receive descriptor and receive job 2597 * descriptor rings. 2598 */ 2599 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2600 rxs = &sc->sc_rxsoft[i]; 2601 if (rxs->rxs_mbuf == NULL) { 2602 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2603 printf("%s: unable to allocate or map rx " 2604 "buffer %d, error = %d\n", 2605 device_xname(sc->sc_dev), i, error); 2606 /* 2607 * XXX Should attempt to run with fewer receive 2608 * XXX buffers instead of just failing. 2609 */ 2610 sipcom_rxdrain(sc); 2611 goto out; 2612 } 2613 } else 2614 sip_init_rxdesc(sc, i); 2615 } 2616 sc->sc_rxptr = 0; 2617 sc->sc_rxdiscard = 0; 2618 sip_rxchain_reset(sc); 2619 2620 /* 2621 * Set the configuration register; it's already initialized 2622 * in sip_attach(). 2623 */ 2624 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2625 2626 /* 2627 * Initialize the prototype TXCFG register. 2628 */ 2629 if (sc->sc_gigabit) { 2630 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2631 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2632 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2633 SIP_SIS900_REV(sc, SIS_REV_960) || 2634 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2635 (sc->sc_cfg & CFG_EDBMASTEN)) { 2636 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2637 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2638 } else { 2639 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2640 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2641 } 2642 2643 sc->sc_txcfg |= TXCFG_ATP | 2644 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2645 sc->sc_tx_drain_thresh; 2646 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2647 2648 /* 2649 * Initialize the receive drain threshold if we have never 2650 * done so. 2651 */ 2652 if (sc->sc_rx_drain_thresh == 0) { 2653 /* 2654 * XXX This value should be tuned. This is set to the 2655 * maximum of 248 bytes, and we may be able to improve 2656 * performance by decreasing it (although we should never 2657 * set this value lower than 2; 14 bytes are required to 2658 * filter the packet). 2659 */ 2660 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2661 } 2662 2663 /* 2664 * Initialize the prototype RXCFG register. 2665 */ 2666 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2667 /* 2668 * Accept long packets (including FCS) so we can handle 2669 * 802.1q-tagged frames and jumbo frames properly. 2670 */ 2671 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2672 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2673 sc->sc_rxcfg |= RXCFG_ALP; 2674 2675 /* 2676 * Checksum offloading is disabled if the user selects an MTU 2677 * larger than 8109. (FreeBSD says 8152, but there is emperical 2678 * evidence that >8109 does not work on some boards, such as the 2679 * Planex GN-1000TE). 2680 */ 2681 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2682 (ifp->if_capenable & 2683 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2684 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2685 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2686 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2687 "disabled.\n", device_xname(sc->sc_dev)); 2688 ifp->if_capenable &= 2689 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2690 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2691 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2692 ifp->if_csum_flags_tx = 0; 2693 ifp->if_csum_flags_rx = 0; 2694 } 2695 2696 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2697 2698 if (sc->sc_gigabit) 2699 sipcom_dp83820_init(sc, ifp->if_capenable); 2700 2701 /* 2702 * Give the transmit and receive rings to the chip. 2703 */ 2704 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2705 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2706 2707 /* 2708 * Initialize the interrupt mask. 2709 */ 2710 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2711 sc->sc_bits.b_isr_sserr | 2712 sc->sc_bits.b_isr_rmabt | 2713 sc->sc_bits.b_isr_rtabt | 2714 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2715 ISR_RXIDLE | ISR_RXDESC; 2716 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2717 2718 /* Set up the receive filter. */ 2719 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2720 2721 /* 2722 * Tune sc_rx_flow_thresh. 2723 * XXX "More than 8KB" is too short for jumbo frames. 2724 * XXX TODO: Threshold value should be user-settable. 2725 */ 2726 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2727 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2728 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2729 2730 /* 2731 * Set the current media. Do this after initializing the prototype 2732 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2733 * control. 2734 */ 2735 if ((error = ether_mediachange(ifp)) != 0) 2736 goto out; 2737 2738 /* 2739 * Set the interrupt hold-off timer to 100us. 2740 */ 2741 if (sc->sc_gigabit) 2742 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2743 2744 /* 2745 * Enable interrupts. 2746 */ 2747 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2748 2749 /* 2750 * Start the transmit and receive processes. 2751 */ 2752 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2753 2754 /* 2755 * Start the one second MII clock. 2756 */ 2757 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2758 2759 /* 2760 * ...all done! 2761 */ 2762 ifp->if_flags |= IFF_RUNNING; 2763 ifp->if_flags &= ~IFF_OACTIVE; 2764 sc->sc_if_flags = ifp->if_flags; 2765 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2766 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2767 sc->sc_prev.if_capenable = ifp->if_capenable; 2768 2769 out: 2770 if (error) 2771 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2772 return error; 2773 } 2774 2775 /* 2776 * sip_drain: 2777 * 2778 * Drain the receive queue. 2779 */ 2780 static void 2781 sipcom_rxdrain(struct sip_softc *sc) 2782 { 2783 struct sip_rxsoft *rxs; 2784 int i; 2785 2786 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2787 rxs = &sc->sc_rxsoft[i]; 2788 if (rxs->rxs_mbuf != NULL) { 2789 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2790 m_freem(rxs->rxs_mbuf); 2791 rxs->rxs_mbuf = NULL; 2792 } 2793 } 2794 } 2795 2796 /* 2797 * sip_stop: [ ifnet interface function ] 2798 * 2799 * Stop transmission on the interface. 2800 */ 2801 static void 2802 sipcom_stop(struct ifnet *ifp, int disable) 2803 { 2804 struct sip_softc *sc = ifp->if_softc; 2805 bus_space_tag_t st = sc->sc_st; 2806 bus_space_handle_t sh = sc->sc_sh; 2807 struct sip_txsoft *txs; 2808 uint32_t cmdsts = 0; /* DEBUG */ 2809 2810 /* 2811 * Stop the one second clock. 2812 */ 2813 callout_stop(&sc->sc_tick_ch); 2814 2815 /* Down the MII. */ 2816 mii_down(&sc->sc_mii); 2817 2818 if (device_is_active(sc->sc_dev)) { 2819 /* 2820 * Disable interrupts. 2821 */ 2822 bus_space_write_4(st, sh, SIP_IER, 0); 2823 2824 /* 2825 * Stop receiver and transmitter. 2826 */ 2827 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2828 } 2829 2830 /* 2831 * Release any queued transmit buffers. 2832 */ 2833 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2834 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2835 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2836 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2837 CMDSTS_INTR) == 0) 2838 printf("%s: sip_stop: last descriptor does not " 2839 "have INTR bit set\n", device_xname(sc->sc_dev)); 2840 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2841 #ifdef DIAGNOSTIC 2842 if (txs->txs_mbuf == NULL) { 2843 printf("%s: dirty txsoft with no mbuf chain\n", 2844 device_xname(sc->sc_dev)); 2845 panic("sip_stop"); 2846 } 2847 #endif 2848 cmdsts |= /* DEBUG */ 2849 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2850 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2851 m_freem(txs->txs_mbuf); 2852 txs->txs_mbuf = NULL; 2853 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2854 } 2855 2856 /* 2857 * Mark the interface down and cancel the watchdog timer. 2858 */ 2859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2860 ifp->if_timer = 0; 2861 2862 if (disable) 2863 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2864 2865 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2866 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2867 printf("%s: sip_stop: no INTR bits set in dirty tx " 2868 "descriptors\n", device_xname(sc->sc_dev)); 2869 } 2870 2871 /* 2872 * sip_read_eeprom: 2873 * 2874 * Read data from the serial EEPROM. 2875 */ 2876 static void 2877 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2878 uint16_t *data) 2879 { 2880 bus_space_tag_t st = sc->sc_st; 2881 bus_space_handle_t sh = sc->sc_sh; 2882 uint16_t reg; 2883 int i, x; 2884 2885 for (i = 0; i < wordcnt; i++) { 2886 /* Send CHIP SELECT. */ 2887 reg = EROMAR_EECS; 2888 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2889 2890 /* Shift in the READ opcode. */ 2891 for (x = 3; x > 0; x--) { 2892 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2893 reg |= EROMAR_EEDI; 2894 else 2895 reg &= ~EROMAR_EEDI; 2896 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2897 bus_space_write_4(st, sh, SIP_EROMAR, 2898 reg | EROMAR_EESK); 2899 delay(4); 2900 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2901 delay(4); 2902 } 2903 2904 /* Shift in address. */ 2905 for (x = 6; x > 0; x--) { 2906 if ((word + i) & (1 << (x - 1))) 2907 reg |= EROMAR_EEDI; 2908 else 2909 reg &= ~EROMAR_EEDI; 2910 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2911 bus_space_write_4(st, sh, SIP_EROMAR, 2912 reg | EROMAR_EESK); 2913 delay(4); 2914 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2915 delay(4); 2916 } 2917 2918 /* Shift out data. */ 2919 reg = EROMAR_EECS; 2920 data[i] = 0; 2921 for (x = 16; x > 0; x--) { 2922 bus_space_write_4(st, sh, SIP_EROMAR, 2923 reg | EROMAR_EESK); 2924 delay(4); 2925 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2926 data[i] |= (1 << (x - 1)); 2927 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2928 delay(4); 2929 } 2930 2931 /* Clear CHIP SELECT. */ 2932 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2933 delay(4); 2934 } 2935 } 2936 2937 /* 2938 * sipcom_add_rxbuf: 2939 * 2940 * Add a receive buffer to the indicated descriptor. 2941 */ 2942 static int 2943 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2944 { 2945 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2946 struct mbuf *m; 2947 int error; 2948 2949 MGETHDR(m, M_DONTWAIT, MT_DATA); 2950 if (m == NULL) 2951 return ENOBUFS; 2952 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2953 2954 MCLGET(m, M_DONTWAIT); 2955 if ((m->m_flags & M_EXT) == 0) { 2956 m_freem(m); 2957 return ENOBUFS; 2958 } 2959 2960 /* XXX I don't believe this is necessary. --dyoung */ 2961 if (sc->sc_gigabit) 2962 m->m_len = sc->sc_parm->p_rxbuf_len; 2963 2964 if (rxs->rxs_mbuf != NULL) 2965 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2966 2967 rxs->rxs_mbuf = m; 2968 2969 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2970 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2971 BUS_DMA_READ | BUS_DMA_NOWAIT); 2972 if (error) { 2973 printf("%s: can't load rx DMA map %d, error = %d\n", 2974 device_xname(sc->sc_dev), idx, error); 2975 panic("%s", __func__); /* XXX */ 2976 } 2977 2978 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2979 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2980 2981 sip_init_rxdesc(sc, idx); 2982 2983 return 0; 2984 } 2985 2986 /* 2987 * sip_sis900_set_filter: 2988 * 2989 * Set up the receive filter. 2990 */ 2991 static void 2992 sipcom_sis900_set_filter(struct sip_softc *sc) 2993 { 2994 bus_space_tag_t st = sc->sc_st; 2995 bus_space_handle_t sh = sc->sc_sh; 2996 struct ethercom *ec = &sc->sc_ethercom; 2997 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2998 struct ether_multi *enm; 2999 const uint8_t *cp; 3000 struct ether_multistep step; 3001 uint32_t crc, mchash[16]; 3002 3003 /* 3004 * Initialize the prototype RFCR. 3005 */ 3006 sc->sc_rfcr = RFCR_RFEN; 3007 if (ifp->if_flags & IFF_BROADCAST) 3008 sc->sc_rfcr |= RFCR_AAB; 3009 if (ifp->if_flags & IFF_PROMISC) { 3010 sc->sc_rfcr |= RFCR_AAP; 3011 goto allmulti; 3012 } 3013 3014 /* 3015 * Set up the multicast address filter by passing all multicast 3016 * addresses through a CRC generator, and then using the high-order 3017 * 6 bits as an index into the 128 bit multicast hash table (only 3018 * the lower 16 bits of each 32 bit multicast hash register are 3019 * valid). The high order bits select the register, while the 3020 * rest of the bits select the bit within the register. 3021 */ 3022 3023 memset(mchash, 0, sizeof(mchash)); 3024 3025 /* 3026 * SiS900 (at least SiS963) requires us to register the address of 3027 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3028 */ 3029 crc = 0x0ed423f9; 3030 3031 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3032 SIP_SIS900_REV(sc, SIS_REV_960) || 3033 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3034 /* Just want the 8 most significant bits. */ 3035 crc >>= 24; 3036 } else { 3037 /* Just want the 7 most significant bits. */ 3038 crc >>= 25; 3039 } 3040 3041 /* Set the corresponding bit in the hash table. */ 3042 mchash[crc >> 4] |= 1 << (crc & 0xf); 3043 3044 ETHER_LOCK(ec); 3045 ETHER_FIRST_MULTI(step, ec, enm); 3046 while (enm != NULL) { 3047 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3048 /* 3049 * We must listen to a range of multicast addresses. 3050 * For now, just accept all multicasts, rather than 3051 * trying to set only those filter bits needed to match 3052 * the range. (At this time, the only use of address 3053 * ranges is for IP multicast routing, for which the 3054 * range is big enough to require all bits set.) 3055 */ 3056 ETHER_UNLOCK(ec); 3057 goto allmulti; 3058 } 3059 3060 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3061 3062 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3063 SIP_SIS900_REV(sc, SIS_REV_960) || 3064 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3065 /* Just want the 8 most significant bits. */ 3066 crc >>= 24; 3067 } else { 3068 /* Just want the 7 most significant bits. */ 3069 crc >>= 25; 3070 } 3071 3072 /* Set the corresponding bit in the hash table. */ 3073 mchash[crc >> 4] |= 1 << (crc & 0xf); 3074 3075 ETHER_NEXT_MULTI(step, enm); 3076 } 3077 ETHER_UNLOCK(ec); 3078 3079 ifp->if_flags &= ~IFF_ALLMULTI; 3080 goto setit; 3081 3082 allmulti: 3083 ifp->if_flags |= IFF_ALLMULTI; 3084 sc->sc_rfcr |= RFCR_AAM; 3085 3086 setit: 3087 #define FILTER_EMIT(addr, data) \ 3088 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3089 delay(1); \ 3090 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3091 delay(1) 3092 3093 /* 3094 * Disable receive filter, and program the node address. 3095 */ 3096 cp = CLLADDR(ifp->if_sadl); 3097 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3098 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3099 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3100 3101 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3102 /* 3103 * Program the multicast hash table. 3104 */ 3105 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3106 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3107 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3108 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3109 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3110 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3111 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3112 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3113 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3114 SIP_SIS900_REV(sc, SIS_REV_960) || 3115 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3116 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3117 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3118 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3119 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3120 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3121 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3122 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3123 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3124 } 3125 } 3126 #undef FILTER_EMIT 3127 3128 /* 3129 * Re-enable the receiver filter. 3130 */ 3131 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3132 } 3133 3134 /* 3135 * sip_dp83815_set_filter: 3136 * 3137 * Set up the receive filter. 3138 */ 3139 static void 3140 sipcom_dp83815_set_filter(struct sip_softc *sc) 3141 { 3142 bus_space_tag_t st = sc->sc_st; 3143 bus_space_handle_t sh = sc->sc_sh; 3144 struct ethercom *ec = &sc->sc_ethercom; 3145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3146 struct ether_multi *enm; 3147 const uint8_t *cp; 3148 struct ether_multistep step; 3149 uint32_t crc, hash, slot, bit; 3150 #define MCHASH_NWORDS_83820 128 3151 #define MCHASH_NWORDS_83815 32 3152 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3153 uint16_t mchash[MCHASH_NWORDS]; 3154 int i; 3155 3156 /* 3157 * Initialize the prototype RFCR. 3158 * Enable the receive filter, and accept on 3159 * Perfect (destination address) Match 3160 * If IFF_BROADCAST, also accept all broadcast packets. 3161 * If IFF_PROMISC, accept all unicast packets (and later, set 3162 * IFF_ALLMULTI and accept all multicast, too). 3163 */ 3164 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3165 if (ifp->if_flags & IFF_BROADCAST) 3166 sc->sc_rfcr |= RFCR_AAB; 3167 if (ifp->if_flags & IFF_PROMISC) { 3168 sc->sc_rfcr |= RFCR_AAP; 3169 goto allmulti; 3170 } 3171 3172 /* 3173 * Set up the DP83820/DP83815 multicast address filter by 3174 * passing all multicast addresses through a CRC generator, 3175 * and then using the high-order 11/9 bits as an index into 3176 * the 2048/512 bit multicast hash table. The high-order 3177 * 7/5 bits select the slot, while the low-order 4 bits 3178 * select the bit within the slot. Note that only the low 3179 * 16-bits of each filter word are used, and there are 3180 * 128/32 filter words. 3181 */ 3182 3183 memset(mchash, 0, sizeof(mchash)); 3184 3185 ifp->if_flags &= ~IFF_ALLMULTI; 3186 ETHER_FIRST_MULTI(step, ec, enm); 3187 if (enm == NULL) 3188 goto setit; 3189 while (enm != NULL) { 3190 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3191 /* 3192 * We must listen to a range of multicast addresses. 3193 * For now, just accept all multicasts, rather than 3194 * trying to set only those filter bits needed to match 3195 * the range. (At this time, the only use of address 3196 * ranges is for IP multicast routing, for which the 3197 * range is big enough to require all bits set.) 3198 */ 3199 goto allmulti; 3200 } 3201 3202 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3203 3204 if (sc->sc_gigabit) { 3205 /* Just want the 11 most significant bits. */ 3206 hash = crc >> 21; 3207 } else { 3208 /* Just want the 9 most significant bits. */ 3209 hash = crc >> 23; 3210 } 3211 3212 slot = hash >> 4; 3213 bit = hash & 0xf; 3214 3215 /* Set the corresponding bit in the hash table. */ 3216 mchash[slot] |= 1 << bit; 3217 3218 ETHER_NEXT_MULTI(step, enm); 3219 } 3220 sc->sc_rfcr |= RFCR_MHEN; 3221 goto setit; 3222 3223 allmulti: 3224 ifp->if_flags |= IFF_ALLMULTI; 3225 sc->sc_rfcr |= RFCR_AAM; 3226 3227 setit: 3228 #define FILTER_EMIT(addr, data) \ 3229 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3230 delay(1); \ 3231 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3232 delay(1) 3233 3234 /* 3235 * Disable receive filter, and program the node address. 3236 */ 3237 cp = CLLADDR(ifp->if_sadl); 3238 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3239 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3240 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3241 3242 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3243 int nwords = 3244 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3245 /* 3246 * Program the multicast hash table. 3247 */ 3248 for (i = 0; i < nwords; i++) { 3249 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3250 } 3251 } 3252 #undef FILTER_EMIT 3253 #undef MCHASH_NWORDS 3254 #undef MCHASH_NWORDS_83815 3255 #undef MCHASH_NWORDS_83820 3256 3257 /* 3258 * Re-enable the receiver filter. 3259 */ 3260 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3261 } 3262 3263 /* 3264 * sip_dp83820_mii_readreg: [mii interface function] 3265 * 3266 * Read a PHY register on the MII of the DP83820. 3267 */ 3268 static int 3269 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3270 { 3271 struct sip_softc *sc = device_private(self); 3272 3273 if (sc->sc_cfg & CFG_TBI_EN) { 3274 bus_addr_t tbireg; 3275 3276 if (phy != 0) 3277 return -1; 3278 3279 switch (reg) { 3280 case MII_BMCR: tbireg = SIP_TBICR; break; 3281 case MII_BMSR: tbireg = SIP_TBISR; break; 3282 case MII_ANAR: tbireg = SIP_TANAR; break; 3283 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3284 case MII_ANER: tbireg = SIP_TANER; break; 3285 case MII_EXTSR: 3286 /* 3287 * Don't even bother reading the TESR register. 3288 * The manual documents that the device has 3289 * 1000baseX full/half capability, but the 3290 * register itself seems read back 0 on some 3291 * boards. Just hard-code the result. 3292 */ 3293 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3294 return 0; 3295 3296 default: 3297 return 0; 3298 } 3299 3300 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3301 if (tbireg == SIP_TBISR) { 3302 /* LINK and ACOMP are switched! */ 3303 int sr = *val; 3304 3305 *val = 0; 3306 if (sr & TBISR_MR_LINK_STATUS) 3307 *val |= BMSR_LINK; 3308 if (sr & TBISR_MR_AN_COMPLETE) 3309 *val |= BMSR_ACOMP; 3310 3311 /* 3312 * The manual claims this register reads back 0 3313 * on hard and soft reset. But we want to let 3314 * the gentbi driver know that we support auto- 3315 * negotiation, so hard-code this bit in the 3316 * result. 3317 */ 3318 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3319 } 3320 3321 return 0; 3322 } 3323 3324 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3325 val); 3326 } 3327 3328 /* 3329 * sip_dp83820_mii_writereg: [mii interface function] 3330 * 3331 * Write a PHY register on the MII of the DP83820. 3332 */ 3333 static int 3334 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3335 { 3336 struct sip_softc *sc = device_private(self); 3337 3338 if (sc->sc_cfg & CFG_TBI_EN) { 3339 bus_addr_t tbireg; 3340 3341 if (phy != 0) 3342 return -1; 3343 3344 switch (reg) { 3345 case MII_BMCR: tbireg = SIP_TBICR; break; 3346 case MII_ANAR: tbireg = SIP_TANAR; break; 3347 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3348 default: 3349 return 0; 3350 } 3351 3352 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3353 return 0; 3354 } 3355 3356 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3357 val); 3358 } 3359 3360 /* 3361 * sip_dp83820_mii_statchg: [mii interface function] 3362 * 3363 * Callback from MII layer when media changes. 3364 */ 3365 static void 3366 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3367 { 3368 struct sip_softc *sc = ifp->if_softc; 3369 struct mii_data *mii = &sc->sc_mii; 3370 uint32_t cfg, pcr; 3371 3372 /* 3373 * Get flow control negotiation result. 3374 */ 3375 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3376 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3377 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3378 mii->mii_media_active &= ~IFM_ETH_FMASK; 3379 } 3380 3381 /* 3382 * Update TXCFG for full-duplex operation. 3383 */ 3384 if ((mii->mii_media_active & IFM_FDX) != 0) 3385 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3386 else 3387 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3388 3389 /* 3390 * Update RXCFG for full-duplex or loopback. 3391 */ 3392 if ((mii->mii_media_active & IFM_FDX) != 0 || 3393 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3394 sc->sc_rxcfg |= RXCFG_ATX; 3395 else 3396 sc->sc_rxcfg &= ~RXCFG_ATX; 3397 3398 /* 3399 * Update CFG for MII/GMII. 3400 */ 3401 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3402 cfg = sc->sc_cfg | CFG_MODE_1000; 3403 else 3404 cfg = sc->sc_cfg; 3405 3406 /* 3407 * 802.3x flow control. 3408 */ 3409 pcr = 0; 3410 if (sc->sc_flowflags & IFM_FLOW) { 3411 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3412 pcr |= sc->sc_rx_flow_thresh; 3413 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3414 pcr |= PCR_PSEN | PCR_PS_MCAST; 3415 } 3416 3417 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3418 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3419 sc->sc_txcfg); 3420 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3421 sc->sc_rxcfg); 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3423 } 3424 3425 /* 3426 * sip_mii_bitbang_read: [mii bit-bang interface function] 3427 * 3428 * Read the MII serial port for the MII bit-bang module. 3429 */ 3430 static uint32_t 3431 sipcom_mii_bitbang_read(device_t self) 3432 { 3433 struct sip_softc *sc = device_private(self); 3434 3435 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3436 } 3437 3438 /* 3439 * sip_mii_bitbang_write: [mii big-bang interface function] 3440 * 3441 * Write the MII serial port for the MII bit-bang module. 3442 */ 3443 static void 3444 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3445 { 3446 struct sip_softc *sc = device_private(self); 3447 3448 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3449 } 3450 3451 /* 3452 * sip_sis900_mii_readreg: [mii interface function] 3453 * 3454 * Read a PHY register on the MII. 3455 */ 3456 static int 3457 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3458 { 3459 struct sip_softc *sc = device_private(self); 3460 uint32_t enphy; 3461 3462 /* 3463 * The PHY of recent SiS chipsets is accessed through bitbang 3464 * operations. 3465 */ 3466 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3467 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3468 phy, reg, val); 3469 3470 #ifndef SIS900_MII_RESTRICT 3471 /* 3472 * The SiS 900 has only an internal PHY on the MII. Only allow 3473 * MII address 0. 3474 */ 3475 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3476 return -1; 3477 #endif 3478 3479 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3480 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3481 ENPHY_RWCMD | ENPHY_ACCESS); 3482 do { 3483 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3484 } while (enphy & ENPHY_ACCESS); 3485 3486 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3487 return 0; 3488 } 3489 3490 /* 3491 * sip_sis900_mii_writereg: [mii interface function] 3492 * 3493 * Write a PHY register on the MII. 3494 */ 3495 static int 3496 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3497 { 3498 struct sip_softc *sc = device_private(self); 3499 uint32_t enphy; 3500 3501 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3502 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3503 phy, reg, val); 3504 } 3505 3506 #ifndef SIS900_MII_RESTRICT 3507 /* 3508 * The SiS 900 has only an internal PHY on the MII. Only allow 3509 * MII address 0. 3510 */ 3511 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3512 return -1; 3513 #endif 3514 3515 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3516 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3517 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3518 do { 3519 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3520 } while (enphy & ENPHY_ACCESS); 3521 3522 return 0; 3523 } 3524 3525 /* 3526 * sip_sis900_mii_statchg: [mii interface function] 3527 * 3528 * Callback from MII layer when media changes. 3529 */ 3530 static void 3531 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3532 { 3533 struct sip_softc *sc = ifp->if_softc; 3534 struct mii_data *mii = &sc->sc_mii; 3535 uint32_t flowctl; 3536 3537 /* 3538 * Get flow control negotiation result. 3539 */ 3540 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3541 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3542 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3543 mii->mii_media_active &= ~IFM_ETH_FMASK; 3544 } 3545 3546 /* 3547 * Update TXCFG for full-duplex operation. 3548 */ 3549 if ((mii->mii_media_active & IFM_FDX) != 0) 3550 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3551 else 3552 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3553 3554 /* 3555 * Update RXCFG for full-duplex or loopback. 3556 */ 3557 if ((mii->mii_media_active & IFM_FDX) != 0 || 3558 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3559 sc->sc_rxcfg |= RXCFG_ATX; 3560 else 3561 sc->sc_rxcfg &= ~RXCFG_ATX; 3562 3563 /* 3564 * Update IMR for use of 802.3x flow control. 3565 */ 3566 if (sc->sc_flowflags & IFM_FLOW) { 3567 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3568 flowctl = FLOWCTL_FLOWEN; 3569 } else { 3570 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3571 flowctl = 0; 3572 } 3573 3574 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3575 sc->sc_txcfg); 3576 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3577 sc->sc_rxcfg); 3578 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3579 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3580 } 3581 3582 /* 3583 * sip_dp83815_mii_readreg: [mii interface function] 3584 * 3585 * Read a PHY register on the MII. 3586 */ 3587 static int 3588 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3589 { 3590 struct sip_softc *sc = device_private(self); 3591 uint32_t data; 3592 3593 /* 3594 * The DP83815 only has an internal PHY. Only allow 3595 * MII address 0. 3596 */ 3597 if (phy != 0) 3598 return -1; 3599 3600 /* 3601 * Apparently, after a reset, the DP83815 can take a while 3602 * to respond. During this recovery period, the BMSR returns 3603 * a value of 0. Catch this -- it's not supposed to happen 3604 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3605 * PHY to come back to life. 3606 * 3607 * This works out because the BMSR is the first register 3608 * read during the PHY probe process. 3609 */ 3610 do { 3611 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3612 } while (reg == MII_BMSR && data == 0); 3613 3614 *val = data & 0xffff; 3615 return 0; 3616 } 3617 3618 /* 3619 * sip_dp83815_mii_writereg: [mii interface function] 3620 * 3621 * Write a PHY register to the MII. 3622 */ 3623 static int 3624 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3625 { 3626 struct sip_softc *sc = device_private(self); 3627 3628 /* 3629 * The DP83815 only has an internal PHY. Only allow 3630 * MII address 0. 3631 */ 3632 if (phy != 0) 3633 return -1; 3634 3635 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3636 3637 return 0; 3638 } 3639 3640 /* 3641 * sip_dp83815_mii_statchg: [mii interface function] 3642 * 3643 * Callback from MII layer when media changes. 3644 */ 3645 static void 3646 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3647 { 3648 struct sip_softc *sc = ifp->if_softc; 3649 3650 /* 3651 * Update TXCFG for full-duplex operation. 3652 */ 3653 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3654 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3655 else 3656 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3657 3658 /* 3659 * Update RXCFG for full-duplex or loopback. 3660 */ 3661 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3662 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3663 sc->sc_rxcfg |= RXCFG_ATX; 3664 else 3665 sc->sc_rxcfg &= ~RXCFG_ATX; 3666 3667 /* 3668 * XXX 802.3x flow control. 3669 */ 3670 3671 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3672 sc->sc_txcfg); 3673 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3674 sc->sc_rxcfg); 3675 3676 /* 3677 * Some DP83815s experience problems when used with short 3678 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3679 * sequence adjusts the DSP's signal attenuation to fix the 3680 * problem. 3681 */ 3682 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3683 uint32_t reg; 3684 3685 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3686 3687 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3688 reg &= 0x0fff; 3689 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3690 delay(100); 3691 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3692 reg &= 0x00ff; 3693 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3695 0x00e8); 3696 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3697 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3698 reg | 0x20); 3699 } 3700 3701 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3702 } 3703 } 3704 3705 static void 3706 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3707 const struct pci_attach_args *pa, uint8_t *enaddr) 3708 { 3709 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3710 uint8_t cksum, *e, match; 3711 int i; 3712 3713 /* 3714 * EEPROM data format for the DP83820 can be found in 3715 * the DP83820 manual, section 4.2.4. 3716 */ 3717 3718 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3719 3720 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3721 match = ~(match - 1); 3722 3723 cksum = 0x55; 3724 e = (uint8_t *)eeprom_data; 3725 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3726 cksum += *e++; 3727 3728 if (cksum != match) 3729 printf("%s: Checksum (%x) mismatch (%x)", 3730 device_xname(sc->sc_dev), cksum, match); 3731 3732 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3733 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3734 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3735 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3736 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3737 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3738 } 3739 3740 static void 3741 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3742 { 3743 int i; 3744 3745 /* 3746 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3747 * a reason, but I don't know it. 3748 */ 3749 for (i = 0; i < 10; i++) 3750 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3751 } 3752 3753 static void 3754 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3755 const struct pci_attach_args *pa, uint8_t *enaddr) 3756 { 3757 uint16_t myea[ETHER_ADDR_LEN / 2]; 3758 3759 switch (sc->sc_rev) { 3760 case SIS_REV_630S: 3761 case SIS_REV_630E: 3762 case SIS_REV_630EA1: 3763 case SIS_REV_630ET: 3764 case SIS_REV_635: 3765 /* 3766 * The MAC address for the on-board Ethernet of 3767 * the SiS 630 chipset is in the NVRAM. Kick 3768 * the chip into re-loading it from NVRAM, and 3769 * read the MAC address out of the filter registers. 3770 */ 3771 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3772 3773 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3774 RFCR_RFADDR_NODE0); 3775 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3776 0xffff; 3777 3778 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3779 RFCR_RFADDR_NODE2); 3780 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3781 0xffff; 3782 3783 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3784 RFCR_RFADDR_NODE4); 3785 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3786 0xffff; 3787 break; 3788 3789 case SIS_REV_960: 3790 { 3791 #define SIS_SET_EROMAR(x, y) \ 3792 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3793 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3794 3795 #define SIS_CLR_EROMAR(x, y) \ 3796 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3797 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3798 3799 int waittime, i; 3800 3801 /* Allow to read EEPROM from LAN. It is shared 3802 * between a 1394 controller and the NIC and each 3803 * time we access it, we need to set SIS_EECMD_REQ. 3804 */ 3805 SIS_SET_EROMAR(sc, EROMAR_REQ); 3806 3807 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3808 /* Force EEPROM to idle state. */ 3809 3810 /* 3811 * XXX-cube This is ugly. 3812 * I'll look for docs about it. 3813 */ 3814 SIS_SET_EROMAR(sc, EROMAR_EECS); 3815 sipcom_sis900_eeprom_delay(sc); 3816 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3817 SIS_SET_EROMAR(sc, EROMAR_EESK); 3818 sipcom_sis900_eeprom_delay(sc); 3819 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3820 sipcom_sis900_eeprom_delay(sc); 3821 } 3822 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3823 sipcom_sis900_eeprom_delay(sc); 3824 bus_space_write_4(sc->sc_st, sc->sc_sh, 3825 SIP_EROMAR, 0); 3826 3827 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3828 SIP_EROMAR) & EROMAR_GNT) { 3829 sipcom_read_eeprom(sc, 3830 SIP_EEPROM_ETHERNET_ID0 >> 1, 3831 sizeof(myea) / sizeof(myea[0]), 3832 myea); 3833 break; 3834 } 3835 DELAY(1); 3836 } 3837 3838 /* 3839 * Set SIS_EECTL_CLK to high, so a other master 3840 * can operate on the i2c bus. 3841 */ 3842 SIS_SET_EROMAR(sc, EROMAR_EESK); 3843 3844 /* Refuse EEPROM access by LAN */ 3845 SIS_SET_EROMAR(sc, EROMAR_DONE); 3846 } break; 3847 3848 default: 3849 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3850 sizeof(myea) / sizeof(myea[0]), myea); 3851 } 3852 3853 enaddr[0] = myea[0] & 0xff; 3854 enaddr[1] = myea[0] >> 8; 3855 enaddr[2] = myea[1] & 0xff; 3856 enaddr[3] = myea[1] >> 8; 3857 enaddr[4] = myea[2] & 0xff; 3858 enaddr[5] = myea[2] >> 8; 3859 } 3860 3861 /* Table and macro to bit-reverse an octet. */ 3862 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3863 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3864 3865 static void 3866 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3867 const struct pci_attach_args *pa, uint8_t *enaddr) 3868 { 3869 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3870 uint8_t cksum, *e, match; 3871 int i; 3872 3873 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3874 sizeof(eeprom_data[0]), eeprom_data); 3875 3876 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3877 match = ~(match - 1); 3878 3879 cksum = 0x55; 3880 e = (uint8_t *)eeprom_data; 3881 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3882 cksum += *e++; 3883 3884 if (cksum != match) 3885 printf("%s: Checksum (%x) mismatch (%x)", 3886 device_xname(sc->sc_dev), cksum, match); 3887 3888 /* 3889 * Unrolled because it makes slightly more sense this way. 3890 * The DP83815 stores the MAC address in bit 0 of word 6 3891 * through bit 15 of word 8. 3892 */ 3893 ea = &eeprom_data[6]; 3894 enaddr[0] = ((*ea & 0x1) << 7); 3895 ea++; 3896 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3897 enaddr[1] = ((*ea & 0x1FE) >> 1); 3898 enaddr[2] = ((*ea & 0x1) << 7); 3899 ea++; 3900 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3901 enaddr[3] = ((*ea & 0x1FE) >> 1); 3902 enaddr[4] = ((*ea & 0x1) << 7); 3903 ea++; 3904 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3905 enaddr[5] = ((*ea & 0x1FE) >> 1); 3906 3907 /* 3908 * In case that's not weird enough, we also need to reverse 3909 * the bits in each byte. This all actually makes more sense 3910 * if you think about the EEPROM storage as an array of bits 3911 * being shifted into bytes, but that's not how we're looking 3912 * at it here... 3913 */ 3914 for (i = 0; i < 6 ;i++) 3915 enaddr[i] = bbr(enaddr[i]); 3916 } 3917 3918 /* 3919 * sip_mediastatus: [ifmedia interface function] 3920 * 3921 * Get the current interface media status. 3922 */ 3923 static void 3924 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3925 { 3926 struct sip_softc *sc = ifp->if_softc; 3927 3928 if (!device_is_active(sc->sc_dev)) { 3929 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3930 ifmr->ifm_status = 0; 3931 return; 3932 } 3933 ether_mediastatus(ifp, ifmr); 3934 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3935 sc->sc_flowflags; 3936 } 3937
Indexes created Tue Sep 30 17:09:57 GMT 2025