if_sip.c revision 1.168.2.2
1 /* $NetBSD: if_sip.c,v 1.168.2.2 2020/04/08 14:08:09 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.168.2.2 2020/04/08 14:08:09 martin Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Set this to 1 to force-disable using the 64-bit data path 142 * on DP83820. 143 */ 144 static int gsip_disable_data64 = 0; 145 146 /* 147 * Control structures are DMA'd to the SiS900 chip. We allocate them in 148 * a single clump that maps to a single DMA segment to make several things 149 * easier. 150 */ 151 struct sip_control_data { 152 /* 153 * The transmit descriptors. 154 */ 155 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 156 157 /* 158 * The receive descriptors. 159 */ 160 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 161 }; 162 163 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 164 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 165 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 166 167 /* 168 * Software state for transmit jobs. 169 */ 170 struct sip_txsoft { 171 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 172 bus_dmamap_t txs_dmamap; /* our DMA map */ 173 int txs_firstdesc; /* first descriptor in packet */ 174 int txs_lastdesc; /* last descriptor in packet */ 175 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 176 }; 177 178 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 179 180 /* 181 * Software state for receive jobs. 182 */ 183 struct sip_rxsoft { 184 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 185 bus_dmamap_t rxs_dmamap; /* our DMA map */ 186 }; 187 188 enum sip_attach_stage { 189 SIP_ATTACH_FIN = 0 190 , SIP_ATTACH_CREATE_RXMAP 191 , SIP_ATTACH_CREATE_TXMAP 192 , SIP_ATTACH_LOAD_MAP 193 , SIP_ATTACH_CREATE_MAP 194 , SIP_ATTACH_MAP_MEM 195 , SIP_ATTACH_ALLOC_MEM 196 , SIP_ATTACH_INTR 197 , SIP_ATTACH_MAP 198 }; 199 200 /* 201 * Software state per device. 202 */ 203 struct sip_softc { 204 device_t sc_dev; /* generic device information */ 205 device_suspensor_t sc_suspensor; 206 pmf_qual_t sc_qual; 207 208 bus_space_tag_t sc_st; /* bus space tag */ 209 bus_space_handle_t sc_sh; /* bus space handle */ 210 bus_size_t sc_sz; /* bus space size */ 211 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 212 pci_chipset_tag_t sc_pc; 213 bus_dma_segment_t sc_seg; 214 struct ethercom sc_ethercom; /* ethernet common data */ 215 216 const struct sip_product *sc_model; /* which model are we? */ 217 bool sc_gigabit; /* 1: 83820, 0: other */ 218 bool sc_dma64; /* using 64-bit DMA addresses */ 219 int sc_rev; /* chip revision */ 220 221 unsigned int sc_bufptr_idx; 222 unsigned int sc_cmdsts_idx; 223 unsigned int sc_extsts_idx; /* DP83820 only */ 224 225 void *sc_ih; /* interrupt cookie */ 226 227 struct mii_data sc_mii; /* MII/media information */ 228 229 callout_t sc_tick_ch; /* tick callout */ 230 231 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 232 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 233 234 /* 235 * Software state for transmit and receive descriptors. 236 */ 237 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 238 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 239 240 /* 241 * Control data structures. 242 */ 243 struct sip_control_data *sc_control_data; 244 #define sc_txdescs sc_control_data->scd_txdescs 245 #define sc_rxdescs sc_control_data->scd_rxdescs 246 247 #ifdef SIP_EVENT_COUNTERS 248 /* 249 * Event counters. 250 */ 251 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 252 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 253 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 254 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 255 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 256 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 257 struct evcnt sc_ev_rxpause; /* PAUSE received */ 258 /* DP83820 only */ 259 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 260 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 261 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 262 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 263 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 264 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 265 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 266 #endif /* SIP_EVENT_COUNTERS */ 267 268 uint32_t sc_txcfg; /* prototype TXCFG register */ 269 uint32_t sc_rxcfg; /* prototype RXCFG register */ 270 uint32_t sc_imr; /* prototype IMR register */ 271 uint32_t sc_rfcr; /* prototype RFCR register */ 272 273 uint32_t sc_cfg; /* prototype CFG register */ 274 275 uint32_t sc_gpior; /* prototype GPIOR register */ 276 277 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 278 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 279 280 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 281 282 int sc_flowflags; /* 802.3x flow control flags */ 283 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 284 int sc_paused; /* paused indication */ 285 286 int sc_txfree; /* number of free Tx descriptors */ 287 int sc_txnext; /* next ready Tx descriptor */ 288 int sc_txwin; /* Tx descriptors since last intr */ 289 290 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 291 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 292 293 /* values of interface state at last init */ 294 struct { 295 /* if_capenable */ 296 uint64_t if_capenable; 297 /* ec_capenable */ 298 int ec_capenable; 299 /* VLAN_ATTACHED */ 300 int is_vlan; 301 } sc_prev; 302 303 short sc_if_flags; 304 305 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 306 int sc_rxdiscard; 307 int sc_rxlen; 308 struct mbuf *sc_rxhead; 309 struct mbuf *sc_rxtail; 310 struct mbuf **sc_rxtailp; 311 312 int sc_ntxdesc; 313 int sc_ntxdesc_mask; 314 315 int sc_nrxdesc_mask; 316 317 const struct sip_parm { 318 const struct sip_regs { 319 int r_rxcfg; 320 int r_txcfg; 321 } p_regs; 322 323 const struct sip_bits { 324 uint32_t b_txcfg_mxdma_8; 325 uint32_t b_txcfg_mxdma_16; 326 uint32_t b_txcfg_mxdma_32; 327 uint32_t b_txcfg_mxdma_64; 328 uint32_t b_txcfg_mxdma_128; 329 uint32_t b_txcfg_mxdma_256; 330 uint32_t b_txcfg_mxdma_512; 331 uint32_t b_txcfg_flth_mask; 332 uint32_t b_txcfg_drth_mask; 333 334 uint32_t b_rxcfg_mxdma_8; 335 uint32_t b_rxcfg_mxdma_16; 336 uint32_t b_rxcfg_mxdma_32; 337 uint32_t b_rxcfg_mxdma_64; 338 uint32_t b_rxcfg_mxdma_128; 339 uint32_t b_rxcfg_mxdma_256; 340 uint32_t b_rxcfg_mxdma_512; 341 342 uint32_t b_isr_txrcmp; 343 uint32_t b_isr_rxrcmp; 344 uint32_t b_isr_dperr; 345 uint32_t b_isr_sserr; 346 uint32_t b_isr_rmabt; 347 uint32_t b_isr_rtabt; 348 349 uint32_t b_cmdsts_size_mask; 350 } p_bits; 351 int p_filtmem; 352 int p_rxbuf_len; 353 bus_size_t p_tx_dmamap_size; 354 int p_ntxsegs; 355 int p_ntxsegs_alloc; 356 int p_nrxdesc; 357 } *sc_parm; 358 359 void (*sc_rxintr)(struct sip_softc *); 360 361 krndsource_t rnd_source; /* random source */ 362 }; 363 364 #define sc_bits sc_parm->p_bits 365 #define sc_regs sc_parm->p_regs 366 367 static const struct sip_parm sip_parm = { 368 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 369 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 370 , .p_tx_dmamap_size = MCLBYTES 371 , .p_ntxsegs = 16 372 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 373 , .p_nrxdesc = SIP_NRXDESC 374 , .p_bits = { 375 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 383 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 384 385 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 386 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 387 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 388 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 389 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 390 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 391 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 392 393 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 394 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 395 , .b_isr_dperr = 0x00800000 /* detected parity error */ 396 , .b_isr_sserr = 0x00400000 /* signalled system error */ 397 , .b_isr_rmabt = 0x00200000 /* received master abort */ 398 , .b_isr_rtabt = 0x00100000 /* received target abort */ 399 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 400 } 401 , .p_regs = { 402 .r_rxcfg = OTHER_SIP_RXCFG, 403 .r_txcfg = OTHER_SIP_TXCFG 404 } 405 }, gsip_parm = { 406 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 407 , .p_rxbuf_len = MCLBYTES - 8 408 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 409 , .p_ntxsegs = 64 410 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 411 , .p_nrxdesc = GSIP_NRXDESC 412 , .p_bits = { 413 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 421 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 422 423 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 424 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 425 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 426 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 427 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 428 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 429 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 430 431 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 432 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 433 , .b_isr_dperr = 0x00100000 /* detected parity error */ 434 , .b_isr_sserr = 0x00080000 /* signalled system error */ 435 , .b_isr_rmabt = 0x00040000 /* received master abort */ 436 , .b_isr_rtabt = 0x00020000 /* received target abort */ 437 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 438 } 439 , .p_regs = { 440 .r_rxcfg = DP83820_SIP_RXCFG, 441 .r_txcfg = DP83820_SIP_TXCFG 442 } 443 }; 444 445 static inline int 446 sip_nexttx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_ntxdesc_mask; 449 } 450 451 static inline int 452 sip_nextrx(const struct sip_softc *sc, int x) 453 { 454 return (x + 1) & sc->sc_nrxdesc_mask; 455 } 456 457 /* 83820 only */ 458 static inline void 459 sip_rxchain_reset(struct sip_softc *sc) 460 { 461 sc->sc_rxtailp = &sc->sc_rxhead; 462 *sc->sc_rxtailp = NULL; 463 sc->sc_rxlen = 0; 464 } 465 466 /* 83820 only */ 467 static inline void 468 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 469 { 470 *sc->sc_rxtailp = sc->sc_rxtail = m; 471 sc->sc_rxtailp = &m->m_next; 472 } 473 474 #ifdef SIP_EVENT_COUNTERS 475 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 476 #else 477 #define SIP_EVCNT_INCR(ev) /* nothing */ 478 #endif 479 480 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 481 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 482 483 static inline void 484 sip_set_rxdp(struct sip_softc *sc, bus_addr_t addr) 485 { 486 if (sc->sc_gigabit) 487 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP_HI, 488 BUS_ADDR_HI32(addr)); 489 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RXDP, BUS_ADDR_LO32(addr)); 490 } 491 492 static inline void 493 sip_set_txdp(struct sip_softc *sc, bus_addr_t addr) 494 { 495 if (sc->sc_gigabit) 496 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP_HI, 497 BUS_ADDR_HI32(addr)); 498 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, BUS_ADDR_LO32(addr)); 499 } 500 501 static inline void 502 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 503 { 504 int x, n; 505 506 x = x0; 507 n = n0; 508 509 /* If it will wrap around, sync to the end of the ring. */ 510 if (x + n > sc->sc_ntxdesc) { 511 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 512 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 513 (sc->sc_ntxdesc - x), ops); 514 n -= (sc->sc_ntxdesc - x); 515 x = 0; 516 } 517 518 /* Now sync whatever is left. */ 519 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 520 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 521 } 522 523 static inline void 524 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 525 { 526 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 527 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 528 } 529 530 static void 531 sip_init_txring(struct sip_softc *sc) 532 { 533 struct sip_desc *sipd; 534 bus_addr_t next_desc; 535 int i; 536 537 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 538 for (i = 0; i < sc->sc_ntxdesc; i++) { 539 sipd = &sc->sc_txdescs[i]; 540 next_desc = SIP_CDTXADDR(sc, sip_nexttx(sc, i)); 541 if (sc->sc_dma64) { 542 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 543 htole32(BUS_ADDR_LO32(next_desc)); 544 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 545 htole32(BUS_ADDR_HI32(next_desc)); 546 } else { 547 /* SIP_DESC_LINK == GSIP_DESC_LINK */ 548 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 549 } 550 } 551 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 553 sc->sc_txfree = sc->sc_ntxdesc; 554 sc->sc_txnext = 0; 555 sc->sc_txwin = 0; 556 } 557 558 static inline void 559 sip_init_txdesc(struct sip_softc *sc, int x, bus_addr_t bufptr, uint32_t cmdsts) 560 { 561 struct sip_desc *sipd = &sc->sc_txdescs[x]; 562 563 if (sc->sc_dma64) { 564 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 565 htole32(BUS_ADDR_LO32(bufptr)); 566 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 567 htole32(BUS_ADDR_HI32(bufptr)); 568 } else { 569 sipd->sipd_words[sc->sc_bufptr_idx] = htole32(bufptr); 570 } 571 sipd->sipd_words[sc->sc_extsts_idx] = 0; 572 membar_producer(); 573 sipd->sipd_words[sc->sc_cmdsts_idx] = htole32(cmdsts); 574 /* sip_cdtxsync() will be done later. */ 575 } 576 577 static inline void 578 sip_init_rxdesc(struct sip_softc *sc, int x) 579 { 580 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 581 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 582 const bus_addr_t next_desc = SIP_CDRXADDR(sc, sip_nextrx(sc, x)); 583 584 if (sc->sc_dma64) { 585 sipd->sipd_words[GSIP64_DESC_LINK_LO] = 586 htole32(BUS_ADDR_LO32(next_desc)); 587 sipd->sipd_words[GSIP64_DESC_LINK_HI] = 588 htole32(BUS_ADDR_HI32(next_desc)); 589 sipd->sipd_words[GSIP64_DESC_BUFPTR_LO] = 590 htole32(BUS_ADDR_LO32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 591 sipd->sipd_words[GSIP64_DESC_BUFPTR_HI] = 592 htole32(BUS_ADDR_HI32(rxs->rxs_dmamap->dm_segs[0].ds_addr)); 593 } else { 594 sipd->sipd_words[SIP_DESC_LINK] = htole32(next_desc); 595 sipd->sipd_words[sc->sc_bufptr_idx] = 596 htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 597 } 598 sipd->sipd_words[sc->sc_extsts_idx] = 0; 599 membar_producer(); 600 sipd->sipd_words[sc->sc_cmdsts_idx] = 601 htole32(CMDSTS_INTR | (sc->sc_parm->p_rxbuf_len & 602 sc->sc_bits.b_cmdsts_size_mask)); 603 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 604 } 605 606 #define SIP_CHIP_VERS(sc, v, p, r) \ 607 ((sc)->sc_model->sip_vendor == (v) && \ 608 (sc)->sc_model->sip_product == (p) && \ 609 (sc)->sc_rev == (r)) 610 611 #define SIP_CHIP_MODEL(sc, v, p) \ 612 ((sc)->sc_model->sip_vendor == (v) && \ 613 (sc)->sc_model->sip_product == (p)) 614 615 #define SIP_SIS900_REV(sc, rev) \ 616 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 617 618 #define SIP_TIMEOUT 1000 619 620 static int sip_ifflags_cb(struct ethercom *); 621 static void sipcom_start(struct ifnet *); 622 static void sipcom_watchdog(struct ifnet *); 623 static int sipcom_ioctl(struct ifnet *, u_long, void *); 624 static int sipcom_init(struct ifnet *); 625 static void sipcom_stop(struct ifnet *, int); 626 627 static bool sipcom_reset(struct sip_softc *); 628 static void sipcom_rxdrain(struct sip_softc *); 629 static int sipcom_add_rxbuf(struct sip_softc *, int); 630 static void sipcom_read_eeprom(struct sip_softc *, int, int, 631 uint16_t *); 632 static void sipcom_tick(void *); 633 634 static void sipcom_sis900_set_filter(struct sip_softc *); 635 static void sipcom_dp83815_set_filter(struct sip_softc *); 636 637 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 638 const struct pci_attach_args *, uint8_t *); 639 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 640 static void sipcom_sis900_read_macaddr(struct sip_softc *, 641 const struct pci_attach_args *, uint8_t *); 642 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 643 const struct pci_attach_args *, uint8_t *); 644 645 static int sipcom_intr(void *); 646 static void sipcom_txintr(struct sip_softc *); 647 static void sip_rxintr(struct sip_softc *); 648 static void gsip_rxintr(struct sip_softc *); 649 650 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 651 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 652 static void sipcom_dp83820_mii_statchg(struct ifnet *); 653 654 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 655 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 656 static void sipcom_sis900_mii_statchg(struct ifnet *); 657 658 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 659 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 660 static void sipcom_dp83815_mii_statchg(struct ifnet *); 661 662 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 663 664 static int sipcom_match(device_t, cfdata_t, void *); 665 static void sipcom_attach(device_t, device_t, void *); 666 static void sipcom_do_detach(device_t, enum sip_attach_stage); 667 static int sipcom_detach(device_t, int); 668 static bool sipcom_resume(device_t, const pmf_qual_t *); 669 static bool sipcom_suspend(device_t, const pmf_qual_t *); 670 671 int gsip_copy_small = 0; 672 int sip_copy_small = 0; 673 674 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 675 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 676 DVF_DETACH_SHUTDOWN); 677 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 678 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 679 DVF_DETACH_SHUTDOWN); 680 681 /* 682 * Descriptions of the variants of the SiS900. 683 */ 684 struct sip_variant { 685 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 686 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 687 void (*sipv_mii_statchg)(struct ifnet *); 688 void (*sipv_set_filter)(struct sip_softc *); 689 void (*sipv_read_macaddr)(struct sip_softc *, 690 const struct pci_attach_args *, uint8_t *); 691 }; 692 693 static uint32_t sipcom_mii_bitbang_read(device_t); 694 static void sipcom_mii_bitbang_write(device_t, uint32_t); 695 696 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 697 sipcom_mii_bitbang_read, 698 sipcom_mii_bitbang_write, 699 { 700 EROMAR_MDIO, /* MII_BIT_MDO */ 701 EROMAR_MDIO, /* MII_BIT_MDI */ 702 EROMAR_MDC, /* MII_BIT_MDC */ 703 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 704 0, /* MII_BIT_DIR_PHY_HOST */ 705 } 706 }; 707 708 static const struct sip_variant sipcom_variant_dp83820 = { 709 sipcom_dp83820_mii_readreg, 710 sipcom_dp83820_mii_writereg, 711 sipcom_dp83820_mii_statchg, 712 sipcom_dp83815_set_filter, 713 sipcom_dp83820_read_macaddr, 714 }; 715 716 static const struct sip_variant sipcom_variant_sis900 = { 717 sipcom_sis900_mii_readreg, 718 sipcom_sis900_mii_writereg, 719 sipcom_sis900_mii_statchg, 720 sipcom_sis900_set_filter, 721 sipcom_sis900_read_macaddr, 722 }; 723 724 static const struct sip_variant sipcom_variant_dp83815 = { 725 sipcom_dp83815_mii_readreg, 726 sipcom_dp83815_mii_writereg, 727 sipcom_dp83815_mii_statchg, 728 sipcom_dp83815_set_filter, 729 sipcom_dp83815_read_macaddr, 730 }; 731 732 733 /* 734 * Devices supported by this driver. 735 */ 736 static const struct sip_product { 737 pci_vendor_id_t sip_vendor; 738 pci_product_id_t sip_product; 739 const char *sip_name; 740 const struct sip_variant *sip_variant; 741 bool sip_gigabit; 742 } sipcom_products[] = { 743 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 744 "NatSemi DP83820 Gigabit Ethernet", 745 &sipcom_variant_dp83820, true }, 746 747 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 748 "SiS 900 10/100 Ethernet", 749 &sipcom_variant_sis900, false }, 750 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 751 "SiS 7016 10/100 Ethernet", 752 &sipcom_variant_sis900, false }, 753 754 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 755 "NatSemi DP83815 10/100 Ethernet", 756 &sipcom_variant_dp83815, false }, 757 758 { 0, 0, 759 NULL, 760 NULL, false }, 761 }; 762 763 static const struct sip_product * 764 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 765 { 766 const struct sip_product *sip; 767 768 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 769 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 770 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 771 sip->sip_gigabit == gigabit) 772 return sip; 773 } 774 return NULL; 775 } 776 777 /* 778 * I really hate stupid hardware vendors. There's a bit in the EEPROM 779 * which indicates if the card can do 64-bit data transfers. Unfortunately, 780 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 781 * which means we try to use 64-bit data transfers on those cards if we 782 * happen to be plugged into a 32-bit slot. 783 * 784 * What we do is use this table of cards known to be 64-bit cards. If 785 * you have a 64-bit card who's subsystem ID is not listed in this table, 786 * send the output of "pcictl dump ..." of the device to me so that your 787 * card will use the 64-bit data path when plugged into a 64-bit slot. 788 * 789 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 790 * June 30, 2002 791 */ 792 static int 793 sipcom_check_64bit(const struct pci_attach_args *pa) 794 { 795 static const struct { 796 pci_vendor_id_t c64_vendor; 797 pci_product_id_t c64_product; 798 } card64[] = { 799 /* Asante GigaNIX */ 800 { 0x128a, 0x0002 }, 801 802 /* Accton EN1407-T, Planex GN-1000TE */ 803 { 0x1113, 0x1407 }, 804 805 /* Netgear GA621 */ 806 { 0x1385, 0x621a }, 807 808 /* Netgear GA622 */ 809 { 0x1385, 0x622a }, 810 811 /* SMC EZ Card 1000 (9462TX) */ 812 { 0x10b8, 0x9462 }, 813 814 { 0, 0} 815 }; 816 pcireg_t subsys; 817 int i; 818 819 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 820 821 for (i = 0; card64[i].c64_vendor != 0; i++) { 822 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 823 PCI_PRODUCT(subsys) == card64[i].c64_product) 824 return 1; 825 } 826 827 return 0; 828 } 829 830 static int 831 sipcom_match(device_t parent, cfdata_t cf, void *aux) 832 { 833 struct pci_attach_args *pa = aux; 834 835 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 836 return 1; 837 838 return 0; 839 } 840 841 static void 842 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 843 { 844 uint32_t reg; 845 int i; 846 847 /* 848 * Cause the chip to load configuration data from the EEPROM. 849 */ 850 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 851 for (i = 0; i < 10000; i++) { 852 delay(10); 853 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 854 PTSCR_EELOAD_EN) == 0) 855 break; 856 } 857 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 858 PTSCR_EELOAD_EN) { 859 printf("%s: timeout loading configuration from EEPROM\n", 860 device_xname(sc->sc_dev)); 861 return; 862 } 863 864 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 865 866 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 867 if (reg & CFG_PCI64_DET) { 868 const char *using64 = NULL; 869 870 if (reg & CFG_DATA64_EN) { 871 /* 872 * Check to see if this card is 64-bit. If so, 873 * enable 64-bit data transfers. 874 * 875 * We can't trust the DATA64_EN bit in the EEPROM, 876 * because vendors of 32-bit cards fail to clear 877 * that bit in many cases (yet the card still detects 878 * that it's in a 64-bit slot because I guess they 879 * wired up ACK64# and REQ64#). 880 */ 881 if (gsip_disable_data64) 882 using64 = "force-disabled"; 883 else if (sipcom_check_64bit(pa)) { 884 sc->sc_cfg |= CFG_DATA64_EN; 885 using64 = "enabled"; 886 } else 887 using64 = "disabled (32-bit card)"; 888 } else { 889 using64 = "disabled in EEPROM"; 890 } 891 printf("%s: 64-bit slot detected, 64-bit tranfers %s\n", 892 device_xname(sc->sc_dev), using64); 893 } 894 895 /* 896 * The T64ADDR bit is loaded by the chip from the EEPROM and 897 * is read-only. 898 */ 899 if (reg & CFG_T64ADDR) 900 sc->sc_cfg |= CFG_T64ADDR; 901 902 /* 903 * We can use 64-bit DMA addressing regardless of what 904 * sort of slot we're in. 905 */ 906 if (pci_dma64_available(pa)) { 907 sc->sc_dmat = pa->pa_dmat64; 908 sc->sc_cfg |= CFG_M64ADDR; 909 sc->sc_dma64 = true; 910 } 911 912 if (reg & (CFG_TBI_EN | CFG_EXT_125)) { 913 const char *sep = ""; 914 printf("%s: using ", device_xname(sc->sc_dev)); 915 if (reg & CFG_EXT_125) { 916 sc->sc_cfg |= CFG_EXT_125; 917 printf("%sexternal 125MHz clock", sep); 918 sep = ", "; 919 } 920 if (reg & CFG_TBI_EN) { 921 sc->sc_cfg |= CFG_TBI_EN; 922 printf("%sten-bit interface", sep); 923 sep = ", "; 924 } 925 printf("\n"); 926 } 927 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 928 (reg & CFG_MRM_DIS) != 0) 929 sc->sc_cfg |= CFG_MRM_DIS; 930 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 931 (reg & CFG_MWI_DIS) != 0) 932 sc->sc_cfg |= CFG_MWI_DIS; 933 934 /* 935 * Use the extended descriptor format on the DP83820. This 936 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 937 * checksumming. 938 */ 939 sc->sc_cfg |= CFG_EXTSTS_EN; 940 } 941 942 static int 943 sipcom_detach(device_t self, int flags) 944 { 945 int s; 946 947 s = splnet(); 948 sipcom_do_detach(self, SIP_ATTACH_FIN); 949 splx(s); 950 951 return 0; 952 } 953 954 static void 955 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 956 { 957 int i; 958 struct sip_softc *sc = device_private(self); 959 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 960 961 /* 962 * Free any resources we've allocated during attach. 963 * Do this in reverse order and fall through. 964 */ 965 switch (stage) { 966 case SIP_ATTACH_FIN: 967 sipcom_stop(ifp, 1); 968 pmf_device_deregister(self); 969 #ifdef SIP_EVENT_COUNTERS 970 /* 971 * Attach event counters. 972 */ 973 evcnt_detach(&sc->sc_ev_txforceintr); 974 evcnt_detach(&sc->sc_ev_txdstall); 975 evcnt_detach(&sc->sc_ev_hiberr); 976 evcnt_detach(&sc->sc_ev_rxintr); 977 evcnt_detach(&sc->sc_ev_txiintr); 978 evcnt_detach(&sc->sc_ev_txdintr); 979 if (!sc->sc_gigabit) { 980 evcnt_detach(&sc->sc_ev_rxpause); 981 } else { 982 evcnt_detach(&sc->sc_ev_txudpsum); 983 evcnt_detach(&sc->sc_ev_txtcpsum); 984 evcnt_detach(&sc->sc_ev_txipsum); 985 evcnt_detach(&sc->sc_ev_rxudpsum); 986 evcnt_detach(&sc->sc_ev_rxtcpsum); 987 evcnt_detach(&sc->sc_ev_rxipsum); 988 evcnt_detach(&sc->sc_ev_txpause); 989 evcnt_detach(&sc->sc_ev_rxpause); 990 } 991 #endif /* SIP_EVENT_COUNTERS */ 992 993 rnd_detach_source(&sc->rnd_source); 994 995 ether_ifdetach(ifp); 996 if_detach(ifp); 997 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 998 ifmedia_fini(&sc->sc_mii.mii_media); 999 1000 /*FALLTHROUGH*/ 1001 case SIP_ATTACH_CREATE_RXMAP: 1002 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1003 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 1004 bus_dmamap_destroy(sc->sc_dmat, 1005 sc->sc_rxsoft[i].rxs_dmamap); 1006 } 1007 /*FALLTHROUGH*/ 1008 case SIP_ATTACH_CREATE_TXMAP: 1009 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1010 if (sc->sc_txsoft[i].txs_dmamap != NULL) 1011 bus_dmamap_destroy(sc->sc_dmat, 1012 sc->sc_txsoft[i].txs_dmamap); 1013 } 1014 /*FALLTHROUGH*/ 1015 case SIP_ATTACH_LOAD_MAP: 1016 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 1017 /*FALLTHROUGH*/ 1018 case SIP_ATTACH_CREATE_MAP: 1019 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 1020 /*FALLTHROUGH*/ 1021 case SIP_ATTACH_MAP_MEM: 1022 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 1023 sizeof(struct sip_control_data)); 1024 /*FALLTHROUGH*/ 1025 case SIP_ATTACH_ALLOC_MEM: 1026 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 1027 /* FALLTHROUGH*/ 1028 case SIP_ATTACH_INTR: 1029 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 1030 /* FALLTHROUGH*/ 1031 case SIP_ATTACH_MAP: 1032 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 1033 break; 1034 default: 1035 break; 1036 } 1037 return; 1038 } 1039 1040 static bool 1041 sipcom_resume(device_t self, const pmf_qual_t *qual) 1042 { 1043 struct sip_softc *sc = device_private(self); 1044 1045 return sipcom_reset(sc); 1046 } 1047 1048 static bool 1049 sipcom_suspend(device_t self, const pmf_qual_t *qual) 1050 { 1051 struct sip_softc *sc = device_private(self); 1052 1053 sipcom_rxdrain(sc); 1054 return true; 1055 } 1056 1057 static void 1058 sipcom_attach(device_t parent, device_t self, void *aux) 1059 { 1060 struct sip_softc *sc = device_private(self); 1061 struct pci_attach_args *pa = aux; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 struct mii_data * const mii = &sc->sc_mii; 1064 pci_chipset_tag_t pc = pa->pa_pc; 1065 pci_intr_handle_t ih; 1066 const char *intrstr = NULL; 1067 bus_space_tag_t iot, memt; 1068 bus_space_handle_t ioh, memh; 1069 bus_size_t iosz, memsz; 1070 int ioh_valid, memh_valid; 1071 int i, rseg, error; 1072 const struct sip_product *sip; 1073 uint8_t enaddr[ETHER_ADDR_LEN]; 1074 pcireg_t csr; 1075 pcireg_t memtype; 1076 bus_size_t tx_dmamap_size; 1077 int ntxsegs_alloc; 1078 cfdata_t cf = device_cfdata(self); 1079 char intrbuf[PCI_INTRSTR_LEN]; 1080 1081 callout_init(&sc->sc_tick_ch, 0); 1082 callout_setfunc(&sc->sc_tick_ch, sipcom_tick, sc); 1083 1084 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1085 if (sip == NULL) { 1086 aprint_error("\n"); 1087 panic("%s: impossible", __func__); 1088 } 1089 sc->sc_dev = self; 1090 sc->sc_gigabit = sip->sip_gigabit; 1091 sc->sc_dma64 = false; 1092 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1093 sc->sc_pc = pc; 1094 1095 if (sc->sc_gigabit) { 1096 if (sc->sc_dma64) { 1097 sc->sc_bufptr_idx = GSIP64_DESC_BUFPTR_LO; 1098 sc->sc_cmdsts_idx = GSIP64_DESC_CMDSTS; 1099 sc->sc_extsts_idx = GSIP64_DESC_EXTSTS; 1100 } else { 1101 sc->sc_bufptr_idx = GSIP_DESC_BUFPTR; 1102 sc->sc_cmdsts_idx = GSIP_DESC_CMDSTS; 1103 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1104 } 1105 sc->sc_rxintr = gsip_rxintr; 1106 sc->sc_parm = &gsip_parm; 1107 } else { 1108 sc->sc_rxintr = sip_rxintr; 1109 sc->sc_parm = &sip_parm; 1110 sc->sc_bufptr_idx = SIP_DESC_BUFPTR; 1111 sc->sc_cmdsts_idx = SIP_DESC_CMDSTS; 1112 /* 1113 * EXTSTS doesn't really exist on non-GigE parts, 1114 * but we initialize the index for simplicity later. 1115 */ 1116 sc->sc_extsts_idx = GSIP_DESC_EXTSTS; 1117 } 1118 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1119 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1120 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1121 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1122 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1123 1124 sc->sc_rev = PCI_REVISION(pa->pa_class); 1125 1126 aprint_naive("\n"); 1127 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1128 1129 sc->sc_model = sip; 1130 1131 /* 1132 * XXX Work-around broken PXE firmware on some boards. 1133 * 1134 * The DP83815 shares an address decoder with the MEM BAR 1135 * and the ROM BAR. Make sure the ROM BAR is disabled, 1136 * so that memory mapped access works. 1137 */ 1138 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1139 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1140 ~PCI_MAPREG_ROM_ENABLE); 1141 1142 /* 1143 * Map the device. 1144 */ 1145 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1146 PCI_MAPREG_TYPE_IO, 0, 1147 &iot, &ioh, NULL, &iosz) == 0); 1148 if (sc->sc_gigabit) { 1149 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1150 switch (memtype) { 1151 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1152 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1153 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1154 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1155 break; 1156 default: 1157 memh_valid = 0; 1158 } 1159 } else { 1160 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1161 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, 1162 &memt, &memh, NULL, &memsz) == 0); 1163 } 1164 1165 if (memh_valid) { 1166 sc->sc_st = memt; 1167 sc->sc_sh = memh; 1168 sc->sc_sz = memsz; 1169 } else if (ioh_valid) { 1170 sc->sc_st = iot; 1171 sc->sc_sh = ioh; 1172 sc->sc_sz = iosz; 1173 } else { 1174 aprint_error_dev(self, "unable to map device registers\n"); 1175 return; 1176 } 1177 1178 sc->sc_dmat = pa->pa_dmat; 1179 1180 /* 1181 * Make sure bus mastering is enabled. Also make sure 1182 * Write/Invalidate is enabled if we're allowed to use it. 1183 */ 1184 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1185 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1186 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1187 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1188 csr | PCI_COMMAND_MASTER_ENABLE); 1189 1190 /* Power up chip */ 1191 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1192 if (error != 0 && error != EOPNOTSUPP) { 1193 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1194 return; 1195 } 1196 1197 /* 1198 * Map and establish our interrupt. 1199 */ 1200 if (pci_intr_map(pa, &ih)) { 1201 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1202 return; 1203 } 1204 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1205 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1206 device_xname(self)); 1207 if (sc->sc_ih == NULL) { 1208 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1209 if (intrstr != NULL) 1210 aprint_error(" at %s", intrstr); 1211 aprint_error("\n"); 1212 sipcom_do_detach(self, SIP_ATTACH_MAP); 1213 return; 1214 } 1215 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1216 1217 SIMPLEQ_INIT(&sc->sc_txfreeq); 1218 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1219 1220 /* 1221 * Allocate the control data structures, and create and load the 1222 * DMA map for it. 1223 */ 1224 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1225 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1226 &rseg, 0)) != 0) { 1227 aprint_error_dev(sc->sc_dev, 1228 "unable to allocate control data, error = %d\n", error); 1229 sipcom_do_detach(self, SIP_ATTACH_INTR); 1230 return; 1231 } 1232 1233 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1234 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1235 BUS_DMA_COHERENT)) != 0) { 1236 aprint_error_dev(sc->sc_dev, 1237 "unable to map control data, error = %d\n", error); 1238 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1239 } 1240 1241 if ((error = bus_dmamap_create(sc->sc_dmat, 1242 sizeof(struct sip_control_data), 1, 1243 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1244 aprint_error_dev(self, "unable to create control data DMA map" 1245 ", error = %d\n", error); 1246 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1247 } 1248 1249 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1250 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1251 0)) != 0) { 1252 aprint_error_dev(self, "unable to load control data DMA map" 1253 ", error = %d\n", error); 1254 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1255 } 1256 1257 /* 1258 * Create the transmit buffer DMA maps. 1259 */ 1260 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1261 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1262 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1263 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1264 aprint_error_dev(self, "unable to create tx DMA map %d" 1265 ", error = %d\n", i, error); 1266 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1267 } 1268 } 1269 1270 /* 1271 * Create the receive buffer DMA maps. 1272 */ 1273 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1274 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1275 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1276 aprint_error_dev(self, "unable to create rx DMA map %d" 1277 ", error = %d\n", i, error); 1278 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1279 } 1280 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1281 } 1282 1283 /* 1284 * Reset the chip to a known state. 1285 */ 1286 sipcom_reset(sc); 1287 1288 /* 1289 * Read the Ethernet address from the EEPROM. This might 1290 * also fetch other stuff from the EEPROM and stash it 1291 * in the softc. 1292 */ 1293 sc->sc_cfg = 0; 1294 if (!sc->sc_gigabit) { 1295 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1296 SIP_SIS900_REV(sc, SIS_REV_900B)) 1297 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1298 1299 if (SIP_SIS900_REV(sc, SIS_REV_635) || 1300 SIP_SIS900_REV(sc, SIS_REV_960) || 1301 SIP_SIS900_REV(sc, SIS_REV_900B)) 1302 sc->sc_cfg |= 1303 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1304 CFG_EDBMASTEN); 1305 } 1306 1307 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1308 1309 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1310 1311 /* 1312 * Initialize the configuration register: aggressive PCI 1313 * bus request algorithm, default backoff, default OW timer, 1314 * default parity error detection. 1315 * 1316 * NOTE: "Big endian mode" is useless on the SiS900 and 1317 * friends -- it affects packet data, not descriptors. 1318 */ 1319 if (sc->sc_gigabit) 1320 sipcom_dp83820_attach(sc, pa); 1321 1322 /* 1323 * Initialize our media structures and probe the MII. 1324 */ 1325 mii->mii_ifp = ifp; 1326 mii->mii_readreg = sip->sip_variant->sipv_mii_readreg; 1327 mii->mii_writereg = sip->sip_variant->sipv_mii_writereg; 1328 mii->mii_statchg = sip->sip_variant->sipv_mii_statchg; 1329 sc->sc_ethercom.ec_mii = mii; 1330 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1331 sipcom_mediastatus); 1332 1333 /* 1334 * XXX We cannot handle flow control on the DP83815. 1335 */ 1336 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1337 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1338 MII_OFFSET_ANY, 0); 1339 else 1340 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 1341 MII_OFFSET_ANY, MIIF_DOPAUSE); 1342 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1343 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1344 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1345 } else 1346 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1347 1348 ifp = &sc->sc_ethercom.ec_if; 1349 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1350 ifp->if_softc = sc; 1351 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1352 sc->sc_if_flags = ifp->if_flags; 1353 ifp->if_ioctl = sipcom_ioctl; 1354 ifp->if_start = sipcom_start; 1355 ifp->if_watchdog = sipcom_watchdog; 1356 ifp->if_init = sipcom_init; 1357 ifp->if_stop = sipcom_stop; 1358 IFQ_SET_READY(&ifp->if_snd); 1359 1360 /* 1361 * We can support 802.1Q VLAN-sized frames. 1362 */ 1363 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1364 1365 if (sc->sc_gigabit) { 1366 /* 1367 * And the DP83820 can do VLAN tagging in hardware, and 1368 * support the jumbo Ethernet MTU. 1369 */ 1370 sc->sc_ethercom.ec_capabilities |= 1371 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1372 1373 /* 1374 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1375 * in hardware. 1376 */ 1377 ifp->if_capabilities |= 1378 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1379 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1380 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1381 } 1382 1383 /* 1384 * Attach the interface. 1385 */ 1386 if_attach(ifp); 1387 if_deferred_start_init(ifp, NULL); 1388 ether_ifattach(ifp, enaddr); 1389 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1390 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1391 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1392 sc->sc_prev.if_capenable = ifp->if_capenable; 1393 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1394 RND_TYPE_NET, RND_FLAG_DEFAULT); 1395 1396 /* 1397 * The number of bytes that must be available in 1398 * the Tx FIFO before the bus master can DMA more 1399 * data into the FIFO. 1400 */ 1401 sc->sc_tx_fill_thresh = 64 / 32; 1402 1403 /* 1404 * Start at a drain threshold of 512 bytes. We will 1405 * increase it if a DMA underrun occurs. 1406 * 1407 * XXX The minimum value of this variable should be 1408 * tuned. We may be able to improve performance 1409 * by starting with a lower value. That, however, 1410 * may trash the first few outgoing packets if the 1411 * PCI bus is saturated. 1412 */ 1413 if (sc->sc_gigabit) 1414 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1415 else 1416 sc->sc_tx_drain_thresh = 1504 / 32; 1417 1418 /* 1419 * Initialize the Rx FIFO drain threshold. 1420 * 1421 * This is in units of 8 bytes. 1422 * 1423 * We should never set this value lower than 2; 14 bytes are 1424 * required to filter the packet. 1425 */ 1426 sc->sc_rx_drain_thresh = 128 / 8; 1427 1428 #ifdef SIP_EVENT_COUNTERS 1429 /* 1430 * Attach event counters. 1431 */ 1432 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1433 NULL, device_xname(sc->sc_dev), "txdstall"); 1434 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1435 NULL, device_xname(sc->sc_dev), "txforceintr"); 1436 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1437 NULL, device_xname(sc->sc_dev), "txdintr"); 1438 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1439 NULL, device_xname(sc->sc_dev), "txiintr"); 1440 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1441 NULL, device_xname(sc->sc_dev), "rxintr"); 1442 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1443 NULL, device_xname(sc->sc_dev), "hiberr"); 1444 if (!sc->sc_gigabit) { 1445 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1446 NULL, device_xname(sc->sc_dev), "rxpause"); 1447 } else { 1448 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1449 NULL, device_xname(sc->sc_dev), "rxpause"); 1450 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1451 NULL, device_xname(sc->sc_dev), "txpause"); 1452 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1453 NULL, device_xname(sc->sc_dev), "rxipsum"); 1454 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1455 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1456 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1457 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1458 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1459 NULL, device_xname(sc->sc_dev), "txipsum"); 1460 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1461 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1462 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1463 NULL, device_xname(sc->sc_dev), "txudpsum"); 1464 } 1465 #endif /* SIP_EVENT_COUNTERS */ 1466 1467 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1468 pmf_class_network_register(self, ifp); 1469 else 1470 aprint_error_dev(self, "couldn't establish power handler\n"); 1471 } 1472 1473 static inline void 1474 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1475 uint64_t capenable) 1476 { 1477 uint32_t extsts = 0; 1478 #ifdef DEBUG 1479 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1480 #endif 1481 /* 1482 * If VLANs are enabled and the packet has a VLAN tag, set 1483 * up the descriptor to encapsulate the packet for us. 1484 * 1485 * This apparently has to be on the last descriptor of 1486 * the packet. 1487 */ 1488 1489 /* 1490 * Byte swapping is tricky. We need to provide the tag 1491 * in a network byte order. On a big-endian machine, 1492 * the byteorder is correct, but we need to swap it 1493 * anyway, because this will be undone by the outside 1494 * htole32(). That's why there must be an 1495 * unconditional swap instead of htons() inside. 1496 */ 1497 if (vlan_has_tag(m0)) { 1498 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |= 1499 htole32(EXTSTS_VPKT | 1500 (bswap16(vlan_get_tag(m0)) & 1501 EXTSTS_VTCI)); 1502 } 1503 1504 /* 1505 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1506 * checksumming, set up the descriptor to do this work 1507 * for us. 1508 * 1509 * This apparently has to be on the first descriptor of 1510 * the packet. 1511 * 1512 * Byte-swap constants so the compiler can optimize. 1513 */ 1514 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1515 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1516 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1517 extsts |= htole32(EXTSTS_IPPKT); 1518 } 1519 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1520 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1521 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1522 extsts |= htole32(EXTSTS_TCPPKT); 1523 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1524 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1525 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1526 extsts |= htole32(EXTSTS_UDPPKT); 1527 } 1528 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts; 1529 } 1530 1531 /* 1532 * sip_start: [ifnet interface function] 1533 * 1534 * Start packet transmission on the interface. 1535 */ 1536 static void 1537 sipcom_start(struct ifnet *ifp) 1538 { 1539 struct sip_softc *sc = ifp->if_softc; 1540 struct mbuf *m0; 1541 struct mbuf *m; 1542 struct sip_txsoft *txs; 1543 bus_dmamap_t dmamap; 1544 int error, nexttx, lasttx, seg; 1545 int ofree = sc->sc_txfree; 1546 uint32_t cmdsts; 1547 #if 0 1548 int firsttx = sc->sc_txnext; 1549 #endif 1550 1551 /* 1552 * If we've been told to pause, don't transmit any more packets. 1553 */ 1554 if (!sc->sc_gigabit && sc->sc_paused) 1555 return; 1556 1557 if ((ifp->if_flags & IFF_RUNNING) != IFF_RUNNING) 1558 return; 1559 1560 /* 1561 * Loop through the send queue, setting up transmit descriptors 1562 * until we drain the queue, or use up all available transmit 1563 * descriptors. 1564 */ 1565 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL) { 1566 /* 1567 * Grab a packet off the queue. 1568 */ 1569 IFQ_POLL(&ifp->if_snd, m0); 1570 if (m0 == NULL) 1571 break; 1572 m = NULL; 1573 1574 dmamap = txs->txs_dmamap; 1575 1576 /* 1577 * Load the DMA map. If this fails, the packet either 1578 * didn't fit in the alloted number of segments, or we 1579 * were short on resources. 1580 */ 1581 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1582 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1583 /* In the non-gigabit case, we'll copy and try again. */ 1584 if (error != 0 && !sc->sc_gigabit) { 1585 MGETHDR(m, M_DONTWAIT, MT_DATA); 1586 if (m == NULL) { 1587 printf("%s: unable to allocate Tx mbuf\n", 1588 device_xname(sc->sc_dev)); 1589 break; 1590 } 1591 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1592 if (m0->m_pkthdr.len > MHLEN) { 1593 MCLGET(m, M_DONTWAIT); 1594 if ((m->m_flags & M_EXT) == 0) { 1595 printf("%s: unable to allocate Tx " 1596 "cluster\n", 1597 device_xname(sc->sc_dev)); 1598 m_freem(m); 1599 break; 1600 } 1601 } 1602 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1603 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1604 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1605 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1606 if (error) { 1607 printf("%s: unable to load Tx buffer, error = " 1608 "%d\n", device_xname(sc->sc_dev), error); 1609 break; 1610 } 1611 } else if (error == EFBIG) { 1612 /* 1613 * For the too-many-segments case, we simply 1614 * report an error and drop the packet, 1615 * since we can't sanely copy a jumbo packet 1616 * to a single buffer. 1617 */ 1618 printf("%s: Tx packet consumes too many DMA segments, " 1619 "dropping...\n", device_xname(sc->sc_dev)); 1620 IFQ_DEQUEUE(&ifp->if_snd, m0); 1621 m_freem(m0); 1622 continue; 1623 } else if (error != 0) { 1624 /* 1625 * Short on resources, just stop for now. 1626 */ 1627 break; 1628 } 1629 1630 /* 1631 * Ensure we have enough descriptors free to describe 1632 * the packet. Note, we always reserve one descriptor 1633 * at the end of the ring as a termination point, to 1634 * prevent wrap-around. 1635 */ 1636 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1637 /* 1638 * Not enough free descriptors to transmit this 1639 * packet. 1640 */ 1641 bus_dmamap_unload(sc->sc_dmat, dmamap); 1642 if (m != NULL) 1643 m_freem(m); 1644 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1645 break; 1646 } 1647 1648 IFQ_DEQUEUE(&ifp->if_snd, m0); 1649 if (m != NULL) { 1650 m_freem(m0); 1651 m0 = m; 1652 } 1653 1654 /* 1655 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1656 */ 1657 1658 /* Sync the DMA map. */ 1659 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1660 BUS_DMASYNC_PREWRITE); 1661 1662 /* 1663 * Initialize the transmit descriptors. 1664 */ 1665 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1666 seg < dmamap->dm_nsegs; 1667 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1668 /* 1669 * If this is the first descriptor we're 1670 * enqueueing, don't set the OWN bit just 1671 * yet. That could cause a race condition. 1672 * We'll do it below. 1673 */ 1674 1675 cmdsts = dmamap->dm_segs[seg].ds_len; 1676 if (nexttx != sc->sc_txnext) 1677 cmdsts |= CMDSTS_OWN; 1678 if (seg < dmamap->dm_nsegs - 1) 1679 cmdsts |= CMDSTS_MORE; 1680 sip_init_txdesc(sc, nexttx, 1681 dmamap->dm_segs[seg].ds_addr, cmdsts); 1682 lasttx = nexttx; 1683 } 1684 1685 /* 1686 * If we're in the interrupt delay window, delay the 1687 * interrupt. 1688 */ 1689 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1690 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1691 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |= 1692 htole32(CMDSTS_INTR); 1693 sc->sc_txwin = 0; 1694 } 1695 1696 if (sc->sc_gigabit) 1697 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1698 1699 /* Sync the descriptors we're using. */ 1700 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1702 1703 /* 1704 * The entire packet is set up. Give the first descrptor 1705 * to the chip now. 1706 */ 1707 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |= 1708 htole32(CMDSTS_OWN); 1709 sip_cdtxsync(sc, sc->sc_txnext, 1, 1710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1711 1712 /* 1713 * Store a pointer to the packet so we can free it later, 1714 * and remember what txdirty will be once the packet is 1715 * done. 1716 */ 1717 txs->txs_mbuf = m0; 1718 txs->txs_firstdesc = sc->sc_txnext; 1719 txs->txs_lastdesc = lasttx; 1720 1721 /* Advance the tx pointer. */ 1722 sc->sc_txfree -= dmamap->dm_nsegs; 1723 sc->sc_txnext = nexttx; 1724 1725 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1726 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1727 1728 /* Pass the packet to any BPF listeners. */ 1729 bpf_mtap(ifp, m0, BPF_D_OUT); 1730 } 1731 1732 if (sc->sc_txfree != ofree) { 1733 /* 1734 * Start the transmit process. Note, the manual says 1735 * that if there are no pending transmissions in the 1736 * chip's internal queue (indicated by TXE being clear), 1737 * then the driver software must set the TXDP to the 1738 * first descriptor to be transmitted. However, if we 1739 * do this, it causes serious performance degredation on 1740 * the DP83820 under load, not setting TXDP doesn't seem 1741 * to adversely affect the SiS 900 or DP83815. 1742 * 1743 * Well, I guess it wouldn't be the first time a manual 1744 * has lied -- and they could be speaking of the NULL- 1745 * terminated descriptor list case, rather than OWN- 1746 * terminated rings. 1747 */ 1748 #if 0 1749 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1750 CR_TXE) == 0) { 1751 sip_set_txdp(sc, SIP_CDTXADDR(sc, firsttx)); 1752 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1753 } 1754 #else 1755 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1756 #endif 1757 1758 /* Set a watchdog timer in case the chip flakes out. */ 1759 /* Gigabit autonegotiation takes 5 seconds. */ 1760 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1761 } 1762 } 1763 1764 /* 1765 * sip_watchdog: [ifnet interface function] 1766 * 1767 * Watchdog timer handler. 1768 */ 1769 static void 1770 sipcom_watchdog(struct ifnet *ifp) 1771 { 1772 struct sip_softc *sc = ifp->if_softc; 1773 1774 /* 1775 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1776 * If we get a timeout, try and sweep up transmit descriptors. 1777 * If we manage to sweep them all up, ignore the lack of 1778 * interrupt. 1779 */ 1780 sipcom_txintr(sc); 1781 1782 if (sc->sc_txfree != sc->sc_ntxdesc) { 1783 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1784 if_statinc(ifp, if_oerrors); 1785 1786 /* Reset the interface. */ 1787 (void) sipcom_init(ifp); 1788 } else if (ifp->if_flags & IFF_DEBUG) 1789 printf("%s: recovered from device timeout\n", 1790 device_xname(sc->sc_dev)); 1791 1792 /* Try to get more packets going. */ 1793 sipcom_start(ifp); 1794 } 1795 1796 /* If the interface is up and running, only modify the receive 1797 * filter when setting promiscuous or debug mode. Otherwise fall 1798 * through to ether_ioctl, which will reset the chip. 1799 */ 1800 static int 1801 sip_ifflags_cb(struct ethercom *ec) 1802 { 1803 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1804 == (sc)->sc_ethercom.ec_capenable) \ 1805 && ((sc)->sc_prev.is_vlan == \ 1806 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1807 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1808 struct ifnet *ifp = &ec->ec_if; 1809 struct sip_softc *sc = ifp->if_softc; 1810 int change = ifp->if_flags ^ sc->sc_if_flags; 1811 1812 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1813 !COMPARE_IC(sc, ifp)) 1814 return ENETRESET; 1815 /* Set up the receive filter. */ 1816 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1817 return 0; 1818 } 1819 1820 /* 1821 * sip_ioctl: [ifnet interface function] 1822 * 1823 * Handle control requests from the operator. 1824 */ 1825 static int 1826 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1827 { 1828 struct sip_softc *sc = ifp->if_softc; 1829 struct ifreq *ifr = (struct ifreq *)data; 1830 int s, error; 1831 1832 s = splnet(); 1833 1834 switch (cmd) { 1835 case SIOCSIFMEDIA: 1836 /* Flow control requires full-duplex mode. */ 1837 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1838 (ifr->ifr_media & IFM_FDX) == 0) 1839 ifr->ifr_media &= ~IFM_ETH_FMASK; 1840 1841 /* XXX */ 1842 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1843 ifr->ifr_media &= ~IFM_ETH_FMASK; 1844 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1845 if (sc->sc_gigabit && 1846 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1847 /* We can do both TXPAUSE and RXPAUSE. */ 1848 ifr->ifr_media |= 1849 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1850 } else if (ifr->ifr_media & IFM_FLOW) { 1851 /* 1852 * Both TXPAUSE and RXPAUSE must be set. 1853 * (SiS900 and DP83815 don't have PAUSE_ASYM 1854 * feature.) 1855 * 1856 * XXX Can SiS900 and DP83815 send PAUSE? 1857 */ 1858 ifr->ifr_media |= 1859 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1860 } 1861 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1862 } 1863 /*FALLTHROUGH*/ 1864 default: 1865 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1866 break; 1867 1868 error = 0; 1869 1870 if (cmd == SIOCSIFCAP) 1871 error = (*ifp->if_init)(ifp); 1872 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1873 ; 1874 else if (ifp->if_flags & IFF_RUNNING) { 1875 /* 1876 * Multicast list has changed; set the hardware filter 1877 * accordingly. 1878 */ 1879 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1880 } 1881 break; 1882 } 1883 1884 /* Try to get more packets going. */ 1885 sipcom_start(ifp); 1886 1887 sc->sc_if_flags = ifp->if_flags; 1888 splx(s); 1889 return error; 1890 } 1891 1892 /* 1893 * sip_intr: 1894 * 1895 * Interrupt service routine. 1896 */ 1897 static int 1898 sipcom_intr(void *arg) 1899 { 1900 struct sip_softc *sc = arg; 1901 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1902 uint32_t isr; 1903 int handled = 0; 1904 1905 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1906 return 0; 1907 1908 /* Disable interrupts. */ 1909 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1910 1911 for (;;) { 1912 /* Reading clears interrupt. */ 1913 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1914 if ((isr & sc->sc_imr) == 0) 1915 break; 1916 1917 rnd_add_uint32(&sc->rnd_source, isr); 1918 1919 handled = 1; 1920 1921 if ((ifp->if_flags & IFF_RUNNING) == 0) 1922 break; 1923 1924 if (isr & (ISR_RXORN | ISR_RXIDLE | ISR_RXDESC)) { 1925 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1926 1927 /* Grab any new packets. */ 1928 (*sc->sc_rxintr)(sc); 1929 1930 if (isr & ISR_RXORN) { 1931 printf("%s: receive FIFO overrun\n", 1932 device_xname(sc->sc_dev)); 1933 1934 /* XXX adjust rx_drain_thresh? */ 1935 } 1936 1937 if (isr & ISR_RXIDLE) { 1938 printf("%s: receive ring overrun\n", 1939 device_xname(sc->sc_dev)); 1940 1941 /* Get the receive process going again. */ 1942 sip_set_rxdp(sc, 1943 SIP_CDRXADDR(sc, sc->sc_rxptr)); 1944 bus_space_write_4(sc->sc_st, sc->sc_sh, 1945 SIP_CR, CR_RXE); 1946 } 1947 } 1948 1949 if (isr & (ISR_TXURN | ISR_TXDESC | ISR_TXIDLE)) { 1950 #ifdef SIP_EVENT_COUNTERS 1951 if (isr & ISR_TXDESC) 1952 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1953 else if (isr & ISR_TXIDLE) 1954 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1955 #endif 1956 1957 /* Sweep up transmit descriptors. */ 1958 sipcom_txintr(sc); 1959 1960 if (isr & ISR_TXURN) { 1961 uint32_t thresh; 1962 int txfifo_size = (sc->sc_gigabit) 1963 ? DP83820_SIP_TXFIFO_SIZE 1964 : OTHER_SIP_TXFIFO_SIZE; 1965 1966 printf("%s: transmit FIFO underrun", 1967 device_xname(sc->sc_dev)); 1968 thresh = sc->sc_tx_drain_thresh + 1; 1969 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1970 && (thresh * 32) <= (txfifo_size - 1971 (sc->sc_tx_fill_thresh * 32))) { 1972 printf("; increasing Tx drain " 1973 "threshold to %u bytes\n", 1974 thresh * 32); 1975 sc->sc_tx_drain_thresh = thresh; 1976 (void) sipcom_init(ifp); 1977 } else { 1978 (void) sipcom_init(ifp); 1979 printf("\n"); 1980 } 1981 } 1982 } 1983 1984 if (sc->sc_imr & (ISR_PAUSE_END | ISR_PAUSE_ST)) { 1985 if (isr & ISR_PAUSE_ST) { 1986 sc->sc_paused = 1; 1987 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1988 } 1989 if (isr & ISR_PAUSE_END) { 1990 sc->sc_paused = 0; 1991 } 1992 } 1993 1994 if (isr & ISR_HIBERR) { 1995 int want_init = 0; 1996 1997 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1998 1999 #define PRINTERR(bit, str) \ 2000 do { \ 2001 if ((isr & (bit)) != 0) { \ 2002 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 2003 printf("%s: %s\n", \ 2004 device_xname(sc->sc_dev), str); \ 2005 want_init = 1; \ 2006 } \ 2007 } while (/*CONSTCOND*/0) 2008 2009 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 2010 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 2011 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 2012 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 2013 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 2014 /* 2015 * Ignore: 2016 * Tx reset complete 2017 * Rx reset complete 2018 */ 2019 if (want_init) 2020 (void) sipcom_init(ifp); 2021 #undef PRINTERR 2022 } 2023 } 2024 2025 /* Re-enable interrupts. */ 2026 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 2027 2028 /* Try to get more packets going. */ 2029 if_schedule_deferred_start(ifp); 2030 2031 return handled; 2032 } 2033 2034 /* 2035 * sip_txintr: 2036 * 2037 * Helper; handle transmit interrupts. 2038 */ 2039 static void 2040 sipcom_txintr(struct sip_softc *sc) 2041 { 2042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2043 struct sip_txsoft *txs; 2044 uint32_t cmdsts; 2045 2046 /* 2047 * Go through our Tx list and free mbufs for those 2048 * frames which have been transmitted. 2049 */ 2050 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2051 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 2052 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2053 2054 cmdsts = le32toh(sc->sc_txdescs[ 2055 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2056 if (cmdsts & CMDSTS_OWN) 2057 break; 2058 2059 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2060 2061 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 2062 2063 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 2064 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2065 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2066 m_freem(txs->txs_mbuf); 2067 txs->txs_mbuf = NULL; 2068 2069 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2070 2071 /* Check for errors and collisions. */ 2072 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 2073 if (cmdsts & (CMDSTS_Tx_TXA | CMDSTS_Tx_TFU | CMDSTS_Tx_ED | 2074 CMDSTS_Tx_EC)) { 2075 if_statinc_ref(nsr, if_oerrors); 2076 if (cmdsts & CMDSTS_Tx_EC) 2077 if_statadd_ref(nsr, if_collisions, 16); 2078 if (ifp->if_flags & IFF_DEBUG) { 2079 if (cmdsts & CMDSTS_Tx_ED) 2080 printf("%s: excessive deferral\n", 2081 device_xname(sc->sc_dev)); 2082 if (cmdsts & CMDSTS_Tx_EC) 2083 printf("%s: excessive collisions\n", 2084 device_xname(sc->sc_dev)); 2085 } 2086 } else { 2087 /* Packet was transmitted successfully. */ 2088 if_statinc_ref(nsr, if_opackets); 2089 if (CMDSTS_COLLISIONS(cmdsts)) 2090 if_statadd_ref(nsr, if_collisions, 2091 CMDSTS_COLLISIONS(cmdsts)); 2092 } 2093 IF_STAT_PUTREF(ifp); 2094 } 2095 2096 /* 2097 * If there are no more pending transmissions, cancel the watchdog 2098 * timer. 2099 */ 2100 if (txs == NULL) { 2101 ifp->if_timer = 0; 2102 sc->sc_txwin = 0; 2103 } 2104 } 2105 2106 /* 2107 * gsip_rxintr: 2108 * 2109 * Helper; handle receive interrupts on gigabit parts. 2110 */ 2111 static void 2112 gsip_rxintr(struct sip_softc *sc) 2113 { 2114 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2115 struct sip_rxsoft *rxs; 2116 struct mbuf *m; 2117 uint32_t cmdsts, extsts; 2118 int i, len; 2119 2120 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2121 rxs = &sc->sc_rxsoft[i]; 2122 2123 sip_cdrxsync(sc, i, 2124 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2125 2126 cmdsts = 2127 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2128 extsts = 2129 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_extsts_idx]); 2130 len = CMDSTS_SIZE(sc, cmdsts); 2131 2132 /* 2133 * NOTE: OWN is set if owned by _consumer_. We're the 2134 * consumer of the receive ring, so if the bit is clear, 2135 * we have processed all of the packets. 2136 */ 2137 if ((cmdsts & CMDSTS_OWN) == 0) { 2138 /* 2139 * We have processed all of the receive buffers. 2140 */ 2141 break; 2142 } 2143 2144 if (__predict_false(sc->sc_rxdiscard)) { 2145 sip_init_rxdesc(sc, i); 2146 if ((cmdsts & CMDSTS_MORE) == 0) { 2147 /* Reset our state. */ 2148 sc->sc_rxdiscard = 0; 2149 } 2150 continue; 2151 } 2152 2153 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2154 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2155 2156 m = rxs->rxs_mbuf; 2157 2158 /* 2159 * Add a new receive buffer to the ring. 2160 */ 2161 if (sipcom_add_rxbuf(sc, i) != 0) { 2162 /* 2163 * Failed, throw away what we've done so 2164 * far, and discard the rest of the packet. 2165 */ 2166 if_statinc(ifp, if_ierrors); 2167 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2168 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2169 sip_init_rxdesc(sc, i); 2170 if (cmdsts & CMDSTS_MORE) 2171 sc->sc_rxdiscard = 1; 2172 if (sc->sc_rxhead != NULL) 2173 m_freem(sc->sc_rxhead); 2174 sip_rxchain_reset(sc); 2175 continue; 2176 } 2177 2178 sip_rxchain_link(sc, m); 2179 2180 m->m_len = len; 2181 2182 /* 2183 * If this is not the end of the packet, keep 2184 * looking. 2185 */ 2186 if (cmdsts & CMDSTS_MORE) { 2187 sc->sc_rxlen += len; 2188 continue; 2189 } 2190 2191 /* 2192 * Okay, we have the entire packet now. The chip includes 2193 * the FCS, so we need to trim it. 2194 */ 2195 m->m_len -= ETHER_CRC_LEN; 2196 2197 *sc->sc_rxtailp = NULL; 2198 len = m->m_len + sc->sc_rxlen; 2199 m = sc->sc_rxhead; 2200 2201 sip_rxchain_reset(sc); 2202 2203 /* If an error occurred, update stats and drop the packet. */ 2204 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2205 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2206 if_statinc(ifp, if_ierrors); 2207 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2208 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2209 /* Receive overrun handled elsewhere. */ 2210 printf("%s: receive descriptor error\n", 2211 device_xname(sc->sc_dev)); 2212 } 2213 #define PRINTERR(bit, str) \ 2214 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2215 (cmdsts & (bit)) != 0) \ 2216 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2217 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2218 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2219 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2220 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2221 #undef PRINTERR 2222 m_freem(m); 2223 continue; 2224 } 2225 2226 /* 2227 * If the packet is small enough to fit in a 2228 * single header mbuf, allocate one and copy 2229 * the data into it. This greatly reduces 2230 * memory consumption when we receive lots 2231 * of small packets. 2232 */ 2233 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2234 struct mbuf *nm; 2235 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2236 if (nm == NULL) { 2237 if_statinc(ifp, if_ierrors); 2238 m_freem(m); 2239 continue; 2240 } 2241 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2242 nm->m_data += 2; 2243 nm->m_pkthdr.len = nm->m_len = len; 2244 m_copydata(m, 0, len, mtod(nm, void *)); 2245 m_freem(m); 2246 m = nm; 2247 } 2248 #ifndef __NO_STRICT_ALIGNMENT 2249 else { 2250 /* 2251 * The DP83820's receive buffers must be 4-byte 2252 * aligned. But this means that the data after 2253 * the Ethernet header is misaligned. To compensate, 2254 * we have artificially shortened the buffer size 2255 * in the descriptor, and we do an overlapping copy 2256 * of the data two bytes further in (in the first 2257 * buffer of the chain only). 2258 */ 2259 memmove(mtod(m, char *) + 2, mtod(m, void *), 2260 m->m_len); 2261 m->m_data += 2; 2262 } 2263 #endif /* ! __NO_STRICT_ALIGNMENT */ 2264 2265 /* 2266 * If VLANs are enabled, VLAN packets have been unwrapped 2267 * for us. Associate the tag with the packet. 2268 */ 2269 2270 /* 2271 * Again, byte swapping is tricky. Hardware provided 2272 * the tag in the network byte order, but extsts was 2273 * passed through le32toh() in the meantime. On a 2274 * big-endian machine, we need to swap it again. On a 2275 * little-endian machine, we need to convert from the 2276 * network to host byte order. This means that we must 2277 * swap it in any case, so unconditional swap instead 2278 * of htons() is used. 2279 */ 2280 if ((extsts & EXTSTS_VPKT) != 0) { 2281 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2282 } 2283 2284 /* 2285 * Set the incoming checksum information for the 2286 * packet. 2287 */ 2288 if ((extsts & EXTSTS_IPPKT) != 0) { 2289 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2290 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2291 if (extsts & EXTSTS_Rx_IPERR) 2292 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2293 if (extsts & EXTSTS_TCPPKT) { 2294 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2295 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2296 if (extsts & EXTSTS_Rx_TCPERR) 2297 m->m_pkthdr.csum_flags |= 2298 M_CSUM_TCP_UDP_BAD; 2299 } else if (extsts & EXTSTS_UDPPKT) { 2300 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2301 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2302 if (extsts & EXTSTS_Rx_UDPERR) 2303 m->m_pkthdr.csum_flags |= 2304 M_CSUM_TCP_UDP_BAD; 2305 } 2306 } 2307 2308 m_set_rcvif(m, ifp); 2309 m->m_pkthdr.len = len; 2310 2311 /* Pass it on. */ 2312 if_percpuq_enqueue(ifp->if_percpuq, m); 2313 } 2314 2315 /* Update the receive pointer. */ 2316 sc->sc_rxptr = i; 2317 } 2318 2319 /* 2320 * sip_rxintr: 2321 * 2322 * Helper; handle receive interrupts on 10/100 parts. 2323 */ 2324 static void 2325 sip_rxintr(struct sip_softc *sc) 2326 { 2327 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2328 struct sip_rxsoft *rxs; 2329 struct mbuf *m; 2330 uint32_t cmdsts; 2331 int i, len; 2332 2333 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2334 rxs = &sc->sc_rxsoft[i]; 2335 2336 sip_cdrxsync(sc, i, 2337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2338 2339 cmdsts = 2340 le32toh(sc->sc_rxdescs[i].sipd_words[sc->sc_cmdsts_idx]); 2341 2342 /* 2343 * NOTE: OWN is set if owned by _consumer_. We're the 2344 * consumer of the receive ring, so if the bit is clear, 2345 * we have processed all of the packets. 2346 */ 2347 if ((cmdsts & CMDSTS_OWN) == 0) { 2348 /* 2349 * We have processed all of the receive buffers. 2350 */ 2351 break; 2352 } 2353 2354 /* If any collisions were seen on the wire, count one. */ 2355 if (cmdsts & CMDSTS_Rx_COL) 2356 if_statinc(ifp, if_collisions); 2357 2358 /* 2359 * If an error occurred, update stats, clear the status 2360 * word, and leave the packet buffer in place. It will 2361 * simply be reused the next time the ring comes around. 2362 */ 2363 if (cmdsts & (CMDSTS_Rx_RXA | CMDSTS_Rx_RUNT | 2364 CMDSTS_Rx_ISE | CMDSTS_Rx_CRCE | CMDSTS_Rx_FAE)) { 2365 if_statinc(ifp, if_ierrors); 2366 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2367 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2368 /* Receive overrun handled elsewhere. */ 2369 printf("%s: receive descriptor error\n", 2370 device_xname(sc->sc_dev)); 2371 } 2372 #define PRINTERR(bit, str) \ 2373 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2374 (cmdsts & (bit)) != 0) \ 2375 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2376 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2377 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2378 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2379 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2380 #undef PRINTERR 2381 sip_init_rxdesc(sc, i); 2382 continue; 2383 } 2384 2385 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2386 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2387 2388 /* 2389 * No errors; receive the packet. Note, the SiS 900 2390 * includes the CRC with every packet. 2391 */ 2392 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2393 2394 #ifdef __NO_STRICT_ALIGNMENT 2395 /* 2396 * If the packet is small enough to fit in a 2397 * single header mbuf, allocate one and copy 2398 * the data into it. This greatly reduces 2399 * memory consumption when we receive lots 2400 * of small packets. 2401 * 2402 * Otherwise, we add a new buffer to the receive 2403 * chain. If this fails, we drop the packet and 2404 * recycle the old buffer. 2405 */ 2406 if (sip_copy_small != 0 && len <= MHLEN) { 2407 MGETHDR(m, M_DONTWAIT, MT_DATA); 2408 if (m == NULL) 2409 goto dropit; 2410 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2411 memcpy(mtod(m, void *), 2412 mtod(rxs->rxs_mbuf, void *), len); 2413 sip_init_rxdesc(sc, i); 2414 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2415 rxs->rxs_dmamap->dm_mapsize, 2416 BUS_DMASYNC_PREREAD); 2417 } else { 2418 m = rxs->rxs_mbuf; 2419 if (sipcom_add_rxbuf(sc, i) != 0) { 2420 dropit: 2421 if_statinc(ifp, if_ierrors); 2422 sip_init_rxdesc(sc, i); 2423 bus_dmamap_sync(sc->sc_dmat, 2424 rxs->rxs_dmamap, 0, 2425 rxs->rxs_dmamap->dm_mapsize, 2426 BUS_DMASYNC_PREREAD); 2427 continue; 2428 } 2429 } 2430 #else 2431 /* 2432 * The SiS 900's receive buffers must be 4-byte aligned. 2433 * But this means that the data after the Ethernet header 2434 * is misaligned. We must allocate a new buffer and 2435 * copy the data, shifted forward 2 bytes. 2436 */ 2437 MGETHDR(m, M_DONTWAIT, MT_DATA); 2438 if (m == NULL) { 2439 dropit: 2440 if_statinc(ifp, if_ierrors); 2441 sip_init_rxdesc(sc, i); 2442 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2443 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2444 continue; 2445 } 2446 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2447 if (len > (MHLEN - 2)) { 2448 MCLGET(m, M_DONTWAIT); 2449 if ((m->m_flags & M_EXT) == 0) { 2450 m_freem(m); 2451 goto dropit; 2452 } 2453 } 2454 m->m_data += 2; 2455 2456 /* 2457 * Note that we use clusters for incoming frames, so the 2458 * buffer is virtually contiguous. 2459 */ 2460 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2461 2462 /* Allow the receive descriptor to continue using its mbuf. */ 2463 sip_init_rxdesc(sc, i); 2464 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2465 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2466 #endif /* __NO_STRICT_ALIGNMENT */ 2467 2468 m_set_rcvif(m, ifp); 2469 m->m_pkthdr.len = m->m_len = len; 2470 2471 /* Pass it on. */ 2472 if_percpuq_enqueue(ifp->if_percpuq, m); 2473 } 2474 2475 /* Update the receive pointer. */ 2476 sc->sc_rxptr = i; 2477 } 2478 2479 /* 2480 * sip_tick: 2481 * 2482 * One second timer, used to tick the MII. 2483 */ 2484 static void 2485 sipcom_tick(void *arg) 2486 { 2487 struct sip_softc *sc = arg; 2488 int s; 2489 2490 s = splnet(); 2491 #ifdef SIP_EVENT_COUNTERS 2492 if (sc->sc_gigabit) { 2493 /* Read PAUSE related counts from MIB registers. */ 2494 sc->sc_ev_rxpause.ev_count += 2495 bus_space_read_4(sc->sc_st, sc->sc_sh, 2496 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2497 sc->sc_ev_txpause.ev_count += 2498 bus_space_read_4(sc->sc_st, sc->sc_sh, 2499 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2500 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2501 } 2502 #endif /* SIP_EVENT_COUNTERS */ 2503 mii_tick(&sc->sc_mii); 2504 splx(s); 2505 2506 callout_schedule(&sc->sc_tick_ch, hz); 2507 } 2508 2509 /* 2510 * sip_reset: 2511 * 2512 * Perform a soft reset on the SiS 900. 2513 */ 2514 static bool 2515 sipcom_reset(struct sip_softc *sc) 2516 { 2517 bus_space_tag_t st = sc->sc_st; 2518 bus_space_handle_t sh = sc->sc_sh; 2519 int i; 2520 2521 bus_space_write_4(st, sh, SIP_IER, 0); 2522 bus_space_write_4(st, sh, SIP_IMR, 0); 2523 bus_space_write_4(st, sh, SIP_RFCR, 0); 2524 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2525 2526 for (i = 0; i < SIP_TIMEOUT; i++) { 2527 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2528 break; 2529 delay(2); 2530 } 2531 2532 if (i == SIP_TIMEOUT) { 2533 printf("%s: reset failed to complete\n", 2534 device_xname(sc->sc_dev)); 2535 return false; 2536 } 2537 2538 delay(1000); 2539 2540 if (sc->sc_gigabit) { 2541 /* 2542 * Set the general purpose I/O bits. Do it here in case we 2543 * need to have GPIO set up to talk to the media interface. 2544 */ 2545 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2546 delay(1000); 2547 } 2548 return true; 2549 } 2550 2551 static void 2552 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2553 { 2554 uint32_t reg; 2555 bus_space_tag_t st = sc->sc_st; 2556 bus_space_handle_t sh = sc->sc_sh; 2557 /* 2558 * Initialize the VLAN/IP receive control register. 2559 * We enable checksum computation on all incoming 2560 * packets, and do not reject packets w/ bad checksums. 2561 */ 2562 reg = 0; 2563 if (capenable & 2564 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 2565 reg |= VRCR_IPEN; 2566 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2567 reg |= VRCR_VTDEN | VRCR_VTREN; 2568 bus_space_write_4(st, sh, SIP_VRCR, reg); 2569 2570 /* 2571 * Initialize the VLAN/IP transmit control register. 2572 * We enable outgoing checksum computation on a 2573 * per-packet basis. 2574 */ 2575 reg = 0; 2576 if (capenable & 2577 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 2578 reg |= VTCR_PPCHK; 2579 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2580 reg |= VTCR_VPPTI; 2581 bus_space_write_4(st, sh, SIP_VTCR, reg); 2582 2583 /* 2584 * If we're using VLANs, initialize the VLAN data register. 2585 * To understand why we bswap the VLAN Ethertype, see section 2586 * 4.2.36 of the DP83820 manual. 2587 */ 2588 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2589 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2590 } 2591 2592 /* 2593 * sip_init: [ ifnet interface function ] 2594 * 2595 * Initialize the interface. Must be called at splnet(). 2596 */ 2597 static int 2598 sipcom_init(struct ifnet *ifp) 2599 { 2600 struct sip_softc *sc = ifp->if_softc; 2601 bus_space_tag_t st = sc->sc_st; 2602 bus_space_handle_t sh = sc->sc_sh; 2603 struct sip_txsoft *txs; 2604 struct sip_rxsoft *rxs; 2605 int i, error = 0; 2606 2607 if (device_is_active(sc->sc_dev)) { 2608 /* 2609 * Cancel any pending I/O. 2610 */ 2611 sipcom_stop(ifp, 0); 2612 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2613 !device_is_active(sc->sc_dev)) 2614 return 0; 2615 2616 /* 2617 * Reset the chip to a known state. 2618 */ 2619 if (!sipcom_reset(sc)) 2620 return EBUSY; 2621 2622 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2623 /* 2624 * DP83815 manual, page 78: 2625 * 4.4 Recommended Registers Configuration 2626 * For optimum performance of the DP83815, version noted 2627 * as DP83815CVNG (SRR = 203h), the listed register 2628 * modifications must be followed in sequence... 2629 * 2630 * It's not clear if this should be 302h or 203h because that 2631 * chip name is listed as SRR 302h in the description of the 2632 * SRR register. However, my revision 302h DP83815 on the 2633 * Netgear FA311 purchased in 02/2001 needs these settings 2634 * to avoid tons of errors in AcceptPerfectMatch (non- 2635 * IFF_PROMISC) mode. I do not know if other revisions need 2636 * this set or not. [briggs -- 09 March 2001] 2637 * 2638 * Note that only the low-order 12 bits of 0xe4 are documented 2639 * and that this sets reserved bits in that register. 2640 */ 2641 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2642 2643 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2644 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2645 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2646 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2647 2648 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2649 } 2650 2651 /* Initialize the transmit descriptor ring. */ 2652 sip_init_txring(sc); 2653 2654 /* 2655 * Initialize the transmit job descriptors. 2656 */ 2657 SIMPLEQ_INIT(&sc->sc_txfreeq); 2658 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2659 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2660 txs = &sc->sc_txsoft[i]; 2661 txs->txs_mbuf = NULL; 2662 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2663 } 2664 2665 /* 2666 * Initialize the receive descriptor and receive job 2667 * descriptor rings. 2668 */ 2669 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2670 rxs = &sc->sc_rxsoft[i]; 2671 if (rxs->rxs_mbuf == NULL) { 2672 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2673 printf("%s: unable to allocate or map rx " 2674 "buffer %d, error = %d\n", 2675 device_xname(sc->sc_dev), i, error); 2676 /* 2677 * XXX Should attempt to run with fewer receive 2678 * XXX buffers instead of just failing. 2679 */ 2680 sipcom_rxdrain(sc); 2681 goto out; 2682 } 2683 } else 2684 sip_init_rxdesc(sc, i); 2685 } 2686 sc->sc_rxptr = 0; 2687 sc->sc_rxdiscard = 0; 2688 sip_rxchain_reset(sc); 2689 2690 /* 2691 * Set the configuration register; it's already initialized 2692 * in sip_attach(). 2693 */ 2694 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2695 2696 /* 2697 * Initialize the prototype TXCFG register. 2698 */ 2699 if (sc->sc_gigabit) { 2700 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2701 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2702 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2703 SIP_SIS900_REV(sc, SIS_REV_960) || 2704 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2705 (sc->sc_cfg & CFG_EDBMASTEN)) { 2706 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2707 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2708 } else { 2709 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2710 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2711 } 2712 2713 sc->sc_txcfg |= TXCFG_ATP | 2714 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2715 sc->sc_tx_drain_thresh; 2716 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2717 2718 /* 2719 * Initialize the receive drain threshold if we have never 2720 * done so. 2721 */ 2722 if (sc->sc_rx_drain_thresh == 0) { 2723 /* 2724 * XXX This value should be tuned. This is set to the 2725 * maximum of 248 bytes, and we may be able to improve 2726 * performance by decreasing it (although we should never 2727 * set this value lower than 2; 14 bytes are required to 2728 * filter the packet). 2729 */ 2730 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2731 } 2732 2733 /* 2734 * Initialize the prototype RXCFG register. 2735 */ 2736 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2737 /* 2738 * Accept long packets (including FCS) so we can handle 2739 * 802.1q-tagged frames and jumbo frames properly. 2740 */ 2741 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2742 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2743 sc->sc_rxcfg |= RXCFG_ALP; 2744 2745 /* 2746 * Checksum offloading is disabled if the user selects an MTU 2747 * larger than 8109. (FreeBSD says 8152, but there is emperical 2748 * evidence that >8109 does not work on some boards, such as the 2749 * Planex GN-1000TE). 2750 */ 2751 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2752 (ifp->if_capenable & 2753 (IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2754 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2755 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx))) { 2756 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2757 "disabled.\n", device_xname(sc->sc_dev)); 2758 ifp->if_capenable &= 2759 ~(IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 2760 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 2761 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx); 2762 ifp->if_csum_flags_tx = 0; 2763 ifp->if_csum_flags_rx = 0; 2764 } 2765 2766 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2767 2768 if (sc->sc_gigabit) 2769 sipcom_dp83820_init(sc, ifp->if_capenable); 2770 2771 /* 2772 * Give the transmit and receive rings to the chip. 2773 */ 2774 sip_set_txdp(sc, SIP_CDTXADDR(sc, sc->sc_txnext)); 2775 sip_set_rxdp(sc, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2776 2777 /* 2778 * Initialize the interrupt mask. 2779 */ 2780 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2781 sc->sc_bits.b_isr_sserr | 2782 sc->sc_bits.b_isr_rmabt | 2783 sc->sc_bits.b_isr_rtabt | 2784 ISR_RXSOVR | ISR_TXURN | ISR_TXDESC | ISR_TXIDLE | ISR_RXORN | 2785 ISR_RXIDLE | ISR_RXDESC; 2786 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2787 2788 /* Set up the receive filter. */ 2789 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2790 2791 /* 2792 * Tune sc_rx_flow_thresh. 2793 * XXX "More than 8KB" is too short for jumbo frames. 2794 * XXX TODO: Threshold value should be user-settable. 2795 */ 2796 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2797 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2798 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2799 2800 /* 2801 * Set the current media. Do this after initializing the prototype 2802 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2803 * control. 2804 */ 2805 if ((error = ether_mediachange(ifp)) != 0) 2806 goto out; 2807 2808 /* 2809 * Set the interrupt hold-off timer to 100us. 2810 */ 2811 if (sc->sc_gigabit) 2812 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2813 2814 /* 2815 * Enable interrupts. 2816 */ 2817 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2818 2819 /* 2820 * Start the transmit and receive processes. 2821 */ 2822 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2823 2824 /* 2825 * Start the one second MII clock. 2826 */ 2827 callout_schedule(&sc->sc_tick_ch, hz); 2828 2829 /* 2830 * ...all done! 2831 */ 2832 ifp->if_flags |= IFF_RUNNING; 2833 sc->sc_if_flags = ifp->if_flags; 2834 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2835 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2836 sc->sc_prev.if_capenable = ifp->if_capenable; 2837 2838 out: 2839 if (error) 2840 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2841 return error; 2842 } 2843 2844 /* 2845 * sip_drain: 2846 * 2847 * Drain the receive queue. 2848 */ 2849 static void 2850 sipcom_rxdrain(struct sip_softc *sc) 2851 { 2852 struct sip_rxsoft *rxs; 2853 int i; 2854 2855 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2856 rxs = &sc->sc_rxsoft[i]; 2857 if (rxs->rxs_mbuf != NULL) { 2858 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2859 m_freem(rxs->rxs_mbuf); 2860 rxs->rxs_mbuf = NULL; 2861 } 2862 } 2863 } 2864 2865 /* 2866 * sip_stop: [ ifnet interface function ] 2867 * 2868 * Stop transmission on the interface. 2869 */ 2870 static void 2871 sipcom_stop(struct ifnet *ifp, int disable) 2872 { 2873 struct sip_softc *sc = ifp->if_softc; 2874 bus_space_tag_t st = sc->sc_st; 2875 bus_space_handle_t sh = sc->sc_sh; 2876 struct sip_txsoft *txs; 2877 uint32_t cmdsts = 0; /* DEBUG */ 2878 2879 /* 2880 * Stop the one second clock. 2881 */ 2882 callout_stop(&sc->sc_tick_ch); 2883 2884 /* Down the MII. */ 2885 mii_down(&sc->sc_mii); 2886 2887 if (device_is_active(sc->sc_dev)) { 2888 /* 2889 * Disable interrupts. 2890 */ 2891 bus_space_write_4(st, sh, SIP_IER, 0); 2892 2893 /* 2894 * Stop receiver and transmitter. 2895 */ 2896 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2897 } 2898 2899 /* 2900 * Release any queued transmit buffers. 2901 */ 2902 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2903 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2904 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2905 (sc->sc_txdescs[ 2906 txs->txs_lastdesc].sipd_words[ 2907 sc->sc_cmdsts_idx] & htole32(CMDSTS_INTR)) == 0) 2908 printf("%s: sip_stop: last descriptor does not " 2909 "have INTR bit set\n", device_xname(sc->sc_dev)); 2910 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2911 #ifdef DIAGNOSTIC 2912 if (txs->txs_mbuf == NULL) { 2913 printf("%s: dirty txsoft with no mbuf chain\n", 2914 device_xname(sc->sc_dev)); 2915 panic("sip_stop"); 2916 } 2917 #endif 2918 cmdsts |= /* DEBUG */ 2919 le32toh(sc->sc_txdescs[ 2920 txs->txs_lastdesc].sipd_words[sc->sc_cmdsts_idx]); 2921 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2922 m_freem(txs->txs_mbuf); 2923 txs->txs_mbuf = NULL; 2924 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2925 } 2926 2927 /* 2928 * Mark the interface down and cancel the watchdog timer. 2929 */ 2930 ifp->if_flags &= ~IFF_RUNNING; 2931 ifp->if_timer = 0; 2932 2933 if (disable) 2934 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2935 2936 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2937 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2938 printf("%s: sip_stop: no INTR bits set in dirty tx " 2939 "descriptors\n", device_xname(sc->sc_dev)); 2940 } 2941 2942 /* 2943 * sip_read_eeprom: 2944 * 2945 * Read data from the serial EEPROM. 2946 */ 2947 static void 2948 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2949 uint16_t *data) 2950 { 2951 bus_space_tag_t st = sc->sc_st; 2952 bus_space_handle_t sh = sc->sc_sh; 2953 uint16_t reg; 2954 int i, x; 2955 2956 for (i = 0; i < wordcnt; i++) { 2957 /* Send CHIP SELECT. */ 2958 reg = EROMAR_EECS; 2959 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2960 2961 /* Shift in the READ opcode. */ 2962 for (x = 3; x > 0; x--) { 2963 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2964 reg |= EROMAR_EEDI; 2965 else 2966 reg &= ~EROMAR_EEDI; 2967 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2968 bus_space_write_4(st, sh, SIP_EROMAR, 2969 reg | EROMAR_EESK); 2970 delay(4); 2971 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2972 delay(4); 2973 } 2974 2975 /* Shift in address. */ 2976 for (x = 6; x > 0; x--) { 2977 if ((word + i) & (1 << (x - 1))) 2978 reg |= EROMAR_EEDI; 2979 else 2980 reg &= ~EROMAR_EEDI; 2981 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2982 bus_space_write_4(st, sh, SIP_EROMAR, 2983 reg | EROMAR_EESK); 2984 delay(4); 2985 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2986 delay(4); 2987 } 2988 2989 /* Shift out data. */ 2990 reg = EROMAR_EECS; 2991 data[i] = 0; 2992 for (x = 16; x > 0; x--) { 2993 bus_space_write_4(st, sh, SIP_EROMAR, 2994 reg | EROMAR_EESK); 2995 delay(4); 2996 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2997 data[i] |= (1 << (x - 1)); 2998 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2999 delay(4); 3000 } 3001 3002 /* Clear CHIP SELECT. */ 3003 bus_space_write_4(st, sh, SIP_EROMAR, 0); 3004 delay(4); 3005 } 3006 } 3007 3008 /* 3009 * sipcom_add_rxbuf: 3010 * 3011 * Add a receive buffer to the indicated descriptor. 3012 */ 3013 static int 3014 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 3015 { 3016 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 3017 struct mbuf *m; 3018 int error; 3019 3020 MGETHDR(m, M_DONTWAIT, MT_DATA); 3021 if (m == NULL) 3022 return ENOBUFS; 3023 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 3024 3025 MCLGET(m, M_DONTWAIT); 3026 if ((m->m_flags & M_EXT) == 0) { 3027 m_freem(m); 3028 return ENOBUFS; 3029 } 3030 3031 /* XXX I don't believe this is necessary. --dyoung */ 3032 if (sc->sc_gigabit) 3033 m->m_len = sc->sc_parm->p_rxbuf_len; 3034 3035 if (rxs->rxs_mbuf != NULL) 3036 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 3037 3038 rxs->rxs_mbuf = m; 3039 3040 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 3041 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 3042 BUS_DMA_READ | BUS_DMA_NOWAIT); 3043 if (error) { 3044 printf("%s: can't load rx DMA map %d, error = %d\n", 3045 device_xname(sc->sc_dev), idx, error); 3046 panic("%s", __func__); /* XXX */ 3047 } 3048 3049 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3050 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3051 3052 sip_init_rxdesc(sc, idx); 3053 3054 return 0; 3055 } 3056 3057 /* 3058 * sip_sis900_set_filter: 3059 * 3060 * Set up the receive filter. 3061 */ 3062 static void 3063 sipcom_sis900_set_filter(struct sip_softc *sc) 3064 { 3065 bus_space_tag_t st = sc->sc_st; 3066 bus_space_handle_t sh = sc->sc_sh; 3067 struct ethercom *ec = &sc->sc_ethercom; 3068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3069 struct ether_multi *enm; 3070 const uint8_t *cp; 3071 struct ether_multistep step; 3072 uint32_t crc, mchash[16]; 3073 3074 /* 3075 * Initialize the prototype RFCR. 3076 */ 3077 sc->sc_rfcr = RFCR_RFEN; 3078 if (ifp->if_flags & IFF_BROADCAST) 3079 sc->sc_rfcr |= RFCR_AAB; 3080 if (ifp->if_flags & IFF_PROMISC) { 3081 sc->sc_rfcr |= RFCR_AAP; 3082 goto allmulti; 3083 } 3084 3085 /* 3086 * Set up the multicast address filter by passing all multicast 3087 * addresses through a CRC generator, and then using the high-order 3088 * 6 bits as an index into the 128 bit multicast hash table (only 3089 * the lower 16 bits of each 32 bit multicast hash register are 3090 * valid). The high order bits select the register, while the 3091 * rest of the bits select the bit within the register. 3092 */ 3093 3094 memset(mchash, 0, sizeof(mchash)); 3095 3096 /* 3097 * SiS900 (at least SiS963) requires us to register the address of 3098 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3099 */ 3100 crc = 0x0ed423f9; 3101 3102 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3103 SIP_SIS900_REV(sc, SIS_REV_960) || 3104 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3105 /* Just want the 8 most significant bits. */ 3106 crc >>= 24; 3107 } else { 3108 /* Just want the 7 most significant bits. */ 3109 crc >>= 25; 3110 } 3111 3112 /* Set the corresponding bit in the hash table. */ 3113 mchash[crc >> 4] |= 1 << (crc & 0xf); 3114 3115 ETHER_LOCK(ec); 3116 ETHER_FIRST_MULTI(step, ec, enm); 3117 while (enm != NULL) { 3118 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3119 /* 3120 * We must listen to a range of multicast addresses. 3121 * For now, just accept all multicasts, rather than 3122 * trying to set only those filter bits needed to match 3123 * the range. (At this time, the only use of address 3124 * ranges is for IP multicast routing, for which the 3125 * range is big enough to require all bits set.) 3126 */ 3127 ETHER_UNLOCK(ec); 3128 goto allmulti; 3129 } 3130 3131 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3132 3133 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3134 SIP_SIS900_REV(sc, SIS_REV_960) || 3135 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3136 /* Just want the 8 most significant bits. */ 3137 crc >>= 24; 3138 } else { 3139 /* Just want the 7 most significant bits. */ 3140 crc >>= 25; 3141 } 3142 3143 /* Set the corresponding bit in the hash table. */ 3144 mchash[crc >> 4] |= 1 << (crc & 0xf); 3145 3146 ETHER_NEXT_MULTI(step, enm); 3147 } 3148 ETHER_UNLOCK(ec); 3149 3150 ifp->if_flags &= ~IFF_ALLMULTI; 3151 goto setit; 3152 3153 allmulti: 3154 ifp->if_flags |= IFF_ALLMULTI; 3155 sc->sc_rfcr |= RFCR_AAM; 3156 3157 setit: 3158 #define FILTER_EMIT(addr, data) \ 3159 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3160 delay(1); \ 3161 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3162 delay(1) 3163 3164 /* 3165 * Disable receive filter, and program the node address. 3166 */ 3167 cp = CLLADDR(ifp->if_sadl); 3168 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3169 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3170 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3171 3172 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3173 /* 3174 * Program the multicast hash table. 3175 */ 3176 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3177 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3178 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3179 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3180 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3181 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3182 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3183 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3184 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3185 SIP_SIS900_REV(sc, SIS_REV_960) || 3186 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3187 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3188 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3189 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3190 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3191 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3192 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3193 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3194 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3195 } 3196 } 3197 #undef FILTER_EMIT 3198 3199 /* 3200 * Re-enable the receiver filter. 3201 */ 3202 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3203 } 3204 3205 /* 3206 * sip_dp83815_set_filter: 3207 * 3208 * Set up the receive filter. 3209 */ 3210 static void 3211 sipcom_dp83815_set_filter(struct sip_softc *sc) 3212 { 3213 bus_space_tag_t st = sc->sc_st; 3214 bus_space_handle_t sh = sc->sc_sh; 3215 struct ethercom *ec = &sc->sc_ethercom; 3216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3217 struct ether_multi *enm; 3218 const uint8_t *cp; 3219 struct ether_multistep step; 3220 uint32_t crc, hash, slot, bit; 3221 #define MCHASH_NWORDS_83820 128 3222 #define MCHASH_NWORDS_83815 32 3223 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3224 uint16_t mchash[MCHASH_NWORDS]; 3225 int i; 3226 3227 /* 3228 * Initialize the prototype RFCR. 3229 * Enable the receive filter, and accept on 3230 * Perfect (destination address) Match 3231 * If IFF_BROADCAST, also accept all broadcast packets. 3232 * If IFF_PROMISC, accept all unicast packets (and later, set 3233 * IFF_ALLMULTI and accept all multicast, too). 3234 */ 3235 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3236 if (ifp->if_flags & IFF_BROADCAST) 3237 sc->sc_rfcr |= RFCR_AAB; 3238 if (ifp->if_flags & IFF_PROMISC) { 3239 sc->sc_rfcr |= RFCR_AAP; 3240 goto allmulti; 3241 } 3242 3243 /* 3244 * Set up the DP83820/DP83815 multicast address filter by 3245 * passing all multicast addresses through a CRC generator, 3246 * and then using the high-order 11/9 bits as an index into 3247 * the 2048/512 bit multicast hash table. The high-order 3248 * 7/5 bits select the slot, while the low-order 4 bits 3249 * select the bit within the slot. Note that only the low 3250 * 16-bits of each filter word are used, and there are 3251 * 128/32 filter words. 3252 */ 3253 3254 memset(mchash, 0, sizeof(mchash)); 3255 3256 ifp->if_flags &= ~IFF_ALLMULTI; 3257 ETHER_FIRST_MULTI(step, ec, enm); 3258 if (enm == NULL) 3259 goto setit; 3260 while (enm != NULL) { 3261 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3262 /* 3263 * We must listen to a range of multicast addresses. 3264 * For now, just accept all multicasts, rather than 3265 * trying to set only those filter bits needed to match 3266 * the range. (At this time, the only use of address 3267 * ranges is for IP multicast routing, for which the 3268 * range is big enough to require all bits set.) 3269 */ 3270 goto allmulti; 3271 } 3272 3273 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3274 3275 if (sc->sc_gigabit) { 3276 /* Just want the 11 most significant bits. */ 3277 hash = crc >> 21; 3278 } else { 3279 /* Just want the 9 most significant bits. */ 3280 hash = crc >> 23; 3281 } 3282 3283 slot = hash >> 4; 3284 bit = hash & 0xf; 3285 3286 /* Set the corresponding bit in the hash table. */ 3287 mchash[slot] |= 1 << bit; 3288 3289 ETHER_NEXT_MULTI(step, enm); 3290 } 3291 sc->sc_rfcr |= RFCR_MHEN; 3292 goto setit; 3293 3294 allmulti: 3295 ifp->if_flags |= IFF_ALLMULTI; 3296 sc->sc_rfcr |= RFCR_AAM; 3297 3298 setit: 3299 #define FILTER_EMIT(addr, data) \ 3300 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3301 delay(1); \ 3302 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3303 delay(1) 3304 3305 /* 3306 * Disable receive filter, and program the node address. 3307 */ 3308 cp = CLLADDR(ifp->if_sadl); 3309 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3310 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3311 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3312 3313 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3314 int nwords = 3315 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3316 /* 3317 * Program the multicast hash table. 3318 */ 3319 for (i = 0; i < nwords; i++) { 3320 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3321 } 3322 } 3323 #undef FILTER_EMIT 3324 #undef MCHASH_NWORDS 3325 #undef MCHASH_NWORDS_83815 3326 #undef MCHASH_NWORDS_83820 3327 3328 /* 3329 * Re-enable the receiver filter. 3330 */ 3331 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3332 } 3333 3334 /* 3335 * sip_dp83820_mii_readreg: [mii interface function] 3336 * 3337 * Read a PHY register on the MII of the DP83820. 3338 */ 3339 static int 3340 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3341 { 3342 struct sip_softc *sc = device_private(self); 3343 3344 if (sc->sc_cfg & CFG_TBI_EN) { 3345 bus_addr_t tbireg; 3346 3347 if (phy != 0) 3348 return -1; 3349 3350 switch (reg) { 3351 case MII_BMCR: tbireg = SIP_TBICR; break; 3352 case MII_BMSR: tbireg = SIP_TBISR; break; 3353 case MII_ANAR: tbireg = SIP_TANAR; break; 3354 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3355 case MII_ANER: tbireg = SIP_TANER; break; 3356 case MII_EXTSR: 3357 /* 3358 * Don't even bother reading the TESR register. 3359 * The manual documents that the device has 3360 * 1000baseX full/half capability, but the 3361 * register itself seems read back 0 on some 3362 * boards. Just hard-code the result. 3363 */ 3364 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3365 return 0; 3366 3367 default: 3368 return 0; 3369 } 3370 3371 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3372 if (tbireg == SIP_TBISR) { 3373 /* LINK and ACOMP are switched! */ 3374 int sr = *val; 3375 3376 *val = 0; 3377 if (sr & TBISR_MR_LINK_STATUS) 3378 *val |= BMSR_LINK; 3379 if (sr & TBISR_MR_AN_COMPLETE) 3380 *val |= BMSR_ACOMP; 3381 3382 /* 3383 * The manual claims this register reads back 0 3384 * on hard and soft reset. But we want to let 3385 * the gentbi driver know that we support auto- 3386 * negotiation, so hard-code this bit in the 3387 * result. 3388 */ 3389 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3390 } 3391 3392 return 0; 3393 } 3394 3395 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3396 val); 3397 } 3398 3399 /* 3400 * sip_dp83820_mii_writereg: [mii interface function] 3401 * 3402 * Write a PHY register on the MII of the DP83820. 3403 */ 3404 static int 3405 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3406 { 3407 struct sip_softc *sc = device_private(self); 3408 3409 if (sc->sc_cfg & CFG_TBI_EN) { 3410 bus_addr_t tbireg; 3411 3412 if (phy != 0) 3413 return -1; 3414 3415 switch (reg) { 3416 case MII_BMCR: tbireg = SIP_TBICR; break; 3417 case MII_ANAR: tbireg = SIP_TANAR; break; 3418 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3419 default: 3420 return 0; 3421 } 3422 3423 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3424 return 0; 3425 } 3426 3427 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3428 val); 3429 } 3430 3431 /* 3432 * sip_dp83820_mii_statchg: [mii interface function] 3433 * 3434 * Callback from MII layer when media changes. 3435 */ 3436 static void 3437 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3438 { 3439 struct sip_softc *sc = ifp->if_softc; 3440 struct mii_data *mii = &sc->sc_mii; 3441 uint32_t cfg, pcr; 3442 3443 /* 3444 * Get flow control negotiation result. 3445 */ 3446 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3447 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3448 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3449 mii->mii_media_active &= ~IFM_ETH_FMASK; 3450 } 3451 3452 /* 3453 * Update TXCFG for full-duplex operation. 3454 */ 3455 if ((mii->mii_media_active & IFM_FDX) != 0) 3456 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3457 else 3458 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3459 3460 /* 3461 * Update RXCFG for full-duplex or loopback. 3462 */ 3463 if ((mii->mii_media_active & IFM_FDX) != 0 || 3464 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3465 sc->sc_rxcfg |= RXCFG_ATX; 3466 else 3467 sc->sc_rxcfg &= ~RXCFG_ATX; 3468 3469 /* 3470 * Update CFG for MII/GMII. 3471 */ 3472 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3473 cfg = sc->sc_cfg | CFG_MODE_1000; 3474 else 3475 cfg = sc->sc_cfg; 3476 3477 /* 3478 * 802.3x flow control. 3479 */ 3480 pcr = 0; 3481 if (sc->sc_flowflags & IFM_FLOW) { 3482 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3483 pcr |= sc->sc_rx_flow_thresh; 3484 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3485 pcr |= PCR_PSEN | PCR_PS_MCAST; 3486 } 3487 3488 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3489 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3490 sc->sc_txcfg); 3491 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3492 sc->sc_rxcfg); 3493 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3494 } 3495 3496 /* 3497 * sip_mii_bitbang_read: [mii bit-bang interface function] 3498 * 3499 * Read the MII serial port for the MII bit-bang module. 3500 */ 3501 static uint32_t 3502 sipcom_mii_bitbang_read(device_t self) 3503 { 3504 struct sip_softc *sc = device_private(self); 3505 3506 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3507 } 3508 3509 /* 3510 * sip_mii_bitbang_write: [mii big-bang interface function] 3511 * 3512 * Write the MII serial port for the MII bit-bang module. 3513 */ 3514 static void 3515 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3516 { 3517 struct sip_softc *sc = device_private(self); 3518 3519 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3520 } 3521 3522 /* 3523 * sip_sis900_mii_readreg: [mii interface function] 3524 * 3525 * Read a PHY register on the MII. 3526 */ 3527 static int 3528 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3529 { 3530 struct sip_softc *sc = device_private(self); 3531 uint32_t enphy; 3532 3533 /* 3534 * The PHY of recent SiS chipsets is accessed through bitbang 3535 * operations. 3536 */ 3537 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3538 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3539 phy, reg, val); 3540 3541 #ifndef SIS900_MII_RESTRICT 3542 /* 3543 * The SiS 900 has only an internal PHY on the MII. Only allow 3544 * MII address 0. 3545 */ 3546 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3547 return -1; 3548 #endif 3549 3550 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3551 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3552 ENPHY_RWCMD | ENPHY_ACCESS); 3553 do { 3554 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3555 } while (enphy & ENPHY_ACCESS); 3556 3557 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3558 return 0; 3559 } 3560 3561 /* 3562 * sip_sis900_mii_writereg: [mii interface function] 3563 * 3564 * Write a PHY register on the MII. 3565 */ 3566 static int 3567 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3568 { 3569 struct sip_softc *sc = device_private(self); 3570 uint32_t enphy; 3571 3572 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3573 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3574 phy, reg, val); 3575 } 3576 3577 #ifndef SIS900_MII_RESTRICT 3578 /* 3579 * The SiS 900 has only an internal PHY on the MII. Only allow 3580 * MII address 0. 3581 */ 3582 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3583 return -1; 3584 #endif 3585 3586 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3587 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3588 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3589 do { 3590 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3591 } while (enphy & ENPHY_ACCESS); 3592 3593 return 0; 3594 } 3595 3596 /* 3597 * sip_sis900_mii_statchg: [mii interface function] 3598 * 3599 * Callback from MII layer when media changes. 3600 */ 3601 static void 3602 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3603 { 3604 struct sip_softc *sc = ifp->if_softc; 3605 struct mii_data *mii = &sc->sc_mii; 3606 uint32_t flowctl; 3607 3608 /* 3609 * Get flow control negotiation result. 3610 */ 3611 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3612 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3613 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3614 mii->mii_media_active &= ~IFM_ETH_FMASK; 3615 } 3616 3617 /* 3618 * Update TXCFG for full-duplex operation. 3619 */ 3620 if ((mii->mii_media_active & IFM_FDX) != 0) 3621 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3622 else 3623 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3624 3625 /* 3626 * Update RXCFG for full-duplex or loopback. 3627 */ 3628 if ((mii->mii_media_active & IFM_FDX) != 0 || 3629 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3630 sc->sc_rxcfg |= RXCFG_ATX; 3631 else 3632 sc->sc_rxcfg &= ~RXCFG_ATX; 3633 3634 /* 3635 * Update IMR for use of 802.3x flow control. 3636 */ 3637 if (sc->sc_flowflags & IFM_FLOW) { 3638 sc->sc_imr |= (ISR_PAUSE_END | ISR_PAUSE_ST); 3639 flowctl = FLOWCTL_FLOWEN; 3640 } else { 3641 sc->sc_imr &= ~(ISR_PAUSE_END | ISR_PAUSE_ST); 3642 flowctl = 0; 3643 } 3644 3645 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3646 sc->sc_txcfg); 3647 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3648 sc->sc_rxcfg); 3649 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3650 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3651 } 3652 3653 /* 3654 * sip_dp83815_mii_readreg: [mii interface function] 3655 * 3656 * Read a PHY register on the MII. 3657 */ 3658 static int 3659 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3660 { 3661 struct sip_softc *sc = device_private(self); 3662 uint32_t data; 3663 3664 /* 3665 * The DP83815 only has an internal PHY. Only allow 3666 * MII address 0. 3667 */ 3668 if (phy != 0) 3669 return -1; 3670 3671 /* 3672 * Apparently, after a reset, the DP83815 can take a while 3673 * to respond. During this recovery period, the BMSR returns 3674 * a value of 0. Catch this -- it's not supposed to happen 3675 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3676 * PHY to come back to life. 3677 * 3678 * This works out because the BMSR is the first register 3679 * read during the PHY probe process. 3680 */ 3681 do { 3682 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3683 } while (reg == MII_BMSR && data == 0); 3684 3685 *val = data & 0xffff; 3686 return 0; 3687 } 3688 3689 /* 3690 * sip_dp83815_mii_writereg: [mii interface function] 3691 * 3692 * Write a PHY register to the MII. 3693 */ 3694 static int 3695 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3696 { 3697 struct sip_softc *sc = device_private(self); 3698 3699 /* 3700 * The DP83815 only has an internal PHY. Only allow 3701 * MII address 0. 3702 */ 3703 if (phy != 0) 3704 return -1; 3705 3706 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3707 3708 return 0; 3709 } 3710 3711 /* 3712 * sip_dp83815_mii_statchg: [mii interface function] 3713 * 3714 * Callback from MII layer when media changes. 3715 */ 3716 static void 3717 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3718 { 3719 struct sip_softc *sc = ifp->if_softc; 3720 3721 /* 3722 * Update TXCFG for full-duplex operation. 3723 */ 3724 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3725 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3726 else 3727 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3728 3729 /* 3730 * Update RXCFG for full-duplex or loopback. 3731 */ 3732 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3733 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3734 sc->sc_rxcfg |= RXCFG_ATX; 3735 else 3736 sc->sc_rxcfg &= ~RXCFG_ATX; 3737 3738 /* 3739 * XXX 802.3x flow control. 3740 */ 3741 3742 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3743 sc->sc_txcfg); 3744 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3745 sc->sc_rxcfg); 3746 3747 /* 3748 * Some DP83815s experience problems when used with short 3749 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3750 * sequence adjusts the DSP's signal attenuation to fix the 3751 * problem. 3752 */ 3753 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3754 uint32_t reg; 3755 3756 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3757 3758 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3759 reg &= 0x0fff; 3760 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3761 delay(100); 3762 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3763 reg &= 0x00ff; 3764 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3765 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3766 0x00e8); 3767 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3768 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3769 reg | 0x20); 3770 } 3771 3772 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3773 } 3774 } 3775 3776 static void 3777 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3778 const struct pci_attach_args *pa, uint8_t *enaddr) 3779 { 3780 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3781 uint8_t cksum, *e, match; 3782 int i; 3783 3784 /* 3785 * EEPROM data format for the DP83820 can be found in 3786 * the DP83820 manual, section 4.2.4. 3787 */ 3788 3789 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3790 3791 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3792 match = ~(match - 1); 3793 3794 cksum = 0x55; 3795 e = (uint8_t *)eeprom_data; 3796 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3797 cksum += *e++; 3798 3799 if (cksum != match) 3800 printf("%s: Checksum (%x) mismatch (%x)", 3801 device_xname(sc->sc_dev), cksum, match); 3802 3803 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3804 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3805 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3806 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3807 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3808 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3809 } 3810 3811 static void 3812 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3813 { 3814 int i; 3815 3816 /* 3817 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3818 * a reason, but I don't know it. 3819 */ 3820 for (i = 0; i < 10; i++) 3821 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3822 } 3823 3824 static void 3825 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3826 const struct pci_attach_args *pa, uint8_t *enaddr) 3827 { 3828 uint16_t myea[ETHER_ADDR_LEN / 2]; 3829 3830 switch (sc->sc_rev) { 3831 case SIS_REV_630S: 3832 case SIS_REV_630E: 3833 case SIS_REV_630EA1: 3834 case SIS_REV_630ET: 3835 case SIS_REV_635: 3836 /* 3837 * The MAC address for the on-board Ethernet of 3838 * the SiS 630 chipset is in the NVRAM. Kick 3839 * the chip into re-loading it from NVRAM, and 3840 * read the MAC address out of the filter registers. 3841 */ 3842 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3843 3844 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3845 RFCR_RFADDR_NODE0); 3846 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3847 0xffff; 3848 3849 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3850 RFCR_RFADDR_NODE2); 3851 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3852 0xffff; 3853 3854 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3855 RFCR_RFADDR_NODE4); 3856 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3857 0xffff; 3858 break; 3859 3860 case SIS_REV_960: 3861 { 3862 #define SIS_SET_EROMAR(x, y) \ 3863 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3864 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3865 3866 #define SIS_CLR_EROMAR(x, y) \ 3867 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3868 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3869 3870 int waittime, i; 3871 3872 /* Allow to read EEPROM from LAN. It is shared 3873 * between a 1394 controller and the NIC and each 3874 * time we access it, we need to set SIS_EECMD_REQ. 3875 */ 3876 SIS_SET_EROMAR(sc, EROMAR_REQ); 3877 3878 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3879 /* Force EEPROM to idle state. */ 3880 3881 /* 3882 * XXX-cube This is ugly. 3883 * I'll look for docs about it. 3884 */ 3885 SIS_SET_EROMAR(sc, EROMAR_EECS); 3886 sipcom_sis900_eeprom_delay(sc); 3887 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3888 SIS_SET_EROMAR(sc, EROMAR_EESK); 3889 sipcom_sis900_eeprom_delay(sc); 3890 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3891 sipcom_sis900_eeprom_delay(sc); 3892 } 3893 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3894 sipcom_sis900_eeprom_delay(sc); 3895 bus_space_write_4(sc->sc_st, sc->sc_sh, 3896 SIP_EROMAR, 0); 3897 3898 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3899 SIP_EROMAR) & EROMAR_GNT) { 3900 sipcom_read_eeprom(sc, 3901 SIP_EEPROM_ETHERNET_ID0 >> 1, 3902 sizeof(myea) / sizeof(myea[0]), 3903 myea); 3904 break; 3905 } 3906 DELAY(1); 3907 } 3908 3909 /* 3910 * Set SIS_EECTL_CLK to high, so a other master 3911 * can operate on the i2c bus. 3912 */ 3913 SIS_SET_EROMAR(sc, EROMAR_EESK); 3914 3915 /* Refuse EEPROM access by LAN */ 3916 SIS_SET_EROMAR(sc, EROMAR_DONE); 3917 } break; 3918 3919 default: 3920 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3921 sizeof(myea) / sizeof(myea[0]), myea); 3922 } 3923 3924 enaddr[0] = myea[0] & 0xff; 3925 enaddr[1] = myea[0] >> 8; 3926 enaddr[2] = myea[1] & 0xff; 3927 enaddr[3] = myea[1] >> 8; 3928 enaddr[4] = myea[2] & 0xff; 3929 enaddr[5] = myea[2] >> 8; 3930 } 3931 3932 /* Table and macro to bit-reverse an octet. */ 3933 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3934 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3935 3936 static void 3937 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3938 const struct pci_attach_args *pa, uint8_t *enaddr) 3939 { 3940 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3941 uint8_t cksum, *e, match; 3942 int i; 3943 3944 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3945 sizeof(eeprom_data[0]), eeprom_data); 3946 3947 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3948 match = ~(match - 1); 3949 3950 cksum = 0x55; 3951 e = (uint8_t *)eeprom_data; 3952 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3953 cksum += *e++; 3954 3955 if (cksum != match) 3956 printf("%s: Checksum (%x) mismatch (%x)", 3957 device_xname(sc->sc_dev), cksum, match); 3958 3959 /* 3960 * Unrolled because it makes slightly more sense this way. 3961 * The DP83815 stores the MAC address in bit 0 of word 6 3962 * through bit 15 of word 8. 3963 */ 3964 ea = &eeprom_data[6]; 3965 enaddr[0] = ((*ea & 0x1) << 7); 3966 ea++; 3967 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3968 enaddr[1] = ((*ea & 0x1FE) >> 1); 3969 enaddr[2] = ((*ea & 0x1) << 7); 3970 ea++; 3971 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3972 enaddr[3] = ((*ea & 0x1FE) >> 1); 3973 enaddr[4] = ((*ea & 0x1) << 7); 3974 ea++; 3975 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3976 enaddr[5] = ((*ea & 0x1FE) >> 1); 3977 3978 /* 3979 * In case that's not weird enough, we also need to reverse 3980 * the bits in each byte. This all actually makes more sense 3981 * if you think about the EEPROM storage as an array of bits 3982 * being shifted into bytes, but that's not how we're looking 3983 * at it here... 3984 */ 3985 for (i = 0; i < 6 ;i++) 3986 enaddr[i] = bbr(enaddr[i]); 3987 } 3988 3989 /* 3990 * sip_mediastatus: [ifmedia interface function] 3991 * 3992 * Get the current interface media status. 3993 */ 3994 static void 3995 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3996 { 3997 struct sip_softc *sc = ifp->if_softc; 3998 3999 if (!device_is_active(sc->sc_dev)) { 4000 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 4001 ifmr->ifm_status = 0; 4002 return; 4003 } 4004 ether_mediastatus(ifp, ifmr); 4005 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 4006 sc->sc_flowflags; 4007 } 4008
Indexes created Tue Sep 30 11:09:46 GMT 2025