if_sip.c revision 1.169
1 /* $NetBSD: if_sip.c,v 1.169 2019/01/22 03:42:27 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.169 2019/01/22 03:42:27 msaitoh Exp $"); 77 78 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/callout.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #include <sys/device.h> 90 #include <sys/queue.h> 91 92 #include <sys/rndsource.h> 93 94 #include <net/if.h> 95 #include <net/if_dl.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #include <net/bpf.h> 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 #include <machine/endian.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 #include <dev/mii/mii_bitbang.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 #include <dev/pci/pcidevs.h> 112 113 #include <dev/pci/if_sipreg.h> 114 115 /* 116 * Transmit descriptor list size. This is arbitrary, but allocate 117 * enough descriptors for 128 pending transmissions, and 8 segments 118 * per packet (64 for DP83820 for jumbo frames). 119 * 120 * This MUST work out to a power of 2. 121 */ 122 #define GSIP_NTXSEGS_ALLOC 16 123 #define SIP_NTXSEGS_ALLOC 8 124 125 #define SIP_TXQUEUELEN 256 126 #define MAX_SIP_NTXDESC \ 127 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 128 129 /* 130 * Receive descriptor list size. We have one Rx buffer per incoming 131 * packet, so this logic is a little simpler. 132 * 133 * Actually, on the DP83820, we allow the packet to consume more than 134 * one buffer, in order to support jumbo Ethernet frames. In that 135 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 136 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 137 * so we'd better be quick about handling receive interrupts. 138 */ 139 #define GSIP_NRXDESC 256 140 #define SIP_NRXDESC 128 141 142 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 143 144 /* 145 * Control structures are DMA'd to the SiS900 chip. We allocate them in 146 * a single clump that maps to a single DMA segment to make several things 147 * easier. 148 */ 149 struct sip_control_data { 150 /* 151 * The transmit descriptors. 152 */ 153 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 154 155 /* 156 * The receive descriptors. 157 */ 158 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 159 }; 160 161 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 162 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 163 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 164 165 /* 166 * Software state for transmit jobs. 167 */ 168 struct sip_txsoft { 169 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 170 bus_dmamap_t txs_dmamap; /* our DMA map */ 171 int txs_firstdesc; /* first descriptor in packet */ 172 int txs_lastdesc; /* last descriptor in packet */ 173 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 174 }; 175 176 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 177 178 /* 179 * Software state for receive jobs. 180 */ 181 struct sip_rxsoft { 182 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 183 bus_dmamap_t rxs_dmamap; /* our DMA map */ 184 }; 185 186 enum sip_attach_stage { 187 SIP_ATTACH_FIN = 0 188 , SIP_ATTACH_CREATE_RXMAP 189 , SIP_ATTACH_CREATE_TXMAP 190 , SIP_ATTACH_LOAD_MAP 191 , SIP_ATTACH_CREATE_MAP 192 , SIP_ATTACH_MAP_MEM 193 , SIP_ATTACH_ALLOC_MEM 194 , SIP_ATTACH_INTR 195 , SIP_ATTACH_MAP 196 }; 197 198 /* 199 * Software state per device. 200 */ 201 struct sip_softc { 202 device_t sc_dev; /* generic device information */ 203 device_suspensor_t sc_suspensor; 204 pmf_qual_t sc_qual; 205 206 bus_space_tag_t sc_st; /* bus space tag */ 207 bus_space_handle_t sc_sh; /* bus space handle */ 208 bus_size_t sc_sz; /* bus space size */ 209 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 210 pci_chipset_tag_t sc_pc; 211 bus_dma_segment_t sc_seg; 212 struct ethercom sc_ethercom; /* ethernet common data */ 213 214 const struct sip_product *sc_model; /* which model are we? */ 215 int sc_gigabit; /* 1: 83820, 0: other */ 216 int sc_rev; /* chip revision */ 217 218 void *sc_ih; /* interrupt cookie */ 219 220 struct mii_data sc_mii; /* MII/media information */ 221 222 callout_t sc_tick_ch; /* tick callout */ 223 224 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 225 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 231 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct sip_control_data *sc_control_data; 237 #define sc_txdescs sc_control_data->scd_txdescs 238 #define sc_rxdescs sc_control_data->scd_rxdescs 239 240 #ifdef SIP_EVENT_COUNTERS 241 /* 242 * Event counters. 243 */ 244 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 245 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 246 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 247 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 248 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 249 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 250 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 251 struct evcnt sc_ev_rxpause; /* PAUSE received */ 252 /* DP83820 only */ 253 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 254 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 255 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 256 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 257 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 258 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 259 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 260 #endif /* SIP_EVENT_COUNTERS */ 261 262 u_int32_t sc_txcfg; /* prototype TXCFG register */ 263 u_int32_t sc_rxcfg; /* prototype RXCFG register */ 264 u_int32_t sc_imr; /* prototype IMR register */ 265 u_int32_t sc_rfcr; /* prototype RFCR register */ 266 267 u_int32_t sc_cfg; /* prototype CFG register */ 268 269 u_int32_t sc_gpior; /* prototype GPIOR register */ 270 271 u_int32_t sc_tx_fill_thresh; /* transmit fill threshold */ 272 u_int32_t sc_tx_drain_thresh; /* transmit drain threshold */ 273 274 u_int32_t sc_rx_drain_thresh; /* receive drain threshold */ 275 276 int sc_flowflags; /* 802.3x flow control flags */ 277 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 278 int sc_paused; /* paused indication */ 279 280 int sc_txfree; /* number of free Tx descriptors */ 281 int sc_txnext; /* next ready Tx descriptor */ 282 int sc_txwin; /* Tx descriptors since last intr */ 283 284 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 285 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 286 287 /* values of interface state at last init */ 288 struct { 289 /* if_capenable */ 290 uint64_t if_capenable; 291 /* ec_capenable */ 292 int ec_capenable; 293 /* VLAN_ATTACHED */ 294 int is_vlan; 295 } sc_prev; 296 297 short sc_if_flags; 298 299 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 300 int sc_rxdiscard; 301 int sc_rxlen; 302 struct mbuf *sc_rxhead; 303 struct mbuf *sc_rxtail; 304 struct mbuf **sc_rxtailp; 305 306 int sc_ntxdesc; 307 int sc_ntxdesc_mask; 308 309 int sc_nrxdesc_mask; 310 311 const struct sip_parm { 312 const struct sip_regs { 313 int r_rxcfg; 314 int r_txcfg; 315 } p_regs; 316 317 const struct sip_bits { 318 uint32_t b_txcfg_mxdma_8; 319 uint32_t b_txcfg_mxdma_16; 320 uint32_t b_txcfg_mxdma_32; 321 uint32_t b_txcfg_mxdma_64; 322 uint32_t b_txcfg_mxdma_128; 323 uint32_t b_txcfg_mxdma_256; 324 uint32_t b_txcfg_mxdma_512; 325 uint32_t b_txcfg_flth_mask; 326 uint32_t b_txcfg_drth_mask; 327 328 uint32_t b_rxcfg_mxdma_8; 329 uint32_t b_rxcfg_mxdma_16; 330 uint32_t b_rxcfg_mxdma_32; 331 uint32_t b_rxcfg_mxdma_64; 332 uint32_t b_rxcfg_mxdma_128; 333 uint32_t b_rxcfg_mxdma_256; 334 uint32_t b_rxcfg_mxdma_512; 335 336 uint32_t b_isr_txrcmp; 337 uint32_t b_isr_rxrcmp; 338 uint32_t b_isr_dperr; 339 uint32_t b_isr_sserr; 340 uint32_t b_isr_rmabt; 341 uint32_t b_isr_rtabt; 342 343 uint32_t b_cmdsts_size_mask; 344 } p_bits; 345 int p_filtmem; 346 int p_rxbuf_len; 347 bus_size_t p_tx_dmamap_size; 348 int p_ntxsegs; 349 int p_ntxsegs_alloc; 350 int p_nrxdesc; 351 } *sc_parm; 352 353 void (*sc_rxintr)(struct sip_softc *); 354 355 krndsource_t rnd_source; /* random source */ 356 }; 357 358 #define sc_bits sc_parm->p_bits 359 #define sc_regs sc_parm->p_regs 360 361 static const struct sip_parm sip_parm = { 362 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 363 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 364 , .p_tx_dmamap_size = MCLBYTES 365 , .p_ntxsegs = 16 366 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 367 , .p_nrxdesc = SIP_NRXDESC 368 , .p_bits = { 369 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 370 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 371 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 372 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 373 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 374 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 375 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 376 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 377 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 378 379 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 380 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 381 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 382 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 383 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 384 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 385 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 386 387 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 388 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 389 , .b_isr_dperr = 0x00800000 /* detected parity error */ 390 , .b_isr_sserr = 0x00400000 /* signalled system error */ 391 , .b_isr_rmabt = 0x00200000 /* received master abort */ 392 , .b_isr_rtabt = 0x00100000 /* received target abort */ 393 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 394 } 395 , .p_regs = { 396 .r_rxcfg = OTHER_SIP_RXCFG, 397 .r_txcfg = OTHER_SIP_TXCFG 398 } 399 }, gsip_parm = { 400 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 401 , .p_rxbuf_len = MCLBYTES - 8 402 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 403 , .p_ntxsegs = 64 404 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 405 , .p_nrxdesc = GSIP_NRXDESC 406 , .p_bits = { 407 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 408 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 409 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 410 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 411 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 412 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 413 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 414 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 415 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 416 417 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 418 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 419 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 420 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 421 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 422 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 423 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 424 425 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 426 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 427 , .b_isr_dperr = 0x00100000 /* detected parity error */ 428 , .b_isr_sserr = 0x00080000 /* signalled system error */ 429 , .b_isr_rmabt = 0x00040000 /* received master abort */ 430 , .b_isr_rtabt = 0x00020000 /* received target abort */ 431 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 432 } 433 , .p_regs = { 434 .r_rxcfg = DP83820_SIP_RXCFG, 435 .r_txcfg = DP83820_SIP_TXCFG 436 } 437 }; 438 439 static inline int 440 sip_nexttx(const struct sip_softc *sc, int x) 441 { 442 return (x + 1) & sc->sc_ntxdesc_mask; 443 } 444 445 static inline int 446 sip_nextrx(const struct sip_softc *sc, int x) 447 { 448 return (x + 1) & sc->sc_nrxdesc_mask; 449 } 450 451 /* 83820 only */ 452 static inline void 453 sip_rxchain_reset(struct sip_softc *sc) 454 { 455 sc->sc_rxtailp = &sc->sc_rxhead; 456 *sc->sc_rxtailp = NULL; 457 sc->sc_rxlen = 0; 458 } 459 460 /* 83820 only */ 461 static inline void 462 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 463 { 464 *sc->sc_rxtailp = sc->sc_rxtail = m; 465 sc->sc_rxtailp = &m->m_next; 466 } 467 468 #ifdef SIP_EVENT_COUNTERS 469 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 470 #else 471 #define SIP_EVCNT_INCR(ev) /* nothing */ 472 #endif 473 474 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 475 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 476 477 static inline void 478 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 479 { 480 int x, n; 481 482 x = x0; 483 n = n0; 484 485 /* If it will wrap around, sync to the end of the ring. */ 486 if (x + n > sc->sc_ntxdesc) { 487 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 488 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 489 (sc->sc_ntxdesc - x), ops); 490 n -= (sc->sc_ntxdesc - x); 491 x = 0; 492 } 493 494 /* Now sync whatever is left. */ 495 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 496 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 497 } 498 499 static inline void 500 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 501 { 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 503 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 504 } 505 506 #if 0 507 #ifdef DP83820 508 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 509 u_int32_t sipd_cmdsts; /* command/status word */ 510 #else 511 u_int32_t sipd_cmdsts; /* command/status word */ 512 u_int32_t sipd_bufptr; /* pointer to DMA segment */ 513 #endif /* DP83820 */ 514 #endif /* 0 */ 515 516 static inline volatile uint32_t * 517 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 518 { 519 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 520 } 521 522 static inline volatile uint32_t * 523 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 524 { 525 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 526 } 527 528 static inline void 529 sip_init_rxdesc(struct sip_softc *sc, int x) 530 { 531 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 532 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 533 534 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 535 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 536 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 537 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 538 sipd->sipd_extsts = 0; 539 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 540 } 541 542 #define SIP_CHIP_VERS(sc, v, p, r) \ 543 ((sc)->sc_model->sip_vendor == (v) && \ 544 (sc)->sc_model->sip_product == (p) && \ 545 (sc)->sc_rev == (r)) 546 547 #define SIP_CHIP_MODEL(sc, v, p) \ 548 ((sc)->sc_model->sip_vendor == (v) && \ 549 (sc)->sc_model->sip_product == (p)) 550 551 #define SIP_SIS900_REV(sc, rev) \ 552 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 553 554 #define SIP_TIMEOUT 1000 555 556 static int sip_ifflags_cb(struct ethercom *); 557 static void sipcom_start(struct ifnet *); 558 static void sipcom_watchdog(struct ifnet *); 559 static int sipcom_ioctl(struct ifnet *, u_long, void *); 560 static int sipcom_init(struct ifnet *); 561 static void sipcom_stop(struct ifnet *, int); 562 563 static bool sipcom_reset(struct sip_softc *); 564 static void sipcom_rxdrain(struct sip_softc *); 565 static int sipcom_add_rxbuf(struct sip_softc *, int); 566 static void sipcom_read_eeprom(struct sip_softc *, int, int, 567 u_int16_t *); 568 static void sipcom_tick(void *); 569 570 static void sipcom_sis900_set_filter(struct sip_softc *); 571 static void sipcom_dp83815_set_filter(struct sip_softc *); 572 573 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 574 const struct pci_attach_args *, u_int8_t *); 575 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 576 static void sipcom_sis900_read_macaddr(struct sip_softc *, 577 const struct pci_attach_args *, u_int8_t *); 578 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 579 const struct pci_attach_args *, u_int8_t *); 580 581 static int sipcom_intr(void *); 582 static void sipcom_txintr(struct sip_softc *); 583 static void sip_rxintr(struct sip_softc *); 584 static void gsip_rxintr(struct sip_softc *); 585 586 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_dp83820_mii_statchg(struct ifnet *); 589 590 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_sis900_mii_statchg(struct ifnet *); 593 594 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 595 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 596 static void sipcom_dp83815_mii_statchg(struct ifnet *); 597 598 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 599 600 static int sipcom_match(device_t, cfdata_t, void *); 601 static void sipcom_attach(device_t, device_t, void *); 602 static void sipcom_do_detach(device_t, enum sip_attach_stage); 603 static int sipcom_detach(device_t, int); 604 static bool sipcom_resume(device_t, const pmf_qual_t *); 605 static bool sipcom_suspend(device_t, const pmf_qual_t *); 606 607 int gsip_copy_small = 0; 608 int sip_copy_small = 0; 609 610 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 611 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 612 DVF_DETACH_SHUTDOWN); 613 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 614 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 615 DVF_DETACH_SHUTDOWN); 616 617 /* 618 * Descriptions of the variants of the SiS900. 619 */ 620 struct sip_variant { 621 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 622 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 623 void (*sipv_mii_statchg)(struct ifnet *); 624 void (*sipv_set_filter)(struct sip_softc *); 625 void (*sipv_read_macaddr)(struct sip_softc *, 626 const struct pci_attach_args *, u_int8_t *); 627 }; 628 629 static u_int32_t sipcom_mii_bitbang_read(device_t); 630 static void sipcom_mii_bitbang_write(device_t, u_int32_t); 631 632 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 633 sipcom_mii_bitbang_read, 634 sipcom_mii_bitbang_write, 635 { 636 EROMAR_MDIO, /* MII_BIT_MDO */ 637 EROMAR_MDIO, /* MII_BIT_MDI */ 638 EROMAR_MDC, /* MII_BIT_MDC */ 639 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 640 0, /* MII_BIT_DIR_PHY_HOST */ 641 } 642 }; 643 644 static const struct sip_variant sipcom_variant_dp83820 = { 645 sipcom_dp83820_mii_readreg, 646 sipcom_dp83820_mii_writereg, 647 sipcom_dp83820_mii_statchg, 648 sipcom_dp83815_set_filter, 649 sipcom_dp83820_read_macaddr, 650 }; 651 652 static const struct sip_variant sipcom_variant_sis900 = { 653 sipcom_sis900_mii_readreg, 654 sipcom_sis900_mii_writereg, 655 sipcom_sis900_mii_statchg, 656 sipcom_sis900_set_filter, 657 sipcom_sis900_read_macaddr, 658 }; 659 660 static const struct sip_variant sipcom_variant_dp83815 = { 661 sipcom_dp83815_mii_readreg, 662 sipcom_dp83815_mii_writereg, 663 sipcom_dp83815_mii_statchg, 664 sipcom_dp83815_set_filter, 665 sipcom_dp83815_read_macaddr, 666 }; 667 668 669 /* 670 * Devices supported by this driver. 671 */ 672 static const struct sip_product { 673 pci_vendor_id_t sip_vendor; 674 pci_product_id_t sip_product; 675 const char *sip_name; 676 const struct sip_variant *sip_variant; 677 int sip_gigabit; 678 } sipcom_products[] = { 679 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 680 "NatSemi DP83820 Gigabit Ethernet", 681 &sipcom_variant_dp83820, 1 }, 682 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 683 "SiS 900 10/100 Ethernet", 684 &sipcom_variant_sis900, 0 }, 685 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 686 "SiS 7016 10/100 Ethernet", 687 &sipcom_variant_sis900, 0 }, 688 689 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 690 "NatSemi DP83815 10/100 Ethernet", 691 &sipcom_variant_dp83815, 0 }, 692 693 { 0, 0, 694 NULL, 695 NULL, 0 }, 696 }; 697 698 static const struct sip_product * 699 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 700 { 701 const struct sip_product *sip; 702 703 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 704 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 705 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 706 sip->sip_gigabit == gigabit) 707 return sip; 708 } 709 return NULL; 710 } 711 712 /* 713 * I really hate stupid hardware vendors. There's a bit in the EEPROM 714 * which indicates if the card can do 64-bit data transfers. Unfortunately, 715 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 716 * which means we try to use 64-bit data transfers on those cards if we 717 * happen to be plugged into a 32-bit slot. 718 * 719 * What we do is use this table of cards known to be 64-bit cards. If 720 * you have a 64-bit card who's subsystem ID is not listed in this table, 721 * send the output of "pcictl dump ..." of the device to me so that your 722 * card will use the 64-bit data path when plugged into a 64-bit slot. 723 * 724 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 725 * June 30, 2002 726 */ 727 static int 728 sipcom_check_64bit(const struct pci_attach_args *pa) 729 { 730 static const struct { 731 pci_vendor_id_t c64_vendor; 732 pci_product_id_t c64_product; 733 } card64[] = { 734 /* Asante GigaNIX */ 735 { 0x128a, 0x0002 }, 736 737 /* Accton EN1407-T, Planex GN-1000TE */ 738 { 0x1113, 0x1407 }, 739 740 /* Netgear GA621 */ 741 { 0x1385, 0x621a }, 742 743 /* Netgear GA622 */ 744 { 0x1385, 0x622a }, 745 746 /* SMC EZ Card 1000 (9462TX) */ 747 { 0x10b8, 0x9462 }, 748 749 { 0, 0} 750 }; 751 pcireg_t subsys; 752 int i; 753 754 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 755 756 for (i = 0; card64[i].c64_vendor != 0; i++) { 757 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 758 PCI_PRODUCT(subsys) == card64[i].c64_product) 759 return (1); 760 } 761 762 return (0); 763 } 764 765 static int 766 sipcom_match(device_t parent, cfdata_t cf, void *aux) 767 { 768 struct pci_attach_args *pa = aux; 769 770 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 771 return 1; 772 773 return 0; 774 } 775 776 static void 777 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 778 { 779 u_int32_t reg; 780 int i; 781 782 /* 783 * Cause the chip to load configuration data from the EEPROM. 784 */ 785 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 786 for (i = 0; i < 10000; i++) { 787 delay(10); 788 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) == 0) 790 break; 791 } 792 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 793 PTSCR_EELOAD_EN) { 794 printf("%s: timeout loading configuration from EEPROM\n", 795 device_xname(sc->sc_dev)); 796 return; 797 } 798 799 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 800 801 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 802 if (reg & CFG_PCI64_DET) { 803 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 804 /* 805 * Check to see if this card is 64-bit. If so, enable 64-bit 806 * data transfers. 807 * 808 * We can't use the DATA64_EN bit in the EEPROM, because 809 * vendors of 32-bit cards fail to clear that bit in many 810 * cases (yet the card still detects that it's in a 64-bit 811 * slot; go figure). 812 */ 813 if (sipcom_check_64bit(pa)) { 814 sc->sc_cfg |= CFG_DATA64_EN; 815 printf(", using 64-bit data transfers"); 816 } 817 printf("\n"); 818 } 819 820 /* 821 * XXX Need some PCI flags indicating support for 822 * XXX 64-bit addressing. 823 */ 824 #if 0 825 if (reg & CFG_M64ADDR) 826 sc->sc_cfg |= CFG_M64ADDR; 827 if (reg & CFG_T64ADDR) 828 sc->sc_cfg |= CFG_T64ADDR; 829 #endif 830 831 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 832 const char *sep = ""; 833 printf("%s: using ", device_xname(sc->sc_dev)); 834 if (reg & CFG_EXT_125) { 835 sc->sc_cfg |= CFG_EXT_125; 836 printf("%s125MHz clock", sep); 837 sep = ", "; 838 } 839 if (reg & CFG_TBI_EN) { 840 sc->sc_cfg |= CFG_TBI_EN; 841 printf("%sten-bit interface", sep); 842 sep = ", "; 843 } 844 printf("\n"); 845 } 846 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 847 (reg & CFG_MRM_DIS) != 0) 848 sc->sc_cfg |= CFG_MRM_DIS; 849 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 850 (reg & CFG_MWI_DIS) != 0) 851 sc->sc_cfg |= CFG_MWI_DIS; 852 853 /* 854 * Use the extended descriptor format on the DP83820. This 855 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 856 * checksumming. 857 */ 858 sc->sc_cfg |= CFG_EXTSTS_EN; 859 } 860 861 static int 862 sipcom_detach(device_t self, int flags) 863 { 864 int s; 865 866 s = splnet(); 867 sipcom_do_detach(self, SIP_ATTACH_FIN); 868 splx(s); 869 870 return 0; 871 } 872 873 static void 874 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 875 { 876 int i; 877 struct sip_softc *sc = device_private(self); 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 880 /* 881 * Free any resources we've allocated during attach. 882 * Do this in reverse order and fall through. 883 */ 884 switch (stage) { 885 case SIP_ATTACH_FIN: 886 sipcom_stop(ifp, 1); 887 pmf_device_deregister(self); 888 #ifdef SIP_EVENT_COUNTERS 889 /* 890 * Attach event counters. 891 */ 892 evcnt_detach(&sc->sc_ev_txforceintr); 893 evcnt_detach(&sc->sc_ev_txdstall); 894 evcnt_detach(&sc->sc_ev_txsstall); 895 evcnt_detach(&sc->sc_ev_hiberr); 896 evcnt_detach(&sc->sc_ev_rxintr); 897 evcnt_detach(&sc->sc_ev_txiintr); 898 evcnt_detach(&sc->sc_ev_txdintr); 899 if (!sc->sc_gigabit) { 900 evcnt_detach(&sc->sc_ev_rxpause); 901 } else { 902 evcnt_detach(&sc->sc_ev_txudpsum); 903 evcnt_detach(&sc->sc_ev_txtcpsum); 904 evcnt_detach(&sc->sc_ev_txipsum); 905 evcnt_detach(&sc->sc_ev_rxudpsum); 906 evcnt_detach(&sc->sc_ev_rxtcpsum); 907 evcnt_detach(&sc->sc_ev_rxipsum); 908 evcnt_detach(&sc->sc_ev_txpause); 909 evcnt_detach(&sc->sc_ev_rxpause); 910 } 911 #endif /* SIP_EVENT_COUNTERS */ 912 913 rnd_detach_source(&sc->rnd_source); 914 915 ether_ifdetach(ifp); 916 if_detach(ifp); 917 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 918 919 /*FALLTHROUGH*/ 920 case SIP_ATTACH_CREATE_RXMAP: 921 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 922 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->sc_rxsoft[i].rxs_dmamap); 925 } 926 /*FALLTHROUGH*/ 927 case SIP_ATTACH_CREATE_TXMAP: 928 for (i = 0; i < SIP_TXQUEUELEN; i++) { 929 if (sc->sc_txsoft[i].txs_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->sc_txsoft[i].txs_dmamap); 932 } 933 /*FALLTHROUGH*/ 934 case SIP_ATTACH_LOAD_MAP: 935 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 936 /*FALLTHROUGH*/ 937 case SIP_ATTACH_CREATE_MAP: 938 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_MAP_MEM: 941 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 942 sizeof(struct sip_control_data)); 943 /*FALLTHROUGH*/ 944 case SIP_ATTACH_ALLOC_MEM: 945 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 946 /* FALLTHROUGH*/ 947 case SIP_ATTACH_INTR: 948 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 949 /* FALLTHROUGH*/ 950 case SIP_ATTACH_MAP: 951 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 952 break; 953 default: 954 break; 955 } 956 return; 957 } 958 959 static bool 960 sipcom_resume(device_t self, const pmf_qual_t *qual) 961 { 962 struct sip_softc *sc = device_private(self); 963 964 return sipcom_reset(sc); 965 } 966 967 static bool 968 sipcom_suspend(device_t self, const pmf_qual_t *qual) 969 { 970 struct sip_softc *sc = device_private(self); 971 972 sipcom_rxdrain(sc); 973 return true; 974 } 975 976 static void 977 sipcom_attach(device_t parent, device_t self, void *aux) 978 { 979 struct sip_softc *sc = device_private(self); 980 struct pci_attach_args *pa = aux; 981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 982 pci_chipset_tag_t pc = pa->pa_pc; 983 pci_intr_handle_t ih; 984 const char *intrstr = NULL; 985 bus_space_tag_t iot, memt; 986 bus_space_handle_t ioh, memh; 987 bus_size_t iosz, memsz; 988 int ioh_valid, memh_valid; 989 int i, rseg, error; 990 const struct sip_product *sip; 991 u_int8_t enaddr[ETHER_ADDR_LEN]; 992 pcireg_t csr; 993 pcireg_t memtype; 994 bus_size_t tx_dmamap_size; 995 int ntxsegs_alloc; 996 cfdata_t cf = device_cfdata(self); 997 char intrbuf[PCI_INTRSTR_LEN]; 998 999 callout_init(&sc->sc_tick_ch, 0); 1000 1001 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 1002 if (sip == NULL) { 1003 aprint_error("\n"); 1004 panic("%s: impossible", __func__); 1005 } 1006 sc->sc_dev = self; 1007 sc->sc_gigabit = sip->sip_gigabit; 1008 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1009 sc->sc_pc = pc; 1010 1011 if (sc->sc_gigabit) { 1012 sc->sc_rxintr = gsip_rxintr; 1013 sc->sc_parm = &gsip_parm; 1014 } else { 1015 sc->sc_rxintr = sip_rxintr; 1016 sc->sc_parm = &sip_parm; 1017 } 1018 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1019 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1020 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1021 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1022 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1023 1024 sc->sc_rev = PCI_REVISION(pa->pa_class); 1025 1026 aprint_naive("\n"); 1027 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1028 1029 sc->sc_model = sip; 1030 1031 /* 1032 * XXX Work-around broken PXE firmware on some boards. 1033 * 1034 * The DP83815 shares an address decoder with the MEM BAR 1035 * and the ROM BAR. Make sure the ROM BAR is disabled, 1036 * so that memory mapped access works. 1037 */ 1038 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1039 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1040 ~PCI_MAPREG_ROM_ENABLE); 1041 1042 /* 1043 * Map the device. 1044 */ 1045 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1046 PCI_MAPREG_TYPE_IO, 0, 1047 &iot, &ioh, NULL, &iosz) == 0); 1048 if (sc->sc_gigabit) { 1049 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1050 switch (memtype) { 1051 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1052 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1053 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1054 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1055 break; 1056 default: 1057 memh_valid = 0; 1058 } 1059 } else { 1060 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1061 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1062 &memt, &memh, NULL, &memsz) == 0); 1063 } 1064 1065 if (memh_valid) { 1066 sc->sc_st = memt; 1067 sc->sc_sh = memh; 1068 sc->sc_sz = memsz; 1069 } else if (ioh_valid) { 1070 sc->sc_st = iot; 1071 sc->sc_sh = ioh; 1072 sc->sc_sz = iosz; 1073 } else { 1074 aprint_error_dev(self, "unable to map device registers\n"); 1075 return; 1076 } 1077 1078 sc->sc_dmat = pa->pa_dmat; 1079 1080 /* 1081 * Make sure bus mastering is enabled. Also make sure 1082 * Write/Invalidate is enabled if we're allowed to use it. 1083 */ 1084 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1085 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1086 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1087 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1088 csr | PCI_COMMAND_MASTER_ENABLE); 1089 1090 /* power up chip */ 1091 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1092 if (error != 0 && error != EOPNOTSUPP) { 1093 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1094 return; 1095 } 1096 1097 /* 1098 * Map and establish our interrupt. 1099 */ 1100 if (pci_intr_map(pa, &ih)) { 1101 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1102 return; 1103 } 1104 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1105 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1106 device_xname(self)); 1107 if (sc->sc_ih == NULL) { 1108 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1109 if (intrstr != NULL) 1110 aprint_error(" at %s", intrstr); 1111 aprint_error("\n"); 1112 sipcom_do_detach(self, SIP_ATTACH_MAP); 1113 return; 1114 } 1115 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1116 1117 SIMPLEQ_INIT(&sc->sc_txfreeq); 1118 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1119 1120 /* 1121 * Allocate the control data structures, and create and load the 1122 * DMA map for it. 1123 */ 1124 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1125 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1126 &rseg, 0)) != 0) { 1127 aprint_error_dev(sc->sc_dev, 1128 "unable to allocate control data, error = %d\n", error); 1129 sipcom_do_detach(self, SIP_ATTACH_INTR); 1130 return; 1131 } 1132 1133 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1134 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1135 BUS_DMA_COHERENT)) != 0) { 1136 aprint_error_dev(sc->sc_dev, 1137 "unable to map control data, error = %d\n", error); 1138 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1139 } 1140 1141 if ((error = bus_dmamap_create(sc->sc_dmat, 1142 sizeof(struct sip_control_data), 1, 1143 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1144 aprint_error_dev(self, "unable to create control data DMA map" 1145 ", error = %d\n", error); 1146 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1147 } 1148 1149 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1150 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1151 0)) != 0) { 1152 aprint_error_dev(self, "unable to load control data DMA map" 1153 ", error = %d\n", error); 1154 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1155 } 1156 1157 /* 1158 * Create the transmit buffer DMA maps. 1159 */ 1160 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1161 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1162 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1163 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1164 aprint_error_dev(self, "unable to create tx DMA map %d" 1165 ", error = %d\n", i, error); 1166 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1167 } 1168 } 1169 1170 /* 1171 * Create the receive buffer DMA maps. 1172 */ 1173 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1174 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1175 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1176 aprint_error_dev(self, "unable to create rx DMA map %d" 1177 ", error = %d\n", i, error); 1178 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1179 } 1180 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1181 } 1182 1183 /* 1184 * Reset the chip to a known state. 1185 */ 1186 sipcom_reset(sc); 1187 1188 /* 1189 * Read the Ethernet address from the EEPROM. This might 1190 * also fetch other stuff from the EEPROM and stash it 1191 * in the softc. 1192 */ 1193 sc->sc_cfg = 0; 1194 if (!sc->sc_gigabit) { 1195 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1196 SIP_SIS900_REV(sc,SIS_REV_900B)) 1197 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1198 1199 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1200 SIP_SIS900_REV(sc,SIS_REV_960) || 1201 SIP_SIS900_REV(sc,SIS_REV_900B)) 1202 sc->sc_cfg |= 1203 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1204 CFG_EDBMASTEN); 1205 } 1206 1207 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1208 1209 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1210 1211 /* 1212 * Initialize the configuration register: aggressive PCI 1213 * bus request algorithm, default backoff, default OW timer, 1214 * default parity error detection. 1215 * 1216 * NOTE: "Big endian mode" is useless on the SiS900 and 1217 * friends -- it affects packet data, not descriptors. 1218 */ 1219 if (sc->sc_gigabit) 1220 sipcom_dp83820_attach(sc, pa); 1221 1222 /* 1223 * Initialize our media structures and probe the MII. 1224 */ 1225 sc->sc_mii.mii_ifp = ifp; 1226 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1227 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1228 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1229 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1230 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1231 sipcom_mediastatus); 1232 1233 /* 1234 * XXX We cannot handle flow control on the DP83815. 1235 */ 1236 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1237 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1238 MII_OFFSET_ANY, 0); 1239 else 1240 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1241 MII_OFFSET_ANY, MIIF_DOPAUSE); 1242 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1243 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1245 } else 1246 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1247 1248 ifp = &sc->sc_ethercom.ec_if; 1249 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1250 ifp->if_softc = sc; 1251 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1252 sc->sc_if_flags = ifp->if_flags; 1253 ifp->if_ioctl = sipcom_ioctl; 1254 ifp->if_start = sipcom_start; 1255 ifp->if_watchdog = sipcom_watchdog; 1256 ifp->if_init = sipcom_init; 1257 ifp->if_stop = sipcom_stop; 1258 IFQ_SET_READY(&ifp->if_snd); 1259 1260 /* 1261 * We can support 802.1Q VLAN-sized frames. 1262 */ 1263 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1264 1265 if (sc->sc_gigabit) { 1266 /* 1267 * And the DP83820 can do VLAN tagging in hardware, and 1268 * support the jumbo Ethernet MTU. 1269 */ 1270 sc->sc_ethercom.ec_capabilities |= 1271 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1272 1273 /* 1274 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1275 * in hardware. 1276 */ 1277 ifp->if_capabilities |= 1278 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1279 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1280 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1281 } 1282 1283 /* 1284 * Attach the interface. 1285 */ 1286 if_attach(ifp); 1287 if_deferred_start_init(ifp, NULL); 1288 ether_ifattach(ifp, enaddr); 1289 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1290 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1291 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1292 sc->sc_prev.if_capenable = ifp->if_capenable; 1293 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1294 RND_TYPE_NET, RND_FLAG_DEFAULT); 1295 1296 /* 1297 * The number of bytes that must be available in 1298 * the Tx FIFO before the bus master can DMA more 1299 * data into the FIFO. 1300 */ 1301 sc->sc_tx_fill_thresh = 64 / 32; 1302 1303 /* 1304 * Start at a drain threshold of 512 bytes. We will 1305 * increase it if a DMA underrun occurs. 1306 * 1307 * XXX The minimum value of this variable should be 1308 * tuned. We may be able to improve performance 1309 * by starting with a lower value. That, however, 1310 * may trash the first few outgoing packets if the 1311 * PCI bus is saturated. 1312 */ 1313 if (sc->sc_gigabit) 1314 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1315 else 1316 sc->sc_tx_drain_thresh = 1504 / 32; 1317 1318 /* 1319 * Initialize the Rx FIFO drain threshold. 1320 * 1321 * This is in units of 8 bytes. 1322 * 1323 * We should never set this value lower than 2; 14 bytes are 1324 * required to filter the packet. 1325 */ 1326 sc->sc_rx_drain_thresh = 128 / 8; 1327 1328 #ifdef SIP_EVENT_COUNTERS 1329 /* 1330 * Attach event counters. 1331 */ 1332 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1333 NULL, device_xname(sc->sc_dev), "txsstall"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1335 NULL, device_xname(sc->sc_dev), "txdstall"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txforceintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "txdintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "txiintr"); 1342 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1343 NULL, device_xname(sc->sc_dev), "rxintr"); 1344 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1345 NULL, device_xname(sc->sc_dev), "hiberr"); 1346 if (!sc->sc_gigabit) { 1347 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1348 NULL, device_xname(sc->sc_dev), "rxpause"); 1349 } else { 1350 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "rxpause"); 1352 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "txpause"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxipsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txipsum"); 1362 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1363 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1364 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1365 NULL, device_xname(sc->sc_dev), "txudpsum"); 1366 } 1367 #endif /* SIP_EVENT_COUNTERS */ 1368 1369 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1370 pmf_class_network_register(self, ifp); 1371 else 1372 aprint_error_dev(self, "couldn't establish power handler\n"); 1373 } 1374 1375 static inline void 1376 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1377 uint64_t capenable) 1378 { 1379 u_int32_t extsts; 1380 #ifdef DEBUG 1381 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1382 #endif 1383 /* 1384 * If VLANs are enabled and the packet has a VLAN tag, set 1385 * up the descriptor to encapsulate the packet for us. 1386 * 1387 * This apparently has to be on the last descriptor of 1388 * the packet. 1389 */ 1390 1391 /* 1392 * Byte swapping is tricky. We need to provide the tag 1393 * in a network byte order. On a big-endian machine, 1394 * the byteorder is correct, but we need to swap it 1395 * anyway, because this will be undone by the outside 1396 * htole32(). That's why there must be an 1397 * unconditional swap instead of htons() inside. 1398 */ 1399 if (vlan_has_tag(m0)) { 1400 sc->sc_txdescs[lasttx].sipd_extsts |= 1401 htole32(EXTSTS_VPKT | 1402 (bswap16(vlan_get_tag(m0)) & 1403 EXTSTS_VTCI)); 1404 } 1405 1406 /* 1407 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1408 * checksumming, set up the descriptor to do this work 1409 * for us. 1410 * 1411 * This apparently has to be on the first descriptor of 1412 * the packet. 1413 * 1414 * Byte-swap constants so the compiler can optimize. 1415 */ 1416 extsts = 0; 1417 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1418 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1419 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1420 extsts |= htole32(EXTSTS_IPPKT); 1421 } 1422 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1425 extsts |= htole32(EXTSTS_TCPPKT); 1426 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1427 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1428 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1429 extsts |= htole32(EXTSTS_UDPPKT); 1430 } 1431 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1432 } 1433 1434 /* 1435 * sip_start: [ifnet interface function] 1436 * 1437 * Start packet transmission on the interface. 1438 */ 1439 static void 1440 sipcom_start(struct ifnet *ifp) 1441 { 1442 struct sip_softc *sc = ifp->if_softc; 1443 struct mbuf *m0; 1444 struct mbuf *m; 1445 struct sip_txsoft *txs; 1446 bus_dmamap_t dmamap; 1447 int error, nexttx, lasttx, seg; 1448 int ofree = sc->sc_txfree; 1449 #if 0 1450 int firsttx = sc->sc_txnext; 1451 #endif 1452 1453 /* 1454 * If we've been told to pause, don't transmit any more packets. 1455 */ 1456 if (!sc->sc_gigabit && sc->sc_paused) 1457 ifp->if_flags |= IFF_OACTIVE; 1458 1459 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1460 return; 1461 1462 /* 1463 * Loop through the send queue, setting up transmit descriptors 1464 * until we drain the queue, or use up all available transmit 1465 * descriptors. 1466 */ 1467 for (;;) { 1468 /* Get a work queue entry. */ 1469 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1470 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1471 break; 1472 } 1473 1474 /* 1475 * Grab a packet off the queue. 1476 */ 1477 IFQ_POLL(&ifp->if_snd, m0); 1478 if (m0 == NULL) 1479 break; 1480 m = NULL; 1481 1482 dmamap = txs->txs_dmamap; 1483 1484 /* 1485 * Load the DMA map. If this fails, the packet either 1486 * didn't fit in the alloted number of segments, or we 1487 * were short on resources. 1488 */ 1489 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1490 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1491 /* In the non-gigabit case, we'll copy and try again. */ 1492 if (error != 0 && !sc->sc_gigabit) { 1493 MGETHDR(m, M_DONTWAIT, MT_DATA); 1494 if (m == NULL) { 1495 printf("%s: unable to allocate Tx mbuf\n", 1496 device_xname(sc->sc_dev)); 1497 break; 1498 } 1499 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1500 if (m0->m_pkthdr.len > MHLEN) { 1501 MCLGET(m, M_DONTWAIT); 1502 if ((m->m_flags & M_EXT) == 0) { 1503 printf("%s: unable to allocate Tx " 1504 "cluster\n", 1505 device_xname(sc->sc_dev)); 1506 m_freem(m); 1507 break; 1508 } 1509 } 1510 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1511 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1512 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1513 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1514 if (error) { 1515 printf("%s: unable to load Tx buffer, error = " 1516 "%d\n", device_xname(sc->sc_dev), error); 1517 break; 1518 } 1519 } else if (error == EFBIG) { 1520 /* 1521 * For the too-many-segments case, we simply 1522 * report an error and drop the packet, 1523 * since we can't sanely copy a jumbo packet 1524 * to a single buffer. 1525 */ 1526 printf("%s: Tx packet consumes too many DMA segments, " 1527 "dropping...\n", device_xname(sc->sc_dev)); 1528 IFQ_DEQUEUE(&ifp->if_snd, m0); 1529 m_freem(m0); 1530 continue; 1531 } else if (error != 0) { 1532 /* 1533 * Short on resources, just stop for now. 1534 */ 1535 break; 1536 } 1537 1538 /* 1539 * Ensure we have enough descriptors free to describe 1540 * the packet. Note, we always reserve one descriptor 1541 * at the end of the ring as a termination point, to 1542 * prevent wrap-around. 1543 */ 1544 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1545 /* 1546 * Not enough free descriptors to transmit this 1547 * packet. We haven't committed anything yet, 1548 * so just unload the DMA map, put the packet 1549 * back on the queue, and punt. Notify the upper 1550 * layer that there are not more slots left. 1551 * 1552 * XXX We could allocate an mbuf and copy, but 1553 * XXX is it worth it? 1554 */ 1555 ifp->if_flags |= IFF_OACTIVE; 1556 bus_dmamap_unload(sc->sc_dmat, dmamap); 1557 if (m != NULL) 1558 m_freem(m); 1559 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1560 break; 1561 } 1562 1563 IFQ_DEQUEUE(&ifp->if_snd, m0); 1564 if (m != NULL) { 1565 m_freem(m0); 1566 m0 = m; 1567 } 1568 1569 /* 1570 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1571 */ 1572 1573 /* Sync the DMA map. */ 1574 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1575 BUS_DMASYNC_PREWRITE); 1576 1577 /* 1578 * Initialize the transmit descriptors. 1579 */ 1580 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1581 seg < dmamap->dm_nsegs; 1582 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1583 /* 1584 * If this is the first descriptor we're 1585 * enqueueing, don't set the OWN bit just 1586 * yet. That could cause a race condition. 1587 * We'll do it below. 1588 */ 1589 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1590 htole32(dmamap->dm_segs[seg].ds_addr); 1591 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1592 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) | 1593 CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1594 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1595 lasttx = nexttx; 1596 } 1597 1598 /* Clear the MORE bit on the last segment. */ 1599 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1600 htole32(~CMDSTS_MORE); 1601 1602 /* 1603 * If we're in the interrupt delay window, delay the 1604 * interrupt. 1605 */ 1606 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1607 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1608 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1609 htole32(CMDSTS_INTR); 1610 sc->sc_txwin = 0; 1611 } 1612 1613 if (sc->sc_gigabit) 1614 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1615 1616 /* Sync the descriptors we're using. */ 1617 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1618 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1619 1620 /* 1621 * The entire packet is set up. Give the first descrptor 1622 * to the chip now. 1623 */ 1624 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1625 htole32(CMDSTS_OWN); 1626 sip_cdtxsync(sc, sc->sc_txnext, 1, 1627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1628 1629 /* 1630 * Store a pointer to the packet so we can free it later, 1631 * and remember what txdirty will be once the packet is 1632 * done. 1633 */ 1634 txs->txs_mbuf = m0; 1635 txs->txs_firstdesc = sc->sc_txnext; 1636 txs->txs_lastdesc = lasttx; 1637 1638 /* Advance the tx pointer. */ 1639 sc->sc_txfree -= dmamap->dm_nsegs; 1640 sc->sc_txnext = nexttx; 1641 1642 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1643 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1644 1645 /* 1646 * Pass the packet to any BPF listeners. 1647 */ 1648 bpf_mtap(ifp, m0, BPF_D_OUT); 1649 } 1650 1651 if (txs == NULL || sc->sc_txfree == 0) { 1652 /* No more slots left; notify upper layer. */ 1653 ifp->if_flags |= IFF_OACTIVE; 1654 } 1655 1656 if (sc->sc_txfree != ofree) { 1657 /* 1658 * Start the transmit process. Note, the manual says 1659 * that if there are no pending transmissions in the 1660 * chip's internal queue (indicated by TXE being clear), 1661 * then the driver software must set the TXDP to the 1662 * first descriptor to be transmitted. However, if we 1663 * do this, it causes serious performance degredation on 1664 * the DP83820 under load, not setting TXDP doesn't seem 1665 * to adversely affect the SiS 900 or DP83815. 1666 * 1667 * Well, I guess it wouldn't be the first time a manual 1668 * has lied -- and they could be speaking of the NULL- 1669 * terminated descriptor list case, rather than OWN- 1670 * terminated rings. 1671 */ 1672 #if 0 1673 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1674 CR_TXE) == 0) { 1675 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1676 SIP_CDTXADDR(sc, firsttx)); 1677 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1678 } 1679 #else 1680 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1681 #endif 1682 1683 /* Set a watchdog timer in case the chip flakes out. */ 1684 /* Gigabit autonegotiation takes 5 seconds. */ 1685 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1686 } 1687 } 1688 1689 /* 1690 * sip_watchdog: [ifnet interface function] 1691 * 1692 * Watchdog timer handler. 1693 */ 1694 static void 1695 sipcom_watchdog(struct ifnet *ifp) 1696 { 1697 struct sip_softc *sc = ifp->if_softc; 1698 1699 /* 1700 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1701 * If we get a timeout, try and sweep up transmit descriptors. 1702 * If we manage to sweep them all up, ignore the lack of 1703 * interrupt. 1704 */ 1705 sipcom_txintr(sc); 1706 1707 if (sc->sc_txfree != sc->sc_ntxdesc) { 1708 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1709 ifp->if_oerrors++; 1710 1711 /* Reset the interface. */ 1712 (void) sipcom_init(ifp); 1713 } else if (ifp->if_flags & IFF_DEBUG) 1714 printf("%s: recovered from device timeout\n", 1715 device_xname(sc->sc_dev)); 1716 1717 /* Try to get more packets going. */ 1718 sipcom_start(ifp); 1719 } 1720 1721 /* If the interface is up and running, only modify the receive 1722 * filter when setting promiscuous or debug mode. Otherwise fall 1723 * through to ether_ioctl, which will reset the chip. 1724 */ 1725 static int 1726 sip_ifflags_cb(struct ethercom *ec) 1727 { 1728 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1729 == (sc)->sc_ethercom.ec_capenable) \ 1730 && ((sc)->sc_prev.is_vlan == \ 1731 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1732 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1733 struct ifnet *ifp = &ec->ec_if; 1734 struct sip_softc *sc = ifp->if_softc; 1735 int change = ifp->if_flags ^ sc->sc_if_flags; 1736 1737 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1738 !COMPARE_IC(sc, ifp)) 1739 return ENETRESET; 1740 /* Set up the receive filter. */ 1741 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1742 return 0; 1743 } 1744 1745 /* 1746 * sip_ioctl: [ifnet interface function] 1747 * 1748 * Handle control requests from the operator. 1749 */ 1750 static int 1751 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1752 { 1753 struct sip_softc *sc = ifp->if_softc; 1754 struct ifreq *ifr = (struct ifreq *)data; 1755 int s, error; 1756 1757 s = splnet(); 1758 1759 switch (cmd) { 1760 case SIOCSIFMEDIA: 1761 /* Flow control requires full-duplex mode. */ 1762 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1763 (ifr->ifr_media & IFM_FDX) == 0) 1764 ifr->ifr_media &= ~IFM_ETH_FMASK; 1765 1766 /* XXX */ 1767 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1768 ifr->ifr_media &= ~IFM_ETH_FMASK; 1769 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1770 if (sc->sc_gigabit && 1771 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1772 /* We can do both TXPAUSE and RXPAUSE. */ 1773 ifr->ifr_media |= 1774 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1775 } else if (ifr->ifr_media & IFM_FLOW) { 1776 /* 1777 * Both TXPAUSE and RXPAUSE must be set. 1778 * (SiS900 and DP83815 don't have PAUSE_ASYM 1779 * feature.) 1780 * 1781 * XXX Can SiS900 and DP83815 send PAUSE? 1782 */ 1783 ifr->ifr_media |= 1784 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1785 } 1786 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1787 } 1788 /*FALLTHROUGH*/ 1789 default: 1790 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1791 break; 1792 1793 error = 0; 1794 1795 if (cmd == SIOCSIFCAP) 1796 error = (*ifp->if_init)(ifp); 1797 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1798 ; 1799 else if (ifp->if_flags & IFF_RUNNING) { 1800 /* 1801 * Multicast list has changed; set the hardware filter 1802 * accordingly. 1803 */ 1804 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1805 } 1806 break; 1807 } 1808 1809 /* Try to get more packets going. */ 1810 sipcom_start(ifp); 1811 1812 sc->sc_if_flags = ifp->if_flags; 1813 splx(s); 1814 return (error); 1815 } 1816 1817 /* 1818 * sip_intr: 1819 * 1820 * Interrupt service routine. 1821 */ 1822 static int 1823 sipcom_intr(void *arg) 1824 { 1825 struct sip_softc *sc = arg; 1826 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1827 u_int32_t isr; 1828 int handled = 0; 1829 1830 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1831 return 0; 1832 1833 /* Disable interrupts. */ 1834 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1835 1836 for (;;) { 1837 /* Reading clears interrupt. */ 1838 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1839 if ((isr & sc->sc_imr) == 0) 1840 break; 1841 1842 rnd_add_uint32(&sc->rnd_source, isr); 1843 1844 handled = 1; 1845 1846 if ((ifp->if_flags & IFF_RUNNING) == 0) 1847 break; 1848 1849 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1850 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1851 1852 /* Grab any new packets. */ 1853 (*sc->sc_rxintr)(sc); 1854 1855 if (isr & ISR_RXORN) { 1856 printf("%s: receive FIFO overrun\n", 1857 device_xname(sc->sc_dev)); 1858 1859 /* XXX adjust rx_drain_thresh? */ 1860 } 1861 1862 if (isr & ISR_RXIDLE) { 1863 printf("%s: receive ring overrun\n", 1864 device_xname(sc->sc_dev)); 1865 1866 /* Get the receive process going again. */ 1867 bus_space_write_4(sc->sc_st, sc->sc_sh, 1868 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1869 bus_space_write_4(sc->sc_st, sc->sc_sh, 1870 SIP_CR, CR_RXE); 1871 } 1872 } 1873 1874 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1875 #ifdef SIP_EVENT_COUNTERS 1876 if (isr & ISR_TXDESC) 1877 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1878 else if (isr & ISR_TXIDLE) 1879 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1880 #endif 1881 1882 /* Sweep up transmit descriptors. */ 1883 sipcom_txintr(sc); 1884 1885 if (isr & ISR_TXURN) { 1886 u_int32_t thresh; 1887 int txfifo_size = (sc->sc_gigabit) 1888 ? DP83820_SIP_TXFIFO_SIZE 1889 : OTHER_SIP_TXFIFO_SIZE; 1890 1891 printf("%s: transmit FIFO underrun", 1892 device_xname(sc->sc_dev)); 1893 thresh = sc->sc_tx_drain_thresh + 1; 1894 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1895 && (thresh * 32) <= (txfifo_size - 1896 (sc->sc_tx_fill_thresh * 32))) { 1897 printf("; increasing Tx drain " 1898 "threshold to %u bytes\n", 1899 thresh * 32); 1900 sc->sc_tx_drain_thresh = thresh; 1901 (void) sipcom_init(ifp); 1902 } else { 1903 (void) sipcom_init(ifp); 1904 printf("\n"); 1905 } 1906 } 1907 } 1908 1909 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1910 if (isr & ISR_PAUSE_ST) { 1911 sc->sc_paused = 1; 1912 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1913 ifp->if_flags |= IFF_OACTIVE; 1914 } 1915 if (isr & ISR_PAUSE_END) { 1916 sc->sc_paused = 0; 1917 ifp->if_flags &= ~IFF_OACTIVE; 1918 } 1919 } 1920 1921 if (isr & ISR_HIBERR) { 1922 int want_init = 0; 1923 1924 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1925 1926 #define PRINTERR(bit, str) \ 1927 do { \ 1928 if ((isr & (bit)) != 0) { \ 1929 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1930 printf("%s: %s\n", \ 1931 device_xname(sc->sc_dev), str); \ 1932 want_init = 1; \ 1933 } \ 1934 } while (/*CONSTCOND*/0) 1935 1936 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1937 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1938 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1939 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1940 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1941 /* 1942 * Ignore: 1943 * Tx reset complete 1944 * Rx reset complete 1945 */ 1946 if (want_init) 1947 (void) sipcom_init(ifp); 1948 #undef PRINTERR 1949 } 1950 } 1951 1952 /* Re-enable interrupts. */ 1953 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1954 1955 /* Try to get more packets going. */ 1956 if_schedule_deferred_start(ifp); 1957 1958 return (handled); 1959 } 1960 1961 /* 1962 * sip_txintr: 1963 * 1964 * Helper; handle transmit interrupts. 1965 */ 1966 static void 1967 sipcom_txintr(struct sip_softc *sc) 1968 { 1969 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1970 struct sip_txsoft *txs; 1971 u_int32_t cmdsts; 1972 1973 if (sc->sc_paused == 0) 1974 ifp->if_flags &= ~IFF_OACTIVE; 1975 1976 /* 1977 * Go through our Tx list and free mbufs for those 1978 * frames which have been transmitted. 1979 */ 1980 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1981 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1982 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1983 1984 cmdsts = le32toh(*sipd_cmdsts(sc, 1985 &sc->sc_txdescs[txs->txs_lastdesc])); 1986 if (cmdsts & CMDSTS_OWN) 1987 break; 1988 1989 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1990 1991 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1992 1993 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1994 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1995 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1996 m_freem(txs->txs_mbuf); 1997 txs->txs_mbuf = NULL; 1998 1999 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2000 2001 /* 2002 * Check for errors and collisions. 2003 */ 2004 if (cmdsts & 2005 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 2006 ifp->if_oerrors++; 2007 if (cmdsts & CMDSTS_Tx_EC) 2008 ifp->if_collisions += 16; 2009 if (ifp->if_flags & IFF_DEBUG) { 2010 if (cmdsts & CMDSTS_Tx_ED) 2011 printf("%s: excessive deferral\n", 2012 device_xname(sc->sc_dev)); 2013 if (cmdsts & CMDSTS_Tx_EC) 2014 printf("%s: excessive collisions\n", 2015 device_xname(sc->sc_dev)); 2016 } 2017 } else { 2018 /* Packet was transmitted successfully. */ 2019 ifp->if_opackets++; 2020 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2021 } 2022 } 2023 2024 /* 2025 * If there are no more pending transmissions, cancel the watchdog 2026 * timer. 2027 */ 2028 if (txs == NULL) { 2029 ifp->if_timer = 0; 2030 sc->sc_txwin = 0; 2031 } 2032 } 2033 2034 /* 2035 * gsip_rxintr: 2036 * 2037 * Helper; handle receive interrupts on gigabit parts. 2038 */ 2039 static void 2040 gsip_rxintr(struct sip_softc *sc) 2041 { 2042 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2043 struct sip_rxsoft *rxs; 2044 struct mbuf *m; 2045 u_int32_t cmdsts, extsts; 2046 int i, len; 2047 2048 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2049 rxs = &sc->sc_rxsoft[i]; 2050 2051 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2052 2053 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2054 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2055 len = CMDSTS_SIZE(sc, cmdsts); 2056 2057 /* 2058 * NOTE: OWN is set if owned by _consumer_. We're the 2059 * consumer of the receive ring, so if the bit is clear, 2060 * we have processed all of the packets. 2061 */ 2062 if ((cmdsts & CMDSTS_OWN) == 0) { 2063 /* 2064 * We have processed all of the receive buffers. 2065 */ 2066 break; 2067 } 2068 2069 if (__predict_false(sc->sc_rxdiscard)) { 2070 sip_init_rxdesc(sc, i); 2071 if ((cmdsts & CMDSTS_MORE) == 0) { 2072 /* Reset our state. */ 2073 sc->sc_rxdiscard = 0; 2074 } 2075 continue; 2076 } 2077 2078 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2079 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2080 2081 m = rxs->rxs_mbuf; 2082 2083 /* 2084 * Add a new receive buffer to the ring. 2085 */ 2086 if (sipcom_add_rxbuf(sc, i) != 0) { 2087 /* 2088 * Failed, throw away what we've done so 2089 * far, and discard the rest of the packet. 2090 */ 2091 ifp->if_ierrors++; 2092 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2093 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2094 sip_init_rxdesc(sc, i); 2095 if (cmdsts & CMDSTS_MORE) 2096 sc->sc_rxdiscard = 1; 2097 if (sc->sc_rxhead != NULL) 2098 m_freem(sc->sc_rxhead); 2099 sip_rxchain_reset(sc); 2100 continue; 2101 } 2102 2103 sip_rxchain_link(sc, m); 2104 2105 m->m_len = len; 2106 2107 /* 2108 * If this is not the end of the packet, keep 2109 * looking. 2110 */ 2111 if (cmdsts & CMDSTS_MORE) { 2112 sc->sc_rxlen += len; 2113 continue; 2114 } 2115 2116 /* 2117 * Okay, we have the entire packet now. The chip includes 2118 * the FCS, so we need to trim it. 2119 */ 2120 m->m_len -= ETHER_CRC_LEN; 2121 2122 *sc->sc_rxtailp = NULL; 2123 len = m->m_len + sc->sc_rxlen; 2124 m = sc->sc_rxhead; 2125 2126 sip_rxchain_reset(sc); 2127 2128 /* 2129 * If an error occurred, update stats and drop the packet. 2130 */ 2131 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2132 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2133 ifp->if_ierrors++; 2134 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2135 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2136 /* Receive overrun handled elsewhere. */ 2137 printf("%s: receive descriptor error\n", 2138 device_xname(sc->sc_dev)); 2139 } 2140 #define PRINTERR(bit, str) \ 2141 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2142 (cmdsts & (bit)) != 0) \ 2143 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2144 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2145 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2146 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2147 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2148 #undef PRINTERR 2149 m_freem(m); 2150 continue; 2151 } 2152 2153 /* 2154 * If the packet is small enough to fit in a 2155 * single header mbuf, allocate one and copy 2156 * the data into it. This greatly reduces 2157 * memory consumption when we receive lots 2158 * of small packets. 2159 */ 2160 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2161 struct mbuf *nm; 2162 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2163 if (nm == NULL) { 2164 ifp->if_ierrors++; 2165 m_freem(m); 2166 continue; 2167 } 2168 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2169 nm->m_data += 2; 2170 nm->m_pkthdr.len = nm->m_len = len; 2171 m_copydata(m, 0, len, mtod(nm, void *)); 2172 m_freem(m); 2173 m = nm; 2174 } 2175 #ifndef __NO_STRICT_ALIGNMENT 2176 else { 2177 /* 2178 * The DP83820's receive buffers must be 4-byte 2179 * aligned. But this means that the data after 2180 * the Ethernet header is misaligned. To compensate, 2181 * we have artificially shortened the buffer size 2182 * in the descriptor, and we do an overlapping copy 2183 * of the data two bytes further in (in the first 2184 * buffer of the chain only). 2185 */ 2186 memmove(mtod(m, char *) + 2, mtod(m, void *), 2187 m->m_len); 2188 m->m_data += 2; 2189 } 2190 #endif /* ! __NO_STRICT_ALIGNMENT */ 2191 2192 /* 2193 * If VLANs are enabled, VLAN packets have been unwrapped 2194 * for us. Associate the tag with the packet. 2195 */ 2196 2197 /* 2198 * Again, byte swapping is tricky. Hardware provided 2199 * the tag in the network byte order, but extsts was 2200 * passed through le32toh() in the meantime. On a 2201 * big-endian machine, we need to swap it again. On a 2202 * little-endian machine, we need to convert from the 2203 * network to host byte order. This means that we must 2204 * swap it in any case, so unconditional swap instead 2205 * of htons() is used. 2206 */ 2207 if ((extsts & EXTSTS_VPKT) != 0) { 2208 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2209 } 2210 2211 /* 2212 * Set the incoming checksum information for the 2213 * packet. 2214 */ 2215 if ((extsts & EXTSTS_IPPKT) != 0) { 2216 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2217 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2218 if (extsts & EXTSTS_Rx_IPERR) 2219 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2220 if (extsts & EXTSTS_TCPPKT) { 2221 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2222 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2223 if (extsts & EXTSTS_Rx_TCPERR) 2224 m->m_pkthdr.csum_flags |= 2225 M_CSUM_TCP_UDP_BAD; 2226 } else if (extsts & EXTSTS_UDPPKT) { 2227 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2228 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2229 if (extsts & EXTSTS_Rx_UDPERR) 2230 m->m_pkthdr.csum_flags |= 2231 M_CSUM_TCP_UDP_BAD; 2232 } 2233 } 2234 2235 m_set_rcvif(m, ifp); 2236 m->m_pkthdr.len = len; 2237 2238 /* Pass it on. */ 2239 if_percpuq_enqueue(ifp->if_percpuq, m); 2240 } 2241 2242 /* Update the receive pointer. */ 2243 sc->sc_rxptr = i; 2244 } 2245 2246 /* 2247 * sip_rxintr: 2248 * 2249 * Helper; handle receive interrupts on 10/100 parts. 2250 */ 2251 static void 2252 sip_rxintr(struct sip_softc *sc) 2253 { 2254 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2255 struct sip_rxsoft *rxs; 2256 struct mbuf *m; 2257 u_int32_t cmdsts; 2258 int i, len; 2259 2260 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2261 rxs = &sc->sc_rxsoft[i]; 2262 2263 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2264 2265 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2266 2267 /* 2268 * NOTE: OWN is set if owned by _consumer_. We're the 2269 * consumer of the receive ring, so if the bit is clear, 2270 * we have processed all of the packets. 2271 */ 2272 if ((cmdsts & CMDSTS_OWN) == 0) { 2273 /* 2274 * We have processed all of the receive buffers. 2275 */ 2276 break; 2277 } 2278 2279 /* 2280 * If any collisions were seen on the wire, count one. 2281 */ 2282 if (cmdsts & CMDSTS_Rx_COL) 2283 ifp->if_collisions++; 2284 2285 /* 2286 * If an error occurred, update stats, clear the status 2287 * word, and leave the packet buffer in place. It will 2288 * simply be reused the next time the ring comes around. 2289 */ 2290 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2291 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2292 ifp->if_ierrors++; 2293 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2294 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2295 /* Receive overrun handled elsewhere. */ 2296 printf("%s: receive descriptor error\n", 2297 device_xname(sc->sc_dev)); 2298 } 2299 #define PRINTERR(bit, str) \ 2300 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2301 (cmdsts & (bit)) != 0) \ 2302 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2303 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2304 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2305 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2306 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2307 #undef PRINTERR 2308 sip_init_rxdesc(sc, i); 2309 continue; 2310 } 2311 2312 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2313 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2314 2315 /* 2316 * No errors; receive the packet. Note, the SiS 900 2317 * includes the CRC with every packet. 2318 */ 2319 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2320 2321 #ifdef __NO_STRICT_ALIGNMENT 2322 /* 2323 * If the packet is small enough to fit in a 2324 * single header mbuf, allocate one and copy 2325 * the data into it. This greatly reduces 2326 * memory consumption when we receive lots 2327 * of small packets. 2328 * 2329 * Otherwise, we add a new buffer to the receive 2330 * chain. If this fails, we drop the packet and 2331 * recycle the old buffer. 2332 */ 2333 if (sip_copy_small != 0 && len <= MHLEN) { 2334 MGETHDR(m, M_DONTWAIT, MT_DATA); 2335 if (m == NULL) 2336 goto dropit; 2337 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2338 memcpy(mtod(m, void *), 2339 mtod(rxs->rxs_mbuf, void *), len); 2340 sip_init_rxdesc(sc, i); 2341 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2342 rxs->rxs_dmamap->dm_mapsize, 2343 BUS_DMASYNC_PREREAD); 2344 } else { 2345 m = rxs->rxs_mbuf; 2346 if (sipcom_add_rxbuf(sc, i) != 0) { 2347 dropit: 2348 ifp->if_ierrors++; 2349 sip_init_rxdesc(sc, i); 2350 bus_dmamap_sync(sc->sc_dmat, 2351 rxs->rxs_dmamap, 0, 2352 rxs->rxs_dmamap->dm_mapsize, 2353 BUS_DMASYNC_PREREAD); 2354 continue; 2355 } 2356 } 2357 #else 2358 /* 2359 * The SiS 900's receive buffers must be 4-byte aligned. 2360 * But this means that the data after the Ethernet header 2361 * is misaligned. We must allocate a new buffer and 2362 * copy the data, shifted forward 2 bytes. 2363 */ 2364 MGETHDR(m, M_DONTWAIT, MT_DATA); 2365 if (m == NULL) { 2366 dropit: 2367 ifp->if_ierrors++; 2368 sip_init_rxdesc(sc, i); 2369 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2370 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2371 continue; 2372 } 2373 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2374 if (len > (MHLEN - 2)) { 2375 MCLGET(m, M_DONTWAIT); 2376 if ((m->m_flags & M_EXT) == 0) { 2377 m_freem(m); 2378 goto dropit; 2379 } 2380 } 2381 m->m_data += 2; 2382 2383 /* 2384 * Note that we use clusters for incoming frames, so the 2385 * buffer is virtually contiguous. 2386 */ 2387 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2388 2389 /* Allow the receive descriptor to continue using its mbuf. */ 2390 sip_init_rxdesc(sc, i); 2391 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2392 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2393 #endif /* __NO_STRICT_ALIGNMENT */ 2394 2395 m_set_rcvif(m, ifp); 2396 m->m_pkthdr.len = m->m_len = len; 2397 2398 /* Pass it on. */ 2399 if_percpuq_enqueue(ifp->if_percpuq, m); 2400 } 2401 2402 /* Update the receive pointer. */ 2403 sc->sc_rxptr = i; 2404 } 2405 2406 /* 2407 * sip_tick: 2408 * 2409 * One second timer, used to tick the MII. 2410 */ 2411 static void 2412 sipcom_tick(void *arg) 2413 { 2414 struct sip_softc *sc = arg; 2415 int s; 2416 2417 s = splnet(); 2418 #ifdef SIP_EVENT_COUNTERS 2419 if (sc->sc_gigabit) { 2420 /* Read PAUSE related counts from MIB registers. */ 2421 sc->sc_ev_rxpause.ev_count += 2422 bus_space_read_4(sc->sc_st, sc->sc_sh, 2423 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2424 sc->sc_ev_txpause.ev_count += 2425 bus_space_read_4(sc->sc_st, sc->sc_sh, 2426 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2427 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2428 } 2429 #endif /* SIP_EVENT_COUNTERS */ 2430 mii_tick(&sc->sc_mii); 2431 splx(s); 2432 2433 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2434 } 2435 2436 /* 2437 * sip_reset: 2438 * 2439 * Perform a soft reset on the SiS 900. 2440 */ 2441 static bool 2442 sipcom_reset(struct sip_softc *sc) 2443 { 2444 bus_space_tag_t st = sc->sc_st; 2445 bus_space_handle_t sh = sc->sc_sh; 2446 int i; 2447 2448 bus_space_write_4(st, sh, SIP_IER, 0); 2449 bus_space_write_4(st, sh, SIP_IMR, 0); 2450 bus_space_write_4(st, sh, SIP_RFCR, 0); 2451 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2452 2453 for (i = 0; i < SIP_TIMEOUT; i++) { 2454 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2455 break; 2456 delay(2); 2457 } 2458 2459 if (i == SIP_TIMEOUT) { 2460 printf("%s: reset failed to complete\n", 2461 device_xname(sc->sc_dev)); 2462 return false; 2463 } 2464 2465 delay(1000); 2466 2467 if (sc->sc_gigabit) { 2468 /* 2469 * Set the general purpose I/O bits. Do it here in case we 2470 * need to have GPIO set up to talk to the media interface. 2471 */ 2472 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2473 delay(1000); 2474 } 2475 return true; 2476 } 2477 2478 static void 2479 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2480 { 2481 u_int32_t reg; 2482 bus_space_tag_t st = sc->sc_st; 2483 bus_space_handle_t sh = sc->sc_sh; 2484 /* 2485 * Initialize the VLAN/IP receive control register. 2486 * We enable checksum computation on all incoming 2487 * packets, and do not reject packets w/ bad checksums. 2488 */ 2489 reg = 0; 2490 if (capenable & 2491 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2492 reg |= VRCR_IPEN; 2493 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2494 reg |= VRCR_VTDEN|VRCR_VTREN; 2495 bus_space_write_4(st, sh, SIP_VRCR, reg); 2496 2497 /* 2498 * Initialize the VLAN/IP transmit control register. 2499 * We enable outgoing checksum computation on a 2500 * per-packet basis. 2501 */ 2502 reg = 0; 2503 if (capenable & 2504 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2505 reg |= VTCR_PPCHK; 2506 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2507 reg |= VTCR_VPPTI; 2508 bus_space_write_4(st, sh, SIP_VTCR, reg); 2509 2510 /* 2511 * If we're using VLANs, initialize the VLAN data register. 2512 * To understand why we bswap the VLAN Ethertype, see section 2513 * 4.2.36 of the DP83820 manual. 2514 */ 2515 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2516 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2517 } 2518 2519 /* 2520 * sip_init: [ ifnet interface function ] 2521 * 2522 * Initialize the interface. Must be called at splnet(). 2523 */ 2524 static int 2525 sipcom_init(struct ifnet *ifp) 2526 { 2527 struct sip_softc *sc = ifp->if_softc; 2528 bus_space_tag_t st = sc->sc_st; 2529 bus_space_handle_t sh = sc->sc_sh; 2530 struct sip_txsoft *txs; 2531 struct sip_rxsoft *rxs; 2532 struct sip_desc *sipd; 2533 int i, error = 0; 2534 2535 if (device_is_active(sc->sc_dev)) { 2536 /* 2537 * Cancel any pending I/O. 2538 */ 2539 sipcom_stop(ifp, 0); 2540 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2541 !device_is_active(sc->sc_dev)) 2542 return 0; 2543 2544 /* 2545 * Reset the chip to a known state. 2546 */ 2547 if (!sipcom_reset(sc)) 2548 return EBUSY; 2549 2550 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2551 /* 2552 * DP83815 manual, page 78: 2553 * 4.4 Recommended Registers Configuration 2554 * For optimum performance of the DP83815, version noted 2555 * as DP83815CVNG (SRR = 203h), the listed register 2556 * modifications must be followed in sequence... 2557 * 2558 * It's not clear if this should be 302h or 203h because that 2559 * chip name is listed as SRR 302h in the description of the 2560 * SRR register. However, my revision 302h DP83815 on the 2561 * Netgear FA311 purchased in 02/2001 needs these settings 2562 * to avoid tons of errors in AcceptPerfectMatch (non- 2563 * IFF_PROMISC) mode. I do not know if other revisions need 2564 * this set or not. [briggs -- 09 March 2001] 2565 * 2566 * Note that only the low-order 12 bits of 0xe4 are documented 2567 * and that this sets reserved bits in that register. 2568 */ 2569 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2570 2571 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2572 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2573 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2574 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2575 2576 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2577 } 2578 2579 /* 2580 * Initialize the transmit descriptor ring. 2581 */ 2582 for (i = 0; i < sc->sc_ntxdesc; i++) { 2583 sipd = &sc->sc_txdescs[i]; 2584 memset(sipd, 0, sizeof(struct sip_desc)); 2585 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2586 } 2587 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2588 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2589 sc->sc_txfree = sc->sc_ntxdesc; 2590 sc->sc_txnext = 0; 2591 sc->sc_txwin = 0; 2592 2593 /* 2594 * Initialize the transmit job descriptors. 2595 */ 2596 SIMPLEQ_INIT(&sc->sc_txfreeq); 2597 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2598 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2599 txs = &sc->sc_txsoft[i]; 2600 txs->txs_mbuf = NULL; 2601 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2602 } 2603 2604 /* 2605 * Initialize the receive descriptor and receive job 2606 * descriptor rings. 2607 */ 2608 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2609 rxs = &sc->sc_rxsoft[i]; 2610 if (rxs->rxs_mbuf == NULL) { 2611 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2612 printf("%s: unable to allocate or map rx " 2613 "buffer %d, error = %d\n", 2614 device_xname(sc->sc_dev), i, error); 2615 /* 2616 * XXX Should attempt to run with fewer receive 2617 * XXX buffers instead of just failing. 2618 */ 2619 sipcom_rxdrain(sc); 2620 goto out; 2621 } 2622 } else 2623 sip_init_rxdesc(sc, i); 2624 } 2625 sc->sc_rxptr = 0; 2626 sc->sc_rxdiscard = 0; 2627 sip_rxchain_reset(sc); 2628 2629 /* 2630 * Set the configuration register; it's already initialized 2631 * in sip_attach(). 2632 */ 2633 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2634 2635 /* 2636 * Initialize the prototype TXCFG register. 2637 */ 2638 if (sc->sc_gigabit) { 2639 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2640 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2641 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2642 SIP_SIS900_REV(sc, SIS_REV_960) || 2643 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2644 (sc->sc_cfg & CFG_EDBMASTEN)) { 2645 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2646 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2647 } else { 2648 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2649 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2650 } 2651 2652 sc->sc_txcfg |= TXCFG_ATP | 2653 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2654 sc->sc_tx_drain_thresh; 2655 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2656 2657 /* 2658 * Initialize the receive drain threshold if we have never 2659 * done so. 2660 */ 2661 if (sc->sc_rx_drain_thresh == 0) { 2662 /* 2663 * XXX This value should be tuned. This is set to the 2664 * maximum of 248 bytes, and we may be able to improve 2665 * performance by decreasing it (although we should never 2666 * set this value lower than 2; 14 bytes are required to 2667 * filter the packet). 2668 */ 2669 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2670 } 2671 2672 /* 2673 * Initialize the prototype RXCFG register. 2674 */ 2675 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2676 /* 2677 * Accept long packets (including FCS) so we can handle 2678 * 802.1q-tagged frames and jumbo frames properly. 2679 */ 2680 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2681 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2682 sc->sc_rxcfg |= RXCFG_ALP; 2683 2684 /* 2685 * Checksum offloading is disabled if the user selects an MTU 2686 * larger than 8109. (FreeBSD says 8152, but there is emperical 2687 * evidence that >8109 does not work on some boards, such as the 2688 * Planex GN-1000TE). 2689 */ 2690 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2691 (ifp->if_capenable & 2692 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2693 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2694 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2695 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2696 "disabled.\n", device_xname(sc->sc_dev)); 2697 ifp->if_capenable &= 2698 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2699 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2700 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2701 ifp->if_csum_flags_tx = 0; 2702 ifp->if_csum_flags_rx = 0; 2703 } 2704 2705 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2706 2707 if (sc->sc_gigabit) 2708 sipcom_dp83820_init(sc, ifp->if_capenable); 2709 2710 /* 2711 * Give the transmit and receive rings to the chip. 2712 */ 2713 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2714 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2715 2716 /* 2717 * Initialize the interrupt mask. 2718 */ 2719 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2720 sc->sc_bits.b_isr_sserr | 2721 sc->sc_bits.b_isr_rmabt | 2722 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2723 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2724 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2725 2726 /* Set up the receive filter. */ 2727 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2728 2729 /* 2730 * Tune sc_rx_flow_thresh. 2731 * XXX "More than 8KB" is too short for jumbo frames. 2732 * XXX TODO: Threshold value should be user-settable. 2733 */ 2734 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2735 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2736 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2737 2738 /* 2739 * Set the current media. Do this after initializing the prototype 2740 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2741 * control. 2742 */ 2743 if ((error = ether_mediachange(ifp)) != 0) 2744 goto out; 2745 2746 /* 2747 * Set the interrupt hold-off timer to 100us. 2748 */ 2749 if (sc->sc_gigabit) 2750 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2751 2752 /* 2753 * Enable interrupts. 2754 */ 2755 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2756 2757 /* 2758 * Start the transmit and receive processes. 2759 */ 2760 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2761 2762 /* 2763 * Start the one second MII clock. 2764 */ 2765 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2766 2767 /* 2768 * ...all done! 2769 */ 2770 ifp->if_flags |= IFF_RUNNING; 2771 ifp->if_flags &= ~IFF_OACTIVE; 2772 sc->sc_if_flags = ifp->if_flags; 2773 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2774 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2775 sc->sc_prev.if_capenable = ifp->if_capenable; 2776 2777 out: 2778 if (error) 2779 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2780 return (error); 2781 } 2782 2783 /* 2784 * sip_drain: 2785 * 2786 * Drain the receive queue. 2787 */ 2788 static void 2789 sipcom_rxdrain(struct sip_softc *sc) 2790 { 2791 struct sip_rxsoft *rxs; 2792 int i; 2793 2794 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2795 rxs = &sc->sc_rxsoft[i]; 2796 if (rxs->rxs_mbuf != NULL) { 2797 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2798 m_freem(rxs->rxs_mbuf); 2799 rxs->rxs_mbuf = NULL; 2800 } 2801 } 2802 } 2803 2804 /* 2805 * sip_stop: [ ifnet interface function ] 2806 * 2807 * Stop transmission on the interface. 2808 */ 2809 static void 2810 sipcom_stop(struct ifnet *ifp, int disable) 2811 { 2812 struct sip_softc *sc = ifp->if_softc; 2813 bus_space_tag_t st = sc->sc_st; 2814 bus_space_handle_t sh = sc->sc_sh; 2815 struct sip_txsoft *txs; 2816 u_int32_t cmdsts = 0; /* DEBUG */ 2817 2818 /* 2819 * Stop the one second clock. 2820 */ 2821 callout_stop(&sc->sc_tick_ch); 2822 2823 /* Down the MII. */ 2824 mii_down(&sc->sc_mii); 2825 2826 if (device_is_active(sc->sc_dev)) { 2827 /* 2828 * Disable interrupts. 2829 */ 2830 bus_space_write_4(st, sh, SIP_IER, 0); 2831 2832 /* 2833 * Stop receiver and transmitter. 2834 */ 2835 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2836 } 2837 2838 /* 2839 * Release any queued transmit buffers. 2840 */ 2841 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2842 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2843 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2844 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2845 CMDSTS_INTR) == 0) 2846 printf("%s: sip_stop: last descriptor does not " 2847 "have INTR bit set\n", device_xname(sc->sc_dev)); 2848 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2849 #ifdef DIAGNOSTIC 2850 if (txs->txs_mbuf == NULL) { 2851 printf("%s: dirty txsoft with no mbuf chain\n", 2852 device_xname(sc->sc_dev)); 2853 panic("sip_stop"); 2854 } 2855 #endif 2856 cmdsts |= /* DEBUG */ 2857 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2858 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2859 m_freem(txs->txs_mbuf); 2860 txs->txs_mbuf = NULL; 2861 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2862 } 2863 2864 /* 2865 * Mark the interface down and cancel the watchdog timer. 2866 */ 2867 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2868 ifp->if_timer = 0; 2869 2870 if (disable) 2871 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2872 2873 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2874 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2875 printf("%s: sip_stop: no INTR bits set in dirty tx " 2876 "descriptors\n", device_xname(sc->sc_dev)); 2877 } 2878 2879 /* 2880 * sip_read_eeprom: 2881 * 2882 * Read data from the serial EEPROM. 2883 */ 2884 static void 2885 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2886 u_int16_t *data) 2887 { 2888 bus_space_tag_t st = sc->sc_st; 2889 bus_space_handle_t sh = sc->sc_sh; 2890 u_int16_t reg; 2891 int i, x; 2892 2893 for (i = 0; i < wordcnt; i++) { 2894 /* Send CHIP SELECT. */ 2895 reg = EROMAR_EECS; 2896 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2897 2898 /* Shift in the READ opcode. */ 2899 for (x = 3; x > 0; x--) { 2900 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2901 reg |= EROMAR_EEDI; 2902 else 2903 reg &= ~EROMAR_EEDI; 2904 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2905 bus_space_write_4(st, sh, SIP_EROMAR, 2906 reg | EROMAR_EESK); 2907 delay(4); 2908 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2909 delay(4); 2910 } 2911 2912 /* Shift in address. */ 2913 for (x = 6; x > 0; x--) { 2914 if ((word + i) & (1 << (x - 1))) 2915 reg |= EROMAR_EEDI; 2916 else 2917 reg &= ~EROMAR_EEDI; 2918 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2919 bus_space_write_4(st, sh, SIP_EROMAR, 2920 reg | EROMAR_EESK); 2921 delay(4); 2922 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2923 delay(4); 2924 } 2925 2926 /* Shift out data. */ 2927 reg = EROMAR_EECS; 2928 data[i] = 0; 2929 for (x = 16; x > 0; x--) { 2930 bus_space_write_4(st, sh, SIP_EROMAR, 2931 reg | EROMAR_EESK); 2932 delay(4); 2933 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2934 data[i] |= (1 << (x - 1)); 2935 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2936 delay(4); 2937 } 2938 2939 /* Clear CHIP SELECT. */ 2940 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2941 delay(4); 2942 } 2943 } 2944 2945 /* 2946 * sipcom_add_rxbuf: 2947 * 2948 * Add a receive buffer to the indicated descriptor. 2949 */ 2950 static int 2951 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2952 { 2953 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2954 struct mbuf *m; 2955 int error; 2956 2957 MGETHDR(m, M_DONTWAIT, MT_DATA); 2958 if (m == NULL) 2959 return (ENOBUFS); 2960 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2961 2962 MCLGET(m, M_DONTWAIT); 2963 if ((m->m_flags & M_EXT) == 0) { 2964 m_freem(m); 2965 return (ENOBUFS); 2966 } 2967 2968 /* XXX I don't believe this is necessary. --dyoung */ 2969 if (sc->sc_gigabit) 2970 m->m_len = sc->sc_parm->p_rxbuf_len; 2971 2972 if (rxs->rxs_mbuf != NULL) 2973 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2974 2975 rxs->rxs_mbuf = m; 2976 2977 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2978 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2979 BUS_DMA_READ|BUS_DMA_NOWAIT); 2980 if (error) { 2981 printf("%s: can't load rx DMA map %d, error = %d\n", 2982 device_xname(sc->sc_dev), idx, error); 2983 panic("%s", __func__); /* XXX */ 2984 } 2985 2986 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2987 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2988 2989 sip_init_rxdesc(sc, idx); 2990 2991 return (0); 2992 } 2993 2994 /* 2995 * sip_sis900_set_filter: 2996 * 2997 * Set up the receive filter. 2998 */ 2999 static void 3000 sipcom_sis900_set_filter(struct sip_softc *sc) 3001 { 3002 bus_space_tag_t st = sc->sc_st; 3003 bus_space_handle_t sh = sc->sc_sh; 3004 struct ethercom *ec = &sc->sc_ethercom; 3005 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3006 struct ether_multi *enm; 3007 const u_int8_t *cp; 3008 struct ether_multistep step; 3009 u_int32_t crc, mchash[16]; 3010 3011 /* 3012 * Initialize the prototype RFCR. 3013 */ 3014 sc->sc_rfcr = RFCR_RFEN; 3015 if (ifp->if_flags & IFF_BROADCAST) 3016 sc->sc_rfcr |= RFCR_AAB; 3017 if (ifp->if_flags & IFF_PROMISC) { 3018 sc->sc_rfcr |= RFCR_AAP; 3019 goto allmulti; 3020 } 3021 3022 /* 3023 * Set up the multicast address filter by passing all multicast 3024 * addresses through a CRC generator, and then using the high-order 3025 * 6 bits as an index into the 128 bit multicast hash table (only 3026 * the lower 16 bits of each 32 bit multicast hash register are 3027 * valid). The high order bits select the register, while the 3028 * rest of the bits select the bit within the register. 3029 */ 3030 3031 memset(mchash, 0, sizeof(mchash)); 3032 3033 /* 3034 * SiS900 (at least SiS963) requires us to register the address of 3035 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3036 */ 3037 crc = 0x0ed423f9; 3038 3039 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3040 SIP_SIS900_REV(sc, SIS_REV_960) || 3041 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3042 /* Just want the 8 most significant bits. */ 3043 crc >>= 24; 3044 } else { 3045 /* Just want the 7 most significant bits. */ 3046 crc >>= 25; 3047 } 3048 3049 /* Set the corresponding bit in the hash table. */ 3050 mchash[crc >> 4] |= 1 << (crc & 0xf); 3051 3052 ETHER_FIRST_MULTI(step, ec, enm); 3053 while (enm != NULL) { 3054 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3055 /* 3056 * We must listen to a range of multicast addresses. 3057 * For now, just accept all multicasts, rather than 3058 * trying to set only those filter bits needed to match 3059 * the range. (At this time, the only use of address 3060 * ranges is for IP multicast routing, for which the 3061 * range is big enough to require all bits set.) 3062 */ 3063 goto allmulti; 3064 } 3065 3066 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3067 3068 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3069 SIP_SIS900_REV(sc, SIS_REV_960) || 3070 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3071 /* Just want the 8 most significant bits. */ 3072 crc >>= 24; 3073 } else { 3074 /* Just want the 7 most significant bits. */ 3075 crc >>= 25; 3076 } 3077 3078 /* Set the corresponding bit in the hash table. */ 3079 mchash[crc >> 4] |= 1 << (crc & 0xf); 3080 3081 ETHER_NEXT_MULTI(step, enm); 3082 } 3083 3084 ifp->if_flags &= ~IFF_ALLMULTI; 3085 goto setit; 3086 3087 allmulti: 3088 ifp->if_flags |= IFF_ALLMULTI; 3089 sc->sc_rfcr |= RFCR_AAM; 3090 3091 setit: 3092 #define FILTER_EMIT(addr, data) \ 3093 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3094 delay(1); \ 3095 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3096 delay(1) 3097 3098 /* 3099 * Disable receive filter, and program the node address. 3100 */ 3101 cp = CLLADDR(ifp->if_sadl); 3102 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3103 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3104 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3105 3106 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3107 /* 3108 * Program the multicast hash table. 3109 */ 3110 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3111 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3112 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3113 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3114 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3115 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3116 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3117 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3118 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3119 SIP_SIS900_REV(sc, SIS_REV_960) || 3120 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3121 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3122 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3123 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3124 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3125 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3126 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3127 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3128 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3129 } 3130 } 3131 #undef FILTER_EMIT 3132 3133 /* 3134 * Re-enable the receiver filter. 3135 */ 3136 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3137 } 3138 3139 /* 3140 * sip_dp83815_set_filter: 3141 * 3142 * Set up the receive filter. 3143 */ 3144 static void 3145 sipcom_dp83815_set_filter(struct sip_softc *sc) 3146 { 3147 bus_space_tag_t st = sc->sc_st; 3148 bus_space_handle_t sh = sc->sc_sh; 3149 struct ethercom *ec = &sc->sc_ethercom; 3150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3151 struct ether_multi *enm; 3152 const u_int8_t *cp; 3153 struct ether_multistep step; 3154 u_int32_t crc, hash, slot, bit; 3155 #define MCHASH_NWORDS_83820 128 3156 #define MCHASH_NWORDS_83815 32 3157 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3158 u_int16_t mchash[MCHASH_NWORDS]; 3159 int i; 3160 3161 /* 3162 * Initialize the prototype RFCR. 3163 * Enable the receive filter, and accept on 3164 * Perfect (destination address) Match 3165 * If IFF_BROADCAST, also accept all broadcast packets. 3166 * If IFF_PROMISC, accept all unicast packets (and later, set 3167 * IFF_ALLMULTI and accept all multicast, too). 3168 */ 3169 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3170 if (ifp->if_flags & IFF_BROADCAST) 3171 sc->sc_rfcr |= RFCR_AAB; 3172 if (ifp->if_flags & IFF_PROMISC) { 3173 sc->sc_rfcr |= RFCR_AAP; 3174 goto allmulti; 3175 } 3176 3177 /* 3178 * Set up the DP83820/DP83815 multicast address filter by 3179 * passing all multicast addresses through a CRC generator, 3180 * and then using the high-order 11/9 bits as an index into 3181 * the 2048/512 bit multicast hash table. The high-order 3182 * 7/5 bits select the slot, while the low-order 4 bits 3183 * select the bit within the slot. Note that only the low 3184 * 16-bits of each filter word are used, and there are 3185 * 128/32 filter words. 3186 */ 3187 3188 memset(mchash, 0, sizeof(mchash)); 3189 3190 ifp->if_flags &= ~IFF_ALLMULTI; 3191 ETHER_FIRST_MULTI(step, ec, enm); 3192 if (enm == NULL) 3193 goto setit; 3194 while (enm != NULL) { 3195 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3196 /* 3197 * We must listen to a range of multicast addresses. 3198 * For now, just accept all multicasts, rather than 3199 * trying to set only those filter bits needed to match 3200 * the range. (At this time, the only use of address 3201 * ranges is for IP multicast routing, for which the 3202 * range is big enough to require all bits set.) 3203 */ 3204 goto allmulti; 3205 } 3206 3207 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3208 3209 if (sc->sc_gigabit) { 3210 /* Just want the 11 most significant bits. */ 3211 hash = crc >> 21; 3212 } else { 3213 /* Just want the 9 most significant bits. */ 3214 hash = crc >> 23; 3215 } 3216 3217 slot = hash >> 4; 3218 bit = hash & 0xf; 3219 3220 /* Set the corresponding bit in the hash table. */ 3221 mchash[slot] |= 1 << bit; 3222 3223 ETHER_NEXT_MULTI(step, enm); 3224 } 3225 sc->sc_rfcr |= RFCR_MHEN; 3226 goto setit; 3227 3228 allmulti: 3229 ifp->if_flags |= IFF_ALLMULTI; 3230 sc->sc_rfcr |= RFCR_AAM; 3231 3232 setit: 3233 #define FILTER_EMIT(addr, data) \ 3234 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3235 delay(1); \ 3236 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3237 delay(1) 3238 3239 /* 3240 * Disable receive filter, and program the node address. 3241 */ 3242 cp = CLLADDR(ifp->if_sadl); 3243 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3244 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3245 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3246 3247 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3248 int nwords = 3249 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3250 /* 3251 * Program the multicast hash table. 3252 */ 3253 for (i = 0; i < nwords; i++) { 3254 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3255 } 3256 } 3257 #undef FILTER_EMIT 3258 #undef MCHASH_NWORDS 3259 #undef MCHASH_NWORDS_83815 3260 #undef MCHASH_NWORDS_83820 3261 3262 /* 3263 * Re-enable the receiver filter. 3264 */ 3265 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3266 } 3267 3268 /* 3269 * sip_dp83820_mii_readreg: [mii interface function] 3270 * 3271 * Read a PHY register on the MII of the DP83820. 3272 */ 3273 static int 3274 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3275 { 3276 struct sip_softc *sc = device_private(self); 3277 3278 if (sc->sc_cfg & CFG_TBI_EN) { 3279 bus_addr_t tbireg; 3280 3281 if (phy != 0) 3282 return -1; 3283 3284 switch (reg) { 3285 case MII_BMCR: tbireg = SIP_TBICR; break; 3286 case MII_BMSR: tbireg = SIP_TBISR; break; 3287 case MII_ANAR: tbireg = SIP_TANAR; break; 3288 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3289 case MII_ANER: tbireg = SIP_TANER; break; 3290 case MII_EXTSR: 3291 /* 3292 * Don't even bother reading the TESR register. 3293 * The manual documents that the device has 3294 * 1000baseX full/half capability, but the 3295 * register itself seems read back 0 on some 3296 * boards. Just hard-code the result. 3297 */ 3298 return (EXTSR_1000XFDX|EXTSR_1000XHDX); 3299 3300 default: 3301 return (0); 3302 } 3303 3304 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3305 if (tbireg == SIP_TBISR) { 3306 /* LINK and ACOMP are switched! */ 3307 int sr = *val; 3308 3309 *val = 0; 3310 if (sr & TBISR_MR_LINK_STATUS) 3311 *val |= BMSR_LINK; 3312 if (sr & TBISR_MR_AN_COMPLETE) 3313 *val |= BMSR_ACOMP; 3314 3315 /* 3316 * The manual claims this register reads back 0 3317 * on hard and soft reset. But we want to let 3318 * the gentbi driver know that we support auto- 3319 * negotiation, so hard-code this bit in the 3320 * result. 3321 */ 3322 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3323 } 3324 3325 return 0; 3326 } 3327 3328 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3329 val); 3330 } 3331 3332 /* 3333 * sip_dp83820_mii_writereg: [mii interface function] 3334 * 3335 * Write a PHY register on the MII of the DP83820. 3336 */ 3337 static int 3338 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3339 { 3340 struct sip_softc *sc = device_private(self); 3341 3342 if (sc->sc_cfg & CFG_TBI_EN) { 3343 bus_addr_t tbireg; 3344 3345 if (phy != 0) 3346 return -1; 3347 3348 switch (reg) { 3349 case MII_BMCR: tbireg = SIP_TBICR; break; 3350 case MII_ANAR: tbireg = SIP_TANAR; break; 3351 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3352 default: 3353 return 0; 3354 } 3355 3356 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3357 return 0; 3358 } 3359 3360 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3361 val); 3362 } 3363 3364 /* 3365 * sip_dp83820_mii_statchg: [mii interface function] 3366 * 3367 * Callback from MII layer when media changes. 3368 */ 3369 static void 3370 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3371 { 3372 struct sip_softc *sc = ifp->if_softc; 3373 struct mii_data *mii = &sc->sc_mii; 3374 u_int32_t cfg, pcr; 3375 3376 /* 3377 * Get flow control negotiation result. 3378 */ 3379 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3380 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3381 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3382 mii->mii_media_active &= ~IFM_ETH_FMASK; 3383 } 3384 3385 /* 3386 * Update TXCFG for full-duplex operation. 3387 */ 3388 if ((mii->mii_media_active & IFM_FDX) != 0) 3389 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3390 else 3391 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3392 3393 /* 3394 * Update RXCFG for full-duplex or loopback. 3395 */ 3396 if ((mii->mii_media_active & IFM_FDX) != 0 || 3397 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3398 sc->sc_rxcfg |= RXCFG_ATX; 3399 else 3400 sc->sc_rxcfg &= ~RXCFG_ATX; 3401 3402 /* 3403 * Update CFG for MII/GMII. 3404 */ 3405 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3406 cfg = sc->sc_cfg | CFG_MODE_1000; 3407 else 3408 cfg = sc->sc_cfg; 3409 3410 /* 3411 * 802.3x flow control. 3412 */ 3413 pcr = 0; 3414 if (sc->sc_flowflags & IFM_FLOW) { 3415 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3416 pcr |= sc->sc_rx_flow_thresh; 3417 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3418 pcr |= PCR_PSEN | PCR_PS_MCAST; 3419 } 3420 3421 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3422 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3423 sc->sc_txcfg); 3424 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3425 sc->sc_rxcfg); 3426 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3427 } 3428 3429 /* 3430 * sip_mii_bitbang_read: [mii bit-bang interface function] 3431 * 3432 * Read the MII serial port for the MII bit-bang module. 3433 */ 3434 static u_int32_t 3435 sipcom_mii_bitbang_read(device_t self) 3436 { 3437 struct sip_softc *sc = device_private(self); 3438 3439 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3440 } 3441 3442 /* 3443 * sip_mii_bitbang_write: [mii big-bang interface function] 3444 * 3445 * Write the MII serial port for the MII bit-bang module. 3446 */ 3447 static void 3448 sipcom_mii_bitbang_write(device_t self, u_int32_t val) 3449 { 3450 struct sip_softc *sc = device_private(self); 3451 3452 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3453 } 3454 3455 /* 3456 * sip_sis900_mii_readreg: [mii interface function] 3457 * 3458 * Read a PHY register on the MII. 3459 */ 3460 static int 3461 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3462 { 3463 struct sip_softc *sc = device_private(self); 3464 u_int32_t enphy; 3465 3466 /* 3467 * The PHY of recent SiS chipsets is accessed through bitbang 3468 * operations. 3469 */ 3470 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3471 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3472 phy, reg, val); 3473 3474 #ifndef SIS900_MII_RESTRICT 3475 /* 3476 * The SiS 900 has only an internal PHY on the MII. Only allow 3477 * MII address 0. 3478 */ 3479 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3480 return -1; 3481 #endif 3482 3483 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3484 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3485 ENPHY_RWCMD | ENPHY_ACCESS); 3486 do { 3487 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3488 } while (enphy & ENPHY_ACCESS); 3489 3490 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3491 return 0; 3492 } 3493 3494 /* 3495 * sip_sis900_mii_writereg: [mii interface function] 3496 * 3497 * Write a PHY register on the MII. 3498 */ 3499 static int 3500 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3501 { 3502 struct sip_softc *sc = device_private(self); 3503 u_int32_t enphy; 3504 3505 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3506 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3507 phy, reg, val); 3508 } 3509 3510 #ifndef SIS900_MII_RESTRICT 3511 /* 3512 * The SiS 900 has only an internal PHY on the MII. Only allow 3513 * MII address 0. 3514 */ 3515 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3516 return -1; 3517 #endif 3518 3519 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3520 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3521 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3522 do { 3523 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3524 } while (enphy & ENPHY_ACCESS); 3525 3526 return 0; 3527 } 3528 3529 /* 3530 * sip_sis900_mii_statchg: [mii interface function] 3531 * 3532 * Callback from MII layer when media changes. 3533 */ 3534 static void 3535 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3536 { 3537 struct sip_softc *sc = ifp->if_softc; 3538 struct mii_data *mii = &sc->sc_mii; 3539 u_int32_t flowctl; 3540 3541 /* 3542 * Get flow control negotiation result. 3543 */ 3544 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3545 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3546 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3547 mii->mii_media_active &= ~IFM_ETH_FMASK; 3548 } 3549 3550 /* 3551 * Update TXCFG for full-duplex operation. 3552 */ 3553 if ((mii->mii_media_active & IFM_FDX) != 0) 3554 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3555 else 3556 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3557 3558 /* 3559 * Update RXCFG for full-duplex or loopback. 3560 */ 3561 if ((mii->mii_media_active & IFM_FDX) != 0 || 3562 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3563 sc->sc_rxcfg |= RXCFG_ATX; 3564 else 3565 sc->sc_rxcfg &= ~RXCFG_ATX; 3566 3567 /* 3568 * Update IMR for use of 802.3x flow control. 3569 */ 3570 if (sc->sc_flowflags & IFM_FLOW) { 3571 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3572 flowctl = FLOWCTL_FLOWEN; 3573 } else { 3574 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3575 flowctl = 0; 3576 } 3577 3578 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3579 sc->sc_txcfg); 3580 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3581 sc->sc_rxcfg); 3582 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3583 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3584 } 3585 3586 /* 3587 * sip_dp83815_mii_readreg: [mii interface function] 3588 * 3589 * Read a PHY register on the MII. 3590 */ 3591 static int 3592 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3593 { 3594 struct sip_softc *sc = device_private(self); 3595 uint32_t data; 3596 3597 /* 3598 * The DP83815 only has an internal PHY. Only allow 3599 * MII address 0. 3600 */ 3601 if (phy != 0) 3602 return -1; 3603 3604 /* 3605 * Apparently, after a reset, the DP83815 can take a while 3606 * to respond. During this recovery period, the BMSR returns 3607 * a value of 0. Catch this -- it's not supposed to happen 3608 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3609 * PHY to come back to life. 3610 * 3611 * This works out because the BMSR is the first register 3612 * read during the PHY probe process. 3613 */ 3614 do { 3615 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3616 } while (reg == MII_BMSR && data == 0); 3617 3618 *val = data & 0xffff; 3619 return 0; 3620 } 3621 3622 /* 3623 * sip_dp83815_mii_writereg: [mii interface function] 3624 * 3625 * Write a PHY register to the MII. 3626 */ 3627 static int 3628 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3629 { 3630 struct sip_softc *sc = device_private(self); 3631 3632 /* 3633 * The DP83815 only has an internal PHY. Only allow 3634 * MII address 0. 3635 */ 3636 if (phy != 0) 3637 return -1; 3638 3639 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3640 3641 return 0; 3642 } 3643 3644 /* 3645 * sip_dp83815_mii_statchg: [mii interface function] 3646 * 3647 * Callback from MII layer when media changes. 3648 */ 3649 static void 3650 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3651 { 3652 struct sip_softc *sc = ifp->if_softc; 3653 3654 /* 3655 * Update TXCFG for full-duplex operation. 3656 */ 3657 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3658 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3659 else 3660 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3661 3662 /* 3663 * Update RXCFG for full-duplex or loopback. 3664 */ 3665 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3666 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3667 sc->sc_rxcfg |= RXCFG_ATX; 3668 else 3669 sc->sc_rxcfg &= ~RXCFG_ATX; 3670 3671 /* 3672 * XXX 802.3x flow control. 3673 */ 3674 3675 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3676 sc->sc_txcfg); 3677 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3678 sc->sc_rxcfg); 3679 3680 /* 3681 * Some DP83815s experience problems when used with short 3682 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3683 * sequence adjusts the DSP's signal attenuation to fix the 3684 * problem. 3685 */ 3686 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3687 uint32_t reg; 3688 3689 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3690 3691 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3692 reg &= 0x0fff; 3693 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3694 delay(100); 3695 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3696 reg &= 0x00ff; 3697 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3698 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3699 0x00e8); 3700 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3701 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3702 reg | 0x20); 3703 } 3704 3705 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3706 } 3707 } 3708 3709 static void 3710 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3711 const struct pci_attach_args *pa, u_int8_t *enaddr) 3712 { 3713 u_int16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3714 u_int8_t cksum, *e, match; 3715 int i; 3716 3717 /* 3718 * EEPROM data format for the DP83820 can be found in 3719 * the DP83820 manual, section 4.2.4. 3720 */ 3721 3722 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3723 3724 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3725 match = ~(match - 1); 3726 3727 cksum = 0x55; 3728 e = (u_int8_t *) eeprom_data; 3729 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3730 cksum += *e++; 3731 3732 if (cksum != match) 3733 printf("%s: Checksum (%x) mismatch (%x)", 3734 device_xname(sc->sc_dev), cksum, match); 3735 3736 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3737 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3738 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3739 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3740 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3741 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3742 } 3743 3744 static void 3745 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3746 { 3747 int i; 3748 3749 /* 3750 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3751 * a reason, but I don't know it. 3752 */ 3753 for (i = 0; i < 10; i++) 3754 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3755 } 3756 3757 static void 3758 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3759 const struct pci_attach_args *pa, u_int8_t *enaddr) 3760 { 3761 u_int16_t myea[ETHER_ADDR_LEN / 2]; 3762 3763 switch (sc->sc_rev) { 3764 case SIS_REV_630S: 3765 case SIS_REV_630E: 3766 case SIS_REV_630EA1: 3767 case SIS_REV_630ET: 3768 case SIS_REV_635: 3769 /* 3770 * The MAC address for the on-board Ethernet of 3771 * the SiS 630 chipset is in the NVRAM. Kick 3772 * the chip into re-loading it from NVRAM, and 3773 * read the MAC address out of the filter registers. 3774 */ 3775 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3776 3777 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3778 RFCR_RFADDR_NODE0); 3779 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3780 0xffff; 3781 3782 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3783 RFCR_RFADDR_NODE2); 3784 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3785 0xffff; 3786 3787 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3788 RFCR_RFADDR_NODE4); 3789 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3790 0xffff; 3791 break; 3792 3793 case SIS_REV_960: 3794 { 3795 #define SIS_SET_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3796 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3797 3798 #define SIS_CLR_EROMAR(x,y) bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3799 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3800 3801 int waittime, i; 3802 3803 /* Allow to read EEPROM from LAN. It is shared 3804 * between a 1394 controller and the NIC and each 3805 * time we access it, we need to set SIS_EECMD_REQ. 3806 */ 3807 SIS_SET_EROMAR(sc, EROMAR_REQ); 3808 3809 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3810 /* Force EEPROM to idle state. */ 3811 3812 /* 3813 * XXX-cube This is ugly. I'll look for docs about it. 3814 */ 3815 SIS_SET_EROMAR(sc, EROMAR_EECS); 3816 sipcom_sis900_eeprom_delay(sc); 3817 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3818 SIS_SET_EROMAR(sc, EROMAR_EESK); 3819 sipcom_sis900_eeprom_delay(sc); 3820 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3821 sipcom_sis900_eeprom_delay(sc); 3822 } 3823 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3824 sipcom_sis900_eeprom_delay(sc); 3825 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, 0); 3826 3827 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR) & EROMAR_GNT) { 3828 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3829 sizeof(myea) / sizeof(myea[0]), myea); 3830 break; 3831 } 3832 DELAY(1); 3833 } 3834 3835 /* 3836 * Set SIS_EECTL_CLK to high, so a other master 3837 * can operate on the i2c bus. 3838 */ 3839 SIS_SET_EROMAR(sc, EROMAR_EESK); 3840 3841 /* Refuse EEPROM access by LAN */ 3842 SIS_SET_EROMAR(sc, EROMAR_DONE); 3843 } break; 3844 3845 default: 3846 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3847 sizeof(myea) / sizeof(myea[0]), myea); 3848 } 3849 3850 enaddr[0] = myea[0] & 0xff; 3851 enaddr[1] = myea[0] >> 8; 3852 enaddr[2] = myea[1] & 0xff; 3853 enaddr[3] = myea[1] >> 8; 3854 enaddr[4] = myea[2] & 0xff; 3855 enaddr[5] = myea[2] >> 8; 3856 } 3857 3858 /* Table and macro to bit-reverse an octet. */ 3859 static const u_int8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3860 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3861 3862 static void 3863 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3864 const struct pci_attach_args *pa, u_int8_t *enaddr) 3865 { 3866 u_int16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3867 u_int8_t cksum, *e, match; 3868 int i; 3869 3870 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3871 sizeof(eeprom_data[0]), eeprom_data); 3872 3873 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3874 match = ~(match - 1); 3875 3876 cksum = 0x55; 3877 e = (u_int8_t *) eeprom_data; 3878 for (i=0 ; i<SIP_DP83815_EEPROM_CHECKSUM ; i++) { 3879 cksum += *e++; 3880 } 3881 if (cksum != match) { 3882 printf("%s: Checksum (%x) mismatch (%x)", 3883 device_xname(sc->sc_dev), cksum, match); 3884 } 3885 3886 /* 3887 * Unrolled because it makes slightly more sense this way. 3888 * The DP83815 stores the MAC address in bit 0 of word 6 3889 * through bit 15 of word 8. 3890 */ 3891 ea = &eeprom_data[6]; 3892 enaddr[0] = ((*ea & 0x1) << 7); 3893 ea++; 3894 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3895 enaddr[1] = ((*ea & 0x1FE) >> 1); 3896 enaddr[2] = ((*ea & 0x1) << 7); 3897 ea++; 3898 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3899 enaddr[3] = ((*ea & 0x1FE) >> 1); 3900 enaddr[4] = ((*ea & 0x1) << 7); 3901 ea++; 3902 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3903 enaddr[5] = ((*ea & 0x1FE) >> 1); 3904 3905 /* 3906 * In case that's not weird enough, we also need to reverse 3907 * the bits in each byte. This all actually makes more sense 3908 * if you think about the EEPROM storage as an array of bits 3909 * being shifted into bytes, but that's not how we're looking 3910 * at it here... 3911 */ 3912 for (i = 0; i < 6 ;i++) 3913 enaddr[i] = bbr(enaddr[i]); 3914 } 3915 3916 /* 3917 * sip_mediastatus: [ifmedia interface function] 3918 * 3919 * Get the current interface media status. 3920 */ 3921 static void 3922 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3923 { 3924 struct sip_softc *sc = ifp->if_softc; 3925 3926 if (!device_is_active(sc->sc_dev)) { 3927 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3928 ifmr->ifm_status = 0; 3929 return; 3930 } 3931 ether_mediastatus(ifp, ifmr); 3932 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3933 sc->sc_flowflags; 3934 } 3935
Indexes created Sun Sep 21 20:09:37 GMT 2025