if_sip.c revision 1.171
1 /* $NetBSD: if_sip.c,v 1.171 2019/04/26 06:33:34 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1999 Network Computer, Inc. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of Network Computer, Inc. nor the names of its 45 * contributors may be used to endorse or promote products derived 46 * from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Device driver for the Silicon Integrated Systems SiS 900, 63 * SiS 7016 10/100, National Semiconductor DP83815 10/100, and 64 * National Semiconductor DP83820 10/100/1000 PCI Ethernet 65 * controllers. 66 * 67 * Originally written to support the SiS 900 by Jason R. Thorpe for 68 * Network Computer, Inc. 69 * 70 * TODO: 71 * 72 * - Reduce the Rx interrupt load. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.171 2019/04/26 06:33:34 msaitoh Exp $"); 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/callout.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/socket.h> 85 #include <sys/ioctl.h> 86 #include <sys/errno.h> 87 #include <sys/device.h> 88 #include <sys/queue.h> 89 #include <sys/rndsource.h> 90 91 #include <net/if.h> 92 #include <net/if_dl.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 #include <net/bpf.h> 96 97 #include <sys/bus.h> 98 #include <sys/intr.h> 99 #include <machine/endian.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include <dev/mii/mii_bitbang.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 109 #include <dev/pci/if_sipreg.h> 110 111 /* 112 * Transmit descriptor list size. This is arbitrary, but allocate 113 * enough descriptors for 128 pending transmissions, and 8 segments 114 * per packet (64 for DP83820 for jumbo frames). 115 * 116 * This MUST work out to a power of 2. 117 */ 118 #define GSIP_NTXSEGS_ALLOC 16 119 #define SIP_NTXSEGS_ALLOC 8 120 121 #define SIP_TXQUEUELEN 256 122 #define MAX_SIP_NTXDESC \ 123 (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC)) 124 125 /* 126 * Receive descriptor list size. We have one Rx buffer per incoming 127 * packet, so this logic is a little simpler. 128 * 129 * Actually, on the DP83820, we allow the packet to consume more than 130 * one buffer, in order to support jumbo Ethernet frames. In that 131 * case, a packet may consume up to 5 buffers (assuming a 2048 byte 132 * mbuf cluster). 256 receive buffers is only 51 maximum size packets, 133 * so we'd better be quick about handling receive interrupts. 134 */ 135 #define GSIP_NRXDESC 256 136 #define SIP_NRXDESC 128 137 138 #define MAX_SIP_NRXDESC MAX(GSIP_NRXDESC, SIP_NRXDESC) 139 140 /* 141 * Control structures are DMA'd to the SiS900 chip. We allocate them in 142 * a single clump that maps to a single DMA segment to make several things 143 * easier. 144 */ 145 struct sip_control_data { 146 /* 147 * The transmit descriptors. 148 */ 149 struct sip_desc scd_txdescs[MAX_SIP_NTXDESC]; 150 151 /* 152 * The receive descriptors. 153 */ 154 struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC]; 155 }; 156 157 #define SIP_CDOFF(x) offsetof(struct sip_control_data, x) 158 #define SIP_CDTXOFF(x) SIP_CDOFF(scd_txdescs[(x)]) 159 #define SIP_CDRXOFF(x) SIP_CDOFF(scd_rxdescs[(x)]) 160 161 /* 162 * Software state for transmit jobs. 163 */ 164 struct sip_txsoft { 165 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 166 bus_dmamap_t txs_dmamap; /* our DMA map */ 167 int txs_firstdesc; /* first descriptor in packet */ 168 int txs_lastdesc; /* last descriptor in packet */ 169 SIMPLEQ_ENTRY(sip_txsoft) txs_q; 170 }; 171 172 SIMPLEQ_HEAD(sip_txsq, sip_txsoft); 173 174 /* 175 * Software state for receive jobs. 176 */ 177 struct sip_rxsoft { 178 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t rxs_dmamap; /* our DMA map */ 180 }; 181 182 enum sip_attach_stage { 183 SIP_ATTACH_FIN = 0 184 , SIP_ATTACH_CREATE_RXMAP 185 , SIP_ATTACH_CREATE_TXMAP 186 , SIP_ATTACH_LOAD_MAP 187 , SIP_ATTACH_CREATE_MAP 188 , SIP_ATTACH_MAP_MEM 189 , SIP_ATTACH_ALLOC_MEM 190 , SIP_ATTACH_INTR 191 , SIP_ATTACH_MAP 192 }; 193 194 /* 195 * Software state per device. 196 */ 197 struct sip_softc { 198 device_t sc_dev; /* generic device information */ 199 device_suspensor_t sc_suspensor; 200 pmf_qual_t sc_qual; 201 202 bus_space_tag_t sc_st; /* bus space tag */ 203 bus_space_handle_t sc_sh; /* bus space handle */ 204 bus_size_t sc_sz; /* bus space size */ 205 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 206 pci_chipset_tag_t sc_pc; 207 bus_dma_segment_t sc_seg; 208 struct ethercom sc_ethercom; /* ethernet common data */ 209 210 const struct sip_product *sc_model; /* which model are we? */ 211 int sc_gigabit; /* 1: 83820, 0: other */ 212 int sc_rev; /* chip revision */ 213 214 void *sc_ih; /* interrupt cookie */ 215 216 struct mii_data sc_mii; /* MII/media information */ 217 218 callout_t sc_tick_ch; /* tick callout */ 219 220 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 221 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 222 223 /* 224 * Software state for transmit and receive descriptors. 225 */ 226 struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN]; 227 struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC]; 228 229 /* 230 * Control data structures. 231 */ 232 struct sip_control_data *sc_control_data; 233 #define sc_txdescs sc_control_data->scd_txdescs 234 #define sc_rxdescs sc_control_data->scd_rxdescs 235 236 #ifdef SIP_EVENT_COUNTERS 237 /* 238 * Event counters. 239 */ 240 struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */ 241 struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */ 242 struct evcnt sc_ev_txforceintr; /* Tx interrupts forced */ 243 struct evcnt sc_ev_txdintr; /* Tx descriptor interrupts */ 244 struct evcnt sc_ev_txiintr; /* Tx idle interrupts */ 245 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 246 struct evcnt sc_ev_hiberr; /* HIBERR interrupts */ 247 struct evcnt sc_ev_rxpause; /* PAUSE received */ 248 /* DP83820 only */ 249 struct evcnt sc_ev_txpause; /* PAUSE transmitted */ 250 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */ 251 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */ 252 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-boudn */ 253 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */ 254 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */ 255 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */ 256 #endif /* SIP_EVENT_COUNTERS */ 257 258 uint32_t sc_txcfg; /* prototype TXCFG register */ 259 uint32_t sc_rxcfg; /* prototype RXCFG register */ 260 uint32_t sc_imr; /* prototype IMR register */ 261 uint32_t sc_rfcr; /* prototype RFCR register */ 262 263 uint32_t sc_cfg; /* prototype CFG register */ 264 265 uint32_t sc_gpior; /* prototype GPIOR register */ 266 267 uint32_t sc_tx_fill_thresh; /* transmit fill threshold */ 268 uint32_t sc_tx_drain_thresh; /* transmit drain threshold */ 269 270 uint32_t sc_rx_drain_thresh; /* receive drain threshold */ 271 272 int sc_flowflags; /* 802.3x flow control flags */ 273 int sc_rx_flow_thresh; /* Rx FIFO threshold for flow control */ 274 int sc_paused; /* paused indication */ 275 276 int sc_txfree; /* number of free Tx descriptors */ 277 int sc_txnext; /* next ready Tx descriptor */ 278 int sc_txwin; /* Tx descriptors since last intr */ 279 280 struct sip_txsq sc_txfreeq; /* free Tx descsofts */ 281 struct sip_txsq sc_txdirtyq; /* dirty Tx descsofts */ 282 283 /* values of interface state at last init */ 284 struct { 285 /* if_capenable */ 286 uint64_t if_capenable; 287 /* ec_capenable */ 288 int ec_capenable; 289 /* VLAN_ATTACHED */ 290 int is_vlan; 291 } sc_prev; 292 293 short sc_if_flags; 294 295 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 296 int sc_rxdiscard; 297 int sc_rxlen; 298 struct mbuf *sc_rxhead; 299 struct mbuf *sc_rxtail; 300 struct mbuf **sc_rxtailp; 301 302 int sc_ntxdesc; 303 int sc_ntxdesc_mask; 304 305 int sc_nrxdesc_mask; 306 307 const struct sip_parm { 308 const struct sip_regs { 309 int r_rxcfg; 310 int r_txcfg; 311 } p_regs; 312 313 const struct sip_bits { 314 uint32_t b_txcfg_mxdma_8; 315 uint32_t b_txcfg_mxdma_16; 316 uint32_t b_txcfg_mxdma_32; 317 uint32_t b_txcfg_mxdma_64; 318 uint32_t b_txcfg_mxdma_128; 319 uint32_t b_txcfg_mxdma_256; 320 uint32_t b_txcfg_mxdma_512; 321 uint32_t b_txcfg_flth_mask; 322 uint32_t b_txcfg_drth_mask; 323 324 uint32_t b_rxcfg_mxdma_8; 325 uint32_t b_rxcfg_mxdma_16; 326 uint32_t b_rxcfg_mxdma_32; 327 uint32_t b_rxcfg_mxdma_64; 328 uint32_t b_rxcfg_mxdma_128; 329 uint32_t b_rxcfg_mxdma_256; 330 uint32_t b_rxcfg_mxdma_512; 331 332 uint32_t b_isr_txrcmp; 333 uint32_t b_isr_rxrcmp; 334 uint32_t b_isr_dperr; 335 uint32_t b_isr_sserr; 336 uint32_t b_isr_rmabt; 337 uint32_t b_isr_rtabt; 338 339 uint32_t b_cmdsts_size_mask; 340 } p_bits; 341 int p_filtmem; 342 int p_rxbuf_len; 343 bus_size_t p_tx_dmamap_size; 344 int p_ntxsegs; 345 int p_ntxsegs_alloc; 346 int p_nrxdesc; 347 } *sc_parm; 348 349 void (*sc_rxintr)(struct sip_softc *); 350 351 krndsource_t rnd_source; /* random source */ 352 }; 353 354 #define sc_bits sc_parm->p_bits 355 #define sc_regs sc_parm->p_regs 356 357 static const struct sip_parm sip_parm = { 358 .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM 359 , .p_rxbuf_len = MCLBYTES - 1 /* field width */ 360 , .p_tx_dmamap_size = MCLBYTES 361 , .p_ntxsegs = 16 362 , .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC 363 , .p_nrxdesc = SIP_NRXDESC 364 , .p_bits = { 365 .b_txcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 366 , .b_txcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 367 , .b_txcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 368 , .b_txcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 369 , .b_txcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 370 , .b_txcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 371 , .b_txcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 372 , .b_txcfg_flth_mask = 0x00003f00 /* Tx fill threshold */ 373 , .b_txcfg_drth_mask = 0x0000003f /* Tx drain threshold */ 374 375 , .b_rxcfg_mxdma_8 = 0x00200000 /* 8 bytes */ 376 , .b_rxcfg_mxdma_16 = 0x00300000 /* 16 bytes */ 377 , .b_rxcfg_mxdma_32 = 0x00400000 /* 32 bytes */ 378 , .b_rxcfg_mxdma_64 = 0x00500000 /* 64 bytes */ 379 , .b_rxcfg_mxdma_128 = 0x00600000 /* 128 bytes */ 380 , .b_rxcfg_mxdma_256 = 0x00700000 /* 256 bytes */ 381 , .b_rxcfg_mxdma_512 = 0x00000000 /* 512 bytes */ 382 383 , .b_isr_txrcmp = 0x02000000 /* transmit reset complete */ 384 , .b_isr_rxrcmp = 0x01000000 /* receive reset complete */ 385 , .b_isr_dperr = 0x00800000 /* detected parity error */ 386 , .b_isr_sserr = 0x00400000 /* signalled system error */ 387 , .b_isr_rmabt = 0x00200000 /* received master abort */ 388 , .b_isr_rtabt = 0x00100000 /* received target abort */ 389 , .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK 390 } 391 , .p_regs = { 392 .r_rxcfg = OTHER_SIP_RXCFG, 393 .r_txcfg = OTHER_SIP_TXCFG 394 } 395 }, gsip_parm = { 396 .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM 397 , .p_rxbuf_len = MCLBYTES - 8 398 , .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO 399 , .p_ntxsegs = 64 400 , .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC 401 , .p_nrxdesc = GSIP_NRXDESC 402 , .p_bits = { 403 .b_txcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 404 , .b_txcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 405 , .b_txcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 406 , .b_txcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 407 , .b_txcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 408 , .b_txcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 409 , .b_txcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 410 , .b_txcfg_flth_mask = 0x0000ff00 /* Fx fill threshold */ 411 , .b_txcfg_drth_mask = 0x000000ff /* Tx drain threshold */ 412 413 , .b_rxcfg_mxdma_8 = 0x00100000 /* 8 bytes */ 414 , .b_rxcfg_mxdma_16 = 0x00200000 /* 16 bytes */ 415 , .b_rxcfg_mxdma_32 = 0x00300000 /* 32 bytes */ 416 , .b_rxcfg_mxdma_64 = 0x00400000 /* 64 bytes */ 417 , .b_rxcfg_mxdma_128 = 0x00500000 /* 128 bytes */ 418 , .b_rxcfg_mxdma_256 = 0x00600000 /* 256 bytes */ 419 , .b_rxcfg_mxdma_512 = 0x00700000 /* 512 bytes */ 420 421 , .b_isr_txrcmp = 0x00400000 /* transmit reset complete */ 422 , .b_isr_rxrcmp = 0x00200000 /* receive reset complete */ 423 , .b_isr_dperr = 0x00100000 /* detected parity error */ 424 , .b_isr_sserr = 0x00080000 /* signalled system error */ 425 , .b_isr_rmabt = 0x00040000 /* received master abort */ 426 , .b_isr_rtabt = 0x00020000 /* received target abort */ 427 , .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK 428 } 429 , .p_regs = { 430 .r_rxcfg = DP83820_SIP_RXCFG, 431 .r_txcfg = DP83820_SIP_TXCFG 432 } 433 }; 434 435 static inline int 436 sip_nexttx(const struct sip_softc *sc, int x) 437 { 438 return (x + 1) & sc->sc_ntxdesc_mask; 439 } 440 441 static inline int 442 sip_nextrx(const struct sip_softc *sc, int x) 443 { 444 return (x + 1) & sc->sc_nrxdesc_mask; 445 } 446 447 /* 83820 only */ 448 static inline void 449 sip_rxchain_reset(struct sip_softc *sc) 450 { 451 sc->sc_rxtailp = &sc->sc_rxhead; 452 *sc->sc_rxtailp = NULL; 453 sc->sc_rxlen = 0; 454 } 455 456 /* 83820 only */ 457 static inline void 458 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m) 459 { 460 *sc->sc_rxtailp = sc->sc_rxtail = m; 461 sc->sc_rxtailp = &m->m_next; 462 } 463 464 #ifdef SIP_EVENT_COUNTERS 465 #define SIP_EVCNT_INCR(ev) (ev)->ev_count++ 466 #else 467 #define SIP_EVCNT_INCR(ev) /* nothing */ 468 #endif 469 470 #define SIP_CDTXADDR(sc, x) ((sc)->sc_cddma + SIP_CDTXOFF((x))) 471 #define SIP_CDRXADDR(sc, x) ((sc)->sc_cddma + SIP_CDRXOFF((x))) 472 473 static inline void 474 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops) 475 { 476 int x, n; 477 478 x = x0; 479 n = n0; 480 481 /* If it will wrap around, sync to the end of the ring. */ 482 if (x + n > sc->sc_ntxdesc) { 483 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 484 SIP_CDTXOFF(x), sizeof(struct sip_desc) * 485 (sc->sc_ntxdesc - x), ops); 486 n -= (sc->sc_ntxdesc - x); 487 x = 0; 488 } 489 490 /* Now sync whatever is left. */ 491 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 492 SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops); 493 } 494 495 static inline void 496 sip_cdrxsync(struct sip_softc *sc, int x, int ops) 497 { 498 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 499 SIP_CDRXOFF(x), sizeof(struct sip_desc), ops); 500 } 501 502 #if 0 503 #ifdef DP83820 504 uint32_t sipd_bufptr; /* pointer to DMA segment */ 505 uint32_t sipd_cmdsts; /* command/status word */ 506 #else 507 uint32_t sipd_cmdsts; /* command/status word */ 508 uint32_t sipd_bufptr; /* pointer to DMA segment */ 509 #endif /* DP83820 */ 510 #endif /* 0 */ 511 512 static inline volatile uint32_t * 513 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd) 514 { 515 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0]; 516 } 517 518 static inline volatile uint32_t * 519 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd) 520 { 521 return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1]; 522 } 523 524 static inline void 525 sip_init_rxdesc(struct sip_softc *sc, int x) 526 { 527 struct sip_rxsoft *rxs = &sc->sc_rxsoft[x]; 528 struct sip_desc *sipd = &sc->sc_rxdescs[x]; 529 530 sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x))); 531 *sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr); 532 *sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR | 533 (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask)); 534 sipd->sipd_extsts = 0; 535 sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 536 } 537 538 #define SIP_CHIP_VERS(sc, v, p, r) \ 539 ((sc)->sc_model->sip_vendor == (v) && \ 540 (sc)->sc_model->sip_product == (p) && \ 541 (sc)->sc_rev == (r)) 542 543 #define SIP_CHIP_MODEL(sc, v, p) \ 544 ((sc)->sc_model->sip_vendor == (v) && \ 545 (sc)->sc_model->sip_product == (p)) 546 547 #define SIP_SIS900_REV(sc, rev) \ 548 SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev)) 549 550 #define SIP_TIMEOUT 1000 551 552 static int sip_ifflags_cb(struct ethercom *); 553 static void sipcom_start(struct ifnet *); 554 static void sipcom_watchdog(struct ifnet *); 555 static int sipcom_ioctl(struct ifnet *, u_long, void *); 556 static int sipcom_init(struct ifnet *); 557 static void sipcom_stop(struct ifnet *, int); 558 559 static bool sipcom_reset(struct sip_softc *); 560 static void sipcom_rxdrain(struct sip_softc *); 561 static int sipcom_add_rxbuf(struct sip_softc *, int); 562 static void sipcom_read_eeprom(struct sip_softc *, int, int, 563 uint16_t *); 564 static void sipcom_tick(void *); 565 566 static void sipcom_sis900_set_filter(struct sip_softc *); 567 static void sipcom_dp83815_set_filter(struct sip_softc *); 568 569 static void sipcom_dp83820_read_macaddr(struct sip_softc *, 570 const struct pci_attach_args *, uint8_t *); 571 static void sipcom_sis900_eeprom_delay(struct sip_softc *sc); 572 static void sipcom_sis900_read_macaddr(struct sip_softc *, 573 const struct pci_attach_args *, uint8_t *); 574 static void sipcom_dp83815_read_macaddr(struct sip_softc *, 575 const struct pci_attach_args *, uint8_t *); 576 577 static int sipcom_intr(void *); 578 static void sipcom_txintr(struct sip_softc *); 579 static void sip_rxintr(struct sip_softc *); 580 static void gsip_rxintr(struct sip_softc *); 581 582 static int sipcom_dp83820_mii_readreg(device_t, int, int, uint16_t *); 583 static int sipcom_dp83820_mii_writereg(device_t, int, int, uint16_t); 584 static void sipcom_dp83820_mii_statchg(struct ifnet *); 585 586 static int sipcom_sis900_mii_readreg(device_t, int, int, uint16_t *); 587 static int sipcom_sis900_mii_writereg(device_t, int, int, uint16_t); 588 static void sipcom_sis900_mii_statchg(struct ifnet *); 589 590 static int sipcom_dp83815_mii_readreg(device_t, int, int, uint16_t *); 591 static int sipcom_dp83815_mii_writereg(device_t, int, int, uint16_t); 592 static void sipcom_dp83815_mii_statchg(struct ifnet *); 593 594 static void sipcom_mediastatus(struct ifnet *, struct ifmediareq *); 595 596 static int sipcom_match(device_t, cfdata_t, void *); 597 static void sipcom_attach(device_t, device_t, void *); 598 static void sipcom_do_detach(device_t, enum sip_attach_stage); 599 static int sipcom_detach(device_t, int); 600 static bool sipcom_resume(device_t, const pmf_qual_t *); 601 static bool sipcom_suspend(device_t, const pmf_qual_t *); 602 603 int gsip_copy_small = 0; 604 int sip_copy_small = 0; 605 606 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc), 607 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 608 DVF_DETACH_SHUTDOWN); 609 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc), 610 sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL, 611 DVF_DETACH_SHUTDOWN); 612 613 /* 614 * Descriptions of the variants of the SiS900. 615 */ 616 struct sip_variant { 617 int (*sipv_mii_readreg)(device_t, int, int, uint16_t *); 618 int (*sipv_mii_writereg)(device_t, int, int, uint16_t); 619 void (*sipv_mii_statchg)(struct ifnet *); 620 void (*sipv_set_filter)(struct sip_softc *); 621 void (*sipv_read_macaddr)(struct sip_softc *, 622 const struct pci_attach_args *, uint8_t *); 623 }; 624 625 static uint32_t sipcom_mii_bitbang_read(device_t); 626 static void sipcom_mii_bitbang_write(device_t, uint32_t); 627 628 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = { 629 sipcom_mii_bitbang_read, 630 sipcom_mii_bitbang_write, 631 { 632 EROMAR_MDIO, /* MII_BIT_MDO */ 633 EROMAR_MDIO, /* MII_BIT_MDI */ 634 EROMAR_MDC, /* MII_BIT_MDC */ 635 EROMAR_MDDIR, /* MII_BIT_DIR_HOST_PHY */ 636 0, /* MII_BIT_DIR_PHY_HOST */ 637 } 638 }; 639 640 static const struct sip_variant sipcom_variant_dp83820 = { 641 sipcom_dp83820_mii_readreg, 642 sipcom_dp83820_mii_writereg, 643 sipcom_dp83820_mii_statchg, 644 sipcom_dp83815_set_filter, 645 sipcom_dp83820_read_macaddr, 646 }; 647 648 static const struct sip_variant sipcom_variant_sis900 = { 649 sipcom_sis900_mii_readreg, 650 sipcom_sis900_mii_writereg, 651 sipcom_sis900_mii_statchg, 652 sipcom_sis900_set_filter, 653 sipcom_sis900_read_macaddr, 654 }; 655 656 static const struct sip_variant sipcom_variant_dp83815 = { 657 sipcom_dp83815_mii_readreg, 658 sipcom_dp83815_mii_writereg, 659 sipcom_dp83815_mii_statchg, 660 sipcom_dp83815_set_filter, 661 sipcom_dp83815_read_macaddr, 662 }; 663 664 665 /* 666 * Devices supported by this driver. 667 */ 668 static const struct sip_product { 669 pci_vendor_id_t sip_vendor; 670 pci_product_id_t sip_product; 671 const char *sip_name; 672 const struct sip_variant *sip_variant; 673 int sip_gigabit; 674 } sipcom_products[] = { 675 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820, 676 "NatSemi DP83820 Gigabit Ethernet", 677 &sipcom_variant_dp83820, 1 }, 678 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, 679 "SiS 900 10/100 Ethernet", 680 &sipcom_variant_sis900, 0 }, 681 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, 682 "SiS 7016 10/100 Ethernet", 683 &sipcom_variant_sis900, 0 }, 684 685 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, 686 "NatSemi DP83815 10/100 Ethernet", 687 &sipcom_variant_dp83815, 0 }, 688 689 { 0, 0, 690 NULL, 691 NULL, 0 }, 692 }; 693 694 static const struct sip_product * 695 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit) 696 { 697 const struct sip_product *sip; 698 699 for (sip = sipcom_products; sip->sip_name != NULL; sip++) { 700 if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor && 701 PCI_PRODUCT(pa->pa_id) == sip->sip_product && 702 sip->sip_gigabit == gigabit) 703 return sip; 704 } 705 return NULL; 706 } 707 708 /* 709 * I really hate stupid hardware vendors. There's a bit in the EEPROM 710 * which indicates if the card can do 64-bit data transfers. Unfortunately, 711 * several vendors of 32-bit cards fail to clear this bit in the EEPROM, 712 * which means we try to use 64-bit data transfers on those cards if we 713 * happen to be plugged into a 32-bit slot. 714 * 715 * What we do is use this table of cards known to be 64-bit cards. If 716 * you have a 64-bit card who's subsystem ID is not listed in this table, 717 * send the output of "pcictl dump ..." of the device to me so that your 718 * card will use the 64-bit data path when plugged into a 64-bit slot. 719 * 720 * -- Jason R. Thorpe <thorpej (at) NetBSD.org> 721 * June 30, 2002 722 */ 723 static int 724 sipcom_check_64bit(const struct pci_attach_args *pa) 725 { 726 static const struct { 727 pci_vendor_id_t c64_vendor; 728 pci_product_id_t c64_product; 729 } card64[] = { 730 /* Asante GigaNIX */ 731 { 0x128a, 0x0002 }, 732 733 /* Accton EN1407-T, Planex GN-1000TE */ 734 { 0x1113, 0x1407 }, 735 736 /* Netgear GA621 */ 737 { 0x1385, 0x621a }, 738 739 /* Netgear GA622 */ 740 { 0x1385, 0x622a }, 741 742 /* SMC EZ Card 1000 (9462TX) */ 743 { 0x10b8, 0x9462 }, 744 745 { 0, 0} 746 }; 747 pcireg_t subsys; 748 int i; 749 750 subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 751 752 for (i = 0; card64[i].c64_vendor != 0; i++) { 753 if (PCI_VENDOR(subsys) == card64[i].c64_vendor && 754 PCI_PRODUCT(subsys) == card64[i].c64_product) 755 return 1; 756 } 757 758 return 0; 759 } 760 761 static int 762 sipcom_match(device_t parent, cfdata_t cf, void *aux) 763 { 764 struct pci_attach_args *pa = aux; 765 766 if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL) 767 return 1; 768 769 return 0; 770 } 771 772 static void 773 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa) 774 { 775 uint32_t reg; 776 int i; 777 778 /* 779 * Cause the chip to load configuration data from the EEPROM. 780 */ 781 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN); 782 for (i = 0; i < 10000; i++) { 783 delay(10); 784 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 785 PTSCR_EELOAD_EN) == 0) 786 break; 787 } 788 if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) & 789 PTSCR_EELOAD_EN) { 790 printf("%s: timeout loading configuration from EEPROM\n", 791 device_xname(sc->sc_dev)); 792 return; 793 } 794 795 sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR); 796 797 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG); 798 if (reg & CFG_PCI64_DET) { 799 printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev)); 800 /* 801 * Check to see if this card is 64-bit. If so, enable 64-bit 802 * data transfers. 803 * 804 * We can't use the DATA64_EN bit in the EEPROM, because 805 * vendors of 32-bit cards fail to clear that bit in many 806 * cases (yet the card still detects that it's in a 64-bit 807 * slot; go figure). 808 */ 809 if (sipcom_check_64bit(pa)) { 810 sc->sc_cfg |= CFG_DATA64_EN; 811 printf(", using 64-bit data transfers"); 812 } 813 printf("\n"); 814 } 815 816 /* 817 * XXX Need some PCI flags indicating support for 818 * XXX 64-bit addressing. 819 */ 820 #if 0 821 if (reg & CFG_M64ADDR) 822 sc->sc_cfg |= CFG_M64ADDR; 823 if (reg & CFG_T64ADDR) 824 sc->sc_cfg |= CFG_T64ADDR; 825 #endif 826 827 if (reg & (CFG_TBI_EN|CFG_EXT_125)) { 828 const char *sep = ""; 829 printf("%s: using ", device_xname(sc->sc_dev)); 830 if (reg & CFG_EXT_125) { 831 sc->sc_cfg |= CFG_EXT_125; 832 printf("%s125MHz clock", sep); 833 sep = ", "; 834 } 835 if (reg & CFG_TBI_EN) { 836 sc->sc_cfg |= CFG_TBI_EN; 837 printf("%sten-bit interface", sep); 838 sep = ", "; 839 } 840 printf("\n"); 841 } 842 if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 || 843 (reg & CFG_MRM_DIS) != 0) 844 sc->sc_cfg |= CFG_MRM_DIS; 845 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 || 846 (reg & CFG_MWI_DIS) != 0) 847 sc->sc_cfg |= CFG_MWI_DIS; 848 849 /* 850 * Use the extended descriptor format on the DP83820. This 851 * gives us an interface to VLAN tagging and IPv4/TCP/UDP 852 * checksumming. 853 */ 854 sc->sc_cfg |= CFG_EXTSTS_EN; 855 } 856 857 static int 858 sipcom_detach(device_t self, int flags) 859 { 860 int s; 861 862 s = splnet(); 863 sipcom_do_detach(self, SIP_ATTACH_FIN); 864 splx(s); 865 866 return 0; 867 } 868 869 static void 870 sipcom_do_detach(device_t self, enum sip_attach_stage stage) 871 { 872 int i; 873 struct sip_softc *sc = device_private(self); 874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 875 876 /* 877 * Free any resources we've allocated during attach. 878 * Do this in reverse order and fall through. 879 */ 880 switch (stage) { 881 case SIP_ATTACH_FIN: 882 sipcom_stop(ifp, 1); 883 pmf_device_deregister(self); 884 #ifdef SIP_EVENT_COUNTERS 885 /* 886 * Attach event counters. 887 */ 888 evcnt_detach(&sc->sc_ev_txforceintr); 889 evcnt_detach(&sc->sc_ev_txdstall); 890 evcnt_detach(&sc->sc_ev_txsstall); 891 evcnt_detach(&sc->sc_ev_hiberr); 892 evcnt_detach(&sc->sc_ev_rxintr); 893 evcnt_detach(&sc->sc_ev_txiintr); 894 evcnt_detach(&sc->sc_ev_txdintr); 895 if (!sc->sc_gigabit) { 896 evcnt_detach(&sc->sc_ev_rxpause); 897 } else { 898 evcnt_detach(&sc->sc_ev_txudpsum); 899 evcnt_detach(&sc->sc_ev_txtcpsum); 900 evcnt_detach(&sc->sc_ev_txipsum); 901 evcnt_detach(&sc->sc_ev_rxudpsum); 902 evcnt_detach(&sc->sc_ev_rxtcpsum); 903 evcnt_detach(&sc->sc_ev_rxipsum); 904 evcnt_detach(&sc->sc_ev_txpause); 905 evcnt_detach(&sc->sc_ev_rxpause); 906 } 907 #endif /* SIP_EVENT_COUNTERS */ 908 909 rnd_detach_source(&sc->rnd_source); 910 911 ether_ifdetach(ifp); 912 if_detach(ifp); 913 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 914 915 /*FALLTHROUGH*/ 916 case SIP_ATTACH_CREATE_RXMAP: 917 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 918 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 919 bus_dmamap_destroy(sc->sc_dmat, 920 sc->sc_rxsoft[i].rxs_dmamap); 921 } 922 /*FALLTHROUGH*/ 923 case SIP_ATTACH_CREATE_TXMAP: 924 for (i = 0; i < SIP_TXQUEUELEN; i++) { 925 if (sc->sc_txsoft[i].txs_dmamap != NULL) 926 bus_dmamap_destroy(sc->sc_dmat, 927 sc->sc_txsoft[i].txs_dmamap); 928 } 929 /*FALLTHROUGH*/ 930 case SIP_ATTACH_LOAD_MAP: 931 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 932 /*FALLTHROUGH*/ 933 case SIP_ATTACH_CREATE_MAP: 934 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 935 /*FALLTHROUGH*/ 936 case SIP_ATTACH_MAP_MEM: 937 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 938 sizeof(struct sip_control_data)); 939 /*FALLTHROUGH*/ 940 case SIP_ATTACH_ALLOC_MEM: 941 bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1); 942 /* FALLTHROUGH*/ 943 case SIP_ATTACH_INTR: 944 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 945 /* FALLTHROUGH*/ 946 case SIP_ATTACH_MAP: 947 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 948 break; 949 default: 950 break; 951 } 952 return; 953 } 954 955 static bool 956 sipcom_resume(device_t self, const pmf_qual_t *qual) 957 { 958 struct sip_softc *sc = device_private(self); 959 960 return sipcom_reset(sc); 961 } 962 963 static bool 964 sipcom_suspend(device_t self, const pmf_qual_t *qual) 965 { 966 struct sip_softc *sc = device_private(self); 967 968 sipcom_rxdrain(sc); 969 return true; 970 } 971 972 static void 973 sipcom_attach(device_t parent, device_t self, void *aux) 974 { 975 struct sip_softc *sc = device_private(self); 976 struct pci_attach_args *pa = aux; 977 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 978 pci_chipset_tag_t pc = pa->pa_pc; 979 pci_intr_handle_t ih; 980 const char *intrstr = NULL; 981 bus_space_tag_t iot, memt; 982 bus_space_handle_t ioh, memh; 983 bus_size_t iosz, memsz; 984 int ioh_valid, memh_valid; 985 int i, rseg, error; 986 const struct sip_product *sip; 987 uint8_t enaddr[ETHER_ADDR_LEN]; 988 pcireg_t csr; 989 pcireg_t memtype; 990 bus_size_t tx_dmamap_size; 991 int ntxsegs_alloc; 992 cfdata_t cf = device_cfdata(self); 993 char intrbuf[PCI_INTRSTR_LEN]; 994 995 callout_init(&sc->sc_tick_ch, 0); 996 997 sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0); 998 if (sip == NULL) { 999 aprint_error("\n"); 1000 panic("%s: impossible", __func__); 1001 } 1002 sc->sc_dev = self; 1003 sc->sc_gigabit = sip->sip_gigabit; 1004 pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual); 1005 sc->sc_pc = pc; 1006 1007 if (sc->sc_gigabit) { 1008 sc->sc_rxintr = gsip_rxintr; 1009 sc->sc_parm = &gsip_parm; 1010 } else { 1011 sc->sc_rxintr = sip_rxintr; 1012 sc->sc_parm = &sip_parm; 1013 } 1014 tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size; 1015 ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc; 1016 sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc; 1017 sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1; 1018 sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1; 1019 1020 sc->sc_rev = PCI_REVISION(pa->pa_class); 1021 1022 aprint_naive("\n"); 1023 aprint_normal(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev); 1024 1025 sc->sc_model = sip; 1026 1027 /* 1028 * XXX Work-around broken PXE firmware on some boards. 1029 * 1030 * The DP83815 shares an address decoder with the MEM BAR 1031 * and the ROM BAR. Make sure the ROM BAR is disabled, 1032 * so that memory mapped access works. 1033 */ 1034 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1035 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1036 ~PCI_MAPREG_ROM_ENABLE); 1037 1038 /* 1039 * Map the device. 1040 */ 1041 ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA, 1042 PCI_MAPREG_TYPE_IO, 0, 1043 &iot, &ioh, NULL, &iosz) == 0); 1044 if (sc->sc_gigabit) { 1045 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA); 1046 switch (memtype) { 1047 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 1048 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 1049 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1050 memtype, 0, &memt, &memh, NULL, &memsz) == 0); 1051 break; 1052 default: 1053 memh_valid = 0; 1054 } 1055 } else { 1056 memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA, 1057 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 1058 &memt, &memh, NULL, &memsz) == 0); 1059 } 1060 1061 if (memh_valid) { 1062 sc->sc_st = memt; 1063 sc->sc_sh = memh; 1064 sc->sc_sz = memsz; 1065 } else if (ioh_valid) { 1066 sc->sc_st = iot; 1067 sc->sc_sh = ioh; 1068 sc->sc_sz = iosz; 1069 } else { 1070 aprint_error_dev(self, "unable to map device registers\n"); 1071 return; 1072 } 1073 1074 sc->sc_dmat = pa->pa_dmat; 1075 1076 /* 1077 * Make sure bus mastering is enabled. Also make sure 1078 * Write/Invalidate is enabled if we're allowed to use it. 1079 */ 1080 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1081 if (pa->pa_flags & PCI_FLAGS_MWI_OKAY) 1082 csr |= PCI_COMMAND_INVALIDATE_ENABLE; 1083 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1084 csr | PCI_COMMAND_MASTER_ENABLE); 1085 1086 /* Power up chip */ 1087 error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null); 1088 if (error != 0 && error != EOPNOTSUPP) { 1089 aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error); 1090 return; 1091 } 1092 1093 /* 1094 * Map and establish our interrupt. 1095 */ 1096 if (pci_intr_map(pa, &ih)) { 1097 aprint_error_dev(sc->sc_dev, "unable to map interrupt\n"); 1098 return; 1099 } 1100 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1101 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, sipcom_intr, sc, 1102 device_xname(self)); 1103 if (sc->sc_ih == NULL) { 1104 aprint_error_dev(sc->sc_dev, "unable to establish interrupt"); 1105 if (intrstr != NULL) 1106 aprint_error(" at %s", intrstr); 1107 aprint_error("\n"); 1108 sipcom_do_detach(self, SIP_ATTACH_MAP); 1109 return; 1110 } 1111 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1112 1113 SIMPLEQ_INIT(&sc->sc_txfreeq); 1114 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1115 1116 /* 1117 * Allocate the control data structures, and create and load the 1118 * DMA map for it. 1119 */ 1120 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1121 sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1, 1122 &rseg, 0)) != 0) { 1123 aprint_error_dev(sc->sc_dev, 1124 "unable to allocate control data, error = %d\n", error); 1125 sipcom_do_detach(self, SIP_ATTACH_INTR); 1126 return; 1127 } 1128 1129 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg, 1130 sizeof(struct sip_control_data), (void **)&sc->sc_control_data, 1131 BUS_DMA_COHERENT)) != 0) { 1132 aprint_error_dev(sc->sc_dev, 1133 "unable to map control data, error = %d\n", error); 1134 sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM); 1135 } 1136 1137 if ((error = bus_dmamap_create(sc->sc_dmat, 1138 sizeof(struct sip_control_data), 1, 1139 sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 1140 aprint_error_dev(self, "unable to create control data DMA map" 1141 ", error = %d\n", error); 1142 sipcom_do_detach(self, SIP_ATTACH_MAP_MEM); 1143 } 1144 1145 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 1146 sc->sc_control_data, sizeof(struct sip_control_data), NULL, 1147 0)) != 0) { 1148 aprint_error_dev(self, "unable to load control data DMA map" 1149 ", error = %d\n", error); 1150 sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP); 1151 } 1152 1153 /* 1154 * Create the transmit buffer DMA maps. 1155 */ 1156 for (i = 0; i < SIP_TXQUEUELEN; i++) { 1157 if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size, 1158 sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0, 1159 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 1160 aprint_error_dev(self, "unable to create tx DMA map %d" 1161 ", error = %d\n", i, error); 1162 sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP); 1163 } 1164 } 1165 1166 /* 1167 * Create the receive buffer DMA maps. 1168 */ 1169 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 1170 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 1171 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 1172 aprint_error_dev(self, "unable to create rx DMA map %d" 1173 ", error = %d\n", i, error); 1174 sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP); 1175 } 1176 sc->sc_rxsoft[i].rxs_mbuf = NULL; 1177 } 1178 1179 /* 1180 * Reset the chip to a known state. 1181 */ 1182 sipcom_reset(sc); 1183 1184 /* 1185 * Read the Ethernet address from the EEPROM. This might 1186 * also fetch other stuff from the EEPROM and stash it 1187 * in the softc. 1188 */ 1189 sc->sc_cfg = 0; 1190 if (!sc->sc_gigabit) { 1191 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1192 SIP_SIS900_REV(sc,SIS_REV_900B)) 1193 sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT); 1194 1195 if (SIP_SIS900_REV(sc,SIS_REV_635) || 1196 SIP_SIS900_REV(sc,SIS_REV_960) || 1197 SIP_SIS900_REV(sc,SIS_REV_900B)) 1198 sc->sc_cfg |= 1199 (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) & 1200 CFG_EDBMASTEN); 1201 } 1202 1203 (*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr); 1204 1205 aprint_normal_dev(self, "Ethernet address %s\n",ether_sprintf(enaddr)); 1206 1207 /* 1208 * Initialize the configuration register: aggressive PCI 1209 * bus request algorithm, default backoff, default OW timer, 1210 * default parity error detection. 1211 * 1212 * NOTE: "Big endian mode" is useless on the SiS900 and 1213 * friends -- it affects packet data, not descriptors. 1214 */ 1215 if (sc->sc_gigabit) 1216 sipcom_dp83820_attach(sc, pa); 1217 1218 /* 1219 * Initialize our media structures and probe the MII. 1220 */ 1221 sc->sc_mii.mii_ifp = ifp; 1222 sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg; 1223 sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg; 1224 sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg; 1225 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1226 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange, 1227 sipcom_mediastatus); 1228 1229 /* 1230 * XXX We cannot handle flow control on the DP83815. 1231 */ 1232 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1233 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1234 MII_OFFSET_ANY, 0); 1235 else 1236 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1237 MII_OFFSET_ANY, MIIF_DOPAUSE); 1238 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1239 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1240 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1241 } else 1242 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1243 1244 ifp = &sc->sc_ethercom.ec_if; 1245 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1246 ifp->if_softc = sc; 1247 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1248 sc->sc_if_flags = ifp->if_flags; 1249 ifp->if_ioctl = sipcom_ioctl; 1250 ifp->if_start = sipcom_start; 1251 ifp->if_watchdog = sipcom_watchdog; 1252 ifp->if_init = sipcom_init; 1253 ifp->if_stop = sipcom_stop; 1254 IFQ_SET_READY(&ifp->if_snd); 1255 1256 /* 1257 * We can support 802.1Q VLAN-sized frames. 1258 */ 1259 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 1260 1261 if (sc->sc_gigabit) { 1262 /* 1263 * And the DP83820 can do VLAN tagging in hardware, and 1264 * support the jumbo Ethernet MTU. 1265 */ 1266 sc->sc_ethercom.ec_capabilities |= 1267 ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU; 1268 1269 /* 1270 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums 1271 * in hardware. 1272 */ 1273 ifp->if_capabilities |= 1274 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1275 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1276 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1277 } 1278 1279 /* 1280 * Attach the interface. 1281 */ 1282 if_attach(ifp); 1283 if_deferred_start_init(ifp, NULL); 1284 ether_ifattach(ifp, enaddr); 1285 ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb); 1286 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 1287 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 1288 sc->sc_prev.if_capenable = ifp->if_capenable; 1289 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 1290 RND_TYPE_NET, RND_FLAG_DEFAULT); 1291 1292 /* 1293 * The number of bytes that must be available in 1294 * the Tx FIFO before the bus master can DMA more 1295 * data into the FIFO. 1296 */ 1297 sc->sc_tx_fill_thresh = 64 / 32; 1298 1299 /* 1300 * Start at a drain threshold of 512 bytes. We will 1301 * increase it if a DMA underrun occurs. 1302 * 1303 * XXX The minimum value of this variable should be 1304 * tuned. We may be able to improve performance 1305 * by starting with a lower value. That, however, 1306 * may trash the first few outgoing packets if the 1307 * PCI bus is saturated. 1308 */ 1309 if (sc->sc_gigabit) 1310 sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */ 1311 else 1312 sc->sc_tx_drain_thresh = 1504 / 32; 1313 1314 /* 1315 * Initialize the Rx FIFO drain threshold. 1316 * 1317 * This is in units of 8 bytes. 1318 * 1319 * We should never set this value lower than 2; 14 bytes are 1320 * required to filter the packet. 1321 */ 1322 sc->sc_rx_drain_thresh = 128 / 8; 1323 1324 #ifdef SIP_EVENT_COUNTERS 1325 /* 1326 * Attach event counters. 1327 */ 1328 evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC, 1329 NULL, device_xname(sc->sc_dev), "txsstall"); 1330 evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC, 1331 NULL, device_xname(sc->sc_dev), "txdstall"); 1332 evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR, 1333 NULL, device_xname(sc->sc_dev), "txforceintr"); 1334 evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR, 1335 NULL, device_xname(sc->sc_dev), "txdintr"); 1336 evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR, 1337 NULL, device_xname(sc->sc_dev), "txiintr"); 1338 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR, 1339 NULL, device_xname(sc->sc_dev), "rxintr"); 1340 evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR, 1341 NULL, device_xname(sc->sc_dev), "hiberr"); 1342 if (!sc->sc_gigabit) { 1343 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR, 1344 NULL, device_xname(sc->sc_dev), "rxpause"); 1345 } else { 1346 evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC, 1347 NULL, device_xname(sc->sc_dev), "rxpause"); 1348 evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC, 1349 NULL, device_xname(sc->sc_dev), "txpause"); 1350 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC, 1351 NULL, device_xname(sc->sc_dev), "rxipsum"); 1352 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC, 1353 NULL, device_xname(sc->sc_dev), "rxtcpsum"); 1354 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC, 1355 NULL, device_xname(sc->sc_dev), "rxudpsum"); 1356 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC, 1357 NULL, device_xname(sc->sc_dev), "txipsum"); 1358 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC, 1359 NULL, device_xname(sc->sc_dev), "txtcpsum"); 1360 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC, 1361 NULL, device_xname(sc->sc_dev), "txudpsum"); 1362 } 1363 #endif /* SIP_EVENT_COUNTERS */ 1364 1365 if (pmf_device_register(self, sipcom_suspend, sipcom_resume)) 1366 pmf_class_network_register(self, ifp); 1367 else 1368 aprint_error_dev(self, "couldn't establish power handler\n"); 1369 } 1370 1371 static inline void 1372 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0, 1373 uint64_t capenable) 1374 { 1375 uint32_t extsts; 1376 #ifdef DEBUG 1377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1378 #endif 1379 /* 1380 * If VLANs are enabled and the packet has a VLAN tag, set 1381 * up the descriptor to encapsulate the packet for us. 1382 * 1383 * This apparently has to be on the last descriptor of 1384 * the packet. 1385 */ 1386 1387 /* 1388 * Byte swapping is tricky. We need to provide the tag 1389 * in a network byte order. On a big-endian machine, 1390 * the byteorder is correct, but we need to swap it 1391 * anyway, because this will be undone by the outside 1392 * htole32(). That's why there must be an 1393 * unconditional swap instead of htons() inside. 1394 */ 1395 if (vlan_has_tag(m0)) { 1396 sc->sc_txdescs[lasttx].sipd_extsts |= 1397 htole32(EXTSTS_VPKT | 1398 (bswap16(vlan_get_tag(m0)) & 1399 EXTSTS_VTCI)); 1400 } 1401 1402 /* 1403 * If the upper-layer has requested IPv4/TCPv4/UDPv4 1404 * checksumming, set up the descriptor to do this work 1405 * for us. 1406 * 1407 * This apparently has to be on the first descriptor of 1408 * the packet. 1409 * 1410 * Byte-swap constants so the compiler can optimize. 1411 */ 1412 extsts = 0; 1413 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) { 1414 KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx); 1415 SIP_EVCNT_INCR(&sc->sc_ev_txipsum); 1416 extsts |= htole32(EXTSTS_IPPKT); 1417 } 1418 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1419 KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx); 1420 SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum); 1421 extsts |= htole32(EXTSTS_TCPPKT); 1422 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1423 KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx); 1424 SIP_EVCNT_INCR(&sc->sc_ev_txudpsum); 1425 extsts |= htole32(EXTSTS_UDPPKT); 1426 } 1427 sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts; 1428 } 1429 1430 /* 1431 * sip_start: [ifnet interface function] 1432 * 1433 * Start packet transmission on the interface. 1434 */ 1435 static void 1436 sipcom_start(struct ifnet *ifp) 1437 { 1438 struct sip_softc *sc = ifp->if_softc; 1439 struct mbuf *m0; 1440 struct mbuf *m; 1441 struct sip_txsoft *txs; 1442 bus_dmamap_t dmamap; 1443 int error, nexttx, lasttx, seg; 1444 int ofree = sc->sc_txfree; 1445 #if 0 1446 int firsttx = sc->sc_txnext; 1447 #endif 1448 1449 /* 1450 * If we've been told to pause, don't transmit any more packets. 1451 */ 1452 if (!sc->sc_gigabit && sc->sc_paused) 1453 ifp->if_flags |= IFF_OACTIVE; 1454 1455 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1456 return; 1457 1458 /* 1459 * Loop through the send queue, setting up transmit descriptors 1460 * until we drain the queue, or use up all available transmit 1461 * descriptors. 1462 */ 1463 for (;;) { 1464 /* Get a work queue entry. */ 1465 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1466 SIP_EVCNT_INCR(&sc->sc_ev_txsstall); 1467 break; 1468 } 1469 1470 /* 1471 * Grab a packet off the queue. 1472 */ 1473 IFQ_POLL(&ifp->if_snd, m0); 1474 if (m0 == NULL) 1475 break; 1476 m = NULL; 1477 1478 dmamap = txs->txs_dmamap; 1479 1480 /* 1481 * Load the DMA map. If this fails, the packet either 1482 * didn't fit in the alloted number of segments, or we 1483 * were short on resources. 1484 */ 1485 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 1486 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1487 /* In the non-gigabit case, we'll copy and try again. */ 1488 if (error != 0 && !sc->sc_gigabit) { 1489 MGETHDR(m, M_DONTWAIT, MT_DATA); 1490 if (m == NULL) { 1491 printf("%s: unable to allocate Tx mbuf\n", 1492 device_xname(sc->sc_dev)); 1493 break; 1494 } 1495 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1496 if (m0->m_pkthdr.len > MHLEN) { 1497 MCLGET(m, M_DONTWAIT); 1498 if ((m->m_flags & M_EXT) == 0) { 1499 printf("%s: unable to allocate Tx " 1500 "cluster\n", 1501 device_xname(sc->sc_dev)); 1502 m_freem(m); 1503 break; 1504 } 1505 } 1506 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1507 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1508 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1509 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1510 if (error) { 1511 printf("%s: unable to load Tx buffer, error = " 1512 "%d\n", device_xname(sc->sc_dev), error); 1513 break; 1514 } 1515 } else if (error == EFBIG) { 1516 /* 1517 * For the too-many-segments case, we simply 1518 * report an error and drop the packet, 1519 * since we can't sanely copy a jumbo packet 1520 * to a single buffer. 1521 */ 1522 printf("%s: Tx packet consumes too many DMA segments, " 1523 "dropping...\n", device_xname(sc->sc_dev)); 1524 IFQ_DEQUEUE(&ifp->if_snd, m0); 1525 m_freem(m0); 1526 continue; 1527 } else if (error != 0) { 1528 /* 1529 * Short on resources, just stop for now. 1530 */ 1531 break; 1532 } 1533 1534 /* 1535 * Ensure we have enough descriptors free to describe 1536 * the packet. Note, we always reserve one descriptor 1537 * at the end of the ring as a termination point, to 1538 * prevent wrap-around. 1539 */ 1540 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 1541 /* 1542 * Not enough free descriptors to transmit this 1543 * packet. We haven't committed anything yet, 1544 * so just unload the DMA map, put the packet 1545 * back on the queue, and punt. Notify the upper 1546 * layer that there are not more slots left. 1547 * 1548 * XXX We could allocate an mbuf and copy, but 1549 * XXX is it worth it? 1550 */ 1551 ifp->if_flags |= IFF_OACTIVE; 1552 bus_dmamap_unload(sc->sc_dmat, dmamap); 1553 if (m != NULL) 1554 m_freem(m); 1555 SIP_EVCNT_INCR(&sc->sc_ev_txdstall); 1556 break; 1557 } 1558 1559 IFQ_DEQUEUE(&ifp->if_snd, m0); 1560 if (m != NULL) { 1561 m_freem(m0); 1562 m0 = m; 1563 } 1564 1565 /* 1566 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1567 */ 1568 1569 /* Sync the DMA map. */ 1570 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1571 BUS_DMASYNC_PREWRITE); 1572 1573 /* 1574 * Initialize the transmit descriptors. 1575 */ 1576 for (nexttx = lasttx = sc->sc_txnext, seg = 0; 1577 seg < dmamap->dm_nsegs; 1578 seg++, nexttx = sip_nexttx(sc, nexttx)) { 1579 /* 1580 * If this is the first descriptor we're 1581 * enqueueing, don't set the OWN bit just 1582 * yet. That could cause a race condition. 1583 * We'll do it below. 1584 */ 1585 *sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) = 1586 htole32(dmamap->dm_segs[seg].ds_addr); 1587 *sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) = 1588 htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) 1589 | CMDSTS_MORE | dmamap->dm_segs[seg].ds_len); 1590 sc->sc_txdescs[nexttx].sipd_extsts = 0; 1591 lasttx = nexttx; 1592 } 1593 1594 /* Clear the MORE bit on the last segment. */ 1595 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &= 1596 htole32(~CMDSTS_MORE); 1597 1598 /* 1599 * If we're in the interrupt delay window, delay the 1600 * interrupt. 1601 */ 1602 if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) { 1603 SIP_EVCNT_INCR(&sc->sc_ev_txforceintr); 1604 *sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |= 1605 htole32(CMDSTS_INTR); 1606 sc->sc_txwin = 0; 1607 } 1608 1609 if (sc->sc_gigabit) 1610 sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable); 1611 1612 /* Sync the descriptors we're using. */ 1613 sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs, 1614 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1615 1616 /* 1617 * The entire packet is set up. Give the first descrptor 1618 * to the chip now. 1619 */ 1620 *sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |= 1621 htole32(CMDSTS_OWN); 1622 sip_cdtxsync(sc, sc->sc_txnext, 1, 1623 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1624 1625 /* 1626 * Store a pointer to the packet so we can free it later, 1627 * and remember what txdirty will be once the packet is 1628 * done. 1629 */ 1630 txs->txs_mbuf = m0; 1631 txs->txs_firstdesc = sc->sc_txnext; 1632 txs->txs_lastdesc = lasttx; 1633 1634 /* Advance the tx pointer. */ 1635 sc->sc_txfree -= dmamap->dm_nsegs; 1636 sc->sc_txnext = nexttx; 1637 1638 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1639 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1640 1641 /* Pass the packet to any BPF listeners. */ 1642 bpf_mtap(ifp, m0, BPF_D_OUT); 1643 } 1644 1645 if (txs == NULL || sc->sc_txfree == 0) { 1646 /* No more slots left; notify upper layer. */ 1647 ifp->if_flags |= IFF_OACTIVE; 1648 } 1649 1650 if (sc->sc_txfree != ofree) { 1651 /* 1652 * Start the transmit process. Note, the manual says 1653 * that if there are no pending transmissions in the 1654 * chip's internal queue (indicated by TXE being clear), 1655 * then the driver software must set the TXDP to the 1656 * first descriptor to be transmitted. However, if we 1657 * do this, it causes serious performance degredation on 1658 * the DP83820 under load, not setting TXDP doesn't seem 1659 * to adversely affect the SiS 900 or DP83815. 1660 * 1661 * Well, I guess it wouldn't be the first time a manual 1662 * has lied -- and they could be speaking of the NULL- 1663 * terminated descriptor list case, rather than OWN- 1664 * terminated rings. 1665 */ 1666 #if 0 1667 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) & 1668 CR_TXE) == 0) { 1669 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP, 1670 SIP_CDTXADDR(sc, firsttx)); 1671 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1672 } 1673 #else 1674 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE); 1675 #endif 1676 1677 /* Set a watchdog timer in case the chip flakes out. */ 1678 /* Gigabit autonegotiation takes 5 seconds. */ 1679 ifp->if_timer = (sc->sc_gigabit) ? 10 : 5; 1680 } 1681 } 1682 1683 /* 1684 * sip_watchdog: [ifnet interface function] 1685 * 1686 * Watchdog timer handler. 1687 */ 1688 static void 1689 sipcom_watchdog(struct ifnet *ifp) 1690 { 1691 struct sip_softc *sc = ifp->if_softc; 1692 1693 /* 1694 * The chip seems to ignore the CMDSTS_INTR bit sometimes! 1695 * If we get a timeout, try and sweep up transmit descriptors. 1696 * If we manage to sweep them all up, ignore the lack of 1697 * interrupt. 1698 */ 1699 sipcom_txintr(sc); 1700 1701 if (sc->sc_txfree != sc->sc_ntxdesc) { 1702 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 1703 ifp->if_oerrors++; 1704 1705 /* Reset the interface. */ 1706 (void) sipcom_init(ifp); 1707 } else if (ifp->if_flags & IFF_DEBUG) 1708 printf("%s: recovered from device timeout\n", 1709 device_xname(sc->sc_dev)); 1710 1711 /* Try to get more packets going. */ 1712 sipcom_start(ifp); 1713 } 1714 1715 /* If the interface is up and running, only modify the receive 1716 * filter when setting promiscuous or debug mode. Otherwise fall 1717 * through to ether_ioctl, which will reset the chip. 1718 */ 1719 static int 1720 sip_ifflags_cb(struct ethercom *ec) 1721 { 1722 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable \ 1723 == (sc)->sc_ethercom.ec_capenable) \ 1724 && ((sc)->sc_prev.is_vlan == \ 1725 VLAN_ATTACHED(&(sc)->sc_ethercom) )) 1726 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable) 1727 struct ifnet *ifp = &ec->ec_if; 1728 struct sip_softc *sc = ifp->if_softc; 1729 int change = ifp->if_flags ^ sc->sc_if_flags; 1730 1731 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) || 1732 !COMPARE_IC(sc, ifp)) 1733 return ENETRESET; 1734 /* Set up the receive filter. */ 1735 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1736 return 0; 1737 } 1738 1739 /* 1740 * sip_ioctl: [ifnet interface function] 1741 * 1742 * Handle control requests from the operator. 1743 */ 1744 static int 1745 sipcom_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1746 { 1747 struct sip_softc *sc = ifp->if_softc; 1748 struct ifreq *ifr = (struct ifreq *)data; 1749 int s, error; 1750 1751 s = splnet(); 1752 1753 switch (cmd) { 1754 case SIOCSIFMEDIA: 1755 /* Flow control requires full-duplex mode. */ 1756 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 1757 (ifr->ifr_media & IFM_FDX) == 0) 1758 ifr->ifr_media &= ~IFM_ETH_FMASK; 1759 1760 /* XXX */ 1761 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) 1762 ifr->ifr_media &= ~IFM_ETH_FMASK; 1763 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 1764 if (sc->sc_gigabit && 1765 (ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 1766 /* We can do both TXPAUSE and RXPAUSE. */ 1767 ifr->ifr_media |= 1768 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1769 } else if (ifr->ifr_media & IFM_FLOW) { 1770 /* 1771 * Both TXPAUSE and RXPAUSE must be set. 1772 * (SiS900 and DP83815 don't have PAUSE_ASYM 1773 * feature.) 1774 * 1775 * XXX Can SiS900 and DP83815 send PAUSE? 1776 */ 1777 ifr->ifr_media |= 1778 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 1779 } 1780 sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 1781 } 1782 /*FALLTHROUGH*/ 1783 default: 1784 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1785 break; 1786 1787 error = 0; 1788 1789 if (cmd == SIOCSIFCAP) 1790 error = (*ifp->if_init)(ifp); 1791 else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1792 ; 1793 else if (ifp->if_flags & IFF_RUNNING) { 1794 /* 1795 * Multicast list has changed; set the hardware filter 1796 * accordingly. 1797 */ 1798 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 1799 } 1800 break; 1801 } 1802 1803 /* Try to get more packets going. */ 1804 sipcom_start(ifp); 1805 1806 sc->sc_if_flags = ifp->if_flags; 1807 splx(s); 1808 return error; 1809 } 1810 1811 /* 1812 * sip_intr: 1813 * 1814 * Interrupt service routine. 1815 */ 1816 static int 1817 sipcom_intr(void *arg) 1818 { 1819 struct sip_softc *sc = arg; 1820 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1821 uint32_t isr; 1822 int handled = 0; 1823 1824 if (!device_activation(sc->sc_dev, DEVACT_LEVEL_DRIVER)) 1825 return 0; 1826 1827 /* Disable interrupts. */ 1828 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, 0); 1829 1830 for (;;) { 1831 /* Reading clears interrupt. */ 1832 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ISR); 1833 if ((isr & sc->sc_imr) == 0) 1834 break; 1835 1836 rnd_add_uint32(&sc->rnd_source, isr); 1837 1838 handled = 1; 1839 1840 if ((ifp->if_flags & IFF_RUNNING) == 0) 1841 break; 1842 1843 if (isr & (ISR_RXORN|ISR_RXIDLE|ISR_RXDESC)) { 1844 SIP_EVCNT_INCR(&sc->sc_ev_rxintr); 1845 1846 /* Grab any new packets. */ 1847 (*sc->sc_rxintr)(sc); 1848 1849 if (isr & ISR_RXORN) { 1850 printf("%s: receive FIFO overrun\n", 1851 device_xname(sc->sc_dev)); 1852 1853 /* XXX adjust rx_drain_thresh? */ 1854 } 1855 1856 if (isr & ISR_RXIDLE) { 1857 printf("%s: receive ring overrun\n", 1858 device_xname(sc->sc_dev)); 1859 1860 /* Get the receive process going again. */ 1861 bus_space_write_4(sc->sc_st, sc->sc_sh, 1862 SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 1863 bus_space_write_4(sc->sc_st, sc->sc_sh, 1864 SIP_CR, CR_RXE); 1865 } 1866 } 1867 1868 if (isr & (ISR_TXURN|ISR_TXDESC|ISR_TXIDLE)) { 1869 #ifdef SIP_EVENT_COUNTERS 1870 if (isr & ISR_TXDESC) 1871 SIP_EVCNT_INCR(&sc->sc_ev_txdintr); 1872 else if (isr & ISR_TXIDLE) 1873 SIP_EVCNT_INCR(&sc->sc_ev_txiintr); 1874 #endif 1875 1876 /* Sweep up transmit descriptors. */ 1877 sipcom_txintr(sc); 1878 1879 if (isr & ISR_TXURN) { 1880 uint32_t thresh; 1881 int txfifo_size = (sc->sc_gigabit) 1882 ? DP83820_SIP_TXFIFO_SIZE 1883 : OTHER_SIP_TXFIFO_SIZE; 1884 1885 printf("%s: transmit FIFO underrun", 1886 device_xname(sc->sc_dev)); 1887 thresh = sc->sc_tx_drain_thresh + 1; 1888 if (thresh <= __SHIFTOUT_MASK(sc->sc_bits.b_txcfg_drth_mask) 1889 && (thresh * 32) <= (txfifo_size - 1890 (sc->sc_tx_fill_thresh * 32))) { 1891 printf("; increasing Tx drain " 1892 "threshold to %u bytes\n", 1893 thresh * 32); 1894 sc->sc_tx_drain_thresh = thresh; 1895 (void) sipcom_init(ifp); 1896 } else { 1897 (void) sipcom_init(ifp); 1898 printf("\n"); 1899 } 1900 } 1901 } 1902 1903 if (sc->sc_imr & (ISR_PAUSE_END|ISR_PAUSE_ST)) { 1904 if (isr & ISR_PAUSE_ST) { 1905 sc->sc_paused = 1; 1906 SIP_EVCNT_INCR(&sc->sc_ev_rxpause); 1907 ifp->if_flags |= IFF_OACTIVE; 1908 } 1909 if (isr & ISR_PAUSE_END) { 1910 sc->sc_paused = 0; 1911 ifp->if_flags &= ~IFF_OACTIVE; 1912 } 1913 } 1914 1915 if (isr & ISR_HIBERR) { 1916 int want_init = 0; 1917 1918 SIP_EVCNT_INCR(&sc->sc_ev_hiberr); 1919 1920 #define PRINTERR(bit, str) \ 1921 do { \ 1922 if ((isr & (bit)) != 0) { \ 1923 if ((ifp->if_flags & IFF_DEBUG) != 0) \ 1924 printf("%s: %s\n", \ 1925 device_xname(sc->sc_dev), str); \ 1926 want_init = 1; \ 1927 } \ 1928 } while (/*CONSTCOND*/0) 1929 1930 PRINTERR(sc->sc_bits.b_isr_dperr, "parity error"); 1931 PRINTERR(sc->sc_bits.b_isr_sserr, "system error"); 1932 PRINTERR(sc->sc_bits.b_isr_rmabt, "master abort"); 1933 PRINTERR(sc->sc_bits.b_isr_rtabt, "target abort"); 1934 PRINTERR(ISR_RXSOVR, "receive status FIFO overrun"); 1935 /* 1936 * Ignore: 1937 * Tx reset complete 1938 * Rx reset complete 1939 */ 1940 if (want_init) 1941 (void) sipcom_init(ifp); 1942 #undef PRINTERR 1943 } 1944 } 1945 1946 /* Re-enable interrupts. */ 1947 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IER, IER_IE); 1948 1949 /* Try to get more packets going. */ 1950 if_schedule_deferred_start(ifp); 1951 1952 return handled; 1953 } 1954 1955 /* 1956 * sip_txintr: 1957 * 1958 * Helper; handle transmit interrupts. 1959 */ 1960 static void 1961 sipcom_txintr(struct sip_softc *sc) 1962 { 1963 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1964 struct sip_txsoft *txs; 1965 uint32_t cmdsts; 1966 1967 if (sc->sc_paused == 0) 1968 ifp->if_flags &= ~IFF_OACTIVE; 1969 1970 /* 1971 * Go through our Tx list and free mbufs for those 1972 * frames which have been transmitted. 1973 */ 1974 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1975 sip_cdtxsync(sc, txs->txs_firstdesc, txs->txs_dmamap->dm_nsegs, 1976 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1977 1978 cmdsts = le32toh(*sipd_cmdsts(sc, 1979 &sc->sc_txdescs[txs->txs_lastdesc])); 1980 if (cmdsts & CMDSTS_OWN) 1981 break; 1982 1983 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1984 1985 sc->sc_txfree += txs->txs_dmamap->dm_nsegs; 1986 1987 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1988 0, txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1989 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1990 m_freem(txs->txs_mbuf); 1991 txs->txs_mbuf = NULL; 1992 1993 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1994 1995 /* Check for errors and collisions. */ 1996 if (cmdsts & 1997 (CMDSTS_Tx_TXA|CMDSTS_Tx_TFU|CMDSTS_Tx_ED|CMDSTS_Tx_EC)) { 1998 ifp->if_oerrors++; 1999 if (cmdsts & CMDSTS_Tx_EC) 2000 ifp->if_collisions += 16; 2001 if (ifp->if_flags & IFF_DEBUG) { 2002 if (cmdsts & CMDSTS_Tx_ED) 2003 printf("%s: excessive deferral\n", 2004 device_xname(sc->sc_dev)); 2005 if (cmdsts & CMDSTS_Tx_EC) 2006 printf("%s: excessive collisions\n", 2007 device_xname(sc->sc_dev)); 2008 } 2009 } else { 2010 /* Packet was transmitted successfully. */ 2011 ifp->if_opackets++; 2012 ifp->if_collisions += CMDSTS_COLLISIONS(cmdsts); 2013 } 2014 } 2015 2016 /* 2017 * If there are no more pending transmissions, cancel the watchdog 2018 * timer. 2019 */ 2020 if (txs == NULL) { 2021 ifp->if_timer = 0; 2022 sc->sc_txwin = 0; 2023 } 2024 } 2025 2026 /* 2027 * gsip_rxintr: 2028 * 2029 * Helper; handle receive interrupts on gigabit parts. 2030 */ 2031 static void 2032 gsip_rxintr(struct sip_softc *sc) 2033 { 2034 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2035 struct sip_rxsoft *rxs; 2036 struct mbuf *m; 2037 uint32_t cmdsts, extsts; 2038 int i, len; 2039 2040 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2041 rxs = &sc->sc_rxsoft[i]; 2042 2043 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2044 2045 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2046 extsts = le32toh(sc->sc_rxdescs[i].sipd_extsts); 2047 len = CMDSTS_SIZE(sc, cmdsts); 2048 2049 /* 2050 * NOTE: OWN is set if owned by _consumer_. We're the 2051 * consumer of the receive ring, so if the bit is clear, 2052 * we have processed all of the packets. 2053 */ 2054 if ((cmdsts & CMDSTS_OWN) == 0) { 2055 /* 2056 * We have processed all of the receive buffers. 2057 */ 2058 break; 2059 } 2060 2061 if (__predict_false(sc->sc_rxdiscard)) { 2062 sip_init_rxdesc(sc, i); 2063 if ((cmdsts & CMDSTS_MORE) == 0) { 2064 /* Reset our state. */ 2065 sc->sc_rxdiscard = 0; 2066 } 2067 continue; 2068 } 2069 2070 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2071 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2072 2073 m = rxs->rxs_mbuf; 2074 2075 /* 2076 * Add a new receive buffer to the ring. 2077 */ 2078 if (sipcom_add_rxbuf(sc, i) != 0) { 2079 /* 2080 * Failed, throw away what we've done so 2081 * far, and discard the rest of the packet. 2082 */ 2083 ifp->if_ierrors++; 2084 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2085 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2086 sip_init_rxdesc(sc, i); 2087 if (cmdsts & CMDSTS_MORE) 2088 sc->sc_rxdiscard = 1; 2089 if (sc->sc_rxhead != NULL) 2090 m_freem(sc->sc_rxhead); 2091 sip_rxchain_reset(sc); 2092 continue; 2093 } 2094 2095 sip_rxchain_link(sc, m); 2096 2097 m->m_len = len; 2098 2099 /* 2100 * If this is not the end of the packet, keep 2101 * looking. 2102 */ 2103 if (cmdsts & CMDSTS_MORE) { 2104 sc->sc_rxlen += len; 2105 continue; 2106 } 2107 2108 /* 2109 * Okay, we have the entire packet now. The chip includes 2110 * the FCS, so we need to trim it. 2111 */ 2112 m->m_len -= ETHER_CRC_LEN; 2113 2114 *sc->sc_rxtailp = NULL; 2115 len = m->m_len + sc->sc_rxlen; 2116 m = sc->sc_rxhead; 2117 2118 sip_rxchain_reset(sc); 2119 2120 /* If an error occurred, update stats and drop the packet. */ 2121 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2122 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2123 ifp->if_ierrors++; 2124 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2125 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2126 /* Receive overrun handled elsewhere. */ 2127 printf("%s: receive descriptor error\n", 2128 device_xname(sc->sc_dev)); 2129 } 2130 #define PRINTERR(bit, str) \ 2131 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2132 (cmdsts & (bit)) != 0) \ 2133 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2134 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2135 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2136 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2137 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2138 #undef PRINTERR 2139 m_freem(m); 2140 continue; 2141 } 2142 2143 /* 2144 * If the packet is small enough to fit in a 2145 * single header mbuf, allocate one and copy 2146 * the data into it. This greatly reduces 2147 * memory consumption when we receive lots 2148 * of small packets. 2149 */ 2150 if (gsip_copy_small != 0 && len <= (MHLEN - 2)) { 2151 struct mbuf *nm; 2152 MGETHDR(nm, M_DONTWAIT, MT_DATA); 2153 if (nm == NULL) { 2154 ifp->if_ierrors++; 2155 m_freem(m); 2156 continue; 2157 } 2158 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2159 nm->m_data += 2; 2160 nm->m_pkthdr.len = nm->m_len = len; 2161 m_copydata(m, 0, len, mtod(nm, void *)); 2162 m_freem(m); 2163 m = nm; 2164 } 2165 #ifndef __NO_STRICT_ALIGNMENT 2166 else { 2167 /* 2168 * The DP83820's receive buffers must be 4-byte 2169 * aligned. But this means that the data after 2170 * the Ethernet header is misaligned. To compensate, 2171 * we have artificially shortened the buffer size 2172 * in the descriptor, and we do an overlapping copy 2173 * of the data two bytes further in (in the first 2174 * buffer of the chain only). 2175 */ 2176 memmove(mtod(m, char *) + 2, mtod(m, void *), 2177 m->m_len); 2178 m->m_data += 2; 2179 } 2180 #endif /* ! __NO_STRICT_ALIGNMENT */ 2181 2182 /* 2183 * If VLANs are enabled, VLAN packets have been unwrapped 2184 * for us. Associate the tag with the packet. 2185 */ 2186 2187 /* 2188 * Again, byte swapping is tricky. Hardware provided 2189 * the tag in the network byte order, but extsts was 2190 * passed through le32toh() in the meantime. On a 2191 * big-endian machine, we need to swap it again. On a 2192 * little-endian machine, we need to convert from the 2193 * network to host byte order. This means that we must 2194 * swap it in any case, so unconditional swap instead 2195 * of htons() is used. 2196 */ 2197 if ((extsts & EXTSTS_VPKT) != 0) { 2198 vlan_set_tag(m, bswap16(extsts & EXTSTS_VTCI)); 2199 } 2200 2201 /* 2202 * Set the incoming checksum information for the 2203 * packet. 2204 */ 2205 if ((extsts & EXTSTS_IPPKT) != 0) { 2206 SIP_EVCNT_INCR(&sc->sc_ev_rxipsum); 2207 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2208 if (extsts & EXTSTS_Rx_IPERR) 2209 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2210 if (extsts & EXTSTS_TCPPKT) { 2211 SIP_EVCNT_INCR(&sc->sc_ev_rxtcpsum); 2212 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 2213 if (extsts & EXTSTS_Rx_TCPERR) 2214 m->m_pkthdr.csum_flags |= 2215 M_CSUM_TCP_UDP_BAD; 2216 } else if (extsts & EXTSTS_UDPPKT) { 2217 SIP_EVCNT_INCR(&sc->sc_ev_rxudpsum); 2218 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 2219 if (extsts & EXTSTS_Rx_UDPERR) 2220 m->m_pkthdr.csum_flags |= 2221 M_CSUM_TCP_UDP_BAD; 2222 } 2223 } 2224 2225 m_set_rcvif(m, ifp); 2226 m->m_pkthdr.len = len; 2227 2228 /* Pass it on. */ 2229 if_percpuq_enqueue(ifp->if_percpuq, m); 2230 } 2231 2232 /* Update the receive pointer. */ 2233 sc->sc_rxptr = i; 2234 } 2235 2236 /* 2237 * sip_rxintr: 2238 * 2239 * Helper; handle receive interrupts on 10/100 parts. 2240 */ 2241 static void 2242 sip_rxintr(struct sip_softc *sc) 2243 { 2244 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2245 struct sip_rxsoft *rxs; 2246 struct mbuf *m; 2247 uint32_t cmdsts; 2248 int i, len; 2249 2250 for (i = sc->sc_rxptr;; i = sip_nextrx(sc, i)) { 2251 rxs = &sc->sc_rxsoft[i]; 2252 2253 sip_cdrxsync(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2254 2255 cmdsts = le32toh(*sipd_cmdsts(sc, &sc->sc_rxdescs[i])); 2256 2257 /* 2258 * NOTE: OWN is set if owned by _consumer_. We're the 2259 * consumer of the receive ring, so if the bit is clear, 2260 * we have processed all of the packets. 2261 */ 2262 if ((cmdsts & CMDSTS_OWN) == 0) { 2263 /* 2264 * We have processed all of the receive buffers. 2265 */ 2266 break; 2267 } 2268 2269 /* If any collisions were seen on the wire, count one. */ 2270 if (cmdsts & CMDSTS_Rx_COL) 2271 ifp->if_collisions++; 2272 2273 /* 2274 * If an error occurred, update stats, clear the status 2275 * word, and leave the packet buffer in place. It will 2276 * simply be reused the next time the ring comes around. 2277 */ 2278 if (cmdsts & (CMDSTS_Rx_RXA|CMDSTS_Rx_RUNT| 2279 CMDSTS_Rx_ISE|CMDSTS_Rx_CRCE|CMDSTS_Rx_FAE)) { 2280 ifp->if_ierrors++; 2281 if ((cmdsts & CMDSTS_Rx_RXA) != 0 && 2282 (cmdsts & CMDSTS_Rx_RXO) == 0) { 2283 /* Receive overrun handled elsewhere. */ 2284 printf("%s: receive descriptor error\n", 2285 device_xname(sc->sc_dev)); 2286 } 2287 #define PRINTERR(bit, str) \ 2288 if ((ifp->if_flags & IFF_DEBUG) != 0 && \ 2289 (cmdsts & (bit)) != 0) \ 2290 printf("%s: %s\n", device_xname(sc->sc_dev), str) 2291 PRINTERR(CMDSTS_Rx_RUNT, "runt packet"); 2292 PRINTERR(CMDSTS_Rx_ISE, "invalid symbol error"); 2293 PRINTERR(CMDSTS_Rx_CRCE, "CRC error"); 2294 PRINTERR(CMDSTS_Rx_FAE, "frame alignment error"); 2295 #undef PRINTERR 2296 sip_init_rxdesc(sc, i); 2297 continue; 2298 } 2299 2300 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2301 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 2302 2303 /* 2304 * No errors; receive the packet. Note, the SiS 900 2305 * includes the CRC with every packet. 2306 */ 2307 len = CMDSTS_SIZE(sc, cmdsts) - ETHER_CRC_LEN; 2308 2309 #ifdef __NO_STRICT_ALIGNMENT 2310 /* 2311 * If the packet is small enough to fit in a 2312 * single header mbuf, allocate one and copy 2313 * the data into it. This greatly reduces 2314 * memory consumption when we receive lots 2315 * of small packets. 2316 * 2317 * Otherwise, we add a new buffer to the receive 2318 * chain. If this fails, we drop the packet and 2319 * recycle the old buffer. 2320 */ 2321 if (sip_copy_small != 0 && len <= MHLEN) { 2322 MGETHDR(m, M_DONTWAIT, MT_DATA); 2323 if (m == NULL) 2324 goto dropit; 2325 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2326 memcpy(mtod(m, void *), 2327 mtod(rxs->rxs_mbuf, void *), len); 2328 sip_init_rxdesc(sc, i); 2329 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2330 rxs->rxs_dmamap->dm_mapsize, 2331 BUS_DMASYNC_PREREAD); 2332 } else { 2333 m = rxs->rxs_mbuf; 2334 if (sipcom_add_rxbuf(sc, i) != 0) { 2335 dropit: 2336 ifp->if_ierrors++; 2337 sip_init_rxdesc(sc, i); 2338 bus_dmamap_sync(sc->sc_dmat, 2339 rxs->rxs_dmamap, 0, 2340 rxs->rxs_dmamap->dm_mapsize, 2341 BUS_DMASYNC_PREREAD); 2342 continue; 2343 } 2344 } 2345 #else 2346 /* 2347 * The SiS 900's receive buffers must be 4-byte aligned. 2348 * But this means that the data after the Ethernet header 2349 * is misaligned. We must allocate a new buffer and 2350 * copy the data, shifted forward 2 bytes. 2351 */ 2352 MGETHDR(m, M_DONTWAIT, MT_DATA); 2353 if (m == NULL) { 2354 dropit: 2355 ifp->if_ierrors++; 2356 sip_init_rxdesc(sc, i); 2357 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2358 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2359 continue; 2360 } 2361 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2362 if (len > (MHLEN - 2)) { 2363 MCLGET(m, M_DONTWAIT); 2364 if ((m->m_flags & M_EXT) == 0) { 2365 m_freem(m); 2366 goto dropit; 2367 } 2368 } 2369 m->m_data += 2; 2370 2371 /* 2372 * Note that we use clusters for incoming frames, so the 2373 * buffer is virtually contiguous. 2374 */ 2375 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 2376 2377 /* Allow the receive descriptor to continue using its mbuf. */ 2378 sip_init_rxdesc(sc, i); 2379 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2380 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2381 #endif /* __NO_STRICT_ALIGNMENT */ 2382 2383 m_set_rcvif(m, ifp); 2384 m->m_pkthdr.len = m->m_len = len; 2385 2386 /* Pass it on. */ 2387 if_percpuq_enqueue(ifp->if_percpuq, m); 2388 } 2389 2390 /* Update the receive pointer. */ 2391 sc->sc_rxptr = i; 2392 } 2393 2394 /* 2395 * sip_tick: 2396 * 2397 * One second timer, used to tick the MII. 2398 */ 2399 static void 2400 sipcom_tick(void *arg) 2401 { 2402 struct sip_softc *sc = arg; 2403 int s; 2404 2405 s = splnet(); 2406 #ifdef SIP_EVENT_COUNTERS 2407 if (sc->sc_gigabit) { 2408 /* Read PAUSE related counts from MIB registers. */ 2409 sc->sc_ev_rxpause.ev_count += 2410 bus_space_read_4(sc->sc_st, sc->sc_sh, 2411 SIP_NS_MIB(MIB_RXPauseFrames)) & 0xffff; 2412 sc->sc_ev_txpause.ev_count += 2413 bus_space_read_4(sc->sc_st, sc->sc_sh, 2414 SIP_NS_MIB(MIB_TXPauseFrames)) & 0xffff; 2415 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_MIBC, MIBC_ACLR); 2416 } 2417 #endif /* SIP_EVENT_COUNTERS */ 2418 mii_tick(&sc->sc_mii); 2419 splx(s); 2420 2421 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2422 } 2423 2424 /* 2425 * sip_reset: 2426 * 2427 * Perform a soft reset on the SiS 900. 2428 */ 2429 static bool 2430 sipcom_reset(struct sip_softc *sc) 2431 { 2432 bus_space_tag_t st = sc->sc_st; 2433 bus_space_handle_t sh = sc->sc_sh; 2434 int i; 2435 2436 bus_space_write_4(st, sh, SIP_IER, 0); 2437 bus_space_write_4(st, sh, SIP_IMR, 0); 2438 bus_space_write_4(st, sh, SIP_RFCR, 0); 2439 bus_space_write_4(st, sh, SIP_CR, CR_RST); 2440 2441 for (i = 0; i < SIP_TIMEOUT; i++) { 2442 if ((bus_space_read_4(st, sh, SIP_CR) & CR_RST) == 0) 2443 break; 2444 delay(2); 2445 } 2446 2447 if (i == SIP_TIMEOUT) { 2448 printf("%s: reset failed to complete\n", 2449 device_xname(sc->sc_dev)); 2450 return false; 2451 } 2452 2453 delay(1000); 2454 2455 if (sc->sc_gigabit) { 2456 /* 2457 * Set the general purpose I/O bits. Do it here in case we 2458 * need to have GPIO set up to talk to the media interface. 2459 */ 2460 bus_space_write_4(st, sh, SIP_GPIOR, sc->sc_gpior); 2461 delay(1000); 2462 } 2463 return true; 2464 } 2465 2466 static void 2467 sipcom_dp83820_init(struct sip_softc *sc, uint64_t capenable) 2468 { 2469 uint32_t reg; 2470 bus_space_tag_t st = sc->sc_st; 2471 bus_space_handle_t sh = sc->sc_sh; 2472 /* 2473 * Initialize the VLAN/IP receive control register. 2474 * We enable checksum computation on all incoming 2475 * packets, and do not reject packets w/ bad checksums. 2476 */ 2477 reg = 0; 2478 if (capenable & 2479 (IFCAP_CSUM_IPv4_Rx|IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 2480 reg |= VRCR_IPEN; 2481 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2482 reg |= VRCR_VTDEN|VRCR_VTREN; 2483 bus_space_write_4(st, sh, SIP_VRCR, reg); 2484 2485 /* 2486 * Initialize the VLAN/IP transmit control register. 2487 * We enable outgoing checksum computation on a 2488 * per-packet basis. 2489 */ 2490 reg = 0; 2491 if (capenable & 2492 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 2493 reg |= VTCR_PPCHK; 2494 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2495 reg |= VTCR_VPPTI; 2496 bus_space_write_4(st, sh, SIP_VTCR, reg); 2497 2498 /* 2499 * If we're using VLANs, initialize the VLAN data register. 2500 * To understand why we bswap the VLAN Ethertype, see section 2501 * 4.2.36 of the DP83820 manual. 2502 */ 2503 if (VLAN_ATTACHED(&sc->sc_ethercom)) 2504 bus_space_write_4(st, sh, SIP_VDR, bswap16(ETHERTYPE_VLAN)); 2505 } 2506 2507 /* 2508 * sip_init: [ ifnet interface function ] 2509 * 2510 * Initialize the interface. Must be called at splnet(). 2511 */ 2512 static int 2513 sipcom_init(struct ifnet *ifp) 2514 { 2515 struct sip_softc *sc = ifp->if_softc; 2516 bus_space_tag_t st = sc->sc_st; 2517 bus_space_handle_t sh = sc->sc_sh; 2518 struct sip_txsoft *txs; 2519 struct sip_rxsoft *rxs; 2520 struct sip_desc *sipd; 2521 int i, error = 0; 2522 2523 if (device_is_active(sc->sc_dev)) { 2524 /* 2525 * Cancel any pending I/O. 2526 */ 2527 sipcom_stop(ifp, 0); 2528 } else if (!pmf_device_subtree_resume(sc->sc_dev, &sc->sc_qual) || 2529 !device_is_active(sc->sc_dev)) 2530 return 0; 2531 2532 /* 2533 * Reset the chip to a known state. 2534 */ 2535 if (!sipcom_reset(sc)) 2536 return EBUSY; 2537 2538 if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815)) { 2539 /* 2540 * DP83815 manual, page 78: 2541 * 4.4 Recommended Registers Configuration 2542 * For optimum performance of the DP83815, version noted 2543 * as DP83815CVNG (SRR = 203h), the listed register 2544 * modifications must be followed in sequence... 2545 * 2546 * It's not clear if this should be 302h or 203h because that 2547 * chip name is listed as SRR 302h in the description of the 2548 * SRR register. However, my revision 302h DP83815 on the 2549 * Netgear FA311 purchased in 02/2001 needs these settings 2550 * to avoid tons of errors in AcceptPerfectMatch (non- 2551 * IFF_PROMISC) mode. I do not know if other revisions need 2552 * this set or not. [briggs -- 09 March 2001] 2553 * 2554 * Note that only the low-order 12 bits of 0xe4 are documented 2555 * and that this sets reserved bits in that register. 2556 */ 2557 bus_space_write_4(st, sh, 0x00cc, 0x0001); 2558 2559 bus_space_write_4(st, sh, 0x00e4, 0x189C); 2560 bus_space_write_4(st, sh, 0x00fc, 0x0000); 2561 bus_space_write_4(st, sh, 0x00f4, 0x5040); 2562 bus_space_write_4(st, sh, 0x00f8, 0x008c); 2563 2564 bus_space_write_4(st, sh, 0x00cc, 0x0000); 2565 } 2566 2567 /* 2568 * Initialize the transmit descriptor ring. 2569 */ 2570 for (i = 0; i < sc->sc_ntxdesc; i++) { 2571 sipd = &sc->sc_txdescs[i]; 2572 memset(sipd, 0, sizeof(struct sip_desc)); 2573 sipd->sipd_link = htole32(SIP_CDTXADDR(sc, sip_nexttx(sc, i))); 2574 } 2575 sip_cdtxsync(sc, 0, sc->sc_ntxdesc, 2576 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2577 sc->sc_txfree = sc->sc_ntxdesc; 2578 sc->sc_txnext = 0; 2579 sc->sc_txwin = 0; 2580 2581 /* 2582 * Initialize the transmit job descriptors. 2583 */ 2584 SIMPLEQ_INIT(&sc->sc_txfreeq); 2585 SIMPLEQ_INIT(&sc->sc_txdirtyq); 2586 for (i = 0; i < SIP_TXQUEUELEN; i++) { 2587 txs = &sc->sc_txsoft[i]; 2588 txs->txs_mbuf = NULL; 2589 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2590 } 2591 2592 /* 2593 * Initialize the receive descriptor and receive job 2594 * descriptor rings. 2595 */ 2596 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2597 rxs = &sc->sc_rxsoft[i]; 2598 if (rxs->rxs_mbuf == NULL) { 2599 if ((error = sipcom_add_rxbuf(sc, i)) != 0) { 2600 printf("%s: unable to allocate or map rx " 2601 "buffer %d, error = %d\n", 2602 device_xname(sc->sc_dev), i, error); 2603 /* 2604 * XXX Should attempt to run with fewer receive 2605 * XXX buffers instead of just failing. 2606 */ 2607 sipcom_rxdrain(sc); 2608 goto out; 2609 } 2610 } else 2611 sip_init_rxdesc(sc, i); 2612 } 2613 sc->sc_rxptr = 0; 2614 sc->sc_rxdiscard = 0; 2615 sip_rxchain_reset(sc); 2616 2617 /* 2618 * Set the configuration register; it's already initialized 2619 * in sip_attach(). 2620 */ 2621 bus_space_write_4(st, sh, SIP_CFG, sc->sc_cfg); 2622 2623 /* 2624 * Initialize the prototype TXCFG register. 2625 */ 2626 if (sc->sc_gigabit) { 2627 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2628 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2629 } else if ((SIP_SIS900_REV(sc, SIS_REV_635) || 2630 SIP_SIS900_REV(sc, SIS_REV_960) || 2631 SIP_SIS900_REV(sc, SIS_REV_900B)) && 2632 (sc->sc_cfg & CFG_EDBMASTEN)) { 2633 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_64; 2634 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_64; 2635 } else { 2636 sc->sc_txcfg = sc->sc_bits.b_txcfg_mxdma_512; 2637 sc->sc_rxcfg = sc->sc_bits.b_rxcfg_mxdma_512; 2638 } 2639 2640 sc->sc_txcfg |= TXCFG_ATP | 2641 __SHIFTIN(sc->sc_tx_fill_thresh, sc->sc_bits.b_txcfg_flth_mask) | 2642 sc->sc_tx_drain_thresh; 2643 bus_space_write_4(st, sh, sc->sc_regs.r_txcfg, sc->sc_txcfg); 2644 2645 /* 2646 * Initialize the receive drain threshold if we have never 2647 * done so. 2648 */ 2649 if (sc->sc_rx_drain_thresh == 0) { 2650 /* 2651 * XXX This value should be tuned. This is set to the 2652 * maximum of 248 bytes, and we may be able to improve 2653 * performance by decreasing it (although we should never 2654 * set this value lower than 2; 14 bytes are required to 2655 * filter the packet). 2656 */ 2657 sc->sc_rx_drain_thresh = __SHIFTOUT_MASK(RXCFG_DRTH_MASK); 2658 } 2659 2660 /* 2661 * Initialize the prototype RXCFG register. 2662 */ 2663 sc->sc_rxcfg |= __SHIFTIN(sc->sc_rx_drain_thresh, RXCFG_DRTH_MASK); 2664 /* 2665 * Accept long packets (including FCS) so we can handle 2666 * 802.1q-tagged frames and jumbo frames properly. 2667 */ 2668 if ((sc->sc_gigabit && ifp->if_mtu > ETHERMTU) || 2669 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 2670 sc->sc_rxcfg |= RXCFG_ALP; 2671 2672 /* 2673 * Checksum offloading is disabled if the user selects an MTU 2674 * larger than 8109. (FreeBSD says 8152, but there is emperical 2675 * evidence that >8109 does not work on some boards, such as the 2676 * Planex GN-1000TE). 2677 */ 2678 if (sc->sc_gigabit && ifp->if_mtu > 8109 && 2679 (ifp->if_capenable & 2680 (IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2681 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2682 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx))) { 2683 printf("%s: Checksum offloading does not work if MTU > 8109 - " 2684 "disabled.\n", device_xname(sc->sc_dev)); 2685 ifp->if_capenable &= 2686 ~(IFCAP_CSUM_IPv4_Tx|IFCAP_CSUM_IPv4_Rx| 2687 IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_TCPv4_Rx| 2688 IFCAP_CSUM_UDPv4_Tx|IFCAP_CSUM_UDPv4_Rx); 2689 ifp->if_csum_flags_tx = 0; 2690 ifp->if_csum_flags_rx = 0; 2691 } 2692 2693 bus_space_write_4(st, sh, sc->sc_regs.r_rxcfg, sc->sc_rxcfg); 2694 2695 if (sc->sc_gigabit) 2696 sipcom_dp83820_init(sc, ifp->if_capenable); 2697 2698 /* 2699 * Give the transmit and receive rings to the chip. 2700 */ 2701 bus_space_write_4(st, sh, SIP_TXDP, SIP_CDTXADDR(sc, sc->sc_txnext)); 2702 bus_space_write_4(st, sh, SIP_RXDP, SIP_CDRXADDR(sc, sc->sc_rxptr)); 2703 2704 /* 2705 * Initialize the interrupt mask. 2706 */ 2707 sc->sc_imr = sc->sc_bits.b_isr_dperr | 2708 sc->sc_bits.b_isr_sserr | 2709 sc->sc_bits.b_isr_rmabt | 2710 sc->sc_bits.b_isr_rtabt | ISR_RXSOVR | 2711 ISR_TXURN|ISR_TXDESC|ISR_TXIDLE|ISR_RXORN|ISR_RXIDLE|ISR_RXDESC; 2712 bus_space_write_4(st, sh, SIP_IMR, sc->sc_imr); 2713 2714 /* Set up the receive filter. */ 2715 (*sc->sc_model->sip_variant->sipv_set_filter)(sc); 2716 2717 /* 2718 * Tune sc_rx_flow_thresh. 2719 * XXX "More than 8KB" is too short for jumbo frames. 2720 * XXX TODO: Threshold value should be user-settable. 2721 */ 2722 sc->sc_rx_flow_thresh = (PCR_PS_STHI_8 | PCR_PS_STLO_4 | 2723 PCR_PS_FFHI_8 | PCR_PS_FFLO_4 | 2724 (PCR_PAUSE_CNT & PCR_PAUSE_CNT_MASK)); 2725 2726 /* 2727 * Set the current media. Do this after initializing the prototype 2728 * IMR, since sip_mii_statchg() modifies the IMR for 802.3x flow 2729 * control. 2730 */ 2731 if ((error = ether_mediachange(ifp)) != 0) 2732 goto out; 2733 2734 /* 2735 * Set the interrupt hold-off timer to 100us. 2736 */ 2737 if (sc->sc_gigabit) 2738 bus_space_write_4(st, sh, SIP_IHR, 0x01); 2739 2740 /* 2741 * Enable interrupts. 2742 */ 2743 bus_space_write_4(st, sh, SIP_IER, IER_IE); 2744 2745 /* 2746 * Start the transmit and receive processes. 2747 */ 2748 bus_space_write_4(st, sh, SIP_CR, CR_RXE | CR_TXE); 2749 2750 /* 2751 * Start the one second MII clock. 2752 */ 2753 callout_reset(&sc->sc_tick_ch, hz, sipcom_tick, sc); 2754 2755 /* 2756 * ...all done! 2757 */ 2758 ifp->if_flags |= IFF_RUNNING; 2759 ifp->if_flags &= ~IFF_OACTIVE; 2760 sc->sc_if_flags = ifp->if_flags; 2761 sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable; 2762 sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom); 2763 sc->sc_prev.if_capenable = ifp->if_capenable; 2764 2765 out: 2766 if (error) 2767 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 2768 return error; 2769 } 2770 2771 /* 2772 * sip_drain: 2773 * 2774 * Drain the receive queue. 2775 */ 2776 static void 2777 sipcom_rxdrain(struct sip_softc *sc) 2778 { 2779 struct sip_rxsoft *rxs; 2780 int i; 2781 2782 for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) { 2783 rxs = &sc->sc_rxsoft[i]; 2784 if (rxs->rxs_mbuf != NULL) { 2785 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2786 m_freem(rxs->rxs_mbuf); 2787 rxs->rxs_mbuf = NULL; 2788 } 2789 } 2790 } 2791 2792 /* 2793 * sip_stop: [ ifnet interface function ] 2794 * 2795 * Stop transmission on the interface. 2796 */ 2797 static void 2798 sipcom_stop(struct ifnet *ifp, int disable) 2799 { 2800 struct sip_softc *sc = ifp->if_softc; 2801 bus_space_tag_t st = sc->sc_st; 2802 bus_space_handle_t sh = sc->sc_sh; 2803 struct sip_txsoft *txs; 2804 uint32_t cmdsts = 0; /* DEBUG */ 2805 2806 /* 2807 * Stop the one second clock. 2808 */ 2809 callout_stop(&sc->sc_tick_ch); 2810 2811 /* Down the MII. */ 2812 mii_down(&sc->sc_mii); 2813 2814 if (device_is_active(sc->sc_dev)) { 2815 /* 2816 * Disable interrupts. 2817 */ 2818 bus_space_write_4(st, sh, SIP_IER, 0); 2819 2820 /* 2821 * Stop receiver and transmitter. 2822 */ 2823 bus_space_write_4(st, sh, SIP_CR, CR_RXD | CR_TXD); 2824 } 2825 2826 /* 2827 * Release any queued transmit buffers. 2828 */ 2829 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2830 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2831 SIMPLEQ_NEXT(txs, txs_q) == NULL && 2832 (le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])) & 2833 CMDSTS_INTR) == 0) 2834 printf("%s: sip_stop: last descriptor does not " 2835 "have INTR bit set\n", device_xname(sc->sc_dev)); 2836 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2837 #ifdef DIAGNOSTIC 2838 if (txs->txs_mbuf == NULL) { 2839 printf("%s: dirty txsoft with no mbuf chain\n", 2840 device_xname(sc->sc_dev)); 2841 panic("sip_stop"); 2842 } 2843 #endif 2844 cmdsts |= /* DEBUG */ 2845 le32toh(*sipd_cmdsts(sc, &sc->sc_txdescs[txs->txs_lastdesc])); 2846 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2847 m_freem(txs->txs_mbuf); 2848 txs->txs_mbuf = NULL; 2849 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2850 } 2851 2852 /* 2853 * Mark the interface down and cancel the watchdog timer. 2854 */ 2855 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2856 ifp->if_timer = 0; 2857 2858 if (disable) 2859 pmf_device_recursive_suspend(sc->sc_dev, &sc->sc_qual); 2860 2861 if ((ifp->if_flags & IFF_DEBUG) != 0 && 2862 (cmdsts & CMDSTS_INTR) == 0 && sc->sc_txfree != sc->sc_ntxdesc) 2863 printf("%s: sip_stop: no INTR bits set in dirty tx " 2864 "descriptors\n", device_xname(sc->sc_dev)); 2865 } 2866 2867 /* 2868 * sip_read_eeprom: 2869 * 2870 * Read data from the serial EEPROM. 2871 */ 2872 static void 2873 sipcom_read_eeprom(struct sip_softc *sc, int word, int wordcnt, 2874 uint16_t *data) 2875 { 2876 bus_space_tag_t st = sc->sc_st; 2877 bus_space_handle_t sh = sc->sc_sh; 2878 uint16_t reg; 2879 int i, x; 2880 2881 for (i = 0; i < wordcnt; i++) { 2882 /* Send CHIP SELECT. */ 2883 reg = EROMAR_EECS; 2884 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2885 2886 /* Shift in the READ opcode. */ 2887 for (x = 3; x > 0; x--) { 2888 if (SIP_EEPROM_OPC_READ & (1 << (x - 1))) 2889 reg |= EROMAR_EEDI; 2890 else 2891 reg &= ~EROMAR_EEDI; 2892 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2893 bus_space_write_4(st, sh, SIP_EROMAR, 2894 reg | EROMAR_EESK); 2895 delay(4); 2896 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2897 delay(4); 2898 } 2899 2900 /* Shift in address. */ 2901 for (x = 6; x > 0; x--) { 2902 if ((word + i) & (1 << (x - 1))) 2903 reg |= EROMAR_EEDI; 2904 else 2905 reg &= ~EROMAR_EEDI; 2906 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2907 bus_space_write_4(st, sh, SIP_EROMAR, 2908 reg | EROMAR_EESK); 2909 delay(4); 2910 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2911 delay(4); 2912 } 2913 2914 /* Shift out data. */ 2915 reg = EROMAR_EECS; 2916 data[i] = 0; 2917 for (x = 16; x > 0; x--) { 2918 bus_space_write_4(st, sh, SIP_EROMAR, 2919 reg | EROMAR_EESK); 2920 delay(4); 2921 if (bus_space_read_4(st, sh, SIP_EROMAR) & EROMAR_EEDO) 2922 data[i] |= (1 << (x - 1)); 2923 bus_space_write_4(st, sh, SIP_EROMAR, reg); 2924 delay(4); 2925 } 2926 2927 /* Clear CHIP SELECT. */ 2928 bus_space_write_4(st, sh, SIP_EROMAR, 0); 2929 delay(4); 2930 } 2931 } 2932 2933 /* 2934 * sipcom_add_rxbuf: 2935 * 2936 * Add a receive buffer to the indicated descriptor. 2937 */ 2938 static int 2939 sipcom_add_rxbuf(struct sip_softc *sc, int idx) 2940 { 2941 struct sip_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2942 struct mbuf *m; 2943 int error; 2944 2945 MGETHDR(m, M_DONTWAIT, MT_DATA); 2946 if (m == NULL) 2947 return ENOBUFS; 2948 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2949 2950 MCLGET(m, M_DONTWAIT); 2951 if ((m->m_flags & M_EXT) == 0) { 2952 m_freem(m); 2953 return ENOBUFS; 2954 } 2955 2956 /* XXX I don't believe this is necessary. --dyoung */ 2957 if (sc->sc_gigabit) 2958 m->m_len = sc->sc_parm->p_rxbuf_len; 2959 2960 if (rxs->rxs_mbuf != NULL) 2961 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2962 2963 rxs->rxs_mbuf = m; 2964 2965 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2966 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2967 BUS_DMA_READ|BUS_DMA_NOWAIT); 2968 if (error) { 2969 printf("%s: can't load rx DMA map %d, error = %d\n", 2970 device_xname(sc->sc_dev), idx, error); 2971 panic("%s", __func__); /* XXX */ 2972 } 2973 2974 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2975 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2976 2977 sip_init_rxdesc(sc, idx); 2978 2979 return 0; 2980 } 2981 2982 /* 2983 * sip_sis900_set_filter: 2984 * 2985 * Set up the receive filter. 2986 */ 2987 static void 2988 sipcom_sis900_set_filter(struct sip_softc *sc) 2989 { 2990 bus_space_tag_t st = sc->sc_st; 2991 bus_space_handle_t sh = sc->sc_sh; 2992 struct ethercom *ec = &sc->sc_ethercom; 2993 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2994 struct ether_multi *enm; 2995 const uint8_t *cp; 2996 struct ether_multistep step; 2997 uint32_t crc, mchash[16]; 2998 2999 /* 3000 * Initialize the prototype RFCR. 3001 */ 3002 sc->sc_rfcr = RFCR_RFEN; 3003 if (ifp->if_flags & IFF_BROADCAST) 3004 sc->sc_rfcr |= RFCR_AAB; 3005 if (ifp->if_flags & IFF_PROMISC) { 3006 sc->sc_rfcr |= RFCR_AAP; 3007 goto allmulti; 3008 } 3009 3010 /* 3011 * Set up the multicast address filter by passing all multicast 3012 * addresses through a CRC generator, and then using the high-order 3013 * 6 bits as an index into the 128 bit multicast hash table (only 3014 * the lower 16 bits of each 32 bit multicast hash register are 3015 * valid). The high order bits select the register, while the 3016 * rest of the bits select the bit within the register. 3017 */ 3018 3019 memset(mchash, 0, sizeof(mchash)); 3020 3021 /* 3022 * SiS900 (at least SiS963) requires us to register the address of 3023 * the PAUSE packet (01:80:c2:00:00:01) into the address filter. 3024 */ 3025 crc = 0x0ed423f9; 3026 3027 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3028 SIP_SIS900_REV(sc, SIS_REV_960) || 3029 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3030 /* Just want the 8 most significant bits. */ 3031 crc >>= 24; 3032 } else { 3033 /* Just want the 7 most significant bits. */ 3034 crc >>= 25; 3035 } 3036 3037 /* Set the corresponding bit in the hash table. */ 3038 mchash[crc >> 4] |= 1 << (crc & 0xf); 3039 3040 ETHER_FIRST_MULTI(step, ec, enm); 3041 while (enm != NULL) { 3042 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3043 /* 3044 * We must listen to a range of multicast addresses. 3045 * For now, just accept all multicasts, rather than 3046 * trying to set only those filter bits needed to match 3047 * the range. (At this time, the only use of address 3048 * ranges is for IP multicast routing, for which the 3049 * range is big enough to require all bits set.) 3050 */ 3051 goto allmulti; 3052 } 3053 3054 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3055 3056 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3057 SIP_SIS900_REV(sc, SIS_REV_960) || 3058 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3059 /* Just want the 8 most significant bits. */ 3060 crc >>= 24; 3061 } else { 3062 /* Just want the 7 most significant bits. */ 3063 crc >>= 25; 3064 } 3065 3066 /* Set the corresponding bit in the hash table. */ 3067 mchash[crc >> 4] |= 1 << (crc & 0xf); 3068 3069 ETHER_NEXT_MULTI(step, enm); 3070 } 3071 3072 ifp->if_flags &= ~IFF_ALLMULTI; 3073 goto setit; 3074 3075 allmulti: 3076 ifp->if_flags |= IFF_ALLMULTI; 3077 sc->sc_rfcr |= RFCR_AAM; 3078 3079 setit: 3080 #define FILTER_EMIT(addr, data) \ 3081 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3082 delay(1); \ 3083 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3084 delay(1) 3085 3086 /* 3087 * Disable receive filter, and program the node address. 3088 */ 3089 cp = CLLADDR(ifp->if_sadl); 3090 FILTER_EMIT(RFCR_RFADDR_NODE0, (cp[1] << 8) | cp[0]); 3091 FILTER_EMIT(RFCR_RFADDR_NODE2, (cp[3] << 8) | cp[2]); 3092 FILTER_EMIT(RFCR_RFADDR_NODE4, (cp[5] << 8) | cp[4]); 3093 3094 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3095 /* 3096 * Program the multicast hash table. 3097 */ 3098 FILTER_EMIT(RFCR_RFADDR_MC0, mchash[0]); 3099 FILTER_EMIT(RFCR_RFADDR_MC1, mchash[1]); 3100 FILTER_EMIT(RFCR_RFADDR_MC2, mchash[2]); 3101 FILTER_EMIT(RFCR_RFADDR_MC3, mchash[3]); 3102 FILTER_EMIT(RFCR_RFADDR_MC4, mchash[4]); 3103 FILTER_EMIT(RFCR_RFADDR_MC5, mchash[5]); 3104 FILTER_EMIT(RFCR_RFADDR_MC6, mchash[6]); 3105 FILTER_EMIT(RFCR_RFADDR_MC7, mchash[7]); 3106 if (SIP_SIS900_REV(sc, SIS_REV_635) || 3107 SIP_SIS900_REV(sc, SIS_REV_960) || 3108 SIP_SIS900_REV(sc, SIS_REV_900B)) { 3109 FILTER_EMIT(RFCR_RFADDR_MC8, mchash[8]); 3110 FILTER_EMIT(RFCR_RFADDR_MC9, mchash[9]); 3111 FILTER_EMIT(RFCR_RFADDR_MC10, mchash[10]); 3112 FILTER_EMIT(RFCR_RFADDR_MC11, mchash[11]); 3113 FILTER_EMIT(RFCR_RFADDR_MC12, mchash[12]); 3114 FILTER_EMIT(RFCR_RFADDR_MC13, mchash[13]); 3115 FILTER_EMIT(RFCR_RFADDR_MC14, mchash[14]); 3116 FILTER_EMIT(RFCR_RFADDR_MC15, mchash[15]); 3117 } 3118 } 3119 #undef FILTER_EMIT 3120 3121 /* 3122 * Re-enable the receiver filter. 3123 */ 3124 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3125 } 3126 3127 /* 3128 * sip_dp83815_set_filter: 3129 * 3130 * Set up the receive filter. 3131 */ 3132 static void 3133 sipcom_dp83815_set_filter(struct sip_softc *sc) 3134 { 3135 bus_space_tag_t st = sc->sc_st; 3136 bus_space_handle_t sh = sc->sc_sh; 3137 struct ethercom *ec = &sc->sc_ethercom; 3138 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 3139 struct ether_multi *enm; 3140 const uint8_t *cp; 3141 struct ether_multistep step; 3142 uint32_t crc, hash, slot, bit; 3143 #define MCHASH_NWORDS_83820 128 3144 #define MCHASH_NWORDS_83815 32 3145 #define MCHASH_NWORDS MAX(MCHASH_NWORDS_83820, MCHASH_NWORDS_83815) 3146 uint16_t mchash[MCHASH_NWORDS]; 3147 int i; 3148 3149 /* 3150 * Initialize the prototype RFCR. 3151 * Enable the receive filter, and accept on 3152 * Perfect (destination address) Match 3153 * If IFF_BROADCAST, also accept all broadcast packets. 3154 * If IFF_PROMISC, accept all unicast packets (and later, set 3155 * IFF_ALLMULTI and accept all multicast, too). 3156 */ 3157 sc->sc_rfcr = RFCR_RFEN | RFCR_APM; 3158 if (ifp->if_flags & IFF_BROADCAST) 3159 sc->sc_rfcr |= RFCR_AAB; 3160 if (ifp->if_flags & IFF_PROMISC) { 3161 sc->sc_rfcr |= RFCR_AAP; 3162 goto allmulti; 3163 } 3164 3165 /* 3166 * Set up the DP83820/DP83815 multicast address filter by 3167 * passing all multicast addresses through a CRC generator, 3168 * and then using the high-order 11/9 bits as an index into 3169 * the 2048/512 bit multicast hash table. The high-order 3170 * 7/5 bits select the slot, while the low-order 4 bits 3171 * select the bit within the slot. Note that only the low 3172 * 16-bits of each filter word are used, and there are 3173 * 128/32 filter words. 3174 */ 3175 3176 memset(mchash, 0, sizeof(mchash)); 3177 3178 ifp->if_flags &= ~IFF_ALLMULTI; 3179 ETHER_FIRST_MULTI(step, ec, enm); 3180 if (enm == NULL) 3181 goto setit; 3182 while (enm != NULL) { 3183 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 3184 /* 3185 * We must listen to a range of multicast addresses. 3186 * For now, just accept all multicasts, rather than 3187 * trying to set only those filter bits needed to match 3188 * the range. (At this time, the only use of address 3189 * ranges is for IP multicast routing, for which the 3190 * range is big enough to require all bits set.) 3191 */ 3192 goto allmulti; 3193 } 3194 3195 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 3196 3197 if (sc->sc_gigabit) { 3198 /* Just want the 11 most significant bits. */ 3199 hash = crc >> 21; 3200 } else { 3201 /* Just want the 9 most significant bits. */ 3202 hash = crc >> 23; 3203 } 3204 3205 slot = hash >> 4; 3206 bit = hash & 0xf; 3207 3208 /* Set the corresponding bit in the hash table. */ 3209 mchash[slot] |= 1 << bit; 3210 3211 ETHER_NEXT_MULTI(step, enm); 3212 } 3213 sc->sc_rfcr |= RFCR_MHEN; 3214 goto setit; 3215 3216 allmulti: 3217 ifp->if_flags |= IFF_ALLMULTI; 3218 sc->sc_rfcr |= RFCR_AAM; 3219 3220 setit: 3221 #define FILTER_EMIT(addr, data) \ 3222 bus_space_write_4(st, sh, SIP_RFCR, (addr)); \ 3223 delay(1); \ 3224 bus_space_write_4(st, sh, SIP_RFDR, (data)); \ 3225 delay(1) 3226 3227 /* 3228 * Disable receive filter, and program the node address. 3229 */ 3230 cp = CLLADDR(ifp->if_sadl); 3231 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH0, (cp[1] << 8) | cp[0]); 3232 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH2, (cp[3] << 8) | cp[2]); 3233 FILTER_EMIT(RFCR_NS_RFADDR_PMATCH4, (cp[5] << 8) | cp[4]); 3234 3235 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 3236 int nwords = 3237 sc->sc_gigabit ? MCHASH_NWORDS_83820 : MCHASH_NWORDS_83815; 3238 /* 3239 * Program the multicast hash table. 3240 */ 3241 for (i = 0; i < nwords; i++) { 3242 FILTER_EMIT(sc->sc_parm->p_filtmem + (i * 2), mchash[i]); 3243 } 3244 } 3245 #undef FILTER_EMIT 3246 #undef MCHASH_NWORDS 3247 #undef MCHASH_NWORDS_83815 3248 #undef MCHASH_NWORDS_83820 3249 3250 /* 3251 * Re-enable the receiver filter. 3252 */ 3253 bus_space_write_4(st, sh, SIP_RFCR, sc->sc_rfcr); 3254 } 3255 3256 /* 3257 * sip_dp83820_mii_readreg: [mii interface function] 3258 * 3259 * Read a PHY register on the MII of the DP83820. 3260 */ 3261 static int 3262 sipcom_dp83820_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3263 { 3264 struct sip_softc *sc = device_private(self); 3265 3266 if (sc->sc_cfg & CFG_TBI_EN) { 3267 bus_addr_t tbireg; 3268 3269 if (phy != 0) 3270 return -1; 3271 3272 switch (reg) { 3273 case MII_BMCR: tbireg = SIP_TBICR; break; 3274 case MII_BMSR: tbireg = SIP_TBISR; break; 3275 case MII_ANAR: tbireg = SIP_TANAR; break; 3276 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3277 case MII_ANER: tbireg = SIP_TANER; break; 3278 case MII_EXTSR: 3279 /* 3280 * Don't even bother reading the TESR register. 3281 * The manual documents that the device has 3282 * 1000baseX full/half capability, but the 3283 * register itself seems read back 0 on some 3284 * boards. Just hard-code the result. 3285 */ 3286 *val = (EXTSR_1000XFDX | EXTSR_1000XHDX); 3287 return 0; 3288 3289 default: 3290 return 0; 3291 } 3292 3293 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffff; 3294 if (tbireg == SIP_TBISR) { 3295 /* LINK and ACOMP are switched! */ 3296 int sr = *val; 3297 3298 *val = 0; 3299 if (sr & TBISR_MR_LINK_STATUS) 3300 *val |= BMSR_LINK; 3301 if (sr & TBISR_MR_AN_COMPLETE) 3302 *val |= BMSR_ACOMP; 3303 3304 /* 3305 * The manual claims this register reads back 0 3306 * on hard and soft reset. But we want to let 3307 * the gentbi driver know that we support auto- 3308 * negotiation, so hard-code this bit in the 3309 * result. 3310 */ 3311 *val |= BMSR_ANEG | BMSR_EXTSTAT; 3312 } 3313 3314 return 0; 3315 } 3316 3317 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, phy, reg, 3318 val); 3319 } 3320 3321 /* 3322 * sip_dp83820_mii_writereg: [mii interface function] 3323 * 3324 * Write a PHY register on the MII of the DP83820. 3325 */ 3326 static int 3327 sipcom_dp83820_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3328 { 3329 struct sip_softc *sc = device_private(self); 3330 3331 if (sc->sc_cfg & CFG_TBI_EN) { 3332 bus_addr_t tbireg; 3333 3334 if (phy != 0) 3335 return -1; 3336 3337 switch (reg) { 3338 case MII_BMCR: tbireg = SIP_TBICR; break; 3339 case MII_ANAR: tbireg = SIP_TANAR; break; 3340 case MII_ANLPAR: tbireg = SIP_TANLPAR; break; 3341 default: 3342 return 0; 3343 } 3344 3345 bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val); 3346 return 0; 3347 } 3348 3349 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, phy, reg, 3350 val); 3351 } 3352 3353 /* 3354 * sip_dp83820_mii_statchg: [mii interface function] 3355 * 3356 * Callback from MII layer when media changes. 3357 */ 3358 static void 3359 sipcom_dp83820_mii_statchg(struct ifnet *ifp) 3360 { 3361 struct sip_softc *sc = ifp->if_softc; 3362 struct mii_data *mii = &sc->sc_mii; 3363 uint32_t cfg, pcr; 3364 3365 /* 3366 * Get flow control negotiation result. 3367 */ 3368 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3369 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3370 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3371 mii->mii_media_active &= ~IFM_ETH_FMASK; 3372 } 3373 3374 /* 3375 * Update TXCFG for full-duplex operation. 3376 */ 3377 if ((mii->mii_media_active & IFM_FDX) != 0) 3378 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3379 else 3380 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3381 3382 /* 3383 * Update RXCFG for full-duplex or loopback. 3384 */ 3385 if ((mii->mii_media_active & IFM_FDX) != 0 || 3386 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3387 sc->sc_rxcfg |= RXCFG_ATX; 3388 else 3389 sc->sc_rxcfg &= ~RXCFG_ATX; 3390 3391 /* 3392 * Update CFG for MII/GMII. 3393 */ 3394 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 3395 cfg = sc->sc_cfg | CFG_MODE_1000; 3396 else 3397 cfg = sc->sc_cfg; 3398 3399 /* 3400 * 802.3x flow control. 3401 */ 3402 pcr = 0; 3403 if (sc->sc_flowflags & IFM_FLOW) { 3404 if (sc->sc_flowflags & IFM_ETH_TXPAUSE) 3405 pcr |= sc->sc_rx_flow_thresh; 3406 if (sc->sc_flowflags & IFM_ETH_RXPAUSE) 3407 pcr |= PCR_PSEN | PCR_PS_MCAST; 3408 } 3409 3410 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CFG, cfg); 3411 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3412 sc->sc_txcfg); 3413 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3414 sc->sc_rxcfg); 3415 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PCR, pcr); 3416 } 3417 3418 /* 3419 * sip_mii_bitbang_read: [mii bit-bang interface function] 3420 * 3421 * Read the MII serial port for the MII bit-bang module. 3422 */ 3423 static uint32_t 3424 sipcom_mii_bitbang_read(device_t self) 3425 { 3426 struct sip_softc *sc = device_private(self); 3427 3428 return (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_EROMAR)); 3429 } 3430 3431 /* 3432 * sip_mii_bitbang_write: [mii big-bang interface function] 3433 * 3434 * Write the MII serial port for the MII bit-bang module. 3435 */ 3436 static void 3437 sipcom_mii_bitbang_write(device_t self, uint32_t val) 3438 { 3439 struct sip_softc *sc = device_private(self); 3440 3441 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_EROMAR, val); 3442 } 3443 3444 /* 3445 * sip_sis900_mii_readreg: [mii interface function] 3446 * 3447 * Read a PHY register on the MII. 3448 */ 3449 static int 3450 sipcom_sis900_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3451 { 3452 struct sip_softc *sc = device_private(self); 3453 uint32_t enphy; 3454 3455 /* 3456 * The PHY of recent SiS chipsets is accessed through bitbang 3457 * operations. 3458 */ 3459 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) 3460 return mii_bitbang_readreg(self, &sipcom_mii_bitbang_ops, 3461 phy, reg, val); 3462 3463 #ifndef SIS900_MII_RESTRICT 3464 /* 3465 * The SiS 900 has only an internal PHY on the MII. Only allow 3466 * MII address 0. 3467 */ 3468 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3469 return -1; 3470 #endif 3471 3472 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3473 (phy << ENPHY_PHYADDR_SHIFT) | (reg << ENPHY_REGADDR_SHIFT) | 3474 ENPHY_RWCMD | ENPHY_ACCESS); 3475 do { 3476 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3477 } while (enphy & ENPHY_ACCESS); 3478 3479 *val = (enphy & ENPHY_PHYDATA) >> ENPHY_DATA_SHIFT; 3480 return 0; 3481 } 3482 3483 /* 3484 * sip_sis900_mii_writereg: [mii interface function] 3485 * 3486 * Write a PHY register on the MII. 3487 */ 3488 static int 3489 sipcom_sis900_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3490 { 3491 struct sip_softc *sc = device_private(self); 3492 uint32_t enphy; 3493 3494 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900) { 3495 return mii_bitbang_writereg(self, &sipcom_mii_bitbang_ops, 3496 phy, reg, val); 3497 } 3498 3499 #ifndef SIS900_MII_RESTRICT 3500 /* 3501 * The SiS 900 has only an internal PHY on the MII. Only allow 3502 * MII address 0. 3503 */ 3504 if (sc->sc_model->sip_product == PCI_PRODUCT_SIS_900 && phy != 0) 3505 return -1; 3506 #endif 3507 3508 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_ENPHY, 3509 (val << ENPHY_DATA_SHIFT) | (phy << ENPHY_PHYADDR_SHIFT) | 3510 (reg << ENPHY_REGADDR_SHIFT) | ENPHY_ACCESS); 3511 do { 3512 enphy = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_ENPHY); 3513 } while (enphy & ENPHY_ACCESS); 3514 3515 return 0; 3516 } 3517 3518 /* 3519 * sip_sis900_mii_statchg: [mii interface function] 3520 * 3521 * Callback from MII layer when media changes. 3522 */ 3523 static void 3524 sipcom_sis900_mii_statchg(struct ifnet *ifp) 3525 { 3526 struct sip_softc *sc = ifp->if_softc; 3527 struct mii_data *mii = &sc->sc_mii; 3528 uint32_t flowctl; 3529 3530 /* 3531 * Get flow control negotiation result. 3532 */ 3533 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 3534 (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) { 3535 sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 3536 mii->mii_media_active &= ~IFM_ETH_FMASK; 3537 } 3538 3539 /* 3540 * Update TXCFG for full-duplex operation. 3541 */ 3542 if ((mii->mii_media_active & IFM_FDX) != 0) 3543 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3544 else 3545 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3546 3547 /* 3548 * Update RXCFG for full-duplex or loopback. 3549 */ 3550 if ((mii->mii_media_active & IFM_FDX) != 0 || 3551 IFM_SUBTYPE(mii->mii_media_active) == IFM_LOOP) 3552 sc->sc_rxcfg |= RXCFG_ATX; 3553 else 3554 sc->sc_rxcfg &= ~RXCFG_ATX; 3555 3556 /* 3557 * Update IMR for use of 802.3x flow control. 3558 */ 3559 if (sc->sc_flowflags & IFM_FLOW) { 3560 sc->sc_imr |= (ISR_PAUSE_END|ISR_PAUSE_ST); 3561 flowctl = FLOWCTL_FLOWEN; 3562 } else { 3563 sc->sc_imr &= ~(ISR_PAUSE_END|ISR_PAUSE_ST); 3564 flowctl = 0; 3565 } 3566 3567 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3568 sc->sc_txcfg); 3569 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3570 sc->sc_rxcfg); 3571 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_IMR, sc->sc_imr); 3572 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_FLOWCTL, flowctl); 3573 } 3574 3575 /* 3576 * sip_dp83815_mii_readreg: [mii interface function] 3577 * 3578 * Read a PHY register on the MII. 3579 */ 3580 static int 3581 sipcom_dp83815_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 3582 { 3583 struct sip_softc *sc = device_private(self); 3584 uint32_t data; 3585 3586 /* 3587 * The DP83815 only has an internal PHY. Only allow 3588 * MII address 0. 3589 */ 3590 if (phy != 0) 3591 return -1; 3592 3593 /* 3594 * Apparently, after a reset, the DP83815 can take a while 3595 * to respond. During this recovery period, the BMSR returns 3596 * a value of 0. Catch this -- it's not supposed to happen 3597 * (the BMSR has some hardcoded-to-1 bits), and wait for the 3598 * PHY to come back to life. 3599 * 3600 * This works out because the BMSR is the first register 3601 * read during the PHY probe process. 3602 */ 3603 do { 3604 data = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg)); 3605 } while (reg == MII_BMSR && data == 0); 3606 3607 *val = data & 0xffff; 3608 return 0; 3609 } 3610 3611 /* 3612 * sip_dp83815_mii_writereg: [mii interface function] 3613 * 3614 * Write a PHY register to the MII. 3615 */ 3616 static int 3617 sipcom_dp83815_mii_writereg(device_t self, int phy, int reg, uint16_t val) 3618 { 3619 struct sip_softc *sc = device_private(self); 3620 3621 /* 3622 * The DP83815 only has an internal PHY. Only allow 3623 * MII address 0. 3624 */ 3625 if (phy != 0) 3626 return -1; 3627 3628 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_NS_PHY(reg), val); 3629 3630 return 0; 3631 } 3632 3633 /* 3634 * sip_dp83815_mii_statchg: [mii interface function] 3635 * 3636 * Callback from MII layer when media changes. 3637 */ 3638 static void 3639 sipcom_dp83815_mii_statchg(struct ifnet *ifp) 3640 { 3641 struct sip_softc *sc = ifp->if_softc; 3642 3643 /* 3644 * Update TXCFG for full-duplex operation. 3645 */ 3646 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 3647 sc->sc_txcfg |= (TXCFG_CSI | TXCFG_HBI); 3648 else 3649 sc->sc_txcfg &= ~(TXCFG_CSI | TXCFG_HBI); 3650 3651 /* 3652 * Update RXCFG for full-duplex or loopback. 3653 */ 3654 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0 || 3655 IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_LOOP) 3656 sc->sc_rxcfg |= RXCFG_ATX; 3657 else 3658 sc->sc_rxcfg &= ~RXCFG_ATX; 3659 3660 /* 3661 * XXX 802.3x flow control. 3662 */ 3663 3664 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_txcfg, 3665 sc->sc_txcfg); 3666 bus_space_write_4(sc->sc_st, sc->sc_sh, sc->sc_regs.r_rxcfg, 3667 sc->sc_rxcfg); 3668 3669 /* 3670 * Some DP83815s experience problems when used with short 3671 * (< 30m/100ft) Ethernet cables in 100BaseTX mode. This 3672 * sequence adjusts the DSP's signal attenuation to fix the 3673 * problem. 3674 */ 3675 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 3676 uint32_t reg; 3677 3678 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0x0001); 3679 3680 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3681 reg &= 0x0fff; 3682 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, reg | 0x1000); 3683 delay(100); 3684 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00fc); 3685 reg &= 0x00ff; 3686 if ((reg & 0x0080) == 0 || (reg >= 0x00d8)) { 3687 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00fc, 3688 0x00e8); 3689 reg = bus_space_read_4(sc->sc_st, sc->sc_sh, 0x00f4); 3690 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00f4, 3691 reg | 0x20); 3692 } 3693 3694 bus_space_write_4(sc->sc_st, sc->sc_sh, 0x00cc, 0); 3695 } 3696 } 3697 3698 static void 3699 sipcom_dp83820_read_macaddr(struct sip_softc *sc, 3700 const struct pci_attach_args *pa, uint8_t *enaddr) 3701 { 3702 uint16_t eeprom_data[SIP_DP83820_EEPROM_LENGTH / 2]; 3703 uint8_t cksum, *e, match; 3704 int i; 3705 3706 /* 3707 * EEPROM data format for the DP83820 can be found in 3708 * the DP83820 manual, section 4.2.4. 3709 */ 3710 3711 sipcom_read_eeprom(sc, 0, __arraycount(eeprom_data), eeprom_data); 3712 3713 match = eeprom_data[SIP_DP83820_EEPROM_CHECKSUM / 2] >> 8; 3714 match = ~(match - 1); 3715 3716 cksum = 0x55; 3717 e = (uint8_t *)eeprom_data; 3718 for (i = 0; i < SIP_DP83820_EEPROM_CHECKSUM; i++) 3719 cksum += *e++; 3720 3721 if (cksum != match) 3722 printf("%s: Checksum (%x) mismatch (%x)", 3723 device_xname(sc->sc_dev), cksum, match); 3724 3725 enaddr[0] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] & 0xff; 3726 enaddr[1] = eeprom_data[SIP_DP83820_EEPROM_PMATCH2 / 2] >> 8; 3727 enaddr[2] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] & 0xff; 3728 enaddr[3] = eeprom_data[SIP_DP83820_EEPROM_PMATCH1 / 2] >> 8; 3729 enaddr[4] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] & 0xff; 3730 enaddr[5] = eeprom_data[SIP_DP83820_EEPROM_PMATCH0 / 2] >> 8; 3731 } 3732 3733 static void 3734 sipcom_sis900_eeprom_delay(struct sip_softc *sc) 3735 { 3736 int i; 3737 3738 /* 3739 * FreeBSD goes from (300/33)+1 [10] to 0. There must be 3740 * a reason, but I don't know it. 3741 */ 3742 for (i = 0; i < 10; i++) 3743 bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR); 3744 } 3745 3746 static void 3747 sipcom_sis900_read_macaddr(struct sip_softc *sc, 3748 const struct pci_attach_args *pa, uint8_t *enaddr) 3749 { 3750 uint16_t myea[ETHER_ADDR_LEN / 2]; 3751 3752 switch (sc->sc_rev) { 3753 case SIS_REV_630S: 3754 case SIS_REV_630E: 3755 case SIS_REV_630EA1: 3756 case SIS_REV_630ET: 3757 case SIS_REV_635: 3758 /* 3759 * The MAC address for the on-board Ethernet of 3760 * the SiS 630 chipset is in the NVRAM. Kick 3761 * the chip into re-loading it from NVRAM, and 3762 * read the MAC address out of the filter registers. 3763 */ 3764 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_RLD); 3765 3766 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3767 RFCR_RFADDR_NODE0); 3768 myea[0] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3769 0xffff; 3770 3771 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3772 RFCR_RFADDR_NODE2); 3773 myea[1] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3774 0xffff; 3775 3776 bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_RFCR, 3777 RFCR_RFADDR_NODE4); 3778 myea[2] = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_RFDR) & 3779 0xffff; 3780 break; 3781 3782 case SIS_REV_960: 3783 { 3784 #define SIS_SET_EROMAR(x,y) \ 3785 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3786 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) | (y)) 3787 3788 #define SIS_CLR_EROMAR(x,y) \ 3789 bus_space_write_4(x->sc_st, x->sc_sh, SIP_EROMAR, \ 3790 bus_space_read_4(x->sc_st, x->sc_sh, SIP_EROMAR) & ~(y)) 3791 3792 int waittime, i; 3793 3794 /* Allow to read EEPROM from LAN. It is shared 3795 * between a 1394 controller and the NIC and each 3796 * time we access it, we need to set SIS_EECMD_REQ. 3797 */ 3798 SIS_SET_EROMAR(sc, EROMAR_REQ); 3799 3800 for (waittime = 0; waittime < 1000; waittime++) { /* 1 ms max */ 3801 /* Force EEPROM to idle state. */ 3802 3803 /* 3804 * XXX-cube This is ugly. 3805 * I'll look for docs about it. 3806 */ 3807 SIS_SET_EROMAR(sc, EROMAR_EECS); 3808 sipcom_sis900_eeprom_delay(sc); 3809 for (i = 0; i <= 25; i++) { /* Yes, 26 times. */ 3810 SIS_SET_EROMAR(sc, EROMAR_EESK); 3811 sipcom_sis900_eeprom_delay(sc); 3812 SIS_CLR_EROMAR(sc, EROMAR_EESK); 3813 sipcom_sis900_eeprom_delay(sc); 3814 } 3815 SIS_CLR_EROMAR(sc, EROMAR_EECS); 3816 sipcom_sis900_eeprom_delay(sc); 3817 bus_space_write_4(sc->sc_st, sc->sc_sh, 3818 SIP_EROMAR, 0); 3819 3820 if (bus_space_read_4(sc->sc_st, sc->sc_sh, 3821 SIP_EROMAR) & EROMAR_GNT) { 3822 sipcom_read_eeprom(sc, 3823 SIP_EEPROM_ETHERNET_ID0 >> 1, 3824 sizeof(myea) / sizeof(myea[0]), 3825 myea); 3826 break; 3827 } 3828 DELAY(1); 3829 } 3830 3831 /* 3832 * Set SIS_EECTL_CLK to high, so a other master 3833 * can operate on the i2c bus. 3834 */ 3835 SIS_SET_EROMAR(sc, EROMAR_EESK); 3836 3837 /* Refuse EEPROM access by LAN */ 3838 SIS_SET_EROMAR(sc, EROMAR_DONE); 3839 } break; 3840 3841 default: 3842 sipcom_read_eeprom(sc, SIP_EEPROM_ETHERNET_ID0 >> 1, 3843 sizeof(myea) / sizeof(myea[0]), myea); 3844 } 3845 3846 enaddr[0] = myea[0] & 0xff; 3847 enaddr[1] = myea[0] >> 8; 3848 enaddr[2] = myea[1] & 0xff; 3849 enaddr[3] = myea[1] >> 8; 3850 enaddr[4] = myea[2] & 0xff; 3851 enaddr[5] = myea[2] >> 8; 3852 } 3853 3854 /* Table and macro to bit-reverse an octet. */ 3855 static const uint8_t bbr4[] = {0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15}; 3856 #define bbr(v) ((bbr4[(v)&0xf] << 4) | bbr4[((v)>>4) & 0xf]) 3857 3858 static void 3859 sipcom_dp83815_read_macaddr(struct sip_softc *sc, 3860 const struct pci_attach_args *pa, uint8_t *enaddr) 3861 { 3862 uint16_t eeprom_data[SIP_DP83815_EEPROM_LENGTH / 2], *ea; 3863 uint8_t cksum, *e, match; 3864 int i; 3865 3866 sipcom_read_eeprom(sc, 0, sizeof(eeprom_data) / 3867 sizeof(eeprom_data[0]), eeprom_data); 3868 3869 match = eeprom_data[SIP_DP83815_EEPROM_CHECKSUM/2] >> 8; 3870 match = ~(match - 1); 3871 3872 cksum = 0x55; 3873 e = (uint8_t *)eeprom_data; 3874 for (i = 0; i < SIP_DP83815_EEPROM_CHECKSUM; i++) 3875 cksum += *e++; 3876 3877 if (cksum != match) 3878 printf("%s: Checksum (%x) mismatch (%x)", 3879 device_xname(sc->sc_dev), cksum, match); 3880 3881 /* 3882 * Unrolled because it makes slightly more sense this way. 3883 * The DP83815 stores the MAC address in bit 0 of word 6 3884 * through bit 15 of word 8. 3885 */ 3886 ea = &eeprom_data[6]; 3887 enaddr[0] = ((*ea & 0x1) << 7); 3888 ea++; 3889 enaddr[0] |= ((*ea & 0xFE00) >> 9); 3890 enaddr[1] = ((*ea & 0x1FE) >> 1); 3891 enaddr[2] = ((*ea & 0x1) << 7); 3892 ea++; 3893 enaddr[2] |= ((*ea & 0xFE00) >> 9); 3894 enaddr[3] = ((*ea & 0x1FE) >> 1); 3895 enaddr[4] = ((*ea & 0x1) << 7); 3896 ea++; 3897 enaddr[4] |= ((*ea & 0xFE00) >> 9); 3898 enaddr[5] = ((*ea & 0x1FE) >> 1); 3899 3900 /* 3901 * In case that's not weird enough, we also need to reverse 3902 * the bits in each byte. This all actually makes more sense 3903 * if you think about the EEPROM storage as an array of bits 3904 * being shifted into bytes, but that's not how we're looking 3905 * at it here... 3906 */ 3907 for (i = 0; i < 6 ;i++) 3908 enaddr[i] = bbr(enaddr[i]); 3909 } 3910 3911 /* 3912 * sip_mediastatus: [ifmedia interface function] 3913 * 3914 * Get the current interface media status. 3915 */ 3916 static void 3917 sipcom_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 3918 { 3919 struct sip_softc *sc = ifp->if_softc; 3920 3921 if (!device_is_active(sc->sc_dev)) { 3922 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 3923 ifmr->ifm_status = 0; 3924 return; 3925 } 3926 ether_mediastatus(ifp, ifmr); 3927 ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK) | 3928 sc->sc_flowflags; 3929 } 3930
Indexes created Tue Sep 30 11:09:46 GMT 2025